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drm/i915: Disable/enable planes as the first/last thing during modeset on HSW
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
75e53986 320 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
e0638cdf
PZ		 338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
1b894b59
CW		 353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
2c07245f 355{
b91ad0ec 356 struct drm_device *dev = crtc->dev;
2c07245f 357 const intel_limit_t *limit;
b91ad0ec
ZW		 358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 360 if (intel_is_dual_link_lvds(dev)) {
1b894b59 361 if (refclk == 100000)
b91ad0ec
ZW		 362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
1b894b59 366 if (refclk == 100000)
b91ad0ec
ZW		 367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
c6bb3538 371 } else
b91ad0ec 372 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 373
374 return limit;
375}
376
044c7c41
ML		 377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
044c7c41
ML		 380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 383 if (intel_is_dual_link_lvds(dev))
e4b36699 384 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 385 else
e4b36699 386 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 389 limit = &intel_limits_g4x_hdmi;
044c7c41 390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 391 limit = &intel_limits_g4x_sdvo;
044c7c41 392 } else /* The option is for other outputs */
e4b36699 393 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 394
395 return limit;
396}
397
1b894b59 398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
bad720ff 403 if (HAS_PCH_SPLIT(dev))
1b894b59 404 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 405 else if (IS_G4X(dev)) {
044c7c41 406 limit = intel_g4x_limit(crtc);
f2b115e6 407 } else if (IS_PINEVIEW(dev)) {
2177832f 408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 409 limit = &intel_limits_pineview_lvds;
2177832f 410 else
f2b115e6 411 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 412 } else if (IS_VALLEYVIEW(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
414 limit = &intel_limits_vlv_dac;
a0c4da24 415 else
65ce4bf5 416 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 424 limit = &intel_limits_i8xx_lvds;
5d536e28 425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 426 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 427 else
428 limit = &intel_limits_i8xx_dac;
79e53945
JB		 429 }
430 return limit;
431}
432
f2b115e6
AJ		 433/* m1 is reserved as 0 in Pineview, n is a ring counter */
434static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 435{
2177832f
SL		 436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 clock->vco = refclk * clock->m / clock->n;
439 clock->dot = clock->vco / clock->p;
440}
441
7429e9d4
DV		 442static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443{
444 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
445}
446
ac58c3f0 447static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 448{
7429e9d4 449 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 450 clock->p = clock->p1 * clock->p2;
451 clock->vco = refclk * clock->m / (clock->n + 2);
452 clock->dot = clock->vco / clock->p;
453}
454
7c04d1d9 455#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 456/**
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
459 */
460
1b894b59
CW		 461static bool intel_PLL_is_valid(struct drm_device *dev,
462 const intel_limit_t *limit,
463 const intel_clock_t *clock)
79e53945 464{
79e53945 465 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 466 INTELPllInvalid("p1 out of range\n");
79e53945 467 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 468 INTELPllInvalid("p out of range\n");
79e53945 469 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 470 INTELPllInvalid("m2 out of range\n");
79e53945 471 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 472 INTELPllInvalid("m1 out of range\n");
f2b115e6 473 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 474 INTELPllInvalid("m1 <= m2\n");
79e53945 475 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 476 INTELPllInvalid("m out of range\n");
79e53945 477 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 478 INTELPllInvalid("n out of range\n");
79e53945 479 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 480 INTELPllInvalid("vco out of range\n");
79e53945
JB		 481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
483 */
484 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 485 INTELPllInvalid("dot out of range\n");
79e53945
JB		 486
487 return true;
488}
489
d4906093 490static bool
ee9300bb 491i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 492 int target, int refclk, intel_clock_t *match_clock,
493 intel_clock_t *best_clock)
79e53945
JB		 494{
495 struct drm_device *dev = crtc->dev;
79e53945 496 intel_clock_t clock;
79e53945
JB		 497 int err = target;
498
a210b028 499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 500 /*
a210b028
DV		 501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
79e53945 504 */
1974cad0 505 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 506 clock.p2 = limit->p2.p2_fast;
507 else
508 clock.p2 = limit->p2.p2_slow;
509 } else {
510 if (target < limit->p2.dot_limit)
511 clock.p2 = limit->p2.p2_slow;
512 else
513 clock.p2 = limit->p2.p2_fast;
514 }
515
0206e353 516 memset(best_clock, 0, sizeof(*best_clock));
79e53945 517
42158660
ZY		 518 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
519 clock.m1++) {
520 for (clock.m2 = limit->m2.min;
521 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 522 if (clock.m2 >= clock.m1)
42158660
ZY		 523 break;
524 for (clock.n = limit->n.min;
525 clock.n <= limit->n.max; clock.n++) {
526 for (clock.p1 = limit->p1.min;
527 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 528 int this_err;
529
ac58c3f0
DV		 530 i9xx_clock(refclk, &clock);
531 if (!intel_PLL_is_valid(dev, limit,
532 &clock))
533 continue;
534 if (match_clock &&
535 clock.p != match_clock->p)
536 continue;
537
538 this_err = abs(clock.dot - target);
539 if (this_err < err) {
540 *best_clock = clock;
541 err = this_err;
542 }
543 }
544 }
545 }
546 }
547
548 return (err != target);
549}
550
551static bool
ee9300bb
DV		 552pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
553 int target, int refclk, intel_clock_t *match_clock,
554 intel_clock_t *best_clock)
79e53945
JB		 555{
556 struct drm_device *dev = crtc->dev;
79e53945 557 intel_clock_t clock;
79e53945
JB		 558 int err = target;
559
a210b028 560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 561 /*
a210b028
DV		 562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
79e53945 565 */
1974cad0 566 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 567 clock.p2 = limit->p2.p2_fast;
568 else
569 clock.p2 = limit->p2.p2_slow;
570 } else {
571 if (target < limit->p2.dot_limit)
572 clock.p2 = limit->p2.p2_slow;
573 else
574 clock.p2 = limit->p2.p2_fast;
575 }
576
0206e353 577 memset(best_clock, 0, sizeof(*best_clock));
79e53945 578
42158660
ZY		 579 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
580 clock.m1++) {
581 for (clock.m2 = limit->m2.min;
582 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 583 for (clock.n = limit->n.min;
584 clock.n <= limit->n.max; clock.n++) {
585 for (clock.p1 = limit->p1.min;
586 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 587 int this_err;
588
ac58c3f0 589 pineview_clock(refclk, &clock);
1b894b59
CW		 590 if (!intel_PLL_is_valid(dev, limit,
591 &clock))
79e53945 592 continue;
cec2f356
SP		 593 if (match_clock &&
594 clock.p != match_clock->p)
595 continue;
79e53945
JB		 596
597 this_err = abs(clock.dot - target);
598 if (this_err < err) {
599 *best_clock = clock;
600 err = this_err;
601 }
602 }
603 }
604 }
605 }
606
607 return (err != target);
608}
609
d4906093 610static bool
ee9300bb
DV		 611g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
612 int target, int refclk, intel_clock_t *match_clock,
613 intel_clock_t *best_clock)
d4906093
ML		 614{
615 struct drm_device *dev = crtc->dev;
d4906093
ML		 616 intel_clock_t clock;
617 int max_n;
618 bool found;
6ba770dc
AJ		 619 /* approximately equals target * 0.00585 */
620 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 621 found = false;
622
623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 624 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 625 clock.p2 = limit->p2.p2_fast;
626 else
627 clock.p2 = limit->p2.p2_slow;
628 } else {
629 if (target < limit->p2.dot_limit)
630 clock.p2 = limit->p2.p2_slow;
631 else
632 clock.p2 = limit->p2.p2_fast;
633 }
634
635 memset(best_clock, 0, sizeof(*best_clock));
636 max_n = limit->n.max;
f77f13e2 637 /* based on hardware requirement, prefer smaller n to precision */
d4906093 638 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 639 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 640 for (clock.m1 = limit->m1.max;
641 clock.m1 >= limit->m1.min; clock.m1--) {
642 for (clock.m2 = limit->m2.max;
643 clock.m2 >= limit->m2.min; clock.m2--) {
644 for (clock.p1 = limit->p1.max;
645 clock.p1 >= limit->p1.min; clock.p1--) {
646 int this_err;
647
ac58c3f0 648 i9xx_clock(refclk, &clock);
1b894b59
CW		 649 if (!intel_PLL_is_valid(dev, limit,
650 &clock))
d4906093 651 continue;
1b894b59
CW		 652
653 this_err = abs(clock.dot - target);
d4906093
ML		 654 if (this_err < err_most) {
655 *best_clock = clock;
656 err_most = this_err;
657 max_n = clock.n;
658 found = true;
659 }
660 }
661 }
662 }
663 }
2c07245f
ZW		 664 return found;
665}
666
a0c4da24 667static bool
ee9300bb
DV		 668vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *match_clock,
670 intel_clock_t *best_clock)
a0c4da24
JB		 671{
672 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
673 u32 m, n, fastclk;
f3f08572 674 u32 updrate, minupdate, p;
a0c4da24
JB		 675 unsigned long bestppm, ppm, absppm;
676 int dotclk, flag;
677
af447bd3 678 flag = 0;
a0c4da24
JB		 679 dotclk = target * 1000;
680 bestppm = 1000000;
681 ppm = absppm = 0;
682 fastclk = dotclk / (2*100);
683 updrate = 0;
684 minupdate = 19200;
a0c4da24
JB		 685 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
686 bestm1 = bestm2 = bestp1 = bestp2 = 0;
687
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
690 updrate = refclk / n;
691 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
692 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
693 if (p2 > 10)
694 p2 = p2 - 1;
695 p = p1 * p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
5de56df5 698 m2 = DIV_ROUND_CLOSEST(fastclk * p * n, refclk * m1);
a0c4da24
JB		 699 m = m1 * m2;
700 vco = updrate * m;
43b0ac53
VS		 701
702 if (vco < limit->vco.min || vco >= limit->vco.max)
703 continue;
704
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
a0c4da24
JB		 722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
241bfc38 743 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
241bfc38 750 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
f6071166
JB		 1469static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1470{
1471 u32 val = 0;
1472
1473 /* Make sure the pipe isn't still relying on us */
1474 assert_pipe_disabled(dev_priv, pipe);
1475
1476 /* Leave integrated clock source enabled */
1477 if (pipe == PIPE_B)
1478 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1479 I915_WRITE(DPLL(pipe), val);
1480 POSTING_READ(DPLL(pipe));
1481}
1482
89b667f8
JB		 1483void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1484{
1485 u32 port_mask;
1486
1487 if (!port)
1488 port_mask = DPLL_PORTB_READY_MASK;
1489 else
1490 port_mask = DPLL_PORTC_READY_MASK;
1491
1492 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1493 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1494 'B' + port, I915_READ(DPLL(0)));
1495}
1496
92f2584a 1497/**
e72f9fbf 1498 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1499 * @dev_priv: i915 private structure
1500 * @pipe: pipe PLL to enable
1501 *
1502 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1503 * drives the transcoder clock.
1504 */
e2b78267 1505static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1506{
e2b78267
DV		 1507 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1508 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1509
48da64a8 1510 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1511 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1512 if (WARN_ON(pll == NULL))
48da64a8
CW		 1513 return;
1514
1515 if (WARN_ON(pll->refcount == 0))
1516 return;
ee7b9f93 1517
46edb027
DV		 1518 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1519 pll->name, pll->active, pll->on,
e2b78267 1520 crtc->base.base.id);
92f2584a 1521
cdbd2316
DV		 1522 if (pll->active++) {
1523 WARN_ON(!pll->on);
e9d6944e 1524 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1525 return;
1526 }
f4a091c7 1527 WARN_ON(pll->on);
ee7b9f93 1528
46edb027 1529 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1530 pll->enable(dev_priv, pll);
ee7b9f93 1531 pll->on = true;
92f2584a
JB		 1532}
1533
e2b78267 1534static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1535{
e2b78267
DV		 1536 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1537 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1538
92f2584a
JB		 1539 /* PCH only available on ILK+ */
1540 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1541 if (WARN_ON(pll == NULL))
ee7b9f93 1542 return;
92f2584a 1543
48da64a8
CW		 1544 if (WARN_ON(pll->refcount == 0))
1545 return;
7a419866 1546
46edb027
DV		 1547 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1548 pll->name, pll->active, pll->on,
e2b78267 1549 crtc->base.base.id);
7a419866 1550
48da64a8 1551 if (WARN_ON(pll->active == 0)) {
e9d6944e 1552 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1553 return;
1554 }
1555
e9d6944e 1556 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1557 WARN_ON(!pll->on);
cdbd2316 1558 if (--pll->active)
7a419866 1559 return;
ee7b9f93 1560
46edb027 1561 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1562 pll->disable(dev_priv, pll);
ee7b9f93 1563 pll->on = false;
92f2584a
JB		 1564}
1565
b8a4f404
PZ		 1566static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
040484af 1568{
23670b32 1569 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1570 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1572 uint32_t reg, val, pipeconf_val;
040484af
JB		 1573
1574 /* PCH only available on ILK+ */
1575 BUG_ON(dev_priv->info->gen < 5);
1576
1577 /* Make sure PCH DPLL is enabled */
e72f9fbf 1578 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1579 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1580
1581 /* FDI must be feeding us bits for PCH ports */
1582 assert_fdi_tx_enabled(dev_priv, pipe);
1583 assert_fdi_rx_enabled(dev_priv, pipe);
1584
23670b32
DV		 1585 if (HAS_PCH_CPT(dev)) {
1586 /* Workaround: Set the timing override bit before enabling the
1587 * pch transcoder. */
1588 reg = TRANS_CHICKEN2(pipe);
1589 val = I915_READ(reg);
1590 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1591 I915_WRITE(reg, val);
59c859d6 1592 }
23670b32 1593
ab9412ba 1594 reg = PCH_TRANSCONF(pipe);
040484af 1595 val = I915_READ(reg);
5f7f726d 1596 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1597
1598 if (HAS_PCH_IBX(dev_priv->dev)) {
1599 /*
1600 * make the BPC in transcoder be consistent with
1601 * that in pipeconf reg.
1602 */
dfd07d72
DV		 1603 val &= ~PIPECONF_BPC_MASK;
1604 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1605 }
5f7f726d
PZ		 1606
1607 val &= ~TRANS_INTERLACE_MASK;
1608 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1609 if (HAS_PCH_IBX(dev_priv->dev) &&
1610 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1611 val |= TRANS_LEGACY_INTERLACED_ILK;
1612 else
1613 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1614 else
1615 val |= TRANS_PROGRESSIVE;
1616
040484af
JB		 1617 I915_WRITE(reg, val | TRANS_ENABLE);
1618 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1619 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1620}
1621
8fb033d7 1622static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1623 enum transcoder cpu_transcoder)
040484af 1624{
8fb033d7 1625 u32 val, pipeconf_val;
8fb033d7
PZ		 1626
1627 /* PCH only available on ILK+ */
1628 BUG_ON(dev_priv->info->gen < 5);
1629
8fb033d7 1630 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1631 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1632 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1633
223a6fdf
PZ		 1634 /* Workaround: set timing override bit. */
1635 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1636 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1637 I915_WRITE(_TRANSA_CHICKEN2, val);
1638
25f3ef11 1639 val = TRANS_ENABLE;
937bb610 1640 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1641
9a76b1c6
PZ		 1642 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1643 PIPECONF_INTERLACED_ILK)
a35f2679 1644 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1645 else
1646 val |= TRANS_PROGRESSIVE;
1647
ab9412ba
DV		 1648 I915_WRITE(LPT_TRANSCONF, val);
1649 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1650 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1651}
1652
b8a4f404
PZ		 1653static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1654 enum pipe pipe)
040484af 1655{
23670b32
DV		 1656 struct drm_device *dev = dev_priv->dev;
1657 uint32_t reg, val;
040484af
JB		 1658
1659 /* FDI relies on the transcoder */
1660 assert_fdi_tx_disabled(dev_priv, pipe);
1661 assert_fdi_rx_disabled(dev_priv, pipe);
1662
291906f1
JB		 1663 /* Ports must be off as well */
1664 assert_pch_ports_disabled(dev_priv, pipe);
1665
ab9412ba 1666 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1667 val = I915_READ(reg);
1668 val &= ~TRANS_ENABLE;
1669 I915_WRITE(reg, val);
1670 /* wait for PCH transcoder off, transcoder state */
1671 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1672 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1673
1674 if (!HAS_PCH_IBX(dev)) {
1675 /* Workaround: Clear the timing override chicken bit again. */
1676 reg = TRANS_CHICKEN2(pipe);
1677 val = I915_READ(reg);
1678 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1679 I915_WRITE(reg, val);
1680 }
040484af
JB		 1681}
1682
ab4d966c 1683static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1684{
8fb033d7
PZ		 1685 u32 val;
1686
ab9412ba 1687 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1688 val &= ~TRANS_ENABLE;
ab9412ba 1689 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1690 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1691 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1692 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1693
1694 /* Workaround: clear timing override bit. */
1695 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1696 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1697 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1698}
1699
b24e7179 1700/**
309cfea8 1701 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1702 * @dev_priv: i915 private structure
1703 * @pipe: pipe to enable
040484af 1704 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1705 *
1706 * Enable @pipe, making sure that various hardware specific requirements
1707 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1708 *
1709 * @pipe should be %PIPE_A or %PIPE_B.
1710 *
1711 * Will wait until the pipe is actually running (i.e. first vblank) before
1712 * returning.
1713 */
040484af 1714static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1715 bool pch_port, bool dsi)
b24e7179 1716{
702e7a56
PZ		 1717 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1718 pipe);
1a240d4d 1719 enum pipe pch_transcoder;
b24e7179
JB		 1720 int reg;
1721 u32 val;
1722
58c6eaa2 1723 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1724 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1725 assert_sprites_disabled(dev_priv, pipe);
1726
681e5811 1727 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1728 pch_transcoder = TRANSCODER_A;
1729 else
1730 pch_transcoder = pipe;
1731
b24e7179
JB		 1732 /*
1733 * A pipe without a PLL won't actually be able to drive bits from
1734 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1735 * need the check.
1736 */
1737 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1738 if (dsi)
1739 assert_dsi_pll_enabled(dev_priv);
1740 else
1741 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1742 else {
1743 if (pch_port) {
1744 /* if driving the PCH, we need FDI enabled */
cc391bbb 1745 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1746 assert_fdi_tx_pll_enabled(dev_priv,
1747 (enum pipe) cpu_transcoder);
040484af
JB		 1748 }
1749 /* FIXME: assert CPU port conditions for SNB+ */
1750 }
b24e7179 1751
702e7a56 1752 reg = PIPECONF(cpu_transcoder);
b24e7179 1753 val = I915_READ(reg);
00d70b15
CW		 1754 if (val & PIPECONF_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1758 intel_wait_for_vblank(dev_priv->dev, pipe);
1759}
1760
1761/**
309cfea8 1762 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1763 * @dev_priv: i915 private structure
1764 * @pipe: pipe to disable
1765 *
1766 * Disable @pipe, making sure that various hardware specific requirements
1767 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1768 *
1769 * @pipe should be %PIPE_A or %PIPE_B.
1770 *
1771 * Will wait until the pipe has shut down before returning.
1772 */
1773static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1774 enum pipe pipe)
1775{
702e7a56
PZ		 1776 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1777 pipe);
b24e7179
JB		 1778 int reg;
1779 u32 val;
1780
1781 /*
1782 * Make sure planes won't keep trying to pump pixels to us,
1783 * or we might hang the display.
1784 */
1785 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1786 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1787 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1788
1789 /* Don't disable pipe A or pipe A PLLs if needed */
1790 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1791 return;
1792
702e7a56 1793 reg = PIPECONF(cpu_transcoder);
b24e7179 1794 val = I915_READ(reg);
00d70b15
CW		 1795 if ((val & PIPECONF_ENABLE) == 0)
1796 return;
1797
1798 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1799 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1800}
1801
d74362c9
KP		 1802/*
1803 * Plane regs are double buffered, going from enabled->disabled needs a
1804 * trigger in order to latch. The display address reg provides this.
1805 */
6f1d69b0 1806void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1807 enum plane plane)
1808{
14f86147
DL		 1809 if (dev_priv->info->gen >= 4)
1810 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1811 else
1812 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1813}
1814
b24e7179
JB		 1815/**
1816 * intel_enable_plane - enable a display plane on a given pipe
1817 * @dev_priv: i915 private structure
1818 * @plane: plane to enable
1819 * @pipe: pipe being fed
1820 *
1821 * Enable @plane on @pipe, making sure that @pipe is running first.
1822 */
1823static void intel_enable_plane(struct drm_i915_private *dev_priv,
1824 enum plane plane, enum pipe pipe)
1825{
1826 int reg;
1827 u32 val;
1828
1829 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1830 assert_pipe_enabled(dev_priv, pipe);
1831
1832 reg = DSPCNTR(plane);
1833 val = I915_READ(reg);
00d70b15
CW		 1834 if (val & DISPLAY_PLANE_ENABLE)
1835 return;
1836
1837 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1838 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1839 intel_wait_for_vblank(dev_priv->dev, pipe);
1840}
1841
b24e7179
JB		 1842/**
1843 * intel_disable_plane - disable a display plane
1844 * @dev_priv: i915 private structure
1845 * @plane: plane to disable
1846 * @pipe: pipe consuming the data
1847 *
1848 * Disable @plane; should be an independent operation.
1849 */
1850static void intel_disable_plane(struct drm_i915_private *dev_priv,
1851 enum plane plane, enum pipe pipe)
1852{
1853 int reg;
1854 u32 val;
1855
1856 reg = DSPCNTR(plane);
1857 val = I915_READ(reg);
00d70b15
CW		 1858 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1859 return;
1860
1861 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1862 intel_flush_display_plane(dev_priv, plane);
1863 intel_wait_for_vblank(dev_priv->dev, pipe);
1864}
1865
693db184
CW		 1866static bool need_vtd_wa(struct drm_device *dev)
1867{
1868#ifdef CONFIG_INTEL_IOMMU
1869 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1870 return true;
1871#endif
1872 return false;
1873}
1874
127bd2ac 1875int
48b956c5 1876intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1877 struct drm_i915_gem_object *obj,
919926ae 1878 struct intel_ring_buffer *pipelined)
6b95a207 1879{
ce453d81 1880 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1881 u32 alignment;
1882 int ret;
1883
05394f39 1884 switch (obj->tiling_mode) {
6b95a207 1885 case I915_TILING_NONE:
534843da
CW		 1886 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1887 alignment = 128 * 1024;
a6c45cf0 1888 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1889 alignment = 4 * 1024;
1890 else
1891 alignment = 64 * 1024;
6b95a207
KH		 1892 break;
1893 case I915_TILING_X:
1894 /* pin() will align the object as required by fence */
1895 alignment = 0;
1896 break;
1897 case I915_TILING_Y:
8bb6e959
DV		 1898 /* Despite that we check this in framebuffer_init userspace can
1899 * screw us over and change the tiling after the fact. Only
1900 * pinned buffers can't change their tiling. */
1901 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1902 return -EINVAL;
1903 default:
1904 BUG();
1905 }
1906
693db184
CW		 1907 /* Note that the w/a also requires 64 PTE of padding following the
1908 * bo. We currently fill all unused PTE with the shadow page and so
1909 * we should always have valid PTE following the scanout preventing
1910 * the VT-d warning.
1911 */
1912 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1913 alignment = 256 * 1024;
1914
ce453d81 1915 dev_priv->mm.interruptible = false;
2da3b9b9 1916 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1917 if (ret)
ce453d81 1918 goto err_interruptible;
6b95a207
KH		 1919
1920 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1921 * fence, whereas 965+ only requires a fence if using
1922 * framebuffer compression. For simplicity, we always install
1923 * a fence as the cost is not that onerous.
1924 */
06d98131 1925 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1926 if (ret)
1927 goto err_unpin;
1690e1eb 1928
9a5a53b3 1929 i915_gem_object_pin_fence(obj);
6b95a207 1930
ce453d81 1931 dev_priv->mm.interruptible = true;
6b95a207 1932 return 0;
48b956c5
CW		 1933
1934err_unpin:
cc98b413 1935 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1936err_interruptible:
1937 dev_priv->mm.interruptible = true;
48b956c5 1938 return ret;
6b95a207
KH		 1939}
1940
1690e1eb
CW		 1941void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1942{
1943 i915_gem_object_unpin_fence(obj);
cc98b413 1944 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1945}
1946
c2c75131
DV		 1947/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1948 * is assumed to be a power-of-two. */
bc752862
CW		 1949unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1950 unsigned int tiling_mode,
1951 unsigned int cpp,
1952 unsigned int pitch)
c2c75131 1953{
bc752862
CW		 1954 if (tiling_mode != I915_TILING_NONE) {
1955 unsigned int tile_rows, tiles;
c2c75131 1956
bc752862
CW		 1957 tile_rows = *y / 8;
1958 *y %= 8;
c2c75131 1959
bc752862
CW		 1960 tiles = *x / (512/cpp);
1961 *x %= 512/cpp;
1962
1963 return tile_rows * pitch * 8 + tiles * 4096;
1964 } else {
1965 unsigned int offset;
1966
1967 offset = *y * pitch + *x * cpp;
1968 *y = 0;
1969 *x = (offset & 4095) / cpp;
1970 return offset & -4096;
1971 }
c2c75131
DV		 1972}
1973
17638cd6
JB		 1974static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975 int x, int y)
81255565
JB		 1976{
1977 struct drm_device *dev = crtc->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 struct intel_framebuffer *intel_fb;
05394f39 1981 struct drm_i915_gem_object *obj;
81255565 1982 int plane = intel_crtc->plane;
e506a0c6 1983 unsigned long linear_offset;
81255565 1984 u32 dspcntr;
5eddb70b 1985 u32 reg;
81255565
JB		 1986
1987 switch (plane) {
1988 case 0:
1989 case 1:
1990 break;
1991 default:
84f44ce7 1992 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1993 return -EINVAL;
1994 }
1995
1996 intel_fb = to_intel_framebuffer(fb);
1997 obj = intel_fb->obj;
81255565 1998
5eddb70b
CW		 1999 reg = DSPCNTR(plane);
2000 dspcntr = I915_READ(reg);
81255565
JB		 2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2003 switch (fb->pixel_format) {
2004 case DRM_FORMAT_C8:
81255565
JB		 2005 dspcntr |= DISPPLANE_8BPP;
2006 break;
57779d06
VS		 2007 case DRM_FORMAT_XRGB1555:
2008 case DRM_FORMAT_ARGB1555:
2009 dspcntr |= DISPPLANE_BGRX555;
81255565 2010 break;
57779d06
VS		 2011 case DRM_FORMAT_RGB565:
2012 dspcntr |= DISPPLANE_BGRX565;
2013 break;
2014 case DRM_FORMAT_XRGB8888:
2015 case DRM_FORMAT_ARGB8888:
2016 dspcntr |= DISPPLANE_BGRX888;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 dspcntr |= DISPPLANE_RGBX888;
2021 break;
2022 case DRM_FORMAT_XRGB2101010:
2023 case DRM_FORMAT_ARGB2101010:
2024 dspcntr |= DISPPLANE_BGRX101010;
2025 break;
2026 case DRM_FORMAT_XBGR2101010:
2027 case DRM_FORMAT_ABGR2101010:
2028 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2029 break;
2030 default:
baba133a 2031 BUG();
81255565 2032 }
57779d06 2033
a6c45cf0 2034 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2035 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2036 dspcntr |= DISPPLANE_TILED;
2037 else
2038 dspcntr &= ~DISPPLANE_TILED;
2039 }
2040
de1aa629
VS		 2041 if (IS_G4X(dev))
2042 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2043
5eddb70b 2044 I915_WRITE(reg, dspcntr);
81255565 2045
e506a0c6 2046 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2047
c2c75131
DV		 2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 intel_crtc->dspaddr_offset =
bc752862
CW		 2050 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051 fb->bits_per_pixel / 8,
2052 fb->pitches[0]);
c2c75131
DV		 2053 linear_offset -= intel_crtc->dspaddr_offset;
2054 } else {
e506a0c6 2055 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2056 }
e506a0c6 2057
f343c5f6
BW		 2058 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2059 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2060 fb->pitches[0]);
01f2c773 2061 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2062 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2063 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2064 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2065 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2066 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2067 } else
f343c5f6 2068 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2069 POSTING_READ(reg);
81255565 2070
17638cd6
JB		 2071 return 0;
2072}
2073
2074static int ironlake_update_plane(struct drm_crtc *crtc,
2075 struct drm_framebuffer *fb, int x, int y)
2076{
2077 struct drm_device *dev = crtc->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 struct intel_framebuffer *intel_fb;
2081 struct drm_i915_gem_object *obj;
2082 int plane = intel_crtc->plane;
e506a0c6 2083 unsigned long linear_offset;
17638cd6
JB		 2084 u32 dspcntr;
2085 u32 reg;
2086
2087 switch (plane) {
2088 case 0:
2089 case 1:
27f8227b 2090 case 2:
17638cd6
JB		 2091 break;
2092 default:
84f44ce7 2093 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2094 return -EINVAL;
2095 }
2096
2097 intel_fb = to_intel_framebuffer(fb);
2098 obj = intel_fb->obj;
2099
2100 reg = DSPCNTR(plane);
2101 dspcntr = I915_READ(reg);
2102 /* Mask out pixel format bits in case we change it */
2103 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2104 switch (fb->pixel_format) {
2105 case DRM_FORMAT_C8:
17638cd6
JB		 2106 dspcntr |= DISPPLANE_8BPP;
2107 break;
57779d06
VS		 2108 case DRM_FORMAT_RGB565:
2109 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2110 break;
57779d06
VS		 2111 case DRM_FORMAT_XRGB8888:
2112 case DRM_FORMAT_ARGB8888:
2113 dspcntr |= DISPPLANE_BGRX888;
2114 break;
2115 case DRM_FORMAT_XBGR8888:
2116 case DRM_FORMAT_ABGR8888:
2117 dspcntr |= DISPPLANE_RGBX888;
2118 break;
2119 case DRM_FORMAT_XRGB2101010:
2120 case DRM_FORMAT_ARGB2101010:
2121 dspcntr |= DISPPLANE_BGRX101010;
2122 break;
2123 case DRM_FORMAT_XBGR2101010:
2124 case DRM_FORMAT_ABGR2101010:
2125 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2126 break;
2127 default:
baba133a 2128 BUG();
17638cd6
JB		 2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
1f5d76db
PZ		 2136 if (IS_HASWELL(dev))
2137 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2138 else
2139 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2140
2141 I915_WRITE(reg, dspcntr);
2142
e506a0c6 2143 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2144 intel_crtc->dspaddr_offset =
bc752862
CW		 2145 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2146 fb->bits_per_pixel / 8,
2147 fb->pitches[0]);
c2c75131 2148 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2149
f343c5f6
BW		 2150 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2151 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2152 fb->pitches[0]);
01f2c773 2153 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2154 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2155 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2156 if (IS_HASWELL(dev)) {
2157 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2158 } else {
2159 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2160 I915_WRITE(DSPLINOFF(plane), linear_offset);
2161 }
17638cd6
JB		 2162 POSTING_READ(reg);
2163
2164 return 0;
2165}
2166
2167/* Assume fb object is pinned & idle & fenced and just update base pointers */
2168static int
2169intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2170 int x, int y, enum mode_set_atomic state)
2171{
2172 struct drm_device *dev = crtc->dev;
2173 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2174
6b8e6ed0
CW		 2175 if (dev_priv->display.disable_fbc)
2176 dev_priv->display.disable_fbc(dev);
3dec0095 2177 intel_increase_pllclock(crtc);
81255565 2178
6b8e6ed0 2179 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2180}
2181
96a02917
VS		 2182void intel_display_handle_reset(struct drm_device *dev)
2183{
2184 struct drm_i915_private *dev_priv = dev->dev_private;
2185 struct drm_crtc *crtc;
2186
2187 /*
2188 * Flips in the rings have been nuked by the reset,
2189 * so complete all pending flips so that user space
2190 * will get its events and not get stuck.
2191 *
2192 * Also update the base address of all primary
2193 * planes to the the last fb to make sure we're
2194 * showing the correct fb after a reset.
2195 *
2196 * Need to make two loops over the crtcs so that we
2197 * don't try to grab a crtc mutex before the
2198 * pending_flip_queue really got woken up.
2199 */
2200
2201 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2203 enum plane plane = intel_crtc->plane;
2204
2205 intel_prepare_page_flip(dev, plane);
2206 intel_finish_page_flip_plane(dev, plane);
2207 }
2208
2209 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2211
2212 mutex_lock(&crtc->mutex);
2213 if (intel_crtc->active)
2214 dev_priv->display.update_plane(crtc, crtc->fb,
2215 crtc->x, crtc->y);
2216 mutex_unlock(&crtc->mutex);
2217 }
2218}
2219
14667a4b
CW		 2220static int
2221intel_finish_fb(struct drm_framebuffer *old_fb)
2222{
2223 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2224 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2225 bool was_interruptible = dev_priv->mm.interruptible;
2226 int ret;
2227
14667a4b
CW		 2228 /* Big Hammer, we also need to ensure that any pending
2229 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2230 * current scanout is retired before unpinning the old
2231 * framebuffer.
2232 *
2233 * This should only fail upon a hung GPU, in which case we
2234 * can safely continue.
2235 */
2236 dev_priv->mm.interruptible = false;
2237 ret = i915_gem_object_finish_gpu(obj);
2238 dev_priv->mm.interruptible = was_interruptible;
2239
2240 return ret;
2241}
2242
198598d0
VS		 2243static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2244{
2245 struct drm_device *dev = crtc->dev;
2246 struct drm_i915_master_private *master_priv;
2247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2248
2249 if (!dev->primary->master)
2250 return;
2251
2252 master_priv = dev->primary->master->driver_priv;
2253 if (!master_priv->sarea_priv)
2254 return;
2255
2256 switch (intel_crtc->pipe) {
2257 case 0:
2258 master_priv->sarea_priv->pipeA_x = x;
2259 master_priv->sarea_priv->pipeA_y = y;
2260 break;
2261 case 1:
2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
2264 break;
2265 default:
2266 break;
2267 }
2268}
2269
5c3b82e2 2270static int
3c4fdcfb 2271intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2272 struct drm_framebuffer *fb)
79e53945
JB		 2273{
2274 struct drm_device *dev = crtc->dev;
6b8e6ed0 2275 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2277 struct drm_framebuffer *old_fb;
5c3b82e2 2278 int ret;
79e53945
JB		 2279
2280 /* no fb bound */
94352cf9 2281 if (!fb) {
a5071c2f 2282 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2283 return 0;
2284 }
2285
7eb552ae 2286 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2287 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2288 plane_name(intel_crtc->plane),
2289 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2290 return -EINVAL;
79e53945
JB		 2291 }
2292
5c3b82e2 2293 mutex_lock(&dev->struct_mutex);
265db958 2294 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2295 to_intel_framebuffer(fb)->obj,
919926ae 2296 NULL);
5c3b82e2
CW		 2297 if (ret != 0) {
2298 mutex_unlock(&dev->struct_mutex);
a5071c2f 2299 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2300 return ret;
2301 }
79e53945 2302
4d6a3e63
JB		 2303 /* Update pipe size and adjust fitter if needed */
2304 if (i915_fastboot) {
2305 I915_WRITE(PIPESRC(intel_crtc->pipe),
2306 ((crtc->mode.hdisplay - 1) << 16) |
2307 (crtc->mode.vdisplay - 1));
fd4daa9c 2308 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2309 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2310 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2311 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2312 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2313 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2314 }
2315 }
2316
94352cf9 2317 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2318 if (ret) {
94352cf9 2319 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2320 mutex_unlock(&dev->struct_mutex);
a5071c2f 2321 DRM_ERROR("failed to update base address\n");
4e6cfefc 2322 return ret;
79e53945 2323 }
3c4fdcfb 2324
94352cf9
DV		 2325 old_fb = crtc->fb;
2326 crtc->fb = fb;
6c4c86f5
DV		 2327 crtc->x = x;
2328 crtc->y = y;
94352cf9 2329
b7f1de28 2330 if (old_fb) {
d7697eea
DV		 2331 if (intel_crtc->active && old_fb != fb)
2332 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2333 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2334 }
652c393a 2335
6b8e6ed0 2336 intel_update_fbc(dev);
4906557e 2337 intel_edp_psr_update(dev);
5c3b82e2 2338 mutex_unlock(&dev->struct_mutex);
79e53945 2339
198598d0 2340 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2341
2342 return 0;
79e53945
JB		 2343}
2344
5e84e1a4
ZW		 2345static void intel_fdi_normal_train(struct drm_crtc *crtc)
2346{
2347 struct drm_device *dev = crtc->dev;
2348 struct drm_i915_private *dev_priv = dev->dev_private;
2349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2350 int pipe = intel_crtc->pipe;
2351 u32 reg, temp;
2352
2353 /* enable normal train */
2354 reg = FDI_TX_CTL(pipe);
2355 temp = I915_READ(reg);
61e499bf 2356 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2357 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2358 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2359 } else {
2360 temp &= ~FDI_LINK_TRAIN_NONE;
2361 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2362 }
5e84e1a4
ZW		 2363 I915_WRITE(reg, temp);
2364
2365 reg = FDI_RX_CTL(pipe);
2366 temp = I915_READ(reg);
2367 if (HAS_PCH_CPT(dev)) {
2368 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2369 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2370 } else {
2371 temp &= ~FDI_LINK_TRAIN_NONE;
2372 temp |= FDI_LINK_TRAIN_NONE;
2373 }
2374 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2375
2376 /* wait one idle pattern time */
2377 POSTING_READ(reg);
2378 udelay(1000);
357555c0
JB		 2379
2380 /* IVB wants error correction enabled */
2381 if (IS_IVYBRIDGE(dev))
2382 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2383 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2384}
2385
1e833f40
DV		 2386static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2387{
2388 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2389}
2390
01a415fd
DV		 2391static void ivb_modeset_global_resources(struct drm_device *dev)
2392{
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 struct intel_crtc *pipe_B_crtc =
2395 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2396 struct intel_crtc *pipe_C_crtc =
2397 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2398 uint32_t temp;
2399
1e833f40
DV		 2400 /*
2401 * When everything is off disable fdi C so that we could enable fdi B
2402 * with all lanes. Note that we don't care about enabled pipes without
2403 * an enabled pch encoder.
2404 */
2405 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2406 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2407 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2408 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2409
2410 temp = I915_READ(SOUTH_CHICKEN1);
2411 temp &= ~FDI_BC_BIFURCATION_SELECT;
2412 DRM_DEBUG_KMS("disabling fdi C rx\n");
2413 I915_WRITE(SOUTH_CHICKEN1, temp);
2414 }
2415}
2416
8db9d77b
ZW		 2417/* The FDI link training functions for ILK/Ibexpeak. */
2418static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2419{
2420 struct drm_device *dev = crtc->dev;
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2423 int pipe = intel_crtc->pipe;
0fc932b8 2424 int plane = intel_crtc->plane;
5eddb70b 2425 u32 reg, temp, tries;
8db9d77b 2426
0fc932b8
JB		 2427 /* FDI needs bits from pipe & plane first */
2428 assert_pipe_enabled(dev_priv, pipe);
2429 assert_plane_enabled(dev_priv, plane);
2430
e1a44743
AJ		 2431 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2432 for train result */
5eddb70b
CW		 2433 reg = FDI_RX_IMR(pipe);
2434 temp = I915_READ(reg);
e1a44743
AJ		 2435 temp &= ~FDI_RX_SYMBOL_LOCK;
2436 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2437 I915_WRITE(reg, temp);
2438 I915_READ(reg);
e1a44743
AJ		 2439 udelay(150);
2440
8db9d77b 2441 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2442 reg = FDI_TX_CTL(pipe);
2443 temp = I915_READ(reg);
627eb5a3
DV		 2444 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2445 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2448 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2449
5eddb70b
CW		 2450 reg = FDI_RX_CTL(pipe);
2451 temp = I915_READ(reg);
8db9d77b
ZW		 2452 temp &= ~FDI_LINK_TRAIN_NONE;
2453 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2454 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2455
2456 POSTING_READ(reg);
8db9d77b
ZW		 2457 udelay(150);
2458
5b2adf89 2459 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2462 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2463
5eddb70b 2464 reg = FDI_RX_IIR(pipe);
e1a44743 2465 for (tries = 0; tries < 5; tries++) {
5eddb70b 2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468
2469 if ((temp & FDI_RX_BIT_LOCK)) {
2470 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2471 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2472 break;
2473 }
8db9d77b 2474 }
e1a44743 2475 if (tries == 5)
5eddb70b 2476 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2477
2478 /* Train 2 */
5eddb70b
CW		 2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
8db9d77b
ZW		 2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2483 I915_WRITE(reg, temp);
8db9d77b 2484
5eddb70b
CW		 2485 reg = FDI_RX_CTL(pipe);
2486 temp = I915_READ(reg);
8db9d77b
ZW		 2487 temp &= ~FDI_LINK_TRAIN_NONE;
2488 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2489 I915_WRITE(reg, temp);
8db9d77b 2490
5eddb70b
CW		 2491 POSTING_READ(reg);
2492 udelay(150);
8db9d77b 2493
5eddb70b 2494 reg = FDI_RX_IIR(pipe);
e1a44743 2495 for (tries = 0; tries < 5; tries++) {
5eddb70b 2496 temp = I915_READ(reg);
8db9d77b
ZW		 2497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2498
2499 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2500 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2501 DRM_DEBUG_KMS("FDI train 2 done.\n");
2502 break;
2503 }
8db9d77b 2504 }
e1a44743 2505 if (tries == 5)
5eddb70b 2506 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2507
2508 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2509
8db9d77b
ZW		 2510}
2511
0206e353 2512static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2513 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2514 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2515 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2516 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2517};
2518
2519/* The FDI link training functions for SNB/Cougarpoint. */
2520static void gen6_fdi_link_train(struct drm_crtc *crtc)
2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
fa37d39e 2526 u32 reg, temp, i, retry;
8db9d77b 2527
e1a44743
AJ		 2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
5eddb70b
CW		 2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
e1a44743
AJ		 2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
e1a44743
AJ		 2537 udelay(150);
2538
8db9d77b 2539 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2540 reg = FDI_TX_CTL(pipe);
2541 temp = I915_READ(reg);
627eb5a3
DV		 2542 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2543 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2544 temp &= ~FDI_LINK_TRAIN_NONE;
2545 temp |= FDI_LINK_TRAIN_PATTERN_1;
2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547 /* SNB-B */
2548 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2549 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2550
d74cf324
DV		 2551 I915_WRITE(FDI_RX_MISC(pipe),
2552 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2553
5eddb70b
CW		 2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1;
2562 }
5eddb70b
CW		 2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(500);
2577
fa37d39e
SP		 2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_BIT_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2584 DRM_DEBUG_KMS("FDI train 1 done.\n");
2585 break;
2586 }
2587 udelay(50);
8db9d77b 2588 }
fa37d39e
SP		 2589 if (retry < 5)
2590 break;
8db9d77b
ZW		 2591 }
2592 if (i == 4)
5eddb70b 2593 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2594
2595 /* Train 2 */
5eddb70b
CW		 2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
8db9d77b
ZW		 2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_2;
2600 if (IS_GEN6(dev)) {
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 /* SNB-B */
2603 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2604 }
5eddb70b 2605 I915_WRITE(reg, temp);
8db9d77b 2606
5eddb70b
CW		 2607 reg = FDI_RX_CTL(pipe);
2608 temp = I915_READ(reg);
8db9d77b
ZW		 2609 if (HAS_PCH_CPT(dev)) {
2610 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2612 } else {
2613 temp &= ~FDI_LINK_TRAIN_NONE;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2;
2615 }
5eddb70b
CW		 2616 I915_WRITE(reg, temp);
2617
2618 POSTING_READ(reg);
8db9d77b
ZW		 2619 udelay(150);
2620
0206e353 2621 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2622 reg = FDI_TX_CTL(pipe);
2623 temp = I915_READ(reg);
8db9d77b
ZW		 2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2626 I915_WRITE(reg, temp);
2627
2628 POSTING_READ(reg);
8db9d77b
ZW		 2629 udelay(500);
2630
fa37d39e
SP		 2631 for (retry = 0; retry < 5; retry++) {
2632 reg = FDI_RX_IIR(pipe);
2633 temp = I915_READ(reg);
2634 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2635 if (temp & FDI_RX_SYMBOL_LOCK) {
2636 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2637 DRM_DEBUG_KMS("FDI train 2 done.\n");
2638 break;
2639 }
2640 udelay(50);
8db9d77b 2641 }
fa37d39e
SP		 2642 if (retry < 5)
2643 break;
8db9d77b
ZW		 2644 }
2645 if (i == 4)
5eddb70b 2646 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2647
2648 DRM_DEBUG_KMS("FDI train done.\n");
2649}
2650
357555c0
JB		 2651/* Manual link training for Ivy Bridge A0 parts */
2652static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2653{
2654 struct drm_device *dev = crtc->dev;
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2657 int pipe = intel_crtc->pipe;
139ccd3f 2658 u32 reg, temp, i, j;
357555c0
JB		 2659
2660 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2661 for train result */
2662 reg = FDI_RX_IMR(pipe);
2663 temp = I915_READ(reg);
2664 temp &= ~FDI_RX_SYMBOL_LOCK;
2665 temp &= ~FDI_RX_BIT_LOCK;
2666 I915_WRITE(reg, temp);
2667
2668 POSTING_READ(reg);
2669 udelay(150);
2670
01a415fd
DV		 2671 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2672 I915_READ(FDI_RX_IIR(pipe)));
2673
139ccd3f
JB		 2674 /* Try each vswing and preemphasis setting twice before moving on */
2675 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2676 /* disable first in case we need to retry */
2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2680 temp &= ~FDI_TX_ENABLE;
2681 I915_WRITE(reg, temp);
357555c0 2682
139ccd3f
JB		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_AUTO;
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp &= ~FDI_RX_ENABLE;
2688 I915_WRITE(reg, temp);
357555c0 2689
139ccd3f 2690 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
139ccd3f
JB		 2693 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2694 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2695 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2696 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2697 temp |= snb_b_fdi_train_param[j/2];
2698 temp |= FDI_COMPOSITE_SYNC;
2699 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2700
139ccd3f
JB		 2701 I915_WRITE(FDI_RX_MISC(pipe),
2702 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2703
139ccd3f 2704 reg = FDI_RX_CTL(pipe);
357555c0 2705 temp = I915_READ(reg);
139ccd3f
JB		 2706 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2707 temp |= FDI_COMPOSITE_SYNC;
2708 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2709
139ccd3f
JB		 2710 POSTING_READ(reg);
2711 udelay(1); /* should be 0.5us */
357555c0 2712
139ccd3f
JB		 2713 for (i = 0; i < 4; i++) {
2714 reg = FDI_RX_IIR(pipe);
2715 temp = I915_READ(reg);
2716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2717
139ccd3f
JB		 2718 if (temp & FDI_RX_BIT_LOCK ||
2719 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2720 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2721 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2722 i);
2723 break;
2724 }
2725 udelay(1); /* should be 0.5us */
2726 }
2727 if (i == 4) {
2728 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2729 continue;
2730 }
357555c0 2731
139ccd3f 2732 /* Train 2 */
357555c0
JB		 2733 reg = FDI_TX_CTL(pipe);
2734 temp = I915_READ(reg);
139ccd3f
JB		 2735 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2736 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2737 I915_WRITE(reg, temp);
2738
2739 reg = FDI_RX_CTL(pipe);
2740 temp = I915_READ(reg);
2741 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2742 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2743 I915_WRITE(reg, temp);
2744
2745 POSTING_READ(reg);
139ccd3f 2746 udelay(2); /* should be 1.5us */
357555c0 2747
139ccd3f
JB		 2748 for (i = 0; i < 4; i++) {
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2752
139ccd3f
JB		 2753 if (temp & FDI_RX_SYMBOL_LOCK ||
2754 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2755 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2756 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2757 i);
2758 goto train_done;
2759 }
2760 udelay(2); /* should be 1.5us */
357555c0 2761 }
139ccd3f
JB		 2762 if (i == 4)
2763 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2764 }
357555c0 2765
139ccd3f 2766train_done:
357555c0
JB		 2767 DRM_DEBUG_KMS("FDI train done.\n");
2768}
2769
88cefb6c 2770static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2771{
88cefb6c 2772 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2773 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2774 int pipe = intel_crtc->pipe;
5eddb70b 2775 u32 reg, temp;
79e53945 2776
c64e311e 2777
c98e9dcf 2778 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
627eb5a3
DV		 2781 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2782 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2783 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2784 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2785
2786 POSTING_READ(reg);
c98e9dcf
JB		 2787 udelay(200);
2788
2789 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp | FDI_PCDCLK);
2792
2793 POSTING_READ(reg);
c98e9dcf
JB		 2794 udelay(200);
2795
20749730
PZ		 2796 /* Enable CPU FDI TX PLL, always on for Ironlake */
2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2800 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2801
20749730
PZ		 2802 POSTING_READ(reg);
2803 udelay(100);
6be4a607 2804 }
0e23b99d
JB		 2805}
2806
88cefb6c
DV		 2807static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2808{
2809 struct drm_device *dev = intel_crtc->base.dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 int pipe = intel_crtc->pipe;
2812 u32 reg, temp;
2813
2814 /* Switch from PCDclk to Rawclk */
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2818
2819 /* Disable CPU FDI TX PLL */
2820 reg = FDI_TX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2823
2824 POSTING_READ(reg);
2825 udelay(100);
2826
2827 reg = FDI_RX_CTL(pipe);
2828 temp = I915_READ(reg);
2829 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2830
2831 /* Wait for the clocks to turn off. */
2832 POSTING_READ(reg);
2833 udelay(100);
2834}
2835
0fc932b8
JB		 2836static void ironlake_fdi_disable(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 int pipe = intel_crtc->pipe;
2842 u32 reg, temp;
2843
2844 /* disable CPU FDI tx and PCH FDI rx */
2845 reg = FDI_TX_CTL(pipe);
2846 temp = I915_READ(reg);
2847 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2848 POSTING_READ(reg);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 temp &= ~(0x7 << 16);
dfd07d72 2853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2854 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2855
2856 POSTING_READ(reg);
2857 udelay(100);
2858
2859 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2860 if (HAS_PCH_IBX(dev)) {
2861 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2862 }
0fc932b8
JB		 2863
2864 /* still set train pattern 1 */
2865 reg = FDI_TX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~FDI_LINK_TRAIN_NONE;
2868 temp |= FDI_LINK_TRAIN_PATTERN_1;
2869 I915_WRITE(reg, temp);
2870
2871 reg = FDI_RX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 if (HAS_PCH_CPT(dev)) {
2874 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2875 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2876 } else {
2877 temp &= ~FDI_LINK_TRAIN_NONE;
2878 temp |= FDI_LINK_TRAIN_PATTERN_1;
2879 }
2880 /* BPC in FDI rx is consistent with that in PIPECONF */
2881 temp &= ~(0x07 << 16);
dfd07d72 2882 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2883 I915_WRITE(reg, temp);
2884
2885 POSTING_READ(reg);
2886 udelay(100);
2887}
2888
5bb61643
CW		 2889static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2890{
2891 struct drm_device *dev = crtc->dev;
2892 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2894 unsigned long flags;
2895 bool pending;
2896
10d83730
VS		 2897 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2898 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2899 return false;
2900
2901 spin_lock_irqsave(&dev->event_lock, flags);
2902 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2903 spin_unlock_irqrestore(&dev->event_lock, flags);
2904
2905 return pending;
2906}
2907
e6c3a2a6
CW		 2908static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2909{
0f91128d 2910 struct drm_device *dev = crtc->dev;
5bb61643 2911 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2912
2913 if (crtc->fb == NULL)
2914 return;
2915
2c10d571
DV		 2916 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2917
5bb61643
CW		 2918 wait_event(dev_priv->pending_flip_queue,
2919 !intel_crtc_has_pending_flip(crtc));
2920
0f91128d
CW		 2921 mutex_lock(&dev->struct_mutex);
2922 intel_finish_fb(crtc->fb);
2923 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2924}
2925
e615efe4
ED		 2926/* Program iCLKIP clock to the desired frequency */
2927static void lpt_program_iclkip(struct drm_crtc *crtc)
2928{
2929 struct drm_device *dev = crtc->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2931 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2932 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2933 u32 temp;
2934
09153000
DV		 2935 mutex_lock(&dev_priv->dpio_lock);
2936
e615efe4
ED		 2937 /* It is necessary to ungate the pixclk gate prior to programming
2938 * the divisors, and gate it back when it is done.
2939 */
2940 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2941
2942 /* Disable SSCCTL */
2943 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2944 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2945 SBI_SSCCTL_DISABLE,
2946 SBI_ICLK);
e615efe4
ED		 2947
2948 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2949 if (clock == 20000) {
e615efe4
ED		 2950 auxdiv = 1;
2951 divsel = 0x41;
2952 phaseinc = 0x20;
2953 } else {
2954 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2955 * but the adjusted_mode->crtc_clock in in KHz. To get the
2956 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2957 * convert the virtual clock precision to KHz here for higher
2958 * precision.
2959 */
2960 u32 iclk_virtual_root_freq = 172800 * 1000;
2961 u32 iclk_pi_range = 64;
2962 u32 desired_divisor, msb_divisor_value, pi_value;
2963
12d7ceed 2964 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2965 msb_divisor_value = desired_divisor / iclk_pi_range;
2966 pi_value = desired_divisor % iclk_pi_range;
2967
2968 auxdiv = 0;
2969 divsel = msb_divisor_value - 2;
2970 phaseinc = pi_value;
2971 }
2972
2973 /* This should not happen with any sane values */
2974 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2975 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2976 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2977 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2978
2979 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2980 clock,
e615efe4
ED		 2981 auxdiv,
2982 divsel,
2983 phasedir,
2984 phaseinc);
2985
2986 /* Program SSCDIVINTPHASE6 */
988d6ee8 2987 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2988 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2989 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2990 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2991 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2992 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2993 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2994 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2995
2996 /* Program SSCAUXDIV */
988d6ee8 2997 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2998 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2999 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3000 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3001
3002 /* Enable modulator and associated divider */
988d6ee8 3003 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3004 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3005 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3006
3007 /* Wait for initialization time */
3008 udelay(24);
3009
3010 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3011
3012 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3013}
3014
275f01b2
DV		 3015static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3016 enum pipe pch_transcoder)
3017{
3018 struct drm_device *dev = crtc->base.dev;
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3021
3022 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3023 I915_READ(HTOTAL(cpu_transcoder)));
3024 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3025 I915_READ(HBLANK(cpu_transcoder)));
3026 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3027 I915_READ(HSYNC(cpu_transcoder)));
3028
3029 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3030 I915_READ(VTOTAL(cpu_transcoder)));
3031 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3032 I915_READ(VBLANK(cpu_transcoder)));
3033 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3034 I915_READ(VSYNC(cpu_transcoder)));
3035 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3036 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3037}
3038
f67a559d
JB		 3039/*
3040 * Enable PCH resources required for PCH ports:
3041 * - PCH PLLs
3042 * - FDI training & RX/TX
3043 * - update transcoder timings
3044 * - DP transcoding bits
3045 * - transcoder
3046 */
3047static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3048{
3049 struct drm_device *dev = crtc->dev;
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 int pipe = intel_crtc->pipe;
ee7b9f93 3053 u32 reg, temp;
2c07245f 3054
ab9412ba 3055 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3056
cd986abb
DV		 3057 /* Write the TU size bits before fdi link training, so that error
3058 * detection works. */
3059 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3060 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3061
c98e9dcf 3062 /* For PCH output, training FDI link */
674cf967 3063 dev_priv->display.fdi_link_train(crtc);
2c07245f 3064
3ad8a208
DV		 3065 /* We need to program the right clock selection before writing the pixel
3066 * mutliplier into the DPLL. */
303b81e0 3067 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3068 u32 sel;
4b645f14 3069
c98e9dcf 3070 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3071 temp |= TRANS_DPLL_ENABLE(pipe);
3072 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3073 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3074 temp |= sel;
3075 else
3076 temp &= ~sel;
c98e9dcf 3077 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3078 }
5eddb70b 3079
3ad8a208
DV		 3080 /* XXX: pch pll's can be enabled any time before we enable the PCH
3081 * transcoder, and we actually should do this to not upset any PCH
3082 * transcoder that already use the clock when we share it.
3083 *
3084 * Note that enable_shared_dpll tries to do the right thing, but
3085 * get_shared_dpll unconditionally resets the pll - we need that to have
3086 * the right LVDS enable sequence. */
3087 ironlake_enable_shared_dpll(intel_crtc);
3088
d9b6cb56
JB		 3089 /* set transcoder timing, panel must allow it */
3090 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3091 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3092
303b81e0 3093 intel_fdi_normal_train(crtc);
5e84e1a4 3094
c98e9dcf
JB		 3095 /* For PCH DP, enable TRANS_DP_CTL */
3096 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3097 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3098 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3099 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3100 reg = TRANS_DP_CTL(pipe);
3101 temp = I915_READ(reg);
3102 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3103 TRANS_DP_SYNC_MASK |
3104 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3105 temp |= (TRANS_DP_OUTPUT_ENABLE |
3106 TRANS_DP_ENH_FRAMING);
9325c9f0 3107 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3108
3109 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3110 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3111 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3112 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3113
3114 switch (intel_trans_dp_port_sel(crtc)) {
3115 case PCH_DP_B:
5eddb70b 3116 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3117 break;
3118 case PCH_DP_C:
5eddb70b 3119 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3120 break;
3121 case PCH_DP_D:
5eddb70b 3122 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3123 break;
3124 default:
e95d41e1 3125 BUG();
32f9d658 3126 }
2c07245f 3127
5eddb70b 3128 I915_WRITE(reg, temp);
6be4a607 3129 }
b52eb4dc 3130
b8a4f404 3131 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3132}
3133
1507e5bd
PZ		 3134static void lpt_pch_enable(struct drm_crtc *crtc)
3135{
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3139 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3140
ab9412ba 3141 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3142
8c52b5e8 3143 lpt_program_iclkip(crtc);
1507e5bd 3144
0540e488 3145 /* Set transcoder timing. */
275f01b2 3146 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3147
937bb610 3148 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3149}
3150
e2b78267 3151static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3152{
e2b78267 3153 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3154
3155 if (pll == NULL)
3156 return;
3157
3158 if (pll->refcount == 0) {
46edb027 3159 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3160 return;
3161 }
3162
f4a091c7
DV		 3163 if (--pll->refcount == 0) {
3164 WARN_ON(pll->on);
3165 WARN_ON(pll->active);
3166 }
3167
a43f6e0f 3168 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3169}
3170
b89a1d39 3171static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3172{
e2b78267
DV		 3173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3174 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3175 enum intel_dpll_id i;
ee7b9f93 3176
ee7b9f93 3177 if (pll) {
46edb027
DV		 3178 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3179 crtc->base.base.id, pll->name);
e2b78267 3180 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3181 }
3182
98b6bd99
DV		 3183 if (HAS_PCH_IBX(dev_priv->dev)) {
3184 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3185 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3186 pll = &dev_priv->shared_dplls[i];
98b6bd99 3187
46edb027
DV		 3188 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3189 crtc->base.base.id, pll->name);
98b6bd99
DV		 3190
3191 goto found;
3192 }
3193
e72f9fbf
DV		 3194 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3195 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3196
3197 /* Only want to check enabled timings first */
3198 if (pll->refcount == 0)
3199 continue;
3200
b89a1d39
DV		 3201 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3202 sizeof(pll->hw_state)) == 0) {
46edb027 3203 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3204 crtc->base.base.id,
46edb027 3205 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3206
3207 goto found;
3208 }
3209 }
3210
3211 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3212 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3213 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3214 if (pll->refcount == 0) {
46edb027
DV		 3215 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3216 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3217 goto found;
3218 }
3219 }
3220
3221 return NULL;
3222
3223found:
a43f6e0f 3224 crtc->config.shared_dpll = i;
46edb027
DV		 3225 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3226 pipe_name(crtc->pipe));
ee7b9f93 3227
cdbd2316 3228 if (pll->active == 0) {
66e985c0
DV		 3229 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3230 sizeof(pll->hw_state));
3231
46edb027 3232 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3233 WARN_ON(pll->on);
e9d6944e 3234 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3235
15bdd4cf 3236 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3237 }
3238 pll->refcount++;
e04c7350 3239
ee7b9f93
JB		 3240 return pll;
3241}
3242
a1520318 3243static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3244{
3245 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3246 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3247 u32 temp;
3248
3249 temp = I915_READ(dslreg);
3250 udelay(500);
3251 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3252 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3253 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3254 }
3255}
3256
b074cec8
JB		 3257static void ironlake_pfit_enable(struct intel_crtc *crtc)
3258{
3259 struct drm_device *dev = crtc->base.dev;
3260 struct drm_i915_private *dev_priv = dev->dev_private;
3261 int pipe = crtc->pipe;
3262
fd4daa9c 3263 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3264 /* Force use of hard-coded filter coefficients
3265 * as some pre-programmed values are broken,
3266 * e.g. x201.
3267 */
3268 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3269 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3270 PF_PIPE_SEL_IVB(pipe));
3271 else
3272 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3273 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3274 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3275 }
3276}
3277
bb53d4ae
VS		 3278static void intel_enable_planes(struct drm_crtc *crtc)
3279{
3280 struct drm_device *dev = crtc->dev;
3281 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3282 struct intel_plane *intel_plane;
3283
3284 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3285 if (intel_plane->pipe == pipe)
3286 intel_plane_restore(&intel_plane->base);
3287}
3288
3289static void intel_disable_planes(struct drm_crtc *crtc)
3290{
3291 struct drm_device *dev = crtc->dev;
3292 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3293 struct intel_plane *intel_plane;
3294
3295 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3296 if (intel_plane->pipe == pipe)
3297 intel_plane_disable(&intel_plane->base);
3298}
3299
d77e4531
PZ		 3300static void hsw_enable_ips(struct intel_crtc *crtc)
3301{
3302 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3303
3304 if (!crtc->config.ips_enabled)
3305 return;
3306
3307 /* We can only enable IPS after we enable a plane and wait for a vblank.
3308 * We guarantee that the plane is enabled by calling intel_enable_ips
3309 * only after intel_enable_plane. And intel_enable_plane already waits
3310 * for a vblank, so all we need to do here is to enable the IPS bit. */
3311 assert_plane_enabled(dev_priv, crtc->plane);
3312 I915_WRITE(IPS_CTL, IPS_ENABLE);
3313}
3314
3315static void hsw_disable_ips(struct intel_crtc *crtc)
3316{
3317 struct drm_device *dev = crtc->base.dev;
3318 struct drm_i915_private *dev_priv = dev->dev_private;
3319
3320 if (!crtc->config.ips_enabled)
3321 return;
3322
3323 assert_plane_enabled(dev_priv, crtc->plane);
3324 I915_WRITE(IPS_CTL, 0);
3325 POSTING_READ(IPS_CTL);
3326
3327 /* We need to wait for a vblank before we can disable the plane. */
3328 intel_wait_for_vblank(dev, crtc->pipe);
3329}
3330
3331/** Loads the palette/gamma unit for the CRTC with the prepared values */
3332static void intel_crtc_load_lut(struct drm_crtc *crtc)
3333{
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 enum pipe pipe = intel_crtc->pipe;
3338 int palreg = PALETTE(pipe);
3339 int i;
3340 bool reenable_ips = false;
3341
3342 /* The clocks have to be on to load the palette. */
3343 if (!crtc->enabled || !intel_crtc->active)
3344 return;
3345
3346 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3347 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3348 assert_dsi_pll_enabled(dev_priv);
3349 else
3350 assert_pll_enabled(dev_priv, pipe);
3351 }
3352
3353 /* use legacy palette for Ironlake */
3354 if (HAS_PCH_SPLIT(dev))
3355 palreg = LGC_PALETTE(pipe);
3356
3357 /* Workaround : Do not read or write the pipe palette/gamma data while
3358 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3359 */
3360 if (intel_crtc->config.ips_enabled &&
3361 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3362 GAMMA_MODE_MODE_SPLIT)) {
3363 hsw_disable_ips(intel_crtc);
3364 reenable_ips = true;
3365 }
3366
3367 for (i = 0; i < 256; i++) {
3368 I915_WRITE(palreg + 4 * i,
3369 (intel_crtc->lut_r[i] << 16) |
3370 (intel_crtc->lut_g[i] << 8) |
3371 intel_crtc->lut_b[i]);
3372 }
3373
3374 if (reenable_ips)
3375 hsw_enable_ips(intel_crtc);
3376}
3377
f67a559d
JB		 3378static void ironlake_crtc_enable(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3383 struct intel_encoder *encoder;
f67a559d
JB		 3384 int pipe = intel_crtc->pipe;
3385 int plane = intel_crtc->plane;
f67a559d 3386
08a48469
DV		 3387 WARN_ON(!crtc->enabled);
3388
f67a559d
JB		 3389 if (intel_crtc->active)
3390 return;
3391
3392 intel_crtc->active = true;
8664281b
PZ		 3393
3394 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3395 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3396
f6736a1a 3397 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3398 if (encoder->pre_enable)
3399 encoder->pre_enable(encoder);
f67a559d 3400
5bfe2ac0 3401 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3402 /* Note: FDI PLL enabling _must_ be done before we enable the
3403 * cpu pipes, hence this is separate from all the other fdi/pch
3404 * enabling. */
88cefb6c 3405 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3406 } else {
3407 assert_fdi_tx_disabled(dev_priv, pipe);
3408 assert_fdi_rx_disabled(dev_priv, pipe);
3409 }
f67a559d 3410
b074cec8 3411 ironlake_pfit_enable(intel_crtc);
f67a559d 3412
9c54c0dd
JB		 3413 /*
3414 * On ILK+ LUT must be loaded before the pipe is running but with
3415 * clocks enabled
3416 */
3417 intel_crtc_load_lut(crtc);
3418
f37fcc2a 3419 intel_update_watermarks(crtc);
5bfe2ac0 3420 intel_enable_pipe(dev_priv, pipe,
23538ef1 3421 intel_crtc->config.has_pch_encoder, false);
f67a559d 3422 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3423 intel_enable_planes(crtc);
5c38d48c 3424 intel_crtc_update_cursor(crtc, true);
f67a559d 3425
5bfe2ac0 3426 if (intel_crtc->config.has_pch_encoder)
f67a559d 3427 ironlake_pch_enable(crtc);
c98e9dcf 3428
d1ebd816 3429 mutex_lock(&dev->struct_mutex);
bed4a673 3430 intel_update_fbc(dev);
d1ebd816
BW		 3431 mutex_unlock(&dev->struct_mutex);
3432
fa5c73b1
DV		 3433 for_each_encoder_on_crtc(dev, crtc, encoder)
3434 encoder->enable(encoder);
61b77ddd
DV		 3435
3436 if (HAS_PCH_CPT(dev))
a1520318 3437 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3438
3439 /*
3440 * There seems to be a race in PCH platform hw (at least on some
3441 * outputs) where an enabled pipe still completes any pageflip right
3442 * away (as if the pipe is off) instead of waiting for vblank. As soon
3443 * as the first vblank happend, everything works as expected. Hence just
3444 * wait for one vblank before returning to avoid strange things
3445 * happening.
3446 */
3447 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3448}
3449
42db64ef
PZ		 3450/* IPS only exists on ULT machines and is tied to pipe A. */
3451static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3452{
f5adf94e 3453 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3454}
3455
dda9a66a
VS		 3456static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3457{
3458 struct drm_device *dev = crtc->dev;
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461 int pipe = intel_crtc->pipe;
3462 int plane = intel_crtc->plane;
3463
3464 intel_enable_plane(dev_priv, plane, pipe);
3465 intel_enable_planes(crtc);
3466 intel_crtc_update_cursor(crtc, true);
3467
3468 hsw_enable_ips(intel_crtc);
3469
3470 mutex_lock(&dev->struct_mutex);
3471 intel_update_fbc(dev);
3472 mutex_unlock(&dev->struct_mutex);
3473}
3474
3475static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3476{
3477 struct drm_device *dev = crtc->dev;
3478 struct drm_i915_private *dev_priv = dev->dev_private;
3479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3480 int pipe = intel_crtc->pipe;
3481 int plane = intel_crtc->plane;
3482
3483 intel_crtc_wait_for_pending_flips(crtc);
3484 drm_vblank_off(dev, pipe);
3485
3486 /* FBC must be disabled before disabling the plane on HSW. */
3487 if (dev_priv->fbc.plane == plane)
3488 intel_disable_fbc(dev);
3489
3490 hsw_disable_ips(intel_crtc);
3491
3492 intel_crtc_update_cursor(crtc, false);
3493 intel_disable_planes(crtc);
3494 intel_disable_plane(dev_priv, plane, pipe);
3495}
3496
4f771f10
PZ		 3497static void haswell_crtc_enable(struct drm_crtc *crtc)
3498{
3499 struct drm_device *dev = crtc->dev;
3500 struct drm_i915_private *dev_priv = dev->dev_private;
3501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3502 struct intel_encoder *encoder;
3503 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3504
3505 WARN_ON(!crtc->enabled);
3506
3507 if (intel_crtc->active)
3508 return;
3509
3510 intel_crtc->active = true;
8664281b
PZ		 3511
3512 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3513 if (intel_crtc->config.has_pch_encoder)
3514 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3515
5bfe2ac0 3516 if (intel_crtc->config.has_pch_encoder)
04945641 3517 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3518
3519 for_each_encoder_on_crtc(dev, crtc, encoder)
3520 if (encoder->pre_enable)
3521 encoder->pre_enable(encoder);
3522
1f544388 3523 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3524
b074cec8 3525 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3526
3527 /*
3528 * On ILK+ LUT must be loaded before the pipe is running but with
3529 * clocks enabled
3530 */
3531 intel_crtc_load_lut(crtc);
3532
1f544388 3533 intel_ddi_set_pipe_settings(crtc);
8228c251 3534 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3535
f37fcc2a 3536 intel_update_watermarks(crtc);
5bfe2ac0 3537 intel_enable_pipe(dev_priv, pipe,
23538ef1 3538 intel_crtc->config.has_pch_encoder, false);
42db64ef 3539
5bfe2ac0 3540 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3541 lpt_pch_enable(crtc);
4f771f10 3542
8807e55b 3543 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3544 encoder->enable(encoder);
8807e55b
JN		 3545 intel_opregion_notify_encoder(encoder, true);
3546 }
4f771f10 3547
dda9a66a
VS		 3548 haswell_crtc_enable_planes(crtc);
3549
4f771f10
PZ		 3550 /*
3551 * There seems to be a race in PCH platform hw (at least on some
3552 * outputs) where an enabled pipe still completes any pageflip right
3553 * away (as if the pipe is off) instead of waiting for vblank. As soon
3554 * as the first vblank happend, everything works as expected. Hence just
3555 * wait for one vblank before returning to avoid strange things
3556 * happening.
3557 */
3558 intel_wait_for_vblank(dev, intel_crtc->pipe);
3559}
3560
3f8dce3a
DV		 3561static void ironlake_pfit_disable(struct intel_crtc *crtc)
3562{
3563 struct drm_device *dev = crtc->base.dev;
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 int pipe = crtc->pipe;
3566
3567 /* To avoid upsetting the power well on haswell only disable the pfit if
3568 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3569 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3570 I915_WRITE(PF_CTL(pipe), 0);
3571 I915_WRITE(PF_WIN_POS(pipe), 0);
3572 I915_WRITE(PF_WIN_SZ(pipe), 0);
3573 }
3574}
3575
6be4a607
JB		 3576static void ironlake_crtc_disable(struct drm_crtc *crtc)
3577{
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3581 struct intel_encoder *encoder;
6be4a607
JB		 3582 int pipe = intel_crtc->pipe;
3583 int plane = intel_crtc->plane;
5eddb70b 3584 u32 reg, temp;
b52eb4dc 3585
ef9c3aee 3586
f7abfe8b
CW		 3587 if (!intel_crtc->active)
3588 return;
3589
ea9d758d
DV		 3590 for_each_encoder_on_crtc(dev, crtc, encoder)
3591 encoder->disable(encoder);
3592
e6c3a2a6 3593 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3594 drm_vblank_off(dev, pipe);
913d8d11 3595
5c3fe8b0 3596 if (dev_priv->fbc.plane == plane)
973d04f9 3597 intel_disable_fbc(dev);
2c07245f 3598
0d5b8c61 3599 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3600 intel_disable_planes(crtc);
0d5b8c61
VS		 3601 intel_disable_plane(dev_priv, plane, pipe);
3602
d925c59a
DV		 3603 if (intel_crtc->config.has_pch_encoder)
3604 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3605
b24e7179 3606 intel_disable_pipe(dev_priv, pipe);
32f9d658 3607
3f8dce3a 3608 ironlake_pfit_disable(intel_crtc);
2c07245f 3609
bf49ec8c
DV		 3610 for_each_encoder_on_crtc(dev, crtc, encoder)
3611 if (encoder->post_disable)
3612 encoder->post_disable(encoder);
2c07245f 3613
d925c59a
DV		 3614 if (intel_crtc->config.has_pch_encoder) {
3615 ironlake_fdi_disable(crtc);
913d8d11 3616
d925c59a
DV		 3617 ironlake_disable_pch_transcoder(dev_priv, pipe);
3618 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3619
d925c59a
DV		 3620 if (HAS_PCH_CPT(dev)) {
3621 /* disable TRANS_DP_CTL */
3622 reg = TRANS_DP_CTL(pipe);
3623 temp = I915_READ(reg);
3624 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3625 TRANS_DP_PORT_SEL_MASK);
3626 temp |= TRANS_DP_PORT_SEL_NONE;
3627 I915_WRITE(reg, temp);
3628
3629 /* disable DPLL_SEL */
3630 temp = I915_READ(PCH_DPLL_SEL);
11887397 3631 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3632 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3633 }
e3421a18 3634
d925c59a 3635 /* disable PCH DPLL */
e72f9fbf 3636 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3637
d925c59a
DV		 3638 ironlake_fdi_pll_disable(intel_crtc);
3639 }
6b383a7f 3640
f7abfe8b 3641 intel_crtc->active = false;
46ba614c 3642 intel_update_watermarks(crtc);
d1ebd816
BW		 3643
3644 mutex_lock(&dev->struct_mutex);
6b383a7f 3645 intel_update_fbc(dev);
d1ebd816 3646 mutex_unlock(&dev->struct_mutex);
6be4a607 3647}
1b3c7a47 3648
4f771f10 3649static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3650{
4f771f10
PZ		 3651 struct drm_device *dev = crtc->dev;
3652 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3654 struct intel_encoder *encoder;
3655 int pipe = intel_crtc->pipe;
3b117c8f 3656 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3657
4f771f10
PZ		 3658 if (!intel_crtc->active)
3659 return;
3660
dda9a66a
VS		 3661 haswell_crtc_disable_planes(crtc);
3662
8807e55b
JN		 3663 for_each_encoder_on_crtc(dev, crtc, encoder) {
3664 intel_opregion_notify_encoder(encoder, false);
4f771f10 3665 encoder->disable(encoder);
8807e55b 3666 }
4f771f10 3667
8664281b
PZ		 3668 if (intel_crtc->config.has_pch_encoder)
3669 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3670 intel_disable_pipe(dev_priv, pipe);
3671
ad80a810 3672 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3673
3f8dce3a 3674 ironlake_pfit_disable(intel_crtc);
4f771f10 3675
1f544388 3676 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3677
3678 for_each_encoder_on_crtc(dev, crtc, encoder)
3679 if (encoder->post_disable)
3680 encoder->post_disable(encoder);
3681
88adfff1 3682 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3683 lpt_disable_pch_transcoder(dev_priv);
8664281b 3684 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3685 intel_ddi_fdi_disable(crtc);
83616634 3686 }
4f771f10
PZ		 3687
3688 intel_crtc->active = false;
46ba614c 3689 intel_update_watermarks(crtc);
4f771f10
PZ		 3690
3691 mutex_lock(&dev->struct_mutex);
3692 intel_update_fbc(dev);
3693 mutex_unlock(&dev->struct_mutex);
3694}
3695
ee7b9f93
JB		 3696static void ironlake_crtc_off(struct drm_crtc *crtc)
3697{
3698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3699 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3700}
3701
6441ab5f
PZ		 3702static void haswell_crtc_off(struct drm_crtc *crtc)
3703{
3704 intel_ddi_put_crtc_pll(crtc);
3705}
3706
02e792fb
DV		 3707static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3708{
02e792fb 3709 if (!enable && intel_crtc->overlay) {
23f09ce3 3710 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3711 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3712
23f09ce3 3713 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3714 dev_priv->mm.interruptible = false;
3715 (void) intel_overlay_switch_off(intel_crtc->overlay);
3716 dev_priv->mm.interruptible = true;
23f09ce3 3717 mutex_unlock(&dev->struct_mutex);
02e792fb 3718 }
02e792fb 3719
5dcdbcb0
CW		 3720 /* Let userspace switch the overlay on again. In most cases userspace
3721 * has to recompute where to put it anyway.
3722 */
02e792fb
DV		 3723}
3724
61bc95c1
EE		 3725/**
3726 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3727 * cursor plane briefly if not already running after enabling the display
3728 * plane.
3729 * This workaround avoids occasional blank screens when self refresh is
3730 * enabled.
3731 */
3732static void
3733g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3734{
3735 u32 cntl = I915_READ(CURCNTR(pipe));
3736
3737 if ((cntl & CURSOR_MODE) == 0) {
3738 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3739
3740 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3741 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3742 intel_wait_for_vblank(dev_priv->dev, pipe);
3743 I915_WRITE(CURCNTR(pipe), cntl);
3744 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3745 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3746 }
3747}
3748
2dd24552
JB		 3749static void i9xx_pfit_enable(struct intel_crtc *crtc)
3750{
3751 struct drm_device *dev = crtc->base.dev;
3752 struct drm_i915_private *dev_priv = dev->dev_private;
3753 struct intel_crtc_config *pipe_config = &crtc->config;
3754
328d8e82 3755 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3756 return;
3757
2dd24552 3758 /*
c0b03411
DV		 3759 * The panel fitter should only be adjusted whilst the pipe is disabled,
3760 * according to register description and PRM.
2dd24552 3761 */
c0b03411
DV		 3762 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3763 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3764
b074cec8
JB		 3765 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3766 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3767
3768 /* Border color in case we don't scale up to the full screen. Black by
3769 * default, change to something else for debugging. */
3770 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3771}
3772
89b667f8
JB		 3773static void valleyview_crtc_enable(struct drm_crtc *crtc)
3774{
3775 struct drm_device *dev = crtc->dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3778 struct intel_encoder *encoder;
3779 int pipe = intel_crtc->pipe;
3780 int plane = intel_crtc->plane;
23538ef1 3781 bool is_dsi;
89b667f8
JB		 3782
3783 WARN_ON(!crtc->enabled);
3784
3785 if (intel_crtc->active)
3786 return;
3787
3788 intel_crtc->active = true;
89b667f8 3789
89b667f8
JB		 3790 for_each_encoder_on_crtc(dev, crtc, encoder)
3791 if (encoder->pre_pll_enable)
3792 encoder->pre_pll_enable(encoder);
3793
23538ef1
JN		 3794 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3795
e9fd1c02
JN		 3796 if (!is_dsi)
3797 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3798
3799 for_each_encoder_on_crtc(dev, crtc, encoder)
3800 if (encoder->pre_enable)
3801 encoder->pre_enable(encoder);
3802
2dd24552
JB		 3803 i9xx_pfit_enable(intel_crtc);
3804
63cbb074
VS		 3805 intel_crtc_load_lut(crtc);
3806
f37fcc2a 3807 intel_update_watermarks(crtc);
23538ef1 3808 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3809 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3810 intel_enable_planes(crtc);
5c38d48c 3811 intel_crtc_update_cursor(crtc, true);
89b667f8 3812
89b667f8 3813 intel_update_fbc(dev);
5004945f
JN		 3814
3815 for_each_encoder_on_crtc(dev, crtc, encoder)
3816 encoder->enable(encoder);
89b667f8
JB		 3817}
3818
0b8765c6 3819static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3820{
3821 struct drm_device *dev = crtc->dev;
79e53945
JB		 3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3824 struct intel_encoder *encoder;
79e53945 3825 int pipe = intel_crtc->pipe;
80824003 3826 int plane = intel_crtc->plane;
79e53945 3827
08a48469
DV		 3828 WARN_ON(!crtc->enabled);
3829
f7abfe8b
CW		 3830 if (intel_crtc->active)
3831 return;
3832
3833 intel_crtc->active = true;
6b383a7f 3834
9d6d9f19
MK		 3835 for_each_encoder_on_crtc(dev, crtc, encoder)
3836 if (encoder->pre_enable)
3837 encoder->pre_enable(encoder);
3838
f6736a1a
DV		 3839 i9xx_enable_pll(intel_crtc);
3840
2dd24552
JB		 3841 i9xx_pfit_enable(intel_crtc);
3842
63cbb074
VS		 3843 intel_crtc_load_lut(crtc);
3844
f37fcc2a 3845 intel_update_watermarks(crtc);
23538ef1 3846 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3847 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3848 intel_enable_planes(crtc);
22e407d7 3849 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3850 if (IS_G4X(dev))
3851 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3852 intel_crtc_update_cursor(crtc, true);
79e53945 3853
0b8765c6
JB		 3854 /* Give the overlay scaler a chance to enable if it's on this pipe */
3855 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3856
f440eb13 3857 intel_update_fbc(dev);
ef9c3aee 3858
fa5c73b1
DV		 3859 for_each_encoder_on_crtc(dev, crtc, encoder)
3860 encoder->enable(encoder);
0b8765c6 3861}
79e53945 3862
87476d63
DV		 3863static void i9xx_pfit_disable(struct intel_crtc *crtc)
3864{
3865 struct drm_device *dev = crtc->base.dev;
3866 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3867
328d8e82
DV		 3868 if (!crtc->config.gmch_pfit.control)
3869 return;
87476d63 3870
328d8e82 3871 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3872
328d8e82
DV		 3873 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3874 I915_READ(PFIT_CONTROL));
3875 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3876}
3877
0b8765c6
JB		 3878static void i9xx_crtc_disable(struct drm_crtc *crtc)
3879{
3880 struct drm_device *dev = crtc->dev;
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3883 struct intel_encoder *encoder;
0b8765c6
JB		 3884 int pipe = intel_crtc->pipe;
3885 int plane = intel_crtc->plane;
ef9c3aee 3886
f7abfe8b
CW		 3887 if (!intel_crtc->active)
3888 return;
3889
ea9d758d
DV		 3890 for_each_encoder_on_crtc(dev, crtc, encoder)
3891 encoder->disable(encoder);
3892
0b8765c6 3893 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3894 intel_crtc_wait_for_pending_flips(crtc);
3895 drm_vblank_off(dev, pipe);
0b8765c6 3896
5c3fe8b0 3897 if (dev_priv->fbc.plane == plane)
973d04f9 3898 intel_disable_fbc(dev);
79e53945 3899
0d5b8c61
VS		 3900 intel_crtc_dpms_overlay(intel_crtc, false);
3901 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3902 intel_disable_planes(crtc);
b24e7179 3903 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3904
b24e7179 3905 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3906
87476d63 3907 i9xx_pfit_disable(intel_crtc);
24a1f16d 3908
89b667f8
JB		 3909 for_each_encoder_on_crtc(dev, crtc, encoder)
3910 if (encoder->post_disable)
3911 encoder->post_disable(encoder);
3912
f6071166
JB		 3913 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3914 vlv_disable_pll(dev_priv, pipe);
3915 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3916 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3917
f7abfe8b 3918 intel_crtc->active = false;
46ba614c 3919 intel_update_watermarks(crtc);
f37fcc2a 3920
6b383a7f 3921 intel_update_fbc(dev);
0b8765c6
JB		 3922}
3923
ee7b9f93
JB		 3924static void i9xx_crtc_off(struct drm_crtc *crtc)
3925{
3926}
3927
976f8a20
DV		 3928static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3929 bool enabled)
2c07245f
ZW		 3930{
3931 struct drm_device *dev = crtc->dev;
3932 struct drm_i915_master_private *master_priv;
3933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3934 int pipe = intel_crtc->pipe;
79e53945
JB		 3935
3936 if (!dev->primary->master)
3937 return;
3938
3939 master_priv = dev->primary->master->driver_priv;
3940 if (!master_priv->sarea_priv)
3941 return;
3942
79e53945
JB		 3943 switch (pipe) {
3944 case 0:
3945 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3946 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3947 break;
3948 case 1:
3949 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3950 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3951 break;
3952 default:
9db4a9c7 3953 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3954 break;
3955 }
79e53945
JB		 3956}
3957
976f8a20
DV		 3958/**
3959 * Sets the power management mode of the pipe and plane.
3960 */
3961void intel_crtc_update_dpms(struct drm_crtc *crtc)
3962{
3963 struct drm_device *dev = crtc->dev;
3964 struct drm_i915_private *dev_priv = dev->dev_private;
3965 struct intel_encoder *intel_encoder;
3966 bool enable = false;
3967
3968 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3969 enable |= intel_encoder->connectors_active;
3970
3971 if (enable)
3972 dev_priv->display.crtc_enable(crtc);
3973 else
3974 dev_priv->display.crtc_disable(crtc);
3975
3976 intel_crtc_update_sarea(crtc, enable);
3977}
3978
cdd59983
CW		 3979static void intel_crtc_disable(struct drm_crtc *crtc)
3980{
cdd59983 3981 struct drm_device *dev = crtc->dev;
976f8a20 3982 struct drm_connector *connector;
ee7b9f93 3983 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3985
976f8a20
DV		 3986 /* crtc should still be enabled when we disable it. */
3987 WARN_ON(!crtc->enabled);
3988
3989 dev_priv->display.crtc_disable(crtc);
c77bf565 3990 intel_crtc->eld_vld = false;
976f8a20 3991 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3992 dev_priv->display.off(crtc);
3993
931872fc 3994 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3995 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3996 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3997
3998 if (crtc->fb) {
3999 mutex_lock(&dev->struct_mutex);
1690e1eb 4000 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4001 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4002 crtc->fb = NULL;
4003 }
4004
4005 /* Update computed state. */
4006 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4007 if (!connector->encoder || !connector->encoder->crtc)
4008 continue;
4009
4010 if (connector->encoder->crtc != crtc)
4011 continue;
4012
4013 connector->dpms = DRM_MODE_DPMS_OFF;
4014 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4015 }
4016}
4017
ea5b213a 4018void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4019{
4ef69c7a 4020 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4021
ea5b213a
CW		 4022 drm_encoder_cleanup(encoder);
4023 kfree(intel_encoder);
7e7d76c3
JB		 4024}
4025
9237329d 4026/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4027 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4028 * state of the entire output pipe. */
9237329d 4029static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4030{
5ab432ef
DV		 4031 if (mode == DRM_MODE_DPMS_ON) {
4032 encoder->connectors_active = true;
4033
b2cabb0e 4034 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4035 } else {
4036 encoder->connectors_active = false;
4037
b2cabb0e 4038 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4039 }
79e53945
JB		 4040}
4041
0a91ca29
DV		 4042/* Cross check the actual hw state with our own modeset state tracking (and it's
4043 * internal consistency). */
b980514c 4044static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4045{
0a91ca29
DV		 4046 if (connector->get_hw_state(connector)) {
4047 struct intel_encoder *encoder = connector->encoder;
4048 struct drm_crtc *crtc;
4049 bool encoder_enabled;
4050 enum pipe pipe;
4051
4052 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4053 connector->base.base.id,
4054 drm_get_connector_name(&connector->base));
4055
4056 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4057 "wrong connector dpms state\n");
4058 WARN(connector->base.encoder != &encoder->base,
4059 "active connector not linked to encoder\n");
4060 WARN(!encoder->connectors_active,
4061 "encoder->connectors_active not set\n");
4062
4063 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4064 WARN(!encoder_enabled, "encoder not enabled\n");
4065 if (WARN_ON(!encoder->base.crtc))
4066 return;
4067
4068 crtc = encoder->base.crtc;
4069
4070 WARN(!crtc->enabled, "crtc not enabled\n");
4071 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4072 WARN(pipe != to_intel_crtc(crtc)->pipe,
4073 "encoder active on the wrong pipe\n");
4074 }
79e53945
JB		 4075}
4076
5ab432ef
DV		 4077/* Even simpler default implementation, if there's really no special case to
4078 * consider. */
4079void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4080{
5ab432ef 4081 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4082
5ab432ef
DV		 4083 /* All the simple cases only support two dpms states. */
4084 if (mode != DRM_MODE_DPMS_ON)
4085 mode = DRM_MODE_DPMS_OFF;
d4270e57 4086
5ab432ef
DV		 4087 if (mode == connector->dpms)
4088 return;
4089
4090 connector->dpms = mode;
4091
4092 /* Only need to change hw state when actually enabled */
4093 if (encoder->base.crtc)
4094 intel_encoder_dpms(encoder, mode);
4095 else
8af6cf88 4096 WARN_ON(encoder->connectors_active != false);
0a91ca29 4097
b980514c 4098 intel_modeset_check_state(connector->dev);
79e53945
JB		 4099}
4100
f0947c37
DV		 4101/* Simple connector->get_hw_state implementation for encoders that support only
4102 * one connector and no cloning and hence the encoder state determines the state
4103 * of the connector. */
4104bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4105{
24929352 4106 enum pipe pipe = 0;
f0947c37 4107 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4108
f0947c37 4109 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4110}
4111
1857e1da
DV		 4112static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4113 struct intel_crtc_config *pipe_config)
4114{
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 struct intel_crtc *pipe_B_crtc =
4117 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4118
4119 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4120 pipe_name(pipe), pipe_config->fdi_lanes);
4121 if (pipe_config->fdi_lanes > 4) {
4122 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4123 pipe_name(pipe), pipe_config->fdi_lanes);
4124 return false;
4125 }
4126
4127 if (IS_HASWELL(dev)) {
4128 if (pipe_config->fdi_lanes > 2) {
4129 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4130 pipe_config->fdi_lanes);
4131 return false;
4132 } else {
4133 return true;
4134 }
4135 }
4136
4137 if (INTEL_INFO(dev)->num_pipes == 2)
4138 return true;
4139
4140 /* Ivybridge 3 pipe is really complicated */
4141 switch (pipe) {
4142 case PIPE_A:
4143 return true;
4144 case PIPE_B:
4145 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4146 pipe_config->fdi_lanes > 2) {
4147 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4148 pipe_name(pipe), pipe_config->fdi_lanes);
4149 return false;
4150 }
4151 return true;
4152 case PIPE_C:
1e833f40 4153 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4154 pipe_B_crtc->config.fdi_lanes <= 2) {
4155 if (pipe_config->fdi_lanes > 2) {
4156 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4157 pipe_name(pipe), pipe_config->fdi_lanes);
4158 return false;
4159 }
4160 } else {
4161 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4162 return false;
4163 }
4164 return true;
4165 default:
4166 BUG();
4167 }
4168}
4169
e29c22c0
DV		 4170#define RETRY 1
4171static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4172 struct intel_crtc_config *pipe_config)
877d48d5 4173{
1857e1da 4174 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4175 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4176 int lane, link_bw, fdi_dotclock;
e29c22c0 4177 bool setup_ok, needs_recompute = false;
877d48d5 4178
e29c22c0 4179retry:
877d48d5
DV		 4180 /* FDI is a binary signal running at ~2.7GHz, encoding
4181 * each output octet as 10 bits. The actual frequency
4182 * is stored as a divider into a 100MHz clock, and the
4183 * mode pixel clock is stored in units of 1KHz.
4184 * Hence the bw of each lane in terms of the mode signal
4185 * is:
4186 */
4187 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4188
241bfc38 4189 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4190
2bd89a07 4191 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4192 pipe_config->pipe_bpp);
4193
4194 pipe_config->fdi_lanes = lane;
4195
2bd89a07 4196 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4197 link_bw, &pipe_config->fdi_m_n);
1857e1da 4198
e29c22c0
DV		 4199 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4200 intel_crtc->pipe, pipe_config);
4201 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4202 pipe_config->pipe_bpp -= 2*3;
4203 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4204 pipe_config->pipe_bpp);
4205 needs_recompute = true;
4206 pipe_config->bw_constrained = true;
4207
4208 goto retry;
4209 }
4210
4211 if (needs_recompute)
4212 return RETRY;
4213
4214 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4215}
4216
42db64ef
PZ		 4217static void hsw_compute_ips_config(struct intel_crtc *crtc,
4218 struct intel_crtc_config *pipe_config)
4219{
3c4ca58c
PZ		 4220 pipe_config->ips_enabled = i915_enable_ips &&
4221 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4222 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4223}
4224
a43f6e0f 4225static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4226 struct intel_crtc_config *pipe_config)
79e53945 4227{
a43f6e0f 4228 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4229 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4230
ad3a4479 4231 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4232 if (INTEL_INFO(dev)->gen < 4) {
4233 struct drm_i915_private *dev_priv = dev->dev_private;
4234 int clock_limit =
4235 dev_priv->display.get_display_clock_speed(dev);
4236
4237 /*
4238 * Enable pixel doubling when the dot clock
4239 * is > 90% of the (display) core speed.
4240 *
b397c96b
VS		 4241 * GDG double wide on either pipe,
4242 * otherwise pipe A only.
cf532bb2 4243 */
b397c96b 4244 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4245 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4246 clock_limit *= 2;
cf532bb2 4247 pipe_config->double_wide = true;
ad3a4479
VS		 4248 }
4249
241bfc38 4250 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4251 return -EINVAL;
2c07245f 4252 }
89749350 4253
1d1d0e27
VS		 4254 /*
4255 * Pipe horizontal size must be even in:
4256 * - DVO ganged mode
4257 * - LVDS dual channel mode
4258 * - Double wide pipe
4259 */
4260 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4261 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4262 pipe_config->pipe_src_w &= ~1;
4263
8693a824
DL		 4264 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4265 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4266 */
4267 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4268 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4269 return -EINVAL;
44f46b42 4270
bd080ee5 4271 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4272 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4273 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4274 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4275 * for lvds. */
4276 pipe_config->pipe_bpp = 8*3;
4277 }
4278
f5adf94e 4279 if (HAS_IPS(dev))
a43f6e0f
DV		 4280 hsw_compute_ips_config(crtc, pipe_config);
4281
4282 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4283 * clock survives for now. */
4284 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4285 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4286
877d48d5 4287 if (pipe_config->has_pch_encoder)
a43f6e0f 4288 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4289
e29c22c0 4290 return 0;
79e53945
JB		 4291}
4292
25eb05fc
JB		 4293static int valleyview_get_display_clock_speed(struct drm_device *dev)
4294{
4295 return 400000; /* FIXME */
4296}
4297
e70236a8
JB		 4298static int i945_get_display_clock_speed(struct drm_device *dev)
4299{
4300 return 400000;
4301}
79e53945 4302
e70236a8 4303static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4304{
e70236a8
JB		 4305 return 333000;
4306}
79e53945 4307
e70236a8
JB		 4308static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4309{
4310 return 200000;
4311}
79e53945 4312
257a7ffc
DV		 4313static int pnv_get_display_clock_speed(struct drm_device *dev)
4314{
4315 u16 gcfgc = 0;
4316
4317 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4318
4319 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4320 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4321 return 267000;
4322 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4323 return 333000;
4324 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4325 return 444000;
4326 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4327 return 200000;
4328 default:
4329 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4330 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4331 return 133000;
4332 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4333 return 167000;
4334 }
4335}
4336
e70236a8
JB		 4337static int i915gm_get_display_clock_speed(struct drm_device *dev)
4338{
4339 u16 gcfgc = 0;
79e53945 4340
e70236a8
JB		 4341 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4342
4343 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4344 return 133000;
4345 else {
4346 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4347 case GC_DISPLAY_CLOCK_333_MHZ:
4348 return 333000;
4349 default:
4350 case GC_DISPLAY_CLOCK_190_200_MHZ:
4351 return 190000;
79e53945 4352 }
e70236a8
JB		 4353 }
4354}
4355
4356static int i865_get_display_clock_speed(struct drm_device *dev)
4357{
4358 return 266000;
4359}
4360
4361static int i855_get_display_clock_speed(struct drm_device *dev)
4362{
4363 u16 hpllcc = 0;
4364 /* Assume that the hardware is in the high speed state. This
4365 * should be the default.
4366 */
4367 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4368 case GC_CLOCK_133_200:
4369 case GC_CLOCK_100_200:
4370 return 200000;
4371 case GC_CLOCK_166_250:
4372 return 250000;
4373 case GC_CLOCK_100_133:
79e53945 4374 return 133000;
e70236a8 4375 }
79e53945 4376
e70236a8
JB		 4377 /* Shouldn't happen */
4378 return 0;
4379}
79e53945 4380
e70236a8
JB		 4381static int i830_get_display_clock_speed(struct drm_device *dev)
4382{
4383 return 133000;
79e53945
JB		 4384}
4385
2c07245f 4386static void
a65851af 4387intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4388{
a65851af
VS		 4389 while (*num > DATA_LINK_M_N_MASK ||
4390 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4391 *num >>= 1;
4392 *den >>= 1;
4393 }
4394}
4395
a65851af
VS		 4396static void compute_m_n(unsigned int m, unsigned int n,
4397 uint32_t *ret_m, uint32_t *ret_n)
4398{
4399 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4400 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4401 intel_reduce_m_n_ratio(ret_m, ret_n);
4402}
4403
e69d0bc1
DV		 4404void
4405intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4406 int pixel_clock, int link_clock,
4407 struct intel_link_m_n *m_n)
2c07245f 4408{
e69d0bc1 4409 m_n->tu = 64;
a65851af
VS		 4410
4411 compute_m_n(bits_per_pixel * pixel_clock,
4412 link_clock * nlanes * 8,
4413 &m_n->gmch_m, &m_n->gmch_n);
4414
4415 compute_m_n(pixel_clock, link_clock,
4416 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4417}
4418
a7615030
CW		 4419static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4420{
72bbe58c
KP		 4421 if (i915_panel_use_ssc >= 0)
4422 return i915_panel_use_ssc != 0;
41aa3448 4423 return dev_priv->vbt.lvds_use_ssc
435793df 4424 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4425}
4426
c65d77d8
JB		 4427static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4428{
4429 struct drm_device *dev = crtc->dev;
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431 int refclk;
4432
a0c4da24 4433 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4434 refclk = 100000;
a0c4da24 4435 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4436 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4437 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4438 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4439 refclk / 1000);
4440 } else if (!IS_GEN2(dev)) {
4441 refclk = 96000;
4442 } else {
4443 refclk = 48000;
4444 }
4445
4446 return refclk;
4447}
4448
7429e9d4 4449static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4450{
7df00d7a 4451 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4452}
f47709a9 4453
7429e9d4
DV		 4454static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4455{
4456 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4457}
4458
f47709a9 4459static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4460 intel_clock_t *reduced_clock)
4461{
f47709a9 4462 struct drm_device *dev = crtc->base.dev;
a7516a05 4463 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4464 int pipe = crtc->pipe;
a7516a05
JB		 4465 u32 fp, fp2 = 0;
4466
4467 if (IS_PINEVIEW(dev)) {
7429e9d4 4468 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4469 if (reduced_clock)
7429e9d4 4470 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4471 } else {
7429e9d4 4472 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4473 if (reduced_clock)
7429e9d4 4474 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4475 }
4476
4477 I915_WRITE(FP0(pipe), fp);
8bcc2795 4478 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4479
f47709a9
DV		 4480 crtc->lowfreq_avail = false;
4481 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4482 reduced_clock && i915_powersave) {
4483 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4484 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4485 crtc->lowfreq_avail = true;
a7516a05
JB		 4486 } else {
4487 I915_WRITE(FP1(pipe), fp);
8bcc2795 4488 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4489 }
4490}
4491
5e69f97f
CML		 4492static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4493 pipe)
89b667f8
JB		 4494{
4495 u32 reg_val;
4496
4497 /*
4498 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4499 * and set it to a reasonable value instead.
4500 */
5e69f97f 4501 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4502 reg_val &= 0xffffff00;
4503 reg_val |= 0x00000030;
5e69f97f 4504 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4505
5e69f97f 4506 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4507 reg_val &= 0x8cffffff;
4508 reg_val = 0x8c000000;
5e69f97f 4509 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4510
5e69f97f 4511 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4512 reg_val &= 0xffffff00;
5e69f97f 4513 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4514
5e69f97f 4515 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4516 reg_val &= 0x00ffffff;
4517 reg_val |= 0xb0000000;
5e69f97f 4518 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4519}
4520
b551842d
DV		 4521static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4522 struct intel_link_m_n *m_n)
4523{
4524 struct drm_device *dev = crtc->base.dev;
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526 int pipe = crtc->pipe;
4527
e3b95f1e
DV		 4528 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4529 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4530 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4531 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4532}
4533
4534static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4535 struct intel_link_m_n *m_n)
4536{
4537 struct drm_device *dev = crtc->base.dev;
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 int pipe = crtc->pipe;
4540 enum transcoder transcoder = crtc->config.cpu_transcoder;
4541
4542 if (INTEL_INFO(dev)->gen >= 5) {
4543 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4544 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4545 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4546 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4547 } else {
e3b95f1e
DV		 4548 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4549 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4550 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4551 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4552 }
4553}
4554
03afc4a2
DV		 4555static void intel_dp_set_m_n(struct intel_crtc *crtc)
4556{
4557 if (crtc->config.has_pch_encoder)
4558 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4559 else
4560 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4561}
4562
f47709a9 4563static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4564{
f47709a9 4565 struct drm_device *dev = crtc->base.dev;
a0c4da24 4566 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4567 int pipe = crtc->pipe;
89b667f8 4568 u32 dpll, mdiv;
a0c4da24 4569 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4570 u32 coreclk, reg_val, dpll_md;
a0c4da24 4571
09153000
DV		 4572 mutex_lock(&dev_priv->dpio_lock);
4573
f47709a9
DV		 4574 bestn = crtc->config.dpll.n;
4575 bestm1 = crtc->config.dpll.m1;
4576 bestm2 = crtc->config.dpll.m2;
4577 bestp1 = crtc->config.dpll.p1;
4578 bestp2 = crtc->config.dpll.p2;
a0c4da24 4579
89b667f8
JB		 4580 /* See eDP HDMI DPIO driver vbios notes doc */
4581
4582 /* PLL B needs special handling */
4583 if (pipe)
5e69f97f 4584 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4585
4586 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4587 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4588
4589 /* Disable target IRef on PLL */
5e69f97f 4590 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4591 reg_val &= 0x00ffffff;
5e69f97f 4592 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4593
4594 /* Disable fast lock */
5e69f97f 4595 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4596
4597 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4598 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4599 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4600 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4601 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4602
4603 /*
4604 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4605 * but we don't support that).
4606 * Note: don't use the DAC post divider as it seems unstable.
4607 */
4608 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4609 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4610
a0c4da24 4611 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4612 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4613
89b667f8 4614 /* Set HBR and RBR LPF coefficients */
ff9a6750 4615 if (crtc->config.port_clock == 162000 ||
99750bd4 4616 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4617 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4618 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4619 0x009f0003);
89b667f8 4620 else
5e69f97f 4621 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4622 0x00d0000f);
4623
4624 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4625 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4626 /* Use SSC source */
4627 if (!pipe)
5e69f97f 4628 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4629 0x0df40000);
4630 else
5e69f97f 4631 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4632 0x0df70000);
4633 } else { /* HDMI or VGA */
4634 /* Use bend source */
4635 if (!pipe)
5e69f97f 4636 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4637 0x0df70000);
4638 else
5e69f97f 4639 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4640 0x0df40000);
4641 }
a0c4da24 4642
5e69f97f 4643 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4644 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4645 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4646 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4647 coreclk |= 0x01000000;
5e69f97f 4648 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4649
5e69f97f 4650 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4651
89b667f8
JB		 4652 /* Enable DPIO clock input */
4653 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4654 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4655 /* We should never disable this, set it here for state tracking */
4656 if (pipe == PIPE_B)
89b667f8 4657 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4658 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4659 crtc->config.dpll_hw_state.dpll = dpll;
4660
ef1b460d
DV		 4661 dpll_md = (crtc->config.pixel_multiplier - 1)
4662 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4663 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4664
89b667f8
JB		 4665 if (crtc->config.has_dp_encoder)
4666 intel_dp_set_m_n(crtc);
09153000
DV		 4667
4668 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4669}
4670
f47709a9
DV		 4671static void i9xx_update_pll(struct intel_crtc *crtc,
4672 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4673 int num_connectors)
4674{
f47709a9 4675 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4676 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4677 u32 dpll;
4678 bool is_sdvo;
f47709a9 4679 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4680
f47709a9 4681 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4682
f47709a9
DV		 4683 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4684 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4685
4686 dpll = DPLL_VGA_MODE_DIS;
4687
f47709a9 4688 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4689 dpll |= DPLLB_MODE_LVDS;
4690 else
4691 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4692
ef1b460d 4693 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4694 dpll |= (crtc->config.pixel_multiplier - 1)
4695 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4696 }
198a037f
DV		 4697
4698 if (is_sdvo)
4a33e48d 4699 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4700
f47709a9 4701 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4702 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4703
4704 /* compute bitmask from p1 value */
4705 if (IS_PINEVIEW(dev))
4706 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4707 else {
4708 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4709 if (IS_G4X(dev) && reduced_clock)
4710 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4711 }
4712 switch (clock->p2) {
4713 case 5:
4714 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4715 break;
4716 case 7:
4717 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4718 break;
4719 case 10:
4720 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4721 break;
4722 case 14:
4723 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4724 break;
4725 }
4726 if (INTEL_INFO(dev)->gen >= 4)
4727 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4728
09ede541 4729 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4730 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4731 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4732 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4733 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4734 else
4735 dpll |= PLL_REF_INPUT_DREFCLK;
4736
4737 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4738 crtc->config.dpll_hw_state.dpll = dpll;
4739
eb1cbe48 4740 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4741 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4742 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4743 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4744 }
66e3d5c0
DV		 4745
4746 if (crtc->config.has_dp_encoder)
4747 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4748}
4749
f47709a9 4750static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4751 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4752 int num_connectors)
4753{
f47709a9 4754 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4755 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4756 u32 dpll;
f47709a9 4757 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4758
f47709a9 4759 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4760
eb1cbe48
DV		 4761 dpll = DPLL_VGA_MODE_DIS;
4762
f47709a9 4763 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4764 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4765 } else {
4766 if (clock->p1 == 2)
4767 dpll |= PLL_P1_DIVIDE_BY_TWO;
4768 else
4769 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4770 if (clock->p2 == 4)
4771 dpll |= PLL_P2_DIVIDE_BY_4;
4772 }
4773
4a33e48d
DV		 4774 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4775 dpll |= DPLL_DVO_2X_MODE;
4776
f47709a9 4777 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4778 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4779 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4780 else
4781 dpll |= PLL_REF_INPUT_DREFCLK;
4782
4783 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4784 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4785}
4786
8a654f3b 4787static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4788{
4789 struct drm_device *dev = intel_crtc->base.dev;
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4792 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4793 struct drm_display_mode *adjusted_mode =
4794 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4795 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4796
4797 /* We need to be careful not to changed the adjusted mode, for otherwise
4798 * the hw state checker will get angry at the mismatch. */
4799 crtc_vtotal = adjusted_mode->crtc_vtotal;
4800 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4801
4802 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4803 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4804 crtc_vtotal -= 1;
4805 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4806 vsyncshift = adjusted_mode->crtc_hsync_start
4807 - adjusted_mode->crtc_htotal / 2;
4808 } else {
4809 vsyncshift = 0;
4810 }
4811
4812 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4813 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4814
fe2b8f9d 4815 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4816 (adjusted_mode->crtc_hdisplay - 1) |
4817 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4818 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4819 (adjusted_mode->crtc_hblank_start - 1) |
4820 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4821 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4822 (adjusted_mode->crtc_hsync_start - 1) |
4823 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4824
fe2b8f9d 4825 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4826 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4827 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4828 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4829 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4830 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4831 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4832 (adjusted_mode->crtc_vsync_start - 1) |
4833 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4834
b5e508d4
PZ		 4835 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4836 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4837 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4838 * bits. */
4839 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4840 (pipe == PIPE_B || pipe == PIPE_C))
4841 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4842
b0e77b9c
PZ		 4843 /* pipesrc controls the size that is scaled from, which should
4844 * always be the user's requested size.
4845 */
4846 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4847 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4848 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4849}
4850
1bd1bd80
DV		 4851static void intel_get_pipe_timings(struct intel_crtc *crtc,
4852 struct intel_crtc_config *pipe_config)
4853{
4854 struct drm_device *dev = crtc->base.dev;
4855 struct drm_i915_private *dev_priv = dev->dev_private;
4856 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4857 uint32_t tmp;
4858
4859 tmp = I915_READ(HTOTAL(cpu_transcoder));
4860 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4861 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4862 tmp = I915_READ(HBLANK(cpu_transcoder));
4863 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4864 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4865 tmp = I915_READ(HSYNC(cpu_transcoder));
4866 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4867 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4868
4869 tmp = I915_READ(VTOTAL(cpu_transcoder));
4870 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4871 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4872 tmp = I915_READ(VBLANK(cpu_transcoder));
4873 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4874 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4875 tmp = I915_READ(VSYNC(cpu_transcoder));
4876 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4877 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4878
4879 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4880 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4881 pipe_config->adjusted_mode.crtc_vtotal += 1;
4882 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4883 }
4884
4885 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4886 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4887 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4888
4889 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4890 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4891}
4892
babea61d
JB		 4893static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4894 struct intel_crtc_config *pipe_config)
4895{
4896 struct drm_crtc *crtc = &intel_crtc->base;
4897
4898 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4899 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4900 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4901 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4902
4903 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4904 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4905 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4906 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4907
4908 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4909
241bfc38 4910 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4911 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4912}
4913
84b046f3
DV		 4914static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4915{
4916 struct drm_device *dev = intel_crtc->base.dev;
4917 struct drm_i915_private *dev_priv = dev->dev_private;
4918 uint32_t pipeconf;
4919
9f11a9e4 4920 pipeconf = 0;
84b046f3 4921
67c72a12
DV		 4922 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4923 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4924 pipeconf |= PIPECONF_ENABLE;
4925
cf532bb2
VS		 4926 if (intel_crtc->config.double_wide)
4927 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4928
ff9ce46e
DV		 4929 /* only g4x and later have fancy bpc/dither controls */
4930 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4931 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4932 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4933 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4934 PIPECONF_DITHER_TYPE_SP;
84b046f3 4935
ff9ce46e
DV		 4936 switch (intel_crtc->config.pipe_bpp) {
4937 case 18:
4938 pipeconf |= PIPECONF_6BPC;
4939 break;
4940 case 24:
4941 pipeconf |= PIPECONF_8BPC;
4942 break;
4943 case 30:
4944 pipeconf |= PIPECONF_10BPC;
4945 break;
4946 default:
4947 /* Case prevented by intel_choose_pipe_bpp_dither. */
4948 BUG();
84b046f3
DV		 4949 }
4950 }
4951
4952 if (HAS_PIPE_CXSR(dev)) {
4953 if (intel_crtc->lowfreq_avail) {
4954 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4955 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4956 } else {
4957 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4958 }
4959 }
4960
84b046f3
DV		 4961 if (!IS_GEN2(dev) &&
4962 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4963 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4964 else
4965 pipeconf |= PIPECONF_PROGRESSIVE;
4966
9f11a9e4
DV		 4967 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4968 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4969
84b046f3
DV		 4970 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4971 POSTING_READ(PIPECONF(intel_crtc->pipe));
4972}
4973
f564048e 4974static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4975 int x, int y,
94352cf9 4976 struct drm_framebuffer *fb)
79e53945
JB		 4977{
4978 struct drm_device *dev = crtc->dev;
4979 struct drm_i915_private *dev_priv = dev->dev_private;
4980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4981 int pipe = intel_crtc->pipe;
80824003 4982 int plane = intel_crtc->plane;
c751ce4f 4983 int refclk, num_connectors = 0;
652c393a 4984 intel_clock_t clock, reduced_clock;
84b046f3 4985 u32 dspcntr;
a16af721 4986 bool ok, has_reduced_clock = false;
e9fd1c02 4987 bool is_lvds = false, is_dsi = false;
5eddb70b 4988 struct intel_encoder *encoder;
d4906093 4989 const intel_limit_t *limit;
5c3b82e2 4990 int ret;
79e53945 4991
6c2b7c12 4992 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4993 switch (encoder->type) {
79e53945
JB		 4994 case INTEL_OUTPUT_LVDS:
4995 is_lvds = true;
4996 break;
e9fd1c02
JN		 4997 case INTEL_OUTPUT_DSI:
4998 is_dsi = true;
4999 break;
79e53945 5000 }
43565a06 5001
c751ce4f 5002 num_connectors++;
79e53945
JB		 5003 }
5004
f2335330
JN		 5005 if (is_dsi)
5006 goto skip_dpll;
5007
5008 if (!intel_crtc->config.clock_set) {
5009 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5010
e9fd1c02
JN		 5011 /*
5012 * Returns a set of divisors for the desired target clock with
5013 * the given refclk, or FALSE. The returned values represent
5014 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5015 * 2) / p1 / p2.
5016 */
5017 limit = intel_limit(crtc, refclk);
5018 ok = dev_priv->display.find_dpll(limit, crtc,
5019 intel_crtc->config.port_clock,
5020 refclk, NULL, &clock);
f2335330 5021 if (!ok) {
e9fd1c02
JN		 5022 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5023 return -EINVAL;
5024 }
79e53945 5025
f2335330
JN		 5026 if (is_lvds && dev_priv->lvds_downclock_avail) {
5027 /*
5028 * Ensure we match the reduced clock's P to the target
5029 * clock. If the clocks don't match, we can't switch
5030 * the display clock by using the FP0/FP1. In such case
5031 * we will disable the LVDS downclock feature.
5032 */
5033 has_reduced_clock =
5034 dev_priv->display.find_dpll(limit, crtc,
5035 dev_priv->lvds_downclock,
5036 refclk, &clock,
5037 &reduced_clock);
5038 }
5039 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5040 intel_crtc->config.dpll.n = clock.n;
5041 intel_crtc->config.dpll.m1 = clock.m1;
5042 intel_crtc->config.dpll.m2 = clock.m2;
5043 intel_crtc->config.dpll.p1 = clock.p1;
5044 intel_crtc->config.dpll.p2 = clock.p2;
5045 }
7026d4ac 5046
e9fd1c02 5047 if (IS_GEN2(dev)) {
8a654f3b 5048 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5049 has_reduced_clock ? &reduced_clock : NULL,
5050 num_connectors);
e9fd1c02 5051 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5052 vlv_update_pll(intel_crtc);
e9fd1c02 5053 } else {
f47709a9 5054 i9xx_update_pll(intel_crtc,
eb1cbe48 5055 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5056 num_connectors);
e9fd1c02 5057 }
79e53945 5058
f2335330 5059skip_dpll:
79e53945
JB		 5060 /* Set up the display plane register */
5061 dspcntr = DISPPLANE_GAMMA_ENABLE;
5062
da6ecc5d
JB		 5063 if (!IS_VALLEYVIEW(dev)) {
5064 if (pipe == 0)
5065 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5066 else
5067 dspcntr |= DISPPLANE_SEL_PIPE_B;
5068 }
79e53945 5069
8a654f3b 5070 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5071
5072 /* pipesrc and dspsize control the size that is scaled from,
5073 * which should always be the user's requested size.
79e53945 5074 */
929c77fb 5075 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5076 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5077 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5078 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5079
84b046f3
DV		 5080 i9xx_set_pipeconf(intel_crtc);
5081
f564048e
EA		 5082 I915_WRITE(DSPCNTR(plane), dspcntr);
5083 POSTING_READ(DSPCNTR(plane));
5084
94352cf9 5085 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5086
f564048e
EA		 5087 return ret;
5088}
5089
2fa2fe9a
DV		 5090static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5091 struct intel_crtc_config *pipe_config)
5092{
5093 struct drm_device *dev = crtc->base.dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 uint32_t tmp;
5096
5097 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5098 if (!(tmp & PFIT_ENABLE))
5099 return;
2fa2fe9a 5100
06922821 5101 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5102 if (INTEL_INFO(dev)->gen < 4) {
5103 if (crtc->pipe != PIPE_B)
5104 return;
2fa2fe9a
DV		 5105 } else {
5106 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5107 return;
5108 }
5109
06922821 5110 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5111 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5112 if (INTEL_INFO(dev)->gen < 5)
5113 pipe_config->gmch_pfit.lvds_border_bits =
5114 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5115}
5116
acbec814
JB		 5117static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5118 struct intel_crtc_config *pipe_config)
5119{
5120 struct drm_device *dev = crtc->base.dev;
5121 struct drm_i915_private *dev_priv = dev->dev_private;
5122 int pipe = pipe_config->cpu_transcoder;
5123 intel_clock_t clock;
5124 u32 mdiv;
662c6ecb 5125 int refclk = 100000;
acbec814
JB		 5126
5127 mutex_lock(&dev_priv->dpio_lock);
5128 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5129 mutex_unlock(&dev_priv->dpio_lock);
5130
5131 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5132 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5133 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5134 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5135 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5136
662c6ecb
CW		 5137 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5138 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5139
5140 pipe_config->port_clock = clock.dot / 10;
5141}
5142
0e8ffe1b
DV		 5143static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5144 struct intel_crtc_config *pipe_config)
5145{
5146 struct drm_device *dev = crtc->base.dev;
5147 struct drm_i915_private *dev_priv = dev->dev_private;
5148 uint32_t tmp;
5149
e143a21c 5150 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5151 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5152
0e8ffe1b
DV		 5153 tmp = I915_READ(PIPECONF(crtc->pipe));
5154 if (!(tmp & PIPECONF_ENABLE))
5155 return false;
5156
42571aef
VS		 5157 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5158 switch (tmp & PIPECONF_BPC_MASK) {
5159 case PIPECONF_6BPC:
5160 pipe_config->pipe_bpp = 18;
5161 break;
5162 case PIPECONF_8BPC:
5163 pipe_config->pipe_bpp = 24;
5164 break;
5165 case PIPECONF_10BPC:
5166 pipe_config->pipe_bpp = 30;
5167 break;
5168 default:
5169 break;
5170 }
5171 }
5172
282740f7
VS		 5173 if (INTEL_INFO(dev)->gen < 4)
5174 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5175
1bd1bd80
DV		 5176 intel_get_pipe_timings(crtc, pipe_config);
5177
2fa2fe9a
DV		 5178 i9xx_get_pfit_config(crtc, pipe_config);
5179
6c49f241
DV		 5180 if (INTEL_INFO(dev)->gen >= 4) {
5181 tmp = I915_READ(DPLL_MD(crtc->pipe));
5182 pipe_config->pixel_multiplier =
5183 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5184 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5185 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5186 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5187 tmp = I915_READ(DPLL(crtc->pipe));
5188 pipe_config->pixel_multiplier =
5189 ((tmp & SDVO_MULTIPLIER_MASK)
5190 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5191 } else {
5192 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5193 * port and will be fixed up in the encoder->get_config
5194 * function. */
5195 pipe_config->pixel_multiplier = 1;
5196 }
8bcc2795
DV		 5197 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5198 if (!IS_VALLEYVIEW(dev)) {
5199 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5200 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5201 } else {
5202 /* Mask out read-only status bits. */
5203 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5204 DPLL_PORTC_READY_MASK |
5205 DPLL_PORTB_READY_MASK);
8bcc2795 5206 }
6c49f241 5207
acbec814
JB		 5208 if (IS_VALLEYVIEW(dev))
5209 vlv_crtc_clock_get(crtc, pipe_config);
5210 else
5211 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5212
0e8ffe1b
DV		 5213 return true;
5214}
5215
dde86e2d 5216static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5217{
5218 struct drm_i915_private *dev_priv = dev->dev_private;
5219 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5220 struct intel_encoder *encoder;
74cfd7ac 5221 u32 val, final;
13d83a67 5222 bool has_lvds = false;
199e5d79 5223 bool has_cpu_edp = false;
199e5d79 5224 bool has_panel = false;
99eb6a01
KP		 5225 bool has_ck505 = false;
5226 bool can_ssc = false;
13d83a67
JB		 5227
5228 /* We need to take the global config into account */
199e5d79
KP		 5229 list_for_each_entry(encoder, &mode_config->encoder_list,
5230 base.head) {
5231 switch (encoder->type) {
5232 case INTEL_OUTPUT_LVDS:
5233 has_panel = true;
5234 has_lvds = true;
5235 break;
5236 case INTEL_OUTPUT_EDP:
5237 has_panel = true;
2de6905f 5238 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5239 has_cpu_edp = true;
5240 break;
13d83a67
JB		 5241 }
5242 }
5243
99eb6a01 5244 if (HAS_PCH_IBX(dev)) {
41aa3448 5245 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5246 can_ssc = has_ck505;
5247 } else {
5248 has_ck505 = false;
5249 can_ssc = true;
5250 }
5251
2de6905f
ID		 5252 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5253 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5254
5255 /* Ironlake: try to setup display ref clock before DPLL
5256 * enabling. This is only under driver's control after
5257 * PCH B stepping, previous chipset stepping should be
5258 * ignoring this setting.
5259 */
74cfd7ac
CW		 5260 val = I915_READ(PCH_DREF_CONTROL);
5261
5262 /* As we must carefully and slowly disable/enable each source in turn,
5263 * compute the final state we want first and check if we need to
5264 * make any changes at all.
5265 */
5266 final = val;
5267 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5268 if (has_ck505)
5269 final |= DREF_NONSPREAD_CK505_ENABLE;
5270 else
5271 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5272
5273 final &= ~DREF_SSC_SOURCE_MASK;
5274 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5275 final &= ~DREF_SSC1_ENABLE;
5276
5277 if (has_panel) {
5278 final |= DREF_SSC_SOURCE_ENABLE;
5279
5280 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5281 final |= DREF_SSC1_ENABLE;
5282
5283 if (has_cpu_edp) {
5284 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5285 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5286 else
5287 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5288 } else
5289 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5290 } else {
5291 final |= DREF_SSC_SOURCE_DISABLE;
5292 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5293 }
5294
5295 if (final == val)
5296 return;
5297
13d83a67 5298 /* Always enable nonspread source */
74cfd7ac 5299 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5300
99eb6a01 5301 if (has_ck505)
74cfd7ac 5302 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5303 else
74cfd7ac 5304 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5305
199e5d79 5306 if (has_panel) {
74cfd7ac
CW		 5307 val &= ~DREF_SSC_SOURCE_MASK;
5308 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5309
199e5d79 5310 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5311 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5312 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5313 val |= DREF_SSC1_ENABLE;
e77166b5 5314 } else
74cfd7ac 5315 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5316
5317 /* Get SSC going before enabling the outputs */
74cfd7ac 5318 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5319 POSTING_READ(PCH_DREF_CONTROL);
5320 udelay(200);
5321
74cfd7ac 5322 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5323
5324 /* Enable CPU source on CPU attached eDP */
199e5d79 5325 if (has_cpu_edp) {
99eb6a01 5326 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5327 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5328 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5329 }
13d83a67 5330 else
74cfd7ac 5331 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5332 } else
74cfd7ac 5333 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5334
74cfd7ac 5335 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5336 POSTING_READ(PCH_DREF_CONTROL);
5337 udelay(200);
5338 } else {
5339 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5340
74cfd7ac 5341 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5342
5343 /* Turn off CPU output */
74cfd7ac 5344 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5345
74cfd7ac 5346 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5347 POSTING_READ(PCH_DREF_CONTROL);
5348 udelay(200);
5349
5350 /* Turn off the SSC source */
74cfd7ac
CW		 5351 val &= ~DREF_SSC_SOURCE_MASK;
5352 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5353
5354 /* Turn off SSC1 */
74cfd7ac 5355 val &= ~DREF_SSC1_ENABLE;
199e5d79 5356
74cfd7ac 5357 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5358 POSTING_READ(PCH_DREF_CONTROL);
5359 udelay(200);
5360 }
74cfd7ac
CW		 5361
5362 BUG_ON(val != final);
13d83a67
JB		 5363}
5364
f31f2d55 5365static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5366{
f31f2d55 5367 uint32_t tmp;
dde86e2d 5368
0ff066a9
PZ		 5369 tmp = I915_READ(SOUTH_CHICKEN2);
5370 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5371 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5372
0ff066a9
PZ		 5373 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5374 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5375 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5376
0ff066a9
PZ		 5377 tmp = I915_READ(SOUTH_CHICKEN2);
5378 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5379 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5380
0ff066a9
PZ		 5381 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5382 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5383 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5384}
5385
5386/* WaMPhyProgramming:hsw */
5387static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5388{
5389 uint32_t tmp;
dde86e2d
PZ		 5390
5391 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5392 tmp &= ~(0xFF << 24);
5393 tmp |= (0x12 << 24);
5394 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5395
dde86e2d
PZ		 5396 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5397 tmp |= (1 << 11);
5398 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5399
5400 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5401 tmp |= (1 << 11);
5402 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5403
dde86e2d
PZ		 5404 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5405 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5406 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5407
5408 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5409 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5410 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5411
0ff066a9
PZ		 5412 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5413 tmp &= ~(7 << 13);
5414 tmp |= (5 << 13);
5415 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5416
0ff066a9
PZ		 5417 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5418 tmp &= ~(7 << 13);
5419 tmp |= (5 << 13);
5420 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5421
5422 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5423 tmp &= ~0xFF;
5424 tmp |= 0x1C;
5425 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5426
5427 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5428 tmp &= ~0xFF;
5429 tmp |= 0x1C;
5430 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5431
5432 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5433 tmp &= ~(0xFF << 16);
5434 tmp |= (0x1C << 16);
5435 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5436
5437 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5438 tmp &= ~(0xFF << 16);
5439 tmp |= (0x1C << 16);
5440 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5441
0ff066a9
PZ		 5442 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5443 tmp |= (1 << 27);
5444 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5445
0ff066a9
PZ		 5446 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5447 tmp |= (1 << 27);
5448 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5449
0ff066a9
PZ		 5450 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5451 tmp &= ~(0xF << 28);
5452 tmp |= (4 << 28);
5453 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5454
0ff066a9
PZ		 5455 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5456 tmp &= ~(0xF << 28);
5457 tmp |= (4 << 28);
5458 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5459}
5460
2fa86a1f
PZ		 5461/* Implements 3 different sequences from BSpec chapter "Display iCLK
5462 * Programming" based on the parameters passed:
5463 * - Sequence to enable CLKOUT_DP
5464 * - Sequence to enable CLKOUT_DP without spread
5465 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5466 */
5467static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5468 bool with_fdi)
f31f2d55
PZ		 5469{
5470 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5471 uint32_t reg, tmp;
5472
5473 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5474 with_spread = true;
5475 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5476 with_fdi, "LP PCH doesn't have FDI\n"))
5477 with_fdi = false;
f31f2d55
PZ		 5478
5479 mutex_lock(&dev_priv->dpio_lock);
5480
5481 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5482 tmp &= ~SBI_SSCCTL_DISABLE;
5483 tmp |= SBI_SSCCTL_PATHALT;
5484 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5485
5486 udelay(24);
5487
2fa86a1f
PZ		 5488 if (with_spread) {
5489 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5490 tmp &= ~SBI_SSCCTL_PATHALT;
5491 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5492
2fa86a1f
PZ		 5493 if (with_fdi) {
5494 lpt_reset_fdi_mphy(dev_priv);
5495 lpt_program_fdi_mphy(dev_priv);
5496 }
5497 }
dde86e2d 5498
2fa86a1f
PZ		 5499 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5500 SBI_GEN0 : SBI_DBUFF0;
5501 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5502 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5503 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5504
5505 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5506}
5507
47701c3b
PZ		 5508/* Sequence to disable CLKOUT_DP */
5509static void lpt_disable_clkout_dp(struct drm_device *dev)
5510{
5511 struct drm_i915_private *dev_priv = dev->dev_private;
5512 uint32_t reg, tmp;
5513
5514 mutex_lock(&dev_priv->dpio_lock);
5515
5516 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5517 SBI_GEN0 : SBI_DBUFF0;
5518 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5519 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5520 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5521
5522 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5523 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5524 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5525 tmp |= SBI_SSCCTL_PATHALT;
5526 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5527 udelay(32);
5528 }
5529 tmp |= SBI_SSCCTL_DISABLE;
5530 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5531 }
5532
5533 mutex_unlock(&dev_priv->dpio_lock);
5534}
5535
bf8fa3d3
PZ		 5536static void lpt_init_pch_refclk(struct drm_device *dev)
5537{
5538 struct drm_mode_config *mode_config = &dev->mode_config;
5539 struct intel_encoder *encoder;
5540 bool has_vga = false;
5541
5542 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5543 switch (encoder->type) {
5544 case INTEL_OUTPUT_ANALOG:
5545 has_vga = true;
5546 break;
5547 }
5548 }
5549
47701c3b
PZ		 5550 if (has_vga)
5551 lpt_enable_clkout_dp(dev, true, true);
5552 else
5553 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5554}
5555
dde86e2d
PZ		 5556/*
5557 * Initialize reference clocks when the driver loads
5558 */
5559void intel_init_pch_refclk(struct drm_device *dev)
5560{
5561 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5562 ironlake_init_pch_refclk(dev);
5563 else if (HAS_PCH_LPT(dev))
5564 lpt_init_pch_refclk(dev);
5565}
5566
d9d444cb
JB		 5567static int ironlake_get_refclk(struct drm_crtc *crtc)
5568{
5569 struct drm_device *dev = crtc->dev;
5570 struct drm_i915_private *dev_priv = dev->dev_private;
5571 struct intel_encoder *encoder;
d9d444cb
JB		 5572 int num_connectors = 0;
5573 bool is_lvds = false;
5574
6c2b7c12 5575 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5576 switch (encoder->type) {
5577 case INTEL_OUTPUT_LVDS:
5578 is_lvds = true;
5579 break;
d9d444cb
JB		 5580 }
5581 num_connectors++;
5582 }
5583
5584 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5585 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5586 dev_priv->vbt.lvds_ssc_freq);
5587 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5588 }
5589
5590 return 120000;
5591}
5592
6ff93609 5593static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5594{
c8203565 5595 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5597 int pipe = intel_crtc->pipe;
c8203565
PZ		 5598 uint32_t val;
5599
78114071 5600 val = 0;
c8203565 5601
965e0c48 5602 switch (intel_crtc->config.pipe_bpp) {
c8203565 5603 case 18:
dfd07d72 5604 val |= PIPECONF_6BPC;
c8203565
PZ		 5605 break;
5606 case 24:
dfd07d72 5607 val |= PIPECONF_8BPC;
c8203565
PZ		 5608 break;
5609 case 30:
dfd07d72 5610 val |= PIPECONF_10BPC;
c8203565
PZ		 5611 break;
5612 case 36:
dfd07d72 5613 val |= PIPECONF_12BPC;
c8203565
PZ		 5614 break;
5615 default:
cc769b62
PZ		 5616 /* Case prevented by intel_choose_pipe_bpp_dither. */
5617 BUG();
c8203565
PZ		 5618 }
5619
d8b32247 5620 if (intel_crtc->config.dither)
c8203565
PZ		 5621 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5622
6ff93609 5623 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5624 val |= PIPECONF_INTERLACED_ILK;
5625 else
5626 val |= PIPECONF_PROGRESSIVE;
5627
50f3b016 5628 if (intel_crtc->config.limited_color_range)
3685a8f3 5629 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5630
c8203565
PZ		 5631 I915_WRITE(PIPECONF(pipe), val);
5632 POSTING_READ(PIPECONF(pipe));
5633}
5634
86d3efce
VS		 5635/*
5636 * Set up the pipe CSC unit.
5637 *
5638 * Currently only full range RGB to limited range RGB conversion
5639 * is supported, but eventually this should handle various
5640 * RGB<->YCbCr scenarios as well.
5641 */
50f3b016 5642static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5643{
5644 struct drm_device *dev = crtc->dev;
5645 struct drm_i915_private *dev_priv = dev->dev_private;
5646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5647 int pipe = intel_crtc->pipe;
5648 uint16_t coeff = 0x7800; /* 1.0 */
5649
5650 /*
5651 * TODO: Check what kind of values actually come out of the pipe
5652 * with these coeff/postoff values and adjust to get the best
5653 * accuracy. Perhaps we even need to take the bpc value into
5654 * consideration.
5655 */
5656
50f3b016 5657 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5658 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5659
5660 /*
5661 * GY/GU and RY/RU should be the other way around according
5662 * to BSpec, but reality doesn't agree. Just set them up in
5663 * a way that results in the correct picture.
5664 */
5665 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5666 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5667
5668 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5669 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5670
5671 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5672 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5673
5674 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5675 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5676 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5677
5678 if (INTEL_INFO(dev)->gen > 6) {
5679 uint16_t postoff = 0;
5680
50f3b016 5681 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5682 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5683
5684 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5685 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5686 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5687
5688 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5689 } else {
5690 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5691
50f3b016 5692 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5693 mode |= CSC_BLACK_SCREEN_OFFSET;
5694
5695 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5696 }
5697}
5698
6ff93609 5699static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5700{
5701 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5703 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5704 uint32_t val;
5705
3eff4faa 5706 val = 0;
ee2b0b38 5707
d8b32247 5708 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5709 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5710
6ff93609 5711 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5712 val |= PIPECONF_INTERLACED_ILK;
5713 else
5714 val |= PIPECONF_PROGRESSIVE;
5715
702e7a56
PZ		 5716 I915_WRITE(PIPECONF(cpu_transcoder), val);
5717 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5718
5719 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5720 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5721}
5722
6591c6e4 5723static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5724 intel_clock_t *clock,
5725 bool *has_reduced_clock,
5726 intel_clock_t *reduced_clock)
5727{
5728 struct drm_device *dev = crtc->dev;
5729 struct drm_i915_private *dev_priv = dev->dev_private;
5730 struct intel_encoder *intel_encoder;
5731 int refclk;
d4906093 5732 const intel_limit_t *limit;
a16af721 5733 bool ret, is_lvds = false;
79e53945 5734
6591c6e4
PZ		 5735 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5736 switch (intel_encoder->type) {
79e53945
JB		 5737 case INTEL_OUTPUT_LVDS:
5738 is_lvds = true;
5739 break;
79e53945
JB		 5740 }
5741 }
5742
d9d444cb 5743 refclk = ironlake_get_refclk(crtc);
79e53945 5744
d4906093
ML		 5745 /*
5746 * Returns a set of divisors for the desired target clock with the given
5747 * refclk, or FALSE. The returned values represent the clock equation:
5748 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5749 */
1b894b59 5750 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5751 ret = dev_priv->display.find_dpll(limit, crtc,
5752 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5753 refclk, NULL, clock);
6591c6e4
PZ		 5754 if (!ret)
5755 return false;
cda4b7d3 5756
ddc9003c 5757 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5758 /*
5759 * Ensure we match the reduced clock's P to the target clock.
5760 * If the clocks don't match, we can't switch the display clock
5761 * by using the FP0/FP1. In such case we will disable the LVDS
5762 * downclock feature.
5763 */
ee9300bb
DV		 5764 *has_reduced_clock =
5765 dev_priv->display.find_dpll(limit, crtc,
5766 dev_priv->lvds_downclock,
5767 refclk, clock,
5768 reduced_clock);
652c393a 5769 }
61e9653f 5770
6591c6e4
PZ		 5771 return true;
5772}
5773
01a415fd
DV		 5774static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5775{
5776 struct drm_i915_private *dev_priv = dev->dev_private;
5777 uint32_t temp;
5778
5779 temp = I915_READ(SOUTH_CHICKEN1);
5780 if (temp & FDI_BC_BIFURCATION_SELECT)
5781 return;
5782
5783 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5784 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5785
5786 temp |= FDI_BC_BIFURCATION_SELECT;
5787 DRM_DEBUG_KMS("enabling fdi C rx\n");
5788 I915_WRITE(SOUTH_CHICKEN1, temp);
5789 POSTING_READ(SOUTH_CHICKEN1);
5790}
5791
ebfd86fd 5792static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5793{
5794 struct drm_device *dev = intel_crtc->base.dev;
5795 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5796
5797 switch (intel_crtc->pipe) {
5798 case PIPE_A:
ebfd86fd 5799 break;
01a415fd 5800 case PIPE_B:
ebfd86fd 5801 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5802 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5803 else
5804 cpt_enable_fdi_bc_bifurcation(dev);
5805
ebfd86fd 5806 break;
01a415fd 5807 case PIPE_C:
01a415fd
DV		 5808 cpt_enable_fdi_bc_bifurcation(dev);
5809
ebfd86fd 5810 break;
01a415fd
DV		 5811 default:
5812 BUG();
5813 }
5814}
5815
d4b1931c
PZ		 5816int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5817{
5818 /*
5819 * Account for spread spectrum to avoid
5820 * oversubscribing the link. Max center spread
5821 * is 2.5%; use 5% for safety's sake.
5822 */
5823 u32 bps = target_clock * bpp * 21 / 20;
5824 return bps / (link_bw * 8) + 1;
5825}
5826
7429e9d4 5827static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5828{
7429e9d4 5829 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5830}
5831
de13a2e3 5832static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5833 u32 *fp,
9a7c7890 5834 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5835{
de13a2e3 5836 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5837 struct drm_device *dev = crtc->dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5839 struct intel_encoder *intel_encoder;
5840 uint32_t dpll;
6cc5f341 5841 int factor, num_connectors = 0;
09ede541 5842 bool is_lvds = false, is_sdvo = false;
79e53945 5843
de13a2e3
PZ		 5844 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5845 switch (intel_encoder->type) {
79e53945
JB		 5846 case INTEL_OUTPUT_LVDS:
5847 is_lvds = true;
5848 break;
5849 case INTEL_OUTPUT_SDVO:
7d57382e 5850 case INTEL_OUTPUT_HDMI:
79e53945 5851 is_sdvo = true;
79e53945 5852 break;
79e53945 5853 }
43565a06 5854
c751ce4f 5855 num_connectors++;
79e53945 5856 }
79e53945 5857
c1858123 5858 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5859 factor = 21;
5860 if (is_lvds) {
5861 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5862 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5863 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5864 factor = 25;
09ede541 5865 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5866 factor = 20;
c1858123 5867
7429e9d4 5868 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5869 *fp |= FP_CB_TUNE;
2c07245f 5870
9a7c7890
DV		 5871 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5872 *fp2 |= FP_CB_TUNE;
5873
5eddb70b 5874 dpll = 0;
2c07245f 5875
a07d6787
EA		 5876 if (is_lvds)
5877 dpll |= DPLLB_MODE_LVDS;
5878 else
5879 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5880
ef1b460d
DV		 5881 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5882 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5883
5884 if (is_sdvo)
4a33e48d 5885 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5886 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5887 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5888
a07d6787 5889 /* compute bitmask from p1 value */
7429e9d4 5890 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5891 /* also FPA1 */
7429e9d4 5892 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5893
7429e9d4 5894 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5895 case 5:
5896 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5897 break;
5898 case 7:
5899 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5900 break;
5901 case 10:
5902 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5903 break;
5904 case 14:
5905 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5906 break;
79e53945
JB		 5907 }
5908
b4c09f3b 5909 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5910 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5911 else
5912 dpll |= PLL_REF_INPUT_DREFCLK;
5913
959e16d6 5914 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5915}
5916
5917static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5918 int x, int y,
5919 struct drm_framebuffer *fb)
5920{
5921 struct drm_device *dev = crtc->dev;
5922 struct drm_i915_private *dev_priv = dev->dev_private;
5923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5924 int pipe = intel_crtc->pipe;
5925 int plane = intel_crtc->plane;
5926 int num_connectors = 0;
5927 intel_clock_t clock, reduced_clock;
cbbab5bd 5928 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5929 bool ok, has_reduced_clock = false;
8b47047b 5930 bool is_lvds = false;
de13a2e3 5931 struct intel_encoder *encoder;
e2b78267 5932 struct intel_shared_dpll *pll;
de13a2e3 5933 int ret;
de13a2e3
PZ		 5934
5935 for_each_encoder_on_crtc(dev, crtc, encoder) {
5936 switch (encoder->type) {
5937 case INTEL_OUTPUT_LVDS:
5938 is_lvds = true;
5939 break;
de13a2e3
PZ		 5940 }
5941
5942 num_connectors++;
a07d6787 5943 }
79e53945 5944
5dc5298b
PZ		 5945 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5946 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5947
ff9a6750 5948 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5949 &has_reduced_clock, &reduced_clock);
ee9300bb 5950 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5951 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5952 return -EINVAL;
79e53945 5953 }
f47709a9
DV		 5954 /* Compat-code for transition, will disappear. */
5955 if (!intel_crtc->config.clock_set) {
5956 intel_crtc->config.dpll.n = clock.n;
5957 intel_crtc->config.dpll.m1 = clock.m1;
5958 intel_crtc->config.dpll.m2 = clock.m2;
5959 intel_crtc->config.dpll.p1 = clock.p1;
5960 intel_crtc->config.dpll.p2 = clock.p2;
5961 }
79e53945 5962
5dc5298b 5963 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5964 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5965 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5966 if (has_reduced_clock)
7429e9d4 5967 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5968
7429e9d4 5969 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5970 &fp, &reduced_clock,
5971 has_reduced_clock ? &fp2 : NULL);
5972
959e16d6 5973 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5974 intel_crtc->config.dpll_hw_state.fp0 = fp;
5975 if (has_reduced_clock)
5976 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5977 else
5978 intel_crtc->config.dpll_hw_state.fp1 = fp;
5979
b89a1d39 5980 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5981 if (pll == NULL) {
84f44ce7
VS		 5982 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5983 pipe_name(pipe));
4b645f14
JB		 5984 return -EINVAL;
5985 }
ee7b9f93 5986 } else
e72f9fbf 5987 intel_put_shared_dpll(intel_crtc);
79e53945 5988
03afc4a2
DV		 5989 if (intel_crtc->config.has_dp_encoder)
5990 intel_dp_set_m_n(intel_crtc);
79e53945 5991
bcd644e0
DV		 5992 if (is_lvds && has_reduced_clock && i915_powersave)
5993 intel_crtc->lowfreq_avail = true;
5994 else
5995 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5996
5997 if (intel_crtc->config.has_pch_encoder) {
5998 pll = intel_crtc_to_shared_dpll(intel_crtc);
5999
652c393a
JB		 6000 }
6001
8a654f3b 6002 intel_set_pipe_timings(intel_crtc);
5eddb70b 6003
ca3a0ff8 6004 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6005 intel_cpu_transcoder_set_m_n(intel_crtc,
6006 &intel_crtc->config.fdi_m_n);
6007 }
2c07245f 6008
ebfd86fd
DV		 6009 if (IS_IVYBRIDGE(dev))
6010 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6011
6ff93609 6012 ironlake_set_pipeconf(crtc);
79e53945 6013
a1f9e77e
PZ		 6014 /* Set up the display plane register */
6015 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6016 POSTING_READ(DSPCNTR(plane));
79e53945 6017
94352cf9 6018 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6019
1857e1da 6020 return ret;
79e53945
JB		 6021}
6022
eb14cb74
VS		 6023static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6024 struct intel_link_m_n *m_n)
6025{
6026 struct drm_device *dev = crtc->base.dev;
6027 struct drm_i915_private *dev_priv = dev->dev_private;
6028 enum pipe pipe = crtc->pipe;
6029
6030 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6031 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6032 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6033 & ~TU_SIZE_MASK;
6034 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6035 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6036 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6037}
6038
6039static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6040 enum transcoder transcoder,
6041 struct intel_link_m_n *m_n)
72419203
DV		 6042{
6043 struct drm_device *dev = crtc->base.dev;
6044 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6045 enum pipe pipe = crtc->pipe;
72419203 6046
eb14cb74
VS		 6047 if (INTEL_INFO(dev)->gen >= 5) {
6048 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6049 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6050 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6051 & ~TU_SIZE_MASK;
6052 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6053 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6054 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6055 } else {
6056 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6057 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6058 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6059 & ~TU_SIZE_MASK;
6060 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6061 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6062 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6063 }
6064}
6065
6066void intel_dp_get_m_n(struct intel_crtc *crtc,
6067 struct intel_crtc_config *pipe_config)
6068{
6069 if (crtc->config.has_pch_encoder)
6070 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6071 else
6072 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6073 &pipe_config->dp_m_n);
6074}
72419203 6075
eb14cb74
VS		 6076static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6077 struct intel_crtc_config *pipe_config)
6078{
6079 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6080 &pipe_config->fdi_m_n);
72419203
DV		 6081}
6082
2fa2fe9a
DV		 6083static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6084 struct intel_crtc_config *pipe_config)
6085{
6086 struct drm_device *dev = crtc->base.dev;
6087 struct drm_i915_private *dev_priv = dev->dev_private;
6088 uint32_t tmp;
6089
6090 tmp = I915_READ(PF_CTL(crtc->pipe));
6091
6092 if (tmp & PF_ENABLE) {
fd4daa9c 6093 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6094 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6095 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6096
6097 /* We currently do not free assignements of panel fitters on
6098 * ivb/hsw (since we don't use the higher upscaling modes which
6099 * differentiates them) so just WARN about this case for now. */
6100 if (IS_GEN7(dev)) {
6101 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6102 PF_PIPE_SEL_IVB(crtc->pipe));
6103 }
2fa2fe9a 6104 }
79e53945
JB		 6105}
6106
0e8ffe1b
DV		 6107static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6108 struct intel_crtc_config *pipe_config)
6109{
6110 struct drm_device *dev = crtc->base.dev;
6111 struct drm_i915_private *dev_priv = dev->dev_private;
6112 uint32_t tmp;
6113
e143a21c 6114 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6115 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6116
0e8ffe1b
DV		 6117 tmp = I915_READ(PIPECONF(crtc->pipe));
6118 if (!(tmp & PIPECONF_ENABLE))
6119 return false;
6120
42571aef
VS		 6121 switch (tmp & PIPECONF_BPC_MASK) {
6122 case PIPECONF_6BPC:
6123 pipe_config->pipe_bpp = 18;
6124 break;
6125 case PIPECONF_8BPC:
6126 pipe_config->pipe_bpp = 24;
6127 break;
6128 case PIPECONF_10BPC:
6129 pipe_config->pipe_bpp = 30;
6130 break;
6131 case PIPECONF_12BPC:
6132 pipe_config->pipe_bpp = 36;
6133 break;
6134 default:
6135 break;
6136 }
6137
ab9412ba 6138 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6139 struct intel_shared_dpll *pll;
6140
88adfff1
DV		 6141 pipe_config->has_pch_encoder = true;
6142
627eb5a3
DV		 6143 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6144 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6145 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6146
6147 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6148
c0d43d62 6149 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6150 pipe_config->shared_dpll =
6151 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6152 } else {
6153 tmp = I915_READ(PCH_DPLL_SEL);
6154 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6155 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6156 else
6157 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6158 }
66e985c0
DV		 6159
6160 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6161
6162 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6163 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6164
6165 tmp = pipe_config->dpll_hw_state.dpll;
6166 pipe_config->pixel_multiplier =
6167 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6168 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6169
6170 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6171 } else {
6172 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6173 }
6174
1bd1bd80
DV		 6175 intel_get_pipe_timings(crtc, pipe_config);
6176
2fa2fe9a
DV		 6177 ironlake_get_pfit_config(crtc, pipe_config);
6178
0e8ffe1b
DV		 6179 return true;
6180}
6181
be256dc7
PZ		 6182static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6183{
6184 struct drm_device *dev = dev_priv->dev;
6185 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6186 struct intel_crtc *crtc;
6187 unsigned long irqflags;
bd633a7c 6188 uint32_t val;
be256dc7
PZ		 6189
6190 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6191 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6192 pipe_name(crtc->pipe));
6193
6194 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6195 WARN(plls->spll_refcount, "SPLL enabled\n");
6196 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6197 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6198 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6199 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6200 "CPU PWM1 enabled\n");
6201 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6202 "CPU PWM2 enabled\n");
6203 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6204 "PCH PWM1 enabled\n");
6205 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6206 "Utility pin enabled\n");
6207 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6208
6209 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6210 val = I915_READ(DEIMR);
6211 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6212 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6213 val = I915_READ(SDEIMR);
bd633a7c 6214 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6215 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6216 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6217}
6218
6219/*
6220 * This function implements pieces of two sequences from BSpec:
6221 * - Sequence for display software to disable LCPLL
6222 * - Sequence for display software to allow package C8+
6223 * The steps implemented here are just the steps that actually touch the LCPLL
6224 * register. Callers should take care of disabling all the display engine
6225 * functions, doing the mode unset, fixing interrupts, etc.
6226 */
6ff58d53
PZ		 6227static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6228 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6229{
6230 uint32_t val;
6231
6232 assert_can_disable_lcpll(dev_priv);
6233
6234 val = I915_READ(LCPLL_CTL);
6235
6236 if (switch_to_fclk) {
6237 val |= LCPLL_CD_SOURCE_FCLK;
6238 I915_WRITE(LCPLL_CTL, val);
6239
6240 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6241 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6242 DRM_ERROR("Switching to FCLK failed\n");
6243
6244 val = I915_READ(LCPLL_CTL);
6245 }
6246
6247 val |= LCPLL_PLL_DISABLE;
6248 I915_WRITE(LCPLL_CTL, val);
6249 POSTING_READ(LCPLL_CTL);
6250
6251 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6252 DRM_ERROR("LCPLL still locked\n");
6253
6254 val = I915_READ(D_COMP);
6255 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6256 mutex_lock(&dev_priv->rps.hw_lock);
6257 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6258 DRM_ERROR("Failed to disable D_COMP\n");
6259 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6260 POSTING_READ(D_COMP);
6261 ndelay(100);
6262
6263 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6264 DRM_ERROR("D_COMP RCOMP still in progress\n");
6265
6266 if (allow_power_down) {
6267 val = I915_READ(LCPLL_CTL);
6268 val |= LCPLL_POWER_DOWN_ALLOW;
6269 I915_WRITE(LCPLL_CTL, val);
6270 POSTING_READ(LCPLL_CTL);
6271 }
6272}
6273
6274/*
6275 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6276 * source.
6277 */
6ff58d53 6278static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6279{
6280 uint32_t val;
6281
6282 val = I915_READ(LCPLL_CTL);
6283
6284 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6285 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6286 return;
6287
215733fa
PZ		 6288 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6289 * we'll hang the machine! */
6290 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6291
be256dc7
PZ		 6292 if (val & LCPLL_POWER_DOWN_ALLOW) {
6293 val &= ~LCPLL_POWER_DOWN_ALLOW;
6294 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6295 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6296 }
6297
6298 val = I915_READ(D_COMP);
6299 val |= D_COMP_COMP_FORCE;
6300 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6301 mutex_lock(&dev_priv->rps.hw_lock);
6302 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6303 DRM_ERROR("Failed to enable D_COMP\n");
6304 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6305 POSTING_READ(D_COMP);
be256dc7
PZ		 6306
6307 val = I915_READ(LCPLL_CTL);
6308 val &= ~LCPLL_PLL_DISABLE;
6309 I915_WRITE(LCPLL_CTL, val);
6310
6311 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6312 DRM_ERROR("LCPLL not locked yet\n");
6313
6314 if (val & LCPLL_CD_SOURCE_FCLK) {
6315 val = I915_READ(LCPLL_CTL);
6316 val &= ~LCPLL_CD_SOURCE_FCLK;
6317 I915_WRITE(LCPLL_CTL, val);
6318
6319 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6320 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6321 DRM_ERROR("Switching back to LCPLL failed\n");
6322 }
215733fa
PZ		 6323
6324 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6325}
6326
c67a470b
PZ		 6327void hsw_enable_pc8_work(struct work_struct *__work)
6328{
6329 struct drm_i915_private *dev_priv =
6330 container_of(to_delayed_work(__work), struct drm_i915_private,
6331 pc8.enable_work);
6332 struct drm_device *dev = dev_priv->dev;
6333 uint32_t val;
6334
6335 if (dev_priv->pc8.enabled)
6336 return;
6337
6338 DRM_DEBUG_KMS("Enabling package C8+\n");
6339
6340 dev_priv->pc8.enabled = true;
6341
6342 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6343 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6344 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6345 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6346 }
6347
6348 lpt_disable_clkout_dp(dev);
6349 hsw_pc8_disable_interrupts(dev);
6350 hsw_disable_lcpll(dev_priv, true, true);
6351}
6352
6353static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6354{
6355 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6356 WARN(dev_priv->pc8.disable_count < 1,
6357 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6358
6359 dev_priv->pc8.disable_count--;
6360 if (dev_priv->pc8.disable_count != 0)
6361 return;
6362
6363 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6364 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6365}
6366
6367static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6368{
6369 struct drm_device *dev = dev_priv->dev;
6370 uint32_t val;
6371
6372 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6373 WARN(dev_priv->pc8.disable_count < 0,
6374 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6375
6376 dev_priv->pc8.disable_count++;
6377 if (dev_priv->pc8.disable_count != 1)
6378 return;
6379
6380 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6381 if (!dev_priv->pc8.enabled)
6382 return;
6383
6384 DRM_DEBUG_KMS("Disabling package C8+\n");
6385
6386 hsw_restore_lcpll(dev_priv);
6387 hsw_pc8_restore_interrupts(dev);
6388 lpt_init_pch_refclk(dev);
6389
6390 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6391 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6392 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6393 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6394 }
6395
6396 intel_prepare_ddi(dev);
6397 i915_gem_init_swizzling(dev);
6398 mutex_lock(&dev_priv->rps.hw_lock);
6399 gen6_update_ring_freq(dev);
6400 mutex_unlock(&dev_priv->rps.hw_lock);
6401 dev_priv->pc8.enabled = false;
6402}
6403
6404void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6405{
6406 mutex_lock(&dev_priv->pc8.lock);
6407 __hsw_enable_package_c8(dev_priv);
6408 mutex_unlock(&dev_priv->pc8.lock);
6409}
6410
6411void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6412{
6413 mutex_lock(&dev_priv->pc8.lock);
6414 __hsw_disable_package_c8(dev_priv);
6415 mutex_unlock(&dev_priv->pc8.lock);
6416}
6417
6418static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6419{
6420 struct drm_device *dev = dev_priv->dev;
6421 struct intel_crtc *crtc;
6422 uint32_t val;
6423
6424 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6425 if (crtc->base.enabled)
6426 return false;
6427
6428 /* This case is still possible since we have the i915.disable_power_well
6429 * parameter and also the KVMr or something else might be requesting the
6430 * power well. */
6431 val = I915_READ(HSW_PWR_WELL_DRIVER);
6432 if (val != 0) {
6433 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6434 return false;
6435 }
6436
6437 return true;
6438}
6439
6440/* Since we're called from modeset_global_resources there's no way to
6441 * symmetrically increase and decrease the refcount, so we use
6442 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6443 * or not.
6444 */
6445static void hsw_update_package_c8(struct drm_device *dev)
6446{
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 bool allow;
6449
6450 if (!i915_enable_pc8)
6451 return;
6452
6453 mutex_lock(&dev_priv->pc8.lock);
6454
6455 allow = hsw_can_enable_package_c8(dev_priv);
6456
6457 if (allow == dev_priv->pc8.requirements_met)
6458 goto done;
6459
6460 dev_priv->pc8.requirements_met = allow;
6461
6462 if (allow)
6463 __hsw_enable_package_c8(dev_priv);
6464 else
6465 __hsw_disable_package_c8(dev_priv);
6466
6467done:
6468 mutex_unlock(&dev_priv->pc8.lock);
6469}
6470
6471static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6472{
6473 if (!dev_priv->pc8.gpu_idle) {
6474 dev_priv->pc8.gpu_idle = true;
6475 hsw_enable_package_c8(dev_priv);
6476 }
6477}
6478
6479static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6480{
6481 if (dev_priv->pc8.gpu_idle) {
6482 dev_priv->pc8.gpu_idle = false;
6483 hsw_disable_package_c8(dev_priv);
6484 }
be256dc7
PZ		 6485}
6486
d6dd9eb1
DV		 6487static void haswell_modeset_global_resources(struct drm_device *dev)
6488{
d6dd9eb1
DV		 6489 bool enable = false;
6490 struct intel_crtc *crtc;
d6dd9eb1
DV		 6491
6492 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6493 if (!crtc->base.enabled)
6494 continue;
d6dd9eb1 6495
fd4daa9c 6496 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6497 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6498 enable = true;
6499 }
6500
d6dd9eb1 6501 intel_set_power_well(dev, enable);
c67a470b
PZ		 6502
6503 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6504}
6505
09b4ddf9 6506static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6507 int x, int y,
6508 struct drm_framebuffer *fb)
6509{
6510 struct drm_device *dev = crtc->dev;
6511 struct drm_i915_private *dev_priv = dev->dev_private;
6512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6513 int plane = intel_crtc->plane;
09b4ddf9 6514 int ret;
09b4ddf9 6515
ff9a6750 6516 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6517 return -EINVAL;
6518
03afc4a2
DV		 6519 if (intel_crtc->config.has_dp_encoder)
6520 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6521
6522 intel_crtc->lowfreq_avail = false;
09b4ddf9 6523
8a654f3b 6524 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6525
ca3a0ff8 6526 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6527 intel_cpu_transcoder_set_m_n(intel_crtc,
6528 &intel_crtc->config.fdi_m_n);
6529 }
09b4ddf9 6530
6ff93609 6531 haswell_set_pipeconf(crtc);
09b4ddf9 6532
50f3b016 6533 intel_set_pipe_csc(crtc);
86d3efce 6534
09b4ddf9 6535 /* Set up the display plane register */
86d3efce 6536 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6537 POSTING_READ(DSPCNTR(plane));
6538
6539 ret = intel_pipe_set_base(crtc, x, y, fb);
6540
1f803ee5 6541 return ret;
79e53945
JB		 6542}
6543
0e8ffe1b
DV		 6544static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6545 struct intel_crtc_config *pipe_config)
6546{
6547 struct drm_device *dev = crtc->base.dev;
6548 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6549 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6550 uint32_t tmp;
6551
e143a21c 6552 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6553 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6554
eccb140b
DV		 6555 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6556 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6557 enum pipe trans_edp_pipe;
6558 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6559 default:
6560 WARN(1, "unknown pipe linked to edp transcoder\n");
6561 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6562 case TRANS_DDI_EDP_INPUT_A_ON:
6563 trans_edp_pipe = PIPE_A;
6564 break;
6565 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6566 trans_edp_pipe = PIPE_B;
6567 break;
6568 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6569 trans_edp_pipe = PIPE_C;
6570 break;
6571 }
6572
6573 if (trans_edp_pipe == crtc->pipe)
6574 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6575 }
6576
b97186f0 6577 if (!intel_display_power_enabled(dev,
eccb140b 6578 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6579 return false;
6580
eccb140b 6581 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6582 if (!(tmp & PIPECONF_ENABLE))
6583 return false;
6584
88adfff1 6585 /*
f196e6be 6586 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6587 * DDI E. So just check whether this pipe is wired to DDI E and whether
6588 * the PCH transcoder is on.
6589 */
eccb140b 6590 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6591 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6592 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6593 pipe_config->has_pch_encoder = true;
6594
627eb5a3
DV		 6595 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6596 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6597 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6598
6599 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6600 }
6601
1bd1bd80
DV		 6602 intel_get_pipe_timings(crtc, pipe_config);
6603
2fa2fe9a
DV		 6604 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6605 if (intel_display_power_enabled(dev, pfit_domain))
6606 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6607
42db64ef
PZ		 6608 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6609 (I915_READ(IPS_CTL) & IPS_ENABLE);
6610
6c49f241
DV		 6611 pipe_config->pixel_multiplier = 1;
6612
0e8ffe1b
DV		 6613 return true;
6614}
6615
f564048e 6616static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6617 int x, int y,
94352cf9 6618 struct drm_framebuffer *fb)
f564048e
EA		 6619{
6620 struct drm_device *dev = crtc->dev;
6621 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6622 struct intel_encoder *encoder;
0b701d27 6623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6624 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6625 int pipe = intel_crtc->pipe;
f564048e
EA		 6626 int ret;
6627
0b701d27 6628 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6629
b8cecdf5
DV		 6630 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6631
79e53945 6632 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6633
9256aa19
DV		 6634 if (ret != 0)
6635 return ret;
6636
6637 for_each_encoder_on_crtc(dev, crtc, encoder) {
6638 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6639 encoder->base.base.id,
6640 drm_get_encoder_name(&encoder->base),
6641 mode->base.id, mode->name);
36f2d1f1 6642 encoder->mode_set(encoder);
9256aa19
DV		 6643 }
6644
6645 return 0;
79e53945
JB		 6646}
6647
3a9627f4
WF		 6648static bool intel_eld_uptodate(struct drm_connector *connector,
6649 int reg_eldv, uint32_t bits_eldv,
6650 int reg_elda, uint32_t bits_elda,
6651 int reg_edid)
6652{
6653 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6654 uint8_t *eld = connector->eld;
6655 uint32_t i;
6656
6657 i = I915_READ(reg_eldv);
6658 i &= bits_eldv;
6659
6660 if (!eld[0])
6661 return !i;
6662
6663 if (!i)
6664 return false;
6665
6666 i = I915_READ(reg_elda);
6667 i &= ~bits_elda;
6668 I915_WRITE(reg_elda, i);
6669
6670 for (i = 0; i < eld[2]; i++)
6671 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6672 return false;
6673
6674 return true;
6675}
6676
e0dac65e
WF		 6677static void g4x_write_eld(struct drm_connector *connector,
6678 struct drm_crtc *crtc)
6679{
6680 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6681 uint8_t *eld = connector->eld;
6682 uint32_t eldv;
6683 uint32_t len;
6684 uint32_t i;
6685
6686 i = I915_READ(G4X_AUD_VID_DID);
6687
6688 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6689 eldv = G4X_ELDV_DEVCL_DEVBLC;
6690 else
6691 eldv = G4X_ELDV_DEVCTG;
6692
3a9627f4
WF		 6693 if (intel_eld_uptodate(connector,
6694 G4X_AUD_CNTL_ST, eldv,
6695 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6696 G4X_HDMIW_HDMIEDID))
6697 return;
6698
e0dac65e
WF		 6699 i = I915_READ(G4X_AUD_CNTL_ST);
6700 i &= ~(eldv | G4X_ELD_ADDR);
6701 len = (i >> 9) & 0x1f; /* ELD buffer size */
6702 I915_WRITE(G4X_AUD_CNTL_ST, i);
6703
6704 if (!eld[0])
6705 return;
6706
6707 len = min_t(uint8_t, eld[2], len);
6708 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6709 for (i = 0; i < len; i++)
6710 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6711
6712 i = I915_READ(G4X_AUD_CNTL_ST);
6713 i |= eldv;
6714 I915_WRITE(G4X_AUD_CNTL_ST, i);
6715}
6716
83358c85
WX		 6717static void haswell_write_eld(struct drm_connector *connector,
6718 struct drm_crtc *crtc)
6719{
6720 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6721 uint8_t *eld = connector->eld;
6722 struct drm_device *dev = crtc->dev;
7b9f35a6 6723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6724 uint32_t eldv;
6725 uint32_t i;
6726 int len;
6727 int pipe = to_intel_crtc(crtc)->pipe;
6728 int tmp;
6729
6730 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6731 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6732 int aud_config = HSW_AUD_CFG(pipe);
6733 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6734
6735
6736 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6737
6738 /* Audio output enable */
6739 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6740 tmp = I915_READ(aud_cntrl_st2);
6741 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6742 I915_WRITE(aud_cntrl_st2, tmp);
6743
6744 /* Wait for 1 vertical blank */
6745 intel_wait_for_vblank(dev, pipe);
6746
6747 /* Set ELD valid state */
6748 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6749 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6750 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6751 I915_WRITE(aud_cntrl_st2, tmp);
6752 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6753 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6754
6755 /* Enable HDMI mode */
6756 tmp = I915_READ(aud_config);
7e7cb34f 6757 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6758 /* clear N_programing_enable and N_value_index */
6759 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6760 I915_WRITE(aud_config, tmp);
6761
6762 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6763
6764 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6765 intel_crtc->eld_vld = true;
83358c85
WX		 6766
6767 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6768 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6769 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6770 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6771 } else
6772 I915_WRITE(aud_config, 0);
6773
6774 if (intel_eld_uptodate(connector,
6775 aud_cntrl_st2, eldv,
6776 aud_cntl_st, IBX_ELD_ADDRESS,
6777 hdmiw_hdmiedid))
6778 return;
6779
6780 i = I915_READ(aud_cntrl_st2);
6781 i &= ~eldv;
6782 I915_WRITE(aud_cntrl_st2, i);
6783
6784 if (!eld[0])
6785 return;
6786
6787 i = I915_READ(aud_cntl_st);
6788 i &= ~IBX_ELD_ADDRESS;
6789 I915_WRITE(aud_cntl_st, i);
6790 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6791 DRM_DEBUG_DRIVER("port num:%d\n", i);
6792
6793 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6794 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6795 for (i = 0; i < len; i++)
6796 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6797
6798 i = I915_READ(aud_cntrl_st2);
6799 i |= eldv;
6800 I915_WRITE(aud_cntrl_st2, i);
6801
6802}
6803
e0dac65e
WF		 6804static void ironlake_write_eld(struct drm_connector *connector,
6805 struct drm_crtc *crtc)
6806{
6807 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6808 uint8_t *eld = connector->eld;
6809 uint32_t eldv;
6810 uint32_t i;
6811 int len;
6812 int hdmiw_hdmiedid;
b6daa025 6813 int aud_config;
e0dac65e
WF		 6814 int aud_cntl_st;
6815 int aud_cntrl_st2;
9b138a83 6816 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6817
b3f33cbf 6818 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6819 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6820 aud_config = IBX_AUD_CFG(pipe);
6821 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6822 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6823 } else {
9b138a83
WX		 6824 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6825 aud_config = CPT_AUD_CFG(pipe);
6826 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6827 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6828 }
6829
9b138a83 6830 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6831
6832 i = I915_READ(aud_cntl_st);
9b138a83 6833 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6834 if (!i) {
6835 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6836 /* operate blindly on all ports */
1202b4c6
WF		 6837 eldv = IBX_ELD_VALIDB;
6838 eldv |= IBX_ELD_VALIDB << 4;
6839 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6840 } else {
2582a850 6841 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6842 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6843 }
6844
3a9627f4
WF		 6845 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6846 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6847 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6848 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6849 } else
6850 I915_WRITE(aud_config, 0);
e0dac65e 6851
3a9627f4
WF		 6852 if (intel_eld_uptodate(connector,
6853 aud_cntrl_st2, eldv,
6854 aud_cntl_st, IBX_ELD_ADDRESS,
6855 hdmiw_hdmiedid))
6856 return;
6857
e0dac65e
WF		 6858 i = I915_READ(aud_cntrl_st2);
6859 i &= ~eldv;
6860 I915_WRITE(aud_cntrl_st2, i);
6861
6862 if (!eld[0])
6863 return;
6864
e0dac65e 6865 i = I915_READ(aud_cntl_st);
1202b4c6 6866 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6867 I915_WRITE(aud_cntl_st, i);
6868
6869 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6870 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6871 for (i = 0; i < len; i++)
6872 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6873
6874 i = I915_READ(aud_cntrl_st2);
6875 i |= eldv;
6876 I915_WRITE(aud_cntrl_st2, i);
6877}
6878
6879void intel_write_eld(struct drm_encoder *encoder,
6880 struct drm_display_mode *mode)
6881{
6882 struct drm_crtc *crtc = encoder->crtc;
6883 struct drm_connector *connector;
6884 struct drm_device *dev = encoder->dev;
6885 struct drm_i915_private *dev_priv = dev->dev_private;
6886
6887 connector = drm_select_eld(encoder, mode);
6888 if (!connector)
6889 return;
6890
6891 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6892 connector->base.id,
6893 drm_get_connector_name(connector),
6894 connector->encoder->base.id,
6895 drm_get_encoder_name(connector->encoder));
6896
6897 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6898
6899 if (dev_priv->display.write_eld)
6900 dev_priv->display.write_eld(connector, crtc);
6901}
6902
560b85bb
CW		 6903static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6904{
6905 struct drm_device *dev = crtc->dev;
6906 struct drm_i915_private *dev_priv = dev->dev_private;
6907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6908 bool visible = base != 0;
6909 u32 cntl;
6910
6911 if (intel_crtc->cursor_visible == visible)
6912 return;
6913
9db4a9c7 6914 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6915 if (visible) {
6916 /* On these chipsets we can only modify the base whilst
6917 * the cursor is disabled.
6918 */
9db4a9c7 6919 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6920
6921 cntl &= ~(CURSOR_FORMAT_MASK);
6922 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6923 cntl |= CURSOR_ENABLE |
6924 CURSOR_GAMMA_ENABLE |
6925 CURSOR_FORMAT_ARGB;
6926 } else
6927 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6928 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6929
6930 intel_crtc->cursor_visible = visible;
6931}
6932
6933static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6934{
6935 struct drm_device *dev = crtc->dev;
6936 struct drm_i915_private *dev_priv = dev->dev_private;
6937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6938 int pipe = intel_crtc->pipe;
6939 bool visible = base != 0;
6940
6941 if (intel_crtc->cursor_visible != visible) {
548f245b 6942 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6943 if (base) {
6944 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6945 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6946 cntl |= pipe << 28; /* Connect to correct pipe */
6947 } else {
6948 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6949 cntl |= CURSOR_MODE_DISABLE;
6950 }
9db4a9c7 6951 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6952
6953 intel_crtc->cursor_visible = visible;
6954 }
6955 /* and commit changes on next vblank */
9db4a9c7 6956 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6957}
6958
65a21cd6
JB		 6959static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6960{
6961 struct drm_device *dev = crtc->dev;
6962 struct drm_i915_private *dev_priv = dev->dev_private;
6963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6964 int pipe = intel_crtc->pipe;
6965 bool visible = base != 0;
6966
6967 if (intel_crtc->cursor_visible != visible) {
6968 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6969 if (base) {
6970 cntl &= ~CURSOR_MODE;
6971 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6972 } else {
6973 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6974 cntl |= CURSOR_MODE_DISABLE;
6975 }
1f5d76db 6976 if (IS_HASWELL(dev)) {
86d3efce 6977 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6978 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6979 }
65a21cd6
JB		 6980 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6981
6982 intel_crtc->cursor_visible = visible;
6983 }
6984 /* and commit changes on next vblank */
6985 I915_WRITE(CURBASE_IVB(pipe), base);
6986}
6987
cda4b7d3 6988/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6989static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6990 bool on)
cda4b7d3
CW		 6991{
6992 struct drm_device *dev = crtc->dev;
6993 struct drm_i915_private *dev_priv = dev->dev_private;
6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6995 int pipe = intel_crtc->pipe;
6996 int x = intel_crtc->cursor_x;
6997 int y = intel_crtc->cursor_y;
d6e4db15 6998 u32 base = 0, pos = 0;
cda4b7d3
CW		 6999 bool visible;
7000
d6e4db15 7001 if (on)
cda4b7d3 7002 base = intel_crtc->cursor_addr;
cda4b7d3 7003
d6e4db15
VS		 7004 if (x >= intel_crtc->config.pipe_src_w)
7005 base = 0;
7006
7007 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7008 base = 0;
7009
7010 if (x < 0) {
efc9064e 7011 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7012 base = 0;
7013
7014 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7015 x = -x;
7016 }
7017 pos |= x << CURSOR_X_SHIFT;
7018
7019 if (y < 0) {
efc9064e 7020 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7021 base = 0;
7022
7023 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7024 y = -y;
7025 }
7026 pos |= y << CURSOR_Y_SHIFT;
7027
7028 visible = base != 0;
560b85bb 7029 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7030 return;
7031
0cd83aa9 7032 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7033 I915_WRITE(CURPOS_IVB(pipe), pos);
7034 ivb_update_cursor(crtc, base);
7035 } else {
7036 I915_WRITE(CURPOS(pipe), pos);
7037 if (IS_845G(dev) || IS_I865G(dev))
7038 i845_update_cursor(crtc, base);
7039 else
7040 i9xx_update_cursor(crtc, base);
7041 }
cda4b7d3
CW		 7042}
7043
79e53945 7044static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7045 struct drm_file *file,
79e53945
JB		 7046 uint32_t handle,
7047 uint32_t width, uint32_t height)
7048{
7049 struct drm_device *dev = crtc->dev;
7050 struct drm_i915_private *dev_priv = dev->dev_private;
7051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7052 struct drm_i915_gem_object *obj;
cda4b7d3 7053 uint32_t addr;
3f8bc370 7054 int ret;
79e53945 7055
79e53945
JB		 7056 /* if we want to turn off the cursor ignore width and height */
7057 if (!handle) {
28c97730 7058 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7059 addr = 0;
05394f39 7060 obj = NULL;
5004417d 7061 mutex_lock(&dev->struct_mutex);
3f8bc370 7062 goto finish;
79e53945
JB		 7063 }
7064
7065 /* Currently we only support 64x64 cursors */
7066 if (width != 64 || height != 64) {
7067 DRM_ERROR("we currently only support 64x64 cursors\n");
7068 return -EINVAL;
7069 }
7070
05394f39 7071 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7072 if (&obj->base == NULL)
79e53945
JB		 7073 return -ENOENT;
7074
05394f39 7075 if (obj->base.size < width * height * 4) {
79e53945 7076 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7077 ret = -ENOMEM;
7078 goto fail;
79e53945
JB		 7079 }
7080
71acb5eb 7081 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7082 mutex_lock(&dev->struct_mutex);
b295d1b6 7083 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7084 unsigned alignment;
7085
d9e86c0e
CW		 7086 if (obj->tiling_mode) {
7087 DRM_ERROR("cursor cannot be tiled\n");
7088 ret = -EINVAL;
7089 goto fail_locked;
7090 }
7091
693db184
CW		 7092 /* Note that the w/a also requires 2 PTE of padding following
7093 * the bo. We currently fill all unused PTE with the shadow
7094 * page and so we should always have valid PTE following the
7095 * cursor preventing the VT-d warning.
7096 */
7097 alignment = 0;
7098 if (need_vtd_wa(dev))
7099 alignment = 64*1024;
7100
7101 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7102 if (ret) {
7103 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7104 goto fail_locked;
e7b526bb
CW		 7105 }
7106
d9e86c0e
CW		 7107 ret = i915_gem_object_put_fence(obj);
7108 if (ret) {
2da3b9b9 7109 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7110 goto fail_unpin;
7111 }
7112
f343c5f6 7113 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7114 } else {
6eeefaf3 7115 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7116 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7117 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7118 align);
71acb5eb
DA		 7119 if (ret) {
7120 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7121 goto fail_locked;
71acb5eb 7122 }
05394f39 7123 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7124 }
7125
a6c45cf0 7126 if (IS_GEN2(dev))
14b60391
JB		 7127 I915_WRITE(CURSIZE, (height << 12) | width);
7128
3f8bc370 7129 finish:
3f8bc370 7130 if (intel_crtc->cursor_bo) {
b295d1b6 7131 if (dev_priv->info->cursor_needs_physical) {
05394f39 7132 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7133 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7134 } else
cc98b413 7135 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7136 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7137 }
80824003 7138
7f9872e0 7139 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7140
7141 intel_crtc->cursor_addr = addr;
05394f39 7142 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7143 intel_crtc->cursor_width = width;
7144 intel_crtc->cursor_height = height;
7145
f2f5f771
VS		 7146 if (intel_crtc->active)
7147 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7148
79e53945 7149 return 0;
e7b526bb 7150fail_unpin:
cc98b413 7151 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7152fail_locked:
34b8686e 7153 mutex_unlock(&dev->struct_mutex);
bc9025bd 7154fail:
05394f39 7155 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7156 return ret;
79e53945
JB		 7157}
7158
7159static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7160{
79e53945 7161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7162
cda4b7d3
CW		 7163 intel_crtc->cursor_x = x;
7164 intel_crtc->cursor_y = y;
652c393a 7165
f2f5f771
VS		 7166 if (intel_crtc->active)
7167 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7168
7169 return 0;
b8c00ac5
DA		 7170}
7171
79e53945 7172static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7173 u16 *blue, uint32_t start, uint32_t size)
79e53945 7174{
7203425a 7175 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7177
7203425a 7178 for (i = start; i < end; i++) {
79e53945
JB		 7179 intel_crtc->lut_r[i] = red[i] >> 8;
7180 intel_crtc->lut_g[i] = green[i] >> 8;
7181 intel_crtc->lut_b[i] = blue[i] >> 8;
7182 }
7183
7184 intel_crtc_load_lut(crtc);
7185}
7186
79e53945
JB		 7187/* VESA 640x480x72Hz mode to set on the pipe */
7188static struct drm_display_mode load_detect_mode = {
7189 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7190 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7191};
7192
d2dff872
CW		 7193static struct drm_framebuffer *
7194intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7195 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7196 struct drm_i915_gem_object *obj)
7197{
7198 struct intel_framebuffer *intel_fb;
7199 int ret;
7200
7201 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7202 if (!intel_fb) {
7203 drm_gem_object_unreference_unlocked(&obj->base);
7204 return ERR_PTR(-ENOMEM);
7205 }
7206
7207 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7208 if (ret) {
7209 drm_gem_object_unreference_unlocked(&obj->base);
7210 kfree(intel_fb);
7211 return ERR_PTR(ret);
7212 }
7213
7214 return &intel_fb->base;
7215}
7216
7217static u32
7218intel_framebuffer_pitch_for_width(int width, int bpp)
7219{
7220 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7221 return ALIGN(pitch, 64);
7222}
7223
7224static u32
7225intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7226{
7227 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7228 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7229}
7230
7231static struct drm_framebuffer *
7232intel_framebuffer_create_for_mode(struct drm_device *dev,
7233 struct drm_display_mode *mode,
7234 int depth, int bpp)
7235{
7236 struct drm_i915_gem_object *obj;
0fed39bd 7237 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7238
7239 obj = i915_gem_alloc_object(dev,
7240 intel_framebuffer_size_for_mode(mode, bpp));
7241 if (obj == NULL)
7242 return ERR_PTR(-ENOMEM);
7243
7244 mode_cmd.width = mode->hdisplay;
7245 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7246 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7247 bpp);
5ca0c34a 7248 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7249
7250 return intel_framebuffer_create(dev, &mode_cmd, obj);
7251}
7252
7253static struct drm_framebuffer *
7254mode_fits_in_fbdev(struct drm_device *dev,
7255 struct drm_display_mode *mode)
7256{
7257 struct drm_i915_private *dev_priv = dev->dev_private;
7258 struct drm_i915_gem_object *obj;
7259 struct drm_framebuffer *fb;
7260
7261 if (dev_priv->fbdev == NULL)
7262 return NULL;
7263
7264 obj = dev_priv->fbdev->ifb.obj;
7265 if (obj == NULL)
7266 return NULL;
7267
7268 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7269 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7270 fb->bits_per_pixel))
d2dff872
CW		 7271 return NULL;
7272
01f2c773 7273 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7274 return NULL;
7275
7276 return fb;
7277}
7278
d2434ab7 7279bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7280 struct drm_display_mode *mode,
8261b191 7281 struct intel_load_detect_pipe *old)
79e53945
JB		 7282{
7283 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7284 struct intel_encoder *intel_encoder =
7285 intel_attached_encoder(connector);
79e53945 7286 struct drm_crtc *possible_crtc;
4ef69c7a 7287 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7288 struct drm_crtc *crtc = NULL;
7289 struct drm_device *dev = encoder->dev;
94352cf9 7290 struct drm_framebuffer *fb;
79e53945
JB		 7291 int i = -1;
7292
d2dff872
CW		 7293 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7294 connector->base.id, drm_get_connector_name(connector),
7295 encoder->base.id, drm_get_encoder_name(encoder));
7296
79e53945
JB		 7297 /*
7298 * Algorithm gets a little messy:
7a5e4805 7299 *
79e53945
JB		 7300 * - if the connector already has an assigned crtc, use it (but make
7301 * sure it's on first)
7a5e4805 7302 *
79e53945
JB		 7303 * - try to find the first unused crtc that can drive this connector,
7304 * and use that if we find one
79e53945
JB		 7305 */
7306
7307 /* See if we already have a CRTC for this connector */
7308 if (encoder->crtc) {
7309 crtc = encoder->crtc;
8261b191 7310
7b24056b
DV		 7311 mutex_lock(&crtc->mutex);
7312
24218aac 7313 old->dpms_mode = connector->dpms;
8261b191
CW		 7314 old->load_detect_temp = false;
7315
7316 /* Make sure the crtc and connector are running */
24218aac
DV		 7317 if (connector->dpms != DRM_MODE_DPMS_ON)
7318 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7319
7173188d 7320 return true;
79e53945
JB		 7321 }
7322
7323 /* Find an unused one (if possible) */
7324 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7325 i++;
7326 if (!(encoder->possible_crtcs & (1 << i)))
7327 continue;
7328 if (!possible_crtc->enabled) {
7329 crtc = possible_crtc;
7330 break;
7331 }
79e53945
JB		 7332 }
7333
7334 /*
7335 * If we didn't find an unused CRTC, don't use any.
7336 */
7337 if (!crtc) {
7173188d
CW		 7338 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7339 return false;
79e53945
JB		 7340 }
7341
7b24056b 7342 mutex_lock(&crtc->mutex);
fc303101
DV		 7343 intel_encoder->new_crtc = to_intel_crtc(crtc);
7344 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7345
7346 intel_crtc = to_intel_crtc(crtc);
24218aac 7347 old->dpms_mode = connector->dpms;
8261b191 7348 old->load_detect_temp = true;
d2dff872 7349 old->release_fb = NULL;
79e53945 7350
6492711d
CW		 7351 if (!mode)
7352 mode = &load_detect_mode;
79e53945 7353
d2dff872
CW		 7354 /* We need a framebuffer large enough to accommodate all accesses
7355 * that the plane may generate whilst we perform load detection.
7356 * We can not rely on the fbcon either being present (we get called
7357 * during its initialisation to detect all boot displays, or it may
7358 * not even exist) or that it is large enough to satisfy the
7359 * requested mode.
7360 */
94352cf9
DV		 7361 fb = mode_fits_in_fbdev(dev, mode);
7362 if (fb == NULL) {
d2dff872 7363 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7364 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7365 old->release_fb = fb;
d2dff872
CW		 7366 } else
7367 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7368 if (IS_ERR(fb)) {
d2dff872 7369 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7370 mutex_unlock(&crtc->mutex);
0e8b3d3e 7371 return false;
79e53945 7372 }
79e53945 7373
c0c36b94 7374 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7375 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7376 if (old->release_fb)
7377 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7378 mutex_unlock(&crtc->mutex);
0e8b3d3e 7379 return false;
79e53945 7380 }
7173188d 7381
79e53945 7382 /* let the connector get through one full cycle before testing */
9d0498a2 7383 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7384 return true;
79e53945
JB		 7385}
7386
d2434ab7 7387void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7388 struct intel_load_detect_pipe *old)
79e53945 7389{
d2434ab7
DV		 7390 struct intel_encoder *intel_encoder =
7391 intel_attached_encoder(connector);
4ef69c7a 7392 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7393 struct drm_crtc *crtc = encoder->crtc;
79e53945 7394
d2dff872
CW		 7395 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7396 connector->base.id, drm_get_connector_name(connector),
7397 encoder->base.id, drm_get_encoder_name(encoder));
7398
8261b191 7399 if (old->load_detect_temp) {
fc303101
DV		 7400 to_intel_connector(connector)->new_encoder = NULL;
7401 intel_encoder->new_crtc = NULL;
7402 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7403
36206361
DV		 7404 if (old->release_fb) {
7405 drm_framebuffer_unregister_private(old->release_fb);
7406 drm_framebuffer_unreference(old->release_fb);
7407 }
d2dff872 7408
67c96400 7409 mutex_unlock(&crtc->mutex);
0622a53c 7410 return;
79e53945
JB		 7411 }
7412
c751ce4f 7413 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7414 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7415 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7416
7417 mutex_unlock(&crtc->mutex);
79e53945
JB		 7418}
7419
da4a1efa
VS		 7420static int i9xx_pll_refclk(struct drm_device *dev,
7421 const struct intel_crtc_config *pipe_config)
7422{
7423 struct drm_i915_private *dev_priv = dev->dev_private;
7424 u32 dpll = pipe_config->dpll_hw_state.dpll;
7425
7426 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7427 return dev_priv->vbt.lvds_ssc_freq * 1000;
7428 else if (HAS_PCH_SPLIT(dev))
7429 return 120000;
7430 else if (!IS_GEN2(dev))
7431 return 96000;
7432 else
7433 return 48000;
7434}
7435
79e53945 7436/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7437static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7438 struct intel_crtc_config *pipe_config)
79e53945 7439{
f1f644dc 7440 struct drm_device *dev = crtc->base.dev;
79e53945 7441 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7442 int pipe = pipe_config->cpu_transcoder;
293623f7 7443 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7444 u32 fp;
7445 intel_clock_t clock;
da4a1efa 7446 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7447
7448 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7449 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7450 else
293623f7 7451 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7452
7453 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7454 if (IS_PINEVIEW(dev)) {
7455 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7456 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7457 } else {
7458 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7459 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7460 }
7461
a6c45cf0 7462 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7463 if (IS_PINEVIEW(dev))
7464 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7465 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7466 else
7467 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7468 DPLL_FPA01_P1_POST_DIV_SHIFT);
7469
7470 switch (dpll & DPLL_MODE_MASK) {
7471 case DPLLB_MODE_DAC_SERIAL:
7472 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7473 5 : 10;
7474 break;
7475 case DPLLB_MODE_LVDS:
7476 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7477 7 : 14;
7478 break;
7479 default:
28c97730 7480 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7481 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7482 return;
79e53945
JB		 7483 }
7484
ac58c3f0 7485 if (IS_PINEVIEW(dev))
da4a1efa 7486 pineview_clock(refclk, &clock);
ac58c3f0 7487 else
da4a1efa 7488 i9xx_clock(refclk, &clock);
79e53945
JB		 7489 } else {
7490 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7491
7492 if (is_lvds) {
7493 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7494 DPLL_FPA01_P1_POST_DIV_SHIFT);
7495 clock.p2 = 14;
79e53945
JB		 7496 } else {
7497 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7498 clock.p1 = 2;
7499 else {
7500 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7501 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7502 }
7503 if (dpll & PLL_P2_DIVIDE_BY_4)
7504 clock.p2 = 4;
7505 else
7506 clock.p2 = 2;
79e53945 7507 }
da4a1efa
VS		 7508
7509 i9xx_clock(refclk, &clock);
79e53945
JB		 7510 }
7511
18442d08
VS		 7512 /*
7513 * This value includes pixel_multiplier. We will use
241bfc38 7514 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7515 * encoder's get_config() function.
7516 */
7517 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7518}
7519
6878da05
VS		 7520int intel_dotclock_calculate(int link_freq,
7521 const struct intel_link_m_n *m_n)
f1f644dc 7522{
f1f644dc
JB		 7523 /*
7524 * The calculation for the data clock is:
1041a02f 7525 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7526 * But we want to avoid losing precison if possible, so:
1041a02f 7527 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7528 *
7529 * and the link clock is simpler:
1041a02f 7530 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7531 */
7532
6878da05
VS		 7533 if (!m_n->link_n)
7534 return 0;
f1f644dc 7535
6878da05
VS		 7536 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7537}
f1f644dc 7538
18442d08
VS		 7539static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7540 struct intel_crtc_config *pipe_config)
6878da05
VS		 7541{
7542 struct drm_device *dev = crtc->base.dev;
79e53945 7543
18442d08
VS		 7544 /* read out port_clock from the DPLL */
7545 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7546
f1f644dc 7547 /*
18442d08 7548 * This value does not include pixel_multiplier.
241bfc38 7549 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7550 * agree once we know their relationship in the encoder's
7551 * get_config() function.
79e53945 7552 */
241bfc38 7553 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7554 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7555 &pipe_config->fdi_m_n);
79e53945
JB		 7556}
7557
7558/** Returns the currently programmed mode of the given pipe. */
7559struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7560 struct drm_crtc *crtc)
7561{
548f245b 7562 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7564 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7565 struct drm_display_mode *mode;
f1f644dc 7566 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7567 int htot = I915_READ(HTOTAL(cpu_transcoder));
7568 int hsync = I915_READ(HSYNC(cpu_transcoder));
7569 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7570 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7571 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7572
7573 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7574 if (!mode)
7575 return NULL;
7576
f1f644dc
JB		 7577 /*
7578 * Construct a pipe_config sufficient for getting the clock info
7579 * back out of crtc_clock_get.
7580 *
7581 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7582 * to use a real value here instead.
7583 */
293623f7 7584 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7585 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7586 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7587 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7588 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7589 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7590
773ae034 7591 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7592 mode->hdisplay = (htot & 0xffff) + 1;
7593 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7594 mode->hsync_start = (hsync & 0xffff) + 1;
7595 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7596 mode->vdisplay = (vtot & 0xffff) + 1;
7597 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7598 mode->vsync_start = (vsync & 0xffff) + 1;
7599 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7600
7601 drm_mode_set_name(mode);
79e53945
JB		 7602
7603 return mode;
7604}
7605
3dec0095 7606static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7607{
7608 struct drm_device *dev = crtc->dev;
7609 drm_i915_private_t *dev_priv = dev->dev_private;
7610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7611 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7612 int dpll_reg = DPLL(pipe);
7613 int dpll;
652c393a 7614
bad720ff 7615 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7616 return;
7617
7618 if (!dev_priv->lvds_downclock_avail)
7619 return;
7620
dbdc6479 7621 dpll = I915_READ(dpll_reg);
652c393a 7622 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7623 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7624
8ac5a6d5 7625 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7626
7627 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7628 I915_WRITE(dpll_reg, dpll);
9d0498a2 7629 intel_wait_for_vblank(dev, pipe);
dbdc6479 7630
652c393a
JB		 7631 dpll = I915_READ(dpll_reg);
7632 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7633 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7634 }
652c393a
JB		 7635}
7636
7637static void intel_decrease_pllclock(struct drm_crtc *crtc)
7638{
7639 struct drm_device *dev = crtc->dev;
7640 drm_i915_private_t *dev_priv = dev->dev_private;
7641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7642
bad720ff 7643 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7644 return;
7645
7646 if (!dev_priv->lvds_downclock_avail)
7647 return;
7648
7649 /*
7650 * Since this is called by a timer, we should never get here in
7651 * the manual case.
7652 */
7653 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7654 int pipe = intel_crtc->pipe;
7655 int dpll_reg = DPLL(pipe);
7656 int dpll;
f6e5b160 7657
44d98a61 7658 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7659
8ac5a6d5 7660 assert_panel_unlocked(dev_priv, pipe);
652c393a 7661
dc257cf1 7662 dpll = I915_READ(dpll_reg);
652c393a
JB		 7663 dpll |= DISPLAY_RATE_SELECT_FPA1;
7664 I915_WRITE(dpll_reg, dpll);
9d0498a2 7665 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7666 dpll = I915_READ(dpll_reg);
7667 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7668 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7669 }
7670
7671}
7672
f047e395
CW		 7673void intel_mark_busy(struct drm_device *dev)
7674{
c67a470b
PZ		 7675 struct drm_i915_private *dev_priv = dev->dev_private;
7676
7677 hsw_package_c8_gpu_busy(dev_priv);
7678 i915_update_gfx_val(dev_priv);
f047e395
CW		 7679}
7680
7681void intel_mark_idle(struct drm_device *dev)
652c393a 7682{
c67a470b 7683 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7684 struct drm_crtc *crtc;
652c393a 7685
c67a470b
PZ		 7686 hsw_package_c8_gpu_idle(dev_priv);
7687
652c393a
JB		 7688 if (!i915_powersave)
7689 return;
7690
652c393a 7691 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7692 if (!crtc->fb)
7693 continue;
7694
725a5b54 7695 intel_decrease_pllclock(crtc);
652c393a 7696 }
652c393a
JB		 7697}
7698
c65355bb
CW		 7699void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7700 struct intel_ring_buffer *ring)
652c393a 7701{
f047e395
CW		 7702 struct drm_device *dev = obj->base.dev;
7703 struct drm_crtc *crtc;
652c393a 7704
f047e395 7705 if (!i915_powersave)
acb87dfb
CW		 7706 return;
7707
652c393a
JB		 7708 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7709 if (!crtc->fb)
7710 continue;
7711
c65355bb
CW		 7712 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7713 continue;
7714
7715 intel_increase_pllclock(crtc);
7716 if (ring && intel_fbc_enabled(dev))
7717 ring->fbc_dirty = true;
652c393a
JB		 7718 }
7719}
7720
79e53945
JB		 7721static void intel_crtc_destroy(struct drm_crtc *crtc)
7722{
7723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7724 struct drm_device *dev = crtc->dev;
7725 struct intel_unpin_work *work;
7726 unsigned long flags;
7727
7728 spin_lock_irqsave(&dev->event_lock, flags);
7729 work = intel_crtc->unpin_work;
7730 intel_crtc->unpin_work = NULL;
7731 spin_unlock_irqrestore(&dev->event_lock, flags);
7732
7733 if (work) {
7734 cancel_work_sync(&work->work);
7735 kfree(work);
7736 }
79e53945 7737
40ccc72b
MK		 7738 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7739
79e53945 7740 drm_crtc_cleanup(crtc);
67e77c5a 7741
79e53945
JB		 7742 kfree(intel_crtc);
7743}
7744
6b95a207
KH		 7745static void intel_unpin_work_fn(struct work_struct *__work)
7746{
7747 struct intel_unpin_work *work =
7748 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7749 struct drm_device *dev = work->crtc->dev;
6b95a207 7750
b4a98e57 7751 mutex_lock(&dev->struct_mutex);
1690e1eb 7752 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7753 drm_gem_object_unreference(&work->pending_flip_obj->base);
7754 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7755
b4a98e57
CW		 7756 intel_update_fbc(dev);
7757 mutex_unlock(&dev->struct_mutex);
7758
7759 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7760 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7761
6b95a207
KH		 7762 kfree(work);
7763}
7764
1afe3e9d 7765static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7766 struct drm_crtc *crtc)
6b95a207
KH		 7767{
7768 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7770 struct intel_unpin_work *work;
6b95a207
KH		 7771 unsigned long flags;
7772
7773 /* Ignore early vblank irqs */
7774 if (intel_crtc == NULL)
7775 return;
7776
7777 spin_lock_irqsave(&dev->event_lock, flags);
7778 work = intel_crtc->unpin_work;
e7d841ca
CW		 7779
7780 /* Ensure we don't miss a work->pending update ... */
7781 smp_rmb();
7782
7783 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7784 spin_unlock_irqrestore(&dev->event_lock, flags);
7785 return;
7786 }
7787
e7d841ca
CW		 7788 /* and that the unpin work is consistent wrt ->pending. */
7789 smp_rmb();
7790
6b95a207 7791 intel_crtc->unpin_work = NULL;
6b95a207 7792
45a066eb
RC		 7793 if (work->event)
7794 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7795
0af7e4df
MK		 7796 drm_vblank_put(dev, intel_crtc->pipe);
7797
6b95a207
KH		 7798 spin_unlock_irqrestore(&dev->event_lock, flags);
7799
2c10d571 7800 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7801
7802 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7803
7804 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7805}
7806
1afe3e9d
JB		 7807void intel_finish_page_flip(struct drm_device *dev, int pipe)
7808{
7809 drm_i915_private_t *dev_priv = dev->dev_private;
7810 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7811
49b14a5c 7812 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7813}
7814
7815void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7816{
7817 drm_i915_private_t *dev_priv = dev->dev_private;
7818 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7819
49b14a5c 7820 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7821}
7822
6b95a207
KH		 7823void intel_prepare_page_flip(struct drm_device *dev, int plane)
7824{
7825 drm_i915_private_t *dev_priv = dev->dev_private;
7826 struct intel_crtc *intel_crtc =
7827 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7828 unsigned long flags;
7829
e7d841ca
CW		 7830 /* NB: An MMIO update of the plane base pointer will also
7831 * generate a page-flip completion irq, i.e. every modeset
7832 * is also accompanied by a spurious intel_prepare_page_flip().
7833 */
6b95a207 7834 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7835 if (intel_crtc->unpin_work)
7836 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7837 spin_unlock_irqrestore(&dev->event_lock, flags);
7838}
7839
e7d841ca
CW		 7840inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7841{
7842 /* Ensure that the work item is consistent when activating it ... */
7843 smp_wmb();
7844 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7845 /* and that it is marked active as soon as the irq could fire. */
7846 smp_wmb();
7847}
7848
8c9f3aaf
JB		 7849static int intel_gen2_queue_flip(struct drm_device *dev,
7850 struct drm_crtc *crtc,
7851 struct drm_framebuffer *fb,
ed8d1975
KP		 7852 struct drm_i915_gem_object *obj,
7853 uint32_t flags)
8c9f3aaf
JB		 7854{
7855 struct drm_i915_private *dev_priv = dev->dev_private;
7856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7857 u32 flip_mask;
6d90c952 7858 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7859 int ret;
7860
6d90c952 7861 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7862 if (ret)
83d4092b 7863 goto err;
8c9f3aaf 7864
6d90c952 7865 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7866 if (ret)
83d4092b 7867 goto err_unpin;
8c9f3aaf
JB		 7868
7869 /* Can't queue multiple flips, so wait for the previous
7870 * one to finish before executing the next.
7871 */
7872 if (intel_crtc->plane)
7873 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7874 else
7875 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7876 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7877 intel_ring_emit(ring, MI_NOOP);
7878 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7879 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7880 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7881 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7882 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7883
7884 intel_mark_page_flip_active(intel_crtc);
09246732 7885 __intel_ring_advance(ring);
83d4092b
CW		 7886 return 0;
7887
7888err_unpin:
7889 intel_unpin_fb_obj(obj);
7890err:
8c9f3aaf
JB		 7891 return ret;
7892}
7893
7894static int intel_gen3_queue_flip(struct drm_device *dev,
7895 struct drm_crtc *crtc,
7896 struct drm_framebuffer *fb,
ed8d1975
KP		 7897 struct drm_i915_gem_object *obj,
7898 uint32_t flags)
8c9f3aaf
JB		 7899{
7900 struct drm_i915_private *dev_priv = dev->dev_private;
7901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7902 u32 flip_mask;
6d90c952 7903 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7904 int ret;
7905
6d90c952 7906 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7907 if (ret)
83d4092b 7908 goto err;
8c9f3aaf 7909
6d90c952 7910 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7911 if (ret)
83d4092b 7912 goto err_unpin;
8c9f3aaf
JB		 7913
7914 if (intel_crtc->plane)
7915 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7916 else
7917 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7918 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7919 intel_ring_emit(ring, MI_NOOP);
7920 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7921 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7922 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7923 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7924 intel_ring_emit(ring, MI_NOOP);
7925
e7d841ca 7926 intel_mark_page_flip_active(intel_crtc);
09246732 7927 __intel_ring_advance(ring);
83d4092b
CW		 7928 return 0;
7929
7930err_unpin:
7931 intel_unpin_fb_obj(obj);
7932err:
8c9f3aaf
JB		 7933 return ret;
7934}
7935
7936static int intel_gen4_queue_flip(struct drm_device *dev,
7937 struct drm_crtc *crtc,
7938 struct drm_framebuffer *fb,
ed8d1975
KP		 7939 struct drm_i915_gem_object *obj,
7940 uint32_t flags)
8c9f3aaf
JB		 7941{
7942 struct drm_i915_private *dev_priv = dev->dev_private;
7943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7944 uint32_t pf, pipesrc;
6d90c952 7945 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7946 int ret;
7947
6d90c952 7948 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7949 if (ret)
83d4092b 7950 goto err;
8c9f3aaf 7951
6d90c952 7952 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7953 if (ret)
83d4092b 7954 goto err_unpin;
8c9f3aaf
JB		 7955
7956 /* i965+ uses the linear or tiled offsets from the
7957 * Display Registers (which do not change across a page-flip)
7958 * so we need only reprogram the base address.
7959 */
6d90c952
DV		 7960 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7961 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7962 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7963 intel_ring_emit(ring,
f343c5f6 7964 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7965 obj->tiling_mode);
8c9f3aaf
JB		 7966
7967 /* XXX Enabling the panel-fitter across page-flip is so far
7968 * untested on non-native modes, so ignore it for now.
7969 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7970 */
7971 pf = 0;
7972 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7973 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7974
7975 intel_mark_page_flip_active(intel_crtc);
09246732 7976 __intel_ring_advance(ring);
83d4092b
CW		 7977 return 0;
7978
7979err_unpin:
7980 intel_unpin_fb_obj(obj);
7981err:
8c9f3aaf
JB		 7982 return ret;
7983}
7984
7985static int intel_gen6_queue_flip(struct drm_device *dev,
7986 struct drm_crtc *crtc,
7987 struct drm_framebuffer *fb,
ed8d1975
KP		 7988 struct drm_i915_gem_object *obj,
7989 uint32_t flags)
8c9f3aaf
JB		 7990{
7991 struct drm_i915_private *dev_priv = dev->dev_private;
7992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7993 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7994 uint32_t pf, pipesrc;
7995 int ret;
7996
6d90c952 7997 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7998 if (ret)
83d4092b 7999 goto err;
8c9f3aaf 8000
6d90c952 8001 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8002 if (ret)
83d4092b 8003 goto err_unpin;
8c9f3aaf 8004
6d90c952
DV		 8005 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8006 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8007 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8008 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8009
dc257cf1
DV		 8010 /* Contrary to the suggestions in the documentation,
8011 * "Enable Panel Fitter" does not seem to be required when page
8012 * flipping with a non-native mode, and worse causes a normal
8013 * modeset to fail.
8014 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8015 */
8016 pf = 0;
8c9f3aaf 8017 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8018 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8019
8020 intel_mark_page_flip_active(intel_crtc);
09246732 8021 __intel_ring_advance(ring);
83d4092b
CW		 8022 return 0;
8023
8024err_unpin:
8025 intel_unpin_fb_obj(obj);
8026err:
8c9f3aaf
JB		 8027 return ret;
8028}
8029
7c9017e5
JB		 8030static int intel_gen7_queue_flip(struct drm_device *dev,
8031 struct drm_crtc *crtc,
8032 struct drm_framebuffer *fb,
ed8d1975
KP		 8033 struct drm_i915_gem_object *obj,
8034 uint32_t flags)
7c9017e5
JB		 8035{
8036 struct drm_i915_private *dev_priv = dev->dev_private;
8037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8038 struct intel_ring_buffer *ring;
cb05d8de 8039 uint32_t plane_bit = 0;
ffe74d75
CW		 8040 int len, ret;
8041
8042 ring = obj->ring;
1c5fd085 8043 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8044 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8045
8046 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8047 if (ret)
83d4092b 8048 goto err;
7c9017e5 8049
cb05d8de
DV		 8050 switch(intel_crtc->plane) {
8051 case PLANE_A:
8052 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8053 break;
8054 case PLANE_B:
8055 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8056 break;
8057 case PLANE_C:
8058 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8059 break;
8060 default:
8061 WARN_ONCE(1, "unknown plane in flip command\n");
8062 ret = -ENODEV;
ab3951eb 8063 goto err_unpin;
cb05d8de
DV		 8064 }
8065
ffe74d75
CW		 8066 len = 4;
8067 if (ring->id == RCS)
8068 len += 6;
8069
8070 ret = intel_ring_begin(ring, len);
7c9017e5 8071 if (ret)
83d4092b 8072 goto err_unpin;
7c9017e5 8073
ffe74d75
CW		 8074 /* Unmask the flip-done completion message. Note that the bspec says that
8075 * we should do this for both the BCS and RCS, and that we must not unmask
8076 * more than one flip event at any time (or ensure that one flip message
8077 * can be sent by waiting for flip-done prior to queueing new flips).
8078 * Experimentation says that BCS works despite DERRMR masking all
8079 * flip-done completion events and that unmasking all planes at once
8080 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8081 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8082 */
8083 if (ring->id == RCS) {
8084 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8085 intel_ring_emit(ring, DERRMR);
8086 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8087 DERRMR_PIPEB_PRI_FLIP_DONE |
8088 DERRMR_PIPEC_PRI_FLIP_DONE));
8089 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8090 intel_ring_emit(ring, DERRMR);
8091 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8092 }
8093
cb05d8de 8094 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8095 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8096 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8097 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8098
8099 intel_mark_page_flip_active(intel_crtc);
09246732 8100 __intel_ring_advance(ring);
83d4092b
CW		 8101 return 0;
8102
8103err_unpin:
8104 intel_unpin_fb_obj(obj);
8105err:
7c9017e5
JB		 8106 return ret;
8107}
8108
8c9f3aaf
JB		 8109static int intel_default_queue_flip(struct drm_device *dev,
8110 struct drm_crtc *crtc,
8111 struct drm_framebuffer *fb,
ed8d1975
KP		 8112 struct drm_i915_gem_object *obj,
8113 uint32_t flags)
8c9f3aaf
JB		 8114{
8115 return -ENODEV;
8116}
8117
6b95a207
KH		 8118static int intel_crtc_page_flip(struct drm_crtc *crtc,
8119 struct drm_framebuffer *fb,
ed8d1975
KP		 8120 struct drm_pending_vblank_event *event,
8121 uint32_t page_flip_flags)
6b95a207
KH		 8122{
8123 struct drm_device *dev = crtc->dev;
8124 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8125 struct drm_framebuffer *old_fb = crtc->fb;
8126 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8128 struct intel_unpin_work *work;
8c9f3aaf 8129 unsigned long flags;
52e68630 8130 int ret;
6b95a207 8131
e6a595d2
VS		 8132 /* Can't change pixel format via MI display flips. */
8133 if (fb->pixel_format != crtc->fb->pixel_format)
8134 return -EINVAL;
8135
8136 /*
8137 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8138 * Note that pitch changes could also affect these register.
8139 */
8140 if (INTEL_INFO(dev)->gen > 3 &&
8141 (fb->offsets[0] != crtc->fb->offsets[0] ||
8142 fb->pitches[0] != crtc->fb->pitches[0]))
8143 return -EINVAL;
8144
b14c5679 8145 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8146 if (work == NULL)
8147 return -ENOMEM;
8148
6b95a207 8149 work->event = event;
b4a98e57 8150 work->crtc = crtc;
4a35f83b 8151 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8152 INIT_WORK(&work->work, intel_unpin_work_fn);
8153
7317c75e
JB		 8154 ret = drm_vblank_get(dev, intel_crtc->pipe);
8155 if (ret)
8156 goto free_work;
8157
6b95a207
KH		 8158 /* We borrow the event spin lock for protecting unpin_work */
8159 spin_lock_irqsave(&dev->event_lock, flags);
8160 if (intel_crtc->unpin_work) {
8161 spin_unlock_irqrestore(&dev->event_lock, flags);
8162 kfree(work);
7317c75e 8163 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8164
8165 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8166 return -EBUSY;
8167 }
8168 intel_crtc->unpin_work = work;
8169 spin_unlock_irqrestore(&dev->event_lock, flags);
8170
b4a98e57
CW		 8171 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8172 flush_workqueue(dev_priv->wq);
8173
79158103
CW		 8174 ret = i915_mutex_lock_interruptible(dev);
8175 if (ret)
8176 goto cleanup;
6b95a207 8177
75dfca80 8178 /* Reference the objects for the scheduled work. */
05394f39
CW		 8179 drm_gem_object_reference(&work->old_fb_obj->base);
8180 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8181
8182 crtc->fb = fb;
96b099fd 8183
e1f99ce6 8184 work->pending_flip_obj = obj;
e1f99ce6 8185
4e5359cd
SF		 8186 work->enable_stall_check = true;
8187
b4a98e57 8188 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8189 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8190
ed8d1975 8191 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8192 if (ret)
8193 goto cleanup_pending;
6b95a207 8194
7782de3b 8195 intel_disable_fbc(dev);
c65355bb 8196 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8197 mutex_unlock(&dev->struct_mutex);
8198
e5510fac
JB		 8199 trace_i915_flip_request(intel_crtc->plane, obj);
8200
6b95a207 8201 return 0;
96b099fd 8202
8c9f3aaf 8203cleanup_pending:
b4a98e57 8204 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8205 crtc->fb = old_fb;
05394f39
CW		 8206 drm_gem_object_unreference(&work->old_fb_obj->base);
8207 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8208 mutex_unlock(&dev->struct_mutex);
8209
79158103 8210cleanup:
96b099fd
CW		 8211 spin_lock_irqsave(&dev->event_lock, flags);
8212 intel_crtc->unpin_work = NULL;
8213 spin_unlock_irqrestore(&dev->event_lock, flags);
8214
7317c75e
JB		 8215 drm_vblank_put(dev, intel_crtc->pipe);
8216free_work:
96b099fd
CW		 8217 kfree(work);
8218
8219 return ret;
6b95a207
KH		 8220}
8221
f6e5b160 8222static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8223 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8224 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8225};
8226
50f56119
DV		 8227static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8228 struct drm_crtc *crtc)
8229{
8230 struct drm_device *dev;
8231 struct drm_crtc *tmp;
8232 int crtc_mask = 1;
47f1c6c9 8233
50f56119 8234 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8235
50f56119 8236 dev = crtc->dev;
47f1c6c9 8237
50f56119
DV		 8238 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8239 if (tmp == crtc)
8240 break;
8241 crtc_mask <<= 1;
8242 }
47f1c6c9 8243
50f56119
DV		 8244 if (encoder->possible_crtcs & crtc_mask)
8245 return true;
8246 return false;
47f1c6c9 8247}
79e53945 8248
9a935856
DV		 8249/**
8250 * intel_modeset_update_staged_output_state
8251 *
8252 * Updates the staged output configuration state, e.g. after we've read out the
8253 * current hw state.
8254 */
8255static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8256{
9a935856
DV		 8257 struct intel_encoder *encoder;
8258 struct intel_connector *connector;
f6e5b160 8259
9a935856
DV		 8260 list_for_each_entry(connector, &dev->mode_config.connector_list,
8261 base.head) {
8262 connector->new_encoder =
8263 to_intel_encoder(connector->base.encoder);
8264 }
f6e5b160 8265
9a935856
DV		 8266 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8267 base.head) {
8268 encoder->new_crtc =
8269 to_intel_crtc(encoder->base.crtc);
8270 }
f6e5b160
CW		 8271}
8272
9a935856
DV		 8273/**
8274 * intel_modeset_commit_output_state
8275 *
8276 * This function copies the stage display pipe configuration to the real one.
8277 */
8278static void intel_modeset_commit_output_state(struct drm_device *dev)
8279{
8280 struct intel_encoder *encoder;
8281 struct intel_connector *connector;
f6e5b160 8282
9a935856
DV		 8283 list_for_each_entry(connector, &dev->mode_config.connector_list,
8284 base.head) {
8285 connector->base.encoder = &connector->new_encoder->base;
8286 }
f6e5b160 8287
9a935856
DV		 8288 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8289 base.head) {
8290 encoder->base.crtc = &encoder->new_crtc->base;
8291 }
8292}
8293
050f7aeb
DV		 8294static void
8295connected_sink_compute_bpp(struct intel_connector * connector,
8296 struct intel_crtc_config *pipe_config)
8297{
8298 int bpp = pipe_config->pipe_bpp;
8299
8300 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8301 connector->base.base.id,
8302 drm_get_connector_name(&connector->base));
8303
8304 /* Don't use an invalid EDID bpc value */
8305 if (connector->base.display_info.bpc &&
8306 connector->base.display_info.bpc * 3 < bpp) {
8307 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8308 bpp, connector->base.display_info.bpc*3);
8309 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8310 }
8311
8312 /* Clamp bpp to 8 on screens without EDID 1.4 */
8313 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8314 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8315 bpp);
8316 pipe_config->pipe_bpp = 24;
8317 }
8318}
8319
4e53c2e0 8320static int
050f7aeb
DV		 8321compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8322 struct drm_framebuffer *fb,
8323 struct intel_crtc_config *pipe_config)
4e53c2e0 8324{
050f7aeb
DV		 8325 struct drm_device *dev = crtc->base.dev;
8326 struct intel_connector *connector;
4e53c2e0
DV		 8327 int bpp;
8328
d42264b1
DV		 8329 switch (fb->pixel_format) {
8330 case DRM_FORMAT_C8:
4e53c2e0
DV		 8331 bpp = 8*3; /* since we go through a colormap */
8332 break;
d42264b1
DV		 8333 case DRM_FORMAT_XRGB1555:
8334 case DRM_FORMAT_ARGB1555:
8335 /* checked in intel_framebuffer_init already */
8336 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8337 return -EINVAL;
8338 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8339 bpp = 6*3; /* min is 18bpp */
8340 break;
d42264b1
DV		 8341 case DRM_FORMAT_XBGR8888:
8342 case DRM_FORMAT_ABGR8888:
8343 /* checked in intel_framebuffer_init already */
8344 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8345 return -EINVAL;
8346 case DRM_FORMAT_XRGB8888:
8347 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8348 bpp = 8*3;
8349 break;
d42264b1
DV		 8350 case DRM_FORMAT_XRGB2101010:
8351 case DRM_FORMAT_ARGB2101010:
8352 case DRM_FORMAT_XBGR2101010:
8353 case DRM_FORMAT_ABGR2101010:
8354 /* checked in intel_framebuffer_init already */
8355 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8356 return -EINVAL;
4e53c2e0
DV		 8357 bpp = 10*3;
8358 break;
baba133a 8359 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8360 default:
8361 DRM_DEBUG_KMS("unsupported depth\n");
8362 return -EINVAL;
8363 }
8364
4e53c2e0
DV		 8365 pipe_config->pipe_bpp = bpp;
8366
8367 /* Clamp display bpp to EDID value */
8368 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8369 base.head) {
1b829e05
DV		 8370 if (!connector->new_encoder ||
8371 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8372 continue;
8373
050f7aeb 8374 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8375 }
8376
8377 return bpp;
8378}
8379
644db711
DV		 8380static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8381{
8382 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8383 "type: 0x%x flags: 0x%x\n",
1342830c 8384 mode->crtc_clock,
644db711
DV		 8385 mode->crtc_hdisplay, mode->crtc_hsync_start,
8386 mode->crtc_hsync_end, mode->crtc_htotal,
8387 mode->crtc_vdisplay, mode->crtc_vsync_start,
8388 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8389}
8390
c0b03411
DV		 8391static void intel_dump_pipe_config(struct intel_crtc *crtc,
8392 struct intel_crtc_config *pipe_config,
8393 const char *context)
8394{
8395 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8396 context, pipe_name(crtc->pipe));
8397
8398 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8399 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8400 pipe_config->pipe_bpp, pipe_config->dither);
8401 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8402 pipe_config->has_pch_encoder,
8403 pipe_config->fdi_lanes,
8404 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8405 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8406 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8407 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8408 pipe_config->has_dp_encoder,
8409 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8410 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8411 pipe_config->dp_m_n.tu);
c0b03411
DV		 8412 DRM_DEBUG_KMS("requested mode:\n");
8413 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8414 DRM_DEBUG_KMS("adjusted mode:\n");
8415 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8416 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8417 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8418 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8419 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8420 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8421 pipe_config->gmch_pfit.control,
8422 pipe_config->gmch_pfit.pgm_ratios,
8423 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8424 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8425 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8426 pipe_config->pch_pfit.size,
8427 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8428 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8429 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8430}
8431
accfc0c5
DV		 8432static bool check_encoder_cloning(struct drm_crtc *crtc)
8433{
8434 int num_encoders = 0;
8435 bool uncloneable_encoders = false;
8436 struct intel_encoder *encoder;
8437
8438 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8439 base.head) {
8440 if (&encoder->new_crtc->base != crtc)
8441 continue;
8442
8443 num_encoders++;
8444 if (!encoder->cloneable)
8445 uncloneable_encoders = true;
8446 }
8447
8448 return !(num_encoders > 1 && uncloneable_encoders);
8449}
8450
b8cecdf5
DV		 8451static struct intel_crtc_config *
8452intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8453 struct drm_framebuffer *fb,
b8cecdf5 8454 struct drm_display_mode *mode)
ee7b9f93 8455{
7758a113 8456 struct drm_device *dev = crtc->dev;
7758a113 8457 struct intel_encoder *encoder;
b8cecdf5 8458 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8459 int plane_bpp, ret = -EINVAL;
8460 bool retry = true;
ee7b9f93 8461
accfc0c5
DV		 8462 if (!check_encoder_cloning(crtc)) {
8463 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8464 return ERR_PTR(-EINVAL);
8465 }
8466
b8cecdf5
DV		 8467 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8468 if (!pipe_config)
7758a113
DV		 8469 return ERR_PTR(-ENOMEM);
8470
b8cecdf5
DV		 8471 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8472 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8473
e143a21c
DV		 8474 pipe_config->cpu_transcoder =
8475 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8476 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8477
2960bc9c
ID		 8478 /*
8479 * Sanitize sync polarity flags based on requested ones. If neither
8480 * positive or negative polarity is requested, treat this as meaning
8481 * negative polarity.
8482 */
8483 if (!(pipe_config->adjusted_mode.flags &
8484 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8485 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8486
8487 if (!(pipe_config->adjusted_mode.flags &
8488 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8489 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8490
050f7aeb
DV		 8491 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8492 * plane pixel format and any sink constraints into account. Returns the
8493 * source plane bpp so that dithering can be selected on mismatches
8494 * after encoders and crtc also have had their say. */
8495 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8496 fb, pipe_config);
4e53c2e0
DV		 8497 if (plane_bpp < 0)
8498 goto fail;
8499
e29c22c0 8500encoder_retry:
ef1b460d 8501 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8502 pipe_config->port_clock = 0;
ef1b460d 8503 pipe_config->pixel_multiplier = 1;
ff9a6750 8504
135c81b8 8505 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8506 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8507
350a10ca
DL		 8508 /* set_crtcinfo() may have adjusted hdisplay/vdisplay */
8509 pipe_config->pipe_src_w = pipe_config->adjusted_mode.crtc_hdisplay;
8510 pipe_config->pipe_src_h = pipe_config->adjusted_mode.crtc_vdisplay;
8511
7758a113
DV		 8512 /* Pass our mode to the connectors and the CRTC to give them a chance to
8513 * adjust it according to limitations or connector properties, and also
8514 * a chance to reject the mode entirely.
47f1c6c9 8515 */
7758a113
DV		 8516 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8517 base.head) {
47f1c6c9 8518
7758a113
DV		 8519 if (&encoder->new_crtc->base != crtc)
8520 continue;
7ae89233 8521
efea6e8e
DV		 8522 if (!(encoder->compute_config(encoder, pipe_config))) {
8523 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8524 goto fail;
8525 }
ee7b9f93 8526 }
47f1c6c9 8527
ff9a6750
DV		 8528 /* Set default port clock if not overwritten by the encoder. Needs to be
8529 * done afterwards in case the encoder adjusts the mode. */
8530 if (!pipe_config->port_clock)
241bfc38
DL		 8531 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8532 * pipe_config->pixel_multiplier;
ff9a6750 8533
a43f6e0f 8534 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8535 if (ret < 0) {
7758a113
DV		 8536 DRM_DEBUG_KMS("CRTC fixup failed\n");
8537 goto fail;
ee7b9f93 8538 }
e29c22c0
DV		 8539
8540 if (ret == RETRY) {
8541 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8542 ret = -EINVAL;
8543 goto fail;
8544 }
8545
8546 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8547 retry = false;
8548 goto encoder_retry;
8549 }
8550
4e53c2e0
DV		 8551 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8552 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8553 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8554
b8cecdf5 8555 return pipe_config;
7758a113 8556fail:
b8cecdf5 8557 kfree(pipe_config);
e29c22c0 8558 return ERR_PTR(ret);
ee7b9f93 8559}
47f1c6c9 8560
e2e1ed41
DV		 8561/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8562 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8563static void
8564intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8565 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8566{
8567 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8568 struct drm_device *dev = crtc->dev;
8569 struct intel_encoder *encoder;
8570 struct intel_connector *connector;
8571 struct drm_crtc *tmp_crtc;
79e53945 8572
e2e1ed41 8573 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8574
e2e1ed41
DV		 8575 /* Check which crtcs have changed outputs connected to them, these need
8576 * to be part of the prepare_pipes mask. We don't (yet) support global
8577 * modeset across multiple crtcs, so modeset_pipes will only have one
8578 * bit set at most. */
8579 list_for_each_entry(connector, &dev->mode_config.connector_list,
8580 base.head) {
8581 if (connector->base.encoder == &connector->new_encoder->base)
8582 continue;
79e53945 8583
e2e1ed41
DV		 8584 if (connector->base.encoder) {
8585 tmp_crtc = connector->base.encoder->crtc;
8586
8587 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8588 }
8589
8590 if (connector->new_encoder)
8591 *prepare_pipes |=
8592 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8593 }
8594
e2e1ed41
DV		 8595 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8596 base.head) {
8597 if (encoder->base.crtc == &encoder->new_crtc->base)
8598 continue;
8599
8600 if (encoder->base.crtc) {
8601 tmp_crtc = encoder->base.crtc;
8602
8603 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8604 }
8605
8606 if (encoder->new_crtc)
8607 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8608 }
8609
e2e1ed41
DV		 8610 /* Check for any pipes that will be fully disabled ... */
8611 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8612 base.head) {
8613 bool used = false;
22fd0fab 8614
e2e1ed41
DV		 8615 /* Don't try to disable disabled crtcs. */
8616 if (!intel_crtc->base.enabled)
8617 continue;
7e7d76c3 8618
e2e1ed41
DV		 8619 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8620 base.head) {
8621 if (encoder->new_crtc == intel_crtc)
8622 used = true;
8623 }
8624
8625 if (!used)
8626 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8627 }
8628
e2e1ed41
DV		 8629
8630 /* set_mode is also used to update properties on life display pipes. */
8631 intel_crtc = to_intel_crtc(crtc);
8632 if (crtc->enabled)
8633 *prepare_pipes |= 1 << intel_crtc->pipe;
8634
b6c5164d
DV		 8635 /*
8636 * For simplicity do a full modeset on any pipe where the output routing
8637 * changed. We could be more clever, but that would require us to be
8638 * more careful with calling the relevant encoder->mode_set functions.
8639 */
e2e1ed41
DV		 8640 if (*prepare_pipes)
8641 *modeset_pipes = *prepare_pipes;
8642
8643 /* ... and mask these out. */
8644 *modeset_pipes &= ~(*disable_pipes);
8645 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8646
8647 /*
8648 * HACK: We don't (yet) fully support global modesets. intel_set_config
8649 * obies this rule, but the modeset restore mode of
8650 * intel_modeset_setup_hw_state does not.
8651 */
8652 *modeset_pipes &= 1 << intel_crtc->pipe;
8653 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8654
8655 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8656 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8657}
79e53945 8658
ea9d758d 8659static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8660{
ea9d758d 8661 struct drm_encoder *encoder;
f6e5b160 8662 struct drm_device *dev = crtc->dev;
f6e5b160 8663
ea9d758d
DV		 8664 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8665 if (encoder->crtc == crtc)
8666 return true;
8667
8668 return false;
8669}
8670
8671static void
8672intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8673{
8674 struct intel_encoder *intel_encoder;
8675 struct intel_crtc *intel_crtc;
8676 struct drm_connector *connector;
8677
8678 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8679 base.head) {
8680 if (!intel_encoder->base.crtc)
8681 continue;
8682
8683 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8684
8685 if (prepare_pipes & (1 << intel_crtc->pipe))
8686 intel_encoder->connectors_active = false;
8687 }
8688
8689 intel_modeset_commit_output_state(dev);
8690
8691 /* Update computed state. */
8692 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8693 base.head) {
8694 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8695 }
8696
8697 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8698 if (!connector->encoder || !connector->encoder->crtc)
8699 continue;
8700
8701 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8702
8703 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8704 struct drm_property *dpms_property =
8705 dev->mode_config.dpms_property;
8706
ea9d758d 8707 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8708 drm_object_property_set_value(&connector->base,
68d34720
DV		 8709 dpms_property,
8710 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8711
8712 intel_encoder = to_intel_encoder(connector->encoder);
8713 intel_encoder->connectors_active = true;
8714 }
8715 }
8716
8717}
8718
3bd26263 8719static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8720{
3bd26263 8721 int diff;
f1f644dc
JB		 8722
8723 if (clock1 == clock2)
8724 return true;
8725
8726 if (!clock1 || !clock2)
8727 return false;
8728
8729 diff = abs(clock1 - clock2);
8730
8731 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8732 return true;
8733
8734 return false;
8735}
8736
25c5b266
DV		 8737#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8738 list_for_each_entry((intel_crtc), \
8739 &(dev)->mode_config.crtc_list, \
8740 base.head) \
0973f18f 8741 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8742
0e8ffe1b 8743static bool
2fa2fe9a
DV		 8744intel_pipe_config_compare(struct drm_device *dev,
8745 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8746 struct intel_crtc_config *pipe_config)
8747{
66e985c0
DV		 8748#define PIPE_CONF_CHECK_X(name) \
8749 if (current_config->name != pipe_config->name) { \
8750 DRM_ERROR("mismatch in " #name " " \
8751 "(expected 0x%08x, found 0x%08x)\n", \
8752 current_config->name, \
8753 pipe_config->name); \
8754 return false; \
8755 }
8756
08a24034
DV		 8757#define PIPE_CONF_CHECK_I(name) \
8758 if (current_config->name != pipe_config->name) { \
8759 DRM_ERROR("mismatch in " #name " " \
8760 "(expected %i, found %i)\n", \
8761 current_config->name, \
8762 pipe_config->name); \
8763 return false; \
88adfff1
DV		 8764 }
8765
1bd1bd80
DV		 8766#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8767 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8768 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8769 "(expected %i, found %i)\n", \
8770 current_config->name & (mask), \
8771 pipe_config->name & (mask)); \
8772 return false; \
8773 }
8774
5e550656
VS		 8775#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8776 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8777 DRM_ERROR("mismatch in " #name " " \
8778 "(expected %i, found %i)\n", \
8779 current_config->name, \
8780 pipe_config->name); \
8781 return false; \
8782 }
8783
bb760063
DV		 8784#define PIPE_CONF_QUIRK(quirk) \
8785 ((current_config->quirks | pipe_config->quirks) & (quirk))
8786
eccb140b
DV		 8787 PIPE_CONF_CHECK_I(cpu_transcoder);
8788
08a24034
DV		 8789 PIPE_CONF_CHECK_I(has_pch_encoder);
8790 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8791 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8792 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8793 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8794 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8795 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8796
eb14cb74
VS		 8797 PIPE_CONF_CHECK_I(has_dp_encoder);
8798 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8799 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8800 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8801 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8802 PIPE_CONF_CHECK_I(dp_m_n.tu);
8803
1bd1bd80
DV		 8804 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8805 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8806 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8807 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8808 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8809 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8810
8811 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8812 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8813 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8814 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8815 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8816 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8817
c93f54cf 8818 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8819
1bd1bd80
DV		 8820 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8821 DRM_MODE_FLAG_INTERLACE);
8822
bb760063
DV		 8823 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8824 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8825 DRM_MODE_FLAG_PHSYNC);
8826 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8827 DRM_MODE_FLAG_NHSYNC);
8828 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8829 DRM_MODE_FLAG_PVSYNC);
8830 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8831 DRM_MODE_FLAG_NVSYNC);
8832 }
045ac3b5 8833
37327abd
VS		 8834 PIPE_CONF_CHECK_I(pipe_src_w);
8835 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8836
2fa2fe9a
DV		 8837 PIPE_CONF_CHECK_I(gmch_pfit.control);
8838 /* pfit ratios are autocomputed by the hw on gen4+ */
8839 if (INTEL_INFO(dev)->gen < 4)
8840 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8841 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8842 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8843 if (current_config->pch_pfit.enabled) {
8844 PIPE_CONF_CHECK_I(pch_pfit.pos);
8845 PIPE_CONF_CHECK_I(pch_pfit.size);
8846 }
2fa2fe9a 8847
42db64ef
PZ		 8848 PIPE_CONF_CHECK_I(ips_enabled);
8849
282740f7
VS		 8850 PIPE_CONF_CHECK_I(double_wide);
8851
c0d43d62 8852 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8853 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8854 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8855 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8856 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8857
42571aef
VS		 8858 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8859 PIPE_CONF_CHECK_I(pipe_bpp);
8860
d71b8d4a 8861 if (!IS_HASWELL(dev)) {
241bfc38 8862 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8863 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8864 }
5e550656 8865
66e985c0 8866#undef PIPE_CONF_CHECK_X
08a24034 8867#undef PIPE_CONF_CHECK_I
1bd1bd80 8868#undef PIPE_CONF_CHECK_FLAGS
5e550656 8869#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8870#undef PIPE_CONF_QUIRK
88adfff1 8871
0e8ffe1b
DV		 8872 return true;
8873}
8874
91d1b4bd
DV		 8875static void
8876check_connector_state(struct drm_device *dev)
8af6cf88 8877{
8af6cf88
DV		 8878 struct intel_connector *connector;
8879
8880 list_for_each_entry(connector, &dev->mode_config.connector_list,
8881 base.head) {
8882 /* This also checks the encoder/connector hw state with the
8883 * ->get_hw_state callbacks. */
8884 intel_connector_check_state(connector);
8885
8886 WARN(&connector->new_encoder->base != connector->base.encoder,
8887 "connector's staged encoder doesn't match current encoder\n");
8888 }
91d1b4bd
DV		 8889}
8890
8891static void
8892check_encoder_state(struct drm_device *dev)
8893{
8894 struct intel_encoder *encoder;
8895 struct intel_connector *connector;
8af6cf88
DV		 8896
8897 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8898 base.head) {
8899 bool enabled = false;
8900 bool active = false;
8901 enum pipe pipe, tracked_pipe;
8902
8903 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8904 encoder->base.base.id,
8905 drm_get_encoder_name(&encoder->base));
8906
8907 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8908 "encoder's stage crtc doesn't match current crtc\n");
8909 WARN(encoder->connectors_active && !encoder->base.crtc,
8910 "encoder's active_connectors set, but no crtc\n");
8911
8912 list_for_each_entry(connector, &dev->mode_config.connector_list,
8913 base.head) {
8914 if (connector->base.encoder != &encoder->base)
8915 continue;
8916 enabled = true;
8917 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8918 active = true;
8919 }
8920 WARN(!!encoder->base.crtc != enabled,
8921 "encoder's enabled state mismatch "
8922 "(expected %i, found %i)\n",
8923 !!encoder->base.crtc, enabled);
8924 WARN(active && !encoder->base.crtc,
8925 "active encoder with no crtc\n");
8926
8927 WARN(encoder->connectors_active != active,
8928 "encoder's computed active state doesn't match tracked active state "
8929 "(expected %i, found %i)\n", active, encoder->connectors_active);
8930
8931 active = encoder->get_hw_state(encoder, &pipe);
8932 WARN(active != encoder->connectors_active,
8933 "encoder's hw state doesn't match sw tracking "
8934 "(expected %i, found %i)\n",
8935 encoder->connectors_active, active);
8936
8937 if (!encoder->base.crtc)
8938 continue;
8939
8940 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8941 WARN(active && pipe != tracked_pipe,
8942 "active encoder's pipe doesn't match"
8943 "(expected %i, found %i)\n",
8944 tracked_pipe, pipe);
8945
8946 }
91d1b4bd
DV		 8947}
8948
8949static void
8950check_crtc_state(struct drm_device *dev)
8951{
8952 drm_i915_private_t *dev_priv = dev->dev_private;
8953 struct intel_crtc *crtc;
8954 struct intel_encoder *encoder;
8955 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8956
8957 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8958 base.head) {
8959 bool enabled = false;
8960 bool active = false;
8961
045ac3b5
JB		 8962 memset(&pipe_config, 0, sizeof(pipe_config));
8963
8af6cf88
DV		 8964 DRM_DEBUG_KMS("[CRTC:%d]\n",
8965 crtc->base.base.id);
8966
8967 WARN(crtc->active && !crtc->base.enabled,
8968 "active crtc, but not enabled in sw tracking\n");
8969
8970 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8971 base.head) {
8972 if (encoder->base.crtc != &crtc->base)
8973 continue;
8974 enabled = true;
8975 if (encoder->connectors_active)
8976 active = true;
8977 }
6c49f241 8978
8af6cf88
DV		 8979 WARN(active != crtc->active,
8980 "crtc's computed active state doesn't match tracked active state "
8981 "(expected %i, found %i)\n", active, crtc->active);
8982 WARN(enabled != crtc->base.enabled,
8983 "crtc's computed enabled state doesn't match tracked enabled state "
8984 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8985
0e8ffe1b
DV		 8986 active = dev_priv->display.get_pipe_config(crtc,
8987 &pipe_config);
d62cf62a
DV		 8988
8989 /* hw state is inconsistent with the pipe A quirk */
8990 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8991 active = crtc->active;
8992
6c49f241
DV		 8993 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8994 base.head) {
3eaba51c 8995 enum pipe pipe;
6c49f241
DV		 8996 if (encoder->base.crtc != &crtc->base)
8997 continue;
3eaba51c
VS		 8998 if (encoder->get_config &&
8999 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9000 encoder->get_config(encoder, &pipe_config);
9001 }
9002
0e8ffe1b
DV		 9003 WARN(crtc->active != active,
9004 "crtc active state doesn't match with hw state "
9005 "(expected %i, found %i)\n", crtc->active, active);
9006
c0b03411
DV		 9007 if (active &&
9008 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9009 WARN(1, "pipe state doesn't match!\n");
9010 intel_dump_pipe_config(crtc, &pipe_config,
9011 "[hw state]");
9012 intel_dump_pipe_config(crtc, &crtc->config,
9013 "[sw state]");
9014 }
8af6cf88
DV		 9015 }
9016}
9017
91d1b4bd
DV		 9018static void
9019check_shared_dpll_state(struct drm_device *dev)
9020{
9021 drm_i915_private_t *dev_priv = dev->dev_private;
9022 struct intel_crtc *crtc;
9023 struct intel_dpll_hw_state dpll_hw_state;
9024 int i;
5358901f
DV		 9025
9026 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9027 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9028 int enabled_crtcs = 0, active_crtcs = 0;
9029 bool active;
9030
9031 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9032
9033 DRM_DEBUG_KMS("%s\n", pll->name);
9034
9035 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9036
9037 WARN(pll->active > pll->refcount,
9038 "more active pll users than references: %i vs %i\n",
9039 pll->active, pll->refcount);
9040 WARN(pll->active && !pll->on,
9041 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9042 WARN(pll->on && !pll->active,
9043 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9044 WARN(pll->on != active,
9045 "pll on state mismatch (expected %i, found %i)\n",
9046 pll->on, active);
9047
9048 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9049 base.head) {
9050 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9051 enabled_crtcs++;
9052 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9053 active_crtcs++;
9054 }
9055 WARN(pll->active != active_crtcs,
9056 "pll active crtcs mismatch (expected %i, found %i)\n",
9057 pll->active, active_crtcs);
9058 WARN(pll->refcount != enabled_crtcs,
9059 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9060 pll->refcount, enabled_crtcs);
66e985c0
DV		 9061
9062 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9063 sizeof(dpll_hw_state)),
9064 "pll hw state mismatch\n");
5358901f 9065 }
8af6cf88
DV		 9066}
9067
91d1b4bd
DV		 9068void
9069intel_modeset_check_state(struct drm_device *dev)
9070{
9071 check_connector_state(dev);
9072 check_encoder_state(dev);
9073 check_crtc_state(dev);
9074 check_shared_dpll_state(dev);
9075}
9076
18442d08
VS		 9077void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9078 int dotclock)
9079{
9080 /*
9081 * FDI already provided one idea for the dotclock.
9082 * Yell if the encoder disagrees.
9083 */
241bfc38 9084 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9085 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9086 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9087}
9088
f30da187
DV		 9089static int __intel_set_mode(struct drm_crtc *crtc,
9090 struct drm_display_mode *mode,
9091 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9092{
9093 struct drm_device *dev = crtc->dev;
dbf2b54e 9094 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9095 struct drm_display_mode *saved_mode, *saved_hwmode;
9096 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9097 struct intel_crtc *intel_crtc;
9098 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9099 int ret = 0;
a6778b3c 9100
a1e22653 9101 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9102 if (!saved_mode)
9103 return -ENOMEM;
3ac18232 9104 saved_hwmode = saved_mode + 1;
a6778b3c 9105
e2e1ed41 9106 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9107 &prepare_pipes, &disable_pipes);
9108
3ac18232
TG		 9109 *saved_hwmode = crtc->hwmode;
9110 *saved_mode = crtc->mode;
a6778b3c 9111
25c5b266
DV		 9112 /* Hack: Because we don't (yet) support global modeset on multiple
9113 * crtcs, we don't keep track of the new mode for more than one crtc.
9114 * Hence simply check whether any bit is set in modeset_pipes in all the
9115 * pieces of code that are not yet converted to deal with mutliple crtcs
9116 * changing their mode at the same time. */
25c5b266 9117 if (modeset_pipes) {
4e53c2e0 9118 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9119 if (IS_ERR(pipe_config)) {
9120 ret = PTR_ERR(pipe_config);
9121 pipe_config = NULL;
9122
3ac18232 9123 goto out;
25c5b266 9124 }
c0b03411
DV		 9125 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9126 "[modeset]");
25c5b266 9127 }
a6778b3c 9128
460da916
DV		 9129 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9130 intel_crtc_disable(&intel_crtc->base);
9131
ea9d758d
DV		 9132 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9133 if (intel_crtc->base.enabled)
9134 dev_priv->display.crtc_disable(&intel_crtc->base);
9135 }
a6778b3c 9136
6c4c86f5
DV		 9137 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9138 * to set it here already despite that we pass it down the callchain.
f6e5b160 9139 */
b8cecdf5 9140 if (modeset_pipes) {
25c5b266 9141 crtc->mode = *mode;
b8cecdf5
DV		 9142 /* mode_set/enable/disable functions rely on a correct pipe
9143 * config. */
9144 to_intel_crtc(crtc)->config = *pipe_config;
9145 }
7758a113 9146
ea9d758d
DV		 9147 /* Only after disabling all output pipelines that will be changed can we
9148 * update the the output configuration. */
9149 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9150
47fab737
DV		 9151 if (dev_priv->display.modeset_global_resources)
9152 dev_priv->display.modeset_global_resources(dev);
9153
a6778b3c
DV		 9154 /* Set up the DPLL and any encoders state that needs to adjust or depend
9155 * on the DPLL.
f6e5b160 9156 */
25c5b266 9157 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9158 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9159 x, y, fb);
9160 if (ret)
9161 goto done;
a6778b3c
DV		 9162 }
9163
9164 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9165 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9166 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9167
25c5b266
DV		 9168 if (modeset_pipes) {
9169 /* Store real post-adjustment hardware mode. */
b8cecdf5 9170 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9171
25c5b266
DV		 9172 /* Calculate and store various constants which
9173 * are later needed by vblank and swap-completion
9174 * timestamping. They are derived from true hwmode.
9175 */
9176 drm_calc_timestamping_constants(crtc);
9177 }
a6778b3c
DV		 9178
9179 /* FIXME: add subpixel order */
9180done:
c0c36b94 9181 if (ret && crtc->enabled) {
3ac18232
TG		 9182 crtc->hwmode = *saved_hwmode;
9183 crtc->mode = *saved_mode;
a6778b3c
DV		 9184 }
9185
3ac18232 9186out:
b8cecdf5 9187 kfree(pipe_config);
3ac18232 9188 kfree(saved_mode);
a6778b3c 9189 return ret;
f6e5b160
CW		 9190}
9191
e7457a9a
DL		 9192static int intel_set_mode(struct drm_crtc *crtc,
9193 struct drm_display_mode *mode,
9194 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9195{
9196 int ret;
9197
9198 ret = __intel_set_mode(crtc, mode, x, y, fb);
9199
9200 if (ret == 0)
9201 intel_modeset_check_state(crtc->dev);
9202
9203 return ret;
9204}
9205
c0c36b94
CW		 9206void intel_crtc_restore_mode(struct drm_crtc *crtc)
9207{
9208 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9209}
9210
25c5b266
DV		 9211#undef for_each_intel_crtc_masked
9212
d9e55608
DV		 9213static void intel_set_config_free(struct intel_set_config *config)
9214{
9215 if (!config)
9216 return;
9217
1aa4b628
DV		 9218 kfree(config->save_connector_encoders);
9219 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9220 kfree(config);
9221}
9222
85f9eb71
DV		 9223static int intel_set_config_save_state(struct drm_device *dev,
9224 struct intel_set_config *config)
9225{
85f9eb71
DV		 9226 struct drm_encoder *encoder;
9227 struct drm_connector *connector;
9228 int count;
9229
1aa4b628
DV		 9230 config->save_encoder_crtcs =
9231 kcalloc(dev->mode_config.num_encoder,
9232 sizeof(struct drm_crtc *), GFP_KERNEL);
9233 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9234 return -ENOMEM;
9235
1aa4b628
DV		 9236 config->save_connector_encoders =
9237 kcalloc(dev->mode_config.num_connector,
9238 sizeof(struct drm_encoder *), GFP_KERNEL);
9239 if (!config->save_connector_encoders)
85f9eb71
DV		 9240 return -ENOMEM;
9241
9242 /* Copy data. Note that driver private data is not affected.
9243 * Should anything bad happen only the expected state is
9244 * restored, not the drivers personal bookkeeping.
9245 */
85f9eb71
DV		 9246 count = 0;
9247 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9248 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9249 }
9250
9251 count = 0;
9252 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9253 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9254 }
9255
9256 return 0;
9257}
9258
9259static void intel_set_config_restore_state(struct drm_device *dev,
9260 struct intel_set_config *config)
9261{
9a935856
DV		 9262 struct intel_encoder *encoder;
9263 struct intel_connector *connector;
85f9eb71
DV		 9264 int count;
9265
85f9eb71 9266 count = 0;
9a935856
DV		 9267 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9268 encoder->new_crtc =
9269 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9270 }
9271
9272 count = 0;
9a935856
DV		 9273 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9274 connector->new_encoder =
9275 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9276 }
9277}
9278
e3de42b6 9279static bool
2e57f47d 9280is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9281{
9282 int i;
9283
2e57f47d
CW		 9284 if (set->num_connectors == 0)
9285 return false;
9286
9287 if (WARN_ON(set->connectors == NULL))
9288 return false;
9289
9290 for (i = 0; i < set->num_connectors; i++)
9291 if (set->connectors[i]->encoder &&
9292 set->connectors[i]->encoder->crtc == set->crtc &&
9293 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9294 return true;
9295
9296 return false;
9297}
9298
5e2b584e
DV		 9299static void
9300intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9301 struct intel_set_config *config)
9302{
9303
9304 /* We should be able to check here if the fb has the same properties
9305 * and then just flip_or_move it */
2e57f47d
CW		 9306 if (is_crtc_connector_off(set)) {
9307 config->mode_changed = true;
e3de42b6 9308 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9309 /* If we have no fb then treat it as a full mode set */
9310 if (set->crtc->fb == NULL) {
319d9827
JB		 9311 struct intel_crtc *intel_crtc =
9312 to_intel_crtc(set->crtc);
9313
9314 if (intel_crtc->active && i915_fastboot) {
9315 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9316 config->fb_changed = true;
9317 } else {
9318 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9319 config->mode_changed = true;
9320 }
5e2b584e
DV		 9321 } else if (set->fb == NULL) {
9322 config->mode_changed = true;
72f4901e
DV		 9323 } else if (set->fb->pixel_format !=
9324 set->crtc->fb->pixel_format) {
5e2b584e 9325 config->mode_changed = true;
e3de42b6 9326 } else {
5e2b584e 9327 config->fb_changed = true;
e3de42b6 9328 }
5e2b584e
DV		 9329 }
9330
835c5873 9331 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9332 config->fb_changed = true;
9333
9334 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9335 DRM_DEBUG_KMS("modes are different, full mode set\n");
9336 drm_mode_debug_printmodeline(&set->crtc->mode);
9337 drm_mode_debug_printmodeline(set->mode);
9338 config->mode_changed = true;
9339 }
a1d95703
CW		 9340
9341 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9342 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9343}
9344
2e431051 9345static int
9a935856
DV		 9346intel_modeset_stage_output_state(struct drm_device *dev,
9347 struct drm_mode_set *set,
9348 struct intel_set_config *config)
50f56119 9349{
85f9eb71 9350 struct drm_crtc *new_crtc;
9a935856
DV		 9351 struct intel_connector *connector;
9352 struct intel_encoder *encoder;
f3f08572 9353 int ro;
50f56119 9354
9abdda74 9355 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9356 * of connectors. For paranoia, double-check this. */
9357 WARN_ON(!set->fb && (set->num_connectors != 0));
9358 WARN_ON(set->fb && (set->num_connectors == 0));
9359
9a935856
DV		 9360 list_for_each_entry(connector, &dev->mode_config.connector_list,
9361 base.head) {
9362 /* Otherwise traverse passed in connector list and get encoders
9363 * for them. */
50f56119 9364 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9365 if (set->connectors[ro] == &connector->base) {
9366 connector->new_encoder = connector->encoder;
50f56119
DV		 9367 break;
9368 }
9369 }
9370
9a935856
DV		 9371 /* If we disable the crtc, disable all its connectors. Also, if
9372 * the connector is on the changing crtc but not on the new
9373 * connector list, disable it. */
9374 if ((!set->fb || ro == set->num_connectors) &&
9375 connector->base.encoder &&
9376 connector->base.encoder->crtc == set->crtc) {
9377 connector->new_encoder = NULL;
9378
9379 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9380 connector->base.base.id,
9381 drm_get_connector_name(&connector->base));
9382 }
9383
9384
9385 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9386 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9387 config->mode_changed = true;
50f56119
DV		 9388 }
9389 }
9a935856 9390 /* connector->new_encoder is now updated for all connectors. */
50f56119 9391
9a935856 9392 /* Update crtc of enabled connectors. */
9a935856
DV		 9393 list_for_each_entry(connector, &dev->mode_config.connector_list,
9394 base.head) {
9395 if (!connector->new_encoder)
50f56119
DV		 9396 continue;
9397
9a935856 9398 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9399
9400 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9401 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9402 new_crtc = set->crtc;
9403 }
9404
9405 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9406 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9407 new_crtc)) {
5e2b584e 9408 return -EINVAL;
50f56119 9409 }
9a935856
DV		 9410 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9411
9412 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9413 connector->base.base.id,
9414 drm_get_connector_name(&connector->base),
9415 new_crtc->base.id);
9416 }
9417
9418 /* Check for any encoders that needs to be disabled. */
9419 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9420 base.head) {
9421 list_for_each_entry(connector,
9422 &dev->mode_config.connector_list,
9423 base.head) {
9424 if (connector->new_encoder == encoder) {
9425 WARN_ON(!connector->new_encoder->new_crtc);
9426
9427 goto next_encoder;
9428 }
9429 }
9430 encoder->new_crtc = NULL;
9431next_encoder:
9432 /* Only now check for crtc changes so we don't miss encoders
9433 * that will be disabled. */
9434 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9435 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9436 config->mode_changed = true;
50f56119
DV		 9437 }
9438 }
9a935856 9439 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9440
2e431051
DV		 9441 return 0;
9442}
9443
9444static int intel_crtc_set_config(struct drm_mode_set *set)
9445{
9446 struct drm_device *dev;
2e431051
DV		 9447 struct drm_mode_set save_set;
9448 struct intel_set_config *config;
9449 int ret;
2e431051 9450
8d3e375e
DV		 9451 BUG_ON(!set);
9452 BUG_ON(!set->crtc);
9453 BUG_ON(!set->crtc->helper_private);
2e431051 9454
7e53f3a4
DV		 9455 /* Enforce sane interface api - has been abused by the fb helper. */
9456 BUG_ON(!set->mode && set->fb);
9457 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9458
2e431051
DV		 9459 if (set->fb) {
9460 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9461 set->crtc->base.id, set->fb->base.id,
9462 (int)set->num_connectors, set->x, set->y);
9463 } else {
9464 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9465 }
9466
9467 dev = set->crtc->dev;
9468
9469 ret = -ENOMEM;
9470 config = kzalloc(sizeof(*config), GFP_KERNEL);
9471 if (!config)
9472 goto out_config;
9473
9474 ret = intel_set_config_save_state(dev, config);
9475 if (ret)
9476 goto out_config;
9477
9478 save_set.crtc = set->crtc;
9479 save_set.mode = &set->crtc->mode;
9480 save_set.x = set->crtc->x;
9481 save_set.y = set->crtc->y;
9482 save_set.fb = set->crtc->fb;
9483
9484 /* Compute whether we need a full modeset, only an fb base update or no
9485 * change at all. In the future we might also check whether only the
9486 * mode changed, e.g. for LVDS where we only change the panel fitter in
9487 * such cases. */
9488 intel_set_config_compute_mode_changes(set, config);
9489
9a935856 9490 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9491 if (ret)
9492 goto fail;
9493
5e2b584e 9494 if (config->mode_changed) {
c0c36b94
CW		 9495 ret = intel_set_mode(set->crtc, set->mode,
9496 set->x, set->y, set->fb);
5e2b584e 9497 } else if (config->fb_changed) {
4878cae2
VS		 9498 intel_crtc_wait_for_pending_flips(set->crtc);
9499
4f660f49 9500 ret = intel_pipe_set_base(set->crtc,
94352cf9 9501 set->x, set->y, set->fb);
50f56119
DV		 9502 }
9503
2d05eae1 9504 if (ret) {
bf67dfeb
DV		 9505 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9506 set->crtc->base.id, ret);
50f56119 9507fail:
2d05eae1 9508 intel_set_config_restore_state(dev, config);
50f56119 9509
2d05eae1
CW		 9510 /* Try to restore the config */
9511 if (config->mode_changed &&
9512 intel_set_mode(save_set.crtc, save_set.mode,
9513 save_set.x, save_set.y, save_set.fb))
9514 DRM_ERROR("failed to restore config after modeset failure\n");
9515 }
50f56119 9516
d9e55608
DV		 9517out_config:
9518 intel_set_config_free(config);
50f56119
DV		 9519 return ret;
9520}
f6e5b160
CW		 9521
9522static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9523 .cursor_set = intel_crtc_cursor_set,
9524 .cursor_move = intel_crtc_cursor_move,
9525 .gamma_set = intel_crtc_gamma_set,
50f56119 9526 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9527 .destroy = intel_crtc_destroy,
9528 .page_flip = intel_crtc_page_flip,
9529};
9530
79f689aa
PZ		 9531static void intel_cpu_pll_init(struct drm_device *dev)
9532{
affa9354 9533 if (HAS_DDI(dev))
79f689aa
PZ		 9534 intel_ddi_pll_init(dev);
9535}
9536
5358901f
DV		 9537static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9538 struct intel_shared_dpll *pll,
9539 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9540{
5358901f 9541 uint32_t val;
ee7b9f93 9542
5358901f 9543 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9544 hw_state->dpll = val;
9545 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9546 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9547
9548 return val & DPLL_VCO_ENABLE;
9549}
9550
15bdd4cf
DV		 9551static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9552 struct intel_shared_dpll *pll)
9553{
9554 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9555 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9556}
9557
e7b903d2
DV		 9558static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9559 struct intel_shared_dpll *pll)
9560{
e7b903d2
DV		 9561 /* PCH refclock must be enabled first */
9562 assert_pch_refclk_enabled(dev_priv);
9563
15bdd4cf
DV		 9564 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9565
9566 /* Wait for the clocks to stabilize. */
9567 POSTING_READ(PCH_DPLL(pll->id));
9568 udelay(150);
9569
9570 /* The pixel multiplier can only be updated once the
9571 * DPLL is enabled and the clocks are stable.
9572 *
9573 * So write it again.
9574 */
9575 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9576 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9577 udelay(200);
9578}
9579
9580static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9581 struct intel_shared_dpll *pll)
9582{
9583 struct drm_device *dev = dev_priv->dev;
9584 struct intel_crtc *crtc;
e7b903d2
DV		 9585
9586 /* Make sure no transcoder isn't still depending on us. */
9587 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9588 if (intel_crtc_to_shared_dpll(crtc) == pll)
9589 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9590 }
9591
15bdd4cf
DV		 9592 I915_WRITE(PCH_DPLL(pll->id), 0);
9593 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9594 udelay(200);
9595}
9596
46edb027
DV		 9597static char *ibx_pch_dpll_names[] = {
9598 "PCH DPLL A",
9599 "PCH DPLL B",
9600};
9601
7c74ade1 9602static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9603{
e7b903d2 9604 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9605 int i;
9606
7c74ade1 9607 dev_priv->num_shared_dpll = 2;
ee7b9f93 9608
e72f9fbf 9609 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9610 dev_priv->shared_dplls[i].id = i;
9611 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9612 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9613 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9614 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9615 dev_priv->shared_dplls[i].get_hw_state =
9616 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9617 }
9618}
9619
7c74ade1
DV		 9620static void intel_shared_dpll_init(struct drm_device *dev)
9621{
e7b903d2 9622 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9623
9624 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9625 ibx_pch_dpll_init(dev);
9626 else
9627 dev_priv->num_shared_dpll = 0;
9628
9629 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9630 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9631 dev_priv->num_shared_dpll);
9632}
9633
b358d0a6 9634static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9635{
22fd0fab 9636 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9637 struct intel_crtc *intel_crtc;
9638 int i;
9639
955382f3 9640 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9641 if (intel_crtc == NULL)
9642 return;
9643
9644 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9645
9646 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9647 for (i = 0; i < 256; i++) {
9648 intel_crtc->lut_r[i] = i;
9649 intel_crtc->lut_g[i] = i;
9650 intel_crtc->lut_b[i] = i;
9651 }
9652
80824003
JB		 9653 /* Swap pipes & planes for FBC on pre-965 */
9654 intel_crtc->pipe = pipe;
9655 intel_crtc->plane = pipe;
e2e767ab 9656 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9657 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9658 intel_crtc->plane = !pipe;
80824003
JB		 9659 }
9660
22fd0fab
JB		 9661 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9662 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9663 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9664 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9665
79e53945 9666 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9667}
9668
08d7b3d1 9669int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9670 struct drm_file *file)
08d7b3d1 9671{
08d7b3d1 9672 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9673 struct drm_mode_object *drmmode_obj;
9674 struct intel_crtc *crtc;
08d7b3d1 9675
1cff8f6b
DV		 9676 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9677 return -ENODEV;
08d7b3d1 9678
c05422d5
DV		 9679 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9680 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9681
c05422d5 9682 if (!drmmode_obj) {
08d7b3d1
CW		 9683 DRM_ERROR("no such CRTC id\n");
9684 return -EINVAL;
9685 }
9686
c05422d5
DV		 9687 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9688 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9689
c05422d5 9690 return 0;
08d7b3d1
CW		 9691}
9692
66a9278e 9693static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9694{
66a9278e
DV		 9695 struct drm_device *dev = encoder->base.dev;
9696 struct intel_encoder *source_encoder;
79e53945 9697 int index_mask = 0;
79e53945
JB		 9698 int entry = 0;
9699
66a9278e
DV		 9700 list_for_each_entry(source_encoder,
9701 &dev->mode_config.encoder_list, base.head) {
9702
9703 if (encoder == source_encoder)
79e53945 9704 index_mask |= (1 << entry);
66a9278e
DV		 9705
9706 /* Intel hw has only one MUX where enocoders could be cloned. */
9707 if (encoder->cloneable && source_encoder->cloneable)
9708 index_mask |= (1 << entry);
9709
79e53945
JB		 9710 entry++;
9711 }
4ef69c7a 9712
79e53945
JB		 9713 return index_mask;
9714}
9715
4d302442
CW		 9716static bool has_edp_a(struct drm_device *dev)
9717{
9718 struct drm_i915_private *dev_priv = dev->dev_private;
9719
9720 if (!IS_MOBILE(dev))
9721 return false;
9722
9723 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9724 return false;
9725
9726 if (IS_GEN5(dev) &&
9727 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9728 return false;
9729
9730 return true;
9731}
9732
79e53945
JB		 9733static void intel_setup_outputs(struct drm_device *dev)
9734{
725e30ad 9735 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9736 struct intel_encoder *encoder;
cb0953d7 9737 bool dpd_is_edp = false;
79e53945 9738
c9093354 9739 intel_lvds_init(dev);
79e53945 9740
c40c0f5b 9741 if (!IS_ULT(dev))
79935fca 9742 intel_crt_init(dev);
cb0953d7 9743
affa9354 9744 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9745 int found;
9746
9747 /* Haswell uses DDI functions to detect digital outputs */
9748 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9749 /* DDI A only supports eDP */
9750 if (found)
9751 intel_ddi_init(dev, PORT_A);
9752
9753 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9754 * register */
9755 found = I915_READ(SFUSE_STRAP);
9756
9757 if (found & SFUSE_STRAP_DDIB_DETECTED)
9758 intel_ddi_init(dev, PORT_B);
9759 if (found & SFUSE_STRAP_DDIC_DETECTED)
9760 intel_ddi_init(dev, PORT_C);
9761 if (found & SFUSE_STRAP_DDID_DETECTED)
9762 intel_ddi_init(dev, PORT_D);
9763 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9764 int found;
270b3042
DV		 9765 dpd_is_edp = intel_dpd_is_edp(dev);
9766
9767 if (has_edp_a(dev))
9768 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9769
dc0fa718 9770 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9771 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9772 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9773 if (!found)
e2debe91 9774 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9775 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9776 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9777 }
9778
dc0fa718 9779 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9780 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9781
dc0fa718 9782 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9783 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9784
5eb08b69 9785 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9786 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9787
270b3042 9788 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9789 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9790 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9791 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9792 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9793 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9794 PORT_C);
9795 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9796 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9797 PORT_C);
9798 }
19c03924 9799
dc0fa718 9800 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9801 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9802 PORT_B);
67cfc203
VS		 9803 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9804 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9805 }
3cfca973
JN		 9806
9807 intel_dsi_init(dev);
103a196f 9808 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9809 bool found = false;
7d57382e 9810
e2debe91 9811 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9812 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9813 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9814 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9815 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9816 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9817 }
27185ae1 9818
e7281eab 9819 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9820 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9821 }
13520b05
KH		 9822
9823 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9824
e2debe91 9825 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9826 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9827 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9828 }
27185ae1 9829
e2debe91 9830 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9831
b01f2c3a
JB		 9832 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9833 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9834 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9835 }
e7281eab 9836 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9837 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9838 }
27185ae1 9839
b01f2c3a 9840 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9841 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9842 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9843 } else if (IS_GEN2(dev))
79e53945
JB		 9844 intel_dvo_init(dev);
9845
103a196f 9846 if (SUPPORTS_TV(dev))
79e53945
JB		 9847 intel_tv_init(dev);
9848
4ef69c7a
CW		 9849 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9850 encoder->base.possible_crtcs = encoder->crtc_mask;
9851 encoder->base.possible_clones =
66a9278e 9852 intel_encoder_clones(encoder);
79e53945 9853 }
47356eb6 9854
dde86e2d 9855 intel_init_pch_refclk(dev);
270b3042
DV		 9856
9857 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9858}
9859
ddfe1567
CW		 9860void intel_framebuffer_fini(struct intel_framebuffer *fb)
9861{
9862 drm_framebuffer_cleanup(&fb->base);
9863 drm_gem_object_unreference_unlocked(&fb->obj->base);
9864}
9865
79e53945
JB		 9866static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9867{
9868 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9869
ddfe1567 9870 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9871 kfree(intel_fb);
9872}
9873
9874static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9875 struct drm_file *file,
79e53945
JB		 9876 unsigned int *handle)
9877{
9878 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9879 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9880
05394f39 9881 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9882}
9883
9884static const struct drm_framebuffer_funcs intel_fb_funcs = {
9885 .destroy = intel_user_framebuffer_destroy,
9886 .create_handle = intel_user_framebuffer_create_handle,
9887};
9888
38651674
DA		 9889int intel_framebuffer_init(struct drm_device *dev,
9890 struct intel_framebuffer *intel_fb,
308e5bcb 9891 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9892 struct drm_i915_gem_object *obj)
79e53945 9893{
a35cdaa0 9894 int pitch_limit;
79e53945
JB		 9895 int ret;
9896
c16ed4be
CW		 9897 if (obj->tiling_mode == I915_TILING_Y) {
9898 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9899 return -EINVAL;
c16ed4be 9900 }
57cd6508 9901
c16ed4be
CW		 9902 if (mode_cmd->pitches[0] & 63) {
9903 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9904 mode_cmd->pitches[0]);
57cd6508 9905 return -EINVAL;
c16ed4be 9906 }
57cd6508 9907
a35cdaa0
CW		 9908 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9909 pitch_limit = 32*1024;
9910 } else if (INTEL_INFO(dev)->gen >= 4) {
9911 if (obj->tiling_mode)
9912 pitch_limit = 16*1024;
9913 else
9914 pitch_limit = 32*1024;
9915 } else if (INTEL_INFO(dev)->gen >= 3) {
9916 if (obj->tiling_mode)
9917 pitch_limit = 8*1024;
9918 else
9919 pitch_limit = 16*1024;
9920 } else
9921 /* XXX DSPC is limited to 4k tiled */
9922 pitch_limit = 8*1024;
9923
9924 if (mode_cmd->pitches[0] > pitch_limit) {
9925 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9926 obj->tiling_mode ? "tiled" : "linear",
9927 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9928 return -EINVAL;
c16ed4be 9929 }
5d7bd705
VS		 9930
9931 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9932 mode_cmd->pitches[0] != obj->stride) {
9933 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9934 mode_cmd->pitches[0], obj->stride);
5d7bd705 9935 return -EINVAL;
c16ed4be 9936 }
5d7bd705 9937
57779d06 9938 /* Reject formats not supported by any plane early. */
308e5bcb 9939 switch (mode_cmd->pixel_format) {
57779d06 9940 case DRM_FORMAT_C8:
04b3924d
VS		 9941 case DRM_FORMAT_RGB565:
9942 case DRM_FORMAT_XRGB8888:
9943 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9944 break;
9945 case DRM_FORMAT_XRGB1555:
9946 case DRM_FORMAT_ARGB1555:
c16ed4be 9947 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9948 DRM_DEBUG("unsupported pixel format: %s\n",
9949 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9950 return -EINVAL;
c16ed4be 9951 }
57779d06
VS		 9952 break;
9953 case DRM_FORMAT_XBGR8888:
9954 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9955 case DRM_FORMAT_XRGB2101010:
9956 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9957 case DRM_FORMAT_XBGR2101010:
9958 case DRM_FORMAT_ABGR2101010:
c16ed4be 9959 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9960 DRM_DEBUG("unsupported pixel format: %s\n",
9961 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9962 return -EINVAL;
c16ed4be 9963 }
b5626747 9964 break;
04b3924d
VS		 9965 case DRM_FORMAT_YUYV:
9966 case DRM_FORMAT_UYVY:
9967 case DRM_FORMAT_YVYU:
9968 case DRM_FORMAT_VYUY:
c16ed4be 9969 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9970 DRM_DEBUG("unsupported pixel format: %s\n",
9971 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9972 return -EINVAL;
c16ed4be 9973 }
57cd6508
CW		 9974 break;
9975 default:
4ee62c76
VS		 9976 DRM_DEBUG("unsupported pixel format: %s\n",
9977 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9978 return -EINVAL;
9979 }
9980
90f9a336
VS		 9981 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9982 if (mode_cmd->offsets[0] != 0)
9983 return -EINVAL;
9984
c7d73f6a
DV		 9985 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9986 intel_fb->obj = obj;
9987
79e53945
JB		 9988 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9989 if (ret) {
9990 DRM_ERROR("framebuffer init failed %d\n", ret);
9991 return ret;
9992 }
9993
79e53945
JB		 9994 return 0;
9995}
9996
79e53945
JB		 9997static struct drm_framebuffer *
9998intel_user_framebuffer_create(struct drm_device *dev,
9999 struct drm_file *filp,
308e5bcb 10000 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10001{
05394f39 10002 struct drm_i915_gem_object *obj;
79e53945 10003
308e5bcb
JB		 10004 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10005 mode_cmd->handles[0]));
c8725226 10006 if (&obj->base == NULL)
cce13ff7 10007 return ERR_PTR(-ENOENT);
79e53945 10008
d2dff872 10009 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10010}
10011
79e53945 10012static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10013 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 10014 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 10015};
10016
e70236a8
JB		 10017/* Set up chip specific display functions */
10018static void intel_init_display(struct drm_device *dev)
10019{
10020 struct drm_i915_private *dev_priv = dev->dev_private;
10021
ee9300bb
DV		 10022 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10023 dev_priv->display.find_dpll = g4x_find_best_dpll;
10024 else if (IS_VALLEYVIEW(dev))
10025 dev_priv->display.find_dpll = vlv_find_best_dpll;
10026 else if (IS_PINEVIEW(dev))
10027 dev_priv->display.find_dpll = pnv_find_best_dpll;
10028 else
10029 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10030
affa9354 10031 if (HAS_DDI(dev)) {
0e8ffe1b 10032 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10033 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10034 dev_priv->display.crtc_enable = haswell_crtc_enable;
10035 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10036 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10037 dev_priv->display.update_plane = ironlake_update_plane;
10038 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10039 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10040 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10041 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10042 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10043 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10044 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10045 } else if (IS_VALLEYVIEW(dev)) {
10046 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10047 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10048 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10049 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10050 dev_priv->display.off = i9xx_crtc_off;
10051 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10052 } else {
0e8ffe1b 10053 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10054 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10055 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10056 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10057 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10058 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10059 }
e70236a8 10060
e70236a8 10061 /* Returns the core display clock speed */
25eb05fc
JB		 10062 if (IS_VALLEYVIEW(dev))
10063 dev_priv->display.get_display_clock_speed =
10064 valleyview_get_display_clock_speed;
10065 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10066 dev_priv->display.get_display_clock_speed =
10067 i945_get_display_clock_speed;
10068 else if (IS_I915G(dev))
10069 dev_priv->display.get_display_clock_speed =
10070 i915_get_display_clock_speed;
257a7ffc 10071 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10072 dev_priv->display.get_display_clock_speed =
10073 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10074 else if (IS_PINEVIEW(dev))
10075 dev_priv->display.get_display_clock_speed =
10076 pnv_get_display_clock_speed;
e70236a8
JB		 10077 else if (IS_I915GM(dev))
10078 dev_priv->display.get_display_clock_speed =
10079 i915gm_get_display_clock_speed;
10080 else if (IS_I865G(dev))
10081 dev_priv->display.get_display_clock_speed =
10082 i865_get_display_clock_speed;
f0f8a9ce 10083 else if (IS_I85X(dev))
e70236a8
JB		 10084 dev_priv->display.get_display_clock_speed =
10085 i855_get_display_clock_speed;
10086 else /* 852, 830 */
10087 dev_priv->display.get_display_clock_speed =
10088 i830_get_display_clock_speed;
10089
7f8a8569 10090 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10091 if (IS_GEN5(dev)) {
674cf967 10092 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10093 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10094 } else if (IS_GEN6(dev)) {
674cf967 10095 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10096 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10097 } else if (IS_IVYBRIDGE(dev)) {
10098 /* FIXME: detect B0+ stepping and use auto training */
10099 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10100 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10101 dev_priv->display.modeset_global_resources =
10102 ivb_modeset_global_resources;
c82e4d26
ED		 10103 } else if (IS_HASWELL(dev)) {
10104 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10105 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10106 dev_priv->display.modeset_global_resources =
10107 haswell_modeset_global_resources;
a0e63c22 10108 }
6067aaea 10109 } else if (IS_G4X(dev)) {
e0dac65e 10110 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10111 }
8c9f3aaf
JB		 10112
10113 /* Default just returns -ENODEV to indicate unsupported */
10114 dev_priv->display.queue_flip = intel_default_queue_flip;
10115
10116 switch (INTEL_INFO(dev)->gen) {
10117 case 2:
10118 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10119 break;
10120
10121 case 3:
10122 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10123 break;
10124
10125 case 4:
10126 case 5:
10127 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10128 break;
10129
10130 case 6:
10131 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10132 break;
7c9017e5
JB		 10133 case 7:
10134 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10135 break;
8c9f3aaf 10136 }
e70236a8
JB		 10137}
10138
b690e96c
JB		 10139/*
10140 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10141 * resume, or other times. This quirk makes sure that's the case for
10142 * affected systems.
10143 */
0206e353 10144static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10145{
10146 struct drm_i915_private *dev_priv = dev->dev_private;
10147
10148 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10149 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10150}
10151
435793df
KP		 10152/*
10153 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10154 */
10155static void quirk_ssc_force_disable(struct drm_device *dev)
10156{
10157 struct drm_i915_private *dev_priv = dev->dev_private;
10158 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10159 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10160}
10161
4dca20ef 10162/*
5a15ab5b
CE		 10163 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10164 * brightness value
4dca20ef
CE		 10165 */
10166static void quirk_invert_brightness(struct drm_device *dev)
10167{
10168 struct drm_i915_private *dev_priv = dev->dev_private;
10169 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10170 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10171}
10172
e85843be
KM		 10173/*
10174 * Some machines (Dell XPS13) suffer broken backlight controls if
10175 * BLM_PCH_PWM_ENABLE is set.
10176 */
10177static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10178{
10179 struct drm_i915_private *dev_priv = dev->dev_private;
10180 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10181 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10182}
10183
b690e96c
JB		 10184struct intel_quirk {
10185 int device;
10186 int subsystem_vendor;
10187 int subsystem_device;
10188 void (*hook)(struct drm_device *dev);
10189};
10190
5f85f176
EE		 10191/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10192struct intel_dmi_quirk {
10193 void (*hook)(struct drm_device *dev);
10194 const struct dmi_system_id (*dmi_id_list)[];
10195};
10196
10197static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10198{
10199 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10200 return 1;
10201}
10202
10203static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10204 {
10205 .dmi_id_list = &(const struct dmi_system_id[]) {
10206 {
10207 .callback = intel_dmi_reverse_brightness,
10208 .ident = "NCR Corporation",
10209 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10210 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10211 },
10212 },
10213 { } /* terminating entry */
10214 },
10215 .hook = quirk_invert_brightness,
10216 },
10217};
10218
c43b5634 10219static struct intel_quirk intel_quirks[] = {
b690e96c 10220 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10221 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10222
b690e96c
JB		 10223 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10224 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10225
b690e96c
JB		 10226 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10227 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10228
ccd0d36e 10229 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10230 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10231 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10232
10233 /* Lenovo U160 cannot use SSC on LVDS */
10234 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10235
10236 /* Sony Vaio Y cannot use SSC on LVDS */
10237 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10238
ee1452d7
JN		 10239 /*
10240 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10241 * seem to use inverted backlight PWM.
10242 */
10243 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10244
10245 /* Dell XPS13 HD Sandy Bridge */
10246 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10247 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10248 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10249};
10250
10251static void intel_init_quirks(struct drm_device *dev)
10252{
10253 struct pci_dev *d = dev->pdev;
10254 int i;
10255
10256 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10257 struct intel_quirk *q = &intel_quirks[i];
10258
10259 if (d->device == q->device &&
10260 (d->subsystem_vendor == q->subsystem_vendor ||
10261 q->subsystem_vendor == PCI_ANY_ID) &&
10262 (d->subsystem_device == q->subsystem_device ||
10263 q->subsystem_device == PCI_ANY_ID))
10264 q->hook(dev);
10265 }
5f85f176
EE		 10266 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10267 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10268 intel_dmi_quirks[i].hook(dev);
10269 }
b690e96c
JB		 10270}
10271
9cce37f4
JB		 10272/* Disable the VGA plane that we never use */
10273static void i915_disable_vga(struct drm_device *dev)
10274{
10275 struct drm_i915_private *dev_priv = dev->dev_private;
10276 u8 sr1;
766aa1c4 10277 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10278
10279 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10280 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10281 sr1 = inb(VGA_SR_DATA);
10282 outb(sr1 | 1<<5, VGA_SR_DATA);
10283 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10284 udelay(300);
10285
10286 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10287 POSTING_READ(vga_reg);
10288}
10289
6e1b4fda 10290static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10291{
10292 /* Enable VGA memory on Intel HD */
10293 if (HAS_PCH_SPLIT(dev)) {
10294 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10295 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10296 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10297 VGA_RSRC_LEGACY_MEM |
10298 VGA_RSRC_NORMAL_IO |
10299 VGA_RSRC_NORMAL_MEM);
10300 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10301 }
10302}
10303
6e1b4fda
VS		 10304void i915_disable_vga_mem(struct drm_device *dev)
10305{
10306 /* Disable VGA memory on Intel HD */
10307 if (HAS_PCH_SPLIT(dev)) {
10308 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10309 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10310 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10311 VGA_RSRC_NORMAL_IO |
10312 VGA_RSRC_NORMAL_MEM);
10313 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10314 }
10315}
10316
f817586c
DV		 10317void intel_modeset_init_hw(struct drm_device *dev)
10318{
f6071166
JB		 10319 struct drm_i915_private *dev_priv = dev->dev_private;
10320
a8f78b58
ED		 10321 intel_prepare_ddi(dev);
10322
f817586c
DV		 10323 intel_init_clock_gating(dev);
10324
f6071166
JB		 10325 /* Enable the CRI clock source so we can get at the display */
10326 if (IS_VALLEYVIEW(dev))
10327 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10328 DPLL_INTEGRATED_CRI_CLK_VLV);
10329
79f5b2c7 10330 mutex_lock(&dev->struct_mutex);
8090c6b9 10331 intel_enable_gt_powersave(dev);
79f5b2c7 10332 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10333}
10334
7d708ee4
ID		 10335void intel_modeset_suspend_hw(struct drm_device *dev)
10336{
10337 intel_suspend_hw(dev);
10338}
10339
79e53945
JB		 10340void intel_modeset_init(struct drm_device *dev)
10341{
652c393a 10342 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10343 int i, j, ret;
79e53945
JB		 10344
10345 drm_mode_config_init(dev);
10346
10347 dev->mode_config.min_width = 0;
10348 dev->mode_config.min_height = 0;
10349
019d96cb
DA		 10350 dev->mode_config.preferred_depth = 24;
10351 dev->mode_config.prefer_shadow = 1;
10352
e6ecefaa 10353 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10354
b690e96c
JB		 10355 intel_init_quirks(dev);
10356
1fa61106
ED		 10357 intel_init_pm(dev);
10358
e3c74757
BW		 10359 if (INTEL_INFO(dev)->num_pipes == 0)
10360 return;
10361
e70236a8
JB		 10362 intel_init_display(dev);
10363
a6c45cf0
CW		 10364 if (IS_GEN2(dev)) {
10365 dev->mode_config.max_width = 2048;
10366 dev->mode_config.max_height = 2048;
10367 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10368 dev->mode_config.max_width = 4096;
10369 dev->mode_config.max_height = 4096;
79e53945 10370 } else {
a6c45cf0
CW		 10371 dev->mode_config.max_width = 8192;
10372 dev->mode_config.max_height = 8192;
79e53945 10373 }
5d4545ae 10374 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10375
28c97730 10376 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10377 INTEL_INFO(dev)->num_pipes,
10378 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10379
08e2a7de 10380 for_each_pipe(i) {
79e53945 10381 intel_crtc_init(dev, i);
7f1f3851
JB		 10382 for (j = 0; j < dev_priv->num_plane; j++) {
10383 ret = intel_plane_init(dev, i, j);
10384 if (ret)
06da8da2
VS		 10385 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10386 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10387 }
79e53945
JB		 10388 }
10389
79f689aa 10390 intel_cpu_pll_init(dev);
e72f9fbf 10391 intel_shared_dpll_init(dev);
ee7b9f93 10392
9cce37f4
JB		 10393 /* Just disable it once at startup */
10394 i915_disable_vga(dev);
79e53945 10395 intel_setup_outputs(dev);
11be49eb
CW		 10396
10397 /* Just in case the BIOS is doing something questionable. */
10398 intel_disable_fbc(dev);
2c7111db
CW		 10399}
10400
24929352
DV		 10401static void
10402intel_connector_break_all_links(struct intel_connector *connector)
10403{
10404 connector->base.dpms = DRM_MODE_DPMS_OFF;
10405 connector->base.encoder = NULL;
10406 connector->encoder->connectors_active = false;
10407 connector->encoder->base.crtc = NULL;
10408}
10409
7fad798e
DV		 10410static void intel_enable_pipe_a(struct drm_device *dev)
10411{
10412 struct intel_connector *connector;
10413 struct drm_connector *crt = NULL;
10414 struct intel_load_detect_pipe load_detect_temp;
10415
10416 /* We can't just switch on the pipe A, we need to set things up with a
10417 * proper mode and output configuration. As a gross hack, enable pipe A
10418 * by enabling the load detect pipe once. */
10419 list_for_each_entry(connector,
10420 &dev->mode_config.connector_list,
10421 base.head) {
10422 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10423 crt = &connector->base;
10424 break;
10425 }
10426 }
10427
10428 if (!crt)
10429 return;
10430
10431 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10432 intel_release_load_detect_pipe(crt, &load_detect_temp);
10433
652c393a 10434
7fad798e
DV		 10435}
10436
fa555837
DV		 10437static bool
10438intel_check_plane_mapping(struct intel_crtc *crtc)
10439{
7eb552ae
BW		 10440 struct drm_device *dev = crtc->base.dev;
10441 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10442 u32 reg, val;
10443
7eb552ae 10444 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10445 return true;
10446
10447 reg = DSPCNTR(!crtc->plane);
10448 val = I915_READ(reg);
10449
10450 if ((val & DISPLAY_PLANE_ENABLE) &&
10451 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10452 return false;
10453
10454 return true;
10455}
10456
24929352
DV		 10457static void intel_sanitize_crtc(struct intel_crtc *crtc)
10458{
10459 struct drm_device *dev = crtc->base.dev;
10460 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10461 u32 reg;
24929352 10462
24929352 10463 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10464 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10465 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10466
10467 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10468 * disable the crtc (and hence change the state) if it is wrong. Note
10469 * that gen4+ has a fixed plane -> pipe mapping. */
10470 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10471 struct intel_connector *connector;
10472 bool plane;
10473
24929352
DV		 10474 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10475 crtc->base.base.id);
10476
10477 /* Pipe has the wrong plane attached and the plane is active.
10478 * Temporarily change the plane mapping and disable everything
10479 * ... */
10480 plane = crtc->plane;
10481 crtc->plane = !plane;
10482 dev_priv->display.crtc_disable(&crtc->base);
10483 crtc->plane = plane;
10484
10485 /* ... and break all links. */
10486 list_for_each_entry(connector, &dev->mode_config.connector_list,
10487 base.head) {
10488 if (connector->encoder->base.crtc != &crtc->base)
10489 continue;
10490
10491 intel_connector_break_all_links(connector);
10492 }
10493
10494 WARN_ON(crtc->active);
10495 crtc->base.enabled = false;
10496 }
24929352 10497
7fad798e
DV		 10498 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10499 crtc->pipe == PIPE_A && !crtc->active) {
10500 /* BIOS forgot to enable pipe A, this mostly happens after
10501 * resume. Force-enable the pipe to fix this, the update_dpms
10502 * call below we restore the pipe to the right state, but leave
10503 * the required bits on. */
10504 intel_enable_pipe_a(dev);
10505 }
10506
24929352
DV		 10507 /* Adjust the state of the output pipe according to whether we
10508 * have active connectors/encoders. */
10509 intel_crtc_update_dpms(&crtc->base);
10510
10511 if (crtc->active != crtc->base.enabled) {
10512 struct intel_encoder *encoder;
10513
10514 /* This can happen either due to bugs in the get_hw_state
10515 * functions or because the pipe is force-enabled due to the
10516 * pipe A quirk. */
10517 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10518 crtc->base.base.id,
10519 crtc->base.enabled ? "enabled" : "disabled",
10520 crtc->active ? "enabled" : "disabled");
10521
10522 crtc->base.enabled = crtc->active;
10523
10524 /* Because we only establish the connector -> encoder ->
10525 * crtc links if something is active, this means the
10526 * crtc is now deactivated. Break the links. connector
10527 * -> encoder links are only establish when things are
10528 * actually up, hence no need to break them. */
10529 WARN_ON(crtc->active);
10530
10531 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10532 WARN_ON(encoder->connectors_active);
10533 encoder->base.crtc = NULL;
10534 }
10535 }
10536}
10537
10538static void intel_sanitize_encoder(struct intel_encoder *encoder)
10539{
10540 struct intel_connector *connector;
10541 struct drm_device *dev = encoder->base.dev;
10542
10543 /* We need to check both for a crtc link (meaning that the
10544 * encoder is active and trying to read from a pipe) and the
10545 * pipe itself being active. */
10546 bool has_active_crtc = encoder->base.crtc &&
10547 to_intel_crtc(encoder->base.crtc)->active;
10548
10549 if (encoder->connectors_active && !has_active_crtc) {
10550 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10551 encoder->base.base.id,
10552 drm_get_encoder_name(&encoder->base));
10553
10554 /* Connector is active, but has no active pipe. This is
10555 * fallout from our resume register restoring. Disable
10556 * the encoder manually again. */
10557 if (encoder->base.crtc) {
10558 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10559 encoder->base.base.id,
10560 drm_get_encoder_name(&encoder->base));
10561 encoder->disable(encoder);
10562 }
10563
10564 /* Inconsistent output/port/pipe state happens presumably due to
10565 * a bug in one of the get_hw_state functions. Or someplace else
10566 * in our code, like the register restore mess on resume. Clamp
10567 * things to off as a safer default. */
10568 list_for_each_entry(connector,
10569 &dev->mode_config.connector_list,
10570 base.head) {
10571 if (connector->encoder != encoder)
10572 continue;
10573
10574 intel_connector_break_all_links(connector);
10575 }
10576 }
10577 /* Enabled encoders without active connectors will be fixed in
10578 * the crtc fixup. */
10579}
10580
44cec740 10581void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10582{
10583 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10584 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10585
8dc8a27c
PZ		 10586 /* This function can be called both from intel_modeset_setup_hw_state or
10587 * at a very early point in our resume sequence, where the power well
10588 * structures are not yet restored. Since this function is at a very
10589 * paranoid "someone might have enabled VGA while we were not looking"
10590 * level, just check if the power well is enabled instead of trying to
10591 * follow the "don't touch the power well if we don't need it" policy
10592 * the rest of the driver uses. */
10593 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10594 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10595 return;
10596
0fde901f
KM		 10597 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10598 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10599 i915_disable_vga(dev);
6e1b4fda 10600 i915_disable_vga_mem(dev);
0fde901f
KM		 10601 }
10602}
10603
30e984df 10604static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10605{
10606 struct drm_i915_private *dev_priv = dev->dev_private;
10607 enum pipe pipe;
24929352
DV		 10608 struct intel_crtc *crtc;
10609 struct intel_encoder *encoder;
10610 struct intel_connector *connector;
5358901f 10611 int i;
24929352 10612
0e8ffe1b
DV		 10613 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10614 base.head) {
88adfff1 10615 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10616
0e8ffe1b
DV		 10617 crtc->active = dev_priv->display.get_pipe_config(crtc,
10618 &crtc->config);
24929352
DV		 10619
10620 crtc->base.enabled = crtc->active;
10621
10622 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10623 crtc->base.base.id,
10624 crtc->active ? "enabled" : "disabled");
10625 }
10626
5358901f 10627 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10628 if (HAS_DDI(dev))
6441ab5f
PZ		 10629 intel_ddi_setup_hw_pll_state(dev);
10630
5358901f
DV		 10631 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10632 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10633
10634 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10635 pll->active = 0;
10636 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10637 base.head) {
10638 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10639 pll->active++;
10640 }
10641 pll->refcount = pll->active;
10642
35c95375
DV		 10643 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10644 pll->name, pll->refcount, pll->on);
5358901f
DV		 10645 }
10646
24929352
DV		 10647 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10648 base.head) {
10649 pipe = 0;
10650
10651 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10652 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10653 encoder->base.crtc = &crtc->base;
510d5f2f 10654 if (encoder->get_config)
045ac3b5 10655 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10656 } else {
10657 encoder->base.crtc = NULL;
10658 }
10659
10660 encoder->connectors_active = false;
10661 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10662 encoder->base.base.id,
10663 drm_get_encoder_name(&encoder->base),
10664 encoder->base.crtc ? "enabled" : "disabled",
10665 pipe);
10666 }
10667
10668 list_for_each_entry(connector, &dev->mode_config.connector_list,
10669 base.head) {
10670 if (connector->get_hw_state(connector)) {
10671 connector->base.dpms = DRM_MODE_DPMS_ON;
10672 connector->encoder->connectors_active = true;
10673 connector->base.encoder = &connector->encoder->base;
10674 } else {
10675 connector->base.dpms = DRM_MODE_DPMS_OFF;
10676 connector->base.encoder = NULL;
10677 }
10678 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10679 connector->base.base.id,
10680 drm_get_connector_name(&connector->base),
10681 connector->base.encoder ? "enabled" : "disabled");
10682 }
30e984df
DV		 10683}
10684
10685/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10686 * and i915 state tracking structures. */
10687void intel_modeset_setup_hw_state(struct drm_device *dev,
10688 bool force_restore)
10689{
10690 struct drm_i915_private *dev_priv = dev->dev_private;
10691 enum pipe pipe;
30e984df
DV		 10692 struct intel_crtc *crtc;
10693 struct intel_encoder *encoder;
35c95375 10694 int i;
30e984df
DV		 10695
10696 intel_modeset_readout_hw_state(dev);
24929352 10697
babea61d
JB		 10698 /*
10699 * Now that we have the config, copy it to each CRTC struct
10700 * Note that this could go away if we move to using crtc_config
10701 * checking everywhere.
10702 */
10703 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10704 base.head) {
10705 if (crtc->active && i915_fastboot) {
10706 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10707
10708 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10709 crtc->base.base.id);
10710 drm_mode_debug_printmodeline(&crtc->base.mode);
10711 }
10712 }
10713
24929352
DV		 10714 /* HW state is read out, now we need to sanitize this mess. */
10715 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10716 base.head) {
10717 intel_sanitize_encoder(encoder);
10718 }
10719
10720 for_each_pipe(pipe) {
10721 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10722 intel_sanitize_crtc(crtc);
c0b03411 10723 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10724 }
9a935856 10725
35c95375
DV		 10726 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10727 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10728
10729 if (!pll->on || pll->active)
10730 continue;
10731
10732 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10733
10734 pll->disable(dev_priv, pll);
10735 pll->on = false;
10736 }
10737
45e2b5f6 10738 if (force_restore) {
7d0bc1ea
VS		 10739 i915_redisable_vga(dev);
10740
f30da187
DV		 10741 /*
10742 * We need to use raw interfaces for restoring state to avoid
10743 * checking (bogus) intermediate states.
10744 */
45e2b5f6 10745 for_each_pipe(pipe) {
b5644d05
JB		 10746 struct drm_crtc *crtc =
10747 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10748
10749 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10750 crtc->fb);
45e2b5f6
DV		 10751 }
10752 } else {
10753 intel_modeset_update_staged_output_state(dev);
10754 }
8af6cf88
DV		 10755
10756 intel_modeset_check_state(dev);
2e938892
DV		 10757
10758 drm_mode_config_reset(dev);
2c7111db
CW		 10759}
10760
10761void intel_modeset_gem_init(struct drm_device *dev)
10762{
1833b134 10763 intel_modeset_init_hw(dev);
02e792fb
DV		 10764
10765 intel_setup_overlay(dev);
24929352 10766
45e2b5f6 10767 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10768}
10769
10770void intel_modeset_cleanup(struct drm_device *dev)
10771{
652c393a
JB		 10772 struct drm_i915_private *dev_priv = dev->dev_private;
10773 struct drm_crtc *crtc;
d9255d57 10774 struct drm_connector *connector;
652c393a 10775
fd0c0642
DV		 10776 /*
10777 * Interrupts and polling as the first thing to avoid creating havoc.
10778 * Too much stuff here (turning of rps, connectors, ...) would
10779 * experience fancy races otherwise.
10780 */
10781 drm_irq_uninstall(dev);
10782 cancel_work_sync(&dev_priv->hotplug_work);
10783 /*
10784 * Due to the hpd irq storm handling the hotplug work can re-arm the
10785 * poll handlers. Hence disable polling after hpd handling is shut down.
10786 */
f87ea761 10787 drm_kms_helper_poll_fini(dev);
fd0c0642 10788
652c393a
JB		 10789 mutex_lock(&dev->struct_mutex);
10790
723bfd70
JB		 10791 intel_unregister_dsm_handler();
10792
652c393a
JB		 10793 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10794 /* Skip inactive CRTCs */
10795 if (!crtc->fb)
10796 continue;
10797
3dec0095 10798 intel_increase_pllclock(crtc);
652c393a
JB		 10799 }
10800
973d04f9 10801 intel_disable_fbc(dev);
e70236a8 10802
6e1b4fda 10803 i915_enable_vga_mem(dev);
81b5c7bc 10804
8090c6b9 10805 intel_disable_gt_powersave(dev);
0cdab21f 10806
930ebb46
DV		 10807 ironlake_teardown_rc6(dev);
10808
69341a5e
KH		 10809 mutex_unlock(&dev->struct_mutex);
10810
1630fe75
CW		 10811 /* flush any delayed tasks or pending work */
10812 flush_scheduled_work();
10813
dc652f90
JN		 10814 /* destroy backlight, if any, before the connectors */
10815 intel_panel_destroy_backlight(dev);
10816
d9255d57
PZ		 10817 /* destroy the sysfs files before encoders/connectors */
10818 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10819 drm_sysfs_connector_remove(connector);
10820
79e53945 10821 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10822
10823 intel_cleanup_overlay(dev);
79e53945
JB		 10824}
10825
f1c79df3
ZW		 10826/*
10827 * Return which encoder is currently attached for connector.
10828 */
df0e9248 10829struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10830{
df0e9248
CW		 10831 return &intel_attached_encoder(connector)->base;
10832}
f1c79df3 10833
df0e9248
CW		 10834void intel_connector_attach_encoder(struct intel_connector *connector,
10835 struct intel_encoder *encoder)
10836{
10837 connector->encoder = encoder;
10838 drm_mode_connector_attach_encoder(&connector->base,
10839 &encoder->base);
79e53945 10840}
28d52043
DA		 10841
10842/*
10843 * set vga decode state - true == enable VGA decode
10844 */
10845int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10846{
10847 struct drm_i915_private *dev_priv = dev->dev_private;
10848 u16 gmch_ctrl;
10849
10850 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10851 if (state)
10852 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10853 else
10854 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10855 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10856 return 0;
10857}
c4a1d9e4 10858
c4a1d9e4 10859struct intel_display_error_state {
ff57f1b0
PZ		 10860
10861 u32 power_well_driver;
10862
63b66e5b
CW		 10863 int num_transcoders;
10864
c4a1d9e4
CW		 10865 struct intel_cursor_error_state {
10866 u32 control;
10867 u32 position;
10868 u32 base;
10869 u32 size;
52331309 10870 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10871
10872 struct intel_pipe_error_state {
c4a1d9e4 10873 u32 source;
52331309 10874 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10875
10876 struct intel_plane_error_state {
10877 u32 control;
10878 u32 stride;
10879 u32 size;
10880 u32 pos;
10881 u32 addr;
10882 u32 surface;
10883 u32 tile_offset;
52331309 10884 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10885
10886 struct intel_transcoder_error_state {
10887 enum transcoder cpu_transcoder;
10888
10889 u32 conf;
10890
10891 u32 htotal;
10892 u32 hblank;
10893 u32 hsync;
10894 u32 vtotal;
10895 u32 vblank;
10896 u32 vsync;
10897 } transcoder[4];
c4a1d9e4
CW		 10898};
10899
10900struct intel_display_error_state *
10901intel_display_capture_error_state(struct drm_device *dev)
10902{
0206e353 10903 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10904 struct intel_display_error_state *error;
63b66e5b
CW		 10905 int transcoders[] = {
10906 TRANSCODER_A,
10907 TRANSCODER_B,
10908 TRANSCODER_C,
10909 TRANSCODER_EDP,
10910 };
c4a1d9e4
CW		 10911 int i;
10912
63b66e5b
CW		 10913 if (INTEL_INFO(dev)->num_pipes == 0)
10914 return NULL;
10915
c4a1d9e4
CW		 10916 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10917 if (error == NULL)
10918 return NULL;
10919
ff57f1b0
PZ		 10920 if (HAS_POWER_WELL(dev))
10921 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10922
52331309 10923 for_each_pipe(i) {
a18c4c3d
PZ		 10924 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10925 error->cursor[i].control = I915_READ(CURCNTR(i));
10926 error->cursor[i].position = I915_READ(CURPOS(i));
10927 error->cursor[i].base = I915_READ(CURBASE(i));
10928 } else {
10929 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10930 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10931 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10932 }
c4a1d9e4
CW		 10933
10934 error->plane[i].control = I915_READ(DSPCNTR(i));
10935 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10936 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10937 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10938 error->plane[i].pos = I915_READ(DSPPOS(i));
10939 }
ca291363
PZ		 10940 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10941 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10942 if (INTEL_INFO(dev)->gen >= 4) {
10943 error->plane[i].surface = I915_READ(DSPSURF(i));
10944 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10945 }
10946
c4a1d9e4 10947 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10948 }
10949
10950 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10951 if (HAS_DDI(dev_priv->dev))
10952 error->num_transcoders++; /* Account for eDP. */
10953
10954 for (i = 0; i < error->num_transcoders; i++) {
10955 enum transcoder cpu_transcoder = transcoders[i];
10956
10957 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10958
10959 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10960 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10961 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10962 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10963 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10964 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10965 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10966 }
10967
12d217c7
PZ		 10968 /* In the code above we read the registers without checking if the power
10969 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10970 * prevent the next I915_WRITE from detecting it and printing an error
10971 * message. */
907b28c5 10972 intel_uncore_clear_errors(dev);
12d217c7 10973
c4a1d9e4
CW		 10974 return error;
10975}
10976
edc3d884
MK		 10977#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10978
c4a1d9e4 10979void
edc3d884 10980intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10981 struct drm_device *dev,
10982 struct intel_display_error_state *error)
10983{
10984 int i;
10985
63b66e5b
CW		 10986 if (!error)
10987 return;
10988
edc3d884 10989 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10990 if (HAS_POWER_WELL(dev))
edc3d884 10991 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10992 error->power_well_driver);
52331309 10993 for_each_pipe(i) {
edc3d884 10994 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10995 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10996
10997 err_printf(m, "Plane [%d]:\n", i);
10998 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10999 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11000 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11001 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11002 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11003 }
4b71a570 11004 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11005 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11006 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11007 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11008 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11009 }
11010
edc3d884
MK		 11011 err_printf(m, "Cursor [%d]:\n", i);
11012 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11013 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11014 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11015 }
63b66e5b
CW		 11016
11017 for (i = 0; i < error->num_transcoders; i++) {
11018 err_printf(m, " CPU transcoder: %c\n",
11019 transcoder_name(error->transcoder[i].cpu_transcoder));
11020 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11021 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11022 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11023 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11024 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11025 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11026 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11027 }
c4a1d9e4 11028}
Linux kernel - Deliverables
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