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drm/i915: program iCLKIP on Lynx Point
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
57f350b6
JB		 387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
618563e3
DV		 398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
b0354385
TI		 416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
121d527a
TI		 421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
618563e3
DV		 425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
b0354385
TI		 428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
1b894b59
CW		 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
2c07245f 446{
b91ad0ec
ZW		 447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec
ZW		 450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 453 /* LVDS dual channel */
1b894b59 454 if (refclk == 100000)
b91ad0ec
ZW		 455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
1b894b59 459 if (refclk == 100000)
b91ad0ec
ZW		 460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
2c07245f 467 else
b91ad0ec 468 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 469
470 return limit;
471}
472
044c7c41
ML		 473static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474{
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 480 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 481 /* LVDS with dual channel */
e4b36699 482 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 483 else
484 /* LVDS with dual channel */
e4b36699 485 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 488 limit = &intel_limits_g4x_hdmi;
044c7c41 489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 490 limit = &intel_limits_g4x_sdvo;
0206e353 491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 492 limit = &intel_limits_g4x_display_port;
044c7c41 493 } else /* The option is for other outputs */
e4b36699 494 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 495
496 return limit;
497}
498
1b894b59 499static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 500{
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
bad720ff 504 if (HAS_PCH_SPLIT(dev))
1b894b59 505 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 506 else if (IS_G4X(dev)) {
044c7c41 507 limit = intel_g4x_limit(crtc);
f2b115e6 508 } else if (IS_PINEVIEW(dev)) {
2177832f 509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 510 limit = &intel_limits_pineview_lvds;
2177832f 511 else
f2b115e6 512 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 520 limit = &intel_limits_i8xx_lvds;
79e53945 521 else
e4b36699 522 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 523 }
524 return limit;
525}
526
f2b115e6
AJ		 527/* m1 is reserved as 0 in Pineview, n is a ring counter */
528static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 529{
2177832f
SL		 530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534}
535
536static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537{
f2b115e6
AJ		 538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
2177832f
SL		 540 return;
541 }
79e53945
JB		 542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546}
547
79e53945
JB		 548/**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
4ef69c7a 551bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 552{
4ef69c7a
CW		 553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
79e53945
JB		 562}
563
7c04d1d9 564#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 565/**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
1b894b59
CW		 570static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
79e53945 573{
79e53945 574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 575 INTELPllInvalid("p1 out of range\n");
79e53945 576 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 577 INTELPllInvalid("p out of range\n");
79e53945 578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 579 INTELPllInvalid("m2 out of range\n");
79e53945 580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 581 INTELPllInvalid("m1 out of range\n");
f2b115e6 582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 583 INTELPllInvalid("m1 <= m2\n");
79e53945 584 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 585 INTELPllInvalid("m out of range\n");
79e53945 586 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 587 INTELPllInvalid("n out of range\n");
79e53945 588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 589 INTELPllInvalid("vco out of range\n");
79e53945
JB		 590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 594 INTELPllInvalid("dot out of range\n");
79e53945
JB		 595
596 return true;
597}
598
d4906093
ML		 599static bool
600intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
d4906093 603
79e53945
JB		 604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
bc5e5718 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 611 (I915_READ(LVDS)) != 0) {
79e53945
JB		 612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
b0354385 618 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
0206e353 629 memset(best_clock, 0, sizeof(*best_clock));
79e53945 630
42158660
ZY		 631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 642 int this_err;
643
2177832f 644 intel_clock(dev, refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
79e53945 647 continue;
cec2f356
SP		 648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
79e53945
JB		 651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663}
664
d4906093
ML		 665static bool
666intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
d4906093
ML		 669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
6ba770dc
AJ		 675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 680 int lvds_reg;
681
c619eed4 682 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
f77f13e2 700 /* based on hardware requirement, prefer smaller n to precision */
d4906093 701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 702 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
2177832f 711 intel_clock(dev, refclk, &clock);
1b894b59
CW		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
d4906093 714 continue;
cec2f356
SP		 715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
1b894b59
CW		 718
719 this_err = abs(clock.dot - target);
d4906093
ML		 720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
2c07245f
ZW		 730 return found;
731}
732
5eb08b69 733static bool
f2b115e6 734intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
5eb08b69
ZW		 737{
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
4547668a 740
5eb08b69
ZW		 741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757}
758
a4fc5ed6
KP		 759/* DisplayPort has only two frequencies, 162MHz and 270MHz */
760static bool
761intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
a4fc5ed6 764{
5eddb70b
CW		 765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
a4fc5ed6
KP		 785}
786
a928d536
PZ		 787static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
9d0498a2
JB		 798/**
799 * intel_wait_for_vblank - wait for vblank on a given pipe
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
804 * mode setting code.
805 */
806void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 807{
9d0498a2 808 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 809 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 810
a928d536
PZ		 811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
300387c0
CW		 816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
818 *
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
825 * vblanks...
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
828 */
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
831
9d0498a2 832 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
835 50))
9d0498a2
JB		 836 DRM_DEBUG_KMS("vblank wait timed out\n");
837}
838
ab7ad7f6
KP		 839/*
840 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 841 * @dev: drm device
842 * @pipe: pipe to wait for
843 *
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
847 *
ab7ad7f6
KP		 848 * On Gen4 and above:
849 * wait for the pipe register state bit to turn off
850 *
851 * Otherwise:
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
58e10eb9 854 *
9d0498a2 855 */
58e10eb9 856void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 857{
858 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 859
860 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 861 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 862
863 /* Wait for the Pipe State to go off */
58e10eb9
CW		 864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
865 100))
ab7ad7f6
KP		 866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
867 } else {
837ba00f 868 u32 last_line, line_mask;
58e10eb9 869 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
871
837ba00f
PZ		 872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
ab7ad7f6
KP		 877 /* Wait for the display line to settle */
878 do {
837ba00f 879 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 880 mdelay(5);
837ba00f 881 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
885 }
79e53945
JB		 886}
887
b24e7179
JB		 888static const char *state_string(bool enabled)
889{
890 return enabled ? "on" : "off";
891}
892
893/* Only for pre-ILK configs */
894static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
896{
897 int reg;
898 u32 val;
899 bool cur_state;
900
901 reg = DPLL(pipe);
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
907}
908#define assert_pll_enabled(d, p) assert_pll(d, p, true)
909#define assert_pll_disabled(d, p) assert_pll(d, p, false)
910
040484af
JB		 911/* For ILK+ */
912static void assert_pch_pll(struct drm_i915_private *dev_priv,
ee7b9f93 913 struct intel_crtc *intel_crtc, bool state)
040484af
JB		 914{
915 int reg;
916 u32 val;
917 bool cur_state;
918
9d82aa17
ED		 919 if (HAS_PCH_LPT(dev_priv->dev)) {
920 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
921 return;
922 }
923
ee7b9f93
JB		 924 if (!intel_crtc->pch_pll) {
925 WARN(1, "asserting PCH PLL enabled with no PLL\n");
926 return;
927 }
928
d3ccbe86
JB		 929 if (HAS_PCH_CPT(dev_priv->dev)) {
930 u32 pch_dpll;
931
932 pch_dpll = I915_READ(PCH_DPLL_SEL);
933
934 /* Make sure the selected PLL is enabled to the transcoder */
ee7b9f93
JB		 935 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
936 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
d3ccbe86
JB		 937 }
938
ee7b9f93 939 reg = intel_crtc->pch_pll->pll_reg;
040484af
JB		 940 val = I915_READ(reg);
941 cur_state = !!(val & DPLL_VCO_ENABLE);
942 WARN(cur_state != state,
943 "PCH PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
947#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
955
bf507ef7
ED		 956 if (IS_HASWELL(dev_priv->dev)) {
957 /* On Haswell, DDI is used instead of FDI_TX_CTL */
958 reg = DDI_FUNC_CTL(pipe);
959 val = I915_READ(reg);
960 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
961 } else {
962 reg = FDI_TX_CTL(pipe);
963 val = I915_READ(reg);
964 cur_state = !!(val & FDI_TX_ENABLE);
965 }
040484af
JB		 966 WARN(cur_state != state,
967 "FDI TX state assertion failure (expected %s, current %s)\n",
968 state_string(state), state_string(cur_state));
969}
970#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
971#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
972
973static void assert_fdi_rx(struct drm_i915_private *dev_priv,
974 enum pipe pipe, bool state)
975{
976 int reg;
977 u32 val;
978 bool cur_state;
979
59c859d6
ED		 980 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
981 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
982 return;
983 } else {
984 reg = FDI_RX_CTL(pipe);
985 val = I915_READ(reg);
986 cur_state = !!(val & FDI_RX_ENABLE);
987 }
040484af
JB		 988 WARN(cur_state != state,
989 "FDI RX state assertion failure (expected %s, current %s)\n",
990 state_string(state), state_string(cur_state));
991}
992#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
993#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
994
995static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
996 enum pipe pipe)
997{
998 int reg;
999 u32 val;
1000
1001 /* ILK FDI PLL is always enabled */
1002 if (dev_priv->info->gen == 5)
1003 return;
1004
bf507ef7
ED		 1005 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1006 if (IS_HASWELL(dev_priv->dev))
1007 return;
1008
040484af
JB		 1009 reg = FDI_TX_CTL(pipe);
1010 val = I915_READ(reg);
1011 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1012}
1013
1014static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1015 enum pipe pipe)
1016{
1017 int reg;
1018 u32 val;
1019
59c859d6
ED		 1020 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1021 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1022 return;
1023 }
040484af
JB		 1024 reg = FDI_RX_CTL(pipe);
1025 val = I915_READ(reg);
1026 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1027}
1028
ea0760cf
JB		 1029static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1030 enum pipe pipe)
1031{
1032 int pp_reg, lvds_reg;
1033 u32 val;
1034 enum pipe panel_pipe = PIPE_A;
0de3b485 1035 bool locked = true;
ea0760cf
JB		 1036
1037 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1038 pp_reg = PCH_PP_CONTROL;
1039 lvds_reg = PCH_LVDS;
1040 } else {
1041 pp_reg = PP_CONTROL;
1042 lvds_reg = LVDS;
1043 }
1044
1045 val = I915_READ(pp_reg);
1046 if (!(val & PANEL_POWER_ON) ||
1047 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1048 locked = false;
1049
1050 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1051 panel_pipe = PIPE_B;
1052
1053 WARN(panel_pipe == pipe && locked,
1054 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1055 pipe_name(pipe));
ea0760cf
JB		 1056}
1057
b840d907
JB		 1058void assert_pipe(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
b24e7179
JB		 1060{
1061 int reg;
1062 u32 val;
63d7bbe9 1063 bool cur_state;
b24e7179 1064
8e636784
DV		 1065 /* if we need the pipe A quirk it must be always on */
1066 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1067 state = true;
1068
b24e7179
JB		 1069 reg = PIPECONF(pipe);
1070 val = I915_READ(reg);
63d7bbe9
JB		 1071 cur_state = !!(val & PIPECONF_ENABLE);
1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1074 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1075}
1076
931872fc
CW		 1077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
b24e7179
JB		 1079{
1080 int reg;
1081 u32 val;
931872fc 1082 bool cur_state;
b24e7179
JB		 1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
931872fc
CW		 1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1090}
1091
931872fc
CW		 1092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
b24e7179
JB		 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
1098 int reg, i;
1099 u32 val;
1100 int cur_pipe;
1101
19ec1358 1102 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1103 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1104 reg = DSPCNTR(pipe);
1105 val = I915_READ(reg);
1106 WARN((val & DISPLAY_PLANE_ENABLE),
1107 "plane %c assertion failure, should be disabled but not\n",
1108 plane_name(pipe));
19ec1358 1109 return;
28c05794 1110 }
19ec1358 1111
b24e7179
JB		 1112 /* Need to check both planes against the pipe */
1113 for (i = 0; i < 2; i++) {
1114 reg = DSPCNTR(i);
1115 val = I915_READ(reg);
1116 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1117 DISPPLANE_SEL_PIPE_SHIFT;
1118 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1119 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1120 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1121 }
1122}
1123
92f2584a
JB		 1124static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1125{
1126 u32 val;
1127 bool enabled;
1128
9d82aa17
ED		 1129 if (HAS_PCH_LPT(dev_priv->dev)) {
1130 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1131 return;
1132 }
1133
92f2584a
JB		 1134 val = I915_READ(PCH_DREF_CONTROL);
1135 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1136 DREF_SUPERSPREAD_SOURCE_MASK));
1137 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1138}
1139
1140static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1141 enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145 bool enabled;
1146
1147 reg = TRANSCONF(pipe);
1148 val = I915_READ(reg);
1149 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1150 WARN(enabled,
1151 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1152 pipe_name(pipe));
92f2584a
JB		 1153}
1154
4e634389
KP		 1155static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1157{
1158 if ((val & DP_PORT_EN) == 0)
1159 return false;
1160
1161 if (HAS_PCH_CPT(dev_priv->dev)) {
1162 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1163 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1164 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1165 return false;
1166 } else {
1167 if ((val & DP_PIPE_MASK) != (pipe << 30))
1168 return false;
1169 }
1170 return true;
1171}
1172
1519b995
KP		 1173static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1174 enum pipe pipe, u32 val)
1175{
1176 if ((val & PORT_ENABLE) == 0)
1177 return false;
1178
1179 if (HAS_PCH_CPT(dev_priv->dev)) {
1180 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1181 return false;
1182 } else {
1183 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1184 return false;
1185 }
1186 return true;
1187}
1188
1189static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, u32 val)
1191{
1192 if ((val & LVDS_PORT_EN) == 0)
1193 return false;
1194
1195 if (HAS_PCH_CPT(dev_priv->dev)) {
1196 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1197 return false;
1198 } else {
1199 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1200 return false;
1201 }
1202 return true;
1203}
1204
1205static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, u32 val)
1207{
1208 if ((val & ADPA_DAC_ENABLE) == 0)
1209 return false;
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
1211 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1212 return false;
1213 } else {
1214 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1215 return false;
1216 }
1217 return true;
1218}
1219
291906f1 1220static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1221 enum pipe pipe, int reg, u32 port_sel)
291906f1 1222{
47a05eca 1223 u32 val = I915_READ(reg);
4e634389 1224 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1225 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1226 reg, pipe_name(pipe));
291906f1
JB		 1227}
1228
1229static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1230 enum pipe pipe, int reg)
1231{
47a05eca 1232 u32 val = I915_READ(reg);
1519b995 1233 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1234 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1235 reg, pipe_name(pipe));
291906f1
JB		 1236}
1237
1238static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1239 enum pipe pipe)
1240{
1241 int reg;
1242 u32 val;
291906f1 1243
f0575e92
KP		 1244 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1245 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1246 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1247
1248 reg = PCH_ADPA;
1249 val = I915_READ(reg);
1519b995 1250 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1251 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1252 pipe_name(pipe));
291906f1
JB		 1253
1254 reg = PCH_LVDS;
1255 val = I915_READ(reg);
1519b995 1256 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1257 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1258 pipe_name(pipe));
291906f1
JB		 1259
1260 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1261 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1262 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1263}
1264
63d7bbe9
JB		 1265/**
1266 * intel_enable_pll - enable a PLL
1267 * @dev_priv: i915 private structure
1268 * @pipe: pipe PLL to enable
1269 *
1270 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1271 * make sure the PLL reg is writable first though, since the panel write
1272 * protect mechanism may be enabled.
1273 *
1274 * Note! This is for pre-ILK only.
1275 */
1276static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1277{
1278 int reg;
1279 u32 val;
1280
1281 /* No really, not for ILK+ */
1282 BUG_ON(dev_priv->info->gen >= 5);
1283
1284 /* PLL is protected by panel, make sure we can write it */
1285 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1286 assert_panel_unlocked(dev_priv, pipe);
1287
1288 reg = DPLL(pipe);
1289 val = I915_READ(reg);
1290 val |= DPLL_VCO_ENABLE;
1291
1292 /* We do this three times for luck */
1293 I915_WRITE(reg, val);
1294 POSTING_READ(reg);
1295 udelay(150); /* wait for warmup */
1296 I915_WRITE(reg, val);
1297 POSTING_READ(reg);
1298 udelay(150); /* wait for warmup */
1299 I915_WRITE(reg, val);
1300 POSTING_READ(reg);
1301 udelay(150); /* wait for warmup */
1302}
1303
1304/**
1305 * intel_disable_pll - disable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to disable
1308 *
1309 * Disable the PLL for @pipe, making sure the pipe is off first.
1310 *
1311 * Note! This is for pre-ILK only.
1312 */
1313static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1314{
1315 int reg;
1316 u32 val;
1317
1318 /* Don't disable pipe A or pipe A PLLs if needed */
1319 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1320 return;
1321
1322 /* Make sure the pipe isn't still relying on us */
1323 assert_pipe_disabled(dev_priv, pipe);
1324
1325 reg = DPLL(pipe);
1326 val = I915_READ(reg);
1327 val &= ~DPLL_VCO_ENABLE;
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330}
1331
a416edef
ED		 1332/* SBI access */
1333static void
1334intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1335{
1336 unsigned long flags;
1337
1338 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1339 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1340 100)) {
1341 DRM_ERROR("timeout waiting for SBI to become ready\n");
1342 goto out_unlock;
1343 }
1344
1345 I915_WRITE(SBI_ADDR,
1346 (reg << 16));
1347 I915_WRITE(SBI_DATA,
1348 value);
1349 I915_WRITE(SBI_CTL_STAT,
1350 SBI_BUSY |
1351 SBI_CTL_OP_CRWR);
1352
1353 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1354 100)) {
1355 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1356 goto out_unlock;
1357 }
1358
1359out_unlock:
1360 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1361}
1362
1363static u32
1364intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1365{
1366 unsigned long flags;
1367 u32 value;
1368
1369 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1370 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1371 100)) {
1372 DRM_ERROR("timeout waiting for SBI to become ready\n");
1373 goto out_unlock;
1374 }
1375
1376 I915_WRITE(SBI_ADDR,
1377 (reg << 16));
1378 I915_WRITE(SBI_CTL_STAT,
1379 SBI_BUSY |
1380 SBI_CTL_OP_CRRD);
1381
1382 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1383 100)) {
1384 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1385 goto out_unlock;
1386 }
1387
1388 value = I915_READ(SBI_DATA);
1389
1390out_unlock:
1391 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1392 return value;
1393}
1394
92f2584a
JB		 1395/**
1396 * intel_enable_pch_pll - enable PCH PLL
1397 * @dev_priv: i915 private structure
1398 * @pipe: pipe PLL to enable
1399 *
1400 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1401 * drives the transcoder clock.
1402 */
ee7b9f93 1403static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1404{
ee7b9f93
JB		 1405 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1406 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a
JB		 1407 int reg;
1408 u32 val;
1409
1410 /* PCH only available on ILK+ */
1411 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1412 BUG_ON(pll == NULL);
1413 BUG_ON(pll->refcount == 0);
1414
1415 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1416 pll->pll_reg, pll->active, pll->on,
1417 intel_crtc->base.base.id);
92f2584a
JB		 1418
1419 /* PCH refclock must be enabled first */
1420 assert_pch_refclk_enabled(dev_priv);
1421
ee7b9f93
JB		 1422 if (pll->active++ && pll->on) {
1423 assert_pch_pll_enabled(dev_priv, intel_crtc);
1424 return;
1425 }
1426
1427 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1428
1429 reg = pll->pll_reg;
92f2584a
JB		 1430 val = I915_READ(reg);
1431 val |= DPLL_VCO_ENABLE;
1432 I915_WRITE(reg, val);
1433 POSTING_READ(reg);
1434 udelay(200);
ee7b9f93
JB		 1435
1436 pll->on = true;
92f2584a
JB		 1437}
1438
ee7b9f93 1439static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1440{
ee7b9f93
JB		 1441 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1442 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1443 int reg;
ee7b9f93 1444 u32 val;
4c609cb8 1445
92f2584a
JB		 1446 /* PCH only available on ILK+ */
1447 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1448 if (pll == NULL)
1449 return;
92f2584a 1450
ee7b9f93 1451 BUG_ON(pll->refcount == 0);
7a419866 1452
ee7b9f93
JB		 1453 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1454 pll->pll_reg, pll->active, pll->on,
1455 intel_crtc->base.base.id);
7a419866 1456
ee7b9f93
JB		 1457 BUG_ON(pll->active == 0);
1458 if (--pll->active) {
1459 assert_pch_pll_enabled(dev_priv, intel_crtc);
7a419866 1460 return;
ee7b9f93
JB		 1461 }
1462
1463 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1464
1465 /* Make sure transcoder isn't still depending on us */
1466 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1467
ee7b9f93 1468 reg = pll->pll_reg;
92f2584a
JB		 1469 val = I915_READ(reg);
1470 val &= ~DPLL_VCO_ENABLE;
1471 I915_WRITE(reg, val);
1472 POSTING_READ(reg);
1473 udelay(200);
ee7b9f93
JB		 1474
1475 pll->on = false;
92f2584a
JB		 1476}
1477
040484af
JB		 1478static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1479 enum pipe pipe)
1480{
1481 int reg;
5f7f726d 1482 u32 val, pipeconf_val;
7c26e5c6 1483 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1484
1485 /* PCH only available on ILK+ */
1486 BUG_ON(dev_priv->info->gen < 5);
1487
1488 /* Make sure PCH DPLL is enabled */
ee7b9f93 1489 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
040484af
JB		 1490
1491 /* FDI must be feeding us bits for PCH ports */
1492 assert_fdi_tx_enabled(dev_priv, pipe);
1493 assert_fdi_rx_enabled(dev_priv, pipe);
1494
59c859d6
ED		 1495 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1496 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1497 return;
1498 }
040484af
JB		 1499 reg = TRANSCONF(pipe);
1500 val = I915_READ(reg);
5f7f726d 1501 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1502
1503 if (HAS_PCH_IBX(dev_priv->dev)) {
1504 /*
1505 * make the BPC in transcoder be consistent with
1506 * that in pipeconf reg.
1507 */
1508 val &= ~PIPE_BPC_MASK;
5f7f726d 1509 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1510 }
5f7f726d
PZ		 1511
1512 val &= ~TRANS_INTERLACE_MASK;
1513 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1514 if (HAS_PCH_IBX(dev_priv->dev) &&
1515 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1516 val |= TRANS_LEGACY_INTERLACED_ILK;
1517 else
1518 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1519 else
1520 val |= TRANS_PROGRESSIVE;
1521
040484af
JB		 1522 I915_WRITE(reg, val | TRANS_ENABLE);
1523 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1524 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1525}
1526
1527static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1528 enum pipe pipe)
1529{
1530 int reg;
1531 u32 val;
1532
1533 /* FDI relies on the transcoder */
1534 assert_fdi_tx_disabled(dev_priv, pipe);
1535 assert_fdi_rx_disabled(dev_priv, pipe);
1536
291906f1
JB		 1537 /* Ports must be off as well */
1538 assert_pch_ports_disabled(dev_priv, pipe);
1539
040484af
JB		 1540 reg = TRANSCONF(pipe);
1541 val = I915_READ(reg);
1542 val &= ~TRANS_ENABLE;
1543 I915_WRITE(reg, val);
1544 /* wait for PCH transcoder off, transcoder state */
1545 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1546 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1547}
1548
b24e7179 1549/**
309cfea8 1550 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1551 * @dev_priv: i915 private structure
1552 * @pipe: pipe to enable
040484af 1553 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1554 *
1555 * Enable @pipe, making sure that various hardware specific requirements
1556 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1557 *
1558 * @pipe should be %PIPE_A or %PIPE_B.
1559 *
1560 * Will wait until the pipe is actually running (i.e. first vblank) before
1561 * returning.
1562 */
040484af
JB		 1563static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1564 bool pch_port)
b24e7179
JB		 1565{
1566 int reg;
1567 u32 val;
1568
1569 /*
1570 * A pipe without a PLL won't actually be able to drive bits from
1571 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1572 * need the check.
1573 */
1574 if (!HAS_PCH_SPLIT(dev_priv->dev))
1575 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1576 else {
1577 if (pch_port) {
1578 /* if driving the PCH, we need FDI enabled */
1579 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1580 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1581 }
1582 /* FIXME: assert CPU port conditions for SNB+ */
1583 }
b24e7179
JB		 1584
1585 reg = PIPECONF(pipe);
1586 val = I915_READ(reg);
00d70b15
CW		 1587 if (val & PIPECONF_ENABLE)
1588 return;
1589
1590 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1591 intel_wait_for_vblank(dev_priv->dev, pipe);
1592}
1593
1594/**
309cfea8 1595 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1596 * @dev_priv: i915 private structure
1597 * @pipe: pipe to disable
1598 *
1599 * Disable @pipe, making sure that various hardware specific requirements
1600 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1601 *
1602 * @pipe should be %PIPE_A or %PIPE_B.
1603 *
1604 * Will wait until the pipe has shut down before returning.
1605 */
1606static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1607 enum pipe pipe)
1608{
1609 int reg;
1610 u32 val;
1611
1612 /*
1613 * Make sure planes won't keep trying to pump pixels to us,
1614 * or we might hang the display.
1615 */
1616 assert_planes_disabled(dev_priv, pipe);
1617
1618 /* Don't disable pipe A or pipe A PLLs if needed */
1619 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1620 return;
1621
1622 reg = PIPECONF(pipe);
1623 val = I915_READ(reg);
00d70b15
CW		 1624 if ((val & PIPECONF_ENABLE) == 0)
1625 return;
1626
1627 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1628 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1629}
1630
d74362c9
KP		 1631/*
1632 * Plane regs are double buffered, going from enabled->disabled needs a
1633 * trigger in order to latch. The display address reg provides this.
1634 */
6f1d69b0 1635void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1636 enum plane plane)
1637{
1638 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1639 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1640}
1641
b24e7179
JB		 1642/**
1643 * intel_enable_plane - enable a display plane on a given pipe
1644 * @dev_priv: i915 private structure
1645 * @plane: plane to enable
1646 * @pipe: pipe being fed
1647 *
1648 * Enable @plane on @pipe, making sure that @pipe is running first.
1649 */
1650static void intel_enable_plane(struct drm_i915_private *dev_priv,
1651 enum plane plane, enum pipe pipe)
1652{
1653 int reg;
1654 u32 val;
1655
1656 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1657 assert_pipe_enabled(dev_priv, pipe);
1658
1659 reg = DSPCNTR(plane);
1660 val = I915_READ(reg);
00d70b15
CW		 1661 if (val & DISPLAY_PLANE_ENABLE)
1662 return;
1663
1664 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1665 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1666 intel_wait_for_vblank(dev_priv->dev, pipe);
1667}
1668
b24e7179
JB		 1669/**
1670 * intel_disable_plane - disable a display plane
1671 * @dev_priv: i915 private structure
1672 * @plane: plane to disable
1673 * @pipe: pipe consuming the data
1674 *
1675 * Disable @plane; should be an independent operation.
1676 */
1677static void intel_disable_plane(struct drm_i915_private *dev_priv,
1678 enum plane plane, enum pipe pipe)
1679{
1680 int reg;
1681 u32 val;
1682
1683 reg = DSPCNTR(plane);
1684 val = I915_READ(reg);
00d70b15
CW		 1685 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1686 return;
1687
1688 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1689 intel_flush_display_plane(dev_priv, plane);
1690 intel_wait_for_vblank(dev_priv->dev, pipe);
1691}
1692
47a05eca 1693static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1694 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1695{
1696 u32 val = I915_READ(reg);
4e634389 1697 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1698 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1699 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1700 }
47a05eca
JB		 1701}
1702
1703static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1704 enum pipe pipe, int reg)
1705{
1706 u32 val = I915_READ(reg);
1519b995 1707 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1708 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1709 reg, pipe);
47a05eca 1710 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1711 }
47a05eca
JB		 1712}
1713
1714/* Disable any ports connected to this transcoder */
1715static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1716 enum pipe pipe)
1717{
1718 u32 reg, val;
1719
1720 val = I915_READ(PCH_PP_CONTROL);
1721 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1722
f0575e92
KP		 1723 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1724 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1725 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1726
1727 reg = PCH_ADPA;
1728 val = I915_READ(reg);
1519b995 1729 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1730 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1731
1732 reg = PCH_LVDS;
1733 val = I915_READ(reg);
1519b995
KP		 1734 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1735 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1736 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1737 POSTING_READ(reg);
1738 udelay(100);
1739 }
1740
1741 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1742 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1743 disable_pch_hdmi(dev_priv, pipe, HDMID);
1744}
1745
127bd2ac 1746int
48b956c5 1747intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1748 struct drm_i915_gem_object *obj,
919926ae 1749 struct intel_ring_buffer *pipelined)
6b95a207 1750{
ce453d81 1751 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1752 u32 alignment;
1753 int ret;
1754
05394f39 1755 switch (obj->tiling_mode) {
6b95a207 1756 case I915_TILING_NONE:
534843da
CW		 1757 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1758 alignment = 128 * 1024;
a6c45cf0 1759 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1760 alignment = 4 * 1024;
1761 else
1762 alignment = 64 * 1024;
6b95a207
KH		 1763 break;
1764 case I915_TILING_X:
1765 /* pin() will align the object as required by fence */
1766 alignment = 0;
1767 break;
1768 case I915_TILING_Y:
1769 /* FIXME: Is this true? */
1770 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1771 return -EINVAL;
1772 default:
1773 BUG();
1774 }
1775
ce453d81 1776 dev_priv->mm.interruptible = false;
2da3b9b9 1777 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1778 if (ret)
ce453d81 1779 goto err_interruptible;
6b95a207
KH		 1780
1781 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1782 * fence, whereas 965+ only requires a fence if using
1783 * framebuffer compression. For simplicity, we always install
1784 * a fence as the cost is not that onerous.
1785 */
06d98131 1786 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1787 if (ret)
1788 goto err_unpin;
1690e1eb 1789
9a5a53b3 1790 i915_gem_object_pin_fence(obj);
6b95a207 1791
ce453d81 1792 dev_priv->mm.interruptible = true;
6b95a207 1793 return 0;
48b956c5
CW		 1794
1795err_unpin:
1796 i915_gem_object_unpin(obj);
ce453d81
CW		 1797err_interruptible:
1798 dev_priv->mm.interruptible = true;
48b956c5 1799 return ret;
6b95a207
KH		 1800}
1801
1690e1eb
CW		 1802void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1803{
1804 i915_gem_object_unpin_fence(obj);
1805 i915_gem_object_unpin(obj);
1806}
1807
17638cd6
JB		 1808static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1809 int x, int y)
81255565
JB		 1810{
1811 struct drm_device *dev = crtc->dev;
1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1814 struct intel_framebuffer *intel_fb;
05394f39 1815 struct drm_i915_gem_object *obj;
81255565
JB		 1816 int plane = intel_crtc->plane;
1817 unsigned long Start, Offset;
81255565 1818 u32 dspcntr;
5eddb70b 1819 u32 reg;
81255565
JB		 1820
1821 switch (plane) {
1822 case 0:
1823 case 1:
1824 break;
1825 default:
1826 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1827 return -EINVAL;
1828 }
1829
1830 intel_fb = to_intel_framebuffer(fb);
1831 obj = intel_fb->obj;
81255565 1832
5eddb70b
CW		 1833 reg = DSPCNTR(plane);
1834 dspcntr = I915_READ(reg);
81255565
JB		 1835 /* Mask out pixel format bits in case we change it */
1836 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1837 switch (fb->bits_per_pixel) {
1838 case 8:
1839 dspcntr |= DISPPLANE_8BPP;
1840 break;
1841 case 16:
1842 if (fb->depth == 15)
1843 dspcntr |= DISPPLANE_15_16BPP;
1844 else
1845 dspcntr |= DISPPLANE_16BPP;
1846 break;
1847 case 24:
1848 case 32:
1849 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1850 break;
1851 default:
17638cd6 1852 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1853 return -EINVAL;
1854 }
a6c45cf0 1855 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1856 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1857 dspcntr |= DISPPLANE_TILED;
1858 else
1859 dspcntr &= ~DISPPLANE_TILED;
1860 }
1861
5eddb70b 1862 I915_WRITE(reg, dspcntr);
81255565 1863
05394f39 1864 Start = obj->gtt_offset;
01f2c773 1865 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1866
4e6cfefc 1867 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1868 Start, Offset, x, y, fb->pitches[0]);
1869 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1870 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1871 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1872 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1873 I915_WRITE(DSPADDR(plane), Offset);
1874 } else
1875 I915_WRITE(DSPADDR(plane), Start + Offset);
1876 POSTING_READ(reg);
81255565 1877
17638cd6
JB		 1878 return 0;
1879}
1880
1881static int ironlake_update_plane(struct drm_crtc *crtc,
1882 struct drm_framebuffer *fb, int x, int y)
1883{
1884 struct drm_device *dev = crtc->dev;
1885 struct drm_i915_private *dev_priv = dev->dev_private;
1886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1887 struct intel_framebuffer *intel_fb;
1888 struct drm_i915_gem_object *obj;
1889 int plane = intel_crtc->plane;
1890 unsigned long Start, Offset;
1891 u32 dspcntr;
1892 u32 reg;
1893
1894 switch (plane) {
1895 case 0:
1896 case 1:
27f8227b 1897 case 2:
17638cd6
JB		 1898 break;
1899 default:
1900 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1901 return -EINVAL;
1902 }
1903
1904 intel_fb = to_intel_framebuffer(fb);
1905 obj = intel_fb->obj;
1906
1907 reg = DSPCNTR(plane);
1908 dspcntr = I915_READ(reg);
1909 /* Mask out pixel format bits in case we change it */
1910 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1911 switch (fb->bits_per_pixel) {
1912 case 8:
1913 dspcntr |= DISPPLANE_8BPP;
1914 break;
1915 case 16:
1916 if (fb->depth != 16)
1917 return -EINVAL;
1918
1919 dspcntr |= DISPPLANE_16BPP;
1920 break;
1921 case 24:
1922 case 32:
1923 if (fb->depth == 24)
1924 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1925 else if (fb->depth == 30)
1926 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1927 else
1928 return -EINVAL;
1929 break;
1930 default:
1931 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1932 return -EINVAL;
1933 }
1934
1935 if (obj->tiling_mode != I915_TILING_NONE)
1936 dspcntr |= DISPPLANE_TILED;
1937 else
1938 dspcntr &= ~DISPPLANE_TILED;
1939
1940 /* must disable */
1941 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1942
1943 I915_WRITE(reg, dspcntr);
1944
1945 Start = obj->gtt_offset;
01f2c773 1946 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1947
1948 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1949 Start, Offset, x, y, fb->pitches[0]);
1950 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1951 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1952 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1953 I915_WRITE(DSPADDR(plane), Offset);
1954 POSTING_READ(reg);
1955
1956 return 0;
1957}
1958
1959/* Assume fb object is pinned & idle & fenced and just update base pointers */
1960static int
1961intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1962 int x, int y, enum mode_set_atomic state)
1963{
1964 struct drm_device *dev = crtc->dev;
1965 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1966
6b8e6ed0
CW		 1967 if (dev_priv->display.disable_fbc)
1968 dev_priv->display.disable_fbc(dev);
3dec0095 1969 intel_increase_pllclock(crtc);
81255565 1970
6b8e6ed0 1971 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1972}
1973
14667a4b
CW		 1974static int
1975intel_finish_fb(struct drm_framebuffer *old_fb)
1976{
1977 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1978 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1979 bool was_interruptible = dev_priv->mm.interruptible;
1980 int ret;
1981
1982 wait_event(dev_priv->pending_flip_queue,
1983 atomic_read(&dev_priv->mm.wedged) ||
1984 atomic_read(&obj->pending_flip) == 0);
1985
1986 /* Big Hammer, we also need to ensure that any pending
1987 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1988 * current scanout is retired before unpinning the old
1989 * framebuffer.
1990 *
1991 * This should only fail upon a hung GPU, in which case we
1992 * can safely continue.
1993 */
1994 dev_priv->mm.interruptible = false;
1995 ret = i915_gem_object_finish_gpu(obj);
1996 dev_priv->mm.interruptible = was_interruptible;
1997
1998 return ret;
1999}
2000
5c3b82e2 2001static int
3c4fdcfb
KH		 2002intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2003 struct drm_framebuffer *old_fb)
79e53945
JB		 2004{
2005 struct drm_device *dev = crtc->dev;
6b8e6ed0 2006 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2007 struct drm_i915_master_private *master_priv;
2008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2009 int ret;
79e53945
JB		 2010
2011 /* no fb bound */
2012 if (!crtc->fb) {
a5071c2f 2013 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2014 return 0;
2015 }
2016
5826eca5
ED		 2017 if(intel_crtc->plane > dev_priv->num_pipe) {
2018 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2019 intel_crtc->plane,
2020 dev_priv->num_pipe);
5c3b82e2 2021 return -EINVAL;
79e53945
JB		 2022 }
2023
5c3b82e2 2024 mutex_lock(&dev->struct_mutex);
265db958
CW		 2025 ret = intel_pin_and_fence_fb_obj(dev,
2026 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2027 NULL);
5c3b82e2
CW		 2028 if (ret != 0) {
2029 mutex_unlock(&dev->struct_mutex);
a5071c2f 2030 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2031 return ret;
2032 }
79e53945 2033
14667a4b
CW		 2034 if (old_fb)
2035 intel_finish_fb(old_fb);
265db958 2036
6b8e6ed0 2037 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2038 if (ret) {
1690e1eb 2039 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2040 mutex_unlock(&dev->struct_mutex);
a5071c2f 2041 DRM_ERROR("failed to update base address\n");
4e6cfefc 2042 return ret;
79e53945 2043 }
3c4fdcfb 2044
b7f1de28
CW		 2045 if (old_fb) {
2046 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2047 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2048 }
652c393a 2049
6b8e6ed0 2050 intel_update_fbc(dev);
5c3b82e2 2051 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2052
2053 if (!dev->primary->master)
5c3b82e2 2054 return 0;
79e53945
JB		 2055
2056 master_priv = dev->primary->master->driver_priv;
2057 if (!master_priv->sarea_priv)
5c3b82e2 2058 return 0;
79e53945 2059
265db958 2060 if (intel_crtc->pipe) {
79e53945
JB		 2061 master_priv->sarea_priv->pipeB_x = x;
2062 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2063 } else {
2064 master_priv->sarea_priv->pipeA_x = x;
2065 master_priv->sarea_priv->pipeA_y = y;
79e53945 2066 }
5c3b82e2
CW		 2067
2068 return 0;
79e53945
JB		 2069}
2070
5eddb70b 2071static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2072{
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 u32 dpa_ctl;
2076
28c97730 2077 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2078 dpa_ctl = I915_READ(DP_A);
2079 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2080
2081 if (clock < 200000) {
2082 u32 temp;
2083 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2084 /* workaround for 160Mhz:
2085 1) program 0x4600c bits 15:0 = 0x8124
2086 2) program 0x46010 bit 0 = 1
2087 3) program 0x46034 bit 24 = 1
2088 4) program 0x64000 bit 14 = 1
2089 */
2090 temp = I915_READ(0x4600c);
2091 temp &= 0xffff0000;
2092 I915_WRITE(0x4600c, temp | 0x8124);
2093
2094 temp = I915_READ(0x46010);
2095 I915_WRITE(0x46010, temp | 1);
2096
2097 temp = I915_READ(0x46034);
2098 I915_WRITE(0x46034, temp | (1 << 24));
2099 } else {
2100 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2101 }
2102 I915_WRITE(DP_A, dpa_ctl);
2103
5eddb70b 2104 POSTING_READ(DP_A);
32f9d658
ZW		 2105 udelay(500);
2106}
2107
5e84e1a4
ZW		 2108static void intel_fdi_normal_train(struct drm_crtc *crtc)
2109{
2110 struct drm_device *dev = crtc->dev;
2111 struct drm_i915_private *dev_priv = dev->dev_private;
2112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2113 int pipe = intel_crtc->pipe;
2114 u32 reg, temp;
2115
2116 /* enable normal train */
2117 reg = FDI_TX_CTL(pipe);
2118 temp = I915_READ(reg);
61e499bf 2119 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2120 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2121 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2122 } else {
2123 temp &= ~FDI_LINK_TRAIN_NONE;
2124 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2125 }
5e84e1a4
ZW		 2126 I915_WRITE(reg, temp);
2127
2128 reg = FDI_RX_CTL(pipe);
2129 temp = I915_READ(reg);
2130 if (HAS_PCH_CPT(dev)) {
2131 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2132 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2133 } else {
2134 temp &= ~FDI_LINK_TRAIN_NONE;
2135 temp |= FDI_LINK_TRAIN_NONE;
2136 }
2137 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2138
2139 /* wait one idle pattern time */
2140 POSTING_READ(reg);
2141 udelay(1000);
357555c0
JB		 2142
2143 /* IVB wants error correction enabled */
2144 if (IS_IVYBRIDGE(dev))
2145 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2146 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2147}
2148
291427f5
JB		 2149static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2150{
2151 struct drm_i915_private *dev_priv = dev->dev_private;
2152 u32 flags = I915_READ(SOUTH_CHICKEN1);
2153
2154 flags |= FDI_PHASE_SYNC_OVR(pipe);
2155 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2156 flags |= FDI_PHASE_SYNC_EN(pipe);
2157 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2158 POSTING_READ(SOUTH_CHICKEN1);
2159}
2160
8db9d77b
ZW		 2161/* The FDI link training functions for ILK/Ibexpeak. */
2162static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2163{
2164 struct drm_device *dev = crtc->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167 int pipe = intel_crtc->pipe;
0fc932b8 2168 int plane = intel_crtc->plane;
5eddb70b 2169 u32 reg, temp, tries;
8db9d77b 2170
0fc932b8
JB		 2171 /* FDI needs bits from pipe & plane first */
2172 assert_pipe_enabled(dev_priv, pipe);
2173 assert_plane_enabled(dev_priv, plane);
2174
e1a44743
AJ		 2175 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2176 for train result */
5eddb70b
CW		 2177 reg = FDI_RX_IMR(pipe);
2178 temp = I915_READ(reg);
e1a44743
AJ		 2179 temp &= ~FDI_RX_SYMBOL_LOCK;
2180 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2181 I915_WRITE(reg, temp);
2182 I915_READ(reg);
e1a44743
AJ		 2183 udelay(150);
2184
8db9d77b 2185 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2186 reg = FDI_TX_CTL(pipe);
2187 temp = I915_READ(reg);
77ffb597
AJ		 2188 temp &= ~(7 << 19);
2189 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2190 temp &= ~FDI_LINK_TRAIN_NONE;
2191 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2192 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2193
5eddb70b
CW		 2194 reg = FDI_RX_CTL(pipe);
2195 temp = I915_READ(reg);
8db9d77b
ZW		 2196 temp &= ~FDI_LINK_TRAIN_NONE;
2197 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2198 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2199
2200 POSTING_READ(reg);
8db9d77b
ZW		 2201 udelay(150);
2202
5b2adf89 2203 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2204 if (HAS_PCH_IBX(dev)) {
2205 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2206 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2207 FDI_RX_PHASE_SYNC_POINTER_EN);
2208 }
5b2adf89 2209
5eddb70b 2210 reg = FDI_RX_IIR(pipe);
e1a44743 2211 for (tries = 0; tries < 5; tries++) {
5eddb70b 2212 temp = I915_READ(reg);
8db9d77b
ZW		 2213 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2214
2215 if ((temp & FDI_RX_BIT_LOCK)) {
2216 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2217 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2218 break;
2219 }
8db9d77b 2220 }
e1a44743 2221 if (tries == 5)
5eddb70b 2222 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2223
2224 /* Train 2 */
5eddb70b
CW		 2225 reg = FDI_TX_CTL(pipe);
2226 temp = I915_READ(reg);
8db9d77b
ZW		 2227 temp &= ~FDI_LINK_TRAIN_NONE;
2228 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2229 I915_WRITE(reg, temp);
8db9d77b 2230
5eddb70b
CW		 2231 reg = FDI_RX_CTL(pipe);
2232 temp = I915_READ(reg);
8db9d77b
ZW		 2233 temp &= ~FDI_LINK_TRAIN_NONE;
2234 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2235 I915_WRITE(reg, temp);
8db9d77b 2236
5eddb70b
CW		 2237 POSTING_READ(reg);
2238 udelay(150);
8db9d77b 2239
5eddb70b 2240 reg = FDI_RX_IIR(pipe);
e1a44743 2241 for (tries = 0; tries < 5; tries++) {
5eddb70b 2242 temp = I915_READ(reg);
8db9d77b
ZW		 2243 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2244
2245 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2246 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2247 DRM_DEBUG_KMS("FDI train 2 done.\n");
2248 break;
2249 }
8db9d77b 2250 }
e1a44743 2251 if (tries == 5)
5eddb70b 2252 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2253
2254 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2255
8db9d77b
ZW		 2256}
2257
0206e353 2258static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2259 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2260 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2261 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2262 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2263};
2264
2265/* The FDI link training functions for SNB/Cougarpoint. */
2266static void gen6_fdi_link_train(struct drm_crtc *crtc)
2267{
2268 struct drm_device *dev = crtc->dev;
2269 struct drm_i915_private *dev_priv = dev->dev_private;
2270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271 int pipe = intel_crtc->pipe;
fa37d39e 2272 u32 reg, temp, i, retry;
8db9d77b 2273
e1a44743
AJ		 2274 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2275 for train result */
5eddb70b
CW		 2276 reg = FDI_RX_IMR(pipe);
2277 temp = I915_READ(reg);
e1a44743
AJ		 2278 temp &= ~FDI_RX_SYMBOL_LOCK;
2279 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2280 I915_WRITE(reg, temp);
2281
2282 POSTING_READ(reg);
e1a44743
AJ		 2283 udelay(150);
2284
8db9d77b 2285 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2286 reg = FDI_TX_CTL(pipe);
2287 temp = I915_READ(reg);
77ffb597
AJ		 2288 temp &= ~(7 << 19);
2289 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2290 temp &= ~FDI_LINK_TRAIN_NONE;
2291 temp |= FDI_LINK_TRAIN_PATTERN_1;
2292 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2293 /* SNB-B */
2294 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2295 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2296
5eddb70b
CW		 2297 reg = FDI_RX_CTL(pipe);
2298 temp = I915_READ(reg);
8db9d77b
ZW		 2299 if (HAS_PCH_CPT(dev)) {
2300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2301 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2302 } else {
2303 temp &= ~FDI_LINK_TRAIN_NONE;
2304 temp |= FDI_LINK_TRAIN_PATTERN_1;
2305 }
5eddb70b
CW		 2306 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2307
2308 POSTING_READ(reg);
8db9d77b
ZW		 2309 udelay(150);
2310
291427f5
JB		 2311 if (HAS_PCH_CPT(dev))
2312 cpt_phase_pointer_enable(dev, pipe);
2313
0206e353 2314 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2315 reg = FDI_TX_CTL(pipe);
2316 temp = I915_READ(reg);
8db9d77b
ZW		 2317 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2318 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2319 I915_WRITE(reg, temp);
2320
2321 POSTING_READ(reg);
8db9d77b
ZW		 2322 udelay(500);
2323
fa37d39e
SP		 2324 for (retry = 0; retry < 5; retry++) {
2325 reg = FDI_RX_IIR(pipe);
2326 temp = I915_READ(reg);
2327 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2328 if (temp & FDI_RX_BIT_LOCK) {
2329 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2330 DRM_DEBUG_KMS("FDI train 1 done.\n");
2331 break;
2332 }
2333 udelay(50);
8db9d77b 2334 }
fa37d39e
SP		 2335 if (retry < 5)
2336 break;
8db9d77b
ZW		 2337 }
2338 if (i == 4)
5eddb70b 2339 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2340
2341 /* Train 2 */
5eddb70b
CW		 2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
8db9d77b
ZW		 2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_PATTERN_2;
2346 if (IS_GEN6(dev)) {
2347 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2348 /* SNB-B */
2349 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2350 }
5eddb70b 2351 I915_WRITE(reg, temp);
8db9d77b 2352
5eddb70b
CW		 2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
8db9d77b
ZW		 2355 if (HAS_PCH_CPT(dev)) {
2356 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2358 } else {
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_PATTERN_2;
2361 }
5eddb70b
CW		 2362 I915_WRITE(reg, temp);
2363
2364 POSTING_READ(reg);
8db9d77b
ZW		 2365 udelay(150);
2366
0206e353 2367 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2368 reg = FDI_TX_CTL(pipe);
2369 temp = I915_READ(reg);
8db9d77b
ZW		 2370 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2371 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2372 I915_WRITE(reg, temp);
2373
2374 POSTING_READ(reg);
8db9d77b
ZW		 2375 udelay(500);
2376
fa37d39e
SP		 2377 for (retry = 0; retry < 5; retry++) {
2378 reg = FDI_RX_IIR(pipe);
2379 temp = I915_READ(reg);
2380 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2381 if (temp & FDI_RX_SYMBOL_LOCK) {
2382 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2383 DRM_DEBUG_KMS("FDI train 2 done.\n");
2384 break;
2385 }
2386 udelay(50);
8db9d77b 2387 }
fa37d39e
SP		 2388 if (retry < 5)
2389 break;
8db9d77b
ZW		 2390 }
2391 if (i == 4)
5eddb70b 2392 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2393
2394 DRM_DEBUG_KMS("FDI train done.\n");
2395}
2396
357555c0
JB		 2397/* Manual link training for Ivy Bridge A0 parts */
2398static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2399{
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2404 u32 reg, temp, i;
2405
2406 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2407 for train result */
2408 reg = FDI_RX_IMR(pipe);
2409 temp = I915_READ(reg);
2410 temp &= ~FDI_RX_SYMBOL_LOCK;
2411 temp &= ~FDI_RX_BIT_LOCK;
2412 I915_WRITE(reg, temp);
2413
2414 POSTING_READ(reg);
2415 udelay(150);
2416
2417 /* enable CPU FDI TX and PCH FDI RX */
2418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
2420 temp &= ~(7 << 19);
2421 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2422 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2423 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2424 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2425 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2426 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2427 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2428
2429 reg = FDI_RX_CTL(pipe);
2430 temp = I915_READ(reg);
2431 temp &= ~FDI_LINK_TRAIN_AUTO;
2432 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2434 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2435 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2436
2437 POSTING_READ(reg);
2438 udelay(150);
2439
291427f5
JB		 2440 if (HAS_PCH_CPT(dev))
2441 cpt_phase_pointer_enable(dev, pipe);
2442
0206e353 2443 for (i = 0; i < 4; i++) {
357555c0
JB		 2444 reg = FDI_TX_CTL(pipe);
2445 temp = I915_READ(reg);
2446 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2447 temp |= snb_b_fdi_train_param[i];
2448 I915_WRITE(reg, temp);
2449
2450 POSTING_READ(reg);
2451 udelay(500);
2452
2453 reg = FDI_RX_IIR(pipe);
2454 temp = I915_READ(reg);
2455 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2456
2457 if (temp & FDI_RX_BIT_LOCK ||
2458 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2459 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2460 DRM_DEBUG_KMS("FDI train 1 done.\n");
2461 break;
2462 }
2463 }
2464 if (i == 4)
2465 DRM_ERROR("FDI train 1 fail!\n");
2466
2467 /* Train 2 */
2468 reg = FDI_TX_CTL(pipe);
2469 temp = I915_READ(reg);
2470 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2471 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2474 I915_WRITE(reg, temp);
2475
2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480 I915_WRITE(reg, temp);
2481
2482 POSTING_READ(reg);
2483 udelay(150);
2484
0206e353 2485 for (i = 0; i < 4; i++) {
357555c0
JB		 2486 reg = FDI_TX_CTL(pipe);
2487 temp = I915_READ(reg);
2488 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2489 temp |= snb_b_fdi_train_param[i];
2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
2493 udelay(500);
2494
2495 reg = FDI_RX_IIR(pipe);
2496 temp = I915_READ(reg);
2497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2498
2499 if (temp & FDI_RX_SYMBOL_LOCK) {
2500 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2501 DRM_DEBUG_KMS("FDI train 2 done.\n");
2502 break;
2503 }
2504 }
2505 if (i == 4)
2506 DRM_ERROR("FDI train 2 fail!\n");
2507
2508 DRM_DEBUG_KMS("FDI train done.\n");
2509}
2510
2511static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2512{
2513 struct drm_device *dev = crtc->dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516 int pipe = intel_crtc->pipe;
5eddb70b 2517 u32 reg, temp;
79e53945 2518
c64e311e 2519 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2520 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2521 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2522
c98e9dcf 2523 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
2526 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2527 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2528 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2529 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2530
2531 POSTING_READ(reg);
c98e9dcf
JB		 2532 udelay(200);
2533
2534 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2535 temp = I915_READ(reg);
2536 I915_WRITE(reg, temp | FDI_PCDCLK);
2537
2538 POSTING_READ(reg);
c98e9dcf
JB		 2539 udelay(200);
2540
bf507ef7
ED		 2541 /* On Haswell, the PLL configuration for ports and pipes is handled
2542 * separately, as part of DDI setup */
2543 if (!IS_HASWELL(dev)) {
2544 /* Enable CPU FDI TX PLL, always on for Ironlake */
2545 reg = FDI_TX_CTL(pipe);
2546 temp = I915_READ(reg);
2547 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2548 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2549
bf507ef7
ED		 2550 POSTING_READ(reg);
2551 udelay(100);
2552 }
6be4a607 2553 }
0e23b99d
JB		 2554}
2555
291427f5
JB		 2556static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2557{
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559 u32 flags = I915_READ(SOUTH_CHICKEN1);
2560
2561 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2562 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2563 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2564 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2565 POSTING_READ(SOUTH_CHICKEN1);
2566}
0fc932b8
JB		 2567static void ironlake_fdi_disable(struct drm_crtc *crtc)
2568{
2569 struct drm_device *dev = crtc->dev;
2570 struct drm_i915_private *dev_priv = dev->dev_private;
2571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2572 int pipe = intel_crtc->pipe;
2573 u32 reg, temp;
2574
2575 /* disable CPU FDI tx and PCH FDI rx */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
2578 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2579 POSTING_READ(reg);
2580
2581 reg = FDI_RX_CTL(pipe);
2582 temp = I915_READ(reg);
2583 temp &= ~(0x7 << 16);
2584 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2585 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2586
2587 POSTING_READ(reg);
2588 udelay(100);
2589
2590 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2591 if (HAS_PCH_IBX(dev)) {
2592 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2593 I915_WRITE(FDI_RX_CHICKEN(pipe),
2594 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2595 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2596 } else if (HAS_PCH_CPT(dev)) {
2597 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2598 }
0fc932b8
JB		 2599
2600 /* still set train pattern 1 */
2601 reg = FDI_TX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_LINK_TRAIN_NONE;
2604 temp |= FDI_LINK_TRAIN_PATTERN_1;
2605 I915_WRITE(reg, temp);
2606
2607 reg = FDI_RX_CTL(pipe);
2608 temp = I915_READ(reg);
2609 if (HAS_PCH_CPT(dev)) {
2610 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2611 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2612 } else {
2613 temp &= ~FDI_LINK_TRAIN_NONE;
2614 temp |= FDI_LINK_TRAIN_PATTERN_1;
2615 }
2616 /* BPC in FDI rx is consistent with that in PIPECONF */
2617 temp &= ~(0x07 << 16);
2618 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2619 I915_WRITE(reg, temp);
2620
2621 POSTING_READ(reg);
2622 udelay(100);
2623}
2624
e6c3a2a6
CW		 2625static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2626{
0f91128d 2627 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2628
2629 if (crtc->fb == NULL)
2630 return;
2631
0f91128d
CW		 2632 mutex_lock(&dev->struct_mutex);
2633 intel_finish_fb(crtc->fb);
2634 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2635}
2636
040484af
JB		 2637static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_mode_config *mode_config = &dev->mode_config;
2641 struct intel_encoder *encoder;
2642
2643 /*
2644 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2645 * must be driven by its own crtc; no sharing is possible.
2646 */
2647 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2648 if (encoder->base.crtc != crtc)
2649 continue;
2650
6ee8bab0
ED		 2651 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2652 * CPU handles all others */
2653 if (IS_HASWELL(dev)) {
2654 /* It is still unclear how this will work on PPT, so throw up a warning */
2655 WARN_ON(!HAS_PCH_LPT(dev));
2656
2657 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2658 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2659 return true;
2660 } else {
2661 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2662 encoder->type);
2663 return false;
2664 }
2665 }
2666
040484af
JB		 2667 switch (encoder->type) {
2668 case INTEL_OUTPUT_EDP:
2669 if (!intel_encoder_is_pch_edp(&encoder->base))
2670 return false;
2671 continue;
2672 }
2673 }
2674
2675 return true;
2676}
2677
e615efe4
ED		 2678/* Program iCLKIP clock to the desired frequency */
2679static void lpt_program_iclkip(struct drm_crtc *crtc)
2680{
2681 struct drm_device *dev = crtc->dev;
2682 struct drm_i915_private *dev_priv = dev->dev_private;
2683 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2684 u32 temp;
2685
2686 /* It is necessary to ungate the pixclk gate prior to programming
2687 * the divisors, and gate it back when it is done.
2688 */
2689 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2690
2691 /* Disable SSCCTL */
2692 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2693 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2694 SBI_SSCCTL_DISABLE);
2695
2696 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2697 if (crtc->mode.clock == 20000) {
2698 auxdiv = 1;
2699 divsel = 0x41;
2700 phaseinc = 0x20;
2701 } else {
2702 /* The iCLK virtual clock root frequency is in MHz,
2703 * but the crtc->mode.clock in in KHz. To get the divisors,
2704 * it is necessary to divide one by another, so we
2705 * convert the virtual clock precision to KHz here for higher
2706 * precision.
2707 */
2708 u32 iclk_virtual_root_freq = 172800 * 1000;
2709 u32 iclk_pi_range = 64;
2710 u32 desired_divisor, msb_divisor_value, pi_value;
2711
2712 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2713 msb_divisor_value = desired_divisor / iclk_pi_range;
2714 pi_value = desired_divisor % iclk_pi_range;
2715
2716 auxdiv = 0;
2717 divsel = msb_divisor_value - 2;
2718 phaseinc = pi_value;
2719 }
2720
2721 /* This should not happen with any sane values */
2722 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2723 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2724 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2725 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2726
2727 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2728 crtc->mode.clock,
2729 auxdiv,
2730 divsel,
2731 phasedir,
2732 phaseinc);
2733
2734 /* Program SSCDIVINTPHASE6 */
2735 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2736 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2737 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2738 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2739 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2740 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2741 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2742
2743 intel_sbi_write(dev_priv,
2744 SBI_SSCDIVINTPHASE6,
2745 temp);
2746
2747 /* Program SSCAUXDIV */
2748 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2749 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2750 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2751 intel_sbi_write(dev_priv,
2752 SBI_SSCAUXDIV6,
2753 temp);
2754
2755
2756 /* Enable modulator and associated divider */
2757 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2758 temp &= ~SBI_SSCCTL_DISABLE;
2759 intel_sbi_write(dev_priv,
2760 SBI_SSCCTL6,
2761 temp);
2762
2763 /* Wait for initialization time */
2764 udelay(24);
2765
2766 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2767}
2768
f67a559d
JB		 2769/*
2770 * Enable PCH resources required for PCH ports:
2771 * - PCH PLLs
2772 * - FDI training & RX/TX
2773 * - update transcoder timings
2774 * - DP transcoding bits
2775 * - transcoder
2776 */
2777static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2778{
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782 int pipe = intel_crtc->pipe;
ee7b9f93 2783 u32 reg, temp;
2c07245f 2784
c98e9dcf 2785 /* For PCH output, training FDI link */
674cf967 2786 dev_priv->display.fdi_link_train(crtc);
2c07245f 2787
e615efe4
ED		 2788 if (HAS_PCH_LPT(dev)) {
2789 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2790 lpt_program_iclkip(crtc);
2791 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2792 u32 sel;
4b645f14 2793
e615efe4
ED		 2794 intel_enable_pch_pll(intel_crtc);
2795
c98e9dcf 2796 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2797 switch (pipe) {
2798 default:
2799 case 0:
2800 temp |= TRANSA_DPLL_ENABLE;
2801 sel = TRANSA_DPLLB_SEL;
2802 break;
2803 case 1:
2804 temp |= TRANSB_DPLL_ENABLE;
2805 sel = TRANSB_DPLLB_SEL;
2806 break;
2807 case 2:
2808 temp |= TRANSC_DPLL_ENABLE;
2809 sel = TRANSC_DPLLB_SEL;
2810 break;
d64311ab 2811 }
ee7b9f93
JB		 2812 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2813 temp |= sel;
2814 else
2815 temp &= ~sel;
c98e9dcf 2816 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2817 }
5eddb70b 2818
d9b6cb56
JB		 2819 /* set transcoder timing, panel must allow it */
2820 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2821 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2822 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2823 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2824
5eddb70b
CW		 2825 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2826 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2827 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2828 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2829
f57e1e3a
ED		 2830 if (!IS_HASWELL(dev))
2831 intel_fdi_normal_train(crtc);
5e84e1a4 2832
c98e9dcf
JB		 2833 /* For PCH DP, enable TRANS_DP_CTL */
2834 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2835 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2836 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2837 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2838 reg = TRANS_DP_CTL(pipe);
2839 temp = I915_READ(reg);
2840 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2841 TRANS_DP_SYNC_MASK |
2842 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2843 temp |= (TRANS_DP_OUTPUT_ENABLE |
2844 TRANS_DP_ENH_FRAMING);
9325c9f0 2845 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2846
2847 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2848 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2849 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2850 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2851
2852 switch (intel_trans_dp_port_sel(crtc)) {
2853 case PCH_DP_B:
5eddb70b 2854 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2855 break;
2856 case PCH_DP_C:
5eddb70b 2857 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2858 break;
2859 case PCH_DP_D:
5eddb70b 2860 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2861 break;
2862 default:
2863 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2864 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2865 break;
32f9d658 2866 }
2c07245f 2867
5eddb70b 2868 I915_WRITE(reg, temp);
6be4a607 2869 }
b52eb4dc 2870
040484af 2871 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2872}
2873
ee7b9f93
JB		 2874static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2875{
2876 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2877
2878 if (pll == NULL)
2879 return;
2880
2881 if (pll->refcount == 0) {
2882 WARN(1, "bad PCH PLL refcount\n");
2883 return;
2884 }
2885
2886 --pll->refcount;
2887 intel_crtc->pch_pll = NULL;
2888}
2889
2890static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2891{
2892 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2893 struct intel_pch_pll *pll;
2894 int i;
2895
2896 pll = intel_crtc->pch_pll;
2897 if (pll) {
2898 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2899 intel_crtc->base.base.id, pll->pll_reg);
2900 goto prepare;
2901 }
2902
2903 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2904 pll = &dev_priv->pch_plls[i];
2905
2906 /* Only want to check enabled timings first */
2907 if (pll->refcount == 0)
2908 continue;
2909
2910 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2911 fp == I915_READ(pll->fp0_reg)) {
2912 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2913 intel_crtc->base.base.id,
2914 pll->pll_reg, pll->refcount, pll->active);
2915
2916 goto found;
2917 }
2918 }
2919
2920 /* Ok no matching timings, maybe there's a free one? */
2921 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2922 pll = &dev_priv->pch_plls[i];
2923 if (pll->refcount == 0) {
2924 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2925 intel_crtc->base.base.id, pll->pll_reg);
2926 goto found;
2927 }
2928 }
2929
2930 return NULL;
2931
2932found:
2933 intel_crtc->pch_pll = pll;
2934 pll->refcount++;
2935 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2936prepare: /* separate function? */
2937 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 2938
e04c7350
CW		 2939 /* Wait for the clocks to stabilize before rewriting the regs */
2940 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2941 POSTING_READ(pll->pll_reg);
2942 udelay(150);
e04c7350
CW		 2943
2944 I915_WRITE(pll->fp0_reg, fp);
2945 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2946 pll->on = false;
2947 return pll;
2948}
2949
d4270e57
JB		 2950void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2951{
2952 struct drm_i915_private *dev_priv = dev->dev_private;
2953 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2954 u32 temp;
2955
2956 temp = I915_READ(dslreg);
2957 udelay(500);
2958 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2959 /* Without this, mode sets may fail silently on FDI */
2960 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2961 udelay(250);
2962 I915_WRITE(tc2reg, 0);
2963 if (wait_for(I915_READ(dslreg) != temp, 5))
2964 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2965 }
2966}
2967
f67a559d
JB		 2968static void ironlake_crtc_enable(struct drm_crtc *crtc)
2969{
2970 struct drm_device *dev = crtc->dev;
2971 struct drm_i915_private *dev_priv = dev->dev_private;
2972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2973 int pipe = intel_crtc->pipe;
2974 int plane = intel_crtc->plane;
2975 u32 temp;
2976 bool is_pch_port;
2977
2978 if (intel_crtc->active)
2979 return;
2980
2981 intel_crtc->active = true;
2982 intel_update_watermarks(dev);
2983
2984 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2985 temp = I915_READ(PCH_LVDS);
2986 if ((temp & LVDS_PORT_EN) == 0)
2987 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2988 }
2989
2990 is_pch_port = intel_crtc_driving_pch(crtc);
2991
2992 if (is_pch_port)
357555c0 2993 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2994 else
2995 ironlake_fdi_disable(crtc);
2996
2997 /* Enable panel fitting for LVDS */
2998 if (dev_priv->pch_pf_size &&
2999 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3000 /* Force use of hard-coded filter coefficients
3001 * as some pre-programmed values are broken,
3002 * e.g. x201.
3003 */
9db4a9c7
JB		 3004 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3005 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3006 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3007 }
3008
9c54c0dd
JB		 3009 /*
3010 * On ILK+ LUT must be loaded before the pipe is running but with
3011 * clocks enabled
3012 */
3013 intel_crtc_load_lut(crtc);
3014
f67a559d
JB		 3015 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3016 intel_enable_plane(dev_priv, plane, pipe);
3017
3018 if (is_pch_port)
3019 ironlake_pch_enable(crtc);
c98e9dcf 3020
d1ebd816 3021 mutex_lock(&dev->struct_mutex);
bed4a673 3022 intel_update_fbc(dev);
d1ebd816
BW		 3023 mutex_unlock(&dev->struct_mutex);
3024
6b383a7f 3025 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3026}
3027
3028static void ironlake_crtc_disable(struct drm_crtc *crtc)
3029{
3030 struct drm_device *dev = crtc->dev;
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3033 int pipe = intel_crtc->pipe;
3034 int plane = intel_crtc->plane;
5eddb70b 3035 u32 reg, temp;
b52eb4dc 3036
f7abfe8b
CW		 3037 if (!intel_crtc->active)
3038 return;
3039
e6c3a2a6 3040 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3041 drm_vblank_off(dev, pipe);
6b383a7f 3042 intel_crtc_update_cursor(crtc, false);
5eddb70b 3043
b24e7179 3044 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3045
973d04f9
CW		 3046 if (dev_priv->cfb_plane == plane)
3047 intel_disable_fbc(dev);
2c07245f 3048
b24e7179 3049 intel_disable_pipe(dev_priv, pipe);
32f9d658 3050
6be4a607 3051 /* Disable PF */
9db4a9c7
JB		 3052 I915_WRITE(PF_CTL(pipe), 0);
3053 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3054
0fc932b8 3055 ironlake_fdi_disable(crtc);
2c07245f 3056
47a05eca
JB		 3057 /* This is a horrible layering violation; we should be doing this in
3058 * the connector/encoder ->prepare instead, but we don't always have
3059 * enough information there about the config to know whether it will
3060 * actually be necessary or just cause undesired flicker.
3061 */
3062 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3063
040484af 3064 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3065
6be4a607
JB		 3066 if (HAS_PCH_CPT(dev)) {
3067 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3068 reg = TRANS_DP_CTL(pipe);
3069 temp = I915_READ(reg);
3070 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3071 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3072 I915_WRITE(reg, temp);
6be4a607
JB		 3073
3074 /* disable DPLL_SEL */
3075 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3076 switch (pipe) {
3077 case 0:
d64311ab 3078 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3079 break;
3080 case 1:
6be4a607 3081 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3082 break;
3083 case 2:
4b645f14 3084 /* C shares PLL A or B */
d64311ab 3085 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3086 break;
3087 default:
3088 BUG(); /* wtf */
3089 }
6be4a607 3090 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3091 }
e3421a18 3092
6be4a607 3093 /* disable PCH DPLL */
ee7b9f93 3094 intel_disable_pch_pll(intel_crtc);
8db9d77b 3095
6be4a607 3096 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3097 reg = FDI_RX_CTL(pipe);
3098 temp = I915_READ(reg);
3099 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3100
6be4a607 3101 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3102 reg = FDI_TX_CTL(pipe);
3103 temp = I915_READ(reg);
3104 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3105
3106 POSTING_READ(reg);
6be4a607 3107 udelay(100);
8db9d77b 3108
5eddb70b
CW		 3109 reg = FDI_RX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3112
6be4a607 3113 /* Wait for the clocks to turn off. */
5eddb70b 3114 POSTING_READ(reg);
6be4a607 3115 udelay(100);
6b383a7f 3116
f7abfe8b 3117 intel_crtc->active = false;
6b383a7f 3118 intel_update_watermarks(dev);
d1ebd816
BW		 3119
3120 mutex_lock(&dev->struct_mutex);
6b383a7f 3121 intel_update_fbc(dev);
d1ebd816 3122 mutex_unlock(&dev->struct_mutex);
6be4a607 3123}
1b3c7a47 3124
6be4a607
JB		 3125static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3126{
3127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3128 int pipe = intel_crtc->pipe;
3129 int plane = intel_crtc->plane;
8db9d77b 3130
6be4a607
JB		 3131 /* XXX: When our outputs are all unaware of DPMS modes other than off
3132 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3133 */
3134 switch (mode) {
3135 case DRM_MODE_DPMS_ON:
3136 case DRM_MODE_DPMS_STANDBY:
3137 case DRM_MODE_DPMS_SUSPEND:
3138 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3139 ironlake_crtc_enable(crtc);
3140 break;
1b3c7a47 3141
6be4a607
JB		 3142 case DRM_MODE_DPMS_OFF:
3143 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3144 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3145 break;
3146 }
3147}
3148
ee7b9f93
JB		 3149static void ironlake_crtc_off(struct drm_crtc *crtc)
3150{
3151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3152 intel_put_pch_pll(intel_crtc);
3153}
3154
02e792fb
DV		 3155static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3156{
02e792fb 3157 if (!enable && intel_crtc->overlay) {
23f09ce3 3158 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3159 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3160
23f09ce3 3161 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3162 dev_priv->mm.interruptible = false;
3163 (void) intel_overlay_switch_off(intel_crtc->overlay);
3164 dev_priv->mm.interruptible = true;
23f09ce3 3165 mutex_unlock(&dev->struct_mutex);
02e792fb 3166 }
02e792fb 3167
5dcdbcb0
CW		 3168 /* Let userspace switch the overlay on again. In most cases userspace
3169 * has to recompute where to put it anyway.
3170 */
02e792fb
DV		 3171}
3172
0b8765c6 3173static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3174{
3175 struct drm_device *dev = crtc->dev;
79e53945
JB		 3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3178 int pipe = intel_crtc->pipe;
80824003 3179 int plane = intel_crtc->plane;
79e53945 3180
f7abfe8b
CW		 3181 if (intel_crtc->active)
3182 return;
3183
3184 intel_crtc->active = true;
6b383a7f
CW		 3185 intel_update_watermarks(dev);
3186
63d7bbe9 3187 intel_enable_pll(dev_priv, pipe);
040484af 3188 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3189 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3190
0b8765c6 3191 intel_crtc_load_lut(crtc);
bed4a673 3192 intel_update_fbc(dev);
79e53945 3193
0b8765c6
JB		 3194 /* Give the overlay scaler a chance to enable if it's on this pipe */
3195 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3196 intel_crtc_update_cursor(crtc, true);
0b8765c6 3197}
79e53945 3198
0b8765c6
JB		 3199static void i9xx_crtc_disable(struct drm_crtc *crtc)
3200{
3201 struct drm_device *dev = crtc->dev;
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3204 int pipe = intel_crtc->pipe;
3205 int plane = intel_crtc->plane;
b690e96c 3206
f7abfe8b
CW		 3207 if (!intel_crtc->active)
3208 return;
3209
0b8765c6 3210 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3211 intel_crtc_wait_for_pending_flips(crtc);
3212 drm_vblank_off(dev, pipe);
0b8765c6 3213 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3214 intel_crtc_update_cursor(crtc, false);
0b8765c6 3215
973d04f9
CW		 3216 if (dev_priv->cfb_plane == plane)
3217 intel_disable_fbc(dev);
79e53945 3218
b24e7179 3219 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3220 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3221 intel_disable_pll(dev_priv, pipe);
0b8765c6 3222
f7abfe8b 3223 intel_crtc->active = false;
6b383a7f
CW		 3224 intel_update_fbc(dev);
3225 intel_update_watermarks(dev);
0b8765c6
JB		 3226}
3227
3228static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3229{
3230 /* XXX: When our outputs are all unaware of DPMS modes other than off
3231 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3232 */
3233 switch (mode) {
3234 case DRM_MODE_DPMS_ON:
3235 case DRM_MODE_DPMS_STANDBY:
3236 case DRM_MODE_DPMS_SUSPEND:
3237 i9xx_crtc_enable(crtc);
3238 break;
3239 case DRM_MODE_DPMS_OFF:
3240 i9xx_crtc_disable(crtc);
79e53945
JB		 3241 break;
3242 }
2c07245f
ZW		 3243}
3244
ee7b9f93
JB		 3245static void i9xx_crtc_off(struct drm_crtc *crtc)
3246{
3247}
3248
2c07245f
ZW		 3249/**
3250 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3251 */
3252static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3253{
3254 struct drm_device *dev = crtc->dev;
e70236a8 3255 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3256 struct drm_i915_master_private *master_priv;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258 int pipe = intel_crtc->pipe;
3259 bool enabled;
3260
032d2a0d
CW		 3261 if (intel_crtc->dpms_mode == mode)
3262 return;
3263
65655d4a 3264 intel_crtc->dpms_mode = mode;
debcaddc 3265
e70236a8 3266 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3267
3268 if (!dev->primary->master)
3269 return;
3270
3271 master_priv = dev->primary->master->driver_priv;
3272 if (!master_priv->sarea_priv)
3273 return;
3274
3275 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3276
3277 switch (pipe) {
3278 case 0:
3279 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3280 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3281 break;
3282 case 1:
3283 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3284 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3285 break;
3286 default:
9db4a9c7 3287 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3288 break;
3289 }
79e53945
JB		 3290}
3291
cdd59983
CW		 3292static void intel_crtc_disable(struct drm_crtc *crtc)
3293{
3294 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3295 struct drm_device *dev = crtc->dev;
ee7b9f93 3296 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3297
3298 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3299 dev_priv->display.off(crtc);
3300
931872fc
CW		 3301 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3302 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3303
3304 if (crtc->fb) {
3305 mutex_lock(&dev->struct_mutex);
1690e1eb 3306 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3307 mutex_unlock(&dev->struct_mutex);
3308 }
3309}
3310
7e7d76c3
JB		 3311/* Prepare for a mode set.
3312 *
3313 * Note we could be a lot smarter here. We need to figure out which outputs
3314 * will be enabled, which disabled (in short, how the config will changes)
3315 * and perform the minimum necessary steps to accomplish that, e.g. updating
3316 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3317 * panel fitting is in the proper state, etc.
3318 */
3319static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3320{
7e7d76c3 3321 i9xx_crtc_disable(crtc);
79e53945
JB		 3322}
3323
7e7d76c3 3324static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3325{
7e7d76c3 3326 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3327}
3328
3329static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3330{
7e7d76c3 3331 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3332}
3333
3334static void ironlake_crtc_commit(struct drm_crtc *crtc)
3335{
7e7d76c3 3336 ironlake_crtc_enable(crtc);
79e53945
JB		 3337}
3338
0206e353 3339void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3340{
3341 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3342 /* lvds has its own version of prepare see intel_lvds_prepare */
3343 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3344}
3345
0206e353 3346void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3347{
3348 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3349 struct drm_device *dev = encoder->dev;
d47d7cb8 3350 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3351
79e53945
JB		 3352 /* lvds has its own version of commit see intel_lvds_commit */
3353 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3354
3355 if (HAS_PCH_CPT(dev))
3356 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3357}
3358
ea5b213a
CW		 3359void intel_encoder_destroy(struct drm_encoder *encoder)
3360{
4ef69c7a 3361 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3362
ea5b213a
CW		 3363 drm_encoder_cleanup(encoder);
3364 kfree(intel_encoder);
3365}
3366
79e53945
JB		 3367static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3368 struct drm_display_mode *mode,
3369 struct drm_display_mode *adjusted_mode)
3370{
2c07245f 3371 struct drm_device *dev = crtc->dev;
89749350 3372
bad720ff 3373 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3374 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3375 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3376 return false;
2c07245f 3377 }
89749350 3378
f9bef081
DV		 3379 /* All interlaced capable intel hw wants timings in frames. Note though
3380 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3381 * timings, so we need to be careful not to clobber these.*/
3382 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3383 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3384
79e53945
JB		 3385 return true;
3386}
3387
25eb05fc
JB		 3388static int valleyview_get_display_clock_speed(struct drm_device *dev)
3389{
3390 return 400000; /* FIXME */
3391}
3392
e70236a8
JB		 3393static int i945_get_display_clock_speed(struct drm_device *dev)
3394{
3395 return 400000;
3396}
79e53945 3397
e70236a8 3398static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3399{
e70236a8
JB		 3400 return 333000;
3401}
79e53945 3402
e70236a8
JB		 3403static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3404{
3405 return 200000;
3406}
79e53945 3407
e70236a8
JB		 3408static int i915gm_get_display_clock_speed(struct drm_device *dev)
3409{
3410 u16 gcfgc = 0;
79e53945 3411
e70236a8
JB		 3412 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3413
3414 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3415 return 133000;
3416 else {
3417 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3418 case GC_DISPLAY_CLOCK_333_MHZ:
3419 return 333000;
3420 default:
3421 case GC_DISPLAY_CLOCK_190_200_MHZ:
3422 return 190000;
79e53945 3423 }
e70236a8
JB		 3424 }
3425}
3426
3427static int i865_get_display_clock_speed(struct drm_device *dev)
3428{
3429 return 266000;
3430}
3431
3432static int i855_get_display_clock_speed(struct drm_device *dev)
3433{
3434 u16 hpllcc = 0;
3435 /* Assume that the hardware is in the high speed state. This
3436 * should be the default.
3437 */
3438 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3439 case GC_CLOCK_133_200:
3440 case GC_CLOCK_100_200:
3441 return 200000;
3442 case GC_CLOCK_166_250:
3443 return 250000;
3444 case GC_CLOCK_100_133:
79e53945 3445 return 133000;
e70236a8 3446 }
79e53945 3447
e70236a8
JB		 3448 /* Shouldn't happen */
3449 return 0;
3450}
79e53945 3451
e70236a8
JB		 3452static int i830_get_display_clock_speed(struct drm_device *dev)
3453{
3454 return 133000;
79e53945
JB		 3455}
3456
2c07245f
ZW		 3457struct fdi_m_n {
3458 u32 tu;
3459 u32 gmch_m;
3460 u32 gmch_n;
3461 u32 link_m;
3462 u32 link_n;
3463};
3464
3465static void
3466fdi_reduce_ratio(u32 *num, u32 *den)
3467{
3468 while (*num > 0xffffff || *den > 0xffffff) {
3469 *num >>= 1;
3470 *den >>= 1;
3471 }
3472}
3473
2c07245f 3474static void
f2b115e6
AJ		 3475ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3476 int link_clock, struct fdi_m_n *m_n)
2c07245f 3477{
2c07245f
ZW		 3478 m_n->tu = 64; /* default size */
3479
22ed1113
CW		 3480 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3481 m_n->gmch_m = bits_per_pixel * pixel_clock;
3482 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3483 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3484
22ed1113
CW		 3485 m_n->link_m = pixel_clock;
3486 m_n->link_n = link_clock;
2c07245f
ZW		 3487 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3488}
3489
a7615030
CW		 3490static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3491{
72bbe58c
KP		 3492 if (i915_panel_use_ssc >= 0)
3493 return i915_panel_use_ssc != 0;
3494 return dev_priv->lvds_use_ssc
435793df 3495 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3496}
3497
5a354204
JB		 3498/**
3499 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3500 * @crtc: CRTC structure
3b5c78a3 3501 * @mode: requested mode
5a354204
JB		 3502 *
3503 * A pipe may be connected to one or more outputs. Based on the depth of the
3504 * attached framebuffer, choose a good color depth to use on the pipe.
3505 *
3506 * If possible, match the pipe depth to the fb depth. In some cases, this
3507 * isn't ideal, because the connected output supports a lesser or restricted
3508 * set of depths. Resolve that here:
3509 * LVDS typically supports only 6bpc, so clamp down in that case
3510 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3511 * Displays may support a restricted set as well, check EDID and clamp as
3512 * appropriate.
3b5c78a3 3513 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3514 *
3515 * RETURNS:
3516 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3517 * true if they don't match).
3518 */
3519static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3520 unsigned int *pipe_bpp,
3521 struct drm_display_mode *mode)
5a354204
JB		 3522{
3523 struct drm_device *dev = crtc->dev;
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525 struct drm_encoder *encoder;
3526 struct drm_connector *connector;
3527 unsigned int display_bpc = UINT_MAX, bpc;
3528
3529 /* Walk the encoders & connectors on this crtc, get min bpc */
3530 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3531 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3532
3533 if (encoder->crtc != crtc)
3534 continue;
3535
3536 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3537 unsigned int lvds_bpc;
3538
3539 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3540 LVDS_A3_POWER_UP)
3541 lvds_bpc = 8;
3542 else
3543 lvds_bpc = 6;
3544
3545 if (lvds_bpc < display_bpc) {
82820490 3546 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3547 display_bpc = lvds_bpc;
3548 }
3549 continue;
3550 }
3551
3552 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3553 /* Use VBT settings if we have an eDP panel */
3554 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3555
3556 if (edp_bpc < display_bpc) {
82820490 3557 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3558 display_bpc = edp_bpc;
3559 }
3560 continue;
3561 }
3562
3563 /* Not one of the known troublemakers, check the EDID */
3564 list_for_each_entry(connector, &dev->mode_config.connector_list,
3565 head) {
3566 if (connector->encoder != encoder)
3567 continue;
3568
62ac41a6
JB		 3569 /* Don't use an invalid EDID bpc value */
3570 if (connector->display_info.bpc &&
3571 connector->display_info.bpc < display_bpc) {
82820490 3572 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3573 display_bpc = connector->display_info.bpc;
3574 }
3575 }
3576
3577 /*
3578 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3579 * through, clamp it down. (Note: >12bpc will be caught below.)
3580 */
3581 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3582 if (display_bpc > 8 && display_bpc < 12) {
82820490 3583 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3584 display_bpc = 12;
3585 } else {
82820490 3586 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3587 display_bpc = 8;
3588 }
3589 }
3590 }
3591
3b5c78a3
AJ		 3592 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3593 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3594 display_bpc = 6;
3595 }
3596
5a354204
JB		 3597 /*
3598 * We could just drive the pipe at the highest bpc all the time and
3599 * enable dithering as needed, but that costs bandwidth. So choose
3600 * the minimum value that expresses the full color range of the fb but
3601 * also stays within the max display bpc discovered above.
3602 */
3603
3604 switch (crtc->fb->depth) {
3605 case 8:
3606 bpc = 8; /* since we go through a colormap */
3607 break;
3608 case 15:
3609 case 16:
3610 bpc = 6; /* min is 18bpp */
3611 break;
3612 case 24:
578393cd 3613 bpc = 8;
5a354204
JB		 3614 break;
3615 case 30:
578393cd 3616 bpc = 10;
5a354204
JB		 3617 break;
3618 case 48:
578393cd 3619 bpc = 12;
5a354204
JB		 3620 break;
3621 default:
3622 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3623 bpc = min((unsigned int)8, display_bpc);
3624 break;
3625 }
3626
578393cd
KP		 3627 display_bpc = min(display_bpc, bpc);
3628
82820490
AJ		 3629 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3630 bpc, display_bpc);
5a354204 3631
578393cd 3632 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3633
3634 return display_bpc != bpc;
3635}
3636
c65d77d8
JB		 3637static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3638{
3639 struct drm_device *dev = crtc->dev;
3640 struct drm_i915_private *dev_priv = dev->dev_private;
3641 int refclk;
3642
3643 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3644 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3645 refclk = dev_priv->lvds_ssc_freq * 1000;
3646 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3647 refclk / 1000);
3648 } else if (!IS_GEN2(dev)) {
3649 refclk = 96000;
3650 } else {
3651 refclk = 48000;
3652 }
3653
3654 return refclk;
3655}
3656
3657static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3658 intel_clock_t *clock)
3659{
3660 /* SDVO TV has fixed PLL values depend on its clock range,
3661 this mirrors vbios setting. */
3662 if (adjusted_mode->clock >= 100000
3663 && adjusted_mode->clock < 140500) {
3664 clock->p1 = 2;
3665 clock->p2 = 10;
3666 clock->n = 3;
3667 clock->m1 = 16;
3668 clock->m2 = 8;
3669 } else if (adjusted_mode->clock >= 140500
3670 && adjusted_mode->clock <= 200000) {
3671 clock->p1 = 1;
3672 clock->p2 = 10;
3673 clock->n = 6;
3674 clock->m1 = 12;
3675 clock->m2 = 8;
3676 }
3677}
3678
a7516a05
JB		 3679static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3680 intel_clock_t *clock,
3681 intel_clock_t *reduced_clock)
3682{
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3686 int pipe = intel_crtc->pipe;
3687 u32 fp, fp2 = 0;
3688
3689 if (IS_PINEVIEW(dev)) {
3690 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3691 if (reduced_clock)
3692 fp2 = (1 << reduced_clock->n) << 16 |
3693 reduced_clock->m1 << 8 | reduced_clock->m2;
3694 } else {
3695 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3696 if (reduced_clock)
3697 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3698 reduced_clock->m2;
3699 }
3700
3701 I915_WRITE(FP0(pipe), fp);
3702
3703 intel_crtc->lowfreq_avail = false;
3704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3705 reduced_clock && i915_powersave) {
3706 I915_WRITE(FP1(pipe), fp2);
3707 intel_crtc->lowfreq_avail = true;
3708 } else {
3709 I915_WRITE(FP1(pipe), fp);
3710 }
3711}
3712
93e537a1
DV		 3713static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3714 struct drm_display_mode *adjusted_mode)
3715{
3716 struct drm_device *dev = crtc->dev;
3717 struct drm_i915_private *dev_priv = dev->dev_private;
3718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3719 int pipe = intel_crtc->pipe;
284d5df5 3720 u32 temp;
93e537a1
DV		 3721
3722 temp = I915_READ(LVDS);
3723 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3724 if (pipe == 1) {
3725 temp |= LVDS_PIPEB_SELECT;
3726 } else {
3727 temp &= ~LVDS_PIPEB_SELECT;
3728 }
3729 /* set the corresponsding LVDS_BORDER bit */
3730 temp |= dev_priv->lvds_border_bits;
3731 /* Set the B0-B3 data pairs corresponding to whether we're going to
3732 * set the DPLLs for dual-channel mode or not.
3733 */
3734 if (clock->p2 == 7)
3735 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3736 else
3737 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3738
3739 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3740 * appropriately here, but we need to look more thoroughly into how
3741 * panels behave in the two modes.
3742 */
3743 /* set the dithering flag on LVDS as needed */
3744 if (INTEL_INFO(dev)->gen >= 4) {
3745 if (dev_priv->lvds_dither)
3746 temp |= LVDS_ENABLE_DITHER;
3747 else
3748 temp &= ~LVDS_ENABLE_DITHER;
3749 }
284d5df5 3750 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3751 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3752 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3753 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3754 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3755 I915_WRITE(LVDS, temp);
3756}
3757
eb1cbe48
DV		 3758static void i9xx_update_pll(struct drm_crtc *crtc,
3759 struct drm_display_mode *mode,
3760 struct drm_display_mode *adjusted_mode,
3761 intel_clock_t *clock, intel_clock_t *reduced_clock,
3762 int num_connectors)
3763{
3764 struct drm_device *dev = crtc->dev;
3765 struct drm_i915_private *dev_priv = dev->dev_private;
3766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767 int pipe = intel_crtc->pipe;
3768 u32 dpll;
3769 bool is_sdvo;
3770
3771 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3772 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3773
3774 dpll = DPLL_VGA_MODE_DIS;
3775
3776 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3777 dpll |= DPLLB_MODE_LVDS;
3778 else
3779 dpll |= DPLLB_MODE_DAC_SERIAL;
3780 if (is_sdvo) {
3781 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3782 if (pixel_multiplier > 1) {
3783 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3784 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3785 }
3786 dpll |= DPLL_DVO_HIGH_SPEED;
3787 }
3788 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3789 dpll |= DPLL_DVO_HIGH_SPEED;
3790
3791 /* compute bitmask from p1 value */
3792 if (IS_PINEVIEW(dev))
3793 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3794 else {
3795 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3796 if (IS_G4X(dev) && reduced_clock)
3797 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3798 }
3799 switch (clock->p2) {
3800 case 5:
3801 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3802 break;
3803 case 7:
3804 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3805 break;
3806 case 10:
3807 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3808 break;
3809 case 14:
3810 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3811 break;
3812 }
3813 if (INTEL_INFO(dev)->gen >= 4)
3814 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3815
3816 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3817 dpll |= PLL_REF_INPUT_TVCLKINBC;
3818 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3819 /* XXX: just matching BIOS for now */
3820 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3821 dpll |= 3;
3822 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3823 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3824 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3825 else
3826 dpll |= PLL_REF_INPUT_DREFCLK;
3827
3828 dpll |= DPLL_VCO_ENABLE;
3829 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3830 POSTING_READ(DPLL(pipe));
3831 udelay(150);
3832
3833 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3834 * This is an exception to the general rule that mode_set doesn't turn
3835 * things on.
3836 */
3837 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3838 intel_update_lvds(crtc, clock, adjusted_mode);
3839
3840 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3841 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3842
3843 I915_WRITE(DPLL(pipe), dpll);
3844
3845 /* Wait for the clocks to stabilize. */
3846 POSTING_READ(DPLL(pipe));
3847 udelay(150);
3848
3849 if (INTEL_INFO(dev)->gen >= 4) {
3850 u32 temp = 0;
3851 if (is_sdvo) {
3852 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3853 if (temp > 1)
3854 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3855 else
3856 temp = 0;
3857 }
3858 I915_WRITE(DPLL_MD(pipe), temp);
3859 } else {
3860 /* The pixel multiplier can only be updated once the
3861 * DPLL is enabled and the clocks are stable.
3862 *
3863 * So write it again.
3864 */
3865 I915_WRITE(DPLL(pipe), dpll);
3866 }
3867}
3868
3869static void i8xx_update_pll(struct drm_crtc *crtc,
3870 struct drm_display_mode *adjusted_mode,
3871 intel_clock_t *clock,
3872 int num_connectors)
3873{
3874 struct drm_device *dev = crtc->dev;
3875 struct drm_i915_private *dev_priv = dev->dev_private;
3876 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3877 int pipe = intel_crtc->pipe;
3878 u32 dpll;
3879
3880 dpll = DPLL_VGA_MODE_DIS;
3881
3882 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3883 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3884 } else {
3885 if (clock->p1 == 2)
3886 dpll |= PLL_P1_DIVIDE_BY_TWO;
3887 else
3888 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3889 if (clock->p2 == 4)
3890 dpll |= PLL_P2_DIVIDE_BY_4;
3891 }
3892
3893 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3894 /* XXX: just matching BIOS for now */
3895 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3896 dpll |= 3;
3897 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3898 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3899 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3900 else
3901 dpll |= PLL_REF_INPUT_DREFCLK;
3902
3903 dpll |= DPLL_VCO_ENABLE;
3904 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3905 POSTING_READ(DPLL(pipe));
3906 udelay(150);
3907
3908 I915_WRITE(DPLL(pipe), dpll);
3909
3910 /* Wait for the clocks to stabilize. */
3911 POSTING_READ(DPLL(pipe));
3912 udelay(150);
3913
3914 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3915 * This is an exception to the general rule that mode_set doesn't turn
3916 * things on.
3917 */
3918 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3919 intel_update_lvds(crtc, clock, adjusted_mode);
3920
3921 /* The pixel multiplier can only be updated once the
3922 * DPLL is enabled and the clocks are stable.
3923 *
3924 * So write it again.
3925 */
3926 I915_WRITE(DPLL(pipe), dpll);
3927}
3928
f564048e
EA		 3929static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3930 struct drm_display_mode *mode,
3931 struct drm_display_mode *adjusted_mode,
3932 int x, int y,
3933 struct drm_framebuffer *old_fb)
79e53945
JB		 3934{
3935 struct drm_device *dev = crtc->dev;
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3938 int pipe = intel_crtc->pipe;
80824003 3939 int plane = intel_crtc->plane;
c751ce4f 3940 int refclk, num_connectors = 0;
652c393a 3941 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3942 u32 dspcntr, pipeconf, vsyncshift;
3943 bool ok, has_reduced_clock = false, is_sdvo = false;
3944 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3945 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3946 struct intel_encoder *encoder;
d4906093 3947 const intel_limit_t *limit;
5c3b82e2 3948 int ret;
79e53945 3949
5eddb70b
CW		 3950 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3951 if (encoder->base.crtc != crtc)
79e53945
JB		 3952 continue;
3953
5eddb70b 3954 switch (encoder->type) {
79e53945
JB		 3955 case INTEL_OUTPUT_LVDS:
3956 is_lvds = true;
3957 break;
3958 case INTEL_OUTPUT_SDVO:
7d57382e 3959 case INTEL_OUTPUT_HDMI:
79e53945 3960 is_sdvo = true;
5eddb70b 3961 if (encoder->needs_tv_clock)
e2f0ba97 3962 is_tv = true;
79e53945 3963 break;
79e53945
JB		 3964 case INTEL_OUTPUT_TVOUT:
3965 is_tv = true;
3966 break;
a4fc5ed6
KP		 3967 case INTEL_OUTPUT_DISPLAYPORT:
3968 is_dp = true;
3969 break;
79e53945 3970 }
43565a06 3971
c751ce4f 3972 num_connectors++;
79e53945
JB		 3973 }
3974
c65d77d8 3975 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 3976
d4906093
ML		 3977 /*
3978 * Returns a set of divisors for the desired target clock with the given
3979 * refclk, or FALSE. The returned values represent the clock equation:
3980 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3981 */
1b894b59 3982 limit = intel_limit(crtc, refclk);
cec2f356
SP		 3983 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3984 &clock);
79e53945
JB		 3985 if (!ok) {
3986 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 3987 return -EINVAL;
79e53945
JB		 3988 }
3989
cda4b7d3 3990 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 3991 intel_crtc_update_cursor(crtc, true);
cda4b7d3 3992
ddc9003c 3993 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 3994 /*
3995 * Ensure we match the reduced clock's P to the target clock.
3996 * If the clocks don't match, we can't switch the display clock
3997 * by using the FP0/FP1. In such case we will disable the LVDS
3998 * downclock feature.
3999 */
ddc9003c 4000 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4001 dev_priv->lvds_downclock,
4002 refclk,
cec2f356 4003 &clock,
5eddb70b 4004 &reduced_clock);
7026d4ac
ZW		 4005 }
4006
c65d77d8
JB		 4007 if (is_sdvo && is_tv)
4008 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4009
a7516a05
JB		 4010 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4011 &reduced_clock : NULL);
79e53945 4012
eb1cbe48
DV		 4013 if (IS_GEN2(dev))
4014 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 4015 else
eb1cbe48
DV		 4016 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4017 has_reduced_clock ? &reduced_clock : NULL,
4018 num_connectors);
79e53945
JB		 4019
4020 /* setup pipeconf */
5eddb70b 4021 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4022
4023 /* Set up the display plane register */
4024 dspcntr = DISPPLANE_GAMMA_ENABLE;
4025
929c77fb
EA		 4026 if (pipe == 0)
4027 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4028 else
4029 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4030
a6c45cf0 4031 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4032 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4033 * core speed.
4034 *
4035 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4036 * pipe == 0 check?
4037 */
e70236a8
JB		 4038 if (mode->clock >
4039 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4040 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4041 else
5eddb70b 4042 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4043 }
4044
3b5c78a3
AJ		 4045 /* default to 8bpc */
4046 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4047 if (is_dp) {
4048 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4049 pipeconf |= PIPECONF_BPP_6 |
4050 PIPECONF_DITHER_EN |
4051 PIPECONF_DITHER_TYPE_SP;
4052 }
4053 }
4054
28c97730 4055 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4056 drm_mode_debug_printmodeline(mode);
4057
a7516a05
JB		 4058 if (HAS_PIPE_CXSR(dev)) {
4059 if (intel_crtc->lowfreq_avail) {
28c97730 4060 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4061 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4062 } else {
28c97730 4063 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4064 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4065 }
4066 }
4067
617cf884 4068 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4069 if (!IS_GEN2(dev) &&
4070 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4071 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4072 /* the chip adds 2 halflines automatically */
734b4157 4073 adjusted_mode->crtc_vtotal -= 1;
734b4157 4074 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4075 vsyncshift = adjusted_mode->crtc_hsync_start
4076 - adjusted_mode->crtc_htotal/2;
4077 } else {
617cf884 4078 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4079 vsyncshift = 0;
4080 }
4081
4082 if (!IS_GEN3(dev))
4083 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4084
5eddb70b
CW		 4085 I915_WRITE(HTOTAL(pipe),
4086 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4087 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4088 I915_WRITE(HBLANK(pipe),
4089 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4090 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4091 I915_WRITE(HSYNC(pipe),
4092 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4093 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4094
4095 I915_WRITE(VTOTAL(pipe),
4096 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4097 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4098 I915_WRITE(VBLANK(pipe),
4099 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4100 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4101 I915_WRITE(VSYNC(pipe),
4102 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4103 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4104
4105 /* pipesrc and dspsize control the size that is scaled from,
4106 * which should always be the user's requested size.
79e53945 4107 */
929c77fb
EA		 4108 I915_WRITE(DSPSIZE(plane),
4109 ((mode->vdisplay - 1) << 16) |
4110 (mode->hdisplay - 1));
4111 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4112 I915_WRITE(PIPESRC(pipe),
4113 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4114
f564048e
EA		 4115 I915_WRITE(PIPECONF(pipe), pipeconf);
4116 POSTING_READ(PIPECONF(pipe));
929c77fb 4117 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4118
4119 intel_wait_for_vblank(dev, pipe);
4120
f564048e
EA		 4121 I915_WRITE(DSPCNTR(plane), dspcntr);
4122 POSTING_READ(DSPCNTR(plane));
4123
4124 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4125
4126 intel_update_watermarks(dev);
4127
f564048e
EA		 4128 return ret;
4129}
4130
9fb526db
KP		 4131/*
4132 * Initialize reference clocks when the driver loads
4133 */
4134void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4135{
4136 struct drm_i915_private *dev_priv = dev->dev_private;
4137 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4138 struct intel_encoder *encoder;
13d83a67
JB		 4139 u32 temp;
4140 bool has_lvds = false;
199e5d79
KP		 4141 bool has_cpu_edp = false;
4142 bool has_pch_edp = false;
4143 bool has_panel = false;
99eb6a01
KP		 4144 bool has_ck505 = false;
4145 bool can_ssc = false;
13d83a67
JB		 4146
4147 /* We need to take the global config into account */
199e5d79
KP		 4148 list_for_each_entry(encoder, &mode_config->encoder_list,
4149 base.head) {
4150 switch (encoder->type) {
4151 case INTEL_OUTPUT_LVDS:
4152 has_panel = true;
4153 has_lvds = true;
4154 break;
4155 case INTEL_OUTPUT_EDP:
4156 has_panel = true;
4157 if (intel_encoder_is_pch_edp(&encoder->base))
4158 has_pch_edp = true;
4159 else
4160 has_cpu_edp = true;
4161 break;
13d83a67
JB		 4162 }
4163 }
4164
99eb6a01
KP		 4165 if (HAS_PCH_IBX(dev)) {
4166 has_ck505 = dev_priv->display_clock_mode;
4167 can_ssc = has_ck505;
4168 } else {
4169 has_ck505 = false;
4170 can_ssc = true;
4171 }
4172
4173 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4174 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4175 has_ck505);
13d83a67
JB		 4176
4177 /* Ironlake: try to setup display ref clock before DPLL
4178 * enabling. This is only under driver's control after
4179 * PCH B stepping, previous chipset stepping should be
4180 * ignoring this setting.
4181 */
4182 temp = I915_READ(PCH_DREF_CONTROL);
4183 /* Always enable nonspread source */
4184 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4185
99eb6a01
KP		 4186 if (has_ck505)
4187 temp |= DREF_NONSPREAD_CK505_ENABLE;
4188 else
4189 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4190
199e5d79
KP		 4191 if (has_panel) {
4192 temp &= ~DREF_SSC_SOURCE_MASK;
4193 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4194
199e5d79 4195 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4196 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4197 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4198 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4199 } else
4200 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4201
4202 /* Get SSC going before enabling the outputs */
4203 I915_WRITE(PCH_DREF_CONTROL, temp);
4204 POSTING_READ(PCH_DREF_CONTROL);
4205 udelay(200);
4206
13d83a67
JB		 4207 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4208
4209 /* Enable CPU source on CPU attached eDP */
199e5d79 4210 if (has_cpu_edp) {
99eb6a01 4211 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4212 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4213 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4214 }
13d83a67
JB		 4215 else
4216 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4217 } else
4218 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4219
4220 I915_WRITE(PCH_DREF_CONTROL, temp);
4221 POSTING_READ(PCH_DREF_CONTROL);
4222 udelay(200);
4223 } else {
4224 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4225
4226 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4227
4228 /* Turn off CPU output */
4229 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4230
4231 I915_WRITE(PCH_DREF_CONTROL, temp);
4232 POSTING_READ(PCH_DREF_CONTROL);
4233 udelay(200);
4234
4235 /* Turn off the SSC source */
4236 temp &= ~DREF_SSC_SOURCE_MASK;
4237 temp |= DREF_SSC_SOURCE_DISABLE;
4238
4239 /* Turn off SSC1 */
4240 temp &= ~ DREF_SSC1_ENABLE;
4241
13d83a67
JB		 4242 I915_WRITE(PCH_DREF_CONTROL, temp);
4243 POSTING_READ(PCH_DREF_CONTROL);
4244 udelay(200);
4245 }
4246}
4247
d9d444cb
JB		 4248static int ironlake_get_refclk(struct drm_crtc *crtc)
4249{
4250 struct drm_device *dev = crtc->dev;
4251 struct drm_i915_private *dev_priv = dev->dev_private;
4252 struct intel_encoder *encoder;
4253 struct drm_mode_config *mode_config = &dev->mode_config;
4254 struct intel_encoder *edp_encoder = NULL;
4255 int num_connectors = 0;
4256 bool is_lvds = false;
4257
4258 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4259 if (encoder->base.crtc != crtc)
4260 continue;
4261
4262 switch (encoder->type) {
4263 case INTEL_OUTPUT_LVDS:
4264 is_lvds = true;
4265 break;
4266 case INTEL_OUTPUT_EDP:
4267 edp_encoder = encoder;
4268 break;
4269 }
4270 num_connectors++;
4271 }
4272
4273 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4274 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4275 dev_priv->lvds_ssc_freq);
4276 return dev_priv->lvds_ssc_freq * 1000;
4277 }
4278
4279 return 120000;
4280}
4281
f564048e
EA		 4282static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4283 struct drm_display_mode *mode,
4284 struct drm_display_mode *adjusted_mode,
4285 int x, int y,
4286 struct drm_framebuffer *old_fb)
79e53945
JB		 4287{
4288 struct drm_device *dev = crtc->dev;
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4291 int pipe = intel_crtc->pipe;
80824003 4292 int plane = intel_crtc->plane;
c751ce4f 4293 int refclk, num_connectors = 0;
652c393a 4294 intel_clock_t clock, reduced_clock;
5eddb70b 4295 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4296 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4297 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4298 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4299 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4300 const intel_limit_t *limit;
5c3b82e2 4301 int ret;
2c07245f 4302 struct fdi_m_n m_n = {0};
fae14981 4303 u32 temp;
5a354204
JB		 4304 int target_clock, pixel_multiplier, lane, link_bw, factor;
4305 unsigned int pipe_bpp;
4306 bool dither;
e3aef172 4307 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4308
5eddb70b
CW		 4309 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4310 if (encoder->base.crtc != crtc)
79e53945
JB		 4311 continue;
4312
5eddb70b 4313 switch (encoder->type) {
79e53945
JB		 4314 case INTEL_OUTPUT_LVDS:
4315 is_lvds = true;
4316 break;
4317 case INTEL_OUTPUT_SDVO:
7d57382e 4318 case INTEL_OUTPUT_HDMI:
79e53945 4319 is_sdvo = true;
5eddb70b 4320 if (encoder->needs_tv_clock)
e2f0ba97 4321 is_tv = true;
79e53945 4322 break;
79e53945
JB		 4323 case INTEL_OUTPUT_TVOUT:
4324 is_tv = true;
4325 break;
4326 case INTEL_OUTPUT_ANALOG:
4327 is_crt = true;
4328 break;
a4fc5ed6
KP		 4329 case INTEL_OUTPUT_DISPLAYPORT:
4330 is_dp = true;
4331 break;
32f9d658 4332 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4333 is_dp = true;
4334 if (intel_encoder_is_pch_edp(&encoder->base))
4335 is_pch_edp = true;
4336 else
4337 is_cpu_edp = true;
4338 edp_encoder = encoder;
32f9d658 4339 break;
79e53945 4340 }
43565a06 4341
c751ce4f 4342 num_connectors++;
79e53945
JB		 4343 }
4344
d9d444cb 4345 refclk = ironlake_get_refclk(crtc);
79e53945 4346
d4906093
ML		 4347 /*
4348 * Returns a set of divisors for the desired target clock with the given
4349 * refclk, or FALSE. The returned values represent the clock equation:
4350 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4351 */
1b894b59 4352 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4353 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4354 &clock);
79e53945
JB		 4355 if (!ok) {
4356 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4357 return -EINVAL;
79e53945
JB		 4358 }
4359
cda4b7d3 4360 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4361 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4362
ddc9003c 4363 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4364 /*
4365 * Ensure we match the reduced clock's P to the target clock.
4366 * If the clocks don't match, we can't switch the display clock
4367 * by using the FP0/FP1. In such case we will disable the LVDS
4368 * downclock feature.
4369 */
ddc9003c 4370 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4371 dev_priv->lvds_downclock,
4372 refclk,
cec2f356 4373 &clock,
5eddb70b 4374 &reduced_clock);
652c393a 4375 }
7026d4ac
ZW		 4376 /* SDVO TV has fixed PLL values depend on its clock range,
4377 this mirrors vbios setting. */
4378 if (is_sdvo && is_tv) {
4379 if (adjusted_mode->clock >= 100000
5eddb70b 4380 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4381 clock.p1 = 2;
4382 clock.p2 = 10;
4383 clock.n = 3;
4384 clock.m1 = 16;
4385 clock.m2 = 8;
4386 } else if (adjusted_mode->clock >= 140500
5eddb70b 4387 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4388 clock.p1 = 1;
4389 clock.p2 = 10;
4390 clock.n = 6;
4391 clock.m1 = 12;
4392 clock.m2 = 8;
4393 }
4394 }
4395
2c07245f 4396 /* FDI link */
8febb297
EA		 4397 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4398 lane = 0;
4399 /* CPU eDP doesn't require FDI link, so just set DP M/N
4400 according to current link config */
e3aef172 4401 if (is_cpu_edp) {
8febb297 4402 target_clock = mode->clock;
e3aef172 4403 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 4404 } else {
4405 /* [e]DP over FDI requires target mode clock
4406 instead of link clock */
e3aef172 4407 if (is_dp)
5eb08b69 4408 target_clock = mode->clock;
8febb297
EA		 4409 else
4410 target_clock = adjusted_mode->clock;
4411
4412 /* FDI is a binary signal running at ~2.7GHz, encoding
4413 * each output octet as 10 bits. The actual frequency
4414 * is stored as a divider into a 100MHz clock, and the
4415 * mode pixel clock is stored in units of 1KHz.
4416 * Hence the bw of each lane in terms of the mode signal
4417 * is:
4418 */
4419 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4420 }
58a27471 4421
8febb297
EA		 4422 /* determine panel color depth */
4423 temp = I915_READ(PIPECONF(pipe));
4424 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4425 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4426 switch (pipe_bpp) {
4427 case 18:
4428 temp |= PIPE_6BPC;
8febb297 4429 break;
5a354204
JB		 4430 case 24:
4431 temp |= PIPE_8BPC;
8febb297 4432 break;
5a354204
JB		 4433 case 30:
4434 temp |= PIPE_10BPC;
8febb297 4435 break;
5a354204
JB		 4436 case 36:
4437 temp |= PIPE_12BPC;
8febb297
EA		 4438 break;
4439 default:
62ac41a6
JB		 4440 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4441 pipe_bpp);
5a354204
JB		 4442 temp |= PIPE_8BPC;
4443 pipe_bpp = 24;
4444 break;
8febb297 4445 }
77ffb597 4446
5a354204
JB		 4447 intel_crtc->bpp = pipe_bpp;
4448 I915_WRITE(PIPECONF(pipe), temp);
4449
8febb297
EA		 4450 if (!lane) {
4451 /*
4452 * Account for spread spectrum to avoid
4453 * oversubscribing the link. Max center spread
4454 * is 2.5%; use 5% for safety's sake.
4455 */
5a354204 4456 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4457 lane = bps / (link_bw * 8) + 1;
5eb08b69 4458 }
2c07245f 4459
8febb297
EA		 4460 intel_crtc->fdi_lanes = lane;
4461
4462 if (pixel_multiplier > 1)
4463 link_bw *= pixel_multiplier;
5a354204
JB		 4464 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4465 &m_n);
8febb297 4466
a07d6787
EA		 4467 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4468 if (has_reduced_clock)
4469 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4470 reduced_clock.m2;
79e53945 4471
c1858123 4472 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4473 factor = 21;
4474 if (is_lvds) {
4475 if ((intel_panel_use_ssc(dev_priv) &&
4476 dev_priv->lvds_ssc_freq == 100) ||
4477 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4478 factor = 25;
4479 } else if (is_sdvo && is_tv)
4480 factor = 20;
c1858123 4481
cb0e0931 4482 if (clock.m < factor * clock.n)
8febb297 4483 fp |= FP_CB_TUNE;
2c07245f 4484
5eddb70b 4485 dpll = 0;
2c07245f 4486
a07d6787
EA		 4487 if (is_lvds)
4488 dpll |= DPLLB_MODE_LVDS;
4489 else
4490 dpll |= DPLLB_MODE_DAC_SERIAL;
4491 if (is_sdvo) {
4492 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4493 if (pixel_multiplier > 1) {
4494 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4495 }
a07d6787
EA		 4496 dpll |= DPLL_DVO_HIGH_SPEED;
4497 }
e3aef172 4498 if (is_dp && !is_cpu_edp)
a07d6787 4499 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4500
a07d6787
EA		 4501 /* compute bitmask from p1 value */
4502 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4503 /* also FPA1 */
4504 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4505
4506 switch (clock.p2) {
4507 case 5:
4508 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4509 break;
4510 case 7:
4511 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4512 break;
4513 case 10:
4514 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4515 break;
4516 case 14:
4517 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4518 break;
79e53945
JB		 4519 }
4520
43565a06
KH		 4521 if (is_sdvo && is_tv)
4522 dpll |= PLL_REF_INPUT_TVCLKINBC;
4523 else if (is_tv)
79e53945 4524 /* XXX: just matching BIOS for now */
43565a06 4525 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4526 dpll |= 3;
a7615030 4527 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4528 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4529 else
4530 dpll |= PLL_REF_INPUT_DREFCLK;
4531
4532 /* setup pipeconf */
5eddb70b 4533 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4534
4535 /* Set up the display plane register */
4536 dspcntr = DISPPLANE_GAMMA_ENABLE;
4537
f7cb34d4 4538 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4539 drm_mode_debug_printmodeline(mode);
4540
9d82aa17
ED		 4541 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4542 * pre-Haswell/LPT generation */
4543 if (HAS_PCH_LPT(dev)) {
4544 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4545 pipe);
4546 } else if (!is_cpu_edp) {
ee7b9f93 4547 struct intel_pch_pll *pll;
4b645f14 4548
ee7b9f93
JB		 4549 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4550 if (pll == NULL) {
4551 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4552 pipe);
4b645f14
JB		 4553 return -EINVAL;
4554 }
ee7b9f93
JB		 4555 } else
4556 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4557
4558 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4559 * This is an exception to the general rule that mode_set doesn't turn
4560 * things on.
4561 */
4562 if (is_lvds) {
fae14981 4563 temp = I915_READ(PCH_LVDS);
5eddb70b 4564 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4565 if (HAS_PCH_CPT(dev)) {
4566 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4567 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4568 } else {
4569 if (pipe == 1)
4570 temp |= LVDS_PIPEB_SELECT;
4571 else
4572 temp &= ~LVDS_PIPEB_SELECT;
4573 }
4b645f14 4574
a3e17eb8 4575 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4576 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4577 /* Set the B0-B3 data pairs corresponding to whether we're going to
4578 * set the DPLLs for dual-channel mode or not.
4579 */
4580 if (clock.p2 == 7)
5eddb70b 4581 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4582 else
5eddb70b 4583 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4584
4585 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4586 * appropriately here, but we need to look more thoroughly into how
4587 * panels behave in the two modes.
4588 */
284d5df5 4589 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4590 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4591 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4592 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4593 temp |= LVDS_VSYNC_POLARITY;
fae14981 4594 I915_WRITE(PCH_LVDS, temp);
79e53945 4595 }
434ed097 4596
8febb297
EA		 4597 pipeconf &= ~PIPECONF_DITHER_EN;
4598 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4599 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4600 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4601 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4602 }
e3aef172 4603 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4604 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4605 } else {
8db9d77b 4606 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4607 I915_WRITE(TRANSDATA_M1(pipe), 0);
4608 I915_WRITE(TRANSDATA_N1(pipe), 0);
4609 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4610 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4611 }
79e53945 4612
ee7b9f93
JB		 4613 if (intel_crtc->pch_pll) {
4614 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4615
32f9d658 4616 /* Wait for the clocks to stabilize. */
ee7b9f93 4617 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4618 udelay(150);
4619
8febb297
EA		 4620 /* The pixel multiplier can only be updated once the
4621 * DPLL is enabled and the clocks are stable.
4622 *
4623 * So write it again.
4624 */
ee7b9f93 4625 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4626 }
79e53945 4627
5eddb70b 4628 intel_crtc->lowfreq_avail = false;
ee7b9f93 4629 if (intel_crtc->pch_pll) {
4b645f14 4630 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4631 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14
JB		 4632 intel_crtc->lowfreq_avail = true;
4633 if (HAS_PIPE_CXSR(dev)) {
4634 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4635 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4636 }
4637 } else {
ee7b9f93 4638 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4b645f14
JB		 4639 if (HAS_PIPE_CXSR(dev)) {
4640 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4641 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4642 }
652c393a
JB		 4643 }
4644 }
4645
617cf884 4646 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4647 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4648 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4649 /* the chip adds 2 halflines automatically */
734b4157 4650 adjusted_mode->crtc_vtotal -= 1;
734b4157 4651 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4652 I915_WRITE(VSYNCSHIFT(pipe),
4653 adjusted_mode->crtc_hsync_start
4654 - adjusted_mode->crtc_htotal/2);
4655 } else {
617cf884 4656 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4657 I915_WRITE(VSYNCSHIFT(pipe), 0);
4658 }
734b4157 4659
5eddb70b
CW		 4660 I915_WRITE(HTOTAL(pipe),
4661 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4662 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4663 I915_WRITE(HBLANK(pipe),
4664 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4665 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4666 I915_WRITE(HSYNC(pipe),
4667 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4668 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4669
4670 I915_WRITE(VTOTAL(pipe),
4671 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4672 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4673 I915_WRITE(VBLANK(pipe),
4674 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4675 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4676 I915_WRITE(VSYNC(pipe),
4677 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4678 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4679
8febb297
EA		 4680 /* pipesrc controls the size that is scaled from, which should
4681 * always be the user's requested size.
79e53945 4682 */
5eddb70b
CW		 4683 I915_WRITE(PIPESRC(pipe),
4684 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4685
8febb297
EA		 4686 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4687 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4688 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4689 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4690
e3aef172 4691 if (is_cpu_edp)
8febb297 4692 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4693
5eddb70b
CW		 4694 I915_WRITE(PIPECONF(pipe), pipeconf);
4695 POSTING_READ(PIPECONF(pipe));
79e53945 4696
9d0498a2 4697 intel_wait_for_vblank(dev, pipe);
79e53945 4698
5eddb70b 4699 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4700 POSTING_READ(DSPCNTR(plane));
79e53945 4701
5c3b82e2 4702 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4703
4704 intel_update_watermarks(dev);
4705
1f8eeabf
ED		 4706 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4707
1f803ee5 4708 return ret;
79e53945
JB		 4709}
4710
f564048e
EA		 4711static int intel_crtc_mode_set(struct drm_crtc *crtc,
4712 struct drm_display_mode *mode,
4713 struct drm_display_mode *adjusted_mode,
4714 int x, int y,
4715 struct drm_framebuffer *old_fb)
4716{
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 int pipe = intel_crtc->pipe;
f564048e
EA		 4721 int ret;
4722
0b701d27 4723 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4724
f564048e
EA		 4725 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4726 x, y, old_fb);
79e53945 4727 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4728
d8e70a25
JB		 4729 if (ret)
4730 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4731 else
4732 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4733
1f803ee5 4734 return ret;
79e53945
JB		 4735}
4736
3a9627f4
WF		 4737static bool intel_eld_uptodate(struct drm_connector *connector,
4738 int reg_eldv, uint32_t bits_eldv,
4739 int reg_elda, uint32_t bits_elda,
4740 int reg_edid)
4741{
4742 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4743 uint8_t *eld = connector->eld;
4744 uint32_t i;
4745
4746 i = I915_READ(reg_eldv);
4747 i &= bits_eldv;
4748
4749 if (!eld[0])
4750 return !i;
4751
4752 if (!i)
4753 return false;
4754
4755 i = I915_READ(reg_elda);
4756 i &= ~bits_elda;
4757 I915_WRITE(reg_elda, i);
4758
4759 for (i = 0; i < eld[2]; i++)
4760 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4761 return false;
4762
4763 return true;
4764}
4765
e0dac65e
WF		 4766static void g4x_write_eld(struct drm_connector *connector,
4767 struct drm_crtc *crtc)
4768{
4769 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4770 uint8_t *eld = connector->eld;
4771 uint32_t eldv;
4772 uint32_t len;
4773 uint32_t i;
4774
4775 i = I915_READ(G4X_AUD_VID_DID);
4776
4777 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4778 eldv = G4X_ELDV_DEVCL_DEVBLC;
4779 else
4780 eldv = G4X_ELDV_DEVCTG;
4781
3a9627f4
WF		 4782 if (intel_eld_uptodate(connector,
4783 G4X_AUD_CNTL_ST, eldv,
4784 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4785 G4X_HDMIW_HDMIEDID))
4786 return;
4787
e0dac65e
WF		 4788 i = I915_READ(G4X_AUD_CNTL_ST);
4789 i &= ~(eldv | G4X_ELD_ADDR);
4790 len = (i >> 9) & 0x1f; /* ELD buffer size */
4791 I915_WRITE(G4X_AUD_CNTL_ST, i);
4792
4793 if (!eld[0])
4794 return;
4795
4796 len = min_t(uint8_t, eld[2], len);
4797 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4798 for (i = 0; i < len; i++)
4799 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4800
4801 i = I915_READ(G4X_AUD_CNTL_ST);
4802 i |= eldv;
4803 I915_WRITE(G4X_AUD_CNTL_ST, i);
4804}
4805
4806static void ironlake_write_eld(struct drm_connector *connector,
4807 struct drm_crtc *crtc)
4808{
4809 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4810 uint8_t *eld = connector->eld;
4811 uint32_t eldv;
4812 uint32_t i;
4813 int len;
4814 int hdmiw_hdmiedid;
b6daa025 4815 int aud_config;
e0dac65e
WF		 4816 int aud_cntl_st;
4817 int aud_cntrl_st2;
4818
b3f33cbf 4819 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4820 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4821 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4822 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4823 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4824 } else {
1202b4c6 4825 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4826 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4827 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4828 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4829 }
4830
4831 i = to_intel_crtc(crtc)->pipe;
4832 hdmiw_hdmiedid += i * 0x100;
4833 aud_cntl_st += i * 0x100;
b6daa025 4834 aud_config += i * 0x100;
e0dac65e
WF		 4835
4836 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4837
4838 i = I915_READ(aud_cntl_st);
4839 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4840 if (!i) {
4841 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4842 /* operate blindly on all ports */
1202b4c6
WF		 4843 eldv = IBX_ELD_VALIDB;
4844 eldv |= IBX_ELD_VALIDB << 4;
4845 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4846 } else {
4847 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4848 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4849 }
4850
3a9627f4
WF		 4851 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4852 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4853 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4854 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4855 } else
4856 I915_WRITE(aud_config, 0);
e0dac65e 4857
3a9627f4
WF		 4858 if (intel_eld_uptodate(connector,
4859 aud_cntrl_st2, eldv,
4860 aud_cntl_st, IBX_ELD_ADDRESS,
4861 hdmiw_hdmiedid))
4862 return;
4863
e0dac65e
WF		 4864 i = I915_READ(aud_cntrl_st2);
4865 i &= ~eldv;
4866 I915_WRITE(aud_cntrl_st2, i);
4867
4868 if (!eld[0])
4869 return;
4870
e0dac65e 4871 i = I915_READ(aud_cntl_st);
1202b4c6 4872 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4873 I915_WRITE(aud_cntl_st, i);
4874
4875 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4876 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4877 for (i = 0; i < len; i++)
4878 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4879
4880 i = I915_READ(aud_cntrl_st2);
4881 i |= eldv;
4882 I915_WRITE(aud_cntrl_st2, i);
4883}
4884
4885void intel_write_eld(struct drm_encoder *encoder,
4886 struct drm_display_mode *mode)
4887{
4888 struct drm_crtc *crtc = encoder->crtc;
4889 struct drm_connector *connector;
4890 struct drm_device *dev = encoder->dev;
4891 struct drm_i915_private *dev_priv = dev->dev_private;
4892
4893 connector = drm_select_eld(encoder, mode);
4894 if (!connector)
4895 return;
4896
4897 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4898 connector->base.id,
4899 drm_get_connector_name(connector),
4900 connector->encoder->base.id,
4901 drm_get_encoder_name(connector->encoder));
4902
4903 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4904
4905 if (dev_priv->display.write_eld)
4906 dev_priv->display.write_eld(connector, crtc);
4907}
4908
79e53945
JB		 4909/** Loads the palette/gamma unit for the CRTC with the prepared values */
4910void intel_crtc_load_lut(struct drm_crtc *crtc)
4911{
4912 struct drm_device *dev = crtc->dev;
4913 struct drm_i915_private *dev_priv = dev->dev_private;
4914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4915 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4916 int i;
4917
4918 /* The clocks have to be on to load the palette. */
aed3f09d 4919 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4920 return;
4921
f2b115e6 4922 /* use legacy palette for Ironlake */
bad720ff 4923 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4924 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4925
79e53945
JB		 4926 for (i = 0; i < 256; i++) {
4927 I915_WRITE(palreg + 4 * i,
4928 (intel_crtc->lut_r[i] << 16) |
4929 (intel_crtc->lut_g[i] << 8) |
4930 intel_crtc->lut_b[i]);
4931 }
4932}
4933
560b85bb
CW		 4934static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4935{
4936 struct drm_device *dev = crtc->dev;
4937 struct drm_i915_private *dev_priv = dev->dev_private;
4938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4939 bool visible = base != 0;
4940 u32 cntl;
4941
4942 if (intel_crtc->cursor_visible == visible)
4943 return;
4944
9db4a9c7 4945 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4946 if (visible) {
4947 /* On these chipsets we can only modify the base whilst
4948 * the cursor is disabled.
4949 */
9db4a9c7 4950 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4951
4952 cntl &= ~(CURSOR_FORMAT_MASK);
4953 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4954 cntl |= CURSOR_ENABLE |
4955 CURSOR_GAMMA_ENABLE |
4956 CURSOR_FORMAT_ARGB;
4957 } else
4958 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4959 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4960
4961 intel_crtc->cursor_visible = visible;
4962}
4963
4964static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4965{
4966 struct drm_device *dev = crtc->dev;
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4969 int pipe = intel_crtc->pipe;
4970 bool visible = base != 0;
4971
4972 if (intel_crtc->cursor_visible != visible) {
548f245b 4973 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4974 if (base) {
4975 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4976 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4977 cntl |= pipe << 28; /* Connect to correct pipe */
4978 } else {
4979 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4980 cntl |= CURSOR_MODE_DISABLE;
4981 }
9db4a9c7 4982 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4983
4984 intel_crtc->cursor_visible = visible;
4985 }
4986 /* and commit changes on next vblank */
9db4a9c7 4987 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 4988}
4989
65a21cd6
JB		 4990static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4991{
4992 struct drm_device *dev = crtc->dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4995 int pipe = intel_crtc->pipe;
4996 bool visible = base != 0;
4997
4998 if (intel_crtc->cursor_visible != visible) {
4999 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5000 if (base) {
5001 cntl &= ~CURSOR_MODE;
5002 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5003 } else {
5004 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5005 cntl |= CURSOR_MODE_DISABLE;
5006 }
5007 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5008
5009 intel_crtc->cursor_visible = visible;
5010 }
5011 /* and commit changes on next vblank */
5012 I915_WRITE(CURBASE_IVB(pipe), base);
5013}
5014
cda4b7d3 5015/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5016static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5017 bool on)
cda4b7d3
CW		 5018{
5019 struct drm_device *dev = crtc->dev;
5020 struct drm_i915_private *dev_priv = dev->dev_private;
5021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5022 int pipe = intel_crtc->pipe;
5023 int x = intel_crtc->cursor_x;
5024 int y = intel_crtc->cursor_y;
560b85bb 5025 u32 base, pos;
cda4b7d3
CW		 5026 bool visible;
5027
5028 pos = 0;
5029
6b383a7f 5030 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5031 base = intel_crtc->cursor_addr;
5032 if (x > (int) crtc->fb->width)
5033 base = 0;
5034
5035 if (y > (int) crtc->fb->height)
5036 base = 0;
5037 } else
5038 base = 0;
5039
5040 if (x < 0) {
5041 if (x + intel_crtc->cursor_width < 0)
5042 base = 0;
5043
5044 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5045 x = -x;
5046 }
5047 pos |= x << CURSOR_X_SHIFT;
5048
5049 if (y < 0) {
5050 if (y + intel_crtc->cursor_height < 0)
5051 base = 0;
5052
5053 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5054 y = -y;
5055 }
5056 pos |= y << CURSOR_Y_SHIFT;
5057
5058 visible = base != 0;
560b85bb 5059 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5060 return;
5061
0cd83aa9 5062 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5063 I915_WRITE(CURPOS_IVB(pipe), pos);
5064 ivb_update_cursor(crtc, base);
5065 } else {
5066 I915_WRITE(CURPOS(pipe), pos);
5067 if (IS_845G(dev) || IS_I865G(dev))
5068 i845_update_cursor(crtc, base);
5069 else
5070 i9xx_update_cursor(crtc, base);
5071 }
cda4b7d3
CW		 5072}
5073
79e53945 5074static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5075 struct drm_file *file,
79e53945
JB		 5076 uint32_t handle,
5077 uint32_t width, uint32_t height)
5078{
5079 struct drm_device *dev = crtc->dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5082 struct drm_i915_gem_object *obj;
cda4b7d3 5083 uint32_t addr;
3f8bc370 5084 int ret;
79e53945 5085
28c97730 5086 DRM_DEBUG_KMS("\n");
79e53945
JB		 5087
5088 /* if we want to turn off the cursor ignore width and height */
5089 if (!handle) {
28c97730 5090 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5091 addr = 0;
05394f39 5092 obj = NULL;
5004417d 5093 mutex_lock(&dev->struct_mutex);
3f8bc370 5094 goto finish;
79e53945
JB		 5095 }
5096
5097 /* Currently we only support 64x64 cursors */
5098 if (width != 64 || height != 64) {
5099 DRM_ERROR("we currently only support 64x64 cursors\n");
5100 return -EINVAL;
5101 }
5102
05394f39 5103 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5104 if (&obj->base == NULL)
79e53945
JB		 5105 return -ENOENT;
5106
05394f39 5107 if (obj->base.size < width * height * 4) {
79e53945 5108 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5109 ret = -ENOMEM;
5110 goto fail;
79e53945
JB		 5111 }
5112
71acb5eb 5113 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5114 mutex_lock(&dev->struct_mutex);
b295d1b6 5115 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5116 if (obj->tiling_mode) {
5117 DRM_ERROR("cursor cannot be tiled\n");
5118 ret = -EINVAL;
5119 goto fail_locked;
5120 }
5121
2da3b9b9 5122 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5123 if (ret) {
5124 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5125 goto fail_locked;
e7b526bb
CW		 5126 }
5127
d9e86c0e
CW		 5128 ret = i915_gem_object_put_fence(obj);
5129 if (ret) {
2da3b9b9 5130 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5131 goto fail_unpin;
5132 }
5133
05394f39 5134 addr = obj->gtt_offset;
71acb5eb 5135 } else {
6eeefaf3 5136 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5137 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5138 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5139 align);
71acb5eb
DA		 5140 if (ret) {
5141 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5142 goto fail_locked;
71acb5eb 5143 }
05394f39 5144 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5145 }
5146
a6c45cf0 5147 if (IS_GEN2(dev))
14b60391
JB		 5148 I915_WRITE(CURSIZE, (height << 12) | width);
5149
3f8bc370 5150 finish:
3f8bc370 5151 if (intel_crtc->cursor_bo) {
b295d1b6 5152 if (dev_priv->info->cursor_needs_physical) {
05394f39 5153 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5154 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5155 } else
5156 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5157 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5158 }
80824003 5159
7f9872e0 5160 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5161
5162 intel_crtc->cursor_addr = addr;
05394f39 5163 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5164 intel_crtc->cursor_width = width;
5165 intel_crtc->cursor_height = height;
5166
6b383a7f 5167 intel_crtc_update_cursor(crtc, true);
3f8bc370 5168
79e53945 5169 return 0;
e7b526bb 5170fail_unpin:
05394f39 5171 i915_gem_object_unpin(obj);
7f9872e0 5172fail_locked:
34b8686e 5173 mutex_unlock(&dev->struct_mutex);
bc9025bd 5174fail:
05394f39 5175 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5176 return ret;
79e53945
JB		 5177}
5178
5179static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5180{
79e53945 5181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5182
cda4b7d3
CW		 5183 intel_crtc->cursor_x = x;
5184 intel_crtc->cursor_y = y;
652c393a 5185
6b383a7f 5186 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5187
5188 return 0;
5189}
5190
5191/** Sets the color ramps on behalf of RandR */
5192void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5193 u16 blue, int regno)
5194{
5195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5196
5197 intel_crtc->lut_r[regno] = red >> 8;
5198 intel_crtc->lut_g[regno] = green >> 8;
5199 intel_crtc->lut_b[regno] = blue >> 8;
5200}
5201
b8c00ac5
DA		 5202void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5203 u16 *blue, int regno)
5204{
5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5206
5207 *red = intel_crtc->lut_r[regno] << 8;
5208 *green = intel_crtc->lut_g[regno] << 8;
5209 *blue = intel_crtc->lut_b[regno] << 8;
5210}
5211
79e53945 5212static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5213 u16 *blue, uint32_t start, uint32_t size)
79e53945 5214{
7203425a 5215 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5217
7203425a 5218 for (i = start; i < end; i++) {
79e53945
JB		 5219 intel_crtc->lut_r[i] = red[i] >> 8;
5220 intel_crtc->lut_g[i] = green[i] >> 8;
5221 intel_crtc->lut_b[i] = blue[i] >> 8;
5222 }
5223
5224 intel_crtc_load_lut(crtc);
5225}
5226
5227/**
5228 * Get a pipe with a simple mode set on it for doing load-based monitor
5229 * detection.
5230 *
5231 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5232 * its requirements. The pipe will be connected to no other encoders.
79e53945 5233 *
c751ce4f 5234 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5235 * configured for it. In the future, it could choose to temporarily disable
5236 * some outputs to free up a pipe for its use.
5237 *
5238 * \return crtc, or NULL if no pipes are available.
5239 */
5240
5241/* VESA 640x480x72Hz mode to set on the pipe */
5242static struct drm_display_mode load_detect_mode = {
5243 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5244 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5245};
5246
d2dff872
CW		 5247static struct drm_framebuffer *
5248intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5249 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5250 struct drm_i915_gem_object *obj)
5251{
5252 struct intel_framebuffer *intel_fb;
5253 int ret;
5254
5255 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5256 if (!intel_fb) {
5257 drm_gem_object_unreference_unlocked(&obj->base);
5258 return ERR_PTR(-ENOMEM);
5259 }
5260
5261 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5262 if (ret) {
5263 drm_gem_object_unreference_unlocked(&obj->base);
5264 kfree(intel_fb);
5265 return ERR_PTR(ret);
5266 }
5267
5268 return &intel_fb->base;
5269}
5270
5271static u32
5272intel_framebuffer_pitch_for_width(int width, int bpp)
5273{
5274 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5275 return ALIGN(pitch, 64);
5276}
5277
5278static u32
5279intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5280{
5281 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5282 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5283}
5284
5285static struct drm_framebuffer *
5286intel_framebuffer_create_for_mode(struct drm_device *dev,
5287 struct drm_display_mode *mode,
5288 int depth, int bpp)
5289{
5290 struct drm_i915_gem_object *obj;
308e5bcb 5291 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5292
5293 obj = i915_gem_alloc_object(dev,
5294 intel_framebuffer_size_for_mode(mode, bpp));
5295 if (obj == NULL)
5296 return ERR_PTR(-ENOMEM);
5297
5298 mode_cmd.width = mode->hdisplay;
5299 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5300 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5301 bpp);
5ca0c34a 5302 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5303
5304 return intel_framebuffer_create(dev, &mode_cmd, obj);
5305}
5306
5307static struct drm_framebuffer *
5308mode_fits_in_fbdev(struct drm_device *dev,
5309 struct drm_display_mode *mode)
5310{
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312 struct drm_i915_gem_object *obj;
5313 struct drm_framebuffer *fb;
5314
5315 if (dev_priv->fbdev == NULL)
5316 return NULL;
5317
5318 obj = dev_priv->fbdev->ifb.obj;
5319 if (obj == NULL)
5320 return NULL;
5321
5322 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5323 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5324 fb->bits_per_pixel))
d2dff872
CW		 5325 return NULL;
5326
01f2c773 5327 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5328 return NULL;
5329
5330 return fb;
5331}
5332
7173188d
CW		 5333bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5334 struct drm_connector *connector,
5335 struct drm_display_mode *mode,
8261b191 5336 struct intel_load_detect_pipe *old)
79e53945
JB		 5337{
5338 struct intel_crtc *intel_crtc;
5339 struct drm_crtc *possible_crtc;
4ef69c7a 5340 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5341 struct drm_crtc *crtc = NULL;
5342 struct drm_device *dev = encoder->dev;
d2dff872 5343 struct drm_framebuffer *old_fb;
79e53945
JB		 5344 int i = -1;
5345
d2dff872
CW		 5346 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5347 connector->base.id, drm_get_connector_name(connector),
5348 encoder->base.id, drm_get_encoder_name(encoder));
5349
79e53945
JB		 5350 /*
5351 * Algorithm gets a little messy:
7a5e4805 5352 *
79e53945
JB		 5353 * - if the connector already has an assigned crtc, use it (but make
5354 * sure it's on first)
7a5e4805 5355 *
79e53945
JB		 5356 * - try to find the first unused crtc that can drive this connector,
5357 * and use that if we find one
79e53945
JB		 5358 */
5359
5360 /* See if we already have a CRTC for this connector */
5361 if (encoder->crtc) {
5362 crtc = encoder->crtc;
8261b191 5363
79e53945 5364 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5365 old->dpms_mode = intel_crtc->dpms_mode;
5366 old->load_detect_temp = false;
5367
5368 /* Make sure the crtc and connector are running */
79e53945 5369 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5370 struct drm_encoder_helper_funcs *encoder_funcs;
5371 struct drm_crtc_helper_funcs *crtc_funcs;
5372
79e53945
JB		 5373 crtc_funcs = crtc->helper_private;
5374 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5375
5376 encoder_funcs = encoder->helper_private;
79e53945
JB		 5377 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5378 }
8261b191 5379
7173188d 5380 return true;
79e53945
JB		 5381 }
5382
5383 /* Find an unused one (if possible) */
5384 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5385 i++;
5386 if (!(encoder->possible_crtcs & (1 << i)))
5387 continue;
5388 if (!possible_crtc->enabled) {
5389 crtc = possible_crtc;
5390 break;
5391 }
79e53945
JB		 5392 }
5393
5394 /*
5395 * If we didn't find an unused CRTC, don't use any.
5396 */
5397 if (!crtc) {
7173188d
CW		 5398 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5399 return false;
79e53945
JB		 5400 }
5401
5402 encoder->crtc = crtc;
c1c43977 5403 connector->encoder = encoder;
79e53945
JB		 5404
5405 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5406 old->dpms_mode = intel_crtc->dpms_mode;
5407 old->load_detect_temp = true;
d2dff872 5408 old->release_fb = NULL;
79e53945 5409
6492711d
CW		 5410 if (!mode)
5411 mode = &load_detect_mode;
79e53945 5412
d2dff872
CW		 5413 old_fb = crtc->fb;
5414
5415 /* We need a framebuffer large enough to accommodate all accesses
5416 * that the plane may generate whilst we perform load detection.
5417 * We can not rely on the fbcon either being present (we get called
5418 * during its initialisation to detect all boot displays, or it may
5419 * not even exist) or that it is large enough to satisfy the
5420 * requested mode.
5421 */
5422 crtc->fb = mode_fits_in_fbdev(dev, mode);
5423 if (crtc->fb == NULL) {
5424 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5425 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5426 old->release_fb = crtc->fb;
5427 } else
5428 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5429 if (IS_ERR(crtc->fb)) {
5430 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5431 crtc->fb = old_fb;
5432 return false;
79e53945 5433 }
79e53945 5434
d2dff872 5435 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5436 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5437 if (old->release_fb)
5438 old->release_fb->funcs->destroy(old->release_fb);
5439 crtc->fb = old_fb;
6492711d 5440 return false;
79e53945 5441 }
7173188d 5442
79e53945 5443 /* let the connector get through one full cycle before testing */
9d0498a2 5444 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5445
7173188d 5446 return true;
79e53945
JB		 5447}
5448
c1c43977 5449void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5450 struct drm_connector *connector,
5451 struct intel_load_detect_pipe *old)
79e53945 5452{
4ef69c7a 5453 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5454 struct drm_device *dev = encoder->dev;
5455 struct drm_crtc *crtc = encoder->crtc;
5456 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5457 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5458
d2dff872
CW		 5459 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5460 connector->base.id, drm_get_connector_name(connector),
5461 encoder->base.id, drm_get_encoder_name(encoder));
5462
8261b191 5463 if (old->load_detect_temp) {
c1c43977 5464 connector->encoder = NULL;
79e53945 5465 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5466
5467 if (old->release_fb)
5468 old->release_fb->funcs->destroy(old->release_fb);
5469
0622a53c 5470 return;
79e53945
JB		 5471 }
5472
c751ce4f 5473 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5474 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5475 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5476 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5477 }
5478}
5479
5480/* Returns the clock of the currently programmed mode of the given pipe. */
5481static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5482{
5483 struct drm_i915_private *dev_priv = dev->dev_private;
5484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5485 int pipe = intel_crtc->pipe;
548f245b 5486 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5487 u32 fp;
5488 intel_clock_t clock;
5489
5490 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5491 fp = I915_READ(FP0(pipe));
79e53945 5492 else
39adb7a5 5493 fp = I915_READ(FP1(pipe));
79e53945
JB		 5494
5495 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5496 if (IS_PINEVIEW(dev)) {
5497 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5498 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5499 } else {
5500 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5501 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5502 }
5503
a6c45cf0 5504 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5505 if (IS_PINEVIEW(dev))
5506 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5507 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5508 else
5509 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5510 DPLL_FPA01_P1_POST_DIV_SHIFT);
5511
5512 switch (dpll & DPLL_MODE_MASK) {
5513 case DPLLB_MODE_DAC_SERIAL:
5514 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5515 5 : 10;
5516 break;
5517 case DPLLB_MODE_LVDS:
5518 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5519 7 : 14;
5520 break;
5521 default:
28c97730 5522 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5523 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5524 return 0;
5525 }
5526
5527 /* XXX: Handle the 100Mhz refclk */
2177832f 5528 intel_clock(dev, 96000, &clock);
79e53945
JB		 5529 } else {
5530 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5531
5532 if (is_lvds) {
5533 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5534 DPLL_FPA01_P1_POST_DIV_SHIFT);
5535 clock.p2 = 14;
5536
5537 if ((dpll & PLL_REF_INPUT_MASK) ==
5538 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5539 /* XXX: might not be 66MHz */
2177832f 5540 intel_clock(dev, 66000, &clock);
79e53945 5541 } else
2177832f 5542 intel_clock(dev, 48000, &clock);
79e53945
JB		 5543 } else {
5544 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5545 clock.p1 = 2;
5546 else {
5547 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5548 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5549 }
5550 if (dpll & PLL_P2_DIVIDE_BY_4)
5551 clock.p2 = 4;
5552 else
5553 clock.p2 = 2;
5554
2177832f 5555 intel_clock(dev, 48000, &clock);
79e53945
JB		 5556 }
5557 }
5558
5559 /* XXX: It would be nice to validate the clocks, but we can't reuse
5560 * i830PllIsValid() because it relies on the xf86_config connector
5561 * configuration being accurate, which it isn't necessarily.
5562 */
5563
5564 return clock.dot;
5565}
5566
5567/** Returns the currently programmed mode of the given pipe. */
5568struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5569 struct drm_crtc *crtc)
5570{
548f245b 5571 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5572 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5573 int pipe = intel_crtc->pipe;
5574 struct drm_display_mode *mode;
548f245b
JB		 5575 int htot = I915_READ(HTOTAL(pipe));
5576 int hsync = I915_READ(HSYNC(pipe));
5577 int vtot = I915_READ(VTOTAL(pipe));
5578 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5579
5580 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5581 if (!mode)
5582 return NULL;
5583
5584 mode->clock = intel_crtc_clock_get(dev, crtc);
5585 mode->hdisplay = (htot & 0xffff) + 1;
5586 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5587 mode->hsync_start = (hsync & 0xffff) + 1;
5588 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5589 mode->vdisplay = (vtot & 0xffff) + 1;
5590 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5591 mode->vsync_start = (vsync & 0xffff) + 1;
5592 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5593
5594 drm_mode_set_name(mode);
79e53945
JB		 5595
5596 return mode;
5597}
5598
652c393a
JB		 5599#define GPU_IDLE_TIMEOUT 500 /* ms */
5600
5601/* When this timer fires, we've been idle for awhile */
5602static void intel_gpu_idle_timer(unsigned long arg)
5603{
5604 struct drm_device *dev = (struct drm_device *)arg;
5605 drm_i915_private_t *dev_priv = dev->dev_private;
5606
ff7ea4c0
CW		 5607 if (!list_empty(&dev_priv->mm.active_list)) {
5608 /* Still processing requests, so just re-arm the timer. */
5609 mod_timer(&dev_priv->idle_timer, jiffies +
5610 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5611 return;
5612 }
652c393a 5613
ff7ea4c0 5614 dev_priv->busy = false;
01dfba93 5615 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5616}
5617
652c393a
JB		 5618#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5619
5620static void intel_crtc_idle_timer(unsigned long arg)
5621{
5622 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5623 struct drm_crtc *crtc = &intel_crtc->base;
5624 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5625 struct intel_framebuffer *intel_fb;
652c393a 5626
ff7ea4c0
CW		 5627 intel_fb = to_intel_framebuffer(crtc->fb);
5628 if (intel_fb && intel_fb->obj->active) {
5629 /* The framebuffer is still being accessed by the GPU. */
5630 mod_timer(&intel_crtc->idle_timer, jiffies +
5631 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5632 return;
5633 }
652c393a 5634
ff7ea4c0 5635 intel_crtc->busy = false;
01dfba93 5636 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5637}
5638
3dec0095 5639static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5640{
5641 struct drm_device *dev = crtc->dev;
5642 drm_i915_private_t *dev_priv = dev->dev_private;
5643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5644 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5645 int dpll_reg = DPLL(pipe);
5646 int dpll;
652c393a 5647
bad720ff 5648 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5649 return;
5650
5651 if (!dev_priv->lvds_downclock_avail)
5652 return;
5653
dbdc6479 5654 dpll = I915_READ(dpll_reg);
652c393a 5655 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5656 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5657
8ac5a6d5 5658 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5659
5660 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5661 I915_WRITE(dpll_reg, dpll);
9d0498a2 5662 intel_wait_for_vblank(dev, pipe);
dbdc6479 5663
652c393a
JB		 5664 dpll = I915_READ(dpll_reg);
5665 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5666 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5667 }
5668
5669 /* Schedule downclock */
3dec0095
DV		 5670 mod_timer(&intel_crtc->idle_timer, jiffies +
5671 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5672}
5673
5674static void intel_decrease_pllclock(struct drm_crtc *crtc)
5675{
5676 struct drm_device *dev = crtc->dev;
5677 drm_i915_private_t *dev_priv = dev->dev_private;
5678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5679
bad720ff 5680 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5681 return;
5682
5683 if (!dev_priv->lvds_downclock_avail)
5684 return;
5685
5686 /*
5687 * Since this is called by a timer, we should never get here in
5688 * the manual case.
5689 */
5690 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5691 int pipe = intel_crtc->pipe;
5692 int dpll_reg = DPLL(pipe);
5693 int dpll;
f6e5b160 5694
44d98a61 5695 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5696
8ac5a6d5 5697 assert_panel_unlocked(dev_priv, pipe);
652c393a 5698
dc257cf1 5699 dpll = I915_READ(dpll_reg);
652c393a
JB		 5700 dpll |= DISPLAY_RATE_SELECT_FPA1;
5701 I915_WRITE(dpll_reg, dpll);
9d0498a2 5702 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5703 dpll = I915_READ(dpll_reg);
5704 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5705 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5706 }
5707
5708}
5709
5710/**
5711 * intel_idle_update - adjust clocks for idleness
5712 * @work: work struct
5713 *
5714 * Either the GPU or display (or both) went idle. Check the busy status
5715 * here and adjust the CRTC and GPU clocks as necessary.
5716 */
5717static void intel_idle_update(struct work_struct *work)
5718{
5719 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5720 idle_work);
5721 struct drm_device *dev = dev_priv->dev;
5722 struct drm_crtc *crtc;
5723 struct intel_crtc *intel_crtc;
5724
5725 if (!i915_powersave)
5726 return;
5727
5728 mutex_lock(&dev->struct_mutex);
5729
7648fa99
JB		 5730 i915_update_gfx_val(dev_priv);
5731
652c393a
JB		 5732 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5733 /* Skip inactive CRTCs */
5734 if (!crtc->fb)
5735 continue;
5736
5737 intel_crtc = to_intel_crtc(crtc);
5738 if (!intel_crtc->busy)
5739 intel_decrease_pllclock(crtc);
5740 }
5741
45ac22c8 5742
652c393a
JB		 5743 mutex_unlock(&dev->struct_mutex);
5744}
5745
5746/**
5747 * intel_mark_busy - mark the GPU and possibly the display busy
5748 * @dev: drm device
5749 * @obj: object we're operating on
5750 *
5751 * Callers can use this function to indicate that the GPU is busy processing
5752 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5753 * buffer), we'll also mark the display as busy, so we know to increase its
5754 * clock frequency.
5755 */
05394f39 5756void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5757{
5758 drm_i915_private_t *dev_priv = dev->dev_private;
5759 struct drm_crtc *crtc = NULL;
5760 struct intel_framebuffer *intel_fb;
5761 struct intel_crtc *intel_crtc;
5762
5e17ee74
ZW		 5763 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5764 return;
5765
9104183d
CW		 5766 if (!dev_priv->busy) {
5767 intel_sanitize_pm(dev);
28cf798f 5768 dev_priv->busy = true;
9104183d 5769 } else
28cf798f
CW		 5770 mod_timer(&dev_priv->idle_timer, jiffies +
5771 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 5772
acb87dfb
CW		 5773 if (obj == NULL)
5774 return;
5775
652c393a
JB		 5776 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5777 if (!crtc->fb)
5778 continue;
5779
5780 intel_crtc = to_intel_crtc(crtc);
5781 intel_fb = to_intel_framebuffer(crtc->fb);
5782 if (intel_fb->obj == obj) {
5783 if (!intel_crtc->busy) {
5784 /* Non-busy -> busy, upclock */
3dec0095 5785 intel_increase_pllclock(crtc);
652c393a
JB		 5786 intel_crtc->busy = true;
5787 } else {
5788 /* Busy -> busy, put off timer */
5789 mod_timer(&intel_crtc->idle_timer, jiffies +
5790 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5791 }
5792 }
5793 }
5794}
5795
79e53945
JB		 5796static void intel_crtc_destroy(struct drm_crtc *crtc)
5797{
5798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5799 struct drm_device *dev = crtc->dev;
5800 struct intel_unpin_work *work;
5801 unsigned long flags;
5802
5803 spin_lock_irqsave(&dev->event_lock, flags);
5804 work = intel_crtc->unpin_work;
5805 intel_crtc->unpin_work = NULL;
5806 spin_unlock_irqrestore(&dev->event_lock, flags);
5807
5808 if (work) {
5809 cancel_work_sync(&work->work);
5810 kfree(work);
5811 }
79e53945
JB		 5812
5813 drm_crtc_cleanup(crtc);
67e77c5a 5814
79e53945
JB		 5815 kfree(intel_crtc);
5816}
5817
6b95a207
KH		 5818static void intel_unpin_work_fn(struct work_struct *__work)
5819{
5820 struct intel_unpin_work *work =
5821 container_of(__work, struct intel_unpin_work, work);
5822
5823 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5824 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5825 drm_gem_object_unreference(&work->pending_flip_obj->base);
5826 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5827
7782de3b 5828 intel_update_fbc(work->dev);
6b95a207
KH		 5829 mutex_unlock(&work->dev->struct_mutex);
5830 kfree(work);
5831}
5832
1afe3e9d 5833static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5834 struct drm_crtc *crtc)
6b95a207
KH		 5835{
5836 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5838 struct intel_unpin_work *work;
05394f39 5839 struct drm_i915_gem_object *obj;
6b95a207 5840 struct drm_pending_vblank_event *e;
49b14a5c 5841 struct timeval tnow, tvbl;
6b95a207
KH		 5842 unsigned long flags;
5843
5844 /* Ignore early vblank irqs */
5845 if (intel_crtc == NULL)
5846 return;
5847
49b14a5c
MK		 5848 do_gettimeofday(&tnow);
5849
6b95a207
KH		 5850 spin_lock_irqsave(&dev->event_lock, flags);
5851 work = intel_crtc->unpin_work;
5852 if (work == NULL || !work->pending) {
5853 spin_unlock_irqrestore(&dev->event_lock, flags);
5854 return;
5855 }
5856
5857 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5858
5859 if (work->event) {
5860 e = work->event;
49b14a5c 5861 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5862
5863 /* Called before vblank count and timestamps have
5864 * been updated for the vblank interval of flip
5865 * completion? Need to increment vblank count and
5866 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5867 * to account for this. We assume this happened if we
5868 * get called over 0.9 frame durations after the last
5869 * timestamped vblank.
5870 *
5871 * This calculation can not be used with vrefresh rates
5872 * below 5Hz (10Hz to be on the safe side) without
5873 * promoting to 64 integers.
0af7e4df 5874 */
49b14a5c
MK		 5875 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5876 9 * crtc->framedur_ns) {
0af7e4df 5877 e->event.sequence++;
49b14a5c
MK		 5878 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5879 crtc->framedur_ns);
0af7e4df
MK		 5880 }
5881
49b14a5c
MK		 5882 e->event.tv_sec = tvbl.tv_sec;
5883 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5884
6b95a207
KH		 5885 list_add_tail(&e->base.link,
5886 &e->base.file_priv->event_list);
5887 wake_up_interruptible(&e->base.file_priv->event_wait);
5888 }
5889
0af7e4df
MK		 5890 drm_vblank_put(dev, intel_crtc->pipe);
5891
6b95a207
KH		 5892 spin_unlock_irqrestore(&dev->event_lock, flags);
5893
05394f39 5894 obj = work->old_fb_obj;
d9e86c0e 5895
e59f2bac 5896 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5897 &obj->pending_flip.counter);
5898 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5899 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5900
6b95a207 5901 schedule_work(&work->work);
e5510fac
JB		 5902
5903 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5904}
5905
1afe3e9d
JB		 5906void intel_finish_page_flip(struct drm_device *dev, int pipe)
5907{
5908 drm_i915_private_t *dev_priv = dev->dev_private;
5909 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5910
49b14a5c 5911 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5912}
5913
5914void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5915{
5916 drm_i915_private_t *dev_priv = dev->dev_private;
5917 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5918
49b14a5c 5919 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5920}
5921
6b95a207
KH		 5922void intel_prepare_page_flip(struct drm_device *dev, int plane)
5923{
5924 drm_i915_private_t *dev_priv = dev->dev_private;
5925 struct intel_crtc *intel_crtc =
5926 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5927 unsigned long flags;
5928
5929 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5930 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5931 if ((++intel_crtc->unpin_work->pending) > 1)
5932 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5933 } else {
5934 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5935 }
6b95a207
KH		 5936 spin_unlock_irqrestore(&dev->event_lock, flags);
5937}
5938
8c9f3aaf
JB		 5939static int intel_gen2_queue_flip(struct drm_device *dev,
5940 struct drm_crtc *crtc,
5941 struct drm_framebuffer *fb,
5942 struct drm_i915_gem_object *obj)
5943{
5944 struct drm_i915_private *dev_priv = dev->dev_private;
5945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5946 unsigned long offset;
5947 u32 flip_mask;
6d90c952 5948 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5949 int ret;
5950
6d90c952 5951 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5952 if (ret)
83d4092b 5953 goto err;
8c9f3aaf
JB		 5954
5955 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5956 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5957
6d90c952 5958 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5959 if (ret)
83d4092b 5960 goto err_unpin;
8c9f3aaf
JB		 5961
5962 /* Can't queue multiple flips, so wait for the previous
5963 * one to finish before executing the next.
5964 */
5965 if (intel_crtc->plane)
5966 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5967 else
5968 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5969 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5970 intel_ring_emit(ring, MI_NOOP);
5971 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5972 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5973 intel_ring_emit(ring, fb->pitches[0]);
5974 intel_ring_emit(ring, obj->gtt_offset + offset);
5975 intel_ring_emit(ring, 0); /* aux display base address, unused */
5976 intel_ring_advance(ring);
83d4092b
CW		 5977 return 0;
5978
5979err_unpin:
5980 intel_unpin_fb_obj(obj);
5981err:
8c9f3aaf
JB		 5982 return ret;
5983}
5984
5985static int intel_gen3_queue_flip(struct drm_device *dev,
5986 struct drm_crtc *crtc,
5987 struct drm_framebuffer *fb,
5988 struct drm_i915_gem_object *obj)
5989{
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5992 unsigned long offset;
5993 u32 flip_mask;
6d90c952 5994 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5995 int ret;
5996
6d90c952 5997 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5998 if (ret)
83d4092b 5999 goto err;
8c9f3aaf
JB		 6000
6001 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 6002 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 6003
6d90c952 6004 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6005 if (ret)
83d4092b 6006 goto err_unpin;
8c9f3aaf
JB		 6007
6008 if (intel_crtc->plane)
6009 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6010 else
6011 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6012 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6013 intel_ring_emit(ring, MI_NOOP);
6014 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6015 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6016 intel_ring_emit(ring, fb->pitches[0]);
6017 intel_ring_emit(ring, obj->gtt_offset + offset);
6018 intel_ring_emit(ring, MI_NOOP);
6019
6020 intel_ring_advance(ring);
83d4092b
CW		 6021 return 0;
6022
6023err_unpin:
6024 intel_unpin_fb_obj(obj);
6025err:
8c9f3aaf
JB		 6026 return ret;
6027}
6028
6029static int intel_gen4_queue_flip(struct drm_device *dev,
6030 struct drm_crtc *crtc,
6031 struct drm_framebuffer *fb,
6032 struct drm_i915_gem_object *obj)
6033{
6034 struct drm_i915_private *dev_priv = dev->dev_private;
6035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6036 uint32_t pf, pipesrc;
6d90c952 6037 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6038 int ret;
6039
6d90c952 6040 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6041 if (ret)
83d4092b 6042 goto err;
8c9f3aaf 6043
6d90c952 6044 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6045 if (ret)
83d4092b 6046 goto err_unpin;
8c9f3aaf
JB		 6047
6048 /* i965+ uses the linear or tiled offsets from the
6049 * Display Registers (which do not change across a page-flip)
6050 * so we need only reprogram the base address.
6051 */
6d90c952
DV		 6052 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6053 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6054 intel_ring_emit(ring, fb->pitches[0]);
6055 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
8c9f3aaf
JB		 6056
6057 /* XXX Enabling the panel-fitter across page-flip is so far
6058 * untested on non-native modes, so ignore it for now.
6059 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6060 */
6061 pf = 0;
6062 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6063 intel_ring_emit(ring, pf | pipesrc);
6064 intel_ring_advance(ring);
83d4092b
CW		 6065 return 0;
6066
6067err_unpin:
6068 intel_unpin_fb_obj(obj);
6069err:
8c9f3aaf
JB		 6070 return ret;
6071}
6072
6073static int intel_gen6_queue_flip(struct drm_device *dev,
6074 struct drm_crtc *crtc,
6075 struct drm_framebuffer *fb,
6076 struct drm_i915_gem_object *obj)
6077{
6078 struct drm_i915_private *dev_priv = dev->dev_private;
6079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6080 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6081 uint32_t pf, pipesrc;
6082 int ret;
6083
6d90c952 6084 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6085 if (ret)
83d4092b 6086 goto err;
8c9f3aaf 6087
6d90c952 6088 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6089 if (ret)
83d4092b 6090 goto err_unpin;
8c9f3aaf 6091
6d90c952
DV		 6092 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6093 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6094 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6095 intel_ring_emit(ring, obj->gtt_offset);
8c9f3aaf 6096
dc257cf1
DV		 6097 /* Contrary to the suggestions in the documentation,
6098 * "Enable Panel Fitter" does not seem to be required when page
6099 * flipping with a non-native mode, and worse causes a normal
6100 * modeset to fail.
6101 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6102 */
6103 pf = 0;
8c9f3aaf 6104 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6105 intel_ring_emit(ring, pf | pipesrc);
6106 intel_ring_advance(ring);
83d4092b
CW		 6107 return 0;
6108
6109err_unpin:
6110 intel_unpin_fb_obj(obj);
6111err:
8c9f3aaf
JB		 6112 return ret;
6113}
6114
7c9017e5
JB		 6115/*
6116 * On gen7 we currently use the blit ring because (in early silicon at least)
6117 * the render ring doesn't give us interrpts for page flip completion, which
6118 * means clients will hang after the first flip is queued. Fortunately the
6119 * blit ring generates interrupts properly, so use it instead.
6120 */
6121static int intel_gen7_queue_flip(struct drm_device *dev,
6122 struct drm_crtc *crtc,
6123 struct drm_framebuffer *fb,
6124 struct drm_i915_gem_object *obj)
6125{
6126 struct drm_i915_private *dev_priv = dev->dev_private;
6127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6128 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6129 int ret;
6130
6131 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6132 if (ret)
83d4092b 6133 goto err;
7c9017e5
JB		 6134
6135 ret = intel_ring_begin(ring, 4);
6136 if (ret)
83d4092b 6137 goto err_unpin;
7c9017e5
JB		 6138
6139 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 6140 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 6141 intel_ring_emit(ring, (obj->gtt_offset));
6142 intel_ring_emit(ring, (MI_NOOP));
6143 intel_ring_advance(ring);
83d4092b
CW		 6144 return 0;
6145
6146err_unpin:
6147 intel_unpin_fb_obj(obj);
6148err:
7c9017e5
JB		 6149 return ret;
6150}
6151
8c9f3aaf
JB		 6152static int intel_default_queue_flip(struct drm_device *dev,
6153 struct drm_crtc *crtc,
6154 struct drm_framebuffer *fb,
6155 struct drm_i915_gem_object *obj)
6156{
6157 return -ENODEV;
6158}
6159
6b95a207
KH		 6160static int intel_crtc_page_flip(struct drm_crtc *crtc,
6161 struct drm_framebuffer *fb,
6162 struct drm_pending_vblank_event *event)
6163{
6164 struct drm_device *dev = crtc->dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166 struct intel_framebuffer *intel_fb;
05394f39 6167 struct drm_i915_gem_object *obj;
6b95a207
KH		 6168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6169 struct intel_unpin_work *work;
8c9f3aaf 6170 unsigned long flags;
52e68630 6171 int ret;
6b95a207
KH		 6172
6173 work = kzalloc(sizeof *work, GFP_KERNEL);
6174 if (work == NULL)
6175 return -ENOMEM;
6176
6b95a207
KH		 6177 work->event = event;
6178 work->dev = crtc->dev;
6179 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6180 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6181 INIT_WORK(&work->work, intel_unpin_work_fn);
6182
7317c75e
JB		 6183 ret = drm_vblank_get(dev, intel_crtc->pipe);
6184 if (ret)
6185 goto free_work;
6186
6b95a207
KH		 6187 /* We borrow the event spin lock for protecting unpin_work */
6188 spin_lock_irqsave(&dev->event_lock, flags);
6189 if (intel_crtc->unpin_work) {
6190 spin_unlock_irqrestore(&dev->event_lock, flags);
6191 kfree(work);
7317c75e 6192 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6193
6194 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6195 return -EBUSY;
6196 }
6197 intel_crtc->unpin_work = work;
6198 spin_unlock_irqrestore(&dev->event_lock, flags);
6199
6200 intel_fb = to_intel_framebuffer(fb);
6201 obj = intel_fb->obj;
6202
468f0b44 6203 mutex_lock(&dev->struct_mutex);
6b95a207 6204
75dfca80 6205 /* Reference the objects for the scheduled work. */
05394f39
CW		 6206 drm_gem_object_reference(&work->old_fb_obj->base);
6207 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6208
6209 crtc->fb = fb;
96b099fd 6210
e1f99ce6 6211 work->pending_flip_obj = obj;
e1f99ce6 6212
4e5359cd
SF		 6213 work->enable_stall_check = true;
6214
e1f99ce6
CW		 6215 /* Block clients from rendering to the new back buffer until
6216 * the flip occurs and the object is no longer visible.
6217 */
05394f39 6218 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6219
8c9f3aaf
JB		 6220 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6221 if (ret)
6222 goto cleanup_pending;
6b95a207 6223
7782de3b 6224 intel_disable_fbc(dev);
acb87dfb 6225 intel_mark_busy(dev, obj);
6b95a207
KH		 6226 mutex_unlock(&dev->struct_mutex);
6227
e5510fac
JB		 6228 trace_i915_flip_request(intel_crtc->plane, obj);
6229
6b95a207 6230 return 0;
96b099fd 6231
8c9f3aaf
JB		 6232cleanup_pending:
6233 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6234 drm_gem_object_unreference(&work->old_fb_obj->base);
6235 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6236 mutex_unlock(&dev->struct_mutex);
6237
6238 spin_lock_irqsave(&dev->event_lock, flags);
6239 intel_crtc->unpin_work = NULL;
6240 spin_unlock_irqrestore(&dev->event_lock, flags);
6241
7317c75e
JB		 6242 drm_vblank_put(dev, intel_crtc->pipe);
6243free_work:
96b099fd
CW		 6244 kfree(work);
6245
6246 return ret;
6b95a207
KH		 6247}
6248
47f1c6c9
CW		 6249static void intel_sanitize_modesetting(struct drm_device *dev,
6250 int pipe, int plane)
6251{
6252 struct drm_i915_private *dev_priv = dev->dev_private;
6253 u32 reg, val;
6254
f47166d2
CW		 6255 /* Clear any frame start delays used for debugging left by the BIOS */
6256 for_each_pipe(pipe) {
6257 reg = PIPECONF(pipe);
6258 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6259 }
6260
47f1c6c9
CW		 6261 if (HAS_PCH_SPLIT(dev))
6262 return;
6263
6264 /* Who knows what state these registers were left in by the BIOS or
6265 * grub?
6266 *
6267 * If we leave the registers in a conflicting state (e.g. with the
6268 * display plane reading from the other pipe than the one we intend
6269 * to use) then when we attempt to teardown the active mode, we will
6270 * not disable the pipes and planes in the correct order -- leaving
6271 * a plane reading from a disabled pipe and possibly leading to
6272 * undefined behaviour.
6273 */
6274
6275 reg = DSPCNTR(plane);
6276 val = I915_READ(reg);
6277
6278 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6279 return;
6280 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6281 return;
6282
6283 /* This display plane is active and attached to the other CPU pipe. */
6284 pipe = !pipe;
6285
6286 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6287 intel_disable_plane(dev_priv, plane, pipe);
6288 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6289}
79e53945 6290
f6e5b160
CW		 6291static void intel_crtc_reset(struct drm_crtc *crtc)
6292{
6293 struct drm_device *dev = crtc->dev;
6294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6295
6296 /* Reset flags back to the 'unknown' status so that they
6297 * will be correctly set on the initial modeset.
6298 */
6299 intel_crtc->dpms_mode = -1;
6300
6301 /* We need to fix up any BIOS configuration that conflicts with
6302 * our expectations.
6303 */
6304 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6305}
6306
6307static struct drm_crtc_helper_funcs intel_helper_funcs = {
6308 .dpms = intel_crtc_dpms,
6309 .mode_fixup = intel_crtc_mode_fixup,
6310 .mode_set = intel_crtc_mode_set,
6311 .mode_set_base = intel_pipe_set_base,
6312 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6313 .load_lut = intel_crtc_load_lut,
6314 .disable = intel_crtc_disable,
6315};
6316
6317static const struct drm_crtc_funcs intel_crtc_funcs = {
6318 .reset = intel_crtc_reset,
6319 .cursor_set = intel_crtc_cursor_set,
6320 .cursor_move = intel_crtc_cursor_move,
6321 .gamma_set = intel_crtc_gamma_set,
6322 .set_config = drm_crtc_helper_set_config,
6323 .destroy = intel_crtc_destroy,
6324 .page_flip = intel_crtc_page_flip,
6325};
6326
ee7b9f93
JB		 6327static void intel_pch_pll_init(struct drm_device *dev)
6328{
6329 drm_i915_private_t *dev_priv = dev->dev_private;
6330 int i;
6331
6332 if (dev_priv->num_pch_pll == 0) {
6333 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6334 return;
6335 }
6336
6337 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6338 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6339 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6340 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6341 }
6342}
6343
b358d0a6 6344static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6345{
22fd0fab 6346 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6347 struct intel_crtc *intel_crtc;
6348 int i;
6349
6350 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6351 if (intel_crtc == NULL)
6352 return;
6353
6354 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6355
6356 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6357 for (i = 0; i < 256; i++) {
6358 intel_crtc->lut_r[i] = i;
6359 intel_crtc->lut_g[i] = i;
6360 intel_crtc->lut_b[i] = i;
6361 }
6362
80824003
JB		 6363 /* Swap pipes & planes for FBC on pre-965 */
6364 intel_crtc->pipe = pipe;
6365 intel_crtc->plane = pipe;
e2e767ab 6366 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6367 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6368 intel_crtc->plane = !pipe;
80824003
JB		 6369 }
6370
22fd0fab
JB		 6371 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6372 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6373 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6374 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6375
5d1d0cc8 6376 intel_crtc_reset(&intel_crtc->base);
04dbff52 6377 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6378 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6379
6380 if (HAS_PCH_SPLIT(dev)) {
6381 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6382 intel_helper_funcs.commit = ironlake_crtc_commit;
6383 } else {
6384 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6385 intel_helper_funcs.commit = i9xx_crtc_commit;
6386 }
6387
79e53945
JB		 6388 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6389
652c393a
JB		 6390 intel_crtc->busy = false;
6391
6392 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6393 (unsigned long)intel_crtc);
79e53945
JB		 6394}
6395
08d7b3d1 6396int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6397 struct drm_file *file)
08d7b3d1 6398{
08d7b3d1 6399 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6400 struct drm_mode_object *drmmode_obj;
6401 struct intel_crtc *crtc;
08d7b3d1 6402
1cff8f6b
DV		 6403 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6404 return -ENODEV;
08d7b3d1 6405
c05422d5
DV		 6406 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6407 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6408
c05422d5 6409 if (!drmmode_obj) {
08d7b3d1
CW		 6410 DRM_ERROR("no such CRTC id\n");
6411 return -EINVAL;
6412 }
6413
c05422d5
DV		 6414 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6415 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6416
c05422d5 6417 return 0;
08d7b3d1
CW		 6418}
6419
c5e4df33 6420static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6421{
4ef69c7a 6422 struct intel_encoder *encoder;
79e53945 6423 int index_mask = 0;
79e53945
JB		 6424 int entry = 0;
6425
4ef69c7a
CW		 6426 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6427 if (type_mask & encoder->clone_mask)
79e53945
JB		 6428 index_mask |= (1 << entry);
6429 entry++;
6430 }
4ef69c7a 6431
79e53945
JB		 6432 return index_mask;
6433}
6434
4d302442
CW		 6435static bool has_edp_a(struct drm_device *dev)
6436{
6437 struct drm_i915_private *dev_priv = dev->dev_private;
6438
6439 if (!IS_MOBILE(dev))
6440 return false;
6441
6442 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6443 return false;
6444
6445 if (IS_GEN5(dev) &&
6446 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6447 return false;
6448
6449 return true;
6450}
6451
79e53945
JB		 6452static void intel_setup_outputs(struct drm_device *dev)
6453{
725e30ad 6454 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6455 struct intel_encoder *encoder;
cb0953d7 6456 bool dpd_is_edp = false;
f3cfcba6 6457 bool has_lvds;
79e53945 6458
f3cfcba6 6459 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6460 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6461 /* disable the panel fitter on everything but LVDS */
6462 I915_WRITE(PFIT_CONTROL, 0);
6463 }
79e53945 6464
bad720ff 6465 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6466 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6467
4d302442 6468 if (has_edp_a(dev))
32f9d658
ZW		 6469 intel_dp_init(dev, DP_A);
6470
cb0953d7
AJ		 6471 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6472 intel_dp_init(dev, PCH_DP_D);
6473 }
6474
6475 intel_crt_init(dev);
6476
6477 if (HAS_PCH_SPLIT(dev)) {
6478 int found;
6479
30ad48b7 6480 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6481 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6482 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6483 if (!found)
6484 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6485 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6486 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6487 }
6488
6489 if (I915_READ(HDMIC) & PORT_DETECTED)
6490 intel_hdmi_init(dev, HDMIC);
6491
6492 if (I915_READ(HDMID) & PORT_DETECTED)
6493 intel_hdmi_init(dev, HDMID);
6494
5eb08b69
ZW		 6495 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6496 intel_dp_init(dev, PCH_DP_C);
6497
cb0953d7 6498 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6499 intel_dp_init(dev, PCH_DP_D);
6500
103a196f 6501 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6502 bool found = false;
7d57382e 6503
725e30ad 6504 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6505 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6506 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6507 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6508 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6509 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6510 }
27185ae1 6511
b01f2c3a
JB		 6512 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6513 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6514 intel_dp_init(dev, DP_B);
b01f2c3a 6515 }
725e30ad 6516 }
13520b05
KH		 6517
6518 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6519
b01f2c3a
JB		 6520 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6521 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6522 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6523 }
27185ae1
ML		 6524
6525 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6526
b01f2c3a
JB		 6527 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6528 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6529 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6530 }
6531 if (SUPPORTS_INTEGRATED_DP(dev)) {
6532 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6533 intel_dp_init(dev, DP_C);
b01f2c3a 6534 }
725e30ad 6535 }
27185ae1 6536
b01f2c3a
JB		 6537 if (SUPPORTS_INTEGRATED_DP(dev) &&
6538 (I915_READ(DP_D) & DP_DETECTED)) {
6539 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6540 intel_dp_init(dev, DP_D);
b01f2c3a 6541 }
bad720ff 6542 } else if (IS_GEN2(dev))
79e53945
JB		 6543 intel_dvo_init(dev);
6544
103a196f 6545 if (SUPPORTS_TV(dev))
79e53945
JB		 6546 intel_tv_init(dev);
6547
4ef69c7a
CW		 6548 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6549 encoder->base.possible_crtcs = encoder->crtc_mask;
6550 encoder->base.possible_clones =
6551 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6552 }
47356eb6 6553
2c7111db
CW		 6554 /* disable all the possible outputs/crtcs before entering KMS mode */
6555 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6556
6557 if (HAS_PCH_SPLIT(dev))
6558 ironlake_init_pch_refclk(dev);
79e53945
JB		 6559}
6560
6561static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6562{
6563 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6564
6565 drm_framebuffer_cleanup(fb);
05394f39 6566 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6567
6568 kfree(intel_fb);
6569}
6570
6571static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6572 struct drm_file *file,
79e53945
JB		 6573 unsigned int *handle)
6574{
6575 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6576 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6577
05394f39 6578 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6579}
6580
6581static const struct drm_framebuffer_funcs intel_fb_funcs = {
6582 .destroy = intel_user_framebuffer_destroy,
6583 .create_handle = intel_user_framebuffer_create_handle,
6584};
6585
38651674
DA		 6586int intel_framebuffer_init(struct drm_device *dev,
6587 struct intel_framebuffer *intel_fb,
308e5bcb 6588 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6589 struct drm_i915_gem_object *obj)
79e53945 6590{
79e53945
JB		 6591 int ret;
6592
05394f39 6593 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6594 return -EINVAL;
6595
308e5bcb 6596 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6597 return -EINVAL;
6598
308e5bcb 6599 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6600 case DRM_FORMAT_RGB332:
6601 case DRM_FORMAT_RGB565:
6602 case DRM_FORMAT_XRGB8888:
b250da79 6603 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6604 case DRM_FORMAT_ARGB8888:
6605 case DRM_FORMAT_XRGB2101010:
6606 case DRM_FORMAT_ARGB2101010:
308e5bcb 6607 /* RGB formats are common across chipsets */
b5626747 6608 break;
04b3924d
VS		 6609 case DRM_FORMAT_YUYV:
6610 case DRM_FORMAT_UYVY:
6611 case DRM_FORMAT_YVYU:
6612 case DRM_FORMAT_VYUY:
57cd6508
CW		 6613 break;
6614 default:
aca25848
ED		 6615 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6616 mode_cmd->pixel_format);
57cd6508
CW		 6617 return -EINVAL;
6618 }
6619
79e53945
JB		 6620 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6621 if (ret) {
6622 DRM_ERROR("framebuffer init failed %d\n", ret);
6623 return ret;
6624 }
6625
6626 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6627 intel_fb->obj = obj;
79e53945
JB		 6628 return 0;
6629}
6630
79e53945
JB		 6631static struct drm_framebuffer *
6632intel_user_framebuffer_create(struct drm_device *dev,
6633 struct drm_file *filp,
308e5bcb 6634 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6635{
05394f39 6636 struct drm_i915_gem_object *obj;
79e53945 6637
308e5bcb
JB		 6638 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6639 mode_cmd->handles[0]));
c8725226 6640 if (&obj->base == NULL)
cce13ff7 6641 return ERR_PTR(-ENOENT);
79e53945 6642
d2dff872 6643 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6644}
6645
79e53945 6646static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6647 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6648 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6649};
6650
e70236a8
JB		 6651/* Set up chip specific display functions */
6652static void intel_init_display(struct drm_device *dev)
6653{
6654 struct drm_i915_private *dev_priv = dev->dev_private;
6655
6656 /* We always want a DPMS function */
f564048e 6657 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6658 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6659 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6660 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6661 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6662 } else {
e70236a8 6663 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6664 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6665 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6666 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6667 }
e70236a8 6668
e70236a8 6669 /* Returns the core display clock speed */
25eb05fc
JB		 6670 if (IS_VALLEYVIEW(dev))
6671 dev_priv->display.get_display_clock_speed =
6672 valleyview_get_display_clock_speed;
6673 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6674 dev_priv->display.get_display_clock_speed =
6675 i945_get_display_clock_speed;
6676 else if (IS_I915G(dev))
6677 dev_priv->display.get_display_clock_speed =
6678 i915_get_display_clock_speed;
f2b115e6 6679 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6680 dev_priv->display.get_display_clock_speed =
6681 i9xx_misc_get_display_clock_speed;
6682 else if (IS_I915GM(dev))
6683 dev_priv->display.get_display_clock_speed =
6684 i915gm_get_display_clock_speed;
6685 else if (IS_I865G(dev))
6686 dev_priv->display.get_display_clock_speed =
6687 i865_get_display_clock_speed;
f0f8a9ce 6688 else if (IS_I85X(dev))
e70236a8
JB		 6689 dev_priv->display.get_display_clock_speed =
6690 i855_get_display_clock_speed;
6691 else /* 852, 830 */
6692 dev_priv->display.get_display_clock_speed =
6693 i830_get_display_clock_speed;
6694
7f8a8569 6695 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6696 if (IS_GEN5(dev)) {
674cf967 6697 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 6698 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 6699 } else if (IS_GEN6(dev)) {
674cf967 6700 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 6701 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6702 } else if (IS_IVYBRIDGE(dev)) {
6703 /* FIXME: detect B0+ stepping and use auto training */
6704 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 6705 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 6706 } else if (IS_HASWELL(dev)) {
6707 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
4abb3c8c 6708 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6709 } else
6710 dev_priv->display.update_wm = NULL;
ceb04246 6711 } else if (IS_VALLEYVIEW(dev)) {
575155a9
JB		 6712 dev_priv->display.force_wake_get = vlv_force_wake_get;
6713 dev_priv->display.force_wake_put = vlv_force_wake_put;
6067aaea 6714 } else if (IS_G4X(dev)) {
e0dac65e 6715 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6716 }
8c9f3aaf
JB		 6717
6718 /* Default just returns -ENODEV to indicate unsupported */
6719 dev_priv->display.queue_flip = intel_default_queue_flip;
6720
6721 switch (INTEL_INFO(dev)->gen) {
6722 case 2:
6723 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6724 break;
6725
6726 case 3:
6727 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6728 break;
6729
6730 case 4:
6731 case 5:
6732 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6733 break;
6734
6735 case 6:
6736 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6737 break;
7c9017e5
JB		 6738 case 7:
6739 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6740 break;
8c9f3aaf 6741 }
e70236a8
JB		 6742}
6743
b690e96c
JB		 6744/*
6745 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6746 * resume, or other times. This quirk makes sure that's the case for
6747 * affected systems.
6748 */
0206e353 6749static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6750{
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752
6753 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6754 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6755}
6756
435793df
KP		 6757/*
6758 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6759 */
6760static void quirk_ssc_force_disable(struct drm_device *dev)
6761{
6762 struct drm_i915_private *dev_priv = dev->dev_private;
6763 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6764 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6765}
6766
4dca20ef 6767/*
5a15ab5b
CE		 6768 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6769 * brightness value
4dca20ef
CE		 6770 */
6771static void quirk_invert_brightness(struct drm_device *dev)
6772{
6773 struct drm_i915_private *dev_priv = dev->dev_private;
6774 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6775 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6776}
6777
b690e96c
JB		 6778struct intel_quirk {
6779 int device;
6780 int subsystem_vendor;
6781 int subsystem_device;
6782 void (*hook)(struct drm_device *dev);
6783};
6784
c43b5634 6785static struct intel_quirk intel_quirks[] = {
b690e96c 6786 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6787 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6788
6789 /* Thinkpad R31 needs pipe A force quirk */
6790 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6791 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6792 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6793
6794 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6795 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6796 /* ThinkPad X40 needs pipe A force quirk */
6797
6798 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6799 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6800
6801 /* 855 & before need to leave pipe A & dpll A up */
6802 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6803 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6804
6805 /* Lenovo U160 cannot use SSC on LVDS */
6806 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6807
6808 /* Sony Vaio Y cannot use SSC on LVDS */
6809 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6810
6811 /* Acer Aspire 5734Z must invert backlight brightness */
6812 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6813};
6814
6815static void intel_init_quirks(struct drm_device *dev)
6816{
6817 struct pci_dev *d = dev->pdev;
6818 int i;
6819
6820 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6821 struct intel_quirk *q = &intel_quirks[i];
6822
6823 if (d->device == q->device &&
6824 (d->subsystem_vendor == q->subsystem_vendor ||
6825 q->subsystem_vendor == PCI_ANY_ID) &&
6826 (d->subsystem_device == q->subsystem_device ||
6827 q->subsystem_device == PCI_ANY_ID))
6828 q->hook(dev);
6829 }
6830}
6831
9cce37f4
JB		 6832/* Disable the VGA plane that we never use */
6833static void i915_disable_vga(struct drm_device *dev)
6834{
6835 struct drm_i915_private *dev_priv = dev->dev_private;
6836 u8 sr1;
6837 u32 vga_reg;
6838
6839 if (HAS_PCH_SPLIT(dev))
6840 vga_reg = CPU_VGACNTRL;
6841 else
6842 vga_reg = VGACNTRL;
6843
6844 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6845 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6846 sr1 = inb(VGA_SR_DATA);
6847 outb(sr1 | 1<<5, VGA_SR_DATA);
6848 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6849 udelay(300);
6850
6851 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6852 POSTING_READ(vga_reg);
6853}
6854
f82cfb6b
JB		 6855static void ivb_pch_pwm_override(struct drm_device *dev)
6856{
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858
6859 /*
6860 * IVB has CPU eDP backlight regs too, set things up to let the
6861 * PCH regs control the backlight
6862 */
6863 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6864 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6865 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6866}
6867
f817586c
DV		 6868void intel_modeset_init_hw(struct drm_device *dev)
6869{
6870 struct drm_i915_private *dev_priv = dev->dev_private;
6871
6872 intel_init_clock_gating(dev);
6873
6874 if (IS_IRONLAKE_M(dev)) {
6875 ironlake_enable_drps(dev);
1833b134 6876 ironlake_enable_rc6(dev);
f817586c
DV		 6877 intel_init_emon(dev);
6878 }
6879
b6834bd6 6880 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6881 gen6_enable_rps(dev_priv);
6882 gen6_update_ring_freq(dev_priv);
6883 }
f82cfb6b
JB		 6884
6885 if (IS_IVYBRIDGE(dev))
6886 ivb_pch_pwm_override(dev);
f817586c
DV		 6887}
6888
79e53945
JB		 6889void intel_modeset_init(struct drm_device *dev)
6890{
652c393a 6891 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6892 int i, ret;
79e53945
JB		 6893
6894 drm_mode_config_init(dev);
6895
6896 dev->mode_config.min_width = 0;
6897 dev->mode_config.min_height = 0;
6898
019d96cb
DA		 6899 dev->mode_config.preferred_depth = 24;
6900 dev->mode_config.prefer_shadow = 1;
6901
79e53945
JB		 6902 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6903
b690e96c
JB		 6904 intel_init_quirks(dev);
6905
1fa61106
ED		 6906 intel_init_pm(dev);
6907
45244b87
ED		 6908 intel_prepare_ddi(dev);
6909
e70236a8
JB		 6910 intel_init_display(dev);
6911
a6c45cf0
CW		 6912 if (IS_GEN2(dev)) {
6913 dev->mode_config.max_width = 2048;
6914 dev->mode_config.max_height = 2048;
6915 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6916 dev->mode_config.max_width = 4096;
6917 dev->mode_config.max_height = 4096;
79e53945 6918 } else {
a6c45cf0
CW		 6919 dev->mode_config.max_width = 8192;
6920 dev->mode_config.max_height = 8192;
79e53945 6921 }
35c3047a 6922 dev->mode_config.fb_base = dev->agp->base;
79e53945 6923
28c97730 6924 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6925 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6926
a3524f1b 6927 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6928 intel_crtc_init(dev, i);
00c2064b
JB		 6929 ret = intel_plane_init(dev, i);
6930 if (ret)
6931 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6932 }
6933
ee7b9f93
JB		 6934 intel_pch_pll_init(dev);
6935
9cce37f4
JB		 6936 /* Just disable it once at startup */
6937 i915_disable_vga(dev);
79e53945 6938 intel_setup_outputs(dev);
652c393a 6939
652c393a
JB		 6940 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6941 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6942 (unsigned long)dev);
2c7111db
CW		 6943}
6944
6945void intel_modeset_gem_init(struct drm_device *dev)
6946{
1833b134 6947 intel_modeset_init_hw(dev);
02e792fb
DV		 6948
6949 intel_setup_overlay(dev);
79e53945
JB		 6950}
6951
6952void intel_modeset_cleanup(struct drm_device *dev)
6953{
652c393a
JB		 6954 struct drm_i915_private *dev_priv = dev->dev_private;
6955 struct drm_crtc *crtc;
6956 struct intel_crtc *intel_crtc;
6957
f87ea761 6958 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6959 mutex_lock(&dev->struct_mutex);
6960
723bfd70
JB		 6961 intel_unregister_dsm_handler();
6962
6963
652c393a
JB		 6964 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6965 /* Skip inactive CRTCs */
6966 if (!crtc->fb)
6967 continue;
6968
6969 intel_crtc = to_intel_crtc(crtc);
3dec0095 6970 intel_increase_pllclock(crtc);
652c393a
JB		 6971 }
6972
973d04f9 6973 intel_disable_fbc(dev);
e70236a8 6974
f97108d1
JB		 6975 if (IS_IRONLAKE_M(dev))
6976 ironlake_disable_drps(dev);
b6834bd6 6977 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 6978 gen6_disable_rps(dev);
f97108d1 6979
d5bb081b
JB		 6980 if (IS_IRONLAKE_M(dev))
6981 ironlake_disable_rc6(dev);
0cdab21f 6982
57f350b6
JB		 6983 if (IS_VALLEYVIEW(dev))
6984 vlv_init_dpio(dev);
6985
69341a5e
KH		 6986 mutex_unlock(&dev->struct_mutex);
6987
6c0d9350
DV		 6988 /* Disable the irq before mode object teardown, for the irq might
6989 * enqueue unpin/hotplug work. */
6990 drm_irq_uninstall(dev);
6991 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 6992 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 6993
1630fe75
CW		 6994 /* flush any delayed tasks or pending work */
6995 flush_scheduled_work();
6996
3dec0095
DV		 6997 /* Shut off idle work before the crtcs get freed. */
6998 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6999 intel_crtc = to_intel_crtc(crtc);
7000 del_timer_sync(&intel_crtc->idle_timer);
7001 }
7002 del_timer_sync(&dev_priv->idle_timer);
7003 cancel_work_sync(&dev_priv->idle_work);
7004
79e53945
JB		 7005 drm_mode_config_cleanup(dev);
7006}
7007
f1c79df3
ZW		 7008/*
7009 * Return which encoder is currently attached for connector.
7010 */
df0e9248 7011struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7012{
df0e9248
CW		 7013 return &intel_attached_encoder(connector)->base;
7014}
f1c79df3 7015
df0e9248
CW		 7016void intel_connector_attach_encoder(struct intel_connector *connector,
7017 struct intel_encoder *encoder)
7018{
7019 connector->encoder = encoder;
7020 drm_mode_connector_attach_encoder(&connector->base,
7021 &encoder->base);
79e53945 7022}
28d52043
DA		 7023
7024/*
7025 * set vga decode state - true == enable VGA decode
7026 */
7027int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7028{
7029 struct drm_i915_private *dev_priv = dev->dev_private;
7030 u16 gmch_ctrl;
7031
7032 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7033 if (state)
7034 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7035 else
7036 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7037 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7038 return 0;
7039}
c4a1d9e4
CW		 7040
7041#ifdef CONFIG_DEBUG_FS
7042#include <linux/seq_file.h>
7043
7044struct intel_display_error_state {
7045 struct intel_cursor_error_state {
7046 u32 control;
7047 u32 position;
7048 u32 base;
7049 u32 size;
7050 } cursor[2];
7051
7052 struct intel_pipe_error_state {
7053 u32 conf;
7054 u32 source;
7055
7056 u32 htotal;
7057 u32 hblank;
7058 u32 hsync;
7059 u32 vtotal;
7060 u32 vblank;
7061 u32 vsync;
7062 } pipe[2];
7063
7064 struct intel_plane_error_state {
7065 u32 control;
7066 u32 stride;
7067 u32 size;
7068 u32 pos;
7069 u32 addr;
7070 u32 surface;
7071 u32 tile_offset;
7072 } plane[2];
7073};
7074
7075struct intel_display_error_state *
7076intel_display_capture_error_state(struct drm_device *dev)
7077{
0206e353 7078 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7079 struct intel_display_error_state *error;
7080 int i;
7081
7082 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7083 if (error == NULL)
7084 return NULL;
7085
7086 for (i = 0; i < 2; i++) {
7087 error->cursor[i].control = I915_READ(CURCNTR(i));
7088 error->cursor[i].position = I915_READ(CURPOS(i));
7089 error->cursor[i].base = I915_READ(CURBASE(i));
7090
7091 error->plane[i].control = I915_READ(DSPCNTR(i));
7092 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7093 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7094 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7095 error->plane[i].addr = I915_READ(DSPADDR(i));
7096 if (INTEL_INFO(dev)->gen >= 4) {
7097 error->plane[i].surface = I915_READ(DSPSURF(i));
7098 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7099 }
7100
7101 error->pipe[i].conf = I915_READ(PIPECONF(i));
7102 error->pipe[i].source = I915_READ(PIPESRC(i));
7103 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7104 error->pipe[i].hblank = I915_READ(HBLANK(i));
7105 error->pipe[i].hsync = I915_READ(HSYNC(i));
7106 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7107 error->pipe[i].vblank = I915_READ(VBLANK(i));
7108 error->pipe[i].vsync = I915_READ(VSYNC(i));
7109 }
7110
7111 return error;
7112}
7113
7114void
7115intel_display_print_error_state(struct seq_file *m,
7116 struct drm_device *dev,
7117 struct intel_display_error_state *error)
7118{
7119 int i;
7120
7121 for (i = 0; i < 2; i++) {
7122 seq_printf(m, "Pipe [%d]:\n", i);
7123 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7124 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7125 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7126 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7127 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7128 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7129 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7130 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7131
7132 seq_printf(m, "Plane [%d]:\n", i);
7133 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7134 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7135 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7136 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7137 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7138 if (INTEL_INFO(dev)->gen >= 4) {
7139 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7140 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7141 }
7142
7143 seq_printf(m, "Cursor [%d]:\n", i);
7144 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7145 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7146 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7147 }
7148}
7149#endif
Linux kernel - Deliverables
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