projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: move more pte encoding to pte encode
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a
JB		 1581/**
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
ee7b9f93 1589static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
040484af
JB		 1673static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
59c859d6
ED		 1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
040484af
JB		 1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
5f7f726d 1698 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
5f7f726d 1706 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1707 }
5f7f726d
PZ		 1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
040484af
JB		 1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722}
1723
1724static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726{
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
291906f1
JB		 1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
040484af
JB		 1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1744}
1745
b24e7179 1746/**
309cfea8 1747 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
040484af 1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
040484af
JB		 1760static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
b24e7179 1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
b24e7179 1783
702e7a56 1784 reg = PIPECONF(cpu_transcoder);
b24e7179 1785 val = I915_READ(reg);
00d70b15
CW		 1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791}
1792
1793/**
309cfea8 1794 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807{
702e7a56
PZ		 1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
b24e7179
JB		 1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
702e7a56 1823 reg = PIPECONF(cpu_transcoder);
b24e7179 1824 val = I915_READ(reg);
00d70b15
CW		 1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830}
1831
d74362c9
KP		 1832/*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
6f1d69b0 1836void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1837 enum plane plane)
1838{
14f86147
DL		 1839 if (dev_priv->info->gen >= 4)
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 else
1842 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1843}
1844
b24e7179
JB		 1845/**
1846 * intel_enable_plane - enable a display plane on a given pipe
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to enable
1849 * @pipe: pipe being fed
1850 *
1851 * Enable @plane on @pipe, making sure that @pipe is running first.
1852 */
1853static void intel_enable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855{
1856 int reg;
1857 u32 val;
1858
1859 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860 assert_pipe_enabled(dev_priv, pipe);
1861
1862 reg = DSPCNTR(plane);
1863 val = I915_READ(reg);
00d70b15
CW		 1864 if (val & DISPLAY_PLANE_ENABLE)
1865 return;
1866
1867 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1868 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1869 intel_wait_for_vblank(dev_priv->dev, pipe);
1870}
1871
b24e7179
JB		 1872/**
1873 * intel_disable_plane - disable a display plane
1874 * @dev_priv: i915 private structure
1875 * @plane: plane to disable
1876 * @pipe: pipe consuming the data
1877 *
1878 * Disable @plane; should be an independent operation.
1879 */
1880static void intel_disable_plane(struct drm_i915_private *dev_priv,
1881 enum plane plane, enum pipe pipe)
1882{
1883 int reg;
1884 u32 val;
1885
1886 reg = DSPCNTR(plane);
1887 val = I915_READ(reg);
00d70b15
CW		 1888 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1889 return;
1890
1891 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1892 intel_flush_display_plane(dev_priv, plane);
1893 intel_wait_for_vblank(dev_priv->dev, pipe);
1894}
1895
127bd2ac 1896int
48b956c5 1897intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1898 struct drm_i915_gem_object *obj,
919926ae 1899 struct intel_ring_buffer *pipelined)
6b95a207 1900{
ce453d81 1901 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1902 u32 alignment;
1903 int ret;
1904
05394f39 1905 switch (obj->tiling_mode) {
6b95a207 1906 case I915_TILING_NONE:
534843da
CW		 1907 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908 alignment = 128 * 1024;
a6c45cf0 1909 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1910 alignment = 4 * 1024;
1911 else
1912 alignment = 64 * 1024;
6b95a207
KH		 1913 break;
1914 case I915_TILING_X:
1915 /* pin() will align the object as required by fence */
1916 alignment = 0;
1917 break;
1918 case I915_TILING_Y:
1919 /* FIXME: Is this true? */
1920 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1921 return -EINVAL;
1922 default:
1923 BUG();
1924 }
1925
ce453d81 1926 dev_priv->mm.interruptible = false;
2da3b9b9 1927 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1928 if (ret)
ce453d81 1929 goto err_interruptible;
6b95a207
KH		 1930
1931 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932 * fence, whereas 965+ only requires a fence if using
1933 * framebuffer compression. For simplicity, we always install
1934 * a fence as the cost is not that onerous.
1935 */
06d98131 1936 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1937 if (ret)
1938 goto err_unpin;
1690e1eb 1939
9a5a53b3 1940 i915_gem_object_pin_fence(obj);
6b95a207 1941
ce453d81 1942 dev_priv->mm.interruptible = true;
6b95a207 1943 return 0;
48b956c5
CW		 1944
1945err_unpin:
1946 i915_gem_object_unpin(obj);
ce453d81
CW		 1947err_interruptible:
1948 dev_priv->mm.interruptible = true;
48b956c5 1949 return ret;
6b95a207
KH		 1950}
1951
1690e1eb
CW		 1952void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953{
1954 i915_gem_object_unpin_fence(obj);
1955 i915_gem_object_unpin(obj);
1956}
1957
c2c75131
DV		 1958/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959 * is assumed to be a power-of-two. */
5a35e99e
DL		 1960unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1961 unsigned int bpp,
1962 unsigned int pitch)
c2c75131
DV		 1963{
1964 int tile_rows, tiles;
1965
1966 tile_rows = *y / 8;
1967 *y %= 8;
1968 tiles = *x / (512/bpp);
1969 *x %= 512/bpp;
1970
1971 return tile_rows * pitch * 8 + tiles * 4096;
1972}
1973
17638cd6
JB		 1974static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975 int x, int y)
81255565
JB		 1976{
1977 struct drm_device *dev = crtc->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 struct intel_framebuffer *intel_fb;
05394f39 1981 struct drm_i915_gem_object *obj;
81255565 1982 int plane = intel_crtc->plane;
e506a0c6 1983 unsigned long linear_offset;
81255565 1984 u32 dspcntr;
5eddb70b 1985 u32 reg;
81255565
JB		 1986
1987 switch (plane) {
1988 case 0:
1989 case 1:
1990 break;
1991 default:
1992 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1993 return -EINVAL;
1994 }
1995
1996 intel_fb = to_intel_framebuffer(fb);
1997 obj = intel_fb->obj;
81255565 1998
5eddb70b
CW		 1999 reg = DSPCNTR(plane);
2000 dspcntr = I915_READ(reg);
81255565
JB		 2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2003 switch (fb->bits_per_pixel) {
2004 case 8:
2005 dspcntr |= DISPPLANE_8BPP;
2006 break;
2007 case 16:
2008 if (fb->depth == 15)
2009 dspcntr |= DISPPLANE_15_16BPP;
2010 else
2011 dspcntr |= DISPPLANE_16BPP;
2012 break;
2013 case 24:
2014 case 32:
2015 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2016 break;
2017 default:
17638cd6 2018 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2019 return -EINVAL;
2020 }
a6c45cf0 2021 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2022 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2023 dspcntr |= DISPPLANE_TILED;
2024 else
2025 dspcntr &= ~DISPPLANE_TILED;
2026 }
2027
5eddb70b 2028 I915_WRITE(reg, dspcntr);
81255565 2029
e506a0c6 2030 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2031
c2c75131
DV		 2032 if (INTEL_INFO(dev)->gen >= 4) {
2033 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2034 intel_gen4_compute_offset_xtiled(&x, &y,
2035 fb->bits_per_pixel / 8,
2036 fb->pitches[0]);
c2c75131
DV		 2037 linear_offset -= intel_crtc->dspaddr_offset;
2038 } else {
e506a0c6 2039 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2040 }
e506a0c6
DV		 2041
2042 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2043 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2044 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2045 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2046 I915_MODIFY_DISPBASE(DSPSURF(plane),
2047 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2048 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2049 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2050 } else
e506a0c6 2051 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2052 POSTING_READ(reg);
81255565 2053
17638cd6
JB		 2054 return 0;
2055}
2056
2057static int ironlake_update_plane(struct drm_crtc *crtc,
2058 struct drm_framebuffer *fb, int x, int y)
2059{
2060 struct drm_device *dev = crtc->dev;
2061 struct drm_i915_private *dev_priv = dev->dev_private;
2062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2063 struct intel_framebuffer *intel_fb;
2064 struct drm_i915_gem_object *obj;
2065 int plane = intel_crtc->plane;
e506a0c6 2066 unsigned long linear_offset;
17638cd6
JB		 2067 u32 dspcntr;
2068 u32 reg;
2069
2070 switch (plane) {
2071 case 0:
2072 case 1:
27f8227b 2073 case 2:
17638cd6
JB		 2074 break;
2075 default:
2076 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2077 return -EINVAL;
2078 }
2079
2080 intel_fb = to_intel_framebuffer(fb);
2081 obj = intel_fb->obj;
2082
2083 reg = DSPCNTR(plane);
2084 dspcntr = I915_READ(reg);
2085 /* Mask out pixel format bits in case we change it */
2086 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2087 switch (fb->bits_per_pixel) {
2088 case 8:
2089 dspcntr |= DISPPLANE_8BPP;
2090 break;
2091 case 16:
2092 if (fb->depth != 16)
2093 return -EINVAL;
2094
2095 dspcntr |= DISPPLANE_16BPP;
2096 break;
2097 case 24:
2098 case 32:
2099 if (fb->depth == 24)
2100 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2101 else if (fb->depth == 30)
2102 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2103 else
2104 return -EINVAL;
2105 break;
2106 default:
2107 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2108 return -EINVAL;
2109 }
2110
2111 if (obj->tiling_mode != I915_TILING_NONE)
2112 dspcntr |= DISPPLANE_TILED;
2113 else
2114 dspcntr &= ~DISPPLANE_TILED;
2115
2116 /* must disable */
2117 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2118
2119 I915_WRITE(reg, dspcntr);
2120
e506a0c6 2121 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2122 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2123 intel_gen4_compute_offset_xtiled(&x, &y,
2124 fb->bits_per_pixel / 8,
2125 fb->pitches[0]);
c2c75131 2126 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2127
e506a0c6
DV		 2128 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2129 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2130 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2131 I915_MODIFY_DISPBASE(DSPSURF(plane),
2132 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2133 if (IS_HASWELL(dev)) {
2134 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2135 } else {
2136 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2137 I915_WRITE(DSPLINOFF(plane), linear_offset);
2138 }
17638cd6
JB		 2139 POSTING_READ(reg);
2140
2141 return 0;
2142}
2143
2144/* Assume fb object is pinned & idle & fenced and just update base pointers */
2145static int
2146intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2147 int x, int y, enum mode_set_atomic state)
2148{
2149 struct drm_device *dev = crtc->dev;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2151
6b8e6ed0
CW		 2152 if (dev_priv->display.disable_fbc)
2153 dev_priv->display.disable_fbc(dev);
3dec0095 2154 intel_increase_pllclock(crtc);
81255565 2155
6b8e6ed0 2156 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2157}
2158
14667a4b
CW		 2159static int
2160intel_finish_fb(struct drm_framebuffer *old_fb)
2161{
2162 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2163 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2164 bool was_interruptible = dev_priv->mm.interruptible;
2165 int ret;
2166
2167 wait_event(dev_priv->pending_flip_queue,
2168 atomic_read(&dev_priv->mm.wedged) ||
2169 atomic_read(&obj->pending_flip) == 0);
2170
2171 /* Big Hammer, we also need to ensure that any pending
2172 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2173 * current scanout is retired before unpinning the old
2174 * framebuffer.
2175 *
2176 * This should only fail upon a hung GPU, in which case we
2177 * can safely continue.
2178 */
2179 dev_priv->mm.interruptible = false;
2180 ret = i915_gem_object_finish_gpu(obj);
2181 dev_priv->mm.interruptible = was_interruptible;
2182
2183 return ret;
2184}
2185
5c3b82e2 2186static int
3c4fdcfb 2187intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2188 struct drm_framebuffer *fb)
79e53945
JB		 2189{
2190 struct drm_device *dev = crtc->dev;
6b8e6ed0 2191 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2192 struct drm_i915_master_private *master_priv;
2193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2194 struct drm_framebuffer *old_fb;
5c3b82e2 2195 int ret;
79e53945
JB		 2196
2197 /* no fb bound */
94352cf9 2198 if (!fb) {
a5071c2f 2199 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2200 return 0;
2201 }
2202
5826eca5
ED		 2203 if(intel_crtc->plane > dev_priv->num_pipe) {
2204 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2205 intel_crtc->plane,
2206 dev_priv->num_pipe);
5c3b82e2 2207 return -EINVAL;
79e53945
JB		 2208 }
2209
5c3b82e2 2210 mutex_lock(&dev->struct_mutex);
265db958 2211 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2212 to_intel_framebuffer(fb)->obj,
919926ae 2213 NULL);
5c3b82e2
CW		 2214 if (ret != 0) {
2215 mutex_unlock(&dev->struct_mutex);
a5071c2f 2216 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2217 return ret;
2218 }
79e53945 2219
94352cf9
DV		 2220 if (crtc->fb)
2221 intel_finish_fb(crtc->fb);
265db958 2222
94352cf9 2223 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2224 if (ret) {
94352cf9 2225 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2226 mutex_unlock(&dev->struct_mutex);
a5071c2f 2227 DRM_ERROR("failed to update base address\n");
4e6cfefc 2228 return ret;
79e53945 2229 }
3c4fdcfb 2230
94352cf9
DV		 2231 old_fb = crtc->fb;
2232 crtc->fb = fb;
6c4c86f5
DV		 2233 crtc->x = x;
2234 crtc->y = y;
94352cf9 2235
b7f1de28
CW		 2236 if (old_fb) {
2237 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2238 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2239 }
652c393a 2240
6b8e6ed0 2241 intel_update_fbc(dev);
5c3b82e2 2242 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2243
2244 if (!dev->primary->master)
5c3b82e2 2245 return 0;
79e53945
JB		 2246
2247 master_priv = dev->primary->master->driver_priv;
2248 if (!master_priv->sarea_priv)
5c3b82e2 2249 return 0;
79e53945 2250
265db958 2251 if (intel_crtc->pipe) {
79e53945
JB		 2252 master_priv->sarea_priv->pipeB_x = x;
2253 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2254 } else {
2255 master_priv->sarea_priv->pipeA_x = x;
2256 master_priv->sarea_priv->pipeA_y = y;
79e53945 2257 }
5c3b82e2
CW		 2258
2259 return 0;
79e53945
JB		 2260}
2261
5eddb70b 2262static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2263{
2264 struct drm_device *dev = crtc->dev;
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 u32 dpa_ctl;
2267
28c97730 2268 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2269 dpa_ctl = I915_READ(DP_A);
2270 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2271
2272 if (clock < 200000) {
2273 u32 temp;
2274 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2275 /* workaround for 160Mhz:
2276 1) program 0x4600c bits 15:0 = 0x8124
2277 2) program 0x46010 bit 0 = 1
2278 3) program 0x46034 bit 24 = 1
2279 4) program 0x64000 bit 14 = 1
2280 */
2281 temp = I915_READ(0x4600c);
2282 temp &= 0xffff0000;
2283 I915_WRITE(0x4600c, temp | 0x8124);
2284
2285 temp = I915_READ(0x46010);
2286 I915_WRITE(0x46010, temp | 1);
2287
2288 temp = I915_READ(0x46034);
2289 I915_WRITE(0x46034, temp | (1 << 24));
2290 } else {
2291 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2292 }
2293 I915_WRITE(DP_A, dpa_ctl);
2294
5eddb70b 2295 POSTING_READ(DP_A);
32f9d658
ZW		 2296 udelay(500);
2297}
2298
5e84e1a4
ZW		 2299static void intel_fdi_normal_train(struct drm_crtc *crtc)
2300{
2301 struct drm_device *dev = crtc->dev;
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2304 int pipe = intel_crtc->pipe;
2305 u32 reg, temp;
2306
2307 /* enable normal train */
2308 reg = FDI_TX_CTL(pipe);
2309 temp = I915_READ(reg);
61e499bf 2310 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2311 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2312 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2313 } else {
2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2316 }
5e84e1a4
ZW		 2317 I915_WRITE(reg, temp);
2318
2319 reg = FDI_RX_CTL(pipe);
2320 temp = I915_READ(reg);
2321 if (HAS_PCH_CPT(dev)) {
2322 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2323 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2324 } else {
2325 temp &= ~FDI_LINK_TRAIN_NONE;
2326 temp |= FDI_LINK_TRAIN_NONE;
2327 }
2328 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2329
2330 /* wait one idle pattern time */
2331 POSTING_READ(reg);
2332 udelay(1000);
357555c0
JB		 2333
2334 /* IVB wants error correction enabled */
2335 if (IS_IVYBRIDGE(dev))
2336 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2337 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2338}
2339
291427f5
JB		 2340static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2341{
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 u32 flags = I915_READ(SOUTH_CHICKEN1);
2344
2345 flags |= FDI_PHASE_SYNC_OVR(pipe);
2346 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2347 flags |= FDI_PHASE_SYNC_EN(pipe);
2348 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2349 POSTING_READ(SOUTH_CHICKEN1);
2350}
2351
01a415fd
DV		 2352static void ivb_modeset_global_resources(struct drm_device *dev)
2353{
2354 struct drm_i915_private *dev_priv = dev->dev_private;
2355 struct intel_crtc *pipe_B_crtc =
2356 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2357 struct intel_crtc *pipe_C_crtc =
2358 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2359 uint32_t temp;
2360
2361 /* When everything is off disable fdi C so that we could enable fdi B
2362 * with all lanes. XXX: This misses the case where a pipe is not using
2363 * any pch resources and so doesn't need any fdi lanes. */
2364 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2365 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2366 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2367
2368 temp = I915_READ(SOUTH_CHICKEN1);
2369 temp &= ~FDI_BC_BIFURCATION_SELECT;
2370 DRM_DEBUG_KMS("disabling fdi C rx\n");
2371 I915_WRITE(SOUTH_CHICKEN1, temp);
2372 }
2373}
2374
8db9d77b
ZW		 2375/* The FDI link training functions for ILK/Ibexpeak. */
2376static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2377{
2378 struct drm_device *dev = crtc->dev;
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2381 int pipe = intel_crtc->pipe;
0fc932b8 2382 int plane = intel_crtc->plane;
5eddb70b 2383 u32 reg, temp, tries;
8db9d77b 2384
0fc932b8
JB		 2385 /* FDI needs bits from pipe & plane first */
2386 assert_pipe_enabled(dev_priv, pipe);
2387 assert_plane_enabled(dev_priv, plane);
2388
e1a44743
AJ		 2389 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2390 for train result */
5eddb70b
CW		 2391 reg = FDI_RX_IMR(pipe);
2392 temp = I915_READ(reg);
e1a44743
AJ		 2393 temp &= ~FDI_RX_SYMBOL_LOCK;
2394 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2395 I915_WRITE(reg, temp);
2396 I915_READ(reg);
e1a44743
AJ		 2397 udelay(150);
2398
8db9d77b 2399 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2400 reg = FDI_TX_CTL(pipe);
2401 temp = I915_READ(reg);
77ffb597
AJ		 2402 temp &= ~(7 << 19);
2403 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2404 temp &= ~FDI_LINK_TRAIN_NONE;
2405 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2407
5eddb70b
CW		 2408 reg = FDI_RX_CTL(pipe);
2409 temp = I915_READ(reg);
8db9d77b
ZW		 2410 temp &= ~FDI_LINK_TRAIN_NONE;
2411 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2412 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2413
2414 POSTING_READ(reg);
8db9d77b
ZW		 2415 udelay(150);
2416
5b2adf89 2417 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2418 if (HAS_PCH_IBX(dev)) {
2419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2420 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2421 FDI_RX_PHASE_SYNC_POINTER_EN);
2422 }
5b2adf89 2423
5eddb70b 2424 reg = FDI_RX_IIR(pipe);
e1a44743 2425 for (tries = 0; tries < 5; tries++) {
5eddb70b 2426 temp = I915_READ(reg);
8db9d77b
ZW		 2427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2428
2429 if ((temp & FDI_RX_BIT_LOCK)) {
2430 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2431 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2432 break;
2433 }
8db9d77b 2434 }
e1a44743 2435 if (tries == 5)
5eddb70b 2436 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2437
2438 /* Train 2 */
5eddb70b
CW		 2439 reg = FDI_TX_CTL(pipe);
2440 temp = I915_READ(reg);
8db9d77b
ZW		 2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2443 I915_WRITE(reg, temp);
8db9d77b 2444
5eddb70b
CW		 2445 reg = FDI_RX_CTL(pipe);
2446 temp = I915_READ(reg);
8db9d77b
ZW		 2447 temp &= ~FDI_LINK_TRAIN_NONE;
2448 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2449 I915_WRITE(reg, temp);
8db9d77b 2450
5eddb70b
CW		 2451 POSTING_READ(reg);
2452 udelay(150);
8db9d77b 2453
5eddb70b 2454 reg = FDI_RX_IIR(pipe);
e1a44743 2455 for (tries = 0; tries < 5; tries++) {
5eddb70b 2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2458
2459 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2460 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2461 DRM_DEBUG_KMS("FDI train 2 done.\n");
2462 break;
2463 }
8db9d77b 2464 }
e1a44743 2465 if (tries == 5)
5eddb70b 2466 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2467
2468 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2469
8db9d77b
ZW		 2470}
2471
0206e353 2472static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2473 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2474 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2475 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2476 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2477};
2478
2479/* The FDI link training functions for SNB/Cougarpoint. */
2480static void gen6_fdi_link_train(struct drm_crtc *crtc)
2481{
2482 struct drm_device *dev = crtc->dev;
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2485 int pipe = intel_crtc->pipe;
fa37d39e 2486 u32 reg, temp, i, retry;
8db9d77b 2487
e1a44743
AJ		 2488 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2489 for train result */
5eddb70b
CW		 2490 reg = FDI_RX_IMR(pipe);
2491 temp = I915_READ(reg);
e1a44743
AJ		 2492 temp &= ~FDI_RX_SYMBOL_LOCK;
2493 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2494 I915_WRITE(reg, temp);
2495
2496 POSTING_READ(reg);
e1a44743
AJ		 2497 udelay(150);
2498
8db9d77b 2499 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2500 reg = FDI_TX_CTL(pipe);
2501 temp = I915_READ(reg);
77ffb597
AJ		 2502 temp &= ~(7 << 19);
2503 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2507 /* SNB-B */
2508 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2509 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2510
d74cf324
DV		 2511 I915_WRITE(FDI_RX_MISC(pipe),
2512 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2513
5eddb70b
CW		 2514 reg = FDI_RX_CTL(pipe);
2515 temp = I915_READ(reg);
8db9d77b
ZW		 2516 if (HAS_PCH_CPT(dev)) {
2517 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2518 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2519 } else {
2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_1;
2522 }
5eddb70b
CW		 2523 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2524
2525 POSTING_READ(reg);
8db9d77b
ZW		 2526 udelay(150);
2527
291427f5
JB		 2528 if (HAS_PCH_CPT(dev))
2529 cpt_phase_pointer_enable(dev, pipe);
2530
0206e353 2531 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2532 reg = FDI_TX_CTL(pipe);
2533 temp = I915_READ(reg);
8db9d77b
ZW		 2534 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2535 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2536 I915_WRITE(reg, temp);
2537
2538 POSTING_READ(reg);
8db9d77b
ZW		 2539 udelay(500);
2540
fa37d39e
SP		 2541 for (retry = 0; retry < 5; retry++) {
2542 reg = FDI_RX_IIR(pipe);
2543 temp = I915_READ(reg);
2544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545 if (temp & FDI_RX_BIT_LOCK) {
2546 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2547 DRM_DEBUG_KMS("FDI train 1 done.\n");
2548 break;
2549 }
2550 udelay(50);
8db9d77b 2551 }
fa37d39e
SP		 2552 if (retry < 5)
2553 break;
8db9d77b
ZW		 2554 }
2555 if (i == 4)
5eddb70b 2556 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2557
2558 /* Train 2 */
5eddb70b
CW		 2559 reg = FDI_TX_CTL(pipe);
2560 temp = I915_READ(reg);
8db9d77b
ZW		 2561 temp &= ~FDI_LINK_TRAIN_NONE;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2;
2563 if (IS_GEN6(dev)) {
2564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565 /* SNB-B */
2566 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2567 }
5eddb70b 2568 I915_WRITE(reg, temp);
8db9d77b 2569
5eddb70b
CW		 2570 reg = FDI_RX_CTL(pipe);
2571 temp = I915_READ(reg);
8db9d77b
ZW		 2572 if (HAS_PCH_CPT(dev)) {
2573 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2574 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2575 } else {
2576 temp &= ~FDI_LINK_TRAIN_NONE;
2577 temp |= FDI_LINK_TRAIN_PATTERN_2;
2578 }
5eddb70b
CW		 2579 I915_WRITE(reg, temp);
2580
2581 POSTING_READ(reg);
8db9d77b
ZW		 2582 udelay(150);
2583
0206e353 2584 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2585 reg = FDI_TX_CTL(pipe);
2586 temp = I915_READ(reg);
8db9d77b
ZW		 2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2589 I915_WRITE(reg, temp);
2590
2591 POSTING_READ(reg);
8db9d77b
ZW		 2592 udelay(500);
2593
fa37d39e
SP		 2594 for (retry = 0; retry < 5; retry++) {
2595 reg = FDI_RX_IIR(pipe);
2596 temp = I915_READ(reg);
2597 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2598 if (temp & FDI_RX_SYMBOL_LOCK) {
2599 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2600 DRM_DEBUG_KMS("FDI train 2 done.\n");
2601 break;
2602 }
2603 udelay(50);
8db9d77b 2604 }
fa37d39e
SP		 2605 if (retry < 5)
2606 break;
8db9d77b
ZW		 2607 }
2608 if (i == 4)
5eddb70b 2609 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2610
2611 DRM_DEBUG_KMS("FDI train done.\n");
2612}
2613
357555c0
JB		 2614/* Manual link training for Ivy Bridge A0 parts */
2615static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2616{
2617 struct drm_device *dev = crtc->dev;
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2620 int pipe = intel_crtc->pipe;
2621 u32 reg, temp, i;
2622
2623 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2624 for train result */
2625 reg = FDI_RX_IMR(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~FDI_RX_SYMBOL_LOCK;
2628 temp &= ~FDI_RX_BIT_LOCK;
2629 I915_WRITE(reg, temp);
2630
2631 POSTING_READ(reg);
2632 udelay(150);
2633
01a415fd
DV		 2634 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2635 I915_READ(FDI_RX_IIR(pipe)));
2636
357555c0
JB		 2637 /* enable CPU FDI TX and PCH FDI RX */
2638 reg = FDI_TX_CTL(pipe);
2639 temp = I915_READ(reg);
2640 temp &= ~(7 << 19);
2641 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2642 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2643 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2646 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2647 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2648
d74cf324
DV		 2649 I915_WRITE(FDI_RX_MISC(pipe),
2650 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2651
357555c0
JB		 2652 reg = FDI_RX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_AUTO;
2655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2657 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2658 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2659
2660 POSTING_READ(reg);
2661 udelay(150);
2662
291427f5
JB		 2663 if (HAS_PCH_CPT(dev))
2664 cpt_phase_pointer_enable(dev, pipe);
2665
0206e353 2666 for (i = 0; i < 4; i++) {
357555c0
JB		 2667 reg = FDI_TX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2670 temp |= snb_b_fdi_train_param[i];
2671 I915_WRITE(reg, temp);
2672
2673 POSTING_READ(reg);
2674 udelay(500);
2675
2676 reg = FDI_RX_IIR(pipe);
2677 temp = I915_READ(reg);
2678 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2679
2680 if (temp & FDI_RX_BIT_LOCK ||
2681 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2682 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2683 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2684 break;
2685 }
2686 }
2687 if (i == 4)
2688 DRM_ERROR("FDI train 1 fail!\n");
2689
2690 /* Train 2 */
2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2694 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2695 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2696 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2697 I915_WRITE(reg, temp);
2698
2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2702 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2703 I915_WRITE(reg, temp);
2704
2705 POSTING_READ(reg);
2706 udelay(150);
2707
0206e353 2708 for (i = 0; i < 4; i++) {
357555c0
JB		 2709 reg = FDI_TX_CTL(pipe);
2710 temp = I915_READ(reg);
2711 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2712 temp |= snb_b_fdi_train_param[i];
2713 I915_WRITE(reg, temp);
2714
2715 POSTING_READ(reg);
2716 udelay(500);
2717
2718 reg = FDI_RX_IIR(pipe);
2719 temp = I915_READ(reg);
2720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2721
2722 if (temp & FDI_RX_SYMBOL_LOCK) {
2723 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2724 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2725 break;
2726 }
2727 }
2728 if (i == 4)
2729 DRM_ERROR("FDI train 2 fail!\n");
2730
2731 DRM_DEBUG_KMS("FDI train done.\n");
2732}
2733
88cefb6c 2734static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2735{
88cefb6c 2736 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2737 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2738 int pipe = intel_crtc->pipe;
5eddb70b 2739 u32 reg, temp;
79e53945 2740
c64e311e 2741
c98e9dcf 2742 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2743 reg = FDI_RX_CTL(pipe);
2744 temp = I915_READ(reg);
2745 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2746 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2747 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2748 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2749
2750 POSTING_READ(reg);
c98e9dcf
JB		 2751 udelay(200);
2752
2753 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2754 temp = I915_READ(reg);
2755 I915_WRITE(reg, temp | FDI_PCDCLK);
2756
2757 POSTING_READ(reg);
c98e9dcf
JB		 2758 udelay(200);
2759
bf507ef7
ED		 2760 /* On Haswell, the PLL configuration for ports and pipes is handled
2761 * separately, as part of DDI setup */
2762 if (!IS_HASWELL(dev)) {
2763 /* Enable CPU FDI TX PLL, always on for Ironlake */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2767 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2768
bf507ef7
ED		 2769 POSTING_READ(reg);
2770 udelay(100);
2771 }
6be4a607 2772 }
0e23b99d
JB		 2773}
2774
88cefb6c
DV		 2775static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2776{
2777 struct drm_device *dev = intel_crtc->base.dev;
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 int pipe = intel_crtc->pipe;
2780 u32 reg, temp;
2781
2782 /* Switch from PCDclk to Rawclk */
2783 reg = FDI_RX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2786
2787 /* Disable CPU FDI TX PLL */
2788 reg = FDI_TX_CTL(pipe);
2789 temp = I915_READ(reg);
2790 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2791
2792 POSTING_READ(reg);
2793 udelay(100);
2794
2795 reg = FDI_RX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2798
2799 /* Wait for the clocks to turn off. */
2800 POSTING_READ(reg);
2801 udelay(100);
2802}
2803
291427f5
JB		 2804static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2805{
2806 struct drm_i915_private *dev_priv = dev->dev_private;
2807 u32 flags = I915_READ(SOUTH_CHICKEN1);
2808
2809 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2810 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2811 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2812 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2813 POSTING_READ(SOUTH_CHICKEN1);
2814}
0fc932b8
JB		 2815static void ironlake_fdi_disable(struct drm_crtc *crtc)
2816{
2817 struct drm_device *dev = crtc->dev;
2818 struct drm_i915_private *dev_priv = dev->dev_private;
2819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2820 int pipe = intel_crtc->pipe;
2821 u32 reg, temp;
2822
2823 /* disable CPU FDI tx and PCH FDI rx */
2824 reg = FDI_TX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2827 POSTING_READ(reg);
2828
2829 reg = FDI_RX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 temp &= ~(0x7 << 16);
2832 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2833 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2834
2835 POSTING_READ(reg);
2836 udelay(100);
2837
2838 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2839 if (HAS_PCH_IBX(dev)) {
2840 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2841 I915_WRITE(FDI_RX_CHICKEN(pipe),
2842 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2843 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2844 } else if (HAS_PCH_CPT(dev)) {
2845 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2846 }
0fc932b8
JB		 2847
2848 /* still set train pattern 1 */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
2853 I915_WRITE(reg, temp);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860 } else {
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863 }
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp &= ~(0x07 << 16);
2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2867 I915_WRITE(reg, temp);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871}
2872
5bb61643
CW		 2873static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874{
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 unsigned long flags;
2878 bool pending;
2879
2880 if (atomic_read(&dev_priv->mm.wedged))
2881 return false;
2882
2883 spin_lock_irqsave(&dev->event_lock, flags);
2884 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2885 spin_unlock_irqrestore(&dev->event_lock, flags);
2886
2887 return pending;
2888}
2889
e6c3a2a6
CW		 2890static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2891{
0f91128d 2892 struct drm_device *dev = crtc->dev;
5bb61643 2893 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2894
2895 if (crtc->fb == NULL)
2896 return;
2897
5bb61643
CW		 2898 wait_event(dev_priv->pending_flip_queue,
2899 !intel_crtc_has_pending_flip(crtc));
2900
0f91128d
CW		 2901 mutex_lock(&dev->struct_mutex);
2902 intel_finish_fb(crtc->fb);
2903 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2904}
2905
fc316cbe 2906static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2907{
2908 struct drm_device *dev = crtc->dev;
228d3e36 2909 struct intel_encoder *intel_encoder;
040484af
JB		 2910
2911 /*
2912 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2913 * must be driven by its own crtc; no sharing is possible.
2914 */
228d3e36 2915 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2916 switch (intel_encoder->type) {
040484af 2917 case INTEL_OUTPUT_EDP:
228d3e36 2918 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2919 return false;
2920 continue;
2921 }
2922 }
2923
2924 return true;
2925}
2926
fc316cbe
PZ		 2927static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2928{
2929 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2930}
2931
e615efe4
ED		 2932/* Program iCLKIP clock to the desired frequency */
2933static void lpt_program_iclkip(struct drm_crtc *crtc)
2934{
2935 struct drm_device *dev = crtc->dev;
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2938 u32 temp;
2939
2940 /* It is necessary to ungate the pixclk gate prior to programming
2941 * the divisors, and gate it back when it is done.
2942 */
2943 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2944
2945 /* Disable SSCCTL */
2946 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2947 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2948 SBI_SSCCTL_DISABLE);
2949
2950 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2951 if (crtc->mode.clock == 20000) {
2952 auxdiv = 1;
2953 divsel = 0x41;
2954 phaseinc = 0x20;
2955 } else {
2956 /* The iCLK virtual clock root frequency is in MHz,
2957 * but the crtc->mode.clock in in KHz. To get the divisors,
2958 * it is necessary to divide one by another, so we
2959 * convert the virtual clock precision to KHz here for higher
2960 * precision.
2961 */
2962 u32 iclk_virtual_root_freq = 172800 * 1000;
2963 u32 iclk_pi_range = 64;
2964 u32 desired_divisor, msb_divisor_value, pi_value;
2965
2966 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2967 msb_divisor_value = desired_divisor / iclk_pi_range;
2968 pi_value = desired_divisor % iclk_pi_range;
2969
2970 auxdiv = 0;
2971 divsel = msb_divisor_value - 2;
2972 phaseinc = pi_value;
2973 }
2974
2975 /* This should not happen with any sane values */
2976 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2977 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2978 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2979 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2980
2981 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2982 crtc->mode.clock,
2983 auxdiv,
2984 divsel,
2985 phasedir,
2986 phaseinc);
2987
2988 /* Program SSCDIVINTPHASE6 */
2989 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2990 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2991 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2992 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2993 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2994 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2995 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2996
2997 intel_sbi_write(dev_priv,
2998 SBI_SSCDIVINTPHASE6,
2999 temp);
3000
3001 /* Program SSCAUXDIV */
3002 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3003 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3004 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3005 intel_sbi_write(dev_priv,
3006 SBI_SSCAUXDIV6,
3007 temp);
3008
3009
3010 /* Enable modulator and associated divider */
3011 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3012 temp &= ~SBI_SSCCTL_DISABLE;
3013 intel_sbi_write(dev_priv,
3014 SBI_SSCCTL6,
3015 temp);
3016
3017 /* Wait for initialization time */
3018 udelay(24);
3019
3020 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3021}
3022
f67a559d
JB		 3023/*
3024 * Enable PCH resources required for PCH ports:
3025 * - PCH PLLs
3026 * - FDI training & RX/TX
3027 * - update transcoder timings
3028 * - DP transcoding bits
3029 * - transcoder
3030 */
3031static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3032{
3033 struct drm_device *dev = crtc->dev;
3034 struct drm_i915_private *dev_priv = dev->dev_private;
3035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3036 int pipe = intel_crtc->pipe;
ee7b9f93 3037 u32 reg, temp;
2c07245f 3038
e7e164db
CW		 3039 assert_transcoder_disabled(dev_priv, pipe);
3040
cd986abb
DV		 3041 /* Write the TU size bits before fdi link training, so that error
3042 * detection works. */
3043 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3044 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3045
c98e9dcf 3046 /* For PCH output, training FDI link */
674cf967 3047 dev_priv->display.fdi_link_train(crtc);
2c07245f 3048
572deb37
DV		 3049 /* XXX: pch pll's can be enabled any time before we enable the PCH
3050 * transcoder, and we actually should do this to not upset any PCH
3051 * transcoder that already use the clock when we share it.
3052 *
3053 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3054 * unconditionally resets the pll - we need that to have the right LVDS
3055 * enable sequence. */
6f13b7b5
CW		 3056 intel_enable_pch_pll(intel_crtc);
3057
e615efe4
ED		 3058 if (HAS_PCH_LPT(dev)) {
3059 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3060 lpt_program_iclkip(crtc);
3061 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3062 u32 sel;
4b645f14 3063
c98e9dcf 3064 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3065 switch (pipe) {
3066 default:
3067 case 0:
3068 temp |= TRANSA_DPLL_ENABLE;
3069 sel = TRANSA_DPLLB_SEL;
3070 break;
3071 case 1:
3072 temp |= TRANSB_DPLL_ENABLE;
3073 sel = TRANSB_DPLLB_SEL;
3074 break;
3075 case 2:
3076 temp |= TRANSC_DPLL_ENABLE;
3077 sel = TRANSC_DPLLB_SEL;
3078 break;
d64311ab 3079 }
ee7b9f93
JB		 3080 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3081 temp |= sel;
3082 else
3083 temp &= ~sel;
c98e9dcf 3084 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3085 }
5eddb70b 3086
d9b6cb56
JB		 3087 /* set transcoder timing, panel must allow it */
3088 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3089 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3090 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3091 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3092
5eddb70b
CW		 3093 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3094 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3095 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3096 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3097
f57e1e3a
ED		 3098 if (!IS_HASWELL(dev))
3099 intel_fdi_normal_train(crtc);
5e84e1a4 3100
c98e9dcf
JB		 3101 /* For PCH DP, enable TRANS_DP_CTL */
3102 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3103 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3104 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3105 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3106 reg = TRANS_DP_CTL(pipe);
3107 temp = I915_READ(reg);
3108 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3109 TRANS_DP_SYNC_MASK |
3110 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3111 temp |= (TRANS_DP_OUTPUT_ENABLE |
3112 TRANS_DP_ENH_FRAMING);
9325c9f0 3113 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3114
3115 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3116 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3117 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3118 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3119
3120 switch (intel_trans_dp_port_sel(crtc)) {
3121 case PCH_DP_B:
5eddb70b 3122 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3123 break;
3124 case PCH_DP_C:
5eddb70b 3125 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3126 break;
3127 case PCH_DP_D:
5eddb70b 3128 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3129 break;
3130 default:
e95d41e1 3131 BUG();
32f9d658 3132 }
2c07245f 3133
5eddb70b 3134 I915_WRITE(reg, temp);
6be4a607 3135 }
b52eb4dc 3136
040484af 3137 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3138}
3139
ee7b9f93
JB		 3140static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3141{
3142 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3143
3144 if (pll == NULL)
3145 return;
3146
3147 if (pll->refcount == 0) {
3148 WARN(1, "bad PCH PLL refcount\n");
3149 return;
3150 }
3151
3152 --pll->refcount;
3153 intel_crtc->pch_pll = NULL;
3154}
3155
3156static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3157{
3158 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3159 struct intel_pch_pll *pll;
3160 int i;
3161
3162 pll = intel_crtc->pch_pll;
3163 if (pll) {
3164 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3165 intel_crtc->base.base.id, pll->pll_reg);
3166 goto prepare;
3167 }
3168
98b6bd99
DV		 3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3171 i = intel_crtc->pipe;
3172 pll = &dev_priv->pch_plls[i];
3173
3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3175 intel_crtc->base.base.id, pll->pll_reg);
3176
3177 goto found;
3178 }
3179
ee7b9f93
JB		 3180 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3181 pll = &dev_priv->pch_plls[i];
3182
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3185 continue;
3186
3187 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3188 fp == I915_READ(pll->fp0_reg)) {
3189 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3190 intel_crtc->base.base.id,
3191 pll->pll_reg, pll->refcount, pll->active);
3192
3193 goto found;
3194 }
3195 }
3196
3197 /* Ok no matching timings, maybe there's a free one? */
3198 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3199 pll = &dev_priv->pch_plls[i];
3200 if (pll->refcount == 0) {
3201 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3202 intel_crtc->base.base.id, pll->pll_reg);
3203 goto found;
3204 }
3205 }
3206
3207 return NULL;
3208
3209found:
3210 intel_crtc->pch_pll = pll;
3211 pll->refcount++;
3212 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3213prepare: /* separate function? */
3214 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3215
e04c7350
CW		 3216 /* Wait for the clocks to stabilize before rewriting the regs */
3217 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3218 POSTING_READ(pll->pll_reg);
3219 udelay(150);
e04c7350
CW		 3220
3221 I915_WRITE(pll->fp0_reg, fp);
3222 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3223 pll->on = false;
3224 return pll;
3225}
3226
d4270e57
JB		 3227void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3228{
3229 struct drm_i915_private *dev_priv = dev->dev_private;
3230 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3231 u32 temp;
3232
3233 temp = I915_READ(dslreg);
3234 udelay(500);
3235 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3236 /* Without this, mode sets may fail silently on FDI */
3237 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3238 udelay(250);
3239 I915_WRITE(tc2reg, 0);
3240 if (wait_for(I915_READ(dslreg) != temp, 5))
3241 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3242 }
3243}
3244
f67a559d
JB		 3245static void ironlake_crtc_enable(struct drm_crtc *crtc)
3246{
3247 struct drm_device *dev = crtc->dev;
3248 struct drm_i915_private *dev_priv = dev->dev_private;
3249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3250 struct intel_encoder *encoder;
f67a559d
JB		 3251 int pipe = intel_crtc->pipe;
3252 int plane = intel_crtc->plane;
3253 u32 temp;
3254 bool is_pch_port;
3255
08a48469
DV		 3256 WARN_ON(!crtc->enabled);
3257
f67a559d
JB		 3258 if (intel_crtc->active)
3259 return;
3260
3261 intel_crtc->active = true;
3262 intel_update_watermarks(dev);
3263
3264 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3265 temp = I915_READ(PCH_LVDS);
3266 if ((temp & LVDS_PORT_EN) == 0)
3267 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3268 }
3269
fc316cbe 3270 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3271
46b6f814 3272 if (is_pch_port) {
fff367c7
DV		 3273 /* Note: FDI PLL enabling _must_ be done before we enable the
3274 * cpu pipes, hence this is separate from all the other fdi/pch
3275 * enabling. */
88cefb6c 3276 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3277 } else {
3278 assert_fdi_tx_disabled(dev_priv, pipe);
3279 assert_fdi_rx_disabled(dev_priv, pipe);
3280 }
f67a559d 3281
bf49ec8c
DV		 3282 for_each_encoder_on_crtc(dev, crtc, encoder)
3283 if (encoder->pre_enable)
3284 encoder->pre_enable(encoder);
3285
f67a559d
JB		 3286 /* Enable panel fitting for LVDS */
3287 if (dev_priv->pch_pf_size &&
3288 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3289 /* Force use of hard-coded filter coefficients
3290 * as some pre-programmed values are broken,
3291 * e.g. x201.
3292 */
9db4a9c7
JB		 3293 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3294 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3295 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3296 }
3297
9c54c0dd
JB		 3298 /*
3299 * On ILK+ LUT must be loaded before the pipe is running but with
3300 * clocks enabled
3301 */
3302 intel_crtc_load_lut(crtc);
3303
f67a559d
JB		 3304 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3305 intel_enable_plane(dev_priv, plane, pipe);
3306
3307 if (is_pch_port)
3308 ironlake_pch_enable(crtc);
c98e9dcf 3309
d1ebd816 3310 mutex_lock(&dev->struct_mutex);
bed4a673 3311 intel_update_fbc(dev);
d1ebd816
BW		 3312 mutex_unlock(&dev->struct_mutex);
3313
6b383a7f 3314 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3315
fa5c73b1
DV		 3316 for_each_encoder_on_crtc(dev, crtc, encoder)
3317 encoder->enable(encoder);
61b77ddd
DV		 3318
3319 if (HAS_PCH_CPT(dev))
3320 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3321
3322 /*
3323 * There seems to be a race in PCH platform hw (at least on some
3324 * outputs) where an enabled pipe still completes any pageflip right
3325 * away (as if the pipe is off) instead of waiting for vblank. As soon
3326 * as the first vblank happend, everything works as expected. Hence just
3327 * wait for one vblank before returning to avoid strange things
3328 * happening.
3329 */
3330 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3331}
3332
4f771f10
PZ		 3333static void haswell_crtc_enable(struct drm_crtc *crtc)
3334{
3335 struct drm_device *dev = crtc->dev;
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338 struct intel_encoder *encoder;
3339 int pipe = intel_crtc->pipe;
3340 int plane = intel_crtc->plane;
4f771f10
PZ		 3341 bool is_pch_port;
3342
3343 WARN_ON(!crtc->enabled);
3344
3345 if (intel_crtc->active)
3346 return;
3347
3348 intel_crtc->active = true;
3349 intel_update_watermarks(dev);
3350
fc316cbe 3351 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3352
83616634 3353 if (is_pch_port)
4f771f10 3354 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3355
3356 for_each_encoder_on_crtc(dev, crtc, encoder)
3357 if (encoder->pre_enable)
3358 encoder->pre_enable(encoder);
3359
1f544388 3360 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3361
1f544388
PZ		 3362 /* Enable panel fitting for eDP */
3363 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3364 /* Force use of hard-coded filter coefficients
3365 * as some pre-programmed values are broken,
3366 * e.g. x201.
3367 */
3368 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3369 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3370 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3371 }
3372
3373 /*
3374 * On ILK+ LUT must be loaded before the pipe is running but with
3375 * clocks enabled
3376 */
3377 intel_crtc_load_lut(crtc);
3378
1f544388
PZ		 3379 intel_ddi_set_pipe_settings(crtc);
3380 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3381
3382 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3383 intel_enable_plane(dev_priv, plane, pipe);
3384
3385 if (is_pch_port)
3386 ironlake_pch_enable(crtc);
3387
3388 mutex_lock(&dev->struct_mutex);
3389 intel_update_fbc(dev);
3390 mutex_unlock(&dev->struct_mutex);
3391
3392 intel_crtc_update_cursor(crtc, true);
3393
3394 for_each_encoder_on_crtc(dev, crtc, encoder)
3395 encoder->enable(encoder);
3396
4f771f10
PZ		 3397 /*
3398 * There seems to be a race in PCH platform hw (at least on some
3399 * outputs) where an enabled pipe still completes any pageflip right
3400 * away (as if the pipe is off) instead of waiting for vblank. As soon
3401 * as the first vblank happend, everything works as expected. Hence just
3402 * wait for one vblank before returning to avoid strange things
3403 * happening.
3404 */
3405 intel_wait_for_vblank(dev, intel_crtc->pipe);
3406}
3407
6be4a607
JB		 3408static void ironlake_crtc_disable(struct drm_crtc *crtc)
3409{
3410 struct drm_device *dev = crtc->dev;
3411 struct drm_i915_private *dev_priv = dev->dev_private;
3412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3413 struct intel_encoder *encoder;
6be4a607
JB		 3414 int pipe = intel_crtc->pipe;
3415 int plane = intel_crtc->plane;
5eddb70b 3416 u32 reg, temp;
b52eb4dc 3417
ef9c3aee 3418
f7abfe8b
CW		 3419 if (!intel_crtc->active)
3420 return;
3421
ea9d758d
DV		 3422 for_each_encoder_on_crtc(dev, crtc, encoder)
3423 encoder->disable(encoder);
3424
e6c3a2a6 3425 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3426 drm_vblank_off(dev, pipe);
6b383a7f 3427 intel_crtc_update_cursor(crtc, false);
5eddb70b 3428
b24e7179 3429 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3430
973d04f9
CW		 3431 if (dev_priv->cfb_plane == plane)
3432 intel_disable_fbc(dev);
2c07245f 3433
b24e7179 3434 intel_disable_pipe(dev_priv, pipe);
32f9d658 3435
6be4a607 3436 /* Disable PF */
9db4a9c7
JB		 3437 I915_WRITE(PF_CTL(pipe), 0);
3438 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3439
bf49ec8c
DV		 3440 for_each_encoder_on_crtc(dev, crtc, encoder)
3441 if (encoder->post_disable)
3442 encoder->post_disable(encoder);
3443
0fc932b8 3444 ironlake_fdi_disable(crtc);
2c07245f 3445
040484af 3446 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3447
6be4a607
JB		 3448 if (HAS_PCH_CPT(dev)) {
3449 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3450 reg = TRANS_DP_CTL(pipe);
3451 temp = I915_READ(reg);
3452 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3453 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3454 I915_WRITE(reg, temp);
6be4a607
JB		 3455
3456 /* disable DPLL_SEL */
3457 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3458 switch (pipe) {
3459 case 0:
d64311ab 3460 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3461 break;
3462 case 1:
6be4a607 3463 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3464 break;
3465 case 2:
4b645f14 3466 /* C shares PLL A or B */
d64311ab 3467 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3468 break;
3469 default:
3470 BUG(); /* wtf */
3471 }
6be4a607 3472 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3473 }
e3421a18 3474
6be4a607 3475 /* disable PCH DPLL */
ee7b9f93 3476 intel_disable_pch_pll(intel_crtc);
8db9d77b 3477
88cefb6c 3478 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3479
f7abfe8b 3480 intel_crtc->active = false;
6b383a7f 3481 intel_update_watermarks(dev);
d1ebd816
BW		 3482
3483 mutex_lock(&dev->struct_mutex);
6b383a7f 3484 intel_update_fbc(dev);
d1ebd816 3485 mutex_unlock(&dev->struct_mutex);
6be4a607 3486}
1b3c7a47 3487
4f771f10
PZ		 3488static void haswell_crtc_disable(struct drm_crtc *crtc)
3489{
3490 struct drm_device *dev = crtc->dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3493 struct intel_encoder *encoder;
3494 int pipe = intel_crtc->pipe;
3495 int plane = intel_crtc->plane;
ad80a810 3496 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3497 bool is_pch_port;
4f771f10
PZ		 3498
3499 if (!intel_crtc->active)
3500 return;
3501
83616634
PZ		 3502 is_pch_port = haswell_crtc_driving_pch(crtc);
3503
4f771f10
PZ		 3504 for_each_encoder_on_crtc(dev, crtc, encoder)
3505 encoder->disable(encoder);
3506
3507 intel_crtc_wait_for_pending_flips(crtc);
3508 drm_vblank_off(dev, pipe);
3509 intel_crtc_update_cursor(crtc, false);
3510
3511 intel_disable_plane(dev_priv, plane, pipe);
3512
3513 if (dev_priv->cfb_plane == plane)
3514 intel_disable_fbc(dev);
3515
3516 intel_disable_pipe(dev_priv, pipe);
3517
ad80a810 3518 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3519
3520 /* Disable PF */
3521 I915_WRITE(PF_CTL(pipe), 0);
3522 I915_WRITE(PF_WIN_SZ(pipe), 0);
3523
1f544388 3524 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3525
3526 for_each_encoder_on_crtc(dev, crtc, encoder)
3527 if (encoder->post_disable)
3528 encoder->post_disable(encoder);
3529
83616634
PZ		 3530 if (is_pch_port) {
3531 ironlake_fdi_disable(crtc);
3532 intel_disable_transcoder(dev_priv, pipe);
3533 intel_disable_pch_pll(intel_crtc);
3534 ironlake_fdi_pll_disable(intel_crtc);
3535 }
4f771f10
PZ		 3536
3537 intel_crtc->active = false;
3538 intel_update_watermarks(dev);
3539
3540 mutex_lock(&dev->struct_mutex);
3541 intel_update_fbc(dev);
3542 mutex_unlock(&dev->struct_mutex);
3543}
3544
ee7b9f93
JB		 3545static void ironlake_crtc_off(struct drm_crtc *crtc)
3546{
3547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3548 intel_put_pch_pll(intel_crtc);
3549}
3550
6441ab5f
PZ		 3551static void haswell_crtc_off(struct drm_crtc *crtc)
3552{
a5c961d1
PZ		 3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554
3555 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3556 * start using it. */
3557 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3558
6441ab5f
PZ		 3559 intel_ddi_put_crtc_pll(crtc);
3560}
3561
02e792fb
DV		 3562static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3563{
02e792fb 3564 if (!enable && intel_crtc->overlay) {
23f09ce3 3565 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3566 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3567
23f09ce3 3568 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3569 dev_priv->mm.interruptible = false;
3570 (void) intel_overlay_switch_off(intel_crtc->overlay);
3571 dev_priv->mm.interruptible = true;
23f09ce3 3572 mutex_unlock(&dev->struct_mutex);
02e792fb 3573 }
02e792fb 3574
5dcdbcb0
CW		 3575 /* Let userspace switch the overlay on again. In most cases userspace
3576 * has to recompute where to put it anyway.
3577 */
02e792fb
DV		 3578}
3579
0b8765c6 3580static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3581{
3582 struct drm_device *dev = crtc->dev;
79e53945
JB		 3583 struct drm_i915_private *dev_priv = dev->dev_private;
3584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3585 struct intel_encoder *encoder;
79e53945 3586 int pipe = intel_crtc->pipe;
80824003 3587 int plane = intel_crtc->plane;
79e53945 3588
08a48469
DV		 3589 WARN_ON(!crtc->enabled);
3590
f7abfe8b
CW		 3591 if (intel_crtc->active)
3592 return;
3593
3594 intel_crtc->active = true;
6b383a7f
CW		 3595 intel_update_watermarks(dev);
3596
63d7bbe9 3597 intel_enable_pll(dev_priv, pipe);
040484af 3598 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3599 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3600
0b8765c6 3601 intel_crtc_load_lut(crtc);
bed4a673 3602 intel_update_fbc(dev);
79e53945 3603
0b8765c6
JB		 3604 /* Give the overlay scaler a chance to enable if it's on this pipe */
3605 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3606 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3607
fa5c73b1
DV		 3608 for_each_encoder_on_crtc(dev, crtc, encoder)
3609 encoder->enable(encoder);
0b8765c6 3610}
79e53945 3611
0b8765c6
JB		 3612static void i9xx_crtc_disable(struct drm_crtc *crtc)
3613{
3614 struct drm_device *dev = crtc->dev;
3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3617 struct intel_encoder *encoder;
0b8765c6
JB		 3618 int pipe = intel_crtc->pipe;
3619 int plane = intel_crtc->plane;
b690e96c 3620
ef9c3aee 3621
f7abfe8b
CW		 3622 if (!intel_crtc->active)
3623 return;
3624
ea9d758d
DV		 3625 for_each_encoder_on_crtc(dev, crtc, encoder)
3626 encoder->disable(encoder);
3627
0b8765c6 3628 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3629 intel_crtc_wait_for_pending_flips(crtc);
3630 drm_vblank_off(dev, pipe);
0b8765c6 3631 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3632 intel_crtc_update_cursor(crtc, false);
0b8765c6 3633
973d04f9
CW		 3634 if (dev_priv->cfb_plane == plane)
3635 intel_disable_fbc(dev);
79e53945 3636
b24e7179 3637 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3638 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3639 intel_disable_pll(dev_priv, pipe);
0b8765c6 3640
f7abfe8b 3641 intel_crtc->active = false;
6b383a7f
CW		 3642 intel_update_fbc(dev);
3643 intel_update_watermarks(dev);
0b8765c6
JB		 3644}
3645
ee7b9f93
JB		 3646static void i9xx_crtc_off(struct drm_crtc *crtc)
3647{
3648}
3649
976f8a20
DV		 3650static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3651 bool enabled)
2c07245f
ZW		 3652{
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_master_private *master_priv;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 int pipe = intel_crtc->pipe;
79e53945
JB		 3657
3658 if (!dev->primary->master)
3659 return;
3660
3661 master_priv = dev->primary->master->driver_priv;
3662 if (!master_priv->sarea_priv)
3663 return;
3664
79e53945
JB		 3665 switch (pipe) {
3666 case 0:
3667 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3668 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3669 break;
3670 case 1:
3671 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3672 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3673 break;
3674 default:
9db4a9c7 3675 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3676 break;
3677 }
79e53945
JB		 3678}
3679
976f8a20
DV		 3680/**
3681 * Sets the power management mode of the pipe and plane.
3682 */
3683void intel_crtc_update_dpms(struct drm_crtc *crtc)
3684{
3685 struct drm_device *dev = crtc->dev;
3686 struct drm_i915_private *dev_priv = dev->dev_private;
3687 struct intel_encoder *intel_encoder;
3688 bool enable = false;
3689
3690 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3691 enable |= intel_encoder->connectors_active;
3692
3693 if (enable)
3694 dev_priv->display.crtc_enable(crtc);
3695 else
3696 dev_priv->display.crtc_disable(crtc);
3697
3698 intel_crtc_update_sarea(crtc, enable);
3699}
3700
3701static void intel_crtc_noop(struct drm_crtc *crtc)
3702{
3703}
3704
cdd59983
CW		 3705static void intel_crtc_disable(struct drm_crtc *crtc)
3706{
cdd59983 3707 struct drm_device *dev = crtc->dev;
976f8a20 3708 struct drm_connector *connector;
ee7b9f93 3709 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3710
976f8a20
DV		 3711 /* crtc should still be enabled when we disable it. */
3712 WARN_ON(!crtc->enabled);
3713
3714 dev_priv->display.crtc_disable(crtc);
3715 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3716 dev_priv->display.off(crtc);
3717
931872fc
CW		 3718 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3719 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3720
3721 if (crtc->fb) {
3722 mutex_lock(&dev->struct_mutex);
1690e1eb 3723 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3724 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3725 crtc->fb = NULL;
3726 }
3727
3728 /* Update computed state. */
3729 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3730 if (!connector->encoder || !connector->encoder->crtc)
3731 continue;
3732
3733 if (connector->encoder->crtc != crtc)
3734 continue;
3735
3736 connector->dpms = DRM_MODE_DPMS_OFF;
3737 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3738 }
3739}
3740
a261b246 3741void intel_modeset_disable(struct drm_device *dev)
79e53945 3742{
a261b246
DV		 3743 struct drm_crtc *crtc;
3744
3745 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3746 if (crtc->enabled)
3747 intel_crtc_disable(crtc);
3748 }
79e53945
JB		 3749}
3750
1f703855 3751void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3752{
7e7d76c3
JB		 3753}
3754
ea5b213a 3755void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3756{
4ef69c7a 3757 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3758
ea5b213a
CW		 3759 drm_encoder_cleanup(encoder);
3760 kfree(intel_encoder);
7e7d76c3
JB		 3761}
3762
5ab432ef
DV		 3763/* Simple dpms helper for encodres with just one connector, no cloning and only
3764 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3765 * state of the entire output pipe. */
3766void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3767{
5ab432ef
DV		 3768 if (mode == DRM_MODE_DPMS_ON) {
3769 encoder->connectors_active = true;
3770
b2cabb0e 3771 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3772 } else {
3773 encoder->connectors_active = false;
3774
b2cabb0e 3775 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3776 }
79e53945
JB		 3777}
3778
0a91ca29
DV		 3779/* Cross check the actual hw state with our own modeset state tracking (and it's
3780 * internal consistency). */
b980514c 3781static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3782{
0a91ca29
DV		 3783 if (connector->get_hw_state(connector)) {
3784 struct intel_encoder *encoder = connector->encoder;
3785 struct drm_crtc *crtc;
3786 bool encoder_enabled;
3787 enum pipe pipe;
3788
3789 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3790 connector->base.base.id,
3791 drm_get_connector_name(&connector->base));
3792
3793 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3794 "wrong connector dpms state\n");
3795 WARN(connector->base.encoder != &encoder->base,
3796 "active connector not linked to encoder\n");
3797 WARN(!encoder->connectors_active,
3798 "encoder->connectors_active not set\n");
3799
3800 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3801 WARN(!encoder_enabled, "encoder not enabled\n");
3802 if (WARN_ON(!encoder->base.crtc))
3803 return;
3804
3805 crtc = encoder->base.crtc;
3806
3807 WARN(!crtc->enabled, "crtc not enabled\n");
3808 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3809 WARN(pipe != to_intel_crtc(crtc)->pipe,
3810 "encoder active on the wrong pipe\n");
3811 }
79e53945
JB		 3812}
3813
5ab432ef
DV		 3814/* Even simpler default implementation, if there's really no special case to
3815 * consider. */
3816void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3817{
5ab432ef 3818 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3819
5ab432ef
DV		 3820 /* All the simple cases only support two dpms states. */
3821 if (mode != DRM_MODE_DPMS_ON)
3822 mode = DRM_MODE_DPMS_OFF;
d4270e57 3823
5ab432ef
DV		 3824 if (mode == connector->dpms)
3825 return;
3826
3827 connector->dpms = mode;
3828
3829 /* Only need to change hw state when actually enabled */
3830 if (encoder->base.crtc)
3831 intel_encoder_dpms(encoder, mode);
3832 else
8af6cf88 3833 WARN_ON(encoder->connectors_active != false);
0a91ca29 3834
b980514c 3835 intel_modeset_check_state(connector->dev);
79e53945
JB		 3836}
3837
f0947c37
DV		 3838/* Simple connector->get_hw_state implementation for encoders that support only
3839 * one connector and no cloning and hence the encoder state determines the state
3840 * of the connector. */
3841bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3842{
24929352 3843 enum pipe pipe = 0;
f0947c37 3844 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3845
f0947c37 3846 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3847}
3848
79e53945 3849static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3850 const struct drm_display_mode *mode,
79e53945
JB		 3851 struct drm_display_mode *adjusted_mode)
3852{
2c07245f 3853 struct drm_device *dev = crtc->dev;
89749350 3854
bad720ff 3855 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3856 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3857 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3858 return false;
2c07245f 3859 }
89749350 3860
f9bef081
DV		 3861 /* All interlaced capable intel hw wants timings in frames. Note though
3862 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3863 * timings, so we need to be careful not to clobber these.*/
3864 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3865 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3866
44f46b42
CW		 3867 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3868 * with a hsync front porch of 0.
3869 */
3870 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3871 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3872 return false;
3873
79e53945
JB		 3874 return true;
3875}
3876
25eb05fc
JB		 3877static int valleyview_get_display_clock_speed(struct drm_device *dev)
3878{
3879 return 400000; /* FIXME */
3880}
3881
e70236a8
JB		 3882static int i945_get_display_clock_speed(struct drm_device *dev)
3883{
3884 return 400000;
3885}
79e53945 3886
e70236a8 3887static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3888{
e70236a8
JB		 3889 return 333000;
3890}
79e53945 3891
e70236a8
JB		 3892static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3893{
3894 return 200000;
3895}
79e53945 3896
e70236a8
JB		 3897static int i915gm_get_display_clock_speed(struct drm_device *dev)
3898{
3899 u16 gcfgc = 0;
79e53945 3900
e70236a8
JB		 3901 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3902
3903 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3904 return 133000;
3905 else {
3906 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3907 case GC_DISPLAY_CLOCK_333_MHZ:
3908 return 333000;
3909 default:
3910 case GC_DISPLAY_CLOCK_190_200_MHZ:
3911 return 190000;
79e53945 3912 }
e70236a8
JB		 3913 }
3914}
3915
3916static int i865_get_display_clock_speed(struct drm_device *dev)
3917{
3918 return 266000;
3919}
3920
3921static int i855_get_display_clock_speed(struct drm_device *dev)
3922{
3923 u16 hpllcc = 0;
3924 /* Assume that the hardware is in the high speed state. This
3925 * should be the default.
3926 */
3927 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3928 case GC_CLOCK_133_200:
3929 case GC_CLOCK_100_200:
3930 return 200000;
3931 case GC_CLOCK_166_250:
3932 return 250000;
3933 case GC_CLOCK_100_133:
79e53945 3934 return 133000;
e70236a8 3935 }
79e53945 3936
e70236a8
JB		 3937 /* Shouldn't happen */
3938 return 0;
3939}
79e53945 3940
e70236a8
JB		 3941static int i830_get_display_clock_speed(struct drm_device *dev)
3942{
3943 return 133000;
79e53945
JB		 3944}
3945
2c07245f
ZW		 3946struct fdi_m_n {
3947 u32 tu;
3948 u32 gmch_m;
3949 u32 gmch_n;
3950 u32 link_m;
3951 u32 link_n;
3952};
3953
3954static void
3955fdi_reduce_ratio(u32 *num, u32 *den)
3956{
3957 while (*num > 0xffffff || *den > 0xffffff) {
3958 *num >>= 1;
3959 *den >>= 1;
3960 }
3961}
3962
2c07245f 3963static void
f2b115e6
AJ		 3964ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3965 int link_clock, struct fdi_m_n *m_n)
2c07245f 3966{
2c07245f
ZW		 3967 m_n->tu = 64; /* default size */
3968
22ed1113
CW		 3969 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3970 m_n->gmch_m = bits_per_pixel * pixel_clock;
3971 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3972 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3973
22ed1113
CW		 3974 m_n->link_m = pixel_clock;
3975 m_n->link_n = link_clock;
2c07245f
ZW		 3976 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3977}
3978
a7615030
CW		 3979static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3980{
72bbe58c
KP		 3981 if (i915_panel_use_ssc >= 0)
3982 return i915_panel_use_ssc != 0;
3983 return dev_priv->lvds_use_ssc
435793df 3984 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3985}
3986
5a354204
JB		 3987/**
3988 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3989 * @crtc: CRTC structure
3b5c78a3 3990 * @mode: requested mode
5a354204
JB		 3991 *
3992 * A pipe may be connected to one or more outputs. Based on the depth of the
3993 * attached framebuffer, choose a good color depth to use on the pipe.
3994 *
3995 * If possible, match the pipe depth to the fb depth. In some cases, this
3996 * isn't ideal, because the connected output supports a lesser or restricted
3997 * set of depths. Resolve that here:
3998 * LVDS typically supports only 6bpc, so clamp down in that case
3999 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4000 * Displays may support a restricted set as well, check EDID and clamp as
4001 * appropriate.
3b5c78a3 4002 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4003 *
4004 * RETURNS:
4005 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4006 * true if they don't match).
4007 */
4008static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4009 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4010 unsigned int *pipe_bpp,
4011 struct drm_display_mode *mode)
5a354204
JB		 4012{
4013 struct drm_device *dev = crtc->dev;
4014 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4015 struct drm_connector *connector;
6c2b7c12 4016 struct intel_encoder *intel_encoder;
5a354204
JB		 4017 unsigned int display_bpc = UINT_MAX, bpc;
4018
4019 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4020 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4021
4022 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4023 unsigned int lvds_bpc;
4024
4025 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4026 LVDS_A3_POWER_UP)
4027 lvds_bpc = 8;
4028 else
4029 lvds_bpc = 6;
4030
4031 if (lvds_bpc < display_bpc) {
82820490 4032 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4033 display_bpc = lvds_bpc;
4034 }
4035 continue;
4036 }
4037
5a354204
JB		 4038 /* Not one of the known troublemakers, check the EDID */
4039 list_for_each_entry(connector, &dev->mode_config.connector_list,
4040 head) {
6c2b7c12 4041 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4042 continue;
4043
62ac41a6
JB		 4044 /* Don't use an invalid EDID bpc value */
4045 if (connector->display_info.bpc &&
4046 connector->display_info.bpc < display_bpc) {
82820490 4047 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4048 display_bpc = connector->display_info.bpc;
4049 }
4050 }
4051
4052 /*
4053 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4054 * through, clamp it down. (Note: >12bpc will be caught below.)
4055 */
4056 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4057 if (display_bpc > 8 && display_bpc < 12) {
82820490 4058 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4059 display_bpc = 12;
4060 } else {
82820490 4061 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4062 display_bpc = 8;
4063 }
4064 }
4065 }
4066
3b5c78a3
AJ		 4067 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4068 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4069 display_bpc = 6;
4070 }
4071
5a354204
JB		 4072 /*
4073 * We could just drive the pipe at the highest bpc all the time and
4074 * enable dithering as needed, but that costs bandwidth. So choose
4075 * the minimum value that expresses the full color range of the fb but
4076 * also stays within the max display bpc discovered above.
4077 */
4078
94352cf9 4079 switch (fb->depth) {
5a354204
JB		 4080 case 8:
4081 bpc = 8; /* since we go through a colormap */
4082 break;
4083 case 15:
4084 case 16:
4085 bpc = 6; /* min is 18bpp */
4086 break;
4087 case 24:
578393cd 4088 bpc = 8;
5a354204
JB		 4089 break;
4090 case 30:
578393cd 4091 bpc = 10;
5a354204
JB		 4092 break;
4093 case 48:
578393cd 4094 bpc = 12;
5a354204
JB		 4095 break;
4096 default:
4097 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4098 bpc = min((unsigned int)8, display_bpc);
4099 break;
4100 }
4101
578393cd
KP		 4102 display_bpc = min(display_bpc, bpc);
4103
82820490
AJ		 4104 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4105 bpc, display_bpc);
5a354204 4106
578393cd 4107 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4108
4109 return display_bpc != bpc;
4110}
4111
a0c4da24
JB		 4112static int vlv_get_refclk(struct drm_crtc *crtc)
4113{
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 int refclk = 27000; /* for DP & HDMI */
4117
4118 return 100000; /* only one validated so far */
4119
4120 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4121 refclk = 96000;
4122 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4123 if (intel_panel_use_ssc(dev_priv))
4124 refclk = 100000;
4125 else
4126 refclk = 96000;
4127 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4128 refclk = 100000;
4129 }
4130
4131 return refclk;
4132}
4133
c65d77d8
JB		 4134static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4135{
4136 struct drm_device *dev = crtc->dev;
4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138 int refclk;
4139
a0c4da24
JB		 4140 if (IS_VALLEYVIEW(dev)) {
4141 refclk = vlv_get_refclk(crtc);
4142 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4143 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4144 refclk = dev_priv->lvds_ssc_freq * 1000;
4145 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4146 refclk / 1000);
4147 } else if (!IS_GEN2(dev)) {
4148 refclk = 96000;
4149 } else {
4150 refclk = 48000;
4151 }
4152
4153 return refclk;
4154}
4155
4156static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4157 intel_clock_t *clock)
4158{
4159 /* SDVO TV has fixed PLL values depend on its clock range,
4160 this mirrors vbios setting. */
4161 if (adjusted_mode->clock >= 100000
4162 && adjusted_mode->clock < 140500) {
4163 clock->p1 = 2;
4164 clock->p2 = 10;
4165 clock->n = 3;
4166 clock->m1 = 16;
4167 clock->m2 = 8;
4168 } else if (adjusted_mode->clock >= 140500
4169 && adjusted_mode->clock <= 200000) {
4170 clock->p1 = 1;
4171 clock->p2 = 10;
4172 clock->n = 6;
4173 clock->m1 = 12;
4174 clock->m2 = 8;
4175 }
4176}
4177
a7516a05
JB		 4178static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4179 intel_clock_t *clock,
4180 intel_clock_t *reduced_clock)
4181{
4182 struct drm_device *dev = crtc->dev;
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4185 int pipe = intel_crtc->pipe;
4186 u32 fp, fp2 = 0;
4187
4188 if (IS_PINEVIEW(dev)) {
4189 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4190 if (reduced_clock)
4191 fp2 = (1 << reduced_clock->n) << 16 |
4192 reduced_clock->m1 << 8 | reduced_clock->m2;
4193 } else {
4194 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4195 if (reduced_clock)
4196 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4197 reduced_clock->m2;
4198 }
4199
4200 I915_WRITE(FP0(pipe), fp);
4201
4202 intel_crtc->lowfreq_avail = false;
4203 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4204 reduced_clock && i915_powersave) {
4205 I915_WRITE(FP1(pipe), fp2);
4206 intel_crtc->lowfreq_avail = true;
4207 } else {
4208 I915_WRITE(FP1(pipe), fp);
4209 }
4210}
4211
93e537a1
DV		 4212static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4213 struct drm_display_mode *adjusted_mode)
4214{
4215 struct drm_device *dev = crtc->dev;
4216 struct drm_i915_private *dev_priv = dev->dev_private;
4217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4218 int pipe = intel_crtc->pipe;
284d5df5 4219 u32 temp;
93e537a1
DV		 4220
4221 temp = I915_READ(LVDS);
4222 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4223 if (pipe == 1) {
4224 temp |= LVDS_PIPEB_SELECT;
4225 } else {
4226 temp &= ~LVDS_PIPEB_SELECT;
4227 }
4228 /* set the corresponsding LVDS_BORDER bit */
4229 temp |= dev_priv->lvds_border_bits;
4230 /* Set the B0-B3 data pairs corresponding to whether we're going to
4231 * set the DPLLs for dual-channel mode or not.
4232 */
4233 if (clock->p2 == 7)
4234 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4235 else
4236 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4237
4238 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4239 * appropriately here, but we need to look more thoroughly into how
4240 * panels behave in the two modes.
4241 */
4242 /* set the dithering flag on LVDS as needed */
4243 if (INTEL_INFO(dev)->gen >= 4) {
4244 if (dev_priv->lvds_dither)
4245 temp |= LVDS_ENABLE_DITHER;
4246 else
4247 temp &= ~LVDS_ENABLE_DITHER;
4248 }
284d5df5 4249 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4250 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4251 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4252 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4253 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4254 I915_WRITE(LVDS, temp);
4255}
4256
a0c4da24
JB		 4257static void vlv_update_pll(struct drm_crtc *crtc,
4258 struct drm_display_mode *mode,
4259 struct drm_display_mode *adjusted_mode,
4260 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4261 int num_connectors)
a0c4da24
JB		 4262{
4263 struct drm_device *dev = crtc->dev;
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4266 int pipe = intel_crtc->pipe;
4267 u32 dpll, mdiv, pdiv;
4268 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4269 bool is_sdvo;
4270 u32 temp;
4271
4272 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4273 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4274
2a8f64ca
VP		 4275 dpll = DPLL_VGA_MODE_DIS;
4276 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4277 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4278 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4279
4280 I915_WRITE(DPLL(pipe), dpll);
4281 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4282
4283 bestn = clock->n;
4284 bestm1 = clock->m1;
4285 bestm2 = clock->m2;
4286 bestp1 = clock->p1;
4287 bestp2 = clock->p2;
4288
2a8f64ca
VP		 4289 /*
4290 * In Valleyview PLL and program lane counter registers are exposed
4291 * through DPIO interface
4292 */
a0c4da24
JB		 4293 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4294 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4295 mdiv |= ((bestn << DPIO_N_SHIFT));
4296 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4297 mdiv |= (1 << DPIO_K_SHIFT);
4298 mdiv |= DPIO_ENABLE_CALIBRATION;
4299 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4300
4301 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4302
2a8f64ca 4303 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4304 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4305 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4306 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4307 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4308
2a8f64ca 4309 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4310
4311 dpll |= DPLL_VCO_ENABLE;
4312 I915_WRITE(DPLL(pipe), dpll);
4313 POSTING_READ(DPLL(pipe));
4314 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4315 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4316
2a8f64ca
VP		 4317 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4318
4319 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4320 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4321
4322 I915_WRITE(DPLL(pipe), dpll);
4323
4324 /* Wait for the clocks to stabilize. */
4325 POSTING_READ(DPLL(pipe));
4326 udelay(150);
a0c4da24 4327
2a8f64ca
VP		 4328 temp = 0;
4329 if (is_sdvo) {
4330 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4331 if (temp > 1)
4332 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4333 else
4334 temp = 0;
a0c4da24 4335 }
2a8f64ca
VP		 4336 I915_WRITE(DPLL_MD(pipe), temp);
4337 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4338
2a8f64ca
VP		 4339 /* Now program lane control registers */
4340 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4341 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4342 {
4343 temp = 0x1000C4;
4344 if(pipe == 1)
4345 temp |= (1 << 21);
4346 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4347 }
4348 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4349 {
4350 temp = 0x1000C4;
4351 if(pipe == 1)
4352 temp |= (1 << 21);
4353 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4354 }
a0c4da24
JB		 4355}
4356
eb1cbe48
DV		 4357static void i9xx_update_pll(struct drm_crtc *crtc,
4358 struct drm_display_mode *mode,
4359 struct drm_display_mode *adjusted_mode,
4360 intel_clock_t *clock, intel_clock_t *reduced_clock,
4361 int num_connectors)
4362{
4363 struct drm_device *dev = crtc->dev;
4364 struct drm_i915_private *dev_priv = dev->dev_private;
4365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4366 int pipe = intel_crtc->pipe;
4367 u32 dpll;
4368 bool is_sdvo;
4369
2a8f64ca
VP		 4370 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4371
eb1cbe48
DV		 4372 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4373 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4374
4375 dpll = DPLL_VGA_MODE_DIS;
4376
4377 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4378 dpll |= DPLLB_MODE_LVDS;
4379 else
4380 dpll |= DPLLB_MODE_DAC_SERIAL;
4381 if (is_sdvo) {
4382 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4383 if (pixel_multiplier > 1) {
4384 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4385 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4386 }
4387 dpll |= DPLL_DVO_HIGH_SPEED;
4388 }
4389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4390 dpll |= DPLL_DVO_HIGH_SPEED;
4391
4392 /* compute bitmask from p1 value */
4393 if (IS_PINEVIEW(dev))
4394 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4395 else {
4396 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4397 if (IS_G4X(dev) && reduced_clock)
4398 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4399 }
4400 switch (clock->p2) {
4401 case 5:
4402 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4403 break;
4404 case 7:
4405 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4406 break;
4407 case 10:
4408 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4409 break;
4410 case 14:
4411 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4412 break;
4413 }
4414 if (INTEL_INFO(dev)->gen >= 4)
4415 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4416
4417 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4418 dpll |= PLL_REF_INPUT_TVCLKINBC;
4419 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4420 /* XXX: just matching BIOS for now */
4421 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4422 dpll |= 3;
4423 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4424 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4425 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4426 else
4427 dpll |= PLL_REF_INPUT_DREFCLK;
4428
4429 dpll |= DPLL_VCO_ENABLE;
4430 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4431 POSTING_READ(DPLL(pipe));
4432 udelay(150);
4433
4434 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4435 * This is an exception to the general rule that mode_set doesn't turn
4436 * things on.
4437 */
4438 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4439 intel_update_lvds(crtc, clock, adjusted_mode);
4440
4441 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4442 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4443
4444 I915_WRITE(DPLL(pipe), dpll);
4445
4446 /* Wait for the clocks to stabilize. */
4447 POSTING_READ(DPLL(pipe));
4448 udelay(150);
4449
4450 if (INTEL_INFO(dev)->gen >= 4) {
4451 u32 temp = 0;
4452 if (is_sdvo) {
4453 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4454 if (temp > 1)
4455 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4456 else
4457 temp = 0;
4458 }
4459 I915_WRITE(DPLL_MD(pipe), temp);
4460 } else {
4461 /* The pixel multiplier can only be updated once the
4462 * DPLL is enabled and the clocks are stable.
4463 *
4464 * So write it again.
4465 */
4466 I915_WRITE(DPLL(pipe), dpll);
4467 }
4468}
4469
4470static void i8xx_update_pll(struct drm_crtc *crtc,
4471 struct drm_display_mode *adjusted_mode,
2a8f64ca 4472 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4473 int num_connectors)
4474{
4475 struct drm_device *dev = crtc->dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4478 int pipe = intel_crtc->pipe;
4479 u32 dpll;
4480
2a8f64ca
VP		 4481 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4482
eb1cbe48
DV		 4483 dpll = DPLL_VGA_MODE_DIS;
4484
4485 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4486 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4487 } else {
4488 if (clock->p1 == 2)
4489 dpll |= PLL_P1_DIVIDE_BY_TWO;
4490 else
4491 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4492 if (clock->p2 == 4)
4493 dpll |= PLL_P2_DIVIDE_BY_4;
4494 }
4495
4496 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4497 /* XXX: just matching BIOS for now */
4498 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4499 dpll |= 3;
4500 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4501 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4502 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4503 else
4504 dpll |= PLL_REF_INPUT_DREFCLK;
4505
4506 dpll |= DPLL_VCO_ENABLE;
4507 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4508 POSTING_READ(DPLL(pipe));
4509 udelay(150);
4510
eb1cbe48
DV		 4511 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4512 * This is an exception to the general rule that mode_set doesn't turn
4513 * things on.
4514 */
4515 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4516 intel_update_lvds(crtc, clock, adjusted_mode);
4517
5b5896e4
DV		 4518 I915_WRITE(DPLL(pipe), dpll);
4519
4520 /* Wait for the clocks to stabilize. */
4521 POSTING_READ(DPLL(pipe));
4522 udelay(150);
4523
eb1cbe48
DV		 4524 /* The pixel multiplier can only be updated once the
4525 * DPLL is enabled and the clocks are stable.
4526 *
4527 * So write it again.
4528 */
4529 I915_WRITE(DPLL(pipe), dpll);
4530}
4531
b0e77b9c
PZ		 4532static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4533 struct drm_display_mode *mode,
4534 struct drm_display_mode *adjusted_mode)
4535{
4536 struct drm_device *dev = intel_crtc->base.dev;
4537 struct drm_i915_private *dev_priv = dev->dev_private;
4538 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4539 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4540 uint32_t vsyncshift;
4541
4542 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4543 /* the chip adds 2 halflines automatically */
4544 adjusted_mode->crtc_vtotal -= 1;
4545 adjusted_mode->crtc_vblank_end -= 1;
4546 vsyncshift = adjusted_mode->crtc_hsync_start
4547 - adjusted_mode->crtc_htotal / 2;
4548 } else {
4549 vsyncshift = 0;
4550 }
4551
4552 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4553 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4554
fe2b8f9d 4555 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4556 (adjusted_mode->crtc_hdisplay - 1) |
4557 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4558 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4559 (adjusted_mode->crtc_hblank_start - 1) |
4560 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4561 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4562 (adjusted_mode->crtc_hsync_start - 1) |
4563 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4564
fe2b8f9d 4565 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4566 (adjusted_mode->crtc_vdisplay - 1) |
4567 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4568 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4569 (adjusted_mode->crtc_vblank_start - 1) |
4570 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4571 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4572 (adjusted_mode->crtc_vsync_start - 1) |
4573 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4574
b5e508d4
PZ		 4575 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4576 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4577 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4578 * bits. */
4579 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4580 (pipe == PIPE_B || pipe == PIPE_C))
4581 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4582
b0e77b9c
PZ		 4583 /* pipesrc controls the size that is scaled from, which should
4584 * always be the user's requested size.
4585 */
4586 I915_WRITE(PIPESRC(pipe),
4587 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4588}
4589
f564048e
EA		 4590static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4591 struct drm_display_mode *mode,
4592 struct drm_display_mode *adjusted_mode,
4593 int x, int y,
94352cf9 4594 struct drm_framebuffer *fb)
79e53945
JB		 4595{
4596 struct drm_device *dev = crtc->dev;
4597 struct drm_i915_private *dev_priv = dev->dev_private;
4598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4599 int pipe = intel_crtc->pipe;
80824003 4600 int plane = intel_crtc->plane;
c751ce4f 4601 int refclk, num_connectors = 0;
652c393a 4602 intel_clock_t clock, reduced_clock;
b0e77b9c 4603 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4604 bool ok, has_reduced_clock = false, is_sdvo = false;
4605 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4606 struct intel_encoder *encoder;
d4906093 4607 const intel_limit_t *limit;
5c3b82e2 4608 int ret;
79e53945 4609
6c2b7c12 4610 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4611 switch (encoder->type) {
79e53945
JB		 4612 case INTEL_OUTPUT_LVDS:
4613 is_lvds = true;
4614 break;
4615 case INTEL_OUTPUT_SDVO:
7d57382e 4616 case INTEL_OUTPUT_HDMI:
79e53945 4617 is_sdvo = true;
5eddb70b 4618 if (encoder->needs_tv_clock)
e2f0ba97 4619 is_tv = true;
79e53945 4620 break;
79e53945
JB		 4621 case INTEL_OUTPUT_TVOUT:
4622 is_tv = true;
4623 break;
a4fc5ed6
KP		 4624 case INTEL_OUTPUT_DISPLAYPORT:
4625 is_dp = true;
4626 break;
79e53945 4627 }
43565a06 4628
c751ce4f 4629 num_connectors++;
79e53945
JB		 4630 }
4631
c65d77d8 4632 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4633
d4906093
ML		 4634 /*
4635 * Returns a set of divisors for the desired target clock with the given
4636 * refclk, or FALSE. The returned values represent the clock equation:
4637 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4638 */
1b894b59 4639 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4640 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4641 &clock);
79e53945
JB		 4642 if (!ok) {
4643 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4644 return -EINVAL;
79e53945
JB		 4645 }
4646
cda4b7d3 4647 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4648 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4649
ddc9003c 4650 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4651 /*
4652 * Ensure we match the reduced clock's P to the target clock.
4653 * If the clocks don't match, we can't switch the display clock
4654 * by using the FP0/FP1. In such case we will disable the LVDS
4655 * downclock feature.
4656 */
ddc9003c 4657 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4658 dev_priv->lvds_downclock,
4659 refclk,
cec2f356 4660 &clock,
5eddb70b 4661 &reduced_clock);
7026d4ac
ZW		 4662 }
4663
c65d77d8
JB		 4664 if (is_sdvo && is_tv)
4665 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4666
eb1cbe48 4667 if (IS_GEN2(dev))
2a8f64ca
VP		 4668 i8xx_update_pll(crtc, adjusted_mode, &clock,
4669 has_reduced_clock ? &reduced_clock : NULL,
4670 num_connectors);
a0c4da24 4671 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4672 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4673 has_reduced_clock ? &reduced_clock : NULL,
4674 num_connectors);
79e53945 4675 else
eb1cbe48
DV		 4676 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4677 has_reduced_clock ? &reduced_clock : NULL,
4678 num_connectors);
79e53945
JB		 4679
4680 /* setup pipeconf */
5eddb70b 4681 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4682
4683 /* Set up the display plane register */
4684 dspcntr = DISPPLANE_GAMMA_ENABLE;
4685
929c77fb
EA		 4686 if (pipe == 0)
4687 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4688 else
4689 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4690
a6c45cf0 4691 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4692 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4693 * core speed.
4694 *
4695 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4696 * pipe == 0 check?
4697 */
e70236a8
JB		 4698 if (mode->clock >
4699 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4700 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4701 else
5eddb70b 4702 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4703 }
4704
3b5c78a3
AJ		 4705 /* default to 8bpc */
4706 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4707 if (is_dp) {
0c96c65b 4708 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4709 pipeconf |= PIPECONF_BPP_6 |
4710 PIPECONF_DITHER_EN |
4711 PIPECONF_DITHER_TYPE_SP;
4712 }
4713 }
4714
19c03924
GB		 4715 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4716 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4717 pipeconf |= PIPECONF_BPP_6 |
4718 PIPECONF_ENABLE |
4719 I965_PIPECONF_ACTIVE;
4720 }
4721 }
4722
28c97730 4723 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4724 drm_mode_debug_printmodeline(mode);
4725
a7516a05
JB		 4726 if (HAS_PIPE_CXSR(dev)) {
4727 if (intel_crtc->lowfreq_avail) {
28c97730 4728 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4729 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4730 } else {
28c97730 4731 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4732 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4733 }
4734 }
4735
617cf884 4736 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4737 if (!IS_GEN2(dev) &&
b0e77b9c 4738 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4739 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4740 else
617cf884 4741 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4742
b0e77b9c 4743 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4744
4745 /* pipesrc and dspsize control the size that is scaled from,
4746 * which should always be the user's requested size.
79e53945 4747 */
929c77fb
EA		 4748 I915_WRITE(DSPSIZE(plane),
4749 ((mode->vdisplay - 1) << 16) |
4750 (mode->hdisplay - 1));
4751 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4752
f564048e
EA		 4753 I915_WRITE(PIPECONF(pipe), pipeconf);
4754 POSTING_READ(PIPECONF(pipe));
929c77fb 4755 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4756
4757 intel_wait_for_vblank(dev, pipe);
4758
f564048e
EA		 4759 I915_WRITE(DSPCNTR(plane), dspcntr);
4760 POSTING_READ(DSPCNTR(plane));
4761
94352cf9 4762 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4763
4764 intel_update_watermarks(dev);
4765
f564048e
EA		 4766 return ret;
4767}
4768
9fb526db
KP		 4769/*
4770 * Initialize reference clocks when the driver loads
4771 */
4772void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4773{
4774 struct drm_i915_private *dev_priv = dev->dev_private;
4775 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4776 struct intel_encoder *encoder;
13d83a67
JB		 4777 u32 temp;
4778 bool has_lvds = false;
199e5d79
KP		 4779 bool has_cpu_edp = false;
4780 bool has_pch_edp = false;
4781 bool has_panel = false;
99eb6a01
KP		 4782 bool has_ck505 = false;
4783 bool can_ssc = false;
13d83a67
JB		 4784
4785 /* We need to take the global config into account */
199e5d79
KP		 4786 list_for_each_entry(encoder, &mode_config->encoder_list,
4787 base.head) {
4788 switch (encoder->type) {
4789 case INTEL_OUTPUT_LVDS:
4790 has_panel = true;
4791 has_lvds = true;
4792 break;
4793 case INTEL_OUTPUT_EDP:
4794 has_panel = true;
4795 if (intel_encoder_is_pch_edp(&encoder->base))
4796 has_pch_edp = true;
4797 else
4798 has_cpu_edp = true;
4799 break;
13d83a67
JB		 4800 }
4801 }
4802
99eb6a01
KP		 4803 if (HAS_PCH_IBX(dev)) {
4804 has_ck505 = dev_priv->display_clock_mode;
4805 can_ssc = has_ck505;
4806 } else {
4807 has_ck505 = false;
4808 can_ssc = true;
4809 }
4810
4811 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4812 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4813 has_ck505);
13d83a67
JB		 4814
4815 /* Ironlake: try to setup display ref clock before DPLL
4816 * enabling. This is only under driver's control after
4817 * PCH B stepping, previous chipset stepping should be
4818 * ignoring this setting.
4819 */
4820 temp = I915_READ(PCH_DREF_CONTROL);
4821 /* Always enable nonspread source */
4822 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4823
99eb6a01
KP		 4824 if (has_ck505)
4825 temp |= DREF_NONSPREAD_CK505_ENABLE;
4826 else
4827 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4828
199e5d79
KP		 4829 if (has_panel) {
4830 temp &= ~DREF_SSC_SOURCE_MASK;
4831 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4832
199e5d79 4833 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4834 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4835 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4836 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4837 } else
4838 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4839
4840 /* Get SSC going before enabling the outputs */
4841 I915_WRITE(PCH_DREF_CONTROL, temp);
4842 POSTING_READ(PCH_DREF_CONTROL);
4843 udelay(200);
4844
13d83a67
JB		 4845 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4846
4847 /* Enable CPU source on CPU attached eDP */
199e5d79 4848 if (has_cpu_edp) {
99eb6a01 4849 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4850 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4851 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4852 }
13d83a67
JB		 4853 else
4854 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4855 } else
4856 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4857
4858 I915_WRITE(PCH_DREF_CONTROL, temp);
4859 POSTING_READ(PCH_DREF_CONTROL);
4860 udelay(200);
4861 } else {
4862 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4863
4864 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4865
4866 /* Turn off CPU output */
4867 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4868
4869 I915_WRITE(PCH_DREF_CONTROL, temp);
4870 POSTING_READ(PCH_DREF_CONTROL);
4871 udelay(200);
4872
4873 /* Turn off the SSC source */
4874 temp &= ~DREF_SSC_SOURCE_MASK;
4875 temp |= DREF_SSC_SOURCE_DISABLE;
4876
4877 /* Turn off SSC1 */
4878 temp &= ~ DREF_SSC1_ENABLE;
4879
13d83a67
JB		 4880 I915_WRITE(PCH_DREF_CONTROL, temp);
4881 POSTING_READ(PCH_DREF_CONTROL);
4882 udelay(200);
4883 }
4884}
4885
d9d444cb
JB		 4886static int ironlake_get_refclk(struct drm_crtc *crtc)
4887{
4888 struct drm_device *dev = crtc->dev;
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 struct intel_encoder *encoder;
d9d444cb
JB		 4891 struct intel_encoder *edp_encoder = NULL;
4892 int num_connectors = 0;
4893 bool is_lvds = false;
4894
6c2b7c12 4895 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4896 switch (encoder->type) {
4897 case INTEL_OUTPUT_LVDS:
4898 is_lvds = true;
4899 break;
4900 case INTEL_OUTPUT_EDP:
4901 edp_encoder = encoder;
4902 break;
4903 }
4904 num_connectors++;
4905 }
4906
4907 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4908 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4909 dev_priv->lvds_ssc_freq);
4910 return dev_priv->lvds_ssc_freq * 1000;
4911 }
4912
4913 return 120000;
4914}
4915
c8203565
PZ		 4916static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4917 struct drm_display_mode *adjusted_mode,
4918 bool dither)
4919{
4920 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4922 int pipe = intel_crtc->pipe;
4923 uint32_t val;
4924
4925 val = I915_READ(PIPECONF(pipe));
4926
4927 val &= ~PIPE_BPC_MASK;
4928 switch (intel_crtc->bpp) {
4929 case 18:
4930 val |= PIPE_6BPC;
4931 break;
4932 case 24:
4933 val |= PIPE_8BPC;
4934 break;
4935 case 30:
4936 val |= PIPE_10BPC;
4937 break;
4938 case 36:
4939 val |= PIPE_12BPC;
4940 break;
4941 default:
cc769b62
PZ		 4942 /* Case prevented by intel_choose_pipe_bpp_dither. */
4943 BUG();
c8203565
PZ		 4944 }
4945
4946 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4947 if (dither)
4948 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4949
4950 val &= ~PIPECONF_INTERLACE_MASK;
4951 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4952 val |= PIPECONF_INTERLACED_ILK;
4953 else
4954 val |= PIPECONF_PROGRESSIVE;
4955
4956 I915_WRITE(PIPECONF(pipe), val);
4957 POSTING_READ(PIPECONF(pipe));
4958}
4959
ee2b0b38
PZ		 4960static void haswell_set_pipeconf(struct drm_crtc *crtc,
4961 struct drm_display_mode *adjusted_mode,
4962 bool dither)
4963{
4964 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 4966 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 4967 uint32_t val;
4968
702e7a56 4969 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4970
4971 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4972 if (dither)
4973 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4974
4975 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4976 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4977 val |= PIPECONF_INTERLACED_ILK;
4978 else
4979 val |= PIPECONF_PROGRESSIVE;
4980
702e7a56
PZ		 4981 I915_WRITE(PIPECONF(cpu_transcoder), val);
4982 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4983}
4984
6591c6e4
PZ		 4985static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4986 struct drm_display_mode *adjusted_mode,
4987 intel_clock_t *clock,
4988 bool *has_reduced_clock,
4989 intel_clock_t *reduced_clock)
4990{
4991 struct drm_device *dev = crtc->dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct intel_encoder *intel_encoder;
4994 int refclk;
4995 const intel_limit_t *limit;
4996 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4997
4998 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4999 switch (intel_encoder->type) {
5000 case INTEL_OUTPUT_LVDS:
5001 is_lvds = true;
5002 break;
5003 case INTEL_OUTPUT_SDVO:
5004 case INTEL_OUTPUT_HDMI:
5005 is_sdvo = true;
5006 if (intel_encoder->needs_tv_clock)
5007 is_tv = true;
5008 break;
5009 case INTEL_OUTPUT_TVOUT:
5010 is_tv = true;
5011 break;
5012 }
5013 }
5014
5015 refclk = ironlake_get_refclk(crtc);
5016
5017 /*
5018 * Returns a set of divisors for the desired target clock with the given
5019 * refclk, or FALSE. The returned values represent the clock equation:
5020 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5021 */
5022 limit = intel_limit(crtc, refclk);
5023 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5024 clock);
5025 if (!ret)
5026 return false;
5027
5028 if (is_lvds && dev_priv->lvds_downclock_avail) {
5029 /*
5030 * Ensure we match the reduced clock's P to the target clock.
5031 * If the clocks don't match, we can't switch the display clock
5032 * by using the FP0/FP1. In such case we will disable the LVDS
5033 * downclock feature.
5034 */
5035 *has_reduced_clock = limit->find_pll(limit, crtc,
5036 dev_priv->lvds_downclock,
5037 refclk,
5038 clock,
5039 reduced_clock);
5040 }
5041
5042 if (is_sdvo && is_tv)
5043 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5044
5045 return true;
5046}
5047
01a415fd
DV		 5048static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5049{
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5051 uint32_t temp;
5052
5053 temp = I915_READ(SOUTH_CHICKEN1);
5054 if (temp & FDI_BC_BIFURCATION_SELECT)
5055 return;
5056
5057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5058 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5059
5060 temp |= FDI_BC_BIFURCATION_SELECT;
5061 DRM_DEBUG_KMS("enabling fdi C rx\n");
5062 I915_WRITE(SOUTH_CHICKEN1, temp);
5063 POSTING_READ(SOUTH_CHICKEN1);
5064}
5065
5066static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5067{
5068 struct drm_device *dev = intel_crtc->base.dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 struct intel_crtc *pipe_B_crtc =
5071 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5072
5073 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5074 intel_crtc->pipe, intel_crtc->fdi_lanes);
5075 if (intel_crtc->fdi_lanes > 4) {
5076 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5077 intel_crtc->pipe, intel_crtc->fdi_lanes);
5078 /* Clamp lanes to avoid programming the hw with bogus values. */
5079 intel_crtc->fdi_lanes = 4;
5080
5081 return false;
5082 }
5083
5084 if (dev_priv->num_pipe == 2)
5085 return true;
5086
5087 switch (intel_crtc->pipe) {
5088 case PIPE_A:
5089 return true;
5090 case PIPE_B:
5091 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5092 intel_crtc->fdi_lanes > 2) {
5093 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5094 intel_crtc->pipe, intel_crtc->fdi_lanes);
5095 /* Clamp lanes to avoid programming the hw with bogus values. */
5096 intel_crtc->fdi_lanes = 2;
5097
5098 return false;
5099 }
5100
5101 if (intel_crtc->fdi_lanes > 2)
5102 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5103 else
5104 cpt_enable_fdi_bc_bifurcation(dev);
5105
5106 return true;
5107 case PIPE_C:
5108 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5109 if (intel_crtc->fdi_lanes > 2) {
5110 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5111 intel_crtc->pipe, intel_crtc->fdi_lanes);
5112 /* Clamp lanes to avoid programming the hw with bogus values. */
5113 intel_crtc->fdi_lanes = 2;
5114
5115 return false;
5116 }
5117 } else {
5118 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5119 return false;
5120 }
5121
5122 cpt_enable_fdi_bc_bifurcation(dev);
5123
5124 return true;
5125 default:
5126 BUG();
5127 }
5128}
5129
f48d8f23
PZ		 5130static void ironlake_set_m_n(struct drm_crtc *crtc,
5131 struct drm_display_mode *mode,
5132 struct drm_display_mode *adjusted_mode)
5133{
5134 struct drm_device *dev = crtc->dev;
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5137 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5138 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5139 struct fdi_m_n m_n = {0};
5140 int target_clock, pixel_multiplier, lane, link_bw;
5141 bool is_dp = false, is_cpu_edp = false;
5142
5143 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5144 switch (intel_encoder->type) {
5145 case INTEL_OUTPUT_DISPLAYPORT:
5146 is_dp = true;
5147 break;
5148 case INTEL_OUTPUT_EDP:
5149 is_dp = true;
5150 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5151 is_cpu_edp = true;
5152 edp_encoder = intel_encoder;
5153 break;
5154 }
5155 }
5156
5157 /* FDI link */
5158 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5159 lane = 0;
5160 /* CPU eDP doesn't require FDI link, so just set DP M/N
5161 according to current link config */
5162 if (is_cpu_edp) {
5163 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5164 } else {
5165 /* FDI is a binary signal running at ~2.7GHz, encoding
5166 * each output octet as 10 bits. The actual frequency
5167 * is stored as a divider into a 100MHz clock, and the
5168 * mode pixel clock is stored in units of 1KHz.
5169 * Hence the bw of each lane in terms of the mode signal
5170 * is:
5171 */
5172 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5173 }
5174
5175 /* [e]DP over FDI requires target mode clock instead of link clock. */
5176 if (edp_encoder)
5177 target_clock = intel_edp_target_clock(edp_encoder, mode);
5178 else if (is_dp)
5179 target_clock = mode->clock;
5180 else
5181 target_clock = adjusted_mode->clock;
5182
5183 if (!lane) {
5184 /*
5185 * Account for spread spectrum to avoid
5186 * oversubscribing the link. Max center spread
5187 * is 2.5%; use 5% for safety's sake.
5188 */
5189 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5190 lane = bps / (link_bw * 8) + 1;
5191 }
5192
5193 intel_crtc->fdi_lanes = lane;
5194
5195 if (pixel_multiplier > 1)
5196 link_bw *= pixel_multiplier;
5197 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5198 &m_n);
5199
afe2fcf5
PZ		 5200 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5201 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5202 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5203 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5204}
5205
de13a2e3
PZ		 5206static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5207 struct drm_display_mode *adjusted_mode,
5208 intel_clock_t *clock, u32 fp)
79e53945 5209{
de13a2e3 5210 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5211 struct drm_device *dev = crtc->dev;
5212 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5213 struct intel_encoder *intel_encoder;
5214 uint32_t dpll;
5215 int factor, pixel_multiplier, num_connectors = 0;
5216 bool is_lvds = false, is_sdvo = false, is_tv = false;
5217 bool is_dp = false, is_cpu_edp = false;
79e53945 5218
de13a2e3
PZ		 5219 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5220 switch (intel_encoder->type) {
79e53945
JB		 5221 case INTEL_OUTPUT_LVDS:
5222 is_lvds = true;
5223 break;
5224 case INTEL_OUTPUT_SDVO:
7d57382e 5225 case INTEL_OUTPUT_HDMI:
79e53945 5226 is_sdvo = true;
de13a2e3 5227 if (intel_encoder->needs_tv_clock)
e2f0ba97 5228 is_tv = true;
79e53945 5229 break;
79e53945
JB		 5230 case INTEL_OUTPUT_TVOUT:
5231 is_tv = true;
5232 break;
a4fc5ed6
KP		 5233 case INTEL_OUTPUT_DISPLAYPORT:
5234 is_dp = true;
5235 break;
32f9d658 5236 case INTEL_OUTPUT_EDP:
e3aef172 5237 is_dp = true;
de13a2e3 5238 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5239 is_cpu_edp = true;
32f9d658 5240 break;
79e53945 5241 }
43565a06 5242
c751ce4f 5243 num_connectors++;
79e53945
JB		 5244 }
5245
c1858123 5246 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5247 factor = 21;
5248 if (is_lvds) {
5249 if ((intel_panel_use_ssc(dev_priv) &&
5250 dev_priv->lvds_ssc_freq == 100) ||
5251 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5252 factor = 25;
5253 } else if (is_sdvo && is_tv)
5254 factor = 20;
c1858123 5255
de13a2e3 5256 if (clock->m < factor * clock->n)
8febb297 5257 fp |= FP_CB_TUNE;
2c07245f 5258
5eddb70b 5259 dpll = 0;
2c07245f 5260
a07d6787
EA		 5261 if (is_lvds)
5262 dpll |= DPLLB_MODE_LVDS;
5263 else
5264 dpll |= DPLLB_MODE_DAC_SERIAL;
5265 if (is_sdvo) {
de13a2e3 5266 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5267 if (pixel_multiplier > 1) {
5268 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5269 }
a07d6787
EA		 5270 dpll |= DPLL_DVO_HIGH_SPEED;
5271 }
e3aef172 5272 if (is_dp && !is_cpu_edp)
a07d6787 5273 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5274
a07d6787 5275 /* compute bitmask from p1 value */
de13a2e3 5276 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5277 /* also FPA1 */
de13a2e3 5278 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5279
de13a2e3 5280 switch (clock->p2) {
a07d6787
EA		 5281 case 5:
5282 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5283 break;
5284 case 7:
5285 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5286 break;
5287 case 10:
5288 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5289 break;
5290 case 14:
5291 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5292 break;
79e53945
JB		 5293 }
5294
43565a06
KH		 5295 if (is_sdvo && is_tv)
5296 dpll |= PLL_REF_INPUT_TVCLKINBC;
5297 else if (is_tv)
79e53945 5298 /* XXX: just matching BIOS for now */
43565a06 5299 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5300 dpll |= 3;
a7615030 5301 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5302 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5303 else
5304 dpll |= PLL_REF_INPUT_DREFCLK;
5305
de13a2e3
PZ		 5306 return dpll;
5307}
5308
5309static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5310 struct drm_display_mode *mode,
5311 struct drm_display_mode *adjusted_mode,
5312 int x, int y,
5313 struct drm_framebuffer *fb)
5314{
5315 struct drm_device *dev = crtc->dev;
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5318 int pipe = intel_crtc->pipe;
5319 int plane = intel_crtc->plane;
5320 int num_connectors = 0;
5321 intel_clock_t clock, reduced_clock;
5322 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5323 bool ok, has_reduced_clock = false;
5324 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5325 struct intel_encoder *encoder;
5326 u32 temp;
5327 int ret;
01a415fd 5328 bool dither, fdi_config_ok;
de13a2e3
PZ		 5329
5330 for_each_encoder_on_crtc(dev, crtc, encoder) {
5331 switch (encoder->type) {
5332 case INTEL_OUTPUT_LVDS:
5333 is_lvds = true;
5334 break;
de13a2e3
PZ		 5335 case INTEL_OUTPUT_DISPLAYPORT:
5336 is_dp = true;
5337 break;
5338 case INTEL_OUTPUT_EDP:
5339 is_dp = true;
e2f12b07 5340 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5341 is_cpu_edp = true;
5342 break;
5343 }
5344
5345 num_connectors++;
5346 }
5347
5dc5298b
PZ		 5348 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5349 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5350
de13a2e3
PZ		 5351 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5352 &has_reduced_clock, &reduced_clock);
5353 if (!ok) {
5354 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5355 return -EINVAL;
5356 }
5357
5358 /* Ensure that the cursor is valid for the new mode before changing... */
5359 intel_crtc_update_cursor(crtc, true);
5360
5361 /* determine panel color depth */
c8241969
JN		 5362 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5363 adjusted_mode);
de13a2e3
PZ		 5364 if (is_lvds && dev_priv->lvds_dither)
5365 dither = true;
5366
5367 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5368 if (has_reduced_clock)
5369 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5370 reduced_clock.m2;
5371
5372 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5373
f7cb34d4 5374 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5375 drm_mode_debug_printmodeline(mode);
5376
5dc5298b
PZ		 5377 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5378 if (!is_cpu_edp) {
ee7b9f93 5379 struct intel_pch_pll *pll;
4b645f14 5380
ee7b9f93
JB		 5381 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5382 if (pll == NULL) {
5383 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5384 pipe);
4b645f14
JB		 5385 return -EINVAL;
5386 }
ee7b9f93
JB		 5387 } else
5388 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5389
5390 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5391 * This is an exception to the general rule that mode_set doesn't turn
5392 * things on.
5393 */
5394 if (is_lvds) {
fae14981 5395 temp = I915_READ(PCH_LVDS);
5eddb70b 5396 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5397 if (HAS_PCH_CPT(dev)) {
5398 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5399 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5400 } else {
5401 if (pipe == 1)
5402 temp |= LVDS_PIPEB_SELECT;
5403 else
5404 temp &= ~LVDS_PIPEB_SELECT;
5405 }
4b645f14 5406
a3e17eb8 5407 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5408 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5409 /* Set the B0-B3 data pairs corresponding to whether we're going to
5410 * set the DPLLs for dual-channel mode or not.
5411 */
5412 if (clock.p2 == 7)
5eddb70b 5413 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5414 else
5eddb70b 5415 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5416
5417 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5418 * appropriately here, but we need to look more thoroughly into how
5419 * panels behave in the two modes.
5420 */
284d5df5 5421 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5422 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5423 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5424 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5425 temp |= LVDS_VSYNC_POLARITY;
fae14981 5426 I915_WRITE(PCH_LVDS, temp);
79e53945 5427 }
434ed097 5428
e3aef172 5429 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5430 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5431 } else {
8db9d77b 5432 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5433 I915_WRITE(TRANSDATA_M1(pipe), 0);
5434 I915_WRITE(TRANSDATA_N1(pipe), 0);
5435 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5436 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5437 }
79e53945 5438
ee7b9f93
JB		 5439 if (intel_crtc->pch_pll) {
5440 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5441
32f9d658 5442 /* Wait for the clocks to stabilize. */
ee7b9f93 5443 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5444 udelay(150);
5445
8febb297
EA		 5446 /* The pixel multiplier can only be updated once the
5447 * DPLL is enabled and the clocks are stable.
5448 *
5449 * So write it again.
5450 */
ee7b9f93 5451 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5452 }
79e53945 5453
5eddb70b 5454 intel_crtc->lowfreq_avail = false;
ee7b9f93 5455 if (intel_crtc->pch_pll) {
4b645f14 5456 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5457 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5458 intel_crtc->lowfreq_avail = true;
4b645f14 5459 } else {
ee7b9f93 5460 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5461 }
5462 }
5463
b0e77b9c 5464 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5465
01a415fd
DV		 5466 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5467 * ironlake_check_fdi_lanes. */
f48d8f23 5468 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5469
01a415fd
DV		 5470 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5471
e3aef172 5472 if (is_cpu_edp)
8febb297 5473 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5474
c8203565 5475 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5476
9d0498a2 5477 intel_wait_for_vblank(dev, pipe);
79e53945 5478
a1f9e77e
PZ		 5479 /* Set up the display plane register */
5480 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5481 POSTING_READ(DSPCNTR(plane));
79e53945 5482
94352cf9 5483 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5484
5485 intel_update_watermarks(dev);
5486
1f8eeabf
ED		 5487 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5488
01a415fd 5489 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5490}
5491
09b4ddf9
PZ		 5492static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5493 struct drm_display_mode *mode,
5494 struct drm_display_mode *adjusted_mode,
5495 int x, int y,
5496 struct drm_framebuffer *fb)
5497{
5498 struct drm_device *dev = crtc->dev;
5499 struct drm_i915_private *dev_priv = dev->dev_private;
5500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5501 int pipe = intel_crtc->pipe;
5502 int plane = intel_crtc->plane;
5503 int num_connectors = 0;
5504 intel_clock_t clock, reduced_clock;
5dc5298b 5505 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5506 bool ok, has_reduced_clock = false;
5507 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5508 struct intel_encoder *encoder;
5509 u32 temp;
5510 int ret;
5511 bool dither;
5512
5513 for_each_encoder_on_crtc(dev, crtc, encoder) {
5514 switch (encoder->type) {
5515 case INTEL_OUTPUT_LVDS:
5516 is_lvds = true;
5517 break;
5518 case INTEL_OUTPUT_DISPLAYPORT:
5519 is_dp = true;
5520 break;
5521 case INTEL_OUTPUT_EDP:
5522 is_dp = true;
5523 if (!intel_encoder_is_pch_edp(&encoder->base))
5524 is_cpu_edp = true;
5525 break;
5526 }
5527
5528 num_connectors++;
5529 }
5530
a5c961d1
PZ		 5531 if (is_cpu_edp)
5532 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5533 else
5534 intel_crtc->cpu_transcoder = pipe;
5535
5dc5298b
PZ		 5536 /* We are not sure yet this won't happen. */
5537 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5538 INTEL_PCH_TYPE(dev));
5539
5540 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5541 num_connectors, pipe_name(pipe));
5542
702e7a56 5543 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5544 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5545
5546 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5547
6441ab5f
PZ		 5548 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5549 return -EINVAL;
5550
5dc5298b
PZ		 5551 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5552 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5553 &has_reduced_clock,
5554 &reduced_clock);
5555 if (!ok) {
5556 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5557 return -EINVAL;
5558 }
09b4ddf9
PZ		 5559 }
5560
5561 /* Ensure that the cursor is valid for the new mode before changing... */
5562 intel_crtc_update_cursor(crtc, true);
5563
5564 /* determine panel color depth */
c8241969
JN		 5565 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5566 adjusted_mode);
09b4ddf9
PZ		 5567 if (is_lvds && dev_priv->lvds_dither)
5568 dither = true;
5569
09b4ddf9
PZ		 5570 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5571 drm_mode_debug_printmodeline(mode);
5572
5dc5298b
PZ		 5573 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5574 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5575 if (has_reduced_clock)
5576 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5577 reduced_clock.m2;
5578
5579 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5580 fp);
5581
5582 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5583 * own on pre-Haswell/LPT generation */
5584 if (!is_cpu_edp) {
5585 struct intel_pch_pll *pll;
5586
5587 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5588 if (pll == NULL) {
5589 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5590 pipe);
5591 return -EINVAL;
5592 }
5593 } else
5594 intel_put_pch_pll(intel_crtc);
09b4ddf9 5595
5dc5298b
PZ		 5596 /* The LVDS pin pair needs to be on before the DPLLs are
5597 * enabled. This is an exception to the general rule that
5598 * mode_set doesn't turn things on.
5599 */
5600 if (is_lvds) {
5601 temp = I915_READ(PCH_LVDS);
5602 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5603 if (HAS_PCH_CPT(dev)) {
5604 temp &= ~PORT_TRANS_SEL_MASK;
5605 temp |= PORT_TRANS_SEL_CPT(pipe);
5606 } else {
5607 if (pipe == 1)
5608 temp |= LVDS_PIPEB_SELECT;
5609 else
5610 temp &= ~LVDS_PIPEB_SELECT;
5611 }
09b4ddf9 5612
5dc5298b
PZ		 5613 /* set the corresponsding LVDS_BORDER bit */
5614 temp |= dev_priv->lvds_border_bits;
5615 /* Set the B0-B3 data pairs corresponding to whether
5616 * we're going to set the DPLLs for dual-channel mode or
5617 * not.
5618 */
5619 if (clock.p2 == 7)
5620 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5621 else
5dc5298b
PZ		 5622 temp &= ~(LVDS_B0B3_POWER_UP |
5623 LVDS_CLKB_POWER_UP);
5624
5625 /* It would be nice to set 24 vs 18-bit mode
5626 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5627 * look more thoroughly into how panels behave in the
5628 * two modes.
5629 */
5630 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5631 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5632 temp |= LVDS_HSYNC_POLARITY;
5633 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5634 temp |= LVDS_VSYNC_POLARITY;
5635 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5636 }
09b4ddf9
PZ		 5637 }
5638
5639 if (is_dp && !is_cpu_edp) {
5640 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5641 } else {
5dc5298b
PZ		 5642 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5643 /* For non-DP output, clear any trans DP clock recovery
5644 * setting.*/
5645 I915_WRITE(TRANSDATA_M1(pipe), 0);
5646 I915_WRITE(TRANSDATA_N1(pipe), 0);
5647 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5648 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5649 }
09b4ddf9
PZ		 5650 }
5651
5652 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5653 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5654 if (intel_crtc->pch_pll) {
5655 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5656
5657 /* Wait for the clocks to stabilize. */
5658 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5659 udelay(150);
5660
5661 /* The pixel multiplier can only be updated once the
5662 * DPLL is enabled and the clocks are stable.
5663 *
5664 * So write it again.
5665 */
5666 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5667 }
5668
5669 if (intel_crtc->pch_pll) {
5670 if (is_lvds && has_reduced_clock && i915_powersave) {
5671 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5672 intel_crtc->lowfreq_avail = true;
5673 } else {
5674 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5675 }
09b4ddf9
PZ		 5676 }
5677 }
5678
5679 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5680
1eb8dfec
PZ		 5681 if (!is_dp || is_cpu_edp)
5682 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5683
5dc5298b
PZ		 5684 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5685 if (is_cpu_edp)
5686 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5687
ee2b0b38 5688 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5689
09b4ddf9
PZ		 5690 /* Set up the display plane register */
5691 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5692 POSTING_READ(DSPCNTR(plane));
5693
5694 ret = intel_pipe_set_base(crtc, x, y, fb);
5695
5696 intel_update_watermarks(dev);
5697
5698 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5699
5700 return ret;
5701}
5702
f564048e
EA		 5703static int intel_crtc_mode_set(struct drm_crtc *crtc,
5704 struct drm_display_mode *mode,
5705 struct drm_display_mode *adjusted_mode,
5706 int x, int y,
94352cf9 5707 struct drm_framebuffer *fb)
f564048e
EA		 5708{
5709 struct drm_device *dev = crtc->dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712 int pipe = intel_crtc->pipe;
f564048e
EA		 5713 int ret;
5714
0b701d27 5715 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5716
f564048e 5717 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5718 x, y, fb);
79e53945 5719 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5720
1f803ee5 5721 return ret;
79e53945
JB		 5722}
5723
3a9627f4
WF		 5724static bool intel_eld_uptodate(struct drm_connector *connector,
5725 int reg_eldv, uint32_t bits_eldv,
5726 int reg_elda, uint32_t bits_elda,
5727 int reg_edid)
5728{
5729 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5730 uint8_t *eld = connector->eld;
5731 uint32_t i;
5732
5733 i = I915_READ(reg_eldv);
5734 i &= bits_eldv;
5735
5736 if (!eld[0])
5737 return !i;
5738
5739 if (!i)
5740 return false;
5741
5742 i = I915_READ(reg_elda);
5743 i &= ~bits_elda;
5744 I915_WRITE(reg_elda, i);
5745
5746 for (i = 0; i < eld[2]; i++)
5747 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5748 return false;
5749
5750 return true;
5751}
5752
e0dac65e
WF		 5753static void g4x_write_eld(struct drm_connector *connector,
5754 struct drm_crtc *crtc)
5755{
5756 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5757 uint8_t *eld = connector->eld;
5758 uint32_t eldv;
5759 uint32_t len;
5760 uint32_t i;
5761
5762 i = I915_READ(G4X_AUD_VID_DID);
5763
5764 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5765 eldv = G4X_ELDV_DEVCL_DEVBLC;
5766 else
5767 eldv = G4X_ELDV_DEVCTG;
5768
3a9627f4
WF		 5769 if (intel_eld_uptodate(connector,
5770 G4X_AUD_CNTL_ST, eldv,
5771 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5772 G4X_HDMIW_HDMIEDID))
5773 return;
5774
e0dac65e
WF		 5775 i = I915_READ(G4X_AUD_CNTL_ST);
5776 i &= ~(eldv | G4X_ELD_ADDR);
5777 len = (i >> 9) & 0x1f; /* ELD buffer size */
5778 I915_WRITE(G4X_AUD_CNTL_ST, i);
5779
5780 if (!eld[0])
5781 return;
5782
5783 len = min_t(uint8_t, eld[2], len);
5784 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5785 for (i = 0; i < len; i++)
5786 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5787
5788 i = I915_READ(G4X_AUD_CNTL_ST);
5789 i |= eldv;
5790 I915_WRITE(G4X_AUD_CNTL_ST, i);
5791}
5792
83358c85
WX		 5793static void haswell_write_eld(struct drm_connector *connector,
5794 struct drm_crtc *crtc)
5795{
5796 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5797 uint8_t *eld = connector->eld;
5798 struct drm_device *dev = crtc->dev;
5799 uint32_t eldv;
5800 uint32_t i;
5801 int len;
5802 int pipe = to_intel_crtc(crtc)->pipe;
5803 int tmp;
5804
5805 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5806 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5807 int aud_config = HSW_AUD_CFG(pipe);
5808 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5809
5810
5811 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5812
5813 /* Audio output enable */
5814 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5815 tmp = I915_READ(aud_cntrl_st2);
5816 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5817 I915_WRITE(aud_cntrl_st2, tmp);
5818
5819 /* Wait for 1 vertical blank */
5820 intel_wait_for_vblank(dev, pipe);
5821
5822 /* Set ELD valid state */
5823 tmp = I915_READ(aud_cntrl_st2);
5824 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5825 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5826 I915_WRITE(aud_cntrl_st2, tmp);
5827 tmp = I915_READ(aud_cntrl_st2);
5828 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5829
5830 /* Enable HDMI mode */
5831 tmp = I915_READ(aud_config);
5832 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5833 /* clear N_programing_enable and N_value_index */
5834 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5835 I915_WRITE(aud_config, tmp);
5836
5837 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5838
5839 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5840
5841 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5842 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5843 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5844 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5845 } else
5846 I915_WRITE(aud_config, 0);
5847
5848 if (intel_eld_uptodate(connector,
5849 aud_cntrl_st2, eldv,
5850 aud_cntl_st, IBX_ELD_ADDRESS,
5851 hdmiw_hdmiedid))
5852 return;
5853
5854 i = I915_READ(aud_cntrl_st2);
5855 i &= ~eldv;
5856 I915_WRITE(aud_cntrl_st2, i);
5857
5858 if (!eld[0])
5859 return;
5860
5861 i = I915_READ(aud_cntl_st);
5862 i &= ~IBX_ELD_ADDRESS;
5863 I915_WRITE(aud_cntl_st, i);
5864 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5865 DRM_DEBUG_DRIVER("port num:%d\n", i);
5866
5867 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5868 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5869 for (i = 0; i < len; i++)
5870 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5871
5872 i = I915_READ(aud_cntrl_st2);
5873 i |= eldv;
5874 I915_WRITE(aud_cntrl_st2, i);
5875
5876}
5877
e0dac65e
WF		 5878static void ironlake_write_eld(struct drm_connector *connector,
5879 struct drm_crtc *crtc)
5880{
5881 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5882 uint8_t *eld = connector->eld;
5883 uint32_t eldv;
5884 uint32_t i;
5885 int len;
5886 int hdmiw_hdmiedid;
b6daa025 5887 int aud_config;
e0dac65e
WF		 5888 int aud_cntl_st;
5889 int aud_cntrl_st2;
9b138a83 5890 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5891
b3f33cbf 5892 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5893 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5894 aud_config = IBX_AUD_CFG(pipe);
5895 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5896 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5897 } else {
9b138a83
WX		 5898 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5899 aud_config = CPT_AUD_CFG(pipe);
5900 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5901 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5902 }
5903
9b138a83 5904 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5905
5906 i = I915_READ(aud_cntl_st);
9b138a83 5907 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5908 if (!i) {
5909 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5910 /* operate blindly on all ports */
1202b4c6
WF		 5911 eldv = IBX_ELD_VALIDB;
5912 eldv |= IBX_ELD_VALIDB << 4;
5913 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5914 } else {
5915 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5916 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5917 }
5918
3a9627f4
WF		 5919 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5920 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5921 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5922 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5923 } else
5924 I915_WRITE(aud_config, 0);
e0dac65e 5925
3a9627f4
WF		 5926 if (intel_eld_uptodate(connector,
5927 aud_cntrl_st2, eldv,
5928 aud_cntl_st, IBX_ELD_ADDRESS,
5929 hdmiw_hdmiedid))
5930 return;
5931
e0dac65e
WF		 5932 i = I915_READ(aud_cntrl_st2);
5933 i &= ~eldv;
5934 I915_WRITE(aud_cntrl_st2, i);
5935
5936 if (!eld[0])
5937 return;
5938
e0dac65e 5939 i = I915_READ(aud_cntl_st);
1202b4c6 5940 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5941 I915_WRITE(aud_cntl_st, i);
5942
5943 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5944 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5945 for (i = 0; i < len; i++)
5946 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5947
5948 i = I915_READ(aud_cntrl_st2);
5949 i |= eldv;
5950 I915_WRITE(aud_cntrl_st2, i);
5951}
5952
5953void intel_write_eld(struct drm_encoder *encoder,
5954 struct drm_display_mode *mode)
5955{
5956 struct drm_crtc *crtc = encoder->crtc;
5957 struct drm_connector *connector;
5958 struct drm_device *dev = encoder->dev;
5959 struct drm_i915_private *dev_priv = dev->dev_private;
5960
5961 connector = drm_select_eld(encoder, mode);
5962 if (!connector)
5963 return;
5964
5965 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5966 connector->base.id,
5967 drm_get_connector_name(connector),
5968 connector->encoder->base.id,
5969 drm_get_encoder_name(connector->encoder));
5970
5971 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5972
5973 if (dev_priv->display.write_eld)
5974 dev_priv->display.write_eld(connector, crtc);
5975}
5976
79e53945
JB		 5977/** Loads the palette/gamma unit for the CRTC with the prepared values */
5978void intel_crtc_load_lut(struct drm_crtc *crtc)
5979{
5980 struct drm_device *dev = crtc->dev;
5981 struct drm_i915_private *dev_priv = dev->dev_private;
5982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5983 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5984 int i;
5985
5986 /* The clocks have to be on to load the palette. */
aed3f09d 5987 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5988 return;
5989
f2b115e6 5990 /* use legacy palette for Ironlake */
bad720ff 5991 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5992 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5993
79e53945
JB		 5994 for (i = 0; i < 256; i++) {
5995 I915_WRITE(palreg + 4 * i,
5996 (intel_crtc->lut_r[i] << 16) |
5997 (intel_crtc->lut_g[i] << 8) |
5998 intel_crtc->lut_b[i]);
5999 }
6000}
6001
560b85bb
CW		 6002static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6003{
6004 struct drm_device *dev = crtc->dev;
6005 struct drm_i915_private *dev_priv = dev->dev_private;
6006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6007 bool visible = base != 0;
6008 u32 cntl;
6009
6010 if (intel_crtc->cursor_visible == visible)
6011 return;
6012
9db4a9c7 6013 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6014 if (visible) {
6015 /* On these chipsets we can only modify the base whilst
6016 * the cursor is disabled.
6017 */
9db4a9c7 6018 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6019
6020 cntl &= ~(CURSOR_FORMAT_MASK);
6021 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6022 cntl |= CURSOR_ENABLE |
6023 CURSOR_GAMMA_ENABLE |
6024 CURSOR_FORMAT_ARGB;
6025 } else
6026 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6027 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6028
6029 intel_crtc->cursor_visible = visible;
6030}
6031
6032static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6033{
6034 struct drm_device *dev = crtc->dev;
6035 struct drm_i915_private *dev_priv = dev->dev_private;
6036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6037 int pipe = intel_crtc->pipe;
6038 bool visible = base != 0;
6039
6040 if (intel_crtc->cursor_visible != visible) {
548f245b 6041 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6042 if (base) {
6043 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6044 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6045 cntl |= pipe << 28; /* Connect to correct pipe */
6046 } else {
6047 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6048 cntl |= CURSOR_MODE_DISABLE;
6049 }
9db4a9c7 6050 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6051
6052 intel_crtc->cursor_visible = visible;
6053 }
6054 /* and commit changes on next vblank */
9db4a9c7 6055 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6056}
6057
65a21cd6
JB		 6058static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6059{
6060 struct drm_device *dev = crtc->dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6063 int pipe = intel_crtc->pipe;
6064 bool visible = base != 0;
6065
6066 if (intel_crtc->cursor_visible != visible) {
6067 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6068 if (base) {
6069 cntl &= ~CURSOR_MODE;
6070 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6071 } else {
6072 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6073 cntl |= CURSOR_MODE_DISABLE;
6074 }
6075 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6076
6077 intel_crtc->cursor_visible = visible;
6078 }
6079 /* and commit changes on next vblank */
6080 I915_WRITE(CURBASE_IVB(pipe), base);
6081}
6082
cda4b7d3 6083/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6084static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6085 bool on)
cda4b7d3
CW		 6086{
6087 struct drm_device *dev = crtc->dev;
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090 int pipe = intel_crtc->pipe;
6091 int x = intel_crtc->cursor_x;
6092 int y = intel_crtc->cursor_y;
560b85bb 6093 u32 base, pos;
cda4b7d3
CW		 6094 bool visible;
6095
6096 pos = 0;
6097
6b383a7f 6098 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6099 base = intel_crtc->cursor_addr;
6100 if (x > (int) crtc->fb->width)
6101 base = 0;
6102
6103 if (y > (int) crtc->fb->height)
6104 base = 0;
6105 } else
6106 base = 0;
6107
6108 if (x < 0) {
6109 if (x + intel_crtc->cursor_width < 0)
6110 base = 0;
6111
6112 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6113 x = -x;
6114 }
6115 pos |= x << CURSOR_X_SHIFT;
6116
6117 if (y < 0) {
6118 if (y + intel_crtc->cursor_height < 0)
6119 base = 0;
6120
6121 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6122 y = -y;
6123 }
6124 pos |= y << CURSOR_Y_SHIFT;
6125
6126 visible = base != 0;
560b85bb 6127 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6128 return;
6129
0cd83aa9 6130 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6131 I915_WRITE(CURPOS_IVB(pipe), pos);
6132 ivb_update_cursor(crtc, base);
6133 } else {
6134 I915_WRITE(CURPOS(pipe), pos);
6135 if (IS_845G(dev) || IS_I865G(dev))
6136 i845_update_cursor(crtc, base);
6137 else
6138 i9xx_update_cursor(crtc, base);
6139 }
cda4b7d3
CW		 6140}
6141
79e53945 6142static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6143 struct drm_file *file,
79e53945
JB		 6144 uint32_t handle,
6145 uint32_t width, uint32_t height)
6146{
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6150 struct drm_i915_gem_object *obj;
cda4b7d3 6151 uint32_t addr;
3f8bc370 6152 int ret;
79e53945 6153
79e53945
JB		 6154 /* if we want to turn off the cursor ignore width and height */
6155 if (!handle) {
28c97730 6156 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6157 addr = 0;
05394f39 6158 obj = NULL;
5004417d 6159 mutex_lock(&dev->struct_mutex);
3f8bc370 6160 goto finish;
79e53945
JB		 6161 }
6162
6163 /* Currently we only support 64x64 cursors */
6164 if (width != 64 || height != 64) {
6165 DRM_ERROR("we currently only support 64x64 cursors\n");
6166 return -EINVAL;
6167 }
6168
05394f39 6169 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6170 if (&obj->base == NULL)
79e53945
JB		 6171 return -ENOENT;
6172
05394f39 6173 if (obj->base.size < width * height * 4) {
79e53945 6174 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6175 ret = -ENOMEM;
6176 goto fail;
79e53945
JB		 6177 }
6178
71acb5eb 6179 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6180 mutex_lock(&dev->struct_mutex);
b295d1b6 6181 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6182 if (obj->tiling_mode) {
6183 DRM_ERROR("cursor cannot be tiled\n");
6184 ret = -EINVAL;
6185 goto fail_locked;
6186 }
6187
2da3b9b9 6188 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6189 if (ret) {
6190 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6191 goto fail_locked;
e7b526bb
CW		 6192 }
6193
d9e86c0e
CW		 6194 ret = i915_gem_object_put_fence(obj);
6195 if (ret) {
2da3b9b9 6196 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6197 goto fail_unpin;
6198 }
6199
05394f39 6200 addr = obj->gtt_offset;
71acb5eb 6201 } else {
6eeefaf3 6202 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6203 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6204 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6205 align);
71acb5eb
DA		 6206 if (ret) {
6207 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6208 goto fail_locked;
71acb5eb 6209 }
05394f39 6210 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6211 }
6212
a6c45cf0 6213 if (IS_GEN2(dev))
14b60391
JB		 6214 I915_WRITE(CURSIZE, (height << 12) | width);
6215
3f8bc370 6216 finish:
3f8bc370 6217 if (intel_crtc->cursor_bo) {
b295d1b6 6218 if (dev_priv->info->cursor_needs_physical) {
05394f39 6219 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6220 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6221 } else
6222 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6223 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6224 }
80824003 6225
7f9872e0 6226 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6227
6228 intel_crtc->cursor_addr = addr;
05394f39 6229 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6230 intel_crtc->cursor_width = width;
6231 intel_crtc->cursor_height = height;
6232
6b383a7f 6233 intel_crtc_update_cursor(crtc, true);
3f8bc370 6234
79e53945 6235 return 0;
e7b526bb 6236fail_unpin:
05394f39 6237 i915_gem_object_unpin(obj);
7f9872e0 6238fail_locked:
34b8686e 6239 mutex_unlock(&dev->struct_mutex);
bc9025bd 6240fail:
05394f39 6241 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6242 return ret;
79e53945
JB		 6243}
6244
6245static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6246{
79e53945 6247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6248
cda4b7d3
CW		 6249 intel_crtc->cursor_x = x;
6250 intel_crtc->cursor_y = y;
652c393a 6251
6b383a7f 6252 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6253
6254 return 0;
6255}
6256
6257/** Sets the color ramps on behalf of RandR */
6258void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6259 u16 blue, int regno)
6260{
6261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6262
6263 intel_crtc->lut_r[regno] = red >> 8;
6264 intel_crtc->lut_g[regno] = green >> 8;
6265 intel_crtc->lut_b[regno] = blue >> 8;
6266}
6267
b8c00ac5
DA		 6268void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6269 u16 *blue, int regno)
6270{
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272
6273 *red = intel_crtc->lut_r[regno] << 8;
6274 *green = intel_crtc->lut_g[regno] << 8;
6275 *blue = intel_crtc->lut_b[regno] << 8;
6276}
6277
79e53945 6278static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6279 u16 *blue, uint32_t start, uint32_t size)
79e53945 6280{
7203425a 6281 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6283
7203425a 6284 for (i = start; i < end; i++) {
79e53945
JB		 6285 intel_crtc->lut_r[i] = red[i] >> 8;
6286 intel_crtc->lut_g[i] = green[i] >> 8;
6287 intel_crtc->lut_b[i] = blue[i] >> 8;
6288 }
6289
6290 intel_crtc_load_lut(crtc);
6291}
6292
6293/**
6294 * Get a pipe with a simple mode set on it for doing load-based monitor
6295 * detection.
6296 *
6297 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6298 * its requirements. The pipe will be connected to no other encoders.
79e53945 6299 *
c751ce4f 6300 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6301 * configured for it. In the future, it could choose to temporarily disable
6302 * some outputs to free up a pipe for its use.
6303 *
6304 * \return crtc, or NULL if no pipes are available.
6305 */
6306
6307/* VESA 640x480x72Hz mode to set on the pipe */
6308static struct drm_display_mode load_detect_mode = {
6309 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6310 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6311};
6312
d2dff872
CW		 6313static struct drm_framebuffer *
6314intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6315 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6316 struct drm_i915_gem_object *obj)
6317{
6318 struct intel_framebuffer *intel_fb;
6319 int ret;
6320
6321 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6322 if (!intel_fb) {
6323 drm_gem_object_unreference_unlocked(&obj->base);
6324 return ERR_PTR(-ENOMEM);
6325 }
6326
6327 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6328 if (ret) {
6329 drm_gem_object_unreference_unlocked(&obj->base);
6330 kfree(intel_fb);
6331 return ERR_PTR(ret);
6332 }
6333
6334 return &intel_fb->base;
6335}
6336
6337static u32
6338intel_framebuffer_pitch_for_width(int width, int bpp)
6339{
6340 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6341 return ALIGN(pitch, 64);
6342}
6343
6344static u32
6345intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6346{
6347 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6348 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6349}
6350
6351static struct drm_framebuffer *
6352intel_framebuffer_create_for_mode(struct drm_device *dev,
6353 struct drm_display_mode *mode,
6354 int depth, int bpp)
6355{
6356 struct drm_i915_gem_object *obj;
308e5bcb 6357 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6358
6359 obj = i915_gem_alloc_object(dev,
6360 intel_framebuffer_size_for_mode(mode, bpp));
6361 if (obj == NULL)
6362 return ERR_PTR(-ENOMEM);
6363
6364 mode_cmd.width = mode->hdisplay;
6365 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6366 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6367 bpp);
5ca0c34a 6368 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6369
6370 return intel_framebuffer_create(dev, &mode_cmd, obj);
6371}
6372
6373static struct drm_framebuffer *
6374mode_fits_in_fbdev(struct drm_device *dev,
6375 struct drm_display_mode *mode)
6376{
6377 struct drm_i915_private *dev_priv = dev->dev_private;
6378 struct drm_i915_gem_object *obj;
6379 struct drm_framebuffer *fb;
6380
6381 if (dev_priv->fbdev == NULL)
6382 return NULL;
6383
6384 obj = dev_priv->fbdev->ifb.obj;
6385 if (obj == NULL)
6386 return NULL;
6387
6388 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6389 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6390 fb->bits_per_pixel))
d2dff872
CW		 6391 return NULL;
6392
01f2c773 6393 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6394 return NULL;
6395
6396 return fb;
6397}
6398
d2434ab7 6399bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6400 struct drm_display_mode *mode,
8261b191 6401 struct intel_load_detect_pipe *old)
79e53945
JB		 6402{
6403 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6404 struct intel_encoder *intel_encoder =
6405 intel_attached_encoder(connector);
79e53945 6406 struct drm_crtc *possible_crtc;
4ef69c7a 6407 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6408 struct drm_crtc *crtc = NULL;
6409 struct drm_device *dev = encoder->dev;
94352cf9 6410 struct drm_framebuffer *fb;
79e53945
JB		 6411 int i = -1;
6412
d2dff872
CW		 6413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6414 connector->base.id, drm_get_connector_name(connector),
6415 encoder->base.id, drm_get_encoder_name(encoder));
6416
79e53945
JB		 6417 /*
6418 * Algorithm gets a little messy:
7a5e4805 6419 *
79e53945
JB		 6420 * - if the connector already has an assigned crtc, use it (but make
6421 * sure it's on first)
7a5e4805 6422 *
79e53945
JB		 6423 * - try to find the first unused crtc that can drive this connector,
6424 * and use that if we find one
79e53945
JB		 6425 */
6426
6427 /* See if we already have a CRTC for this connector */
6428 if (encoder->crtc) {
6429 crtc = encoder->crtc;
8261b191 6430
24218aac 6431 old->dpms_mode = connector->dpms;
8261b191
CW		 6432 old->load_detect_temp = false;
6433
6434 /* Make sure the crtc and connector are running */
24218aac
DV		 6435 if (connector->dpms != DRM_MODE_DPMS_ON)
6436 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6437
7173188d 6438 return true;
79e53945
JB		 6439 }
6440
6441 /* Find an unused one (if possible) */
6442 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6443 i++;
6444 if (!(encoder->possible_crtcs & (1 << i)))
6445 continue;
6446 if (!possible_crtc->enabled) {
6447 crtc = possible_crtc;
6448 break;
6449 }
79e53945
JB		 6450 }
6451
6452 /*
6453 * If we didn't find an unused CRTC, don't use any.
6454 */
6455 if (!crtc) {
7173188d
CW		 6456 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6457 return false;
79e53945
JB		 6458 }
6459
fc303101
DV		 6460 intel_encoder->new_crtc = to_intel_crtc(crtc);
6461 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6462
6463 intel_crtc = to_intel_crtc(crtc);
24218aac 6464 old->dpms_mode = connector->dpms;
8261b191 6465 old->load_detect_temp = true;
d2dff872 6466 old->release_fb = NULL;
79e53945 6467
6492711d
CW		 6468 if (!mode)
6469 mode = &load_detect_mode;
79e53945 6470
d2dff872
CW		 6471 /* We need a framebuffer large enough to accommodate all accesses
6472 * that the plane may generate whilst we perform load detection.
6473 * We can not rely on the fbcon either being present (we get called
6474 * during its initialisation to detect all boot displays, or it may
6475 * not even exist) or that it is large enough to satisfy the
6476 * requested mode.
6477 */
94352cf9
DV		 6478 fb = mode_fits_in_fbdev(dev, mode);
6479 if (fb == NULL) {
d2dff872 6480 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6481 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6482 old->release_fb = fb;
d2dff872
CW		 6483 } else
6484 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6485 if (IS_ERR(fb)) {
d2dff872 6486 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6487 goto fail;
79e53945 6488 }
79e53945 6489
94352cf9 6490 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6491 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6492 if (old->release_fb)
6493 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6494 goto fail;
79e53945 6495 }
7173188d 6496
79e53945 6497 /* let the connector get through one full cycle before testing */
9d0498a2 6498 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6499
7173188d 6500 return true;
24218aac
DV		 6501fail:
6502 connector->encoder = NULL;
6503 encoder->crtc = NULL;
24218aac 6504 return false;
79e53945
JB		 6505}
6506
d2434ab7 6507void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6508 struct intel_load_detect_pipe *old)
79e53945 6509{
d2434ab7
DV		 6510 struct intel_encoder *intel_encoder =
6511 intel_attached_encoder(connector);
4ef69c7a 6512 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6513
d2dff872
CW		 6514 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6515 connector->base.id, drm_get_connector_name(connector),
6516 encoder->base.id, drm_get_encoder_name(encoder));
6517
8261b191 6518 if (old->load_detect_temp) {
fc303101
DV		 6519 struct drm_crtc *crtc = encoder->crtc;
6520
6521 to_intel_connector(connector)->new_encoder = NULL;
6522 intel_encoder->new_crtc = NULL;
6523 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6524
6525 if (old->release_fb)
6526 old->release_fb->funcs->destroy(old->release_fb);
6527
0622a53c 6528 return;
79e53945
JB		 6529 }
6530
c751ce4f 6531 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6532 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6533 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6534}
6535
6536/* Returns the clock of the currently programmed mode of the given pipe. */
6537static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6538{
6539 struct drm_i915_private *dev_priv = dev->dev_private;
6540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6541 int pipe = intel_crtc->pipe;
548f245b 6542 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6543 u32 fp;
6544 intel_clock_t clock;
6545
6546 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6547 fp = I915_READ(FP0(pipe));
79e53945 6548 else
39adb7a5 6549 fp = I915_READ(FP1(pipe));
79e53945
JB		 6550
6551 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6552 if (IS_PINEVIEW(dev)) {
6553 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6554 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6555 } else {
6556 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6557 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6558 }
6559
a6c45cf0 6560 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6561 if (IS_PINEVIEW(dev))
6562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6563 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6564 else
6565 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6566 DPLL_FPA01_P1_POST_DIV_SHIFT);
6567
6568 switch (dpll & DPLL_MODE_MASK) {
6569 case DPLLB_MODE_DAC_SERIAL:
6570 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6571 5 : 10;
6572 break;
6573 case DPLLB_MODE_LVDS:
6574 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6575 7 : 14;
6576 break;
6577 default:
28c97730 6578 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6579 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6580 return 0;
6581 }
6582
6583 /* XXX: Handle the 100Mhz refclk */
2177832f 6584 intel_clock(dev, 96000, &clock);
79e53945
JB		 6585 } else {
6586 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6587
6588 if (is_lvds) {
6589 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6590 DPLL_FPA01_P1_POST_DIV_SHIFT);
6591 clock.p2 = 14;
6592
6593 if ((dpll & PLL_REF_INPUT_MASK) ==
6594 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6595 /* XXX: might not be 66MHz */
2177832f 6596 intel_clock(dev, 66000, &clock);
79e53945 6597 } else
2177832f 6598 intel_clock(dev, 48000, &clock);
79e53945
JB		 6599 } else {
6600 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6601 clock.p1 = 2;
6602 else {
6603 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6604 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6605 }
6606 if (dpll & PLL_P2_DIVIDE_BY_4)
6607 clock.p2 = 4;
6608 else
6609 clock.p2 = 2;
6610
2177832f 6611 intel_clock(dev, 48000, &clock);
79e53945
JB		 6612 }
6613 }
6614
6615 /* XXX: It would be nice to validate the clocks, but we can't reuse
6616 * i830PllIsValid() because it relies on the xf86_config connector
6617 * configuration being accurate, which it isn't necessarily.
6618 */
6619
6620 return clock.dot;
6621}
6622
6623/** Returns the currently programmed mode of the given pipe. */
6624struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6625 struct drm_crtc *crtc)
6626{
548f245b 6627 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6629 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6630 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6631 int htot = I915_READ(HTOTAL(cpu_transcoder));
6632 int hsync = I915_READ(HSYNC(cpu_transcoder));
6633 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6634 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6635
6636 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6637 if (!mode)
6638 return NULL;
6639
6640 mode->clock = intel_crtc_clock_get(dev, crtc);
6641 mode->hdisplay = (htot & 0xffff) + 1;
6642 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6643 mode->hsync_start = (hsync & 0xffff) + 1;
6644 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6645 mode->vdisplay = (vtot & 0xffff) + 1;
6646 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6647 mode->vsync_start = (vsync & 0xffff) + 1;
6648 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6649
6650 drm_mode_set_name(mode);
79e53945
JB		 6651
6652 return mode;
6653}
6654
3dec0095 6655static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6656{
6657 struct drm_device *dev = crtc->dev;
6658 drm_i915_private_t *dev_priv = dev->dev_private;
6659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6660 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6661 int dpll_reg = DPLL(pipe);
6662 int dpll;
652c393a 6663
bad720ff 6664 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6665 return;
6666
6667 if (!dev_priv->lvds_downclock_avail)
6668 return;
6669
dbdc6479 6670 dpll = I915_READ(dpll_reg);
652c393a 6671 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6672 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6673
8ac5a6d5 6674 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6675
6676 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6677 I915_WRITE(dpll_reg, dpll);
9d0498a2 6678 intel_wait_for_vblank(dev, pipe);
dbdc6479 6679
652c393a
JB		 6680 dpll = I915_READ(dpll_reg);
6681 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6682 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6683 }
652c393a
JB		 6684}
6685
6686static void intel_decrease_pllclock(struct drm_crtc *crtc)
6687{
6688 struct drm_device *dev = crtc->dev;
6689 drm_i915_private_t *dev_priv = dev->dev_private;
6690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6691
bad720ff 6692 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6693 return;
6694
6695 if (!dev_priv->lvds_downclock_avail)
6696 return;
6697
6698 /*
6699 * Since this is called by a timer, we should never get here in
6700 * the manual case.
6701 */
6702 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6703 int pipe = intel_crtc->pipe;
6704 int dpll_reg = DPLL(pipe);
6705 int dpll;
f6e5b160 6706
44d98a61 6707 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6708
8ac5a6d5 6709 assert_panel_unlocked(dev_priv, pipe);
652c393a 6710
dc257cf1 6711 dpll = I915_READ(dpll_reg);
652c393a
JB		 6712 dpll |= DISPLAY_RATE_SELECT_FPA1;
6713 I915_WRITE(dpll_reg, dpll);
9d0498a2 6714 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6715 dpll = I915_READ(dpll_reg);
6716 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6717 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6718 }
6719
6720}
6721
f047e395
CW		 6722void intel_mark_busy(struct drm_device *dev)
6723{
f047e395
CW		 6724 i915_update_gfx_val(dev->dev_private);
6725}
6726
6727void intel_mark_idle(struct drm_device *dev)
652c393a 6728{
f047e395
CW		 6729}
6730
6731void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6732{
6733 struct drm_device *dev = obj->base.dev;
652c393a 6734 struct drm_crtc *crtc;
652c393a
JB		 6735
6736 if (!i915_powersave)
6737 return;
6738
652c393a 6739 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6740 if (!crtc->fb)
6741 continue;
6742
f047e395
CW		 6743 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6744 intel_increase_pllclock(crtc);
652c393a 6745 }
652c393a
JB		 6746}
6747
f047e395 6748void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6749{
f047e395
CW		 6750 struct drm_device *dev = obj->base.dev;
6751 struct drm_crtc *crtc;
652c393a 6752
f047e395 6753 if (!i915_powersave)
acb87dfb
CW		 6754 return;
6755
652c393a
JB		 6756 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6757 if (!crtc->fb)
6758 continue;
6759
f047e395
CW		 6760 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6761 intel_decrease_pllclock(crtc);
652c393a
JB		 6762 }
6763}
6764
79e53945
JB		 6765static void intel_crtc_destroy(struct drm_crtc *crtc)
6766{
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6768 struct drm_device *dev = crtc->dev;
6769 struct intel_unpin_work *work;
6770 unsigned long flags;
6771
6772 spin_lock_irqsave(&dev->event_lock, flags);
6773 work = intel_crtc->unpin_work;
6774 intel_crtc->unpin_work = NULL;
6775 spin_unlock_irqrestore(&dev->event_lock, flags);
6776
6777 if (work) {
6778 cancel_work_sync(&work->work);
6779 kfree(work);
6780 }
79e53945
JB		 6781
6782 drm_crtc_cleanup(crtc);
67e77c5a 6783
79e53945
JB		 6784 kfree(intel_crtc);
6785}
6786
6b95a207
KH		 6787static void intel_unpin_work_fn(struct work_struct *__work)
6788{
6789 struct intel_unpin_work *work =
6790 container_of(__work, struct intel_unpin_work, work);
6791
6792 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6793 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6794 drm_gem_object_unreference(&work->pending_flip_obj->base);
6795 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6796
7782de3b 6797 intel_update_fbc(work->dev);
6b95a207
KH		 6798 mutex_unlock(&work->dev->struct_mutex);
6799 kfree(work);
6800}
6801
1afe3e9d 6802static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6803 struct drm_crtc *crtc)
6b95a207
KH		 6804{
6805 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807 struct intel_unpin_work *work;
05394f39 6808 struct drm_i915_gem_object *obj;
6b95a207 6809 struct drm_pending_vblank_event *e;
95cb1b02 6810 struct timeval tvbl;
6b95a207
KH		 6811 unsigned long flags;
6812
6813 /* Ignore early vblank irqs */
6814 if (intel_crtc == NULL)
6815 return;
6816
6817 spin_lock_irqsave(&dev->event_lock, flags);
6818 work = intel_crtc->unpin_work;
6819 if (work == NULL || !work->pending) {
6820 spin_unlock_irqrestore(&dev->event_lock, flags);
6821 return;
6822 }
6823
6824 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6825
6826 if (work->event) {
6827 e = work->event;
49b14a5c 6828 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6829
49b14a5c
MK		 6830 e->event.tv_sec = tvbl.tv_sec;
6831 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6832
6b95a207
KH		 6833 list_add_tail(&e->base.link,
6834 &e->base.file_priv->event_list);
6835 wake_up_interruptible(&e->base.file_priv->event_wait);
6836 }
6837
0af7e4df
MK		 6838 drm_vblank_put(dev, intel_crtc->pipe);
6839
6b95a207
KH		 6840 spin_unlock_irqrestore(&dev->event_lock, flags);
6841
05394f39 6842 obj = work->old_fb_obj;
d9e86c0e 6843
e59f2bac 6844 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6845 &obj->pending_flip.counter);
d9e86c0e 6846
5bb61643 6847 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6848 schedule_work(&work->work);
e5510fac
JB		 6849
6850 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6851}
6852
1afe3e9d
JB		 6853void intel_finish_page_flip(struct drm_device *dev, int pipe)
6854{
6855 drm_i915_private_t *dev_priv = dev->dev_private;
6856 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6857
49b14a5c 6858 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6859}
6860
6861void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6862{
6863 drm_i915_private_t *dev_priv = dev->dev_private;
6864 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6865
49b14a5c 6866 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6867}
6868
6b95a207
KH		 6869void intel_prepare_page_flip(struct drm_device *dev, int plane)
6870{
6871 drm_i915_private_t *dev_priv = dev->dev_private;
6872 struct intel_crtc *intel_crtc =
6873 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6874 unsigned long flags;
6875
6876 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6877 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6878 if ((++intel_crtc->unpin_work->pending) > 1)
6879 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6880 } else {
6881 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6882 }
6b95a207
KH		 6883 spin_unlock_irqrestore(&dev->event_lock, flags);
6884}
6885
8c9f3aaf
JB		 6886static int intel_gen2_queue_flip(struct drm_device *dev,
6887 struct drm_crtc *crtc,
6888 struct drm_framebuffer *fb,
6889 struct drm_i915_gem_object *obj)
6890{
6891 struct drm_i915_private *dev_priv = dev->dev_private;
6892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6893 u32 flip_mask;
6d90c952 6894 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6895 int ret;
6896
6d90c952 6897 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6898 if (ret)
83d4092b 6899 goto err;
8c9f3aaf 6900
6d90c952 6901 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6902 if (ret)
83d4092b 6903 goto err_unpin;
8c9f3aaf
JB		 6904
6905 /* Can't queue multiple flips, so wait for the previous
6906 * one to finish before executing the next.
6907 */
6908 if (intel_crtc->plane)
6909 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6910 else
6911 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6912 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6913 intel_ring_emit(ring, MI_NOOP);
6914 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6915 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6916 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6917 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6918 intel_ring_emit(ring, 0); /* aux display base address, unused */
6919 intel_ring_advance(ring);
83d4092b
CW		 6920 return 0;
6921
6922err_unpin:
6923 intel_unpin_fb_obj(obj);
6924err:
8c9f3aaf
JB		 6925 return ret;
6926}
6927
6928static int intel_gen3_queue_flip(struct drm_device *dev,
6929 struct drm_crtc *crtc,
6930 struct drm_framebuffer *fb,
6931 struct drm_i915_gem_object *obj)
6932{
6933 struct drm_i915_private *dev_priv = dev->dev_private;
6934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6935 u32 flip_mask;
6d90c952 6936 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6937 int ret;
6938
6d90c952 6939 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6940 if (ret)
83d4092b 6941 goto err;
8c9f3aaf 6942
6d90c952 6943 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6944 if (ret)
83d4092b 6945 goto err_unpin;
8c9f3aaf
JB		 6946
6947 if (intel_crtc->plane)
6948 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6949 else
6950 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6951 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6952 intel_ring_emit(ring, MI_NOOP);
6953 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6954 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6955 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6956 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6957 intel_ring_emit(ring, MI_NOOP);
6958
6959 intel_ring_advance(ring);
83d4092b
CW		 6960 return 0;
6961
6962err_unpin:
6963 intel_unpin_fb_obj(obj);
6964err:
8c9f3aaf
JB		 6965 return ret;
6966}
6967
6968static int intel_gen4_queue_flip(struct drm_device *dev,
6969 struct drm_crtc *crtc,
6970 struct drm_framebuffer *fb,
6971 struct drm_i915_gem_object *obj)
6972{
6973 struct drm_i915_private *dev_priv = dev->dev_private;
6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6975 uint32_t pf, pipesrc;
6d90c952 6976 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6977 int ret;
6978
6d90c952 6979 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6980 if (ret)
83d4092b 6981 goto err;
8c9f3aaf 6982
6d90c952 6983 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6984 if (ret)
83d4092b 6985 goto err_unpin;
8c9f3aaf
JB		 6986
6987 /* i965+ uses the linear or tiled offsets from the
6988 * Display Registers (which do not change across a page-flip)
6989 * so we need only reprogram the base address.
6990 */
6d90c952
DV		 6991 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6992 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6993 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6994 intel_ring_emit(ring,
6995 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6996 obj->tiling_mode);
8c9f3aaf
JB		 6997
6998 /* XXX Enabling the panel-fitter across page-flip is so far
6999 * untested on non-native modes, so ignore it for now.
7000 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7001 */
7002 pf = 0;
7003 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7004 intel_ring_emit(ring, pf | pipesrc);
7005 intel_ring_advance(ring);
83d4092b
CW		 7006 return 0;
7007
7008err_unpin:
7009 intel_unpin_fb_obj(obj);
7010err:
8c9f3aaf
JB		 7011 return ret;
7012}
7013
7014static int intel_gen6_queue_flip(struct drm_device *dev,
7015 struct drm_crtc *crtc,
7016 struct drm_framebuffer *fb,
7017 struct drm_i915_gem_object *obj)
7018{
7019 struct drm_i915_private *dev_priv = dev->dev_private;
7020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7021 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7022 uint32_t pf, pipesrc;
7023 int ret;
7024
6d90c952 7025 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7026 if (ret)
83d4092b 7027 goto err;
8c9f3aaf 7028
6d90c952 7029 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7030 if (ret)
83d4092b 7031 goto err_unpin;
8c9f3aaf 7032
6d90c952
DV		 7033 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7034 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7035 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7036 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7037
dc257cf1
DV		 7038 /* Contrary to the suggestions in the documentation,
7039 * "Enable Panel Fitter" does not seem to be required when page
7040 * flipping with a non-native mode, and worse causes a normal
7041 * modeset to fail.
7042 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7043 */
7044 pf = 0;
8c9f3aaf 7045 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7046 intel_ring_emit(ring, pf | pipesrc);
7047 intel_ring_advance(ring);
83d4092b
CW		 7048 return 0;
7049
7050err_unpin:
7051 intel_unpin_fb_obj(obj);
7052err:
8c9f3aaf
JB		 7053 return ret;
7054}
7055
7c9017e5
JB		 7056/*
7057 * On gen7 we currently use the blit ring because (in early silicon at least)
7058 * the render ring doesn't give us interrpts for page flip completion, which
7059 * means clients will hang after the first flip is queued. Fortunately the
7060 * blit ring generates interrupts properly, so use it instead.
7061 */
7062static int intel_gen7_queue_flip(struct drm_device *dev,
7063 struct drm_crtc *crtc,
7064 struct drm_framebuffer *fb,
7065 struct drm_i915_gem_object *obj)
7066{
7067 struct drm_i915_private *dev_priv = dev->dev_private;
7068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7069 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7070 uint32_t plane_bit = 0;
7c9017e5
JB		 7071 int ret;
7072
7073 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7074 if (ret)
83d4092b 7075 goto err;
7c9017e5 7076
cb05d8de
DV		 7077 switch(intel_crtc->plane) {
7078 case PLANE_A:
7079 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7080 break;
7081 case PLANE_B:
7082 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7083 break;
7084 case PLANE_C:
7085 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7086 break;
7087 default:
7088 WARN_ONCE(1, "unknown plane in flip command\n");
7089 ret = -ENODEV;
ab3951eb 7090 goto err_unpin;
cb05d8de
DV		 7091 }
7092
7c9017e5
JB		 7093 ret = intel_ring_begin(ring, 4);
7094 if (ret)
83d4092b 7095 goto err_unpin;
7c9017e5 7096
cb05d8de 7097 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7098 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7099 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7100 intel_ring_emit(ring, (MI_NOOP));
7101 intel_ring_advance(ring);
83d4092b
CW		 7102 return 0;
7103
7104err_unpin:
7105 intel_unpin_fb_obj(obj);
7106err:
7c9017e5
JB		 7107 return ret;
7108}
7109
8c9f3aaf
JB		 7110static int intel_default_queue_flip(struct drm_device *dev,
7111 struct drm_crtc *crtc,
7112 struct drm_framebuffer *fb,
7113 struct drm_i915_gem_object *obj)
7114{
7115 return -ENODEV;
7116}
7117
6b95a207
KH		 7118static int intel_crtc_page_flip(struct drm_crtc *crtc,
7119 struct drm_framebuffer *fb,
7120 struct drm_pending_vblank_event *event)
7121{
7122 struct drm_device *dev = crtc->dev;
7123 struct drm_i915_private *dev_priv = dev->dev_private;
7124 struct intel_framebuffer *intel_fb;
05394f39 7125 struct drm_i915_gem_object *obj;
6b95a207
KH		 7126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7127 struct intel_unpin_work *work;
8c9f3aaf 7128 unsigned long flags;
52e68630 7129 int ret;
6b95a207 7130
e6a595d2
VS		 7131 /* Can't change pixel format via MI display flips. */
7132 if (fb->pixel_format != crtc->fb->pixel_format)
7133 return -EINVAL;
7134
7135 /*
7136 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7137 * Note that pitch changes could also affect these register.
7138 */
7139 if (INTEL_INFO(dev)->gen > 3 &&
7140 (fb->offsets[0] != crtc->fb->offsets[0] ||
7141 fb->pitches[0] != crtc->fb->pitches[0]))
7142 return -EINVAL;
7143
6b95a207
KH		 7144 work = kzalloc(sizeof *work, GFP_KERNEL);
7145 if (work == NULL)
7146 return -ENOMEM;
7147
6b95a207
KH		 7148 work->event = event;
7149 work->dev = crtc->dev;
7150 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7151 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7152 INIT_WORK(&work->work, intel_unpin_work_fn);
7153
7317c75e
JB		 7154 ret = drm_vblank_get(dev, intel_crtc->pipe);
7155 if (ret)
7156 goto free_work;
7157
6b95a207
KH		 7158 /* We borrow the event spin lock for protecting unpin_work */
7159 spin_lock_irqsave(&dev->event_lock, flags);
7160 if (intel_crtc->unpin_work) {
7161 spin_unlock_irqrestore(&dev->event_lock, flags);
7162 kfree(work);
7317c75e 7163 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7164
7165 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7166 return -EBUSY;
7167 }
7168 intel_crtc->unpin_work = work;
7169 spin_unlock_irqrestore(&dev->event_lock, flags);
7170
7171 intel_fb = to_intel_framebuffer(fb);
7172 obj = intel_fb->obj;
7173
79158103
CW		 7174 ret = i915_mutex_lock_interruptible(dev);
7175 if (ret)
7176 goto cleanup;
6b95a207 7177
75dfca80 7178 /* Reference the objects for the scheduled work. */
05394f39
CW		 7179 drm_gem_object_reference(&work->old_fb_obj->base);
7180 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7181
7182 crtc->fb = fb;
96b099fd 7183
e1f99ce6 7184 work->pending_flip_obj = obj;
e1f99ce6 7185
4e5359cd
SF		 7186 work->enable_stall_check = true;
7187
e1f99ce6
CW		 7188 /* Block clients from rendering to the new back buffer until
7189 * the flip occurs and the object is no longer visible.
7190 */
05394f39 7191 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7192
8c9f3aaf
JB		 7193 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7194 if (ret)
7195 goto cleanup_pending;
6b95a207 7196
7782de3b 7197 intel_disable_fbc(dev);
f047e395 7198 intel_mark_fb_busy(obj);
6b95a207
KH		 7199 mutex_unlock(&dev->struct_mutex);
7200
e5510fac
JB		 7201 trace_i915_flip_request(intel_crtc->plane, obj);
7202
6b95a207 7203 return 0;
96b099fd 7204
8c9f3aaf
JB		 7205cleanup_pending:
7206 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7207 drm_gem_object_unreference(&work->old_fb_obj->base);
7208 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7209 mutex_unlock(&dev->struct_mutex);
7210
79158103 7211cleanup:
96b099fd
CW		 7212 spin_lock_irqsave(&dev->event_lock, flags);
7213 intel_crtc->unpin_work = NULL;
7214 spin_unlock_irqrestore(&dev->event_lock, flags);
7215
7317c75e
JB		 7216 drm_vblank_put(dev, intel_crtc->pipe);
7217free_work:
96b099fd
CW		 7218 kfree(work);
7219
7220 return ret;
6b95a207
KH		 7221}
7222
f6e5b160 7223static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7224 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7225 .load_lut = intel_crtc_load_lut,
976f8a20 7226 .disable = intel_crtc_noop,
f6e5b160
CW		 7227};
7228
6ed0f796 7229bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7230{
6ed0f796
DV		 7231 struct intel_encoder *other_encoder;
7232 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7233
6ed0f796
DV		 7234 if (WARN_ON(!crtc))
7235 return false;
7236
7237 list_for_each_entry(other_encoder,
7238 &crtc->dev->mode_config.encoder_list,
7239 base.head) {
7240
7241 if (&other_encoder->new_crtc->base != crtc ||
7242 encoder == other_encoder)
7243 continue;
7244 else
7245 return true;
f47166d2
CW		 7246 }
7247
6ed0f796
DV		 7248 return false;
7249}
47f1c6c9 7250
50f56119
DV		 7251static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7252 struct drm_crtc *crtc)
7253{
7254 struct drm_device *dev;
7255 struct drm_crtc *tmp;
7256 int crtc_mask = 1;
47f1c6c9 7257
50f56119 7258 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7259
50f56119 7260 dev = crtc->dev;
47f1c6c9 7261
50f56119
DV		 7262 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7263 if (tmp == crtc)
7264 break;
7265 crtc_mask <<= 1;
7266 }
47f1c6c9 7267
50f56119
DV		 7268 if (encoder->possible_crtcs & crtc_mask)
7269 return true;
7270 return false;
47f1c6c9 7271}
79e53945 7272
9a935856
DV		 7273/**
7274 * intel_modeset_update_staged_output_state
7275 *
7276 * Updates the staged output configuration state, e.g. after we've read out the
7277 * current hw state.
7278 */
7279static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7280{
9a935856
DV		 7281 struct intel_encoder *encoder;
7282 struct intel_connector *connector;
f6e5b160 7283
9a935856
DV		 7284 list_for_each_entry(connector, &dev->mode_config.connector_list,
7285 base.head) {
7286 connector->new_encoder =
7287 to_intel_encoder(connector->base.encoder);
7288 }
f6e5b160 7289
9a935856
DV		 7290 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7291 base.head) {
7292 encoder->new_crtc =
7293 to_intel_crtc(encoder->base.crtc);
7294 }
f6e5b160
CW		 7295}
7296
9a935856
DV		 7297/**
7298 * intel_modeset_commit_output_state
7299 *
7300 * This function copies the stage display pipe configuration to the real one.
7301 */
7302static void intel_modeset_commit_output_state(struct drm_device *dev)
7303{
7304 struct intel_encoder *encoder;
7305 struct intel_connector *connector;
f6e5b160 7306
9a935856
DV		 7307 list_for_each_entry(connector, &dev->mode_config.connector_list,
7308 base.head) {
7309 connector->base.encoder = &connector->new_encoder->base;
7310 }
f6e5b160 7311
9a935856
DV		 7312 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7313 base.head) {
7314 encoder->base.crtc = &encoder->new_crtc->base;
7315 }
7316}
7317
7758a113
DV		 7318static struct drm_display_mode *
7319intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7320 struct drm_display_mode *mode)
ee7b9f93 7321{
7758a113
DV		 7322 struct drm_device *dev = crtc->dev;
7323 struct drm_display_mode *adjusted_mode;
7324 struct drm_encoder_helper_funcs *encoder_funcs;
7325 struct intel_encoder *encoder;
ee7b9f93 7326
7758a113
DV		 7327 adjusted_mode = drm_mode_duplicate(dev, mode);
7328 if (!adjusted_mode)
7329 return ERR_PTR(-ENOMEM);
7330
7331 /* Pass our mode to the connectors and the CRTC to give them a chance to
7332 * adjust it according to limitations or connector properties, and also
7333 * a chance to reject the mode entirely.
7334 */
7335 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7336 base.head) {
7337
7338 if (&encoder->new_crtc->base != crtc)
7339 continue;
7340 encoder_funcs = encoder->base.helper_private;
7341 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7342 adjusted_mode))) {
7343 DRM_DEBUG_KMS("Encoder fixup failed\n");
7344 goto fail;
7345 }
ee7b9f93
JB		 7346 }
7347
7758a113
DV		 7348 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7349 DRM_DEBUG_KMS("CRTC fixup failed\n");
7350 goto fail;
ee7b9f93 7351 }
7758a113
DV		 7352 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7353
7354 return adjusted_mode;
7355fail:
7356 drm_mode_destroy(dev, adjusted_mode);
7357 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7358}
7359
e2e1ed41
DV		 7360/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7361 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7362static void
7363intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7364 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7365{
7366 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7367 struct drm_device *dev = crtc->dev;
7368 struct intel_encoder *encoder;
7369 struct intel_connector *connector;
7370 struct drm_crtc *tmp_crtc;
79e53945 7371
e2e1ed41 7372 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7373
e2e1ed41
DV		 7374 /* Check which crtcs have changed outputs connected to them, these need
7375 * to be part of the prepare_pipes mask. We don't (yet) support global
7376 * modeset across multiple crtcs, so modeset_pipes will only have one
7377 * bit set at most. */
7378 list_for_each_entry(connector, &dev->mode_config.connector_list,
7379 base.head) {
7380 if (connector->base.encoder == &connector->new_encoder->base)
7381 continue;
79e53945 7382
e2e1ed41
DV		 7383 if (connector->base.encoder) {
7384 tmp_crtc = connector->base.encoder->crtc;
7385
7386 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7387 }
7388
7389 if (connector->new_encoder)
7390 *prepare_pipes |=
7391 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7392 }
7393
e2e1ed41
DV		 7394 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7395 base.head) {
7396 if (encoder->base.crtc == &encoder->new_crtc->base)
7397 continue;
7398
7399 if (encoder->base.crtc) {
7400 tmp_crtc = encoder->base.crtc;
7401
7402 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7403 }
7404
7405 if (encoder->new_crtc)
7406 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7407 }
7408
e2e1ed41
DV		 7409 /* Check for any pipes that will be fully disabled ... */
7410 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7411 base.head) {
7412 bool used = false;
22fd0fab 7413
e2e1ed41
DV		 7414 /* Don't try to disable disabled crtcs. */
7415 if (!intel_crtc->base.enabled)
7416 continue;
7e7d76c3 7417
e2e1ed41
DV		 7418 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7419 base.head) {
7420 if (encoder->new_crtc == intel_crtc)
7421 used = true;
7422 }
7423
7424 if (!used)
7425 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7426 }
7427
e2e1ed41
DV		 7428
7429 /* set_mode is also used to update properties on life display pipes. */
7430 intel_crtc = to_intel_crtc(crtc);
7431 if (crtc->enabled)
7432 *prepare_pipes |= 1 << intel_crtc->pipe;
7433
7434 /* We only support modeset on one single crtc, hence we need to do that
7435 * only for the passed in crtc iff we change anything else than just
7436 * disable crtcs.
7437 *
7438 * This is actually not true, to be fully compatible with the old crtc
7439 * helper we automatically disable _any_ output (i.e. doesn't need to be
7440 * connected to the crtc we're modesetting on) if it's disconnected.
7441 * Which is a rather nutty api (since changed the output configuration
7442 * without userspace's explicit request can lead to confusion), but
7443 * alas. Hence we currently need to modeset on all pipes we prepare. */
7444 if (*prepare_pipes)
7445 *modeset_pipes = *prepare_pipes;
7446
7447 /* ... and mask these out. */
7448 *modeset_pipes &= ~(*disable_pipes);
7449 *prepare_pipes &= ~(*disable_pipes);
7450}
7451
ea9d758d
DV		 7452static bool intel_crtc_in_use(struct drm_crtc *crtc)
7453{
7454 struct drm_encoder *encoder;
7455 struct drm_device *dev = crtc->dev;
7456
7457 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7458 if (encoder->crtc == crtc)
7459 return true;
7460
7461 return false;
7462}
7463
7464static void
7465intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7466{
7467 struct intel_encoder *intel_encoder;
7468 struct intel_crtc *intel_crtc;
7469 struct drm_connector *connector;
7470
7471 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7472 base.head) {
7473 if (!intel_encoder->base.crtc)
7474 continue;
7475
7476 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7477
7478 if (prepare_pipes & (1 << intel_crtc->pipe))
7479 intel_encoder->connectors_active = false;
7480 }
7481
7482 intel_modeset_commit_output_state(dev);
7483
7484 /* Update computed state. */
7485 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7486 base.head) {
7487 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7488 }
7489
7490 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7491 if (!connector->encoder || !connector->encoder->crtc)
7492 continue;
7493
7494 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7495
7496 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7497 struct drm_property *dpms_property =
7498 dev->mode_config.dpms_property;
7499
ea9d758d 7500 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7501 drm_connector_property_set_value(connector,
7502 dpms_property,
7503 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7504
7505 intel_encoder = to_intel_encoder(connector->encoder);
7506 intel_encoder->connectors_active = true;
7507 }
7508 }
7509
7510}
7511
25c5b266
DV		 7512#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7513 list_for_each_entry((intel_crtc), \
7514 &(dev)->mode_config.crtc_list, \
7515 base.head) \
7516 if (mask & (1 <<(intel_crtc)->pipe)) \
7517
b980514c 7518void
8af6cf88
DV		 7519intel_modeset_check_state(struct drm_device *dev)
7520{
7521 struct intel_crtc *crtc;
7522 struct intel_encoder *encoder;
7523 struct intel_connector *connector;
7524
7525 list_for_each_entry(connector, &dev->mode_config.connector_list,
7526 base.head) {
7527 /* This also checks the encoder/connector hw state with the
7528 * ->get_hw_state callbacks. */
7529 intel_connector_check_state(connector);
7530
7531 WARN(&connector->new_encoder->base != connector->base.encoder,
7532 "connector's staged encoder doesn't match current encoder\n");
7533 }
7534
7535 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7536 base.head) {
7537 bool enabled = false;
7538 bool active = false;
7539 enum pipe pipe, tracked_pipe;
7540
7541 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7542 encoder->base.base.id,
7543 drm_get_encoder_name(&encoder->base));
7544
7545 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7546 "encoder's stage crtc doesn't match current crtc\n");
7547 WARN(encoder->connectors_active && !encoder->base.crtc,
7548 "encoder's active_connectors set, but no crtc\n");
7549
7550 list_for_each_entry(connector, &dev->mode_config.connector_list,
7551 base.head) {
7552 if (connector->base.encoder != &encoder->base)
7553 continue;
7554 enabled = true;
7555 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7556 active = true;
7557 }
7558 WARN(!!encoder->base.crtc != enabled,
7559 "encoder's enabled state mismatch "
7560 "(expected %i, found %i)\n",
7561 !!encoder->base.crtc, enabled);
7562 WARN(active && !encoder->base.crtc,
7563 "active encoder with no crtc\n");
7564
7565 WARN(encoder->connectors_active != active,
7566 "encoder's computed active state doesn't match tracked active state "
7567 "(expected %i, found %i)\n", active, encoder->connectors_active);
7568
7569 active = encoder->get_hw_state(encoder, &pipe);
7570 WARN(active != encoder->connectors_active,
7571 "encoder's hw state doesn't match sw tracking "
7572 "(expected %i, found %i)\n",
7573 encoder->connectors_active, active);
7574
7575 if (!encoder->base.crtc)
7576 continue;
7577
7578 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7579 WARN(active && pipe != tracked_pipe,
7580 "active encoder's pipe doesn't match"
7581 "(expected %i, found %i)\n",
7582 tracked_pipe, pipe);
7583
7584 }
7585
7586 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7587 base.head) {
7588 bool enabled = false;
7589 bool active = false;
7590
7591 DRM_DEBUG_KMS("[CRTC:%d]\n",
7592 crtc->base.base.id);
7593
7594 WARN(crtc->active && !crtc->base.enabled,
7595 "active crtc, but not enabled in sw tracking\n");
7596
7597 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7598 base.head) {
7599 if (encoder->base.crtc != &crtc->base)
7600 continue;
7601 enabled = true;
7602 if (encoder->connectors_active)
7603 active = true;
7604 }
7605 WARN(active != crtc->active,
7606 "crtc's computed active state doesn't match tracked active state "
7607 "(expected %i, found %i)\n", active, crtc->active);
7608 WARN(enabled != crtc->base.enabled,
7609 "crtc's computed enabled state doesn't match tracked enabled state "
7610 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7611
7612 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7613 }
7614}
7615
a6778b3c
DV		 7616bool intel_set_mode(struct drm_crtc *crtc,
7617 struct drm_display_mode *mode,
94352cf9 7618 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7619{
7620 struct drm_device *dev = crtc->dev;
dbf2b54e 7621 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7622 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 7623 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c 7624 struct drm_encoder *encoder;
25c5b266
DV		 7625 struct intel_crtc *intel_crtc;
7626 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7627 bool ret = true;
7628
e2e1ed41 7629 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7630 &prepare_pipes, &disable_pipes);
7631
7632 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7633 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7634
976f8a20
DV		 7635 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7636 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7637
a6778b3c
DV		 7638 saved_hwmode = crtc->hwmode;
7639 saved_mode = crtc->mode;
a6778b3c 7640
25c5b266
DV		 7641 /* Hack: Because we don't (yet) support global modeset on multiple
7642 * crtcs, we don't keep track of the new mode for more than one crtc.
7643 * Hence simply check whether any bit is set in modeset_pipes in all the
7644 * pieces of code that are not yet converted to deal with mutliple crtcs
7645 * changing their mode at the same time. */
7646 adjusted_mode = NULL;
7647 if (modeset_pipes) {
7648 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7649 if (IS_ERR(adjusted_mode)) {
7650 return false;
7651 }
25c5b266 7652 }
a6778b3c 7653
ea9d758d
DV		 7654 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7655 if (intel_crtc->base.enabled)
7656 dev_priv->display.crtc_disable(&intel_crtc->base);
7657 }
a6778b3c 7658
6c4c86f5
DV		 7659 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7660 * to set it here already despite that we pass it down the callchain.
7661 */
7662 if (modeset_pipes)
25c5b266 7663 crtc->mode = *mode;
7758a113 7664
ea9d758d
DV		 7665 /* Only after disabling all output pipelines that will be changed can we
7666 * update the the output configuration. */
7667 intel_modeset_update_state(dev, prepare_pipes);
7668
47fab737
DV		 7669 if (dev_priv->display.modeset_global_resources)
7670 dev_priv->display.modeset_global_resources(dev);
7671
a6778b3c
DV		 7672 /* Set up the DPLL and any encoders state that needs to adjust or depend
7673 * on the DPLL.
7674 */
25c5b266
DV		 7675 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7676 ret = !intel_crtc_mode_set(&intel_crtc->base,
7677 mode, adjusted_mode,
7678 x, y, fb);
7679 if (!ret)
7680 goto done;
a6778b3c 7681
25c5b266 7682 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
a6778b3c 7683
25c5b266
DV		 7684 if (encoder->crtc != &intel_crtc->base)
7685 continue;
a6778b3c 7686
25c5b266
DV		 7687 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7688 encoder->base.id, drm_get_encoder_name(encoder),
7689 mode->base.id, mode->name);
7690 encoder_funcs = encoder->helper_private;
7691 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7692 }
a6778b3c
DV		 7693 }
7694
7695 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7696 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7697 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7698
25c5b266
DV		 7699 if (modeset_pipes) {
7700 /* Store real post-adjustment hardware mode. */
7701 crtc->hwmode = *adjusted_mode;
a6778b3c 7702
25c5b266
DV		 7703 /* Calculate and store various constants which
7704 * are later needed by vblank and swap-completion
7705 * timestamping. They are derived from true hwmode.
7706 */
7707 drm_calc_timestamping_constants(crtc);
7708 }
a6778b3c
DV		 7709
7710 /* FIXME: add subpixel order */
7711done:
7712 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7713 if (!ret && crtc->enabled) {
a6778b3c
DV		 7714 crtc->hwmode = saved_hwmode;
7715 crtc->mode = saved_mode;
8af6cf88
DV		 7716 } else {
7717 intel_modeset_check_state(dev);
a6778b3c
DV		 7718 }
7719
7720 return ret;
7721}
7722
25c5b266
DV		 7723#undef for_each_intel_crtc_masked
7724
d9e55608
DV		 7725static void intel_set_config_free(struct intel_set_config *config)
7726{
7727 if (!config)
7728 return;
7729
1aa4b628
DV		 7730 kfree(config->save_connector_encoders);
7731 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7732 kfree(config);
7733}
7734
85f9eb71
DV		 7735static int intel_set_config_save_state(struct drm_device *dev,
7736 struct intel_set_config *config)
7737{
85f9eb71
DV		 7738 struct drm_encoder *encoder;
7739 struct drm_connector *connector;
7740 int count;
7741
1aa4b628
DV		 7742 config->save_encoder_crtcs =
7743 kcalloc(dev->mode_config.num_encoder,
7744 sizeof(struct drm_crtc *), GFP_KERNEL);
7745 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7746 return -ENOMEM;
7747
1aa4b628
DV		 7748 config->save_connector_encoders =
7749 kcalloc(dev->mode_config.num_connector,
7750 sizeof(struct drm_encoder *), GFP_KERNEL);
7751 if (!config->save_connector_encoders)
85f9eb71
DV		 7752 return -ENOMEM;
7753
7754 /* Copy data. Note that driver private data is not affected.
7755 * Should anything bad happen only the expected state is
7756 * restored, not the drivers personal bookkeeping.
7757 */
85f9eb71
DV		 7758 count = 0;
7759 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7760 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7761 }
7762
7763 count = 0;
7764 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7765 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7766 }
7767
7768 return 0;
7769}
7770
7771static void intel_set_config_restore_state(struct drm_device *dev,
7772 struct intel_set_config *config)
7773{
9a935856
DV		 7774 struct intel_encoder *encoder;
7775 struct intel_connector *connector;
85f9eb71
DV		 7776 int count;
7777
85f9eb71 7778 count = 0;
9a935856
DV		 7779 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7780 encoder->new_crtc =
7781 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7782 }
7783
7784 count = 0;
9a935856
DV		 7785 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7786 connector->new_encoder =
7787 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7788 }
7789}
7790
5e2b584e
DV		 7791static void
7792intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7793 struct intel_set_config *config)
7794{
7795
7796 /* We should be able to check here if the fb has the same properties
7797 * and then just flip_or_move it */
7798 if (set->crtc->fb != set->fb) {
7799 /* If we have no fb then treat it as a full mode set */
7800 if (set->crtc->fb == NULL) {
7801 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7802 config->mode_changed = true;
7803 } else if (set->fb == NULL) {
7804 config->mode_changed = true;
7805 } else if (set->fb->depth != set->crtc->fb->depth) {
7806 config->mode_changed = true;
7807 } else if (set->fb->bits_per_pixel !=
7808 set->crtc->fb->bits_per_pixel) {
7809 config->mode_changed = true;
7810 } else
7811 config->fb_changed = true;
7812 }
7813
835c5873 7814 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7815 config->fb_changed = true;
7816
7817 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7818 DRM_DEBUG_KMS("modes are different, full mode set\n");
7819 drm_mode_debug_printmodeline(&set->crtc->mode);
7820 drm_mode_debug_printmodeline(set->mode);
7821 config->mode_changed = true;
7822 }
7823}
7824
2e431051 7825static int
9a935856
DV		 7826intel_modeset_stage_output_state(struct drm_device *dev,
7827 struct drm_mode_set *set,
7828 struct intel_set_config *config)
50f56119 7829{
85f9eb71 7830 struct drm_crtc *new_crtc;
9a935856
DV		 7831 struct intel_connector *connector;
7832 struct intel_encoder *encoder;
2e431051 7833 int count, ro;
50f56119 7834
9a935856
DV		 7835 /* The upper layers ensure that we either disabl a crtc or have a list
7836 * of connectors. For paranoia, double-check this. */
7837 WARN_ON(!set->fb && (set->num_connectors != 0));
7838 WARN_ON(set->fb && (set->num_connectors == 0));
7839
50f56119 7840 count = 0;
9a935856
DV		 7841 list_for_each_entry(connector, &dev->mode_config.connector_list,
7842 base.head) {
7843 /* Otherwise traverse passed in connector list and get encoders
7844 * for them. */
50f56119 7845 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7846 if (set->connectors[ro] == &connector->base) {
7847 connector->new_encoder = connector->encoder;
50f56119
DV		 7848 break;
7849 }
7850 }
7851
9a935856
DV		 7852 /* If we disable the crtc, disable all its connectors. Also, if
7853 * the connector is on the changing crtc but not on the new
7854 * connector list, disable it. */
7855 if ((!set->fb || ro == set->num_connectors) &&
7856 connector->base.encoder &&
7857 connector->base.encoder->crtc == set->crtc) {
7858 connector->new_encoder = NULL;
7859
7860 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7861 connector->base.base.id,
7862 drm_get_connector_name(&connector->base));
7863 }
7864
7865
7866 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7867 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7868 config->mode_changed = true;
50f56119 7869 }
9a935856
DV		 7870
7871 /* Disable all disconnected encoders. */
7872 if (connector->base.status == connector_status_disconnected)
7873 connector->new_encoder = NULL;
50f56119 7874 }
9a935856 7875 /* connector->new_encoder is now updated for all connectors. */
50f56119 7876
9a935856 7877 /* Update crtc of enabled connectors. */
50f56119 7878 count = 0;
9a935856
DV		 7879 list_for_each_entry(connector, &dev->mode_config.connector_list,
7880 base.head) {
7881 if (!connector->new_encoder)
50f56119
DV		 7882 continue;
7883
9a935856 7884 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7885
7886 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7887 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7888 new_crtc = set->crtc;
7889 }
7890
7891 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7892 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7893 new_crtc)) {
5e2b584e 7894 return -EINVAL;
50f56119 7895 }
9a935856
DV		 7896 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7897
7898 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7899 connector->base.base.id,
7900 drm_get_connector_name(&connector->base),
7901 new_crtc->base.id);
7902 }
7903
7904 /* Check for any encoders that needs to be disabled. */
7905 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7906 base.head) {
7907 list_for_each_entry(connector,
7908 &dev->mode_config.connector_list,
7909 base.head) {
7910 if (connector->new_encoder == encoder) {
7911 WARN_ON(!connector->new_encoder->new_crtc);
7912
7913 goto next_encoder;
7914 }
7915 }
7916 encoder->new_crtc = NULL;
7917next_encoder:
7918 /* Only now check for crtc changes so we don't miss encoders
7919 * that will be disabled. */
7920 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7921 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7922 config->mode_changed = true;
50f56119
DV		 7923 }
7924 }
9a935856 7925 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7926
2e431051
DV		 7927 return 0;
7928}
7929
7930static int intel_crtc_set_config(struct drm_mode_set *set)
7931{
7932 struct drm_device *dev;
2e431051
DV		 7933 struct drm_mode_set save_set;
7934 struct intel_set_config *config;
7935 int ret;
2e431051 7936
8d3e375e
DV		 7937 BUG_ON(!set);
7938 BUG_ON(!set->crtc);
7939 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7940
7941 if (!set->mode)
7942 set->fb = NULL;
7943
431e50f7
DV		 7944 /* The fb helper likes to play gross jokes with ->mode_set_config.
7945 * Unfortunately the crtc helper doesn't do much at all for this case,
7946 * so we have to cope with this madness until the fb helper is fixed up. */
7947 if (set->fb && set->num_connectors == 0)
7948 return 0;
7949
2e431051
DV		 7950 if (set->fb) {
7951 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7952 set->crtc->base.id, set->fb->base.id,
7953 (int)set->num_connectors, set->x, set->y);
7954 } else {
7955 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7956 }
7957
7958 dev = set->crtc->dev;
7959
7960 ret = -ENOMEM;
7961 config = kzalloc(sizeof(*config), GFP_KERNEL);
7962 if (!config)
7963 goto out_config;
7964
7965 ret = intel_set_config_save_state(dev, config);
7966 if (ret)
7967 goto out_config;
7968
7969 save_set.crtc = set->crtc;
7970 save_set.mode = &set->crtc->mode;
7971 save_set.x = set->crtc->x;
7972 save_set.y = set->crtc->y;
7973 save_set.fb = set->crtc->fb;
7974
7975 /* Compute whether we need a full modeset, only an fb base update or no
7976 * change at all. In the future we might also check whether only the
7977 * mode changed, e.g. for LVDS where we only change the panel fitter in
7978 * such cases. */
7979 intel_set_config_compute_mode_changes(set, config);
7980
9a935856 7981 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7982 if (ret)
7983 goto fail;
7984
5e2b584e 7985 if (config->mode_changed) {
87f1faa6 7986 if (set->mode) {
50f56119
DV		 7987 DRM_DEBUG_KMS("attempting to set mode from"
7988 " userspace\n");
7989 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7990 }
7991
7992 if (!intel_set_mode(set->crtc, set->mode,
7993 set->x, set->y, set->fb)) {
7994 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7995 set->crtc->base.id);
7996 ret = -EINVAL;
7997 goto fail;
7998 }
5e2b584e 7999 } else if (config->fb_changed) {
4f660f49 8000 ret = intel_pipe_set_base(set->crtc,
94352cf9 8001 set->x, set->y, set->fb);
50f56119
DV		 8002 }
8003
d9e55608
DV		 8004 intel_set_config_free(config);
8005
50f56119
DV		 8006 return 0;
8007
8008fail:
85f9eb71 8009 intel_set_config_restore_state(dev, config);
50f56119
DV		 8010
8011 /* Try to restore the config */
5e2b584e 8012 if (config->mode_changed &&
a6778b3c
DV		 8013 !intel_set_mode(save_set.crtc, save_set.mode,
8014 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8015 DRM_ERROR("failed to restore config after modeset failure\n");
8016
d9e55608
DV		 8017out_config:
8018 intel_set_config_free(config);
50f56119
DV		 8019 return ret;
8020}
8021
f6e5b160 8022static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8023 .cursor_set = intel_crtc_cursor_set,
8024 .cursor_move = intel_crtc_cursor_move,
8025 .gamma_set = intel_crtc_gamma_set,
50f56119 8026 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8027 .destroy = intel_crtc_destroy,
8028 .page_flip = intel_crtc_page_flip,
8029};
8030
79f689aa
PZ		 8031static void intel_cpu_pll_init(struct drm_device *dev)
8032{
8033 if (IS_HASWELL(dev))
8034 intel_ddi_pll_init(dev);
8035}
8036
ee7b9f93
JB		 8037static void intel_pch_pll_init(struct drm_device *dev)
8038{
8039 drm_i915_private_t *dev_priv = dev->dev_private;
8040 int i;
8041
8042 if (dev_priv->num_pch_pll == 0) {
8043 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8044 return;
8045 }
8046
8047 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8048 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8049 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8050 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8051 }
8052}
8053
b358d0a6 8054static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8055{
22fd0fab 8056 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8057 struct intel_crtc *intel_crtc;
8058 int i;
8059
8060 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8061 if (intel_crtc == NULL)
8062 return;
8063
8064 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8065
8066 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8067 for (i = 0; i < 256; i++) {
8068 intel_crtc->lut_r[i] = i;
8069 intel_crtc->lut_g[i] = i;
8070 intel_crtc->lut_b[i] = i;
8071 }
8072
80824003
JB		 8073 /* Swap pipes & planes for FBC on pre-965 */
8074 intel_crtc->pipe = pipe;
8075 intel_crtc->plane = pipe;
a5c961d1 8076 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8077 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8078 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8079 intel_crtc->plane = !pipe;
80824003
JB		 8080 }
8081
22fd0fab
JB		 8082 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8083 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8084 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8085 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8086
5a354204 8087 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8088
79e53945 8089 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8090}
8091
08d7b3d1 8092int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8093 struct drm_file *file)
08d7b3d1 8094{
08d7b3d1 8095 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8096 struct drm_mode_object *drmmode_obj;
8097 struct intel_crtc *crtc;
08d7b3d1 8098
1cff8f6b
DV		 8099 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8100 return -ENODEV;
08d7b3d1 8101
c05422d5
DV		 8102 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8103 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8104
c05422d5 8105 if (!drmmode_obj) {
08d7b3d1
CW		 8106 DRM_ERROR("no such CRTC id\n");
8107 return -EINVAL;
8108 }
8109
c05422d5
DV		 8110 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8111 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8112
c05422d5 8113 return 0;
08d7b3d1
CW		 8114}
8115
66a9278e 8116static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8117{
66a9278e
DV		 8118 struct drm_device *dev = encoder->base.dev;
8119 struct intel_encoder *source_encoder;
79e53945 8120 int index_mask = 0;
79e53945
JB		 8121 int entry = 0;
8122
66a9278e
DV		 8123 list_for_each_entry(source_encoder,
8124 &dev->mode_config.encoder_list, base.head) {
8125
8126 if (encoder == source_encoder)
79e53945 8127 index_mask |= (1 << entry);
66a9278e
DV		 8128
8129 /* Intel hw has only one MUX where enocoders could be cloned. */
8130 if (encoder->cloneable && source_encoder->cloneable)
8131 index_mask |= (1 << entry);
8132
79e53945
JB		 8133 entry++;
8134 }
4ef69c7a 8135
79e53945
JB		 8136 return index_mask;
8137}
8138
4d302442
CW		 8139static bool has_edp_a(struct drm_device *dev)
8140{
8141 struct drm_i915_private *dev_priv = dev->dev_private;
8142
8143 if (!IS_MOBILE(dev))
8144 return false;
8145
8146 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8147 return false;
8148
8149 if (IS_GEN5(dev) &&
8150 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8151 return false;
8152
8153 return true;
8154}
8155
79e53945
JB		 8156static void intel_setup_outputs(struct drm_device *dev)
8157{
725e30ad 8158 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8159 struct intel_encoder *encoder;
cb0953d7 8160 bool dpd_is_edp = false;
f3cfcba6 8161 bool has_lvds;
79e53945 8162
f3cfcba6 8163 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8164 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8165 /* disable the panel fitter on everything but LVDS */
8166 I915_WRITE(PFIT_CONTROL, 0);
8167 }
79e53945 8168
bad720ff 8169 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8170 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8171
4d302442 8172 if (has_edp_a(dev))
ab9d7c30 8173 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8174
cb0953d7 8175 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8176 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8177 }
8178
8179 intel_crt_init(dev);
8180
0e72a5b5
ED		 8181 if (IS_HASWELL(dev)) {
8182 int found;
8183
8184 /* Haswell uses DDI functions to detect digital outputs */
8185 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8186 /* DDI A only supports eDP */
8187 if (found)
8188 intel_ddi_init(dev, PORT_A);
8189
8190 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8191 * register */
8192 found = I915_READ(SFUSE_STRAP);
8193
8194 if (found & SFUSE_STRAP_DDIB_DETECTED)
8195 intel_ddi_init(dev, PORT_B);
8196 if (found & SFUSE_STRAP_DDIC_DETECTED)
8197 intel_ddi_init(dev, PORT_C);
8198 if (found & SFUSE_STRAP_DDID_DETECTED)
8199 intel_ddi_init(dev, PORT_D);
8200 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8201 int found;
8202
30ad48b7 8203 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8204 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8205 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8206 if (!found)
08d644ad 8207 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8208 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8209 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8210 }
8211
8212 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8213 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8214
b708a1d5 8215 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8216 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8217
5eb08b69 8218 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8219 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8220
cb0953d7 8221 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8222 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8223 } else if (IS_VALLEYVIEW(dev)) {
8224 int found;
8225
19c03924
GB		 8226 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8227 if (I915_READ(DP_C) & DP_DETECTED)
8228 intel_dp_init(dev, DP_C, PORT_C);
8229
4a87d65d
JB		 8230 if (I915_READ(SDVOB) & PORT_DETECTED) {
8231 /* SDVOB multiplex with HDMIB */
8232 found = intel_sdvo_init(dev, SDVOB, true);
8233 if (!found)
08d644ad 8234 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8235 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8236 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8237 }
8238
8239 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8240 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8241
103a196f 8242 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8243 bool found = false;
7d57382e 8244
725e30ad 8245 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8246 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8247 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8248 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8249 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8250 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8251 }
27185ae1 8252
b01f2c3a
JB		 8253 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8254 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8255 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8256 }
725e30ad 8257 }
13520b05
KH		 8258
8259 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8260
b01f2c3a
JB		 8261 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8262 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8263 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8264 }
27185ae1
ML		 8265
8266 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8267
b01f2c3a
JB		 8268 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8269 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8270 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8271 }
8272 if (SUPPORTS_INTEGRATED_DP(dev)) {
8273 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8274 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8275 }
725e30ad 8276 }
27185ae1 8277
b01f2c3a
JB		 8278 if (SUPPORTS_INTEGRATED_DP(dev) &&
8279 (I915_READ(DP_D) & DP_DETECTED)) {
8280 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8281 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8282 }
bad720ff 8283 } else if (IS_GEN2(dev))
79e53945
JB		 8284 intel_dvo_init(dev);
8285
103a196f 8286 if (SUPPORTS_TV(dev))
79e53945
JB		 8287 intel_tv_init(dev);
8288
4ef69c7a
CW		 8289 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8290 encoder->base.possible_crtcs = encoder->crtc_mask;
8291 encoder->base.possible_clones =
66a9278e 8292 intel_encoder_clones(encoder);
79e53945 8293 }
47356eb6 8294
40579abe 8295 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8296 ironlake_init_pch_refclk(dev);
79e53945
JB		 8297}
8298
8299static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8300{
8301 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8302
8303 drm_framebuffer_cleanup(fb);
05394f39 8304 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8305
8306 kfree(intel_fb);
8307}
8308
8309static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8310 struct drm_file *file,
79e53945
JB		 8311 unsigned int *handle)
8312{
8313 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8314 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8315
05394f39 8316 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8317}
8318
8319static const struct drm_framebuffer_funcs intel_fb_funcs = {
8320 .destroy = intel_user_framebuffer_destroy,
8321 .create_handle = intel_user_framebuffer_create_handle,
8322};
8323
38651674
DA		 8324int intel_framebuffer_init(struct drm_device *dev,
8325 struct intel_framebuffer *intel_fb,
308e5bcb 8326 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8327 struct drm_i915_gem_object *obj)
79e53945 8328{
79e53945
JB		 8329 int ret;
8330
05394f39 8331 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8332 return -EINVAL;
8333
308e5bcb 8334 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8335 return -EINVAL;
8336
308e5bcb 8337 switch (mode_cmd->pixel_format) {
04b3924d
VS		 8338 case DRM_FORMAT_RGB332:
8339 case DRM_FORMAT_RGB565:
8340 case DRM_FORMAT_XRGB8888:
b250da79 8341 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 8342 case DRM_FORMAT_ARGB8888:
8343 case DRM_FORMAT_XRGB2101010:
8344 case DRM_FORMAT_ARGB2101010:
308e5bcb 8345 /* RGB formats are common across chipsets */
b5626747 8346 break;
04b3924d
VS		 8347 case DRM_FORMAT_YUYV:
8348 case DRM_FORMAT_UYVY:
8349 case DRM_FORMAT_YVYU:
8350 case DRM_FORMAT_VYUY:
57cd6508
CW		 8351 break;
8352 default:
aca25848
ED		 8353 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8354 mode_cmd->pixel_format);
57cd6508
CW		 8355 return -EINVAL;
8356 }
8357
79e53945
JB		 8358 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8359 if (ret) {
8360 DRM_ERROR("framebuffer init failed %d\n", ret);
8361 return ret;
8362 }
8363
8364 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8365 intel_fb->obj = obj;
79e53945
JB		 8366 return 0;
8367}
8368
79e53945
JB		 8369static struct drm_framebuffer *
8370intel_user_framebuffer_create(struct drm_device *dev,
8371 struct drm_file *filp,
308e5bcb 8372 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8373{
05394f39 8374 struct drm_i915_gem_object *obj;
79e53945 8375
308e5bcb
JB		 8376 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8377 mode_cmd->handles[0]));
c8725226 8378 if (&obj->base == NULL)
cce13ff7 8379 return ERR_PTR(-ENOENT);
79e53945 8380
d2dff872 8381 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8382}
8383
79e53945 8384static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8385 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8386 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8387};
8388
e70236a8
JB		 8389/* Set up chip specific display functions */
8390static void intel_init_display(struct drm_device *dev)
8391{
8392 struct drm_i915_private *dev_priv = dev->dev_private;
8393
8394 /* We always want a DPMS function */
09b4ddf9
PZ		 8395 if (IS_HASWELL(dev)) {
8396 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8397 dev_priv->display.crtc_enable = haswell_crtc_enable;
8398 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8399 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8400 dev_priv->display.update_plane = ironlake_update_plane;
8401 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8402 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8403 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8404 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8405 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8406 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8407 } else {
f564048e 8408 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8409 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8410 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8411 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8412 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8413 }
e70236a8 8414
e70236a8 8415 /* Returns the core display clock speed */
25eb05fc
JB		 8416 if (IS_VALLEYVIEW(dev))
8417 dev_priv->display.get_display_clock_speed =
8418 valleyview_get_display_clock_speed;
8419 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8420 dev_priv->display.get_display_clock_speed =
8421 i945_get_display_clock_speed;
8422 else if (IS_I915G(dev))
8423 dev_priv->display.get_display_clock_speed =
8424 i915_get_display_clock_speed;
f2b115e6 8425 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8426 dev_priv->display.get_display_clock_speed =
8427 i9xx_misc_get_display_clock_speed;
8428 else if (IS_I915GM(dev))
8429 dev_priv->display.get_display_clock_speed =
8430 i915gm_get_display_clock_speed;
8431 else if (IS_I865G(dev))
8432 dev_priv->display.get_display_clock_speed =
8433 i865_get_display_clock_speed;
f0f8a9ce 8434 else if (IS_I85X(dev))
e70236a8
JB		 8435 dev_priv->display.get_display_clock_speed =
8436 i855_get_display_clock_speed;
8437 else /* 852, 830 */
8438 dev_priv->display.get_display_clock_speed =
8439 i830_get_display_clock_speed;
8440
7f8a8569 8441 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8442 if (IS_GEN5(dev)) {
674cf967 8443 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8444 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8445 } else if (IS_GEN6(dev)) {
674cf967 8446 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8447 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8448 } else if (IS_IVYBRIDGE(dev)) {
8449 /* FIXME: detect B0+ stepping and use auto training */
8450 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8451 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8452 dev_priv->display.modeset_global_resources =
8453 ivb_modeset_global_resources;
c82e4d26
ED		 8454 } else if (IS_HASWELL(dev)) {
8455 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8456 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8457 } else
8458 dev_priv->display.update_wm = NULL;
6067aaea 8459 } else if (IS_G4X(dev)) {
e0dac65e 8460 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8461 }
8c9f3aaf
JB		 8462
8463 /* Default just returns -ENODEV to indicate unsupported */
8464 dev_priv->display.queue_flip = intel_default_queue_flip;
8465
8466 switch (INTEL_INFO(dev)->gen) {
8467 case 2:
8468 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8469 break;
8470
8471 case 3:
8472 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8473 break;
8474
8475 case 4:
8476 case 5:
8477 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8478 break;
8479
8480 case 6:
8481 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8482 break;
7c9017e5
JB		 8483 case 7:
8484 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8485 break;
8c9f3aaf 8486 }
e70236a8
JB		 8487}
8488
b690e96c
JB		 8489/*
8490 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8491 * resume, or other times. This quirk makes sure that's the case for
8492 * affected systems.
8493 */
0206e353 8494static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8495{
8496 struct drm_i915_private *dev_priv = dev->dev_private;
8497
8498 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8499 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8500}
8501
435793df
KP		 8502/*
8503 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8504 */
8505static void quirk_ssc_force_disable(struct drm_device *dev)
8506{
8507 struct drm_i915_private *dev_priv = dev->dev_private;
8508 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8509 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8510}
8511
4dca20ef 8512/*
5a15ab5b
CE		 8513 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8514 * brightness value
4dca20ef
CE		 8515 */
8516static void quirk_invert_brightness(struct drm_device *dev)
8517{
8518 struct drm_i915_private *dev_priv = dev->dev_private;
8519 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8520 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8521}
8522
b690e96c
JB		 8523struct intel_quirk {
8524 int device;
8525 int subsystem_vendor;
8526 int subsystem_device;
8527 void (*hook)(struct drm_device *dev);
8528};
8529
c43b5634 8530static struct intel_quirk intel_quirks[] = {
b690e96c 8531 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8532 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8533
b690e96c
JB		 8534 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8535 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8536
b690e96c
JB		 8537 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8538 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8539
ccd0d36e 8540 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8541 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8542 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8543
8544 /* Lenovo U160 cannot use SSC on LVDS */
8545 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8546
8547 /* Sony Vaio Y cannot use SSC on LVDS */
8548 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8549
8550 /* Acer Aspire 5734Z must invert backlight brightness */
8551 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8552};
8553
8554static void intel_init_quirks(struct drm_device *dev)
8555{
8556 struct pci_dev *d = dev->pdev;
8557 int i;
8558
8559 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8560 struct intel_quirk *q = &intel_quirks[i];
8561
8562 if (d->device == q->device &&
8563 (d->subsystem_vendor == q->subsystem_vendor ||
8564 q->subsystem_vendor == PCI_ANY_ID) &&
8565 (d->subsystem_device == q->subsystem_device ||
8566 q->subsystem_device == PCI_ANY_ID))
8567 q->hook(dev);
8568 }
8569}
8570
9cce37f4
JB		 8571/* Disable the VGA plane that we never use */
8572static void i915_disable_vga(struct drm_device *dev)
8573{
8574 struct drm_i915_private *dev_priv = dev->dev_private;
8575 u8 sr1;
8576 u32 vga_reg;
8577
8578 if (HAS_PCH_SPLIT(dev))
8579 vga_reg = CPU_VGACNTRL;
8580 else
8581 vga_reg = VGACNTRL;
8582
8583 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8584 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8585 sr1 = inb(VGA_SR_DATA);
8586 outb(sr1 | 1<<5, VGA_SR_DATA);
8587 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8588 udelay(300);
8589
8590 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8591 POSTING_READ(vga_reg);
8592}
8593
f817586c
DV		 8594void intel_modeset_init_hw(struct drm_device *dev)
8595{
0232e927
ED		 8596 /* We attempt to init the necessary power wells early in the initialization
8597 * time, so the subsystems that expect power to be enabled can work.
8598 */
8599 intel_init_power_wells(dev);
8600
a8f78b58
ED		 8601 intel_prepare_ddi(dev);
8602
f817586c
DV		 8603 intel_init_clock_gating(dev);
8604
79f5b2c7 8605 mutex_lock(&dev->struct_mutex);
8090c6b9 8606 intel_enable_gt_powersave(dev);
79f5b2c7 8607 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8608}
8609
79e53945
JB		 8610void intel_modeset_init(struct drm_device *dev)
8611{
652c393a 8612 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8613 int i, ret;
79e53945
JB		 8614
8615 drm_mode_config_init(dev);
8616
8617 dev->mode_config.min_width = 0;
8618 dev->mode_config.min_height = 0;
8619
019d96cb
DA		 8620 dev->mode_config.preferred_depth = 24;
8621 dev->mode_config.prefer_shadow = 1;
8622
e6ecefaa 8623 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8624
b690e96c
JB		 8625 intel_init_quirks(dev);
8626
1fa61106
ED		 8627 intel_init_pm(dev);
8628
e70236a8
JB		 8629 intel_init_display(dev);
8630
a6c45cf0
CW		 8631 if (IS_GEN2(dev)) {
8632 dev->mode_config.max_width = 2048;
8633 dev->mode_config.max_height = 2048;
8634 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8635 dev->mode_config.max_width = 4096;
8636 dev->mode_config.max_height = 4096;
79e53945 8637 } else {
a6c45cf0
CW		 8638 dev->mode_config.max_width = 8192;
8639 dev->mode_config.max_height = 8192;
79e53945 8640 }
dd2757f8 8641 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8642
28c97730 8643 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8644 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8645
a3524f1b 8646 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8647 intel_crtc_init(dev, i);
00c2064b
JB		 8648 ret = intel_plane_init(dev, i);
8649 if (ret)
8650 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8651 }
8652
79f689aa 8653 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8654 intel_pch_pll_init(dev);
8655
9cce37f4
JB		 8656 /* Just disable it once at startup */
8657 i915_disable_vga(dev);
79e53945 8658 intel_setup_outputs(dev);
2c7111db
CW		 8659}
8660
24929352
DV		 8661static void
8662intel_connector_break_all_links(struct intel_connector *connector)
8663{
8664 connector->base.dpms = DRM_MODE_DPMS_OFF;
8665 connector->base.encoder = NULL;
8666 connector->encoder->connectors_active = false;
8667 connector->encoder->base.crtc = NULL;
8668}
8669
7fad798e
DV		 8670static void intel_enable_pipe_a(struct drm_device *dev)
8671{
8672 struct intel_connector *connector;
8673 struct drm_connector *crt = NULL;
8674 struct intel_load_detect_pipe load_detect_temp;
8675
8676 /* We can't just switch on the pipe A, we need to set things up with a
8677 * proper mode and output configuration. As a gross hack, enable pipe A
8678 * by enabling the load detect pipe once. */
8679 list_for_each_entry(connector,
8680 &dev->mode_config.connector_list,
8681 base.head) {
8682 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8683 crt = &connector->base;
8684 break;
8685 }
8686 }
8687
8688 if (!crt)
8689 return;
8690
8691 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8692 intel_release_load_detect_pipe(crt, &load_detect_temp);
8693
8694
8695}
8696
fa555837
DV		 8697static bool
8698intel_check_plane_mapping(struct intel_crtc *crtc)
8699{
8700 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8701 u32 reg, val;
8702
8703 if (dev_priv->num_pipe == 1)
8704 return true;
8705
8706 reg = DSPCNTR(!crtc->plane);
8707 val = I915_READ(reg);
8708
8709 if ((val & DISPLAY_PLANE_ENABLE) &&
8710 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8711 return false;
8712
8713 return true;
8714}
8715
24929352
DV		 8716static void intel_sanitize_crtc(struct intel_crtc *crtc)
8717{
8718 struct drm_device *dev = crtc->base.dev;
8719 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8720 u32 reg;
24929352 8721
24929352 8722 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8723 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8724 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8725
8726 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8727 * disable the crtc (and hence change the state) if it is wrong. Note
8728 * that gen4+ has a fixed plane -> pipe mapping. */
8729 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8730 struct intel_connector *connector;
8731 bool plane;
8732
24929352
DV		 8733 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8734 crtc->base.base.id);
8735
8736 /* Pipe has the wrong plane attached and the plane is active.
8737 * Temporarily change the plane mapping and disable everything
8738 * ... */
8739 plane = crtc->plane;
8740 crtc->plane = !plane;
8741 dev_priv->display.crtc_disable(&crtc->base);
8742 crtc->plane = plane;
8743
8744 /* ... and break all links. */
8745 list_for_each_entry(connector, &dev->mode_config.connector_list,
8746 base.head) {
8747 if (connector->encoder->base.crtc != &crtc->base)
8748 continue;
8749
8750 intel_connector_break_all_links(connector);
8751 }
8752
8753 WARN_ON(crtc->active);
8754 crtc->base.enabled = false;
8755 }
24929352 8756
7fad798e
DV		 8757 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8758 crtc->pipe == PIPE_A && !crtc->active) {
8759 /* BIOS forgot to enable pipe A, this mostly happens after
8760 * resume. Force-enable the pipe to fix this, the update_dpms
8761 * call below we restore the pipe to the right state, but leave
8762 * the required bits on. */
8763 intel_enable_pipe_a(dev);
8764 }
8765
24929352
DV		 8766 /* Adjust the state of the output pipe according to whether we
8767 * have active connectors/encoders. */
8768 intel_crtc_update_dpms(&crtc->base);
8769
8770 if (crtc->active != crtc->base.enabled) {
8771 struct intel_encoder *encoder;
8772
8773 /* This can happen either due to bugs in the get_hw_state
8774 * functions or because the pipe is force-enabled due to the
8775 * pipe A quirk. */
8776 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8777 crtc->base.base.id,
8778 crtc->base.enabled ? "enabled" : "disabled",
8779 crtc->active ? "enabled" : "disabled");
8780
8781 crtc->base.enabled = crtc->active;
8782
8783 /* Because we only establish the connector -> encoder ->
8784 * crtc links if something is active, this means the
8785 * crtc is now deactivated. Break the links. connector
8786 * -> encoder links are only establish when things are
8787 * actually up, hence no need to break them. */
8788 WARN_ON(crtc->active);
8789
8790 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8791 WARN_ON(encoder->connectors_active);
8792 encoder->base.crtc = NULL;
8793 }
8794 }
8795}
8796
8797static void intel_sanitize_encoder(struct intel_encoder *encoder)
8798{
8799 struct intel_connector *connector;
8800 struct drm_device *dev = encoder->base.dev;
8801
8802 /* We need to check both for a crtc link (meaning that the
8803 * encoder is active and trying to read from a pipe) and the
8804 * pipe itself being active. */
8805 bool has_active_crtc = encoder->base.crtc &&
8806 to_intel_crtc(encoder->base.crtc)->active;
8807
8808 if (encoder->connectors_active && !has_active_crtc) {
8809 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8810 encoder->base.base.id,
8811 drm_get_encoder_name(&encoder->base));
8812
8813 /* Connector is active, but has no active pipe. This is
8814 * fallout from our resume register restoring. Disable
8815 * the encoder manually again. */
8816 if (encoder->base.crtc) {
8817 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8818 encoder->base.base.id,
8819 drm_get_encoder_name(&encoder->base));
8820 encoder->disable(encoder);
8821 }
8822
8823 /* Inconsistent output/port/pipe state happens presumably due to
8824 * a bug in one of the get_hw_state functions. Or someplace else
8825 * in our code, like the register restore mess on resume. Clamp
8826 * things to off as a safer default. */
8827 list_for_each_entry(connector,
8828 &dev->mode_config.connector_list,
8829 base.head) {
8830 if (connector->encoder != encoder)
8831 continue;
8832
8833 intel_connector_break_all_links(connector);
8834 }
8835 }
8836 /* Enabled encoders without active connectors will be fixed in
8837 * the crtc fixup. */
8838}
8839
8840/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8841 * and i915 state tracking structures. */
8842void intel_modeset_setup_hw_state(struct drm_device *dev)
8843{
8844 struct drm_i915_private *dev_priv = dev->dev_private;
8845 enum pipe pipe;
8846 u32 tmp;
8847 struct intel_crtc *crtc;
8848 struct intel_encoder *encoder;
8849 struct intel_connector *connector;
8850
e28d54cb
PZ		 8851 if (IS_HASWELL(dev)) {
8852 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8853
8854 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8855 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8856 case TRANS_DDI_EDP_INPUT_A_ON:
8857 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8858 pipe = PIPE_A;
8859 break;
8860 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8861 pipe = PIPE_B;
8862 break;
8863 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8864 pipe = PIPE_C;
8865 break;
8866 }
8867
8868 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8869 crtc->cpu_transcoder = TRANSCODER_EDP;
8870
8871 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8872 pipe_name(pipe));
8873 }
8874 }
8875
24929352
DV		 8876 for_each_pipe(pipe) {
8877 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8878
702e7a56 8879 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8880 if (tmp & PIPECONF_ENABLE)
8881 crtc->active = true;
8882 else
8883 crtc->active = false;
8884
8885 crtc->base.enabled = crtc->active;
8886
8887 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8888 crtc->base.base.id,
8889 crtc->active ? "enabled" : "disabled");
8890 }
8891
6441ab5f
PZ		 8892 if (IS_HASWELL(dev))
8893 intel_ddi_setup_hw_pll_state(dev);
8894
24929352
DV		 8895 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8896 base.head) {
8897 pipe = 0;
8898
8899 if (encoder->get_hw_state(encoder, &pipe)) {
8900 encoder->base.crtc =
8901 dev_priv->pipe_to_crtc_mapping[pipe];
8902 } else {
8903 encoder->base.crtc = NULL;
8904 }
8905
8906 encoder->connectors_active = false;
8907 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8908 encoder->base.base.id,
8909 drm_get_encoder_name(&encoder->base),
8910 encoder->base.crtc ? "enabled" : "disabled",
8911 pipe);
8912 }
8913
8914 list_for_each_entry(connector, &dev->mode_config.connector_list,
8915 base.head) {
8916 if (connector->get_hw_state(connector)) {
8917 connector->base.dpms = DRM_MODE_DPMS_ON;
8918 connector->encoder->connectors_active = true;
8919 connector->base.encoder = &connector->encoder->base;
8920 } else {
8921 connector->base.dpms = DRM_MODE_DPMS_OFF;
8922 connector->base.encoder = NULL;
8923 }
8924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8925 connector->base.base.id,
8926 drm_get_connector_name(&connector->base),
8927 connector->base.encoder ? "enabled" : "disabled");
8928 }
8929
8930 /* HW state is read out, now we need to sanitize this mess. */
8931 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8932 base.head) {
8933 intel_sanitize_encoder(encoder);
8934 }
8935
8936 for_each_pipe(pipe) {
8937 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8938 intel_sanitize_crtc(crtc);
8939 }
9a935856
DV		 8940
8941 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 8942
8943 intel_modeset_check_state(dev);
2e938892
DV		 8944
8945 drm_mode_config_reset(dev);
24929352
DV		 8946}
8947
2c7111db
CW		 8948void intel_modeset_gem_init(struct drm_device *dev)
8949{
1833b134 8950 intel_modeset_init_hw(dev);
02e792fb
DV		 8951
8952 intel_setup_overlay(dev);
24929352
DV		 8953
8954 intel_modeset_setup_hw_state(dev);
79e53945
JB		 8955}
8956
8957void intel_modeset_cleanup(struct drm_device *dev)
8958{
652c393a
JB		 8959 struct drm_i915_private *dev_priv = dev->dev_private;
8960 struct drm_crtc *crtc;
8961 struct intel_crtc *intel_crtc;
8962
f87ea761 8963 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8964 mutex_lock(&dev->struct_mutex);
8965
723bfd70
JB		 8966 intel_unregister_dsm_handler();
8967
8968
652c393a
JB		 8969 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8970 /* Skip inactive CRTCs */
8971 if (!crtc->fb)
8972 continue;
8973
8974 intel_crtc = to_intel_crtc(crtc);
3dec0095 8975 intel_increase_pllclock(crtc);
652c393a
JB		 8976 }
8977
973d04f9 8978 intel_disable_fbc(dev);
e70236a8 8979
8090c6b9 8980 intel_disable_gt_powersave(dev);
0cdab21f 8981
930ebb46
DV		 8982 ironlake_teardown_rc6(dev);
8983
57f350b6
JB		 8984 if (IS_VALLEYVIEW(dev))
8985 vlv_init_dpio(dev);
8986
69341a5e
KH		 8987 mutex_unlock(&dev->struct_mutex);
8988
6c0d9350
DV		 8989 /* Disable the irq before mode object teardown, for the irq might
8990 * enqueue unpin/hotplug work. */
8991 drm_irq_uninstall(dev);
8992 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8993 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8994
1630fe75
CW		 8995 /* flush any delayed tasks or pending work */
8996 flush_scheduled_work();
8997
79e53945
JB		 8998 drm_mode_config_cleanup(dev);
8999}
9000
f1c79df3
ZW		 9001/*
9002 * Return which encoder is currently attached for connector.
9003 */
df0e9248 9004struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9005{
df0e9248
CW		 9006 return &intel_attached_encoder(connector)->base;
9007}
f1c79df3 9008
df0e9248
CW		 9009void intel_connector_attach_encoder(struct intel_connector *connector,
9010 struct intel_encoder *encoder)
9011{
9012 connector->encoder = encoder;
9013 drm_mode_connector_attach_encoder(&connector->base,
9014 &encoder->base);
79e53945 9015}
28d52043
DA		 9016
9017/*
9018 * set vga decode state - true == enable VGA decode
9019 */
9020int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9021{
9022 struct drm_i915_private *dev_priv = dev->dev_private;
9023 u16 gmch_ctrl;
9024
9025 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9026 if (state)
9027 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9028 else
9029 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9030 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9031 return 0;
9032}
c4a1d9e4
CW		 9033
9034#ifdef CONFIG_DEBUG_FS
9035#include <linux/seq_file.h>
9036
9037struct intel_display_error_state {
9038 struct intel_cursor_error_state {
9039 u32 control;
9040 u32 position;
9041 u32 base;
9042 u32 size;
52331309 9043 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9044
9045 struct intel_pipe_error_state {
9046 u32 conf;
9047 u32 source;
9048
9049 u32 htotal;
9050 u32 hblank;
9051 u32 hsync;
9052 u32 vtotal;
9053 u32 vblank;
9054 u32 vsync;
52331309 9055 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9056
9057 struct intel_plane_error_state {
9058 u32 control;
9059 u32 stride;
9060 u32 size;
9061 u32 pos;
9062 u32 addr;
9063 u32 surface;
9064 u32 tile_offset;
52331309 9065 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9066};
9067
9068struct intel_display_error_state *
9069intel_display_capture_error_state(struct drm_device *dev)
9070{
0206e353 9071 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9072 struct intel_display_error_state *error;
702e7a56 9073 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9074 int i;
9075
9076 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9077 if (error == NULL)
9078 return NULL;
9079
52331309 9080 for_each_pipe(i) {
702e7a56
PZ		 9081 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9082
c4a1d9e4
CW		 9083 error->cursor[i].control = I915_READ(CURCNTR(i));
9084 error->cursor[i].position = I915_READ(CURPOS(i));
9085 error->cursor[i].base = I915_READ(CURBASE(i));
9086
9087 error->plane[i].control = I915_READ(DSPCNTR(i));
9088 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9089 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9090 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9091 error->plane[i].addr = I915_READ(DSPADDR(i));
9092 if (INTEL_INFO(dev)->gen >= 4) {
9093 error->plane[i].surface = I915_READ(DSPSURF(i));
9094 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9095 }
9096
702e7a56 9097 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9098 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9099 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9100 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9101 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9102 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9103 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9104 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9105 }
9106
9107 return error;
9108}
9109
9110void
9111intel_display_print_error_state(struct seq_file *m,
9112 struct drm_device *dev,
9113 struct intel_display_error_state *error)
9114{
52331309 9115 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9116 int i;
9117
52331309
DL		 9118 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9119 for_each_pipe(i) {
c4a1d9e4
CW		 9120 seq_printf(m, "Pipe [%d]:\n", i);
9121 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9122 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9123 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9124 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9125 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9126 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9127 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9128 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9129
9130 seq_printf(m, "Plane [%d]:\n", i);
9131 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9132 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9133 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9134 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9135 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9136 if (INTEL_INFO(dev)->gen >= 4) {
9137 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9138 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9139 }
9140
9141 seq_printf(m, "Cursor [%d]:\n", i);
9142 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9143 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9144 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9145 }
9146}
9147#endif
Linux kernel - Deliverables
This page took 1.287506 seconds and 5 git commands to generate.