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drm/i915: Notify GuC rc6 state
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
eb1bfe80
JB		 89static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
5b18e57c
DV		 93static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 95static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
29407aab 98static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 99static void haswell_set_pipeconf(struct drm_crtc *crtc);
100static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 101static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
d288f65f 103static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 105static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
106static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 107static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 109static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
043e9bda 111static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 112
79e53945 113typedef struct {
0206e353 114 int min, max;
79e53945
JB		 115} intel_range_t;
116
117typedef struct {
0206e353
AJ		 118 int dot_limit;
119 int p2_slow, p2_fast;
79e53945
JB		 120} intel_p2_t;
121
d4906093
ML		 122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
0206e353
AJ		 124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
d4906093 126};
79e53945 127
d2acd215
DV		 128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
021357ac
CW		 138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
8b99e68c
CW		 141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
021357ac
CW		 146}
147
5d536e28 148static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 149 .dot = { .min = 25000, .max = 350000 },
9c333719 150 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 151 .n = { .min = 2, .max = 16 },
0206e353
AJ		 152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 159};
160
5d536e28
DV		 161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
9c333719 163 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 164 .n = { .min = 2, .max = 16 },
5d536e28
DV		 165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
e4b36699 174static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 175 .dot = { .min = 25000, .max = 350000 },
9c333719 176 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 177 .n = { .min = 2, .max = 16 },
0206e353
AJ		 178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
e4b36699 185};
273e27ca 186
e4b36699 187static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 211};
212
273e27ca 213
e4b36699 214static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
044c7c41 226 },
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
044c7c41 253 },
e4b36699
KP		 254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
044c7c41 267 },
e4b36699
KP		 268};
269
f2b115e6 270static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 273 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
273e27ca 276 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 283};
284
f2b115e6 285static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 296};
297
273e27ca
EA		 298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
b91ad0ec 303static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 314};
315
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 340};
341
273e27ca 342/* LVDS 100mhz refclk limits. */
b91ad0ec 343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
0206e353 351 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
0206e353 364 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 367};
368
dc730512 369static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 377 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 378 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
b99ab663 381 .p1 = { .min = 2, .max = 3 },
5fdc9c49 382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 383};
384
ef9348c8
CML		 385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 393 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
5ab7b0b7
ID		 401static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
e6292556 404 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
411};
412
cdba954e
ACO		 413static bool
414needs_modeset(struct drm_crtc_state *state)
415{
fc596660 416 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 417}
418
e0638cdf
PZ		 419/**
420 * Returns whether any output on the specified pipe is of the specified type
421 */
4093561b 422bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 423{
409ee761 424 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 425 struct intel_encoder *encoder;
426
409ee761 427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 428 if (encoder->type == type)
429 return true;
430
431 return false;
432}
433
d0737e1d
ACO		 434/**
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
438 * encoder->crtc.
439 */
a93e255f
ACO		 440static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
441 int type)
d0737e1d 442{
a93e255f 443 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 444 struct drm_connector *connector;
a93e255f 445 struct drm_connector_state *connector_state;
d0737e1d 446 struct intel_encoder *encoder;
a93e255f
ACO		 447 int i, num_connectors = 0;
448
da3ced29 449 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 450 if (connector_state->crtc != crtc_state->base.crtc)
451 continue;
452
453 num_connectors++;
d0737e1d 454
a93e255f
ACO		 455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
d0737e1d 457 return true;
a93e255f
ACO		 458 }
459
460 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 461
462 return false;
463}
464
a93e255f
ACO		 465static const intel_limit_t *
466intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 467{
a93e255f 468 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 469 const intel_limit_t *limit;
b91ad0ec 470
a93e255f 471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 472 if (intel_is_dual_link_lvds(dev)) {
1b894b59 473 if (refclk == 100000)
b91ad0ec
ZW		 474 limit = &intel_limits_ironlake_dual_lvds_100m;
475 else
476 limit = &intel_limits_ironlake_dual_lvds;
477 } else {
1b894b59 478 if (refclk == 100000)
b91ad0ec
ZW		 479 limit = &intel_limits_ironlake_single_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_single_lvds;
482 }
c6bb3538 483 } else
b91ad0ec 484 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 485
486 return limit;
487}
488
a93e255f
ACO		 489static const intel_limit_t *
490intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 491{
a93e255f 492 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 493 const intel_limit_t *limit;
494
a93e255f 495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 496 if (intel_is_dual_link_lvds(dev))
e4b36699 497 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 498 else
e4b36699 499 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 502 limit = &intel_limits_g4x_hdmi;
a93e255f 503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 504 limit = &intel_limits_g4x_sdvo;
044c7c41 505 } else /* The option is for other outputs */
e4b36699 506 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 507
508 return limit;
509}
510
a93e255f
ACO		 511static const intel_limit_t *
512intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 513{
a93e255f 514 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 515 const intel_limit_t *limit;
516
5ab7b0b7
ID		 517 if (IS_BROXTON(dev))
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
a93e255f 520 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 521 else if (IS_G4X(dev)) {
a93e255f 522 limit = intel_g4x_limit(crtc_state);
f2b115e6 523 } else if (IS_PINEVIEW(dev)) {
a93e255f 524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 525 limit = &intel_limits_pineview_lvds;
2177832f 526 else
f2b115e6 527 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
a0c4da24 530 } else if (IS_VALLEYVIEW(dev)) {
dc730512 531 limit = &intel_limits_vlv;
a6c45cf0 532 } else if (!IS_GEN2(dev)) {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 534 limit = &intel_limits_i9xx_lvds;
535 else
536 limit = &intel_limits_i9xx_sdvo;
79e53945 537 } else {
a93e255f 538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 539 limit = &intel_limits_i8xx_lvds;
a93e255f 540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 541 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 542 else
543 limit = &intel_limits_i8xx_dac;
79e53945
JB		 544 }
545 return limit;
546}
547
dccbea3b
ID		 548/*
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
555 */
f2b115e6 556/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 557static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 558{
2177832f
SL		 559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
ed5ca77e 561 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 562 return 0;
fb03ac01
VS		 563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 565
566 return clock->dot;
2177832f
SL		 567}
568
7429e9d4
DV		 569static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570{
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572}
573
dccbea3b 574static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 575{
7429e9d4 576 clock->m = i9xx_dpll_compute_m(clock);
79e53945 577 clock->p = clock->p1 * clock->p2;
ed5ca77e 578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 579 return 0;
fb03ac01
VS		 580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 582
583 return clock->dot;
79e53945
JB		 584}
585
dccbea3b 586static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 587{
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 591 return 0;
589eca67
ID		 592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 594
595 return clock->dot / 5;
589eca67
ID		 596}
597
dccbea3b 598int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 599{
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 603 return 0;
ef9348c8
CML		 604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
605 clock->n << 22);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 607
608 return clock->dot / 5;
ef9348c8
CML		 609}
610
7c04d1d9 611#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 612/**
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
615 */
616
1b894b59
CW		 617static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
79e53945 620{
f01b7962
VS		 621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
79e53945 623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 624 INTELPllInvalid("p1 out of range\n");
79e53945 625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 626 INTELPllInvalid("m2 out of range\n");
79e53945 627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 628 INTELPllInvalid("m1 out of range\n");
f01b7962 629
5ab7b0b7 630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
633
5ab7b0b7 634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
639 }
640
79e53945 641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 642 INTELPllInvalid("vco out of range\n");
79e53945
JB		 643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
645 */
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 647 INTELPllInvalid("dot out of range\n");
79e53945
JB		 648
649 return true;
650}
651
3b1429d9
VS		 652static int
653i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
655 int target)
79e53945 656{
3b1429d9 657 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 658
a93e255f 659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 660 /*
a210b028
DV		 661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
79e53945 664 */
1974cad0 665 if (intel_is_dual_link_lvds(dev))
3b1429d9 666 return limit->p2.p2_fast;
79e53945 667 else
3b1429d9 668 return limit->p2.p2_slow;
79e53945
JB		 669 } else {
670 if (target < limit->p2.dot_limit)
3b1429d9 671 return limit->p2.p2_slow;
79e53945 672 else
3b1429d9 673 return limit->p2.p2_fast;
79e53945 674 }
3b1429d9
VS		 675}
676
677static bool
678i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
682{
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684 intel_clock_t clock;
685 int err = target;
79e53945 686
0206e353 687 memset(best_clock, 0, sizeof(*best_clock));
79e53945 688
3b1429d9
VS		 689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
690
42158660
ZY		 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 695 if (clock.m2 >= clock.m1)
42158660
ZY		 696 break;
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 701 int this_err;
702
dccbea3b 703 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 704 if (!intel_PLL_is_valid(dev, limit,
705 &clock))
706 continue;
707 if (match_clock &&
708 clock.p != match_clock->p)
709 continue;
710
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
713 *best_clock = clock;
714 err = this_err;
715 }
716 }
717 }
718 }
719 }
720
721 return (err != target);
722}
723
724static bool
a93e255f
ACO		 725pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
79e53945 729{
3b1429d9 730 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 731 intel_clock_t clock;
79e53945
JB		 732 int err = target;
733
0206e353 734 memset(best_clock, 0, sizeof(*best_clock));
79e53945 735
3b1429d9
VS		 736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737
42158660
ZY		 738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 clock.m1++) {
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 746 int this_err;
747
dccbea3b 748 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
79e53945 751 continue;
cec2f356
SP		 752 if (match_clock &&
753 clock.p != match_clock->p)
754 continue;
79e53945
JB		 755
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
758 *best_clock = clock;
759 err = this_err;
760 }
761 }
762 }
763 }
764 }
765
766 return (err != target);
767}
768
d4906093 769static bool
a93e255f
ACO		 770g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
d4906093 774{
3b1429d9 775 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 776 intel_clock_t clock;
777 int max_n;
3b1429d9 778 bool found = false;
6ba770dc
AJ		 779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 781
782 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
d4906093 786 max_n = limit->n.max;
f77f13e2 787 /* based on hardware requirement, prefer smaller n to precision */
d4906093 788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 789 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
796 int this_err;
797
dccbea3b 798 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 799 if (!intel_PLL_is_valid(dev, limit,
800 &clock))
d4906093 801 continue;
1b894b59
CW		 802
803 this_err = abs(clock.dot - target);
d4906093
ML		 804 if (this_err < err_most) {
805 *best_clock = clock;
806 err_most = this_err;
807 max_n = clock.n;
808 found = true;
809 }
810 }
811 }
812 }
813 }
2c07245f
ZW		 814 return found;
815}
816
d5dd62bd
ID		 817/*
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
820 */
821static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
826{
9ca3ba01
ID		 827 /*
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
830 */
831 if (IS_CHERRYVIEW(dev)) {
832 *error_ppm = 0;
833
834 return calculated_clock->p > best_clock->p;
835 }
836
24be4e46
ID		 837 if (WARN_ON_ONCE(!target_freq))
838 return false;
839
d5dd62bd
ID		 840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
842 target_freq);
843 /*
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
847 */
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
849 *error_ppm = 0;
850
851 return true;
852 }
853
854 return *error_ppm + 10 < best_error_ppm;
855}
856
a0c4da24 857static bool
a93e255f
ACO		 858vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
a0c4da24 862{
a93e255f 863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 864 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 865 intel_clock_t clock;
69e4f900 866 unsigned int bestppm = 1000000;
27e639bf
VS		 867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 869 bool found = false;
a0c4da24 870
6b4bf1c4
VS		 871 target *= 5; /* fast clock */
872
873 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 874
875 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 880 clock.p = clock.p1 * clock.p2;
a0c4da24 881 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 883 unsigned int ppm;
69e4f900 884
6b4bf1c4
VS		 885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
886 refclk * clock.m1);
887
dccbea3b 888 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 889
f01b7962
VS		 890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
43b0ac53
VS		 892 continue;
893
d5dd62bd
ID		 894 if (!vlv_PLL_is_optimal(dev, target,
895 &clock,
896 best_clock,
897 bestppm, &ppm))
898 continue;
6b4bf1c4 899
d5dd62bd
ID		 900 *best_clock = clock;
901 bestppm = ppm;
902 found = true;
a0c4da24
JB		 903 }
904 }
905 }
906 }
a0c4da24 907
49e497ef 908 return found;
a0c4da24 909}
a4fc5ed6 910
ef9348c8 911static bool
a93e255f
ACO		 912chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
916{
a93e255f 917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 918 struct drm_device *dev = crtc->base.dev;
9ca3ba01 919 unsigned int best_error_ppm;
ef9348c8
CML		 920 intel_clock_t clock;
921 uint64_t m2;
922 int found = false;
923
924 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 925 best_error_ppm = 1000000;
ef9348c8
CML		 926
927 /*
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
931 */
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
934
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 939 unsigned int error_ppm;
ef9348c8
CML		 940
941 clock.p = clock.p1 * clock.p2;
942
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
945
946 if (m2 > INT_MAX/clock.m1)
947 continue;
948
949 clock.m2 = m2;
950
dccbea3b 951 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 952
953 if (!intel_PLL_is_valid(dev, limit, &clock))
954 continue;
955
9ca3ba01
ID		 956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
958 continue;
959
960 *best_clock = clock;
961 best_error_ppm = error_ppm;
962 found = true;
ef9348c8
CML		 963 }
964 }
965
966 return found;
967}
968
5ab7b0b7
ID		 969bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
971{
972 int refclk = i9xx_get_refclk(crtc_state, 0);
973
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
976}
977
20ddf665
VS		 978bool intel_crtc_active(struct drm_crtc *crtc)
979{
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
981
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
984 *
241bfc38 985 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 986 * as Haswell has gained clock readout/fastboot support.
987 *
66e514c1 988 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 989 * properly reconstruct framebuffers.
c3d1f436
MR		 990 *
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
993 * for atomic.
20ddf665 994 */
c3d1f436 995 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 996 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 997}
998
a5c961d1
PZ		 999enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001{
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
6e3c9717 1005 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1006}
1007
fbf49ea2
VS		 1008static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009{
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1012 u32 line1, line2;
1013 u32 line_mask;
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1021 msleep(5);
fbf49ea2
VS		 1022 line2 = I915_READ(reg) & line_mask;
1023
1024 return line1 == line2;
1025}
1026
ab7ad7f6
KP		 1027/*
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1029 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1030 *
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1034 *
ab7ad7f6
KP		 1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1037 *
1038 * Otherwise:
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
58e10eb9 1041 *
9d0498a2 1042 */
575f7ab7 1043static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1044{
575f7ab7 1045 struct drm_device *dev = crtc->base.dev;
9d0498a2 1046 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1048 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1051 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1052
1053 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055 100))
284637d9 1056 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1057 } else {
ab7ad7f6 1058 /* Wait for the display line to settle */
fbf49ea2 1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1060 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1061 }
79e53945
JB		 1062}
1063
b24e7179
JB		 1064static const char *state_string(bool enabled)
1065{
1066 return enabled ? "on" : "off";
1067}
1068
1069/* Only for pre-ILK configs */
55607e8a
DV		 1070void assert_pll(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, bool state)
b24e7179
JB		 1072{
1073 int reg;
1074 u32 val;
1075 bool cur_state;
1076
1077 reg = DPLL(pipe);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1080 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1081 "PLL state assertion failure (expected %s, current %s)\n",
1082 state_string(state), state_string(cur_state));
1083}
b24e7179 1084
23538ef1
JN		 1085/* XXX: the dsi pll is shared between MIPI DSI ports */
1086static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1087{
1088 u32 val;
1089 bool cur_state;
1090
a580516d 1091 mutex_lock(&dev_priv->sb_lock);
23538ef1 1092 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1093 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1094
1095 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1096 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1097 "DSI PLL state assertion failure (expected %s, current %s)\n",
1098 state_string(state), state_string(cur_state));
1099}
1100#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1101#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1102
55607e8a 1103struct intel_shared_dpll *
e2b78267
DV		 1104intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1105{
1106 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1107
6e3c9717 1108 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1109 return NULL;
1110
6e3c9717 1111 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1112}
1113
040484af 1114/* For ILK+ */
55607e8a
DV		 1115void assert_shared_dpll(struct drm_i915_private *dev_priv,
1116 struct intel_shared_dpll *pll,
1117 bool state)
040484af 1118{
040484af 1119 bool cur_state;
5358901f 1120 struct intel_dpll_hw_state hw_state;
040484af 1121
92b27b08 1122 if (WARN (!pll,
46edb027 1123 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1124 return;
ee7b9f93 1125
5358901f 1126 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1127 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1128 "%s assertion failure (expected %s, current %s)\n",
1129 pll->name, state_string(state), state_string(cur_state));
040484af 1130}
040484af
JB		 1131
1132static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1133 enum pipe pipe, bool state)
1134{
1135 int reg;
1136 u32 val;
1137 bool cur_state;
ad80a810
PZ		 1138 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1139 pipe);
040484af 1140
affa9354
PZ		 1141 if (HAS_DDI(dev_priv->dev)) {
1142 /* DDI does not have a specific FDI_TX register */
ad80a810 1143 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1144 val = I915_READ(reg);
ad80a810 1145 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1146 } else {
1147 reg = FDI_TX_CTL(pipe);
1148 val = I915_READ(reg);
1149 cur_state = !!(val & FDI_TX_ENABLE);
1150 }
e2c719b7 1151 I915_STATE_WARN(cur_state != state,
040484af
JB		 1152 "FDI TX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1156#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1157
1158static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1159 enum pipe pipe, bool state)
1160{
1161 int reg;
1162 u32 val;
1163 bool cur_state;
1164
d63fa0dc
PZ		 1165 reg = FDI_RX_CTL(pipe);
1166 val = I915_READ(reg);
1167 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1168 I915_STATE_WARN(cur_state != state,
040484af
JB		 1169 "FDI RX state assertion failure (expected %s, current %s)\n",
1170 state_string(state), state_string(cur_state));
1171}
1172#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1173#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1174
1175static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int reg;
1179 u32 val;
1180
1181 /* ILK FDI PLL is always enabled */
3d13ef2e 1182 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1183 return;
1184
bf507ef7 1185 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1186 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1187 return;
1188
040484af
JB		 1189 reg = FDI_TX_CTL(pipe);
1190 val = I915_READ(reg);
e2c719b7 1191 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1192}
1193
55607e8a
DV		 1194void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1195 enum pipe pipe, bool state)
040484af
JB		 1196{
1197 int reg;
1198 u32 val;
55607e8a 1199 bool cur_state;
040484af
JB		 1200
1201 reg = FDI_RX_CTL(pipe);
1202 val = I915_READ(reg);
55607e8a 1203 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1204 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1205 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1206 state_string(state), state_string(cur_state));
040484af
JB		 1207}
1208
b680c37a
DV		 1209void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
ea0760cf 1211{
bedd4dba
JN		 1212 struct drm_device *dev = dev_priv->dev;
1213 int pp_reg;
ea0760cf
JB		 1214 u32 val;
1215 enum pipe panel_pipe = PIPE_A;
0de3b485 1216 bool locked = true;
ea0760cf 1217
bedd4dba
JN		 1218 if (WARN_ON(HAS_DDI(dev)))
1219 return;
1220
1221 if (HAS_PCH_SPLIT(dev)) {
1222 u32 port_sel;
1223
ea0760cf 1224 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1225 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1226
1227 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1228 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1229 panel_pipe = PIPE_B;
1230 /* XXX: else fix for eDP */
1231 } else if (IS_VALLEYVIEW(dev)) {
1232 /* presumably write lock depends on pipe, not port select */
1233 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1234 panel_pipe = pipe;
ea0760cf
JB		 1235 } else {
1236 pp_reg = PP_CONTROL;
bedd4dba
JN		 1237 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1238 panel_pipe = PIPE_B;
ea0760cf
JB		 1239 }
1240
1241 val = I915_READ(pp_reg);
1242 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1243 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1244 locked = false;
1245
e2c719b7 1246 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1247 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1248 pipe_name(pipe));
ea0760cf
JB		 1249}
1250
93ce0ba6
JN		 1251static void assert_cursor(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
1253{
1254 struct drm_device *dev = dev_priv->dev;
1255 bool cur_state;
1256
d9d82081 1257 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1258 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1259 else
5efb3e28 1260 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1261
e2c719b7 1262 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1263 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1264 pipe_name(pipe), state_string(state), state_string(cur_state));
1265}
1266#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1267#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1268
b840d907
JB		 1269void assert_pipe(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, bool state)
b24e7179
JB		 1271{
1272 int reg;
1273 u32 val;
63d7bbe9 1274 bool cur_state;
702e7a56
PZ		 1275 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1276 pipe);
b24e7179 1277
b6b5d049
VS		 1278 /* if we need the pipe quirk it must be always on */
1279 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1280 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1281 state = true;
1282
f458ebbc 1283 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1284 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1285 cur_state = false;
1286 } else {
1287 reg = PIPECONF(cpu_transcoder);
1288 val = I915_READ(reg);
1289 cur_state = !!(val & PIPECONF_ENABLE);
1290 }
1291
e2c719b7 1292 I915_STATE_WARN(cur_state != state,
63d7bbe9 1293 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1294 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1295}
1296
931872fc
CW		 1297static void assert_plane(struct drm_i915_private *dev_priv,
1298 enum plane plane, bool state)
b24e7179
JB		 1299{
1300 int reg;
1301 u32 val;
931872fc 1302 bool cur_state;
b24e7179
JB		 1303
1304 reg = DSPCNTR(plane);
1305 val = I915_READ(reg);
931872fc 1306 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1307 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1308 "plane %c assertion failure (expected %s, current %s)\n",
1309 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1310}
1311
931872fc
CW		 1312#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1313#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1314
b24e7179
JB		 1315static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
653e1026 1318 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1319 int reg, i;
1320 u32 val;
1321 int cur_pipe;
1322
653e1026
VS		 1323 /* Primary planes are fixed to pipes on gen4+ */
1324 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1325 reg = DSPCNTR(pipe);
1326 val = I915_READ(reg);
e2c719b7 1327 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1328 "plane %c assertion failure, should be disabled but not\n",
1329 plane_name(pipe));
19ec1358 1330 return;
28c05794 1331 }
19ec1358 1332
b24e7179 1333 /* Need to check both planes against the pipe */
055e393f 1334 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1335 reg = DSPCNTR(i);
1336 val = I915_READ(reg);
1337 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1338 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1339 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1340 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1341 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1342 }
1343}
1344
19332d7a
JB		 1345static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1346 enum pipe pipe)
1347{
20674eef 1348 struct drm_device *dev = dev_priv->dev;
1fe47785 1349 int reg, sprite;
19332d7a
JB		 1350 u32 val;
1351
7feb8b88 1352 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1353 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1354 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1355 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1356 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1357 sprite, pipe_name(pipe));
1358 }
1359 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1360 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1361 reg = SPCNTR(pipe, sprite);
20674eef 1362 val = I915_READ(reg);
e2c719b7 1363 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1364 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1365 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1366 }
1367 } else if (INTEL_INFO(dev)->gen >= 7) {
1368 reg = SPRCTL(pipe);
19332d7a 1369 val = I915_READ(reg);
e2c719b7 1370 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1371 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1372 plane_name(pipe), pipe_name(pipe));
1373 } else if (INTEL_INFO(dev)->gen >= 5) {
1374 reg = DVSCNTR(pipe);
19332d7a 1375 val = I915_READ(reg);
e2c719b7 1376 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1377 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1378 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1379 }
1380}
1381
08c71e5e
VS		 1382static void assert_vblank_disabled(struct drm_crtc *crtc)
1383{
e2c719b7 1384 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1385 drm_crtc_vblank_put(crtc);
1386}
1387
89eff4be 1388static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1389{
1390 u32 val;
1391 bool enabled;
1392
e2c719b7 1393 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1394
92f2584a
JB		 1395 val = I915_READ(PCH_DREF_CONTROL);
1396 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1397 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1398 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1399}
1400
ab9412ba
DV		 1401static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1402 enum pipe pipe)
92f2584a
JB		 1403{
1404 int reg;
1405 u32 val;
1406 bool enabled;
1407
ab9412ba 1408 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1409 val = I915_READ(reg);
1410 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1411 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1412 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1413 pipe_name(pipe));
92f2584a
JB		 1414}
1415
4e634389
KP		 1416static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1417 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1418{
1419 if ((val & DP_PORT_EN) == 0)
1420 return false;
1421
1422 if (HAS_PCH_CPT(dev_priv->dev)) {
1423 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1424 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1425 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1426 return false;
44f37d1f
CML		 1427 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1428 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1429 return false;
f0575e92
KP		 1430 } else {
1431 if ((val & DP_PIPE_MASK) != (pipe << 30))
1432 return false;
1433 }
1434 return true;
1435}
1436
1519b995
KP		 1437static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1438 enum pipe pipe, u32 val)
1439{
dc0fa718 1440 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1441 return false;
1442
1443 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1444 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1445 return false;
44f37d1f
CML		 1446 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1447 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1448 return false;
1519b995 1449 } else {
dc0fa718 1450 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1451 return false;
1452 }
1453 return true;
1454}
1455
1456static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, u32 val)
1458{
1459 if ((val & LVDS_PORT_EN) == 0)
1460 return false;
1461
1462 if (HAS_PCH_CPT(dev_priv->dev)) {
1463 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1464 return false;
1465 } else {
1466 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1467 return false;
1468 }
1469 return true;
1470}
1471
1472static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, u32 val)
1474{
1475 if ((val & ADPA_DAC_ENABLE) == 0)
1476 return false;
1477 if (HAS_PCH_CPT(dev_priv->dev)) {
1478 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1479 return false;
1480 } else {
1481 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1482 return false;
1483 }
1484 return true;
1485}
1486
291906f1 1487static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1488 enum pipe pipe, int reg, u32 port_sel)
291906f1 1489{
47a05eca 1490 u32 val = I915_READ(reg);
e2c719b7 1491 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1492 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1493 reg, pipe_name(pipe));
de9a35ab 1494
e2c719b7 1495 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1496 && (val & DP_PIPEB_SELECT),
de9a35ab 1497 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1498}
1499
1500static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1501 enum pipe pipe, int reg)
1502{
47a05eca 1503 u32 val = I915_READ(reg);
e2c719b7 1504 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1505 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1506 reg, pipe_name(pipe));
de9a35ab 1507
e2c719b7 1508 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1509 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1510 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1511}
1512
1513static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe)
1515{
1516 int reg;
1517 u32 val;
291906f1 1518
f0575e92
KP		 1519 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1520 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1521 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1522
1523 reg = PCH_ADPA;
1524 val = I915_READ(reg);
e2c719b7 1525 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1526 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1527 pipe_name(pipe));
291906f1
JB		 1528
1529 reg = PCH_LVDS;
1530 val = I915_READ(reg);
e2c719b7 1531 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1532 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1533 pipe_name(pipe));
291906f1 1534
e2debe91
PZ		 1535 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1536 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1537 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1538}
1539
d288f65f 1540static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1541 const struct intel_crtc_state *pipe_config)
87442f73 1542{
426115cf
DV		 1543 struct drm_device *dev = crtc->base.dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 int reg = DPLL(crtc->pipe);
d288f65f 1546 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1547
426115cf 1548 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1549
1550 /* No really, not for ILK+ */
1551 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1552
1553 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1554 if (IS_MOBILE(dev_priv->dev))
426115cf 1555 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1556
426115cf
DV		 1557 I915_WRITE(reg, dpll);
1558 POSTING_READ(reg);
1559 udelay(150);
1560
1561 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1562 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1563
d288f65f 1564 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1565 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1566
1567 /* We do this three times for luck */
426115cf 1568 I915_WRITE(reg, dpll);
87442f73
DV		 1569 POSTING_READ(reg);
1570 udelay(150); /* wait for warmup */
426115cf 1571 I915_WRITE(reg, dpll);
87442f73
DV		 1572 POSTING_READ(reg);
1573 udelay(150); /* wait for warmup */
426115cf 1574 I915_WRITE(reg, dpll);
87442f73
DV		 1575 POSTING_READ(reg);
1576 udelay(150); /* wait for warmup */
1577}
1578
d288f65f 1579static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1580 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1581{
1582 struct drm_device *dev = crtc->base.dev;
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 int pipe = crtc->pipe;
1585 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1586 u32 tmp;
1587
1588 assert_pipe_disabled(dev_priv, crtc->pipe);
1589
1590 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1591
a580516d 1592 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1593
1594 /* Enable back the 10bit clock to display controller */
1595 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1596 tmp |= DPIO_DCLKP_EN;
1597 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1598
54433e91
VS		 1599 mutex_unlock(&dev_priv->sb_lock);
1600
9d556c99
CML		 1601 /*
1602 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1603 */
1604 udelay(1);
1605
1606 /* Enable PLL */
d288f65f 1607 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1608
1609 /* Check PLL is locked */
a11b0703 1610 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1611 DRM_ERROR("PLL %d failed to lock\n", pipe);
1612
a11b0703 1613 /* not sure when this should be written */
d288f65f 1614 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1615 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1616}
1617
1c4e0274
VS		 1618static int intel_num_dvo_pipes(struct drm_device *dev)
1619{
1620 struct intel_crtc *crtc;
1621 int count = 0;
1622
1623 for_each_intel_crtc(dev, crtc)
3538b9df 1624 count += crtc->base.state->active &&
409ee761 1625 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1626
1627 return count;
1628}
1629
66e3d5c0 1630static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1631{
66e3d5c0
DV		 1632 struct drm_device *dev = crtc->base.dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int reg = DPLL(crtc->pipe);
6e3c9717 1635 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1636
66e3d5c0 1637 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1638
63d7bbe9 1639 /* No really, not for ILK+ */
3d13ef2e 1640 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1641
1642 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1643 if (IS_MOBILE(dev) && !IS_I830(dev))
1644 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1645
1c4e0274
VS		 1646 /* Enable DVO 2x clock on both PLLs if necessary */
1647 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1648 /*
1649 * It appears to be important that we don't enable this
1650 * for the current pipe before otherwise configuring the
1651 * PLL. No idea how this should be handled if multiple
1652 * DVO outputs are enabled simultaneosly.
1653 */
1654 dpll |= DPLL_DVO_2X_MODE;
1655 I915_WRITE(DPLL(!crtc->pipe),
1656 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1657 }
66e3d5c0
DV		 1658
1659 /* Wait for the clocks to stabilize. */
1660 POSTING_READ(reg);
1661 udelay(150);
1662
1663 if (INTEL_INFO(dev)->gen >= 4) {
1664 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1665 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1666 } else {
1667 /* The pixel multiplier can only be updated once the
1668 * DPLL is enabled and the clocks are stable.
1669 *
1670 * So write it again.
1671 */
1672 I915_WRITE(reg, dpll);
1673 }
63d7bbe9
JB		 1674
1675 /* We do this three times for luck */
66e3d5c0 1676 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1677 POSTING_READ(reg);
1678 udelay(150); /* wait for warmup */
66e3d5c0 1679 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1680 POSTING_READ(reg);
1681 udelay(150); /* wait for warmup */
66e3d5c0 1682 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1683 POSTING_READ(reg);
1684 udelay(150); /* wait for warmup */
1685}
1686
1687/**
50b44a44 1688 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe PLL to disable
1691 *
1692 * Disable the PLL for @pipe, making sure the pipe is off first.
1693 *
1694 * Note! This is for pre-ILK only.
1695 */
1c4e0274 1696static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1697{
1c4e0274
VS		 1698 struct drm_device *dev = crtc->base.dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 enum pipe pipe = crtc->pipe;
1701
1702 /* Disable DVO 2x clock on both PLLs if necessary */
1703 if (IS_I830(dev) &&
409ee761 1704 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1705 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1706 I915_WRITE(DPLL(PIPE_B),
1707 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1708 I915_WRITE(DPLL(PIPE_A),
1709 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1710 }
1711
b6b5d049
VS		 1712 /* Don't disable pipe or pipe PLLs if needed */
1713 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1714 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1715 return;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
b8afb911 1720 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1721 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1722}
1723
f6071166
JB		 1724static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1725{
b8afb911 1726 u32 val;
f6071166
JB		 1727
1728 /* Make sure the pipe isn't still relying on us */
1729 assert_pipe_disabled(dev_priv, pipe);
1730
e5cbfbfb
ID		 1731 /*
1732 * Leave integrated clock source and reference clock enabled for pipe B.
1733 * The latter is needed for VGA hotplug / manual detection.
1734 */
b8afb911 1735 val = DPLL_VGA_MODE_DIS;
f6071166 1736 if (pipe == PIPE_B)
60bfe44f 1737 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1738 I915_WRITE(DPLL(pipe), val);
1739 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1740
1741}
1742
1743static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1744{
d752048d 1745 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1746 u32 val;
1747
a11b0703
VS		 1748 /* Make sure the pipe isn't still relying on us */
1749 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1750
a11b0703 1751 /* Set PLL en = 0 */
60bfe44f
VS		 1752 val = DPLL_SSC_REF_CLK_CHV |
1753 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1754 if (pipe != PIPE_A)
1755 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1756 I915_WRITE(DPLL(pipe), val);
1757 POSTING_READ(DPLL(pipe));
d752048d 1758
a580516d 1759 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1760
1761 /* Disable 10bit clock to display controller */
1762 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1763 val &= ~DPIO_DCLKP_EN;
1764 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1765
a580516d 1766 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1767}
1768
e4607fcf 1769void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1770 struct intel_digital_port *dport,
1771 unsigned int expected_mask)
89b667f8
JB		 1772{
1773 u32 port_mask;
00fc31b7 1774 int dpll_reg;
89b667f8 1775
e4607fcf
CML		 1776 switch (dport->port) {
1777 case PORT_B:
89b667f8 1778 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1779 dpll_reg = DPLL(0);
e4607fcf
CML		 1780 break;
1781 case PORT_C:
89b667f8 1782 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1783 dpll_reg = DPLL(0);
9b6de0a1 1784 expected_mask <<= 4;
00fc31b7
CML		 1785 break;
1786 case PORT_D:
1787 port_mask = DPLL_PORTD_READY_MASK;
1788 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1789 break;
1790 default:
1791 BUG();
1792 }
89b667f8 1793
9b6de0a1
VS		 1794 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1795 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1796 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1797}
1798
b14b1055
DV		 1799static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1800{
1801 struct drm_device *dev = crtc->base.dev;
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1804
be19f0ff
CW		 1805 if (WARN_ON(pll == NULL))
1806 return;
1807
3e369b76 1808 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1809 if (pll->active == 0) {
1810 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1811 WARN_ON(pll->on);
1812 assert_shared_dpll_disabled(dev_priv, pll);
1813
1814 pll->mode_set(dev_priv, pll);
1815 }
1816}
1817
92f2584a 1818/**
85b3894f 1819 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1820 * @dev_priv: i915 private structure
1821 * @pipe: pipe PLL to enable
1822 *
1823 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1824 * drives the transcoder clock.
1825 */
85b3894f 1826static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1827{
3d13ef2e
DL		 1828 struct drm_device *dev = crtc->base.dev;
1829 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1830 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1831
87a875bb 1832 if (WARN_ON(pll == NULL))
48da64a8
CW		 1833 return;
1834
3e369b76 1835 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1836 return;
ee7b9f93 1837
74dd6928 1838 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1839 pll->name, pll->active, pll->on,
e2b78267 1840 crtc->base.base.id);
92f2584a 1841
cdbd2316
DV		 1842 if (pll->active++) {
1843 WARN_ON(!pll->on);
e9d6944e 1844 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1845 return;
1846 }
f4a091c7 1847 WARN_ON(pll->on);
ee7b9f93 1848
bd2bb1b9
PZ		 1849 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1850
46edb027 1851 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1852 pll->enable(dev_priv, pll);
ee7b9f93 1853 pll->on = true;
92f2584a
JB		 1854}
1855
f6daaec2 1856static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1857{
3d13ef2e
DL		 1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1861
92f2584a 1862 /* PCH only available on ILK+ */
80aa9312
JB		 1863 if (INTEL_INFO(dev)->gen < 5)
1864 return;
1865
eddfcbcd
ML		 1866 if (pll == NULL)
1867 return;
92f2584a 1868
eddfcbcd 1869 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1870 return;
7a419866 1871
46edb027
DV		 1872 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1873 pll->name, pll->active, pll->on,
e2b78267 1874 crtc->base.base.id);
7a419866 1875
48da64a8 1876 if (WARN_ON(pll->active == 0)) {
e9d6944e 1877 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1878 return;
1879 }
1880
e9d6944e 1881 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1882 WARN_ON(!pll->on);
cdbd2316 1883 if (--pll->active)
7a419866 1884 return;
ee7b9f93 1885
46edb027 1886 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1887 pll->disable(dev_priv, pll);
ee7b9f93 1888 pll->on = false;
bd2bb1b9
PZ		 1889
1890 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1891}
1892
b8a4f404
PZ		 1893static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1894 enum pipe pipe)
040484af 1895{
23670b32 1896 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1897 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1899 uint32_t reg, val, pipeconf_val;
040484af
JB		 1900
1901 /* PCH only available on ILK+ */
55522f37 1902 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1903
1904 /* Make sure PCH DPLL is enabled */
e72f9fbf 1905 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1906 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1907
1908 /* FDI must be feeding us bits for PCH ports */
1909 assert_fdi_tx_enabled(dev_priv, pipe);
1910 assert_fdi_rx_enabled(dev_priv, pipe);
1911
23670b32
DV		 1912 if (HAS_PCH_CPT(dev)) {
1913 /* Workaround: Set the timing override bit before enabling the
1914 * pch transcoder. */
1915 reg = TRANS_CHICKEN2(pipe);
1916 val = I915_READ(reg);
1917 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1918 I915_WRITE(reg, val);
59c859d6 1919 }
23670b32 1920
ab9412ba 1921 reg = PCH_TRANSCONF(pipe);
040484af 1922 val = I915_READ(reg);
5f7f726d 1923 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1924
1925 if (HAS_PCH_IBX(dev_priv->dev)) {
1926 /*
c5de7c6f
VS		 1927 * Make the BPC in transcoder be consistent with
1928 * that in pipeconf reg. For HDMI we must use 8bpc
1929 * here for both 8bpc and 12bpc.
e9bcff5c 1930 */
dfd07d72 1931 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1932 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1933 val |= PIPECONF_8BPC;
1934 else
1935 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1936 }
5f7f726d
PZ		 1937
1938 val &= ~TRANS_INTERLACE_MASK;
1939 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1940 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1941 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1942 val |= TRANS_LEGACY_INTERLACED_ILK;
1943 else
1944 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1945 else
1946 val |= TRANS_PROGRESSIVE;
1947
040484af
JB		 1948 I915_WRITE(reg, val | TRANS_ENABLE);
1949 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1950 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1951}
1952
8fb033d7 1953static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1954 enum transcoder cpu_transcoder)
040484af 1955{
8fb033d7 1956 u32 val, pipeconf_val;
8fb033d7
PZ		 1957
1958 /* PCH only available on ILK+ */
55522f37 1959 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 1960
8fb033d7 1961 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1962 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1963 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1964
223a6fdf
PZ		 1965 /* Workaround: set timing override bit. */
1966 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1967 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1968 I915_WRITE(_TRANSA_CHICKEN2, val);
1969
25f3ef11 1970 val = TRANS_ENABLE;
937bb610 1971 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1972
9a76b1c6
PZ		 1973 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1974 PIPECONF_INTERLACED_ILK)
a35f2679 1975 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1976 else
1977 val |= TRANS_PROGRESSIVE;
1978
ab9412ba
DV		 1979 I915_WRITE(LPT_TRANSCONF, val);
1980 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1981 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1982}
1983
b8a4f404
PZ		 1984static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1985 enum pipe pipe)
040484af 1986{
23670b32
DV		 1987 struct drm_device *dev = dev_priv->dev;
1988 uint32_t reg, val;
040484af
JB		 1989
1990 /* FDI relies on the transcoder */
1991 assert_fdi_tx_disabled(dev_priv, pipe);
1992 assert_fdi_rx_disabled(dev_priv, pipe);
1993
291906f1
JB		 1994 /* Ports must be off as well */
1995 assert_pch_ports_disabled(dev_priv, pipe);
1996
ab9412ba 1997 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1998 val = I915_READ(reg);
1999 val &= ~TRANS_ENABLE;
2000 I915_WRITE(reg, val);
2001 /* wait for PCH transcoder off, transcoder state */
2002 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2003 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2004
2005 if (!HAS_PCH_IBX(dev)) {
2006 /* Workaround: Clear the timing override chicken bit again. */
2007 reg = TRANS_CHICKEN2(pipe);
2008 val = I915_READ(reg);
2009 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2010 I915_WRITE(reg, val);
2011 }
040484af
JB		 2012}
2013
ab4d966c 2014static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2015{
8fb033d7
PZ		 2016 u32 val;
2017
ab9412ba 2018 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2019 val &= ~TRANS_ENABLE;
ab9412ba 2020 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2021 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2022 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2023 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2024
2025 /* Workaround: clear timing override bit. */
2026 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2027 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2028 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2029}
2030
b24e7179 2031/**
309cfea8 2032 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2033 * @crtc: crtc responsible for the pipe
b24e7179 2034 *
0372264a 2035 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2036 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2037 */
e1fdc473 2038static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2039{
0372264a
PZ		 2040 struct drm_device *dev = crtc->base.dev;
2041 struct drm_i915_private *dev_priv = dev->dev_private;
2042 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2043 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2044 pipe);
1a240d4d 2045 enum pipe pch_transcoder;
b24e7179
JB		 2046 int reg;
2047 u32 val;
2048
9e2ee2dd
VS		 2049 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2050
58c6eaa2 2051 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2052 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2053 assert_sprites_disabled(dev_priv, pipe);
2054
681e5811 2055 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2056 pch_transcoder = TRANSCODER_A;
2057 else
2058 pch_transcoder = pipe;
2059
b24e7179
JB		 2060 /*
2061 * A pipe without a PLL won't actually be able to drive bits from
2062 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2063 * need the check.
2064 */
50360403 2065 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2066 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2067 assert_dsi_pll_enabled(dev_priv);
2068 else
2069 assert_pll_enabled(dev_priv, pipe);
040484af 2070 else {
6e3c9717 2071 if (crtc->config->has_pch_encoder) {
040484af 2072 /* if driving the PCH, we need FDI enabled */
cc391bbb 2073 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2074 assert_fdi_tx_pll_enabled(dev_priv,
2075 (enum pipe) cpu_transcoder);
040484af
JB		 2076 }
2077 /* FIXME: assert CPU port conditions for SNB+ */
2078 }
b24e7179 2079
702e7a56 2080 reg = PIPECONF(cpu_transcoder);
b24e7179 2081 val = I915_READ(reg);
7ad25d48 2082 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2083 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2084 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2085 return;
7ad25d48 2086 }
00d70b15
CW		 2087
2088 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2089 POSTING_READ(reg);
b24e7179
JB		 2090}
2091
2092/**
309cfea8 2093 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2094 * @crtc: crtc whose pipes is to be disabled
b24e7179 2095 *
575f7ab7
VS		 2096 * Disable the pipe of @crtc, making sure that various hardware
2097 * specific requirements are met, if applicable, e.g. plane
2098 * disabled, panel fitter off, etc.
b24e7179
JB		 2099 *
2100 * Will wait until the pipe has shut down before returning.
2101 */
575f7ab7 2102static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2103{
575f7ab7 2104 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2105 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2106 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2107 int reg;
2108 u32 val;
2109
9e2ee2dd
VS		 2110 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2111
b24e7179
JB		 2112 /*
2113 * Make sure planes won't keep trying to pump pixels to us,
2114 * or we might hang the display.
2115 */
2116 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2117 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2118 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2119
702e7a56 2120 reg = PIPECONF(cpu_transcoder);
b24e7179 2121 val = I915_READ(reg);
00d70b15
CW		 2122 if ((val & PIPECONF_ENABLE) == 0)
2123 return;
2124
67adc644
VS		 2125 /*
2126 * Double wide has implications for planes
2127 * so best keep it disabled when not needed.
2128 */
6e3c9717 2129 if (crtc->config->double_wide)
67adc644
VS		 2130 val &= ~PIPECONF_DOUBLE_WIDE;
2131
2132 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2133 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2134 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2135 val &= ~PIPECONF_ENABLE;
2136
2137 I915_WRITE(reg, val);
2138 if ((val & PIPECONF_ENABLE) == 0)
2139 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2140}
2141
693db184
CW		 2142static bool need_vtd_wa(struct drm_device *dev)
2143{
2144#ifdef CONFIG_INTEL_IOMMU
2145 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2146 return true;
2147#endif
2148 return false;
2149}
2150
50470bb0 2151unsigned int
6761dd31
TU		 2152intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2153 uint64_t fb_format_modifier)
a57ce0b2 2154{
6761dd31
TU		 2155 unsigned int tile_height;
2156 uint32_t pixel_bytes;
a57ce0b2 2157
b5d0e9bf
DL		 2158 switch (fb_format_modifier) {
2159 case DRM_FORMAT_MOD_NONE:
2160 tile_height = 1;
2161 break;
2162 case I915_FORMAT_MOD_X_TILED:
2163 tile_height = IS_GEN2(dev) ? 16 : 8;
2164 break;
2165 case I915_FORMAT_MOD_Y_TILED:
2166 tile_height = 32;
2167 break;
2168 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2169 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2170 switch (pixel_bytes) {
b5d0e9bf 2171 default:
6761dd31 2172 case 1:
b5d0e9bf
DL		 2173 tile_height = 64;
2174 break;
6761dd31
TU		 2175 case 2:
2176 case 4:
b5d0e9bf
DL		 2177 tile_height = 32;
2178 break;
6761dd31 2179 case 8:
b5d0e9bf
DL		 2180 tile_height = 16;
2181 break;
6761dd31 2182 case 16:
b5d0e9bf
DL		 2183 WARN_ONCE(1,
2184 "128-bit pixels are not supported for display!");
2185 tile_height = 16;
2186 break;
2187 }
2188 break;
2189 default:
2190 MISSING_CASE(fb_format_modifier);
2191 tile_height = 1;
2192 break;
2193 }
091df6cb 2194
6761dd31
TU		 2195 return tile_height;
2196}
2197
2198unsigned int
2199intel_fb_align_height(struct drm_device *dev, unsigned int height,
2200 uint32_t pixel_format, uint64_t fb_format_modifier)
2201{
2202 return ALIGN(height, intel_tile_height(dev, pixel_format,
2203 fb_format_modifier));
a57ce0b2
JB		 2204}
2205
f64b98cd
TU		 2206static int
2207intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2208 const struct drm_plane_state *plane_state)
2209{
50470bb0 2210 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2211 unsigned int tile_height, tile_pitch;
50470bb0 2212
f64b98cd
TU		 2213 *view = i915_ggtt_view_normal;
2214
50470bb0
TU		 2215 if (!plane_state)
2216 return 0;
2217
121920fa 2218 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2219 return 0;
2220
9abc4648 2221 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2222
2223 info->height = fb->height;
2224 info->pixel_format = fb->pixel_format;
2225 info->pitch = fb->pitches[0];
2226 info->fb_modifier = fb->modifier[0];
2227
84fe03f7
TU		 2228 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2229 fb->modifier[0]);
2230 tile_pitch = PAGE_SIZE / tile_height;
2231 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2232 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2233 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2234
f64b98cd
TU		 2235 return 0;
2236}
2237
4e9a86b6
VS		 2238static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2239{
2240 if (INTEL_INFO(dev_priv)->gen >= 9)
2241 return 256 * 1024;
985b8bb4
VS		 2242 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2243 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2244 return 128 * 1024;
2245 else if (INTEL_INFO(dev_priv)->gen >= 4)
2246 return 4 * 1024;
2247 else
44c5905e 2248 return 0;
4e9a86b6
VS		 2249}
2250
127bd2ac 2251int
850c4cdc
TU		 2252intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2253 struct drm_framebuffer *fb,
82bc3b2d 2254 const struct drm_plane_state *plane_state,
91af127f
JH		 2255 struct intel_engine_cs *pipelined,
2256 struct drm_i915_gem_request **pipelined_request)
6b95a207 2257{
850c4cdc 2258 struct drm_device *dev = fb->dev;
ce453d81 2259 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2260 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2261 struct i915_ggtt_view view;
6b95a207
KH		 2262 u32 alignment;
2263 int ret;
2264
ebcdd39e
MR		 2265 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2266
7b911adc
TU		 2267 switch (fb->modifier[0]) {
2268 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2269 alignment = intel_linear_alignment(dev_priv);
6b95a207 2270 break;
7b911adc 2271 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2272 if (INTEL_INFO(dev)->gen >= 9)
2273 alignment = 256 * 1024;
2274 else {
2275 /* pin() will align the object as required by fence */
2276 alignment = 0;
2277 }
6b95a207 2278 break;
7b911adc 2279 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2280 case I915_FORMAT_MOD_Yf_TILED:
2281 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2282 "Y tiling bo slipped through, driver bug!\n"))
2283 return -EINVAL;
2284 alignment = 1 * 1024 * 1024;
2285 break;
6b95a207 2286 default:
7b911adc
TU		 2287 MISSING_CASE(fb->modifier[0]);
2288 return -EINVAL;
6b95a207
KH		 2289 }
2290
f64b98cd
TU		 2291 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2292 if (ret)
2293 return ret;
2294
693db184
CW		 2295 /* Note that the w/a also requires 64 PTE of padding following the
2296 * bo. We currently fill all unused PTE with the shadow page and so
2297 * we should always have valid PTE following the scanout preventing
2298 * the VT-d warning.
2299 */
2300 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2301 alignment = 256 * 1024;
2302
d6dd6843
PZ		 2303 /*
2304 * Global gtt pte registers are special registers which actually forward
2305 * writes to a chunk of system memory. Which means that there is no risk
2306 * that the register values disappear as soon as we call
2307 * intel_runtime_pm_put(), so it is correct to wrap only the
2308 * pin/unpin/fence and not more.
2309 */
2310 intel_runtime_pm_get(dev_priv);
2311
ce453d81 2312 dev_priv->mm.interruptible = false;
e6617330 2313 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2314 pipelined_request, &view);
48b956c5 2315 if (ret)
ce453d81 2316 goto err_interruptible;
6b95a207
KH		 2317
2318 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2319 * fence, whereas 965+ only requires a fence if using
2320 * framebuffer compression. For simplicity, we always install
2321 * a fence as the cost is not that onerous.
2322 */
06d98131 2323 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2324 if (ret == -EDEADLK) {
2325 /*
2326 * -EDEADLK means there are no free fences
2327 * no pending flips.
2328 *
2329 * This is propagated to atomic, but it uses
2330 * -EDEADLK to force a locking recovery, so
2331 * change the returned error to -EBUSY.
2332 */
2333 ret = -EBUSY;
2334 goto err_unpin;
2335 } else if (ret)
9a5a53b3 2336 goto err_unpin;
1690e1eb 2337
9a5a53b3 2338 i915_gem_object_pin_fence(obj);
6b95a207 2339
ce453d81 2340 dev_priv->mm.interruptible = true;
d6dd6843 2341 intel_runtime_pm_put(dev_priv);
6b95a207 2342 return 0;
48b956c5
CW		 2343
2344err_unpin:
f64b98cd 2345 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2346err_interruptible:
2347 dev_priv->mm.interruptible = true;
d6dd6843 2348 intel_runtime_pm_put(dev_priv);
48b956c5 2349 return ret;
6b95a207
KH		 2350}
2351
82bc3b2d
TU		 2352static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2353 const struct drm_plane_state *plane_state)
1690e1eb 2354{
82bc3b2d 2355 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2356 struct i915_ggtt_view view;
2357 int ret;
82bc3b2d 2358
ebcdd39e
MR		 2359 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2360
f64b98cd
TU		 2361 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2362 WARN_ONCE(ret, "Couldn't get view from plane state!");
2363
1690e1eb 2364 i915_gem_object_unpin_fence(obj);
f64b98cd 2365 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2366}
2367
c2c75131
DV		 2368/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2369 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2370unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2371 int *x, int *y,
bc752862
CW		 2372 unsigned int tiling_mode,
2373 unsigned int cpp,
2374 unsigned int pitch)
c2c75131 2375{
bc752862
CW		 2376 if (tiling_mode != I915_TILING_NONE) {
2377 unsigned int tile_rows, tiles;
c2c75131 2378
bc752862
CW		 2379 tile_rows = *y / 8;
2380 *y %= 8;
c2c75131 2381
bc752862
CW		 2382 tiles = *x / (512/cpp);
2383 *x %= 512/cpp;
2384
2385 return tile_rows * pitch * 8 + tiles * 4096;
2386 } else {
4e9a86b6 2387 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2388 unsigned int offset;
2389
2390 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2391 *y = (offset & alignment) / pitch;
2392 *x = ((offset & alignment) - *y * pitch) / cpp;
2393 return offset & ~alignment;
bc752862 2394 }
c2c75131
DV		 2395}
2396
b35d63fa 2397static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2398{
2399 switch (format) {
2400 case DISPPLANE_8BPP:
2401 return DRM_FORMAT_C8;
2402 case DISPPLANE_BGRX555:
2403 return DRM_FORMAT_XRGB1555;
2404 case DISPPLANE_BGRX565:
2405 return DRM_FORMAT_RGB565;
2406 default:
2407 case DISPPLANE_BGRX888:
2408 return DRM_FORMAT_XRGB8888;
2409 case DISPPLANE_RGBX888:
2410 return DRM_FORMAT_XBGR8888;
2411 case DISPPLANE_BGRX101010:
2412 return DRM_FORMAT_XRGB2101010;
2413 case DISPPLANE_RGBX101010:
2414 return DRM_FORMAT_XBGR2101010;
2415 }
2416}
2417
bc8d7dff
DL		 2418static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2419{
2420 switch (format) {
2421 case PLANE_CTL_FORMAT_RGB_565:
2422 return DRM_FORMAT_RGB565;
2423 default:
2424 case PLANE_CTL_FORMAT_XRGB_8888:
2425 if (rgb_order) {
2426 if (alpha)
2427 return DRM_FORMAT_ABGR8888;
2428 else
2429 return DRM_FORMAT_XBGR8888;
2430 } else {
2431 if (alpha)
2432 return DRM_FORMAT_ARGB8888;
2433 else
2434 return DRM_FORMAT_XRGB8888;
2435 }
2436 case PLANE_CTL_FORMAT_XRGB_2101010:
2437 if (rgb_order)
2438 return DRM_FORMAT_XBGR2101010;
2439 else
2440 return DRM_FORMAT_XRGB2101010;
2441 }
2442}
2443
5724dbd1 2444static bool
f6936e29
DV		 2445intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2446 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2447{
2448 struct drm_device *dev = crtc->base.dev;
2449 struct drm_i915_gem_object *obj = NULL;
2450 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2451 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2452 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2453 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2454 PAGE_SIZE);
2455
2456 size_aligned -= base_aligned;
46f297fb 2457
ff2652ea
CW		 2458 if (plane_config->size == 0)
2459 return false;
2460
f37b5c2b
DV		 2461 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2462 base_aligned,
2463 base_aligned,
2464 size_aligned);
46f297fb 2465 if (!obj)
484b41dd 2466 return false;
46f297fb 2467
49af449b
DL		 2468 obj->tiling_mode = plane_config->tiling;
2469 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2470 obj->stride = fb->pitches[0];
46f297fb 2471
6bf129df
DL		 2472 mode_cmd.pixel_format = fb->pixel_format;
2473 mode_cmd.width = fb->width;
2474 mode_cmd.height = fb->height;
2475 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2476 mode_cmd.modifier[0] = fb->modifier[0];
2477 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2478
2479 mutex_lock(&dev->struct_mutex);
6bf129df 2480 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2481 &mode_cmd, obj)) {
46f297fb
JB		 2482 DRM_DEBUG_KMS("intel fb init failed\n");
2483 goto out_unref_obj;
2484 }
46f297fb 2485 mutex_unlock(&dev->struct_mutex);
484b41dd 2486
f6936e29 2487 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2488 return true;
46f297fb
JB		 2489
2490out_unref_obj:
2491 drm_gem_object_unreference(&obj->base);
2492 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2493 return false;
2494}
2495
afd65eb4
MR		 2496/* Update plane->state->fb to match plane->fb after driver-internal updates */
2497static void
2498update_state_fb(struct drm_plane *plane)
2499{
2500 if (plane->fb == plane->state->fb)
2501 return;
2502
2503 if (plane->state->fb)
2504 drm_framebuffer_unreference(plane->state->fb);
2505 plane->state->fb = plane->fb;
2506 if (plane->state->fb)
2507 drm_framebuffer_reference(plane->state->fb);
2508}
2509
5724dbd1 2510static void
f6936e29
DV		 2511intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2512 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2513{
2514 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2515 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2516 struct drm_crtc *c;
2517 struct intel_crtc *i;
2ff8fde1 2518 struct drm_i915_gem_object *obj;
88595ac9 2519 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2520 struct drm_plane_state *plane_state = primary->state;
88595ac9 2521 struct drm_framebuffer *fb;
484b41dd 2522
2d14030b 2523 if (!plane_config->fb)
484b41dd
JB		 2524 return;
2525
f6936e29 2526 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2527 fb = &plane_config->fb->base;
2528 goto valid_fb;
f55548b5 2529 }
484b41dd 2530
2d14030b 2531 kfree(plane_config->fb);
484b41dd
JB		 2532
2533 /*
2534 * Failed to alloc the obj, check to see if we should share
2535 * an fb with another CRTC instead
2536 */
70e1e0ec 2537 for_each_crtc(dev, c) {
484b41dd
JB		 2538 i = to_intel_crtc(c);
2539
2540 if (c == &intel_crtc->base)
2541 continue;
2542
2ff8fde1
MR		 2543 if (!i->active)
2544 continue;
2545
88595ac9
DV		 2546 fb = c->primary->fb;
2547 if (!fb)
484b41dd
JB		 2548 continue;
2549
88595ac9 2550 obj = intel_fb_obj(fb);
2ff8fde1 2551 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2552 drm_framebuffer_reference(fb);
2553 goto valid_fb;
484b41dd
JB		 2554 }
2555 }
88595ac9
DV		 2556
2557 return;
2558
2559valid_fb:
be5651f2
ML		 2560 plane_state->src_x = plane_state->src_y = 0;
2561 plane_state->src_w = fb->width << 16;
2562 plane_state->src_h = fb->height << 16;
2563
2564 plane_state->crtc_x = plane_state->src_y = 0;
2565 plane_state->crtc_w = fb->width;
2566 plane_state->crtc_h = fb->height;
2567
88595ac9
DV		 2568 obj = intel_fb_obj(fb);
2569 if (obj->tiling_mode != I915_TILING_NONE)
2570 dev_priv->preserve_bios_swizzle = true;
2571
be5651f2
ML		 2572 drm_framebuffer_reference(fb);
2573 primary->fb = primary->state->fb = fb;
36750f28 2574 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2575 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2576 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2577}
2578
29b9bde6
DV		 2579static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2580 struct drm_framebuffer *fb,
2581 int x, int y)
81255565
JB		 2582{
2583 struct drm_device *dev = crtc->dev;
2584 struct drm_i915_private *dev_priv = dev->dev_private;
2585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2586 struct drm_plane *primary = crtc->primary;
2587 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2588 struct drm_i915_gem_object *obj;
81255565 2589 int plane = intel_crtc->plane;
e506a0c6 2590 unsigned long linear_offset;
81255565 2591 u32 dspcntr;
f45651ba 2592 u32 reg = DSPCNTR(plane);
48404c1e 2593 int pixel_size;
f45651ba 2594
b70709a6 2595 if (!visible || !fb) {
fdd508a6
VS		 2596 I915_WRITE(reg, 0);
2597 if (INTEL_INFO(dev)->gen >= 4)
2598 I915_WRITE(DSPSURF(plane), 0);
2599 else
2600 I915_WRITE(DSPADDR(plane), 0);
2601 POSTING_READ(reg);
2602 return;
2603 }
2604
c9ba6fad
VS		 2605 obj = intel_fb_obj(fb);
2606 if (WARN_ON(obj == NULL))
2607 return;
2608
2609 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2610
f45651ba
VS		 2611 dspcntr = DISPPLANE_GAMMA_ENABLE;
2612
fdd508a6 2613 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2614
2615 if (INTEL_INFO(dev)->gen < 4) {
2616 if (intel_crtc->pipe == PIPE_B)
2617 dspcntr |= DISPPLANE_SEL_PIPE_B;
2618
2619 /* pipesrc and dspsize control the size that is scaled from,
2620 * which should always be the user's requested size.
2621 */
2622 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2623 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2624 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2625 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2626 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2627 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2628 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2629 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2630 I915_WRITE(PRIMPOS(plane), 0);
2631 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2632 }
81255565 2633
57779d06
VS		 2634 switch (fb->pixel_format) {
2635 case DRM_FORMAT_C8:
81255565
JB		 2636 dspcntr |= DISPPLANE_8BPP;
2637 break;
57779d06 2638 case DRM_FORMAT_XRGB1555:
57779d06 2639 dspcntr |= DISPPLANE_BGRX555;
81255565 2640 break;
57779d06
VS		 2641 case DRM_FORMAT_RGB565:
2642 dspcntr |= DISPPLANE_BGRX565;
2643 break;
2644 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2645 dspcntr |= DISPPLANE_BGRX888;
2646 break;
2647 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2648 dspcntr |= DISPPLANE_RGBX888;
2649 break;
2650 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2651 dspcntr |= DISPPLANE_BGRX101010;
2652 break;
2653 case DRM_FORMAT_XBGR2101010:
57779d06 2654 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2655 break;
2656 default:
baba133a 2657 BUG();
81255565 2658 }
57779d06 2659
f45651ba
VS		 2660 if (INTEL_INFO(dev)->gen >= 4 &&
2661 obj->tiling_mode != I915_TILING_NONE)
2662 dspcntr |= DISPPLANE_TILED;
81255565 2663
de1aa629
VS		 2664 if (IS_G4X(dev))
2665 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2666
b9897127 2667 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2668
c2c75131
DV		 2669 if (INTEL_INFO(dev)->gen >= 4) {
2670 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2671 intel_gen4_compute_page_offset(dev_priv,
2672 &x, &y, obj->tiling_mode,
b9897127 2673 pixel_size,
bc752862 2674 fb->pitches[0]);
c2c75131
DV		 2675 linear_offset -= intel_crtc->dspaddr_offset;
2676 } else {
e506a0c6 2677 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2678 }
e506a0c6 2679
8e7d688b 2680 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2681 dspcntr |= DISPPLANE_ROTATE_180;
2682
6e3c9717
ACO		 2683 x += (intel_crtc->config->pipe_src_w - 1);
2684 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2685
2686 /* Finding the last pixel of the last line of the display
2687 data and adding to linear_offset*/
2688 linear_offset +=
6e3c9717
ACO		 2689 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2690 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2691 }
2692
2693 I915_WRITE(reg, dspcntr);
2694
01f2c773 2695 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2696 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2697 I915_WRITE(DSPSURF(plane),
2698 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2699 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2700 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2701 } else
f343c5f6 2702 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2703 POSTING_READ(reg);
17638cd6
JB		 2704}
2705
29b9bde6
DV		 2706static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2707 struct drm_framebuffer *fb,
2708 int x, int y)
17638cd6
JB		 2709{
2710 struct drm_device *dev = crtc->dev;
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2713 struct drm_plane *primary = crtc->primary;
2714 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2715 struct drm_i915_gem_object *obj;
17638cd6 2716 int plane = intel_crtc->plane;
e506a0c6 2717 unsigned long linear_offset;
17638cd6 2718 u32 dspcntr;
f45651ba 2719 u32 reg = DSPCNTR(plane);
48404c1e 2720 int pixel_size;
f45651ba 2721
b70709a6 2722 if (!visible || !fb) {
fdd508a6
VS		 2723 I915_WRITE(reg, 0);
2724 I915_WRITE(DSPSURF(plane), 0);
2725 POSTING_READ(reg);
2726 return;
2727 }
2728
c9ba6fad
VS		 2729 obj = intel_fb_obj(fb);
2730 if (WARN_ON(obj == NULL))
2731 return;
2732
2733 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2734
f45651ba
VS		 2735 dspcntr = DISPPLANE_GAMMA_ENABLE;
2736
fdd508a6 2737 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2738
2739 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2740 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2741
57779d06
VS		 2742 switch (fb->pixel_format) {
2743 case DRM_FORMAT_C8:
17638cd6
JB		 2744 dspcntr |= DISPPLANE_8BPP;
2745 break;
57779d06
VS		 2746 case DRM_FORMAT_RGB565:
2747 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2748 break;
57779d06 2749 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2750 dspcntr |= DISPPLANE_BGRX888;
2751 break;
2752 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2753 dspcntr |= DISPPLANE_RGBX888;
2754 break;
2755 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2756 dspcntr |= DISPPLANE_BGRX101010;
2757 break;
2758 case DRM_FORMAT_XBGR2101010:
57779d06 2759 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2760 break;
2761 default:
baba133a 2762 BUG();
17638cd6
JB		 2763 }
2764
2765 if (obj->tiling_mode != I915_TILING_NONE)
2766 dspcntr |= DISPPLANE_TILED;
17638cd6 2767
f45651ba 2768 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2769 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2770
b9897127 2771 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2772 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2773 intel_gen4_compute_page_offset(dev_priv,
2774 &x, &y, obj->tiling_mode,
b9897127 2775 pixel_size,
bc752862 2776 fb->pitches[0]);
c2c75131 2777 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2778 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2779 dspcntr |= DISPPLANE_ROTATE_180;
2780
2781 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2782 x += (intel_crtc->config->pipe_src_w - 1);
2783 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2784
2785 /* Finding the last pixel of the last line of the display
2786 data and adding to linear_offset*/
2787 linear_offset +=
6e3c9717
ACO		 2788 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2789 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2790 }
2791 }
2792
2793 I915_WRITE(reg, dspcntr);
17638cd6 2794
01f2c773 2795 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2796 I915_WRITE(DSPSURF(plane),
2797 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2798 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2799 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2800 } else {
2801 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2802 I915_WRITE(DSPLINOFF(plane), linear_offset);
2803 }
17638cd6 2804 POSTING_READ(reg);
17638cd6
JB		 2805}
2806
b321803d
DL		 2807u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2808 uint32_t pixel_format)
2809{
2810 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2811
2812 /*
2813 * The stride is either expressed as a multiple of 64 bytes
2814 * chunks for linear buffers or in number of tiles for tiled
2815 * buffers.
2816 */
2817 switch (fb_modifier) {
2818 case DRM_FORMAT_MOD_NONE:
2819 return 64;
2820 case I915_FORMAT_MOD_X_TILED:
2821 if (INTEL_INFO(dev)->gen == 2)
2822 return 128;
2823 return 512;
2824 case I915_FORMAT_MOD_Y_TILED:
2825 /* No need to check for old gens and Y tiling since this is
2826 * about the display engine and those will be blocked before
2827 * we get here.
2828 */
2829 return 128;
2830 case I915_FORMAT_MOD_Yf_TILED:
2831 if (bits_per_pixel == 8)
2832 return 64;
2833 else
2834 return 128;
2835 default:
2836 MISSING_CASE(fb_modifier);
2837 return 64;
2838 }
2839}
2840
121920fa
TU		 2841unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2842 struct drm_i915_gem_object *obj)
2843{
9abc4648 2844 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2845
2846 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2847 view = &i915_ggtt_view_rotated;
121920fa
TU		 2848
2849 return i915_gem_obj_ggtt_offset_view(obj, view);
2850}
2851
e435d6e5
ML		 2852static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2853{
2854 struct drm_device *dev = intel_crtc->base.dev;
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856
2857 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2858 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2859 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2860}
2861
a1b2278e
CK		 2862/*
2863 * This function detaches (aka. unbinds) unused scalers in hardware
2864 */
0583236e 2865static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2866{
a1b2278e
CK		 2867 struct intel_crtc_scaler_state *scaler_state;
2868 int i;
2869
a1b2278e
CK		 2870 scaler_state = &intel_crtc->config->scaler_state;
2871
2872 /* loop through and disable scalers that aren't in use */
2873 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2874 if (!scaler_state->scalers[i].in_use)
2875 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2876 }
2877}
2878
6156a456 2879u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2880{
6156a456 2881 switch (pixel_format) {
d161cf7a 2882 case DRM_FORMAT_C8:
c34ce3d1 2883 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2884 case DRM_FORMAT_RGB565:
c34ce3d1 2885 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2886 case DRM_FORMAT_XBGR8888:
c34ce3d1 2887 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2888 case DRM_FORMAT_XRGB8888:
c34ce3d1 2889 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2890 /*
2891 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2892 * to be already pre-multiplied. We need to add a knob (or a different
2893 * DRM_FORMAT) for user-space to configure that.
2894 */
f75fb42a 2895 case DRM_FORMAT_ABGR8888:
c34ce3d1 2896 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2897 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2898 case DRM_FORMAT_ARGB8888:
c34ce3d1 2899 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2900 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2901 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2902 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2903 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2904 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2905 case DRM_FORMAT_YUYV:
c34ce3d1 2906 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2907 case DRM_FORMAT_YVYU:
c34ce3d1 2908 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2909 case DRM_FORMAT_UYVY:
c34ce3d1 2910 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2911 case DRM_FORMAT_VYUY:
c34ce3d1 2912 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2913 default:
4249eeef 2914 MISSING_CASE(pixel_format);
70d21f0e 2915 }
8cfcba41 2916
c34ce3d1 2917 return 0;
6156a456 2918}
70d21f0e 2919
6156a456
CK		 2920u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2921{
6156a456 2922 switch (fb_modifier) {
30af77c4 2923 case DRM_FORMAT_MOD_NONE:
70d21f0e 2924 break;
30af77c4 2925 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2926 return PLANE_CTL_TILED_X;
b321803d 2927 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2928 return PLANE_CTL_TILED_Y;
b321803d 2929 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2930 return PLANE_CTL_TILED_YF;
70d21f0e 2931 default:
6156a456 2932 MISSING_CASE(fb_modifier);
70d21f0e 2933 }
8cfcba41 2934
c34ce3d1 2935 return 0;
6156a456 2936}
70d21f0e 2937
6156a456
CK		 2938u32 skl_plane_ctl_rotation(unsigned int rotation)
2939{
3b7a5119 2940 switch (rotation) {
6156a456
CK		 2941 case BIT(DRM_ROTATE_0):
2942 break;
1e8df167
SJ		 2943 /*
2944 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2945 * while i915 HW rotation is clockwise, thats why this swapping.
2946 */
3b7a5119 2947 case BIT(DRM_ROTATE_90):
1e8df167 2948 return PLANE_CTL_ROTATE_270;
3b7a5119 2949 case BIT(DRM_ROTATE_180):
c34ce3d1 2950 return PLANE_CTL_ROTATE_180;
3b7a5119 2951 case BIT(DRM_ROTATE_270):
1e8df167 2952 return PLANE_CTL_ROTATE_90;
6156a456
CK		 2953 default:
2954 MISSING_CASE(rotation);
2955 }
2956
c34ce3d1 2957 return 0;
6156a456
CK		 2958}
2959
2960static void skylake_update_primary_plane(struct drm_crtc *crtc,
2961 struct drm_framebuffer *fb,
2962 int x, int y)
2963{
2964 struct drm_device *dev = crtc->dev;
2965 struct drm_i915_private *dev_priv = dev->dev_private;
2966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2967 struct drm_plane *plane = crtc->primary;
2968 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 2969 struct drm_i915_gem_object *obj;
2970 int pipe = intel_crtc->pipe;
2971 u32 plane_ctl, stride_div, stride;
2972 u32 tile_height, plane_offset, plane_size;
2973 unsigned int rotation;
2974 int x_offset, y_offset;
2975 unsigned long surf_addr;
6156a456
CK		 2976 struct intel_crtc_state *crtc_state = intel_crtc->config;
2977 struct intel_plane_state *plane_state;
2978 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
2979 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
2980 int scaler_id = -1;
2981
6156a456
CK		 2982 plane_state = to_intel_plane_state(plane->state);
2983
b70709a6 2984 if (!visible || !fb) {
6156a456
CK		 2985 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2986 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2987 POSTING_READ(PLANE_CTL(pipe, 0));
2988 return;
3b7a5119 2989 }
70d21f0e 2990
6156a456
CK		 2991 plane_ctl = PLANE_CTL_ENABLE |
2992 PLANE_CTL_PIPE_GAMMA_ENABLE |
2993 PLANE_CTL_PIPE_CSC_ENABLE;
2994
2995 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
2996 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
2997 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2998
2999 rotation = plane->state->rotation;
3000 plane_ctl |= skl_plane_ctl_rotation(rotation);
3001
b321803d
DL		 3002 obj = intel_fb_obj(fb);
3003 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3004 fb->pixel_format);
3b7a5119
SJ		 3005 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3006
6156a456
CK		 3007 /*
3008 * FIXME: intel_plane_state->src, dst aren't set when transitional
3009 * update_plane helpers are called from legacy paths.
3010 * Once full atomic crtc is available, below check can be avoided.
3011 */
3012 if (drm_rect_width(&plane_state->src)) {
3013 scaler_id = plane_state->scaler_id;
3014 src_x = plane_state->src.x1 >> 16;
3015 src_y = plane_state->src.y1 >> 16;
3016 src_w = drm_rect_width(&plane_state->src) >> 16;
3017 src_h = drm_rect_height(&plane_state->src) >> 16;
3018 dst_x = plane_state->dst.x1;
3019 dst_y = plane_state->dst.y1;
3020 dst_w = drm_rect_width(&plane_state->dst);
3021 dst_h = drm_rect_height(&plane_state->dst);
3022
3023 WARN_ON(x != src_x || y != src_y);
3024 } else {
3025 src_w = intel_crtc->config->pipe_src_w;
3026 src_h = intel_crtc->config->pipe_src_h;
3027 }
3028
3b7a5119
SJ		 3029 if (intel_rotation_90_or_270(rotation)) {
3030 /* stride = Surface height in tiles */
2614f17d 3031 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3032 fb->modifier[0]);
3033 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3034 x_offset = stride * tile_height - y - src_h;
3b7a5119 3035 y_offset = x;
6156a456 3036 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3037 } else {
3038 stride = fb->pitches[0] / stride_div;
3039 x_offset = x;
3040 y_offset = y;
6156a456 3041 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3042 }
3043 plane_offset = y_offset << 16 | x_offset;
b321803d 3044
70d21f0e 3045 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3046 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3047 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3048 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3049
3050 if (scaler_id >= 0) {
3051 uint32_t ps_ctrl = 0;
3052
3053 WARN_ON(!dst_w || !dst_h);
3054 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3055 crtc_state->scaler_state.scalers[scaler_id].mode;
3056 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3057 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3058 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3059 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3060 I915_WRITE(PLANE_POS(pipe, 0), 0);
3061 } else {
3062 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3063 }
3064
121920fa 3065 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3066
3067 POSTING_READ(PLANE_SURF(pipe, 0));
3068}
3069
17638cd6
JB		 3070/* Assume fb object is pinned & idle & fenced and just update base pointers */
3071static int
3072intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3073 int x, int y, enum mode_set_atomic state)
3074{
3075 struct drm_device *dev = crtc->dev;
3076 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3077
ff2a3117 3078 if (dev_priv->fbc.disable_fbc)
7733b49b 3079 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3080
29b9bde6
DV		 3081 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3082
3083 return 0;
81255565
JB		 3084}
3085
7514747d 3086static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3087{
96a02917
VS		 3088 struct drm_crtc *crtc;
3089
70e1e0ec 3090 for_each_crtc(dev, crtc) {
96a02917
VS		 3091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3092 enum plane plane = intel_crtc->plane;
3093
3094 intel_prepare_page_flip(dev, plane);
3095 intel_finish_page_flip_plane(dev, plane);
3096 }
7514747d
VS		 3097}
3098
3099static void intel_update_primary_planes(struct drm_device *dev)
3100{
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 struct drm_crtc *crtc;
96a02917 3103
70e1e0ec 3104 for_each_crtc(dev, crtc) {
96a02917
VS		 3105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3106
51fd371b 3107 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3108 /*
3109 * FIXME: Once we have proper support for primary planes (and
3110 * disabling them without disabling the entire crtc) allow again
66e514c1 3111 * a NULL crtc->primary->fb.
947fdaad 3112 */
f4510a27 3113 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3114 dev_priv->display.update_primary_plane(crtc,
66e514c1 3115 crtc->primary->fb,
262ca2b0
MR		 3116 crtc->x,
3117 crtc->y);
51fd371b 3118 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3119 }
3120}
3121
7514747d
VS		 3122void intel_prepare_reset(struct drm_device *dev)
3123{
3124 /* no reset support for gen2 */
3125 if (IS_GEN2(dev))
3126 return;
3127
3128 /* reset doesn't touch the display */
3129 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3130 return;
3131
3132 drm_modeset_lock_all(dev);
f98ce92f
VS		 3133 /*
3134 * Disabling the crtcs gracefully seems nicer. Also the
3135 * g33 docs say we should at least disable all the planes.
3136 */
6b72d486 3137 intel_display_suspend(dev);
7514747d
VS		 3138}
3139
3140void intel_finish_reset(struct drm_device *dev)
3141{
3142 struct drm_i915_private *dev_priv = to_i915(dev);
3143
3144 /*
3145 * Flips in the rings will be nuked by the reset,
3146 * so complete all pending flips so that user space
3147 * will get its events and not get stuck.
3148 */
3149 intel_complete_page_flips(dev);
3150
3151 /* no reset support for gen2 */
3152 if (IS_GEN2(dev))
3153 return;
3154
3155 /* reset doesn't touch the display */
3156 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3157 /*
3158 * Flips in the rings have been nuked by the reset,
3159 * so update the base address of all primary
3160 * planes to the the last fb to make sure we're
3161 * showing the correct fb after a reset.
3162 */
3163 intel_update_primary_planes(dev);
3164 return;
3165 }
3166
3167 /*
3168 * The display has been reset as well,
3169 * so need a full re-initialization.
3170 */
3171 intel_runtime_pm_disable_interrupts(dev_priv);
3172 intel_runtime_pm_enable_interrupts(dev_priv);
3173
3174 intel_modeset_init_hw(dev);
3175
3176 spin_lock_irq(&dev_priv->irq_lock);
3177 if (dev_priv->display.hpd_irq_setup)
3178 dev_priv->display.hpd_irq_setup(dev);
3179 spin_unlock_irq(&dev_priv->irq_lock);
3180
043e9bda 3181 intel_display_resume(dev);
7514747d
VS		 3182
3183 intel_hpd_init(dev_priv);
3184
3185 drm_modeset_unlock_all(dev);
3186}
3187
2e2f351d 3188static void
14667a4b
CW		 3189intel_finish_fb(struct drm_framebuffer *old_fb)
3190{
2ff8fde1 3191 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3192 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3193 bool was_interruptible = dev_priv->mm.interruptible;
3194 int ret;
3195
14667a4b
CW		 3196 /* Big Hammer, we also need to ensure that any pending
3197 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3198 * current scanout is retired before unpinning the old
2e2f351d
CW		 3199 * framebuffer. Note that we rely on userspace rendering
3200 * into the buffer attached to the pipe they are waiting
3201 * on. If not, userspace generates a GPU hang with IPEHR
3202 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3203 *
3204 * This should only fail upon a hung GPU, in which case we
3205 * can safely continue.
3206 */
3207 dev_priv->mm.interruptible = false;
2e2f351d 3208 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3209 dev_priv->mm.interruptible = was_interruptible;
3210
2e2f351d 3211 WARN_ON(ret);
14667a4b
CW		 3212}
3213
7d5e3799
CW		 3214static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3215{
3216 struct drm_device *dev = crtc->dev;
3217 struct drm_i915_private *dev_priv = dev->dev_private;
3218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3219 bool pending;
3220
3221 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3222 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3223 return false;
3224
5e2d7afc 3225 spin_lock_irq(&dev->event_lock);
7d5e3799 3226 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3227 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3228
3229 return pending;
3230}
3231
e30e8f75
GP		 3232static void intel_update_pipe_size(struct intel_crtc *crtc)
3233{
3234 struct drm_device *dev = crtc->base.dev;
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3236 const struct drm_display_mode *adjusted_mode;
3237
3238 if (!i915.fastboot)
3239 return;
3240
3241 /*
3242 * Update pipe size and adjust fitter if needed: the reason for this is
3243 * that in compute_mode_changes we check the native mode (not the pfit
3244 * mode) to see if we can flip rather than do a full mode set. In the
3245 * fastboot case, we'll flip, but if we don't update the pipesrc and
3246 * pfit state, we'll end up with a big fb scanned out into the wrong
3247 * sized surface.
3248 *
3249 * To fix this properly, we need to hoist the checks up into
3250 * compute_mode_changes (or above), check the actual pfit state and
3251 * whether the platform allows pfit disable with pipe active, and only
3252 * then update the pipesrc and pfit state, even on the flip path.
3253 */
3254
6e3c9717 3255 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3256
3257 I915_WRITE(PIPESRC(crtc->pipe),
3258 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3259 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3260 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3261 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3262 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3263 I915_WRITE(PF_CTL(crtc->pipe), 0);
3264 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3265 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3266 }
6e3c9717
ACO		 3267 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3268 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3269}
3270
5e84e1a4
ZW		 3271static void intel_fdi_normal_train(struct drm_crtc *crtc)
3272{
3273 struct drm_device *dev = crtc->dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3276 int pipe = intel_crtc->pipe;
3277 u32 reg, temp;
3278
3279 /* enable normal train */
3280 reg = FDI_TX_CTL(pipe);
3281 temp = I915_READ(reg);
61e499bf 3282 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3283 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3284 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3285 } else {
3286 temp &= ~FDI_LINK_TRAIN_NONE;
3287 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3288 }
5e84e1a4
ZW		 3289 I915_WRITE(reg, temp);
3290
3291 reg = FDI_RX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 if (HAS_PCH_CPT(dev)) {
3294 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3295 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3296 } else {
3297 temp &= ~FDI_LINK_TRAIN_NONE;
3298 temp |= FDI_LINK_TRAIN_NONE;
3299 }
3300 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3301
3302 /* wait one idle pattern time */
3303 POSTING_READ(reg);
3304 udelay(1000);
357555c0
JB		 3305
3306 /* IVB wants error correction enabled */
3307 if (IS_IVYBRIDGE(dev))
3308 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3309 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3310}
3311
8db9d77b
ZW		 3312/* The FDI link training functions for ILK/Ibexpeak. */
3313static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3314{
3315 struct drm_device *dev = crtc->dev;
3316 struct drm_i915_private *dev_priv = dev->dev_private;
3317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3318 int pipe = intel_crtc->pipe;
5eddb70b 3319 u32 reg, temp, tries;
8db9d77b 3320
1c8562f6 3321 /* FDI needs bits from pipe first */
0fc932b8 3322 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3323
e1a44743
AJ		 3324 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3325 for train result */
5eddb70b
CW		 3326 reg = FDI_RX_IMR(pipe);
3327 temp = I915_READ(reg);
e1a44743
AJ		 3328 temp &= ~FDI_RX_SYMBOL_LOCK;
3329 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3330 I915_WRITE(reg, temp);
3331 I915_READ(reg);
e1a44743
AJ		 3332 udelay(150);
3333
8db9d77b 3334 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3335 reg = FDI_TX_CTL(pipe);
3336 temp = I915_READ(reg);
627eb5a3 3337 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3338 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3339 temp &= ~FDI_LINK_TRAIN_NONE;
3340 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3341 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3342
5eddb70b
CW		 3343 reg = FDI_RX_CTL(pipe);
3344 temp = I915_READ(reg);
8db9d77b
ZW		 3345 temp &= ~FDI_LINK_TRAIN_NONE;
3346 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3347 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3348
3349 POSTING_READ(reg);
8db9d77b
ZW		 3350 udelay(150);
3351
5b2adf89 3352 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3353 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3354 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3355 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3356
5eddb70b 3357 reg = FDI_RX_IIR(pipe);
e1a44743 3358 for (tries = 0; tries < 5; tries++) {
5eddb70b 3359 temp = I915_READ(reg);
8db9d77b
ZW		 3360 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3361
3362 if ((temp & FDI_RX_BIT_LOCK)) {
3363 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3364 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3365 break;
3366 }
8db9d77b 3367 }
e1a44743 3368 if (tries == 5)
5eddb70b 3369 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3370
3371 /* Train 2 */
5eddb70b
CW		 3372 reg = FDI_TX_CTL(pipe);
3373 temp = I915_READ(reg);
8db9d77b
ZW		 3374 temp &= ~FDI_LINK_TRAIN_NONE;
3375 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3376 I915_WRITE(reg, temp);
8db9d77b 3377
5eddb70b
CW		 3378 reg = FDI_RX_CTL(pipe);
3379 temp = I915_READ(reg);
8db9d77b
ZW		 3380 temp &= ~FDI_LINK_TRAIN_NONE;
3381 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3382 I915_WRITE(reg, temp);
8db9d77b 3383
5eddb70b
CW		 3384 POSTING_READ(reg);
3385 udelay(150);
8db9d77b 3386
5eddb70b 3387 reg = FDI_RX_IIR(pipe);
e1a44743 3388 for (tries = 0; tries < 5; tries++) {
5eddb70b 3389 temp = I915_READ(reg);
8db9d77b
ZW		 3390 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3391
3392 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3393 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3394 DRM_DEBUG_KMS("FDI train 2 done.\n");
3395 break;
3396 }
8db9d77b 3397 }
e1a44743 3398 if (tries == 5)
5eddb70b 3399 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3400
3401 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3402
8db9d77b
ZW		 3403}
3404
0206e353 3405static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3406 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3407 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3408 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3409 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3410};
3411
3412/* The FDI link training functions for SNB/Cougarpoint. */
3413static void gen6_fdi_link_train(struct drm_crtc *crtc)
3414{
3415 struct drm_device *dev = crtc->dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3418 int pipe = intel_crtc->pipe;
fa37d39e 3419 u32 reg, temp, i, retry;
8db9d77b 3420
e1a44743
AJ		 3421 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3422 for train result */
5eddb70b
CW		 3423 reg = FDI_RX_IMR(pipe);
3424 temp = I915_READ(reg);
e1a44743
AJ		 3425 temp &= ~FDI_RX_SYMBOL_LOCK;
3426 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3427 I915_WRITE(reg, temp);
3428
3429 POSTING_READ(reg);
e1a44743
AJ		 3430 udelay(150);
3431
8db9d77b 3432 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3433 reg = FDI_TX_CTL(pipe);
3434 temp = I915_READ(reg);
627eb5a3 3435 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3436 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3437 temp &= ~FDI_LINK_TRAIN_NONE;
3438 temp |= FDI_LINK_TRAIN_PATTERN_1;
3439 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3440 /* SNB-B */
3441 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3442 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3443
d74cf324
DV		 3444 I915_WRITE(FDI_RX_MISC(pipe),
3445 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3446
5eddb70b
CW		 3447 reg = FDI_RX_CTL(pipe);
3448 temp = I915_READ(reg);
8db9d77b
ZW		 3449 if (HAS_PCH_CPT(dev)) {
3450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3451 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3452 } else {
3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_1;
3455 }
5eddb70b
CW		 3456 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3457
3458 POSTING_READ(reg);
8db9d77b
ZW		 3459 udelay(150);
3460
0206e353 3461 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3462 reg = FDI_TX_CTL(pipe);
3463 temp = I915_READ(reg);
8db9d77b
ZW		 3464 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3465 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3466 I915_WRITE(reg, temp);
3467
3468 POSTING_READ(reg);
8db9d77b
ZW		 3469 udelay(500);
3470
fa37d39e
SP		 3471 for (retry = 0; retry < 5; retry++) {
3472 reg = FDI_RX_IIR(pipe);
3473 temp = I915_READ(reg);
3474 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3475 if (temp & FDI_RX_BIT_LOCK) {
3476 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3477 DRM_DEBUG_KMS("FDI train 1 done.\n");
3478 break;
3479 }
3480 udelay(50);
8db9d77b 3481 }
fa37d39e
SP		 3482 if (retry < 5)
3483 break;
8db9d77b
ZW		 3484 }
3485 if (i == 4)
5eddb70b 3486 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3487
3488 /* Train 2 */
5eddb70b
CW		 3489 reg = FDI_TX_CTL(pipe);
3490 temp = I915_READ(reg);
8db9d77b
ZW		 3491 temp &= ~FDI_LINK_TRAIN_NONE;
3492 temp |= FDI_LINK_TRAIN_PATTERN_2;
3493 if (IS_GEN6(dev)) {
3494 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3495 /* SNB-B */
3496 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3497 }
5eddb70b 3498 I915_WRITE(reg, temp);
8db9d77b 3499
5eddb70b
CW		 3500 reg = FDI_RX_CTL(pipe);
3501 temp = I915_READ(reg);
8db9d77b
ZW		 3502 if (HAS_PCH_CPT(dev)) {
3503 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3504 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3505 } else {
3506 temp &= ~FDI_LINK_TRAIN_NONE;
3507 temp |= FDI_LINK_TRAIN_PATTERN_2;
3508 }
5eddb70b
CW		 3509 I915_WRITE(reg, temp);
3510
3511 POSTING_READ(reg);
8db9d77b
ZW		 3512 udelay(150);
3513
0206e353 3514 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3515 reg = FDI_TX_CTL(pipe);
3516 temp = I915_READ(reg);
8db9d77b
ZW		 3517 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3518 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3519 I915_WRITE(reg, temp);
3520
3521 POSTING_READ(reg);
8db9d77b
ZW		 3522 udelay(500);
3523
fa37d39e
SP		 3524 for (retry = 0; retry < 5; retry++) {
3525 reg = FDI_RX_IIR(pipe);
3526 temp = I915_READ(reg);
3527 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3528 if (temp & FDI_RX_SYMBOL_LOCK) {
3529 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3530 DRM_DEBUG_KMS("FDI train 2 done.\n");
3531 break;
3532 }
3533 udelay(50);
8db9d77b 3534 }
fa37d39e
SP		 3535 if (retry < 5)
3536 break;
8db9d77b
ZW		 3537 }
3538 if (i == 4)
5eddb70b 3539 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3540
3541 DRM_DEBUG_KMS("FDI train done.\n");
3542}
3543
357555c0
JB		 3544/* Manual link training for Ivy Bridge A0 parts */
3545static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3546{
3547 struct drm_device *dev = crtc->dev;
3548 struct drm_i915_private *dev_priv = dev->dev_private;
3549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3550 int pipe = intel_crtc->pipe;
139ccd3f 3551 u32 reg, temp, i, j;
357555c0
JB		 3552
3553 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3554 for train result */
3555 reg = FDI_RX_IMR(pipe);
3556 temp = I915_READ(reg);
3557 temp &= ~FDI_RX_SYMBOL_LOCK;
3558 temp &= ~FDI_RX_BIT_LOCK;
3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
3562 udelay(150);
3563
01a415fd
DV		 3564 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3565 I915_READ(FDI_RX_IIR(pipe)));
3566
139ccd3f
JB		 3567 /* Try each vswing and preemphasis setting twice before moving on */
3568 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3569 /* disable first in case we need to retry */
3570 reg = FDI_TX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3573 temp &= ~FDI_TX_ENABLE;
3574 I915_WRITE(reg, temp);
357555c0 3575
139ccd3f
JB		 3576 reg = FDI_RX_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~FDI_LINK_TRAIN_AUTO;
3579 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3580 temp &= ~FDI_RX_ENABLE;
3581 I915_WRITE(reg, temp);
357555c0 3582
139ccd3f 3583 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3584 reg = FDI_TX_CTL(pipe);
3585 temp = I915_READ(reg);
139ccd3f 3586 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3587 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3588 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3590 temp |= snb_b_fdi_train_param[j/2];
3591 temp |= FDI_COMPOSITE_SYNC;
3592 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3593
139ccd3f
JB		 3594 I915_WRITE(FDI_RX_MISC(pipe),
3595 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3596
139ccd3f 3597 reg = FDI_RX_CTL(pipe);
357555c0 3598 temp = I915_READ(reg);
139ccd3f
JB		 3599 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3600 temp |= FDI_COMPOSITE_SYNC;
3601 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3602
139ccd3f
JB		 3603 POSTING_READ(reg);
3604 udelay(1); /* should be 0.5us */
357555c0 3605
139ccd3f
JB		 3606 for (i = 0; i < 4; i++) {
3607 reg = FDI_RX_IIR(pipe);
3608 temp = I915_READ(reg);
3609 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3610
139ccd3f
JB		 3611 if (temp & FDI_RX_BIT_LOCK ||
3612 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3613 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3614 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3615 i);
3616 break;
3617 }
3618 udelay(1); /* should be 0.5us */
3619 }
3620 if (i == 4) {
3621 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3622 continue;
3623 }
357555c0 3624
139ccd3f 3625 /* Train 2 */
357555c0
JB		 3626 reg = FDI_TX_CTL(pipe);
3627 temp = I915_READ(reg);
139ccd3f
JB		 3628 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3629 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3630 I915_WRITE(reg, temp);
3631
3632 reg = FDI_RX_CTL(pipe);
3633 temp = I915_READ(reg);
3634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3636 I915_WRITE(reg, temp);
3637
3638 POSTING_READ(reg);
139ccd3f 3639 udelay(2); /* should be 1.5us */
357555c0 3640
139ccd3f
JB		 3641 for (i = 0; i < 4; i++) {
3642 reg = FDI_RX_IIR(pipe);
3643 temp = I915_READ(reg);
3644 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3645
139ccd3f
JB		 3646 if (temp & FDI_RX_SYMBOL_LOCK ||
3647 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3648 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3649 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3650 i);
3651 goto train_done;
3652 }
3653 udelay(2); /* should be 1.5us */
357555c0 3654 }
139ccd3f
JB		 3655 if (i == 4)
3656 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3657 }
357555c0 3658
139ccd3f 3659train_done:
357555c0
JB		 3660 DRM_DEBUG_KMS("FDI train done.\n");
3661}
3662
88cefb6c 3663static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3664{
88cefb6c 3665 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3666 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3667 int pipe = intel_crtc->pipe;
5eddb70b 3668 u32 reg, temp;
79e53945 3669
c64e311e 3670
c98e9dcf 3671 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3672 reg = FDI_RX_CTL(pipe);
3673 temp = I915_READ(reg);
627eb5a3 3674 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3675 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3676 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3677 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3678
3679 POSTING_READ(reg);
c98e9dcf
JB		 3680 udelay(200);
3681
3682 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3683 temp = I915_READ(reg);
3684 I915_WRITE(reg, temp | FDI_PCDCLK);
3685
3686 POSTING_READ(reg);
c98e9dcf
JB		 3687 udelay(200);
3688
20749730
PZ		 3689 /* Enable CPU FDI TX PLL, always on for Ironlake */
3690 reg = FDI_TX_CTL(pipe);
3691 temp = I915_READ(reg);
3692 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3693 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3694
20749730
PZ		 3695 POSTING_READ(reg);
3696 udelay(100);
6be4a607 3697 }
0e23b99d
JB		 3698}
3699
88cefb6c
DV		 3700static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3701{
3702 struct drm_device *dev = intel_crtc->base.dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 int pipe = intel_crtc->pipe;
3705 u32 reg, temp;
3706
3707 /* Switch from PCDclk to Rawclk */
3708 reg = FDI_RX_CTL(pipe);
3709 temp = I915_READ(reg);
3710 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3711
3712 /* Disable CPU FDI TX PLL */
3713 reg = FDI_TX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3716
3717 POSTING_READ(reg);
3718 udelay(100);
3719
3720 reg = FDI_RX_CTL(pipe);
3721 temp = I915_READ(reg);
3722 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3723
3724 /* Wait for the clocks to turn off. */
3725 POSTING_READ(reg);
3726 udelay(100);
3727}
3728
0fc932b8
JB		 3729static void ironlake_fdi_disable(struct drm_crtc *crtc)
3730{
3731 struct drm_device *dev = crtc->dev;
3732 struct drm_i915_private *dev_priv = dev->dev_private;
3733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3734 int pipe = intel_crtc->pipe;
3735 u32 reg, temp;
3736
3737 /* disable CPU FDI tx and PCH FDI rx */
3738 reg = FDI_TX_CTL(pipe);
3739 temp = I915_READ(reg);
3740 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3741 POSTING_READ(reg);
3742
3743 reg = FDI_RX_CTL(pipe);
3744 temp = I915_READ(reg);
3745 temp &= ~(0x7 << 16);
dfd07d72 3746 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3747 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3748
3749 POSTING_READ(reg);
3750 udelay(100);
3751
3752 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3753 if (HAS_PCH_IBX(dev))
6f06ce18 3754 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3755
3756 /* still set train pattern 1 */
3757 reg = FDI_TX_CTL(pipe);
3758 temp = I915_READ(reg);
3759 temp &= ~FDI_LINK_TRAIN_NONE;
3760 temp |= FDI_LINK_TRAIN_PATTERN_1;
3761 I915_WRITE(reg, temp);
3762
3763 reg = FDI_RX_CTL(pipe);
3764 temp = I915_READ(reg);
3765 if (HAS_PCH_CPT(dev)) {
3766 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3767 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3768 } else {
3769 temp &= ~FDI_LINK_TRAIN_NONE;
3770 temp |= FDI_LINK_TRAIN_PATTERN_1;
3771 }
3772 /* BPC in FDI rx is consistent with that in PIPECONF */
3773 temp &= ~(0x07 << 16);
dfd07d72 3774 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3775 I915_WRITE(reg, temp);
3776
3777 POSTING_READ(reg);
3778 udelay(100);
3779}
3780
5dce5b93
CW		 3781bool intel_has_pending_fb_unpin(struct drm_device *dev)
3782{
3783 struct intel_crtc *crtc;
3784
3785 /* Note that we don't need to be called with mode_config.lock here
3786 * as our list of CRTC objects is static for the lifetime of the
3787 * device and so cannot disappear as we iterate. Similarly, we can
3788 * happily treat the predicates as racy, atomic checks as userspace
3789 * cannot claim and pin a new fb without at least acquring the
3790 * struct_mutex and so serialising with us.
3791 */
d3fcc808 3792 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3793 if (atomic_read(&crtc->unpin_work_count) == 0)
3794 continue;
3795
3796 if (crtc->unpin_work)
3797 intel_wait_for_vblank(dev, crtc->pipe);
3798
3799 return true;
3800 }
3801
3802 return false;
3803}
3804
d6bbafa1
CW		 3805static void page_flip_completed(struct intel_crtc *intel_crtc)
3806{
3807 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3808 struct intel_unpin_work *work = intel_crtc->unpin_work;
3809
3810 /* ensure that the unpin work is consistent wrt ->pending. */
3811 smp_rmb();
3812 intel_crtc->unpin_work = NULL;
3813
3814 if (work->event)
3815 drm_send_vblank_event(intel_crtc->base.dev,
3816 intel_crtc->pipe,
3817 work->event);
3818
3819 drm_crtc_vblank_put(&intel_crtc->base);
3820
3821 wake_up_all(&dev_priv->pending_flip_queue);
3822 queue_work(dev_priv->wq, &work->work);
3823
3824 trace_i915_flip_complete(intel_crtc->plane,
3825 work->pending_flip_obj);
3826}
3827
46a55d30 3828void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3829{
0f91128d 3830 struct drm_device *dev = crtc->dev;
5bb61643 3831 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3832
2c10d571 3833 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3834 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3835 !intel_crtc_has_pending_flip(crtc),
3836 60*HZ) == 0)) {
3837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3838
5e2d7afc 3839 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3840 if (intel_crtc->unpin_work) {
3841 WARN_ONCE(1, "Removing stuck page flip\n");
3842 page_flip_completed(intel_crtc);
3843 }
5e2d7afc 3844 spin_unlock_irq(&dev->event_lock);
9c787942 3845 }
5bb61643 3846
975d568a
CW		 3847 if (crtc->primary->fb) {
3848 mutex_lock(&dev->struct_mutex);
3849 intel_finish_fb(crtc->primary->fb);
3850 mutex_unlock(&dev->struct_mutex);
3851 }
e6c3a2a6
CW		 3852}
3853
e615efe4
ED		 3854/* Program iCLKIP clock to the desired frequency */
3855static void lpt_program_iclkip(struct drm_crtc *crtc)
3856{
3857 struct drm_device *dev = crtc->dev;
3858 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3859 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3860 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3861 u32 temp;
3862
a580516d 3863 mutex_lock(&dev_priv->sb_lock);
09153000 3864
e615efe4
ED		 3865 /* It is necessary to ungate the pixclk gate prior to programming
3866 * the divisors, and gate it back when it is done.
3867 */
3868 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3869
3870 /* Disable SSCCTL */
3871 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3872 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3873 SBI_SSCCTL_DISABLE,
3874 SBI_ICLK);
e615efe4
ED		 3875
3876 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3877 if (clock == 20000) {
e615efe4
ED		 3878 auxdiv = 1;
3879 divsel = 0x41;
3880 phaseinc = 0x20;
3881 } else {
3882 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3883 * but the adjusted_mode->crtc_clock in in KHz. To get the
3884 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3885 * convert the virtual clock precision to KHz here for higher
3886 * precision.
3887 */
3888 u32 iclk_virtual_root_freq = 172800 * 1000;
3889 u32 iclk_pi_range = 64;
3890 u32 desired_divisor, msb_divisor_value, pi_value;
3891
12d7ceed 3892 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3893 msb_divisor_value = desired_divisor / iclk_pi_range;
3894 pi_value = desired_divisor % iclk_pi_range;
3895
3896 auxdiv = 0;
3897 divsel = msb_divisor_value - 2;
3898 phaseinc = pi_value;
3899 }
3900
3901 /* This should not happen with any sane values */
3902 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3903 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3904 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3905 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3906
3907 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3908 clock,
e615efe4
ED		 3909 auxdiv,
3910 divsel,
3911 phasedir,
3912 phaseinc);
3913
3914 /* Program SSCDIVINTPHASE6 */
988d6ee8 3915 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3916 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3917 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3918 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3919 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3920 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3921 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3922 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3923
3924 /* Program SSCAUXDIV */
988d6ee8 3925 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3926 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3927 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3928 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3929
3930 /* Enable modulator and associated divider */
988d6ee8 3931 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3932 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3933 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3934
3935 /* Wait for initialization time */
3936 udelay(24);
3937
3938 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3939
a580516d 3940 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 3941}
3942
275f01b2
DV		 3943static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3944 enum pipe pch_transcoder)
3945{
3946 struct drm_device *dev = crtc->base.dev;
3947 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3948 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3949
3950 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3951 I915_READ(HTOTAL(cpu_transcoder)));
3952 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3953 I915_READ(HBLANK(cpu_transcoder)));
3954 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3955 I915_READ(HSYNC(cpu_transcoder)));
3956
3957 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3958 I915_READ(VTOTAL(cpu_transcoder)));
3959 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3960 I915_READ(VBLANK(cpu_transcoder)));
3961 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3962 I915_READ(VSYNC(cpu_transcoder)));
3963 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3964 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3965}
3966
003632d9 3967static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3968{
3969 struct drm_i915_private *dev_priv = dev->dev_private;
3970 uint32_t temp;
3971
3972 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3973 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3974 return;
3975
3976 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3977 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3978
003632d9
ACO		 3979 temp &= ~FDI_BC_BIFURCATION_SELECT;
3980 if (enable)
3981 temp |= FDI_BC_BIFURCATION_SELECT;
3982
3983 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 3984 I915_WRITE(SOUTH_CHICKEN1, temp);
3985 POSTING_READ(SOUTH_CHICKEN1);
3986}
3987
3988static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3989{
3990 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 3991
3992 switch (intel_crtc->pipe) {
3993 case PIPE_A:
3994 break;
3995 case PIPE_B:
6e3c9717 3996 if (intel_crtc->config->fdi_lanes > 2)
003632d9 3997 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 3998 else
003632d9 3999 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4000
4001 break;
4002 case PIPE_C:
003632d9 4003 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4004
4005 break;
4006 default:
4007 BUG();
4008 }
4009}
4010
f67a559d
JB		 4011/*
4012 * Enable PCH resources required for PCH ports:
4013 * - PCH PLLs
4014 * - FDI training & RX/TX
4015 * - update transcoder timings
4016 * - DP transcoding bits
4017 * - transcoder
4018 */
4019static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4020{
4021 struct drm_device *dev = crtc->dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
4023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4024 int pipe = intel_crtc->pipe;
ee7b9f93 4025 u32 reg, temp;
2c07245f 4026
ab9412ba 4027 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4028
1fbc0d78
DV		 4029 if (IS_IVYBRIDGE(dev))
4030 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4031
cd986abb
DV		 4032 /* Write the TU size bits before fdi link training, so that error
4033 * detection works. */
4034 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4035 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4036
c98e9dcf 4037 /* For PCH output, training FDI link */
674cf967 4038 dev_priv->display.fdi_link_train(crtc);
2c07245f 4039
3ad8a208
DV		 4040 /* We need to program the right clock selection before writing the pixel
4041 * mutliplier into the DPLL. */
303b81e0 4042 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4043 u32 sel;
4b645f14 4044
c98e9dcf 4045 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4046 temp |= TRANS_DPLL_ENABLE(pipe);
4047 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4048 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4049 temp |= sel;
4050 else
4051 temp &= ~sel;
c98e9dcf 4052 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4053 }
5eddb70b 4054
3ad8a208
DV		 4055 /* XXX: pch pll's can be enabled any time before we enable the PCH
4056 * transcoder, and we actually should do this to not upset any PCH
4057 * transcoder that already use the clock when we share it.
4058 *
4059 * Note that enable_shared_dpll tries to do the right thing, but
4060 * get_shared_dpll unconditionally resets the pll - we need that to have
4061 * the right LVDS enable sequence. */
85b3894f 4062 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4063
d9b6cb56
JB		 4064 /* set transcoder timing, panel must allow it */
4065 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4066 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4067
303b81e0 4068 intel_fdi_normal_train(crtc);
5e84e1a4 4069
c98e9dcf 4070 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4071 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4072 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4073 reg = TRANS_DP_CTL(pipe);
4074 temp = I915_READ(reg);
4075 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4076 TRANS_DP_SYNC_MASK |
4077 TRANS_DP_BPC_MASK);
e3ef4479 4078 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4079 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4080
4081 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4082 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4083 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4084 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4085
4086 switch (intel_trans_dp_port_sel(crtc)) {
4087 case PCH_DP_B:
5eddb70b 4088 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4089 break;
4090 case PCH_DP_C:
5eddb70b 4091 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4092 break;
4093 case PCH_DP_D:
5eddb70b 4094 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4095 break;
4096 default:
e95d41e1 4097 BUG();
32f9d658 4098 }
2c07245f 4099
5eddb70b 4100 I915_WRITE(reg, temp);
6be4a607 4101 }
b52eb4dc 4102
b8a4f404 4103 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4104}
4105
1507e5bd
PZ		 4106static void lpt_pch_enable(struct drm_crtc *crtc)
4107{
4108 struct drm_device *dev = crtc->dev;
4109 struct drm_i915_private *dev_priv = dev->dev_private;
4110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4111 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4112
ab9412ba 4113 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4114
8c52b5e8 4115 lpt_program_iclkip(crtc);
1507e5bd 4116
0540e488 4117 /* Set transcoder timing. */
275f01b2 4118 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4119
937bb610 4120 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4121}
4122
190f68c5
ACO		 4123struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4124 struct intel_crtc_state *crtc_state)
ee7b9f93 4125{
e2b78267 4126 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4127 struct intel_shared_dpll *pll;
de419ab6 4128 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4129 enum intel_dpll_id i;
ee7b9f93 4130
de419ab6
ML		 4131 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4132
98b6bd99
DV		 4133 if (HAS_PCH_IBX(dev_priv->dev)) {
4134 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4135 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4136 pll = &dev_priv->shared_dplls[i];
98b6bd99 4137
46edb027
DV		 4138 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4139 crtc->base.base.id, pll->name);
98b6bd99 4140
de419ab6 4141 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4142
98b6bd99
DV		 4143 goto found;
4144 }
4145
bcddf610
S		 4146 if (IS_BROXTON(dev_priv->dev)) {
4147 /* PLL is attached to port in bxt */
4148 struct intel_encoder *encoder;
4149 struct intel_digital_port *intel_dig_port;
4150
4151 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4152 if (WARN_ON(!encoder))
4153 return NULL;
4154
4155 intel_dig_port = enc_to_dig_port(&encoder->base);
4156 /* 1:1 mapping between ports and PLLs */
4157 i = (enum intel_dpll_id)intel_dig_port->port;
4158 pll = &dev_priv->shared_dplls[i];
4159 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4160 crtc->base.base.id, pll->name);
de419ab6 4161 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4162
4163 goto found;
4164 }
4165
e72f9fbf
DV		 4166 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4167 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4168
4169 /* Only want to check enabled timings first */
de419ab6 4170 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4171 continue;
4172
190f68c5 4173 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4174 &shared_dpll[i].hw_state,
4175 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4176 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4177 crtc->base.base.id, pll->name,
de419ab6 4178 shared_dpll[i].crtc_mask,
8bd31e67 4179 pll->active);
ee7b9f93
JB		 4180 goto found;
4181 }
4182 }
4183
4184 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4185 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4186 pll = &dev_priv->shared_dplls[i];
de419ab6 4187 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4188 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4189 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4190 goto found;
4191 }
4192 }
4193
4194 return NULL;
4195
4196found:
de419ab6
ML		 4197 if (shared_dpll[i].crtc_mask == 0)
4198 shared_dpll[i].hw_state =
4199 crtc_state->dpll_hw_state;
f2a69f44 4200
190f68c5 4201 crtc_state->shared_dpll = i;
46edb027
DV		 4202 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4203 pipe_name(crtc->pipe));
ee7b9f93 4204
de419ab6 4205 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4206
ee7b9f93
JB		 4207 return pll;
4208}
4209
de419ab6 4210static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4211{
de419ab6
ML		 4212 struct drm_i915_private *dev_priv = to_i915(state->dev);
4213 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4214 struct intel_shared_dpll *pll;
4215 enum intel_dpll_id i;
4216
de419ab6
ML		 4217 if (!to_intel_atomic_state(state)->dpll_set)
4218 return;
8bd31e67 4219
de419ab6 4220 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4221 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4222 pll = &dev_priv->shared_dplls[i];
de419ab6 4223 pll->config = shared_dpll[i];
8bd31e67
ACO		 4224 }
4225}
4226
a1520318 4227static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4228{
4229 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4230 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4231 u32 temp;
4232
4233 temp = I915_READ(dslreg);
4234 udelay(500);
4235 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4236 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4237 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4238 }
4239}
4240
86adf9d7
ML		 4241static int
4242skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4243 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4244 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4245{
86adf9d7
ML		 4246 struct intel_crtc_scaler_state *scaler_state =
4247 &crtc_state->scaler_state;
4248 struct intel_crtc *intel_crtc =
4249 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4250 int need_scaling;
6156a456
CK		 4251
4252 need_scaling = intel_rotation_90_or_270(rotation) ?
4253 (src_h != dst_w || src_w != dst_h):
4254 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4255
4256 /*
4257 * if plane is being disabled or scaler is no more required or force detach
4258 * - free scaler binded to this plane/crtc
4259 * - in order to do this, update crtc->scaler_usage
4260 *
4261 * Here scaler state in crtc_state is set free so that
4262 * scaler can be assigned to other user. Actual register
4263 * update to free the scaler is done in plane/panel-fit programming.
4264 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4265 */
86adf9d7 4266 if (force_detach || !need_scaling) {
a1b2278e 4267 if (*scaler_id >= 0) {
86adf9d7 4268 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4269 scaler_state->scalers[*scaler_id].in_use = 0;
4270
86adf9d7
ML		 4271 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4272 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4273 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4274 scaler_state->scaler_users);
4275 *scaler_id = -1;
4276 }
4277 return 0;
4278 }
4279
4280 /* range checks */
4281 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4282 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4283
4284 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4285 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4286 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4287 "size is out of scaler range\n",
86adf9d7 4288 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4289 return -EINVAL;
4290 }
4291
86adf9d7
ML		 4292 /* mark this plane as a scaler user in crtc_state */
4293 scaler_state->scaler_users |= (1 << scaler_user);
4294 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4295 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4296 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4297 scaler_state->scaler_users);
4298
4299 return 0;
4300}
4301
4302/**
4303 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4304 *
4305 * @state: crtc's scaler state
86adf9d7
ML		 4306 *
4307 * Return
4308 * 0 - scaler_usage updated successfully
4309 * error - requested scaling cannot be supported or other error condition
4310 */
e435d6e5 4311int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4312{
4313 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4314 struct drm_display_mode *adjusted_mode =
4315 &state->base.adjusted_mode;
4316
4317 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4318 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4319
e435d6e5 4320 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4321 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4322 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4323 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4324}
4325
4326/**
4327 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4328 *
4329 * @state: crtc's scaler state
86adf9d7
ML		 4330 * @plane_state: atomic plane state to update
4331 *
4332 * Return
4333 * 0 - scaler_usage updated successfully
4334 * error - requested scaling cannot be supported or other error condition
4335 */
da20eabd
ML		 4336static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4337 struct intel_plane_state *plane_state)
86adf9d7
ML		 4338{
4339
4340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4341 struct intel_plane *intel_plane =
4342 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4343 struct drm_framebuffer *fb = plane_state->base.fb;
4344 int ret;
4345
4346 bool force_detach = !fb || !plane_state->visible;
4347
4348 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4349 intel_plane->base.base.id, intel_crtc->pipe,
4350 drm_plane_index(&intel_plane->base));
4351
4352 ret = skl_update_scaler(crtc_state, force_detach,
4353 drm_plane_index(&intel_plane->base),
4354 &plane_state->scaler_id,
4355 plane_state->base.rotation,
4356 drm_rect_width(&plane_state->src) >> 16,
4357 drm_rect_height(&plane_state->src) >> 16,
4358 drm_rect_width(&plane_state->dst),
4359 drm_rect_height(&plane_state->dst));
4360
4361 if (ret || plane_state->scaler_id < 0)
4362 return ret;
4363
a1b2278e 4364 /* check colorkey */
818ed961 4365 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4366 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4367 intel_plane->base.base.id);
a1b2278e
CK		 4368 return -EINVAL;
4369 }
4370
4371 /* Check src format */
86adf9d7
ML		 4372 switch (fb->pixel_format) {
4373 case DRM_FORMAT_RGB565:
4374 case DRM_FORMAT_XBGR8888:
4375 case DRM_FORMAT_XRGB8888:
4376 case DRM_FORMAT_ABGR8888:
4377 case DRM_FORMAT_ARGB8888:
4378 case DRM_FORMAT_XRGB2101010:
4379 case DRM_FORMAT_XBGR2101010:
4380 case DRM_FORMAT_YUYV:
4381 case DRM_FORMAT_YVYU:
4382 case DRM_FORMAT_UYVY:
4383 case DRM_FORMAT_VYUY:
4384 break;
4385 default:
4386 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4387 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4388 return -EINVAL;
a1b2278e
CK		 4389 }
4390
a1b2278e
CK		 4391 return 0;
4392}
4393
e435d6e5
ML		 4394static void skylake_scaler_disable(struct intel_crtc *crtc)
4395{
4396 int i;
4397
4398 for (i = 0; i < crtc->num_scalers; i++)
4399 skl_detach_scaler(crtc, i);
4400}
4401
4402static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4403{
4404 struct drm_device *dev = crtc->base.dev;
4405 struct drm_i915_private *dev_priv = dev->dev_private;
4406 int pipe = crtc->pipe;
a1b2278e
CK		 4407 struct intel_crtc_scaler_state *scaler_state =
4408 &crtc->config->scaler_state;
4409
4410 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4411
6e3c9717 4412 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4413 int id;
4414
4415 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4416 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4417 return;
4418 }
4419
4420 id = scaler_state->scaler_id;
4421 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4422 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4423 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4424 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4425
4426 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4427 }
4428}
4429
b074cec8
JB		 4430static void ironlake_pfit_enable(struct intel_crtc *crtc)
4431{
4432 struct drm_device *dev = crtc->base.dev;
4433 struct drm_i915_private *dev_priv = dev->dev_private;
4434 int pipe = crtc->pipe;
4435
6e3c9717 4436 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4437 /* Force use of hard-coded filter coefficients
4438 * as some pre-programmed values are broken,
4439 * e.g. x201.
4440 */
4441 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4442 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4443 PF_PIPE_SEL_IVB(pipe));
4444 else
4445 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4446 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4447 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4448 }
4449}
4450
20bc8673 4451void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4452{
cea165c3
VS		 4453 struct drm_device *dev = crtc->base.dev;
4454 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4455
6e3c9717 4456 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4457 return;
4458
cea165c3
VS		 4459 /* We can only enable IPS after we enable a plane and wait for a vblank */
4460 intel_wait_for_vblank(dev, crtc->pipe);
4461
d77e4531 4462 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4463 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4464 mutex_lock(&dev_priv->rps.hw_lock);
4465 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4466 mutex_unlock(&dev_priv->rps.hw_lock);
4467 /* Quoting Art Runyan: "its not safe to expect any particular
4468 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4469 * mailbox." Moreover, the mailbox may return a bogus state,
4470 * so we need to just enable it and continue on.
2a114cc1
BW		 4471 */
4472 } else {
4473 I915_WRITE(IPS_CTL, IPS_ENABLE);
4474 /* The bit only becomes 1 in the next vblank, so this wait here
4475 * is essentially intel_wait_for_vblank. If we don't have this
4476 * and don't wait for vblanks until the end of crtc_enable, then
4477 * the HW state readout code will complain that the expected
4478 * IPS_CTL value is not the one we read. */
4479 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4480 DRM_ERROR("Timed out waiting for IPS enable\n");
4481 }
d77e4531
PZ		 4482}
4483
20bc8673 4484void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4485{
4486 struct drm_device *dev = crtc->base.dev;
4487 struct drm_i915_private *dev_priv = dev->dev_private;
4488
6e3c9717 4489 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4490 return;
4491
4492 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4493 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4494 mutex_lock(&dev_priv->rps.hw_lock);
4495 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4496 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4497 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4498 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4499 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4500 } else {
2a114cc1 4501 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4502 POSTING_READ(IPS_CTL);
4503 }
d77e4531
PZ		 4504
4505 /* We need to wait for a vblank before we can disable the plane. */
4506 intel_wait_for_vblank(dev, crtc->pipe);
4507}
4508
4509/** Loads the palette/gamma unit for the CRTC with the prepared values */
4510static void intel_crtc_load_lut(struct drm_crtc *crtc)
4511{
4512 struct drm_device *dev = crtc->dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4515 enum pipe pipe = intel_crtc->pipe;
4516 int palreg = PALETTE(pipe);
4517 int i;
4518 bool reenable_ips = false;
4519
4520 /* The clocks have to be on to load the palette. */
53d9f4e9 4521 if (!crtc->state->active)
d77e4531
PZ		 4522 return;
4523
50360403 4524 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4525 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4526 assert_dsi_pll_enabled(dev_priv);
4527 else
4528 assert_pll_enabled(dev_priv, pipe);
4529 }
4530
4531 /* use legacy palette for Ironlake */
7a1db49a 4532 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4533 palreg = LGC_PALETTE(pipe);
4534
4535 /* Workaround : Do not read or write the pipe palette/gamma data while
4536 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4537 */
6e3c9717 4538 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4539 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4540 GAMMA_MODE_MODE_SPLIT)) {
4541 hsw_disable_ips(intel_crtc);
4542 reenable_ips = true;
4543 }
4544
4545 for (i = 0; i < 256; i++) {
4546 I915_WRITE(palreg + 4 * i,
4547 (intel_crtc->lut_r[i] << 16) |
4548 (intel_crtc->lut_g[i] << 8) |
4549 intel_crtc->lut_b[i]);
4550 }
4551
4552 if (reenable_ips)
4553 hsw_enable_ips(intel_crtc);
4554}
4555
7cac945f 4556static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4557{
7cac945f 4558 if (intel_crtc->overlay) {
d3eedb1a
VS		 4559 struct drm_device *dev = intel_crtc->base.dev;
4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561
4562 mutex_lock(&dev->struct_mutex);
4563 dev_priv->mm.interruptible = false;
4564 (void) intel_overlay_switch_off(intel_crtc->overlay);
4565 dev_priv->mm.interruptible = true;
4566 mutex_unlock(&dev->struct_mutex);
4567 }
4568
4569 /* Let userspace switch the overlay on again. In most cases userspace
4570 * has to recompute where to put it anyway.
4571 */
4572}
4573
87d4300a
ML		 4574/**
4575 * intel_post_enable_primary - Perform operations after enabling primary plane
4576 * @crtc: the CRTC whose primary plane was just enabled
4577 *
4578 * Performs potentially sleeping operations that must be done after the primary
4579 * plane is enabled, such as updating FBC and IPS. Note that this may be
4580 * called due to an explicit primary plane update, or due to an implicit
4581 * re-enable that is caused when a sprite plane is updated to no longer
4582 * completely hide the primary plane.
4583 */
4584static void
4585intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4586{
4587 struct drm_device *dev = crtc->dev;
87d4300a 4588 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4590 int pipe = intel_crtc->pipe;
a5c4d7bc 4591
87d4300a
ML		 4592 /*
4593 * BDW signals flip done immediately if the plane
4594 * is disabled, even if the plane enable is already
4595 * armed to occur at the next vblank :(
4596 */
4597 if (IS_BROADWELL(dev))
4598 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4599
87d4300a
ML		 4600 /*
4601 * FIXME IPS should be fine as long as one plane is
4602 * enabled, but in practice it seems to have problems
4603 * when going from primary only to sprite only and vice
4604 * versa.
4605 */
a5c4d7bc
VS		 4606 hsw_enable_ips(intel_crtc);
4607
f99d7069 4608 /*
87d4300a
ML		 4609 * Gen2 reports pipe underruns whenever all planes are disabled.
4610 * So don't enable underrun reporting before at least some planes
4611 * are enabled.
4612 * FIXME: Need to fix the logic to work when we turn off all planes
4613 * but leave the pipe running.
f99d7069 4614 */
87d4300a
ML		 4615 if (IS_GEN2(dev))
4616 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4617
4618 /* Underruns don't raise interrupts, so check manually. */
4619 if (HAS_GMCH_DISPLAY(dev))
4620 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4621}
4622
87d4300a
ML		 4623/**
4624 * intel_pre_disable_primary - Perform operations before disabling primary plane
4625 * @crtc: the CRTC whose primary plane is to be disabled
4626 *
4627 * Performs potentially sleeping operations that must be done before the
4628 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4629 * be called due to an explicit primary plane update, or due to an implicit
4630 * disable that is caused when a sprite plane completely hides the primary
4631 * plane.
4632 */
4633static void
4634intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4635{
4636 struct drm_device *dev = crtc->dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4639 int pipe = intel_crtc->pipe;
a5c4d7bc 4640
87d4300a
ML		 4641 /*
4642 * Gen2 reports pipe underruns whenever all planes are disabled.
4643 * So diasble underrun reporting before all the planes get disabled.
4644 * FIXME: Need to fix the logic to work when we turn off all planes
4645 * but leave the pipe running.
4646 */
4647 if (IS_GEN2(dev))
4648 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4649
87d4300a
ML		 4650 /*
4651 * Vblank time updates from the shadow to live plane control register
4652 * are blocked if the memory self-refresh mode is active at that
4653 * moment. So to make sure the plane gets truly disabled, disable
4654 * first the self-refresh mode. The self-refresh enable bit in turn
4655 * will be checked/applied by the HW only at the next frame start
4656 * event which is after the vblank start event, so we need to have a
4657 * wait-for-vblank between disabling the plane and the pipe.
4658 */
262cd2e1 4659 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4660 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4661 dev_priv->wm.vlv.cxsr = false;
4662 intel_wait_for_vblank(dev, pipe);
4663 }
87d4300a 4664
87d4300a
ML		 4665 /*
4666 * FIXME IPS should be fine as long as one plane is
4667 * enabled, but in practice it seems to have problems
4668 * when going from primary only to sprite only and vice
4669 * versa.
4670 */
a5c4d7bc 4671 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4672}
4673
ac21b225
ML		 4674static void intel_post_plane_update(struct intel_crtc *crtc)
4675{
4676 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4677 struct drm_device *dev = crtc->base.dev;
7733b49b 4678 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4679 struct drm_plane *plane;
4680
4681 if (atomic->wait_vblank)
4682 intel_wait_for_vblank(dev, crtc->pipe);
4683
4684 intel_frontbuffer_flip(dev, atomic->fb_bits);
4685
852eb00d
VS		 4686 if (atomic->disable_cxsr)
4687 crtc->wm.cxsr_allowed = true;
4688
f015c551
VS		 4689 if (crtc->atomic.update_wm_post)
4690 intel_update_watermarks(&crtc->base);
4691
c80ac854 4692 if (atomic->update_fbc)
7733b49b 4693 intel_fbc_update(dev_priv);
ac21b225
ML		 4694
4695 if (atomic->post_enable_primary)
4696 intel_post_enable_primary(&crtc->base);
4697
4698 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4699 intel_update_sprite_watermarks(plane, &crtc->base,
4700 0, 0, 0, false, false);
4701
4702 memset(atomic, 0, sizeof(*atomic));
4703}
4704
4705static void intel_pre_plane_update(struct intel_crtc *crtc)
4706{
4707 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4708 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4709 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4710 struct drm_plane *p;
4711
4712 /* Track fb's for any planes being disabled */
ac21b225
ML		 4713 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4714 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4715
4716 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4717 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4718 plane->frontbuffer_bit);
ac21b225
ML		 4719 mutex_unlock(&dev->struct_mutex);
4720 }
4721
4722 if (atomic->wait_for_flips)
4723 intel_crtc_wait_for_pending_flips(&crtc->base);
4724
c80ac854 4725 if (atomic->disable_fbc)
25ad93fd 4726 intel_fbc_disable_crtc(crtc);
ac21b225 4727
066cf55b
RV		 4728 if (crtc->atomic.disable_ips)
4729 hsw_disable_ips(crtc);
4730
ac21b225
ML		 4731 if (atomic->pre_disable_primary)
4732 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4733
4734 if (atomic->disable_cxsr) {
4735 crtc->wm.cxsr_allowed = false;
4736 intel_set_memory_cxsr(dev_priv, false);
4737 }
ac21b225
ML		 4738}
4739
d032ffa0 4740static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4741{
4742 struct drm_device *dev = crtc->dev;
4743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4744 struct drm_plane *p;
87d4300a
ML		 4745 int pipe = intel_crtc->pipe;
4746
7cac945f 4747 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4748
d032ffa0
ML		 4749 drm_for_each_plane_mask(p, dev, plane_mask)
4750 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4751
f99d7069
DV		 4752 /*
4753 * FIXME: Once we grow proper nuclear flip support out of this we need
4754 * to compute the mask of flip planes precisely. For the time being
4755 * consider this a flip to a NULL plane.
4756 */
4757 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4758}
4759
f67a559d
JB		 4760static void ironlake_crtc_enable(struct drm_crtc *crtc)
4761{
4762 struct drm_device *dev = crtc->dev;
4763 struct drm_i915_private *dev_priv = dev->dev_private;
4764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4765 struct intel_encoder *encoder;
f67a559d 4766 int pipe = intel_crtc->pipe;
f67a559d 4767
53d9f4e9 4768 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4769 return;
4770
6e3c9717 4771 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4772 intel_prepare_shared_dpll(intel_crtc);
4773
6e3c9717 4774 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4775 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4776
4777 intel_set_pipe_timings(intel_crtc);
4778
6e3c9717 4779 if (intel_crtc->config->has_pch_encoder) {
29407aab 4780 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4781 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4782 }
4783
4784 ironlake_set_pipeconf(crtc);
4785
f67a559d 4786 intel_crtc->active = true;
8664281b 4787
a72e4c9f
DV		 4788 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4789 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4790
f6736a1a 4791 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4792 if (encoder->pre_enable)
4793 encoder->pre_enable(encoder);
f67a559d 4794
6e3c9717 4795 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4796 /* Note: FDI PLL enabling _must_ be done before we enable the
4797 * cpu pipes, hence this is separate from all the other fdi/pch
4798 * enabling. */
88cefb6c 4799 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4800 } else {
4801 assert_fdi_tx_disabled(dev_priv, pipe);
4802 assert_fdi_rx_disabled(dev_priv, pipe);
4803 }
f67a559d 4804
b074cec8 4805 ironlake_pfit_enable(intel_crtc);
f67a559d 4806
9c54c0dd
JB		 4807 /*
4808 * On ILK+ LUT must be loaded before the pipe is running but with
4809 * clocks enabled
4810 */
4811 intel_crtc_load_lut(crtc);
4812
f37fcc2a 4813 intel_update_watermarks(crtc);
e1fdc473 4814 intel_enable_pipe(intel_crtc);
f67a559d 4815
6e3c9717 4816 if (intel_crtc->config->has_pch_encoder)
f67a559d 4817 ironlake_pch_enable(crtc);
c98e9dcf 4818
f9b61ff6
DV		 4819 assert_vblank_disabled(crtc);
4820 drm_crtc_vblank_on(crtc);
4821
fa5c73b1
DV		 4822 for_each_encoder_on_crtc(dev, crtc, encoder)
4823 encoder->enable(encoder);
61b77ddd
DV		 4824
4825 if (HAS_PCH_CPT(dev))
a1520318 4826 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4827}
4828
42db64ef
PZ		 4829/* IPS only exists on ULT machines and is tied to pipe A. */
4830static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4831{
f5adf94e 4832 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4833}
4834
4f771f10
PZ		 4835static void haswell_crtc_enable(struct drm_crtc *crtc)
4836{
4837 struct drm_device *dev = crtc->dev;
4838 struct drm_i915_private *dev_priv = dev->dev_private;
4839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4840 struct intel_encoder *encoder;
99d736a2
ML		 4841 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4842 struct intel_crtc_state *pipe_config =
4843 to_intel_crtc_state(crtc->state);
4f771f10 4844
53d9f4e9 4845 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4846 return;
4847
df8ad70c
DV		 4848 if (intel_crtc_to_shared_dpll(intel_crtc))
4849 intel_enable_shared_dpll(intel_crtc);
4850
6e3c9717 4851 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4852 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4853
4854 intel_set_pipe_timings(intel_crtc);
4855
6e3c9717
ACO		 4856 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4857 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4858 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4859 }
4860
6e3c9717 4861 if (intel_crtc->config->has_pch_encoder) {
229fca97 4862 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4863 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4864 }
4865
4866 haswell_set_pipeconf(crtc);
4867
4868 intel_set_pipe_csc(crtc);
4869
4f771f10 4870 intel_crtc->active = true;
8664281b 4871
a72e4c9f 4872 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4873 for_each_encoder_on_crtc(dev, crtc, encoder)
4874 if (encoder->pre_enable)
4875 encoder->pre_enable(encoder);
4876
6e3c9717 4877 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4878 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4879 true);
4fe9467d
ID		 4880 dev_priv->display.fdi_link_train(crtc);
4881 }
4882
1f544388 4883 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4884
ff6d9f55 4885 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 4886 skylake_pfit_enable(intel_crtc);
ff6d9f55 4887 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4888 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4889 else
4890 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4891
4892 /*
4893 * On ILK+ LUT must be loaded before the pipe is running but with
4894 * clocks enabled
4895 */
4896 intel_crtc_load_lut(crtc);
4897
1f544388 4898 intel_ddi_set_pipe_settings(crtc);
8228c251 4899 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4900
f37fcc2a 4901 intel_update_watermarks(crtc);
e1fdc473 4902 intel_enable_pipe(intel_crtc);
42db64ef 4903
6e3c9717 4904 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4905 lpt_pch_enable(crtc);
4f771f10 4906
6e3c9717 4907 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4908 intel_ddi_set_vc_payload_alloc(crtc, true);
4909
f9b61ff6
DV		 4910 assert_vblank_disabled(crtc);
4911 drm_crtc_vblank_on(crtc);
4912
8807e55b 4913 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4914 encoder->enable(encoder);
8807e55b
JN		 4915 intel_opregion_notify_encoder(encoder, true);
4916 }
4f771f10 4917
e4916946
PZ		 4918 /* If we change the relative order between pipe/planes enabling, we need
4919 * to change the workaround. */
99d736a2
ML		 4920 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4921 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4922 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4923 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4924 }
4f771f10
PZ		 4925}
4926
3f8dce3a
DV		 4927static void ironlake_pfit_disable(struct intel_crtc *crtc)
4928{
4929 struct drm_device *dev = crtc->base.dev;
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 int pipe = crtc->pipe;
4932
4933 /* To avoid upsetting the power well on haswell only disable the pfit if
4934 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4935 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4936 I915_WRITE(PF_CTL(pipe), 0);
4937 I915_WRITE(PF_WIN_POS(pipe), 0);
4938 I915_WRITE(PF_WIN_SZ(pipe), 0);
4939 }
4940}
4941
6be4a607
JB		 4942static void ironlake_crtc_disable(struct drm_crtc *crtc)
4943{
4944 struct drm_device *dev = crtc->dev;
4945 struct drm_i915_private *dev_priv = dev->dev_private;
4946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4947 struct intel_encoder *encoder;
6be4a607 4948 int pipe = intel_crtc->pipe;
5eddb70b 4949 u32 reg, temp;
b52eb4dc 4950
ea9d758d
DV		 4951 for_each_encoder_on_crtc(dev, crtc, encoder)
4952 encoder->disable(encoder);
4953
f9b61ff6
DV		 4954 drm_crtc_vblank_off(crtc);
4955 assert_vblank_disabled(crtc);
4956
6e3c9717 4957 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4958 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4959
575f7ab7 4960 intel_disable_pipe(intel_crtc);
32f9d658 4961
3f8dce3a 4962 ironlake_pfit_disable(intel_crtc);
2c07245f 4963
5a74f70a
VS		 4964 if (intel_crtc->config->has_pch_encoder)
4965 ironlake_fdi_disable(crtc);
4966
bf49ec8c
DV		 4967 for_each_encoder_on_crtc(dev, crtc, encoder)
4968 if (encoder->post_disable)
4969 encoder->post_disable(encoder);
2c07245f 4970
6e3c9717 4971 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4972 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4973
d925c59a
DV		 4974 if (HAS_PCH_CPT(dev)) {
4975 /* disable TRANS_DP_CTL */
4976 reg = TRANS_DP_CTL(pipe);
4977 temp = I915_READ(reg);
4978 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4979 TRANS_DP_PORT_SEL_MASK);
4980 temp |= TRANS_DP_PORT_SEL_NONE;
4981 I915_WRITE(reg, temp);
4982
4983 /* disable DPLL_SEL */
4984 temp = I915_READ(PCH_DPLL_SEL);
11887397 4985 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4986 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4987 }
e3421a18 4988
d925c59a
DV		 4989 ironlake_fdi_pll_disable(intel_crtc);
4990 }
e4ca0612
PJ		 4991
4992 intel_crtc->active = false;
4993 intel_update_watermarks(crtc);
6be4a607 4994}
1b3c7a47 4995
4f771f10 4996static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 4997{
4f771f10
PZ		 4998 struct drm_device *dev = crtc->dev;
4999 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5001 struct intel_encoder *encoder;
6e3c9717 5002 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5003
8807e55b
JN		 5004 for_each_encoder_on_crtc(dev, crtc, encoder) {
5005 intel_opregion_notify_encoder(encoder, false);
4f771f10 5006 encoder->disable(encoder);
8807e55b 5007 }
4f771f10 5008
f9b61ff6
DV		 5009 drm_crtc_vblank_off(crtc);
5010 assert_vblank_disabled(crtc);
5011
6e3c9717 5012 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5013 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5014 false);
575f7ab7 5015 intel_disable_pipe(intel_crtc);
4f771f10 5016
6e3c9717 5017 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5018 intel_ddi_set_vc_payload_alloc(crtc, false);
5019
ad80a810 5020 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5021
ff6d9f55 5022 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 5023 skylake_scaler_disable(intel_crtc);
ff6d9f55 5024 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5025 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5026 else
5027 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5028
1f544388 5029 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5030
6e3c9717 5031 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5032 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5033 intel_ddi_fdi_disable(crtc);
83616634 5034 }
4f771f10 5035
97b040aa
ID		 5036 for_each_encoder_on_crtc(dev, crtc, encoder)
5037 if (encoder->post_disable)
5038 encoder->post_disable(encoder);
e4ca0612
PJ		 5039
5040 intel_crtc->active = false;
5041 intel_update_watermarks(crtc);
4f771f10
PZ		 5042}
5043
2dd24552
JB		 5044static void i9xx_pfit_enable(struct intel_crtc *crtc)
5045{
5046 struct drm_device *dev = crtc->base.dev;
5047 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5048 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5049
681a8504 5050 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5051 return;
5052
2dd24552 5053 /*
c0b03411
DV		 5054 * The panel fitter should only be adjusted whilst the pipe is disabled,
5055 * according to register description and PRM.
2dd24552 5056 */
c0b03411
DV		 5057 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5058 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5059
b074cec8
JB		 5060 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5061 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5062
5063 /* Border color in case we don't scale up to the full screen. Black by
5064 * default, change to something else for debugging. */
5065 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5066}
5067
d05410f9
DA		 5068static enum intel_display_power_domain port_to_power_domain(enum port port)
5069{
5070 switch (port) {
5071 case PORT_A:
a513e3d7 5072 case PORT_E:
d05410f9
DA		 5073 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5074 case PORT_B:
5075 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5076 case PORT_C:
5077 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5078 case PORT_D:
5079 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5080 default:
5081 WARN_ON_ONCE(1);
5082 return POWER_DOMAIN_PORT_OTHER;
5083 }
5084}
5085
77d22dca
ID		 5086#define for_each_power_domain(domain, mask) \
5087 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5088 if ((1 << (domain)) & (mask))
5089
319be8ae
ID		 5090enum intel_display_power_domain
5091intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5092{
5093 struct drm_device *dev = intel_encoder->base.dev;
5094 struct intel_digital_port *intel_dig_port;
5095
5096 switch (intel_encoder->type) {
5097 case INTEL_OUTPUT_UNKNOWN:
5098 /* Only DDI platforms should ever use this output type */
5099 WARN_ON_ONCE(!HAS_DDI(dev));
5100 case INTEL_OUTPUT_DISPLAYPORT:
5101 case INTEL_OUTPUT_HDMI:
5102 case INTEL_OUTPUT_EDP:
5103 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5104 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5105 case INTEL_OUTPUT_DP_MST:
5106 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5107 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5108 case INTEL_OUTPUT_ANALOG:
5109 return POWER_DOMAIN_PORT_CRT;
5110 case INTEL_OUTPUT_DSI:
5111 return POWER_DOMAIN_PORT_DSI;
5112 default:
5113 return POWER_DOMAIN_PORT_OTHER;
5114 }
5115}
5116
5117static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5118{
319be8ae
ID		 5119 struct drm_device *dev = crtc->dev;
5120 struct intel_encoder *intel_encoder;
5121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5122 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5123 unsigned long mask;
5124 enum transcoder transcoder;
5125
292b990e
ML		 5126 if (!crtc->state->active)
5127 return 0;
5128
77d22dca
ID		 5129 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5130
5131 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5132 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5133 if (intel_crtc->config->pch_pfit.enabled ||
5134 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5135 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5136
319be8ae
ID		 5137 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5138 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5139
77d22dca
ID		 5140 return mask;
5141}
5142
292b990e 5143static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5144{
292b990e
ML		 5145 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5147 enum intel_display_power_domain domain;
5148 unsigned long domains, new_domains, old_domains;
77d22dca 5149
292b990e
ML		 5150 old_domains = intel_crtc->enabled_power_domains;
5151 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5152
292b990e
ML		 5153 domains = new_domains & ~old_domains;
5154
5155 for_each_power_domain(domain, domains)
5156 intel_display_power_get(dev_priv, domain);
5157
5158 return old_domains & ~new_domains;
5159}
5160
5161static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5162 unsigned long domains)
5163{
5164 enum intel_display_power_domain domain;
5165
5166 for_each_power_domain(domain, domains)
5167 intel_display_power_put(dev_priv, domain);
5168}
77d22dca 5169
292b990e
ML		 5170static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5171{
5172 struct drm_device *dev = state->dev;
5173 struct drm_i915_private *dev_priv = dev->dev_private;
5174 unsigned long put_domains[I915_MAX_PIPES] = {};
5175 struct drm_crtc_state *crtc_state;
5176 struct drm_crtc *crtc;
5177 int i;
77d22dca 5178
292b990e
ML		 5179 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5180 if (needs_modeset(crtc->state))
5181 put_domains[to_intel_crtc(crtc)->pipe] =
5182 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5183 }
5184
27c329ed
ML		 5185 if (dev_priv->display.modeset_commit_cdclk) {
5186 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5187
5188 if (cdclk != dev_priv->cdclk_freq &&
5189 !WARN_ON(!state->allow_modeset))
5190 dev_priv->display.modeset_commit_cdclk(state);
5191 }
50f6e502 5192
292b990e
ML		 5193 for (i = 0; i < I915_MAX_PIPES; i++)
5194 if (put_domains[i])
5195 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5196}
5197
adafdc6f
MK		 5198static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5199{
5200 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5201
5202 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5203 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5204 return max_cdclk_freq;
5205 else if (IS_CHERRYVIEW(dev_priv))
5206 return max_cdclk_freq*95/100;
5207 else if (INTEL_INFO(dev_priv)->gen < 4)
5208 return 2*max_cdclk_freq*90/100;
5209 else
5210 return max_cdclk_freq*90/100;
5211}
5212
560a7ae4
DL		 5213static void intel_update_max_cdclk(struct drm_device *dev)
5214{
5215 struct drm_i915_private *dev_priv = dev->dev_private;
5216
5217 if (IS_SKYLAKE(dev)) {
5218 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5219
5220 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5221 dev_priv->max_cdclk_freq = 675000;
5222 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5223 dev_priv->max_cdclk_freq = 540000;
5224 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5225 dev_priv->max_cdclk_freq = 450000;
5226 else
5227 dev_priv->max_cdclk_freq = 337500;
5228 } else if (IS_BROADWELL(dev)) {
5229 /*
5230 * FIXME with extra cooling we can allow
5231 * 540 MHz for ULX and 675 Mhz for ULT.
5232 * How can we know if extra cooling is
5233 * available? PCI ID, VTB, something else?
5234 */
5235 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5236 dev_priv->max_cdclk_freq = 450000;
5237 else if (IS_BDW_ULX(dev))
5238 dev_priv->max_cdclk_freq = 450000;
5239 else if (IS_BDW_ULT(dev))
5240 dev_priv->max_cdclk_freq = 540000;
5241 else
5242 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5243 } else if (IS_CHERRYVIEW(dev)) {
5244 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5245 } else if (IS_VALLEYVIEW(dev)) {
5246 dev_priv->max_cdclk_freq = 400000;
5247 } else {
5248 /* otherwise assume cdclk is fixed */
5249 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5250 }
5251
adafdc6f
MK		 5252 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5253
560a7ae4
DL		 5254 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5255 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5256
5257 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5258 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5259}
5260
5261static void intel_update_cdclk(struct drm_device *dev)
5262{
5263 struct drm_i915_private *dev_priv = dev->dev_private;
5264
5265 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5266 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5267 dev_priv->cdclk_freq);
5268
5269 /*
5270 * Program the gmbus_freq based on the cdclk frequency.
5271 * BSpec erroneously claims we should aim for 4MHz, but
5272 * in fact 1MHz is the correct frequency.
5273 */
5274 if (IS_VALLEYVIEW(dev)) {
5275 /*
5276 * Program the gmbus_freq based on the cdclk frequency.
5277 * BSpec erroneously claims we should aim for 4MHz, but
5278 * in fact 1MHz is the correct frequency.
5279 */
5280 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5281 }
5282
5283 if (dev_priv->max_cdclk_freq == 0)
5284 intel_update_max_cdclk(dev);
5285}
5286
70d0c574 5287static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5288{
5289 struct drm_i915_private *dev_priv = dev->dev_private;
5290 uint32_t divider;
5291 uint32_t ratio;
5292 uint32_t current_freq;
5293 int ret;
5294
5295 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5296 switch (frequency) {
5297 case 144000:
5298 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5299 ratio = BXT_DE_PLL_RATIO(60);
5300 break;
5301 case 288000:
5302 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5303 ratio = BXT_DE_PLL_RATIO(60);
5304 break;
5305 case 384000:
5306 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5307 ratio = BXT_DE_PLL_RATIO(60);
5308 break;
5309 case 576000:
5310 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5311 ratio = BXT_DE_PLL_RATIO(60);
5312 break;
5313 case 624000:
5314 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5315 ratio = BXT_DE_PLL_RATIO(65);
5316 break;
5317 case 19200:
5318 /*
5319 * Bypass frequency with DE PLL disabled. Init ratio, divider
5320 * to suppress GCC warning.
5321 */
5322 ratio = 0;
5323 divider = 0;
5324 break;
5325 default:
5326 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5327
5328 return;
5329 }
5330
5331 mutex_lock(&dev_priv->rps.hw_lock);
5332 /* Inform power controller of upcoming frequency change */
5333 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5334 0x80000000);
5335 mutex_unlock(&dev_priv->rps.hw_lock);
5336
5337 if (ret) {
5338 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5339 ret, frequency);
5340 return;
5341 }
5342
5343 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5344 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5345 current_freq = current_freq * 500 + 1000;
5346
5347 /*
5348 * DE PLL has to be disabled when
5349 * - setting to 19.2MHz (bypass, PLL isn't used)
5350 * - before setting to 624MHz (PLL needs toggling)
5351 * - before setting to any frequency from 624MHz (PLL needs toggling)
5352 */
5353 if (frequency == 19200 || frequency == 624000 ||
5354 current_freq == 624000) {
5355 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5356 /* Timeout 200us */
5357 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5358 1))
5359 DRM_ERROR("timout waiting for DE PLL unlock\n");
5360 }
5361
5362 if (frequency != 19200) {
5363 uint32_t val;
5364
5365 val = I915_READ(BXT_DE_PLL_CTL);
5366 val &= ~BXT_DE_PLL_RATIO_MASK;
5367 val |= ratio;
5368 I915_WRITE(BXT_DE_PLL_CTL, val);
5369
5370 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5371 /* Timeout 200us */
5372 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5373 DRM_ERROR("timeout waiting for DE PLL lock\n");
5374
5375 val = I915_READ(CDCLK_CTL);
5376 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5377 val |= divider;
5378 /*
5379 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5380 * enable otherwise.
5381 */
5382 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5383 if (frequency >= 500000)
5384 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5385
5386 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5387 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5388 val |= (frequency - 1000) / 500;
5389 I915_WRITE(CDCLK_CTL, val);
5390 }
5391
5392 mutex_lock(&dev_priv->rps.hw_lock);
5393 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5394 DIV_ROUND_UP(frequency, 25000));
5395 mutex_unlock(&dev_priv->rps.hw_lock);
5396
5397 if (ret) {
5398 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5399 ret, frequency);
5400 return;
5401 }
5402
a47871bd 5403 intel_update_cdclk(dev);
f8437dd1
VK		 5404}
5405
5406void broxton_init_cdclk(struct drm_device *dev)
5407{
5408 struct drm_i915_private *dev_priv = dev->dev_private;
5409 uint32_t val;
5410
5411 /*
5412 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5413 * or else the reset will hang because there is no PCH to respond.
5414 * Move the handshake programming to initialization sequence.
5415 * Previously was left up to BIOS.
5416 */
5417 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5418 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5419 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5420
5421 /* Enable PG1 for cdclk */
5422 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5423
5424 /* check if cd clock is enabled */
5425 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5426 DRM_DEBUG_KMS("Display already initialized\n");
5427 return;
5428 }
5429
5430 /*
5431 * FIXME:
5432 * - The initial CDCLK needs to be read from VBT.
5433 * Need to make this change after VBT has changes for BXT.
5434 * - check if setting the max (or any) cdclk freq is really necessary
5435 * here, it belongs to modeset time
5436 */
5437 broxton_set_cdclk(dev, 624000);
5438
5439 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5440 POSTING_READ(DBUF_CTL);
5441
f8437dd1
VK		 5442 udelay(10);
5443
5444 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5445 DRM_ERROR("DBuf power enable timeout!\n");
5446}
5447
5448void broxton_uninit_cdclk(struct drm_device *dev)
5449{
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451
5452 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5453 POSTING_READ(DBUF_CTL);
5454
f8437dd1
VK		 5455 udelay(10);
5456
5457 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5458 DRM_ERROR("DBuf power disable timeout!\n");
5459
5460 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5461 broxton_set_cdclk(dev, 19200);
5462
5463 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5464}
5465
5d96d8af
DL		 5466static const struct skl_cdclk_entry {
5467 unsigned int freq;
5468 unsigned int vco;
5469} skl_cdclk_frequencies[] = {
5470 { .freq = 308570, .vco = 8640 },
5471 { .freq = 337500, .vco = 8100 },
5472 { .freq = 432000, .vco = 8640 },
5473 { .freq = 450000, .vco = 8100 },
5474 { .freq = 540000, .vco = 8100 },
5475 { .freq = 617140, .vco = 8640 },
5476 { .freq = 675000, .vco = 8100 },
5477};
5478
5479static unsigned int skl_cdclk_decimal(unsigned int freq)
5480{
5481 return (freq - 1000) / 500;
5482}
5483
5484static unsigned int skl_cdclk_get_vco(unsigned int freq)
5485{
5486 unsigned int i;
5487
5488 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5489 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5490
5491 if (e->freq == freq)
5492 return e->vco;
5493 }
5494
5495 return 8100;
5496}
5497
5498static void
5499skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5500{
5501 unsigned int min_freq;
5502 u32 val;
5503
5504 /* select the minimum CDCLK before enabling DPLL 0 */
5505 val = I915_READ(CDCLK_CTL);
5506 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5507 val |= CDCLK_FREQ_337_308;
5508
5509 if (required_vco == 8640)
5510 min_freq = 308570;
5511 else
5512 min_freq = 337500;
5513
5514 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5515
5516 I915_WRITE(CDCLK_CTL, val);
5517 POSTING_READ(CDCLK_CTL);
5518
5519 /*
5520 * We always enable DPLL0 with the lowest link rate possible, but still
5521 * taking into account the VCO required to operate the eDP panel at the
5522 * desired frequency. The usual DP link rates operate with a VCO of
5523 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5524 * The modeset code is responsible for the selection of the exact link
5525 * rate later on, with the constraint of choosing a frequency that
5526 * works with required_vco.
5527 */
5528 val = I915_READ(DPLL_CTRL1);
5529
5530 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5531 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5532 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5533 if (required_vco == 8640)
5534 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5535 SKL_DPLL0);
5536 else
5537 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5538 SKL_DPLL0);
5539
5540 I915_WRITE(DPLL_CTRL1, val);
5541 POSTING_READ(DPLL_CTRL1);
5542
5543 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5544
5545 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5546 DRM_ERROR("DPLL0 not locked\n");
5547}
5548
5549static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5550{
5551 int ret;
5552 u32 val;
5553
5554 /* inform PCU we want to change CDCLK */
5555 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5556 mutex_lock(&dev_priv->rps.hw_lock);
5557 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5558 mutex_unlock(&dev_priv->rps.hw_lock);
5559
5560 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5561}
5562
5563static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5564{
5565 unsigned int i;
5566
5567 for (i = 0; i < 15; i++) {
5568 if (skl_cdclk_pcu_ready(dev_priv))
5569 return true;
5570 udelay(10);
5571 }
5572
5573 return false;
5574}
5575
5576static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5577{
560a7ae4 5578 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5579 u32 freq_select, pcu_ack;
5580
5581 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5582
5583 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5584 DRM_ERROR("failed to inform PCU about cdclk change\n");
5585 return;
5586 }
5587
5588 /* set CDCLK_CTL */
5589 switch(freq) {
5590 case 450000:
5591 case 432000:
5592 freq_select = CDCLK_FREQ_450_432;
5593 pcu_ack = 1;
5594 break;
5595 case 540000:
5596 freq_select = CDCLK_FREQ_540;
5597 pcu_ack = 2;
5598 break;
5599 case 308570:
5600 case 337500:
5601 default:
5602 freq_select = CDCLK_FREQ_337_308;
5603 pcu_ack = 0;
5604 break;
5605 case 617140:
5606 case 675000:
5607 freq_select = CDCLK_FREQ_675_617;
5608 pcu_ack = 3;
5609 break;
5610 }
5611
5612 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5613 POSTING_READ(CDCLK_CTL);
5614
5615 /* inform PCU of the change */
5616 mutex_lock(&dev_priv->rps.hw_lock);
5617 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5618 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5619
5620 intel_update_cdclk(dev);
5d96d8af
DL		 5621}
5622
5623void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5624{
5625 /* disable DBUF power */
5626 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5627 POSTING_READ(DBUF_CTL);
5628
5629 udelay(10);
5630
5631 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5632 DRM_ERROR("DBuf power disable timeout\n");
5633
5634 /* disable DPLL0 */
5635 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5636 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5637 DRM_ERROR("Couldn't disable DPLL0\n");
5638
5639 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5640}
5641
5642void skl_init_cdclk(struct drm_i915_private *dev_priv)
5643{
5644 u32 val;
5645 unsigned int required_vco;
5646
5647 /* enable PCH reset handshake */
5648 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5649 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5650
5651 /* enable PG1 and Misc I/O */
5652 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5653
5654 /* DPLL0 already enabed !? */
5655 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5656 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5657 return;
5658 }
5659
5660 /* enable DPLL0 */
5661 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5662 skl_dpll0_enable(dev_priv, required_vco);
5663
5664 /* set CDCLK to the frequency the BIOS chose */
5665 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5666
5667 /* enable DBUF power */
5668 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5669 POSTING_READ(DBUF_CTL);
5670
5671 udelay(10);
5672
5673 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5674 DRM_ERROR("DBuf power enable timeout\n");
5675}
5676
dfcab17e 5677/* returns HPLL frequency in kHz */
f8bf63fd 5678static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5679{
586f49dc 5680 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5681
586f49dc 5682 /* Obtain SKU information */
a580516d 5683 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5684 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5685 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5686 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5687
dfcab17e 5688 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5689}
5690
5691/* Adjust CDclk dividers to allow high res or save power if possible */
5692static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5693{
5694 struct drm_i915_private *dev_priv = dev->dev_private;
5695 u32 val, cmd;
5696
164dfd28
VK		 5697 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5698 != dev_priv->cdclk_freq);
d60c4473 5699
dfcab17e 5700 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5701 cmd = 2;
dfcab17e 5702 else if (cdclk == 266667)
30a970c6
JB		 5703 cmd = 1;
5704 else
5705 cmd = 0;
5706
5707 mutex_lock(&dev_priv->rps.hw_lock);
5708 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5709 val &= ~DSPFREQGUAR_MASK;
5710 val |= (cmd << DSPFREQGUAR_SHIFT);
5711 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5712 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5713 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5714 50)) {
5715 DRM_ERROR("timed out waiting for CDclk change\n");
5716 }
5717 mutex_unlock(&dev_priv->rps.hw_lock);
5718
54433e91
VS		 5719 mutex_lock(&dev_priv->sb_lock);
5720
dfcab17e 5721 if (cdclk == 400000) {
6bcda4f0 5722 u32 divider;
30a970c6 5723
6bcda4f0 5724 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5725
30a970c6
JB		 5726 /* adjust cdclk divider */
5727 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5728 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5729 val |= divider;
5730 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5731
5732 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5733 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5734 50))
5735 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5736 }
5737
30a970c6
JB		 5738 /* adjust self-refresh exit latency value */
5739 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5740 val &= ~0x7f;
5741
5742 /*
5743 * For high bandwidth configs, we set a higher latency in the bunit
5744 * so that the core display fetch happens in time to avoid underruns.
5745 */
dfcab17e 5746 if (cdclk == 400000)
30a970c6
JB		 5747 val |= 4500 / 250; /* 4.5 usec */
5748 else
5749 val |= 3000 / 250; /* 3.0 usec */
5750 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5751
a580516d 5752 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5753
b6283055 5754 intel_update_cdclk(dev);
30a970c6
JB		 5755}
5756
383c5a6a
VS		 5757static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5758{
5759 struct drm_i915_private *dev_priv = dev->dev_private;
5760 u32 val, cmd;
5761
164dfd28
VK		 5762 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5763 != dev_priv->cdclk_freq);
383c5a6a
VS		 5764
5765 switch (cdclk) {
383c5a6a
VS		 5766 case 333333:
5767 case 320000:
383c5a6a 5768 case 266667:
383c5a6a 5769 case 200000:
383c5a6a
VS		 5770 break;
5771 default:
5f77eeb0 5772 MISSING_CASE(cdclk);
383c5a6a
VS		 5773 return;
5774 }
5775
9d0d3fda
VS		 5776 /*
5777 * Specs are full of misinformation, but testing on actual
5778 * hardware has shown that we just need to write the desired
5779 * CCK divider into the Punit register.
5780 */
5781 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5782
383c5a6a
VS		 5783 mutex_lock(&dev_priv->rps.hw_lock);
5784 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5785 val &= ~DSPFREQGUAR_MASK_CHV;
5786 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5787 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5788 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5789 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5790 50)) {
5791 DRM_ERROR("timed out waiting for CDclk change\n");
5792 }
5793 mutex_unlock(&dev_priv->rps.hw_lock);
5794
b6283055 5795 intel_update_cdclk(dev);
383c5a6a
VS		 5796}
5797
30a970c6
JB		 5798static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5799 int max_pixclk)
5800{
6bcda4f0 5801 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5802 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5803
30a970c6
JB		 5804 /*
5805 * Really only a few cases to deal with, as only 4 CDclks are supported:
5806 * 200MHz
5807 * 267MHz
29dc7ef3 5808 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5809 * 400MHz (VLV only)
5810 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5811 * of the lower bin and adjust if needed.
e37c67a1
VS		 5812 *
5813 * We seem to get an unstable or solid color picture at 200MHz.
5814 * Not sure what's wrong. For now use 200MHz only when all pipes
5815 * are off.
30a970c6 5816 */
6cca3195
VS		 5817 if (!IS_CHERRYVIEW(dev_priv) &&
5818 max_pixclk > freq_320*limit/100)
dfcab17e 5819 return 400000;
6cca3195 5820 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5821 return freq_320;
e37c67a1 5822 else if (max_pixclk > 0)
dfcab17e 5823 return 266667;
e37c67a1
VS		 5824 else
5825 return 200000;
30a970c6
JB		 5826}
5827
f8437dd1
VK		 5828static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5829 int max_pixclk)
5830{
5831 /*
5832 * FIXME:
5833 * - remove the guardband, it's not needed on BXT
5834 * - set 19.2MHz bypass frequency if there are no active pipes
5835 */
5836 if (max_pixclk > 576000*9/10)
5837 return 624000;
5838 else if (max_pixclk > 384000*9/10)
5839 return 576000;
5840 else if (max_pixclk > 288000*9/10)
5841 return 384000;
5842 else if (max_pixclk > 144000*9/10)
5843 return 288000;
5844 else
5845 return 144000;
5846}
5847
a821fc46
ACO		 5848/* Compute the max pixel clock for new configuration. Uses atomic state if
5849 * that's non-NULL, look at current state otherwise. */
5850static int intel_mode_max_pixclk(struct drm_device *dev,
5851 struct drm_atomic_state *state)
30a970c6 5852{
30a970c6 5853 struct intel_crtc *intel_crtc;
304603f4 5854 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5855 int max_pixclk = 0;
5856
d3fcc808 5857 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5858 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5859 if (IS_ERR(crtc_state))
5860 return PTR_ERR(crtc_state);
5861
5862 if (!crtc_state->base.enable)
5863 continue;
5864
5865 max_pixclk = max(max_pixclk,
5866 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5867 }
5868
5869 return max_pixclk;
5870}
5871
27c329ed 5872static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5873{
27c329ed
ML		 5874 struct drm_device *dev = state->dev;
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5876 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5877
304603f4
ACO		 5878 if (max_pixclk < 0)
5879 return max_pixclk;
30a970c6 5880
27c329ed
ML		 5881 to_intel_atomic_state(state)->cdclk =
5882 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5883
27c329ed
ML		 5884 return 0;
5885}
304603f4 5886
27c329ed
ML		 5887static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5888{
5889 struct drm_device *dev = state->dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5892
27c329ed
ML		 5893 if (max_pixclk < 0)
5894 return max_pixclk;
85a96e7a 5895
27c329ed
ML		 5896 to_intel_atomic_state(state)->cdclk =
5897 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5898
27c329ed 5899 return 0;
30a970c6
JB		 5900}
5901
1e69cd74
VS		 5902static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5903{
5904 unsigned int credits, default_credits;
5905
5906 if (IS_CHERRYVIEW(dev_priv))
5907 default_credits = PFI_CREDIT(12);
5908 else
5909 default_credits = PFI_CREDIT(8);
5910
164dfd28 5911 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5912 /* CHV suggested value is 31 or 63 */
5913 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5914 credits = PFI_CREDIT_63;
1e69cd74
VS		 5915 else
5916 credits = PFI_CREDIT(15);
5917 } else {
5918 credits = default_credits;
5919 }
5920
5921 /*
5922 * WA - write default credits before re-programming
5923 * FIXME: should we also set the resend bit here?
5924 */
5925 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5926 default_credits);
5927
5928 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5929 credits | PFI_CREDIT_RESEND);
5930
5931 /*
5932 * FIXME is this guaranteed to clear
5933 * immediately or should we poll for it?
5934 */
5935 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5936}
5937
27c329ed 5938static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5939{
a821fc46 5940 struct drm_device *dev = old_state->dev;
27c329ed 5941 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5942 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5943
27c329ed
ML		 5944 /*
5945 * FIXME: We can end up here with all power domains off, yet
5946 * with a CDCLK frequency other than the minimum. To account
5947 * for this take the PIPE-A power domain, which covers the HW
5948 * blocks needed for the following programming. This can be
5949 * removed once it's guaranteed that we get here either with
5950 * the minimum CDCLK set, or the required power domains
5951 * enabled.
5952 */
5953 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5954
27c329ed
ML		 5955 if (IS_CHERRYVIEW(dev))
5956 cherryview_set_cdclk(dev, req_cdclk);
5957 else
5958 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5959
27c329ed 5960 vlv_program_pfi_credits(dev_priv);
1e69cd74 5961
27c329ed 5962 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 5963}
5964
89b667f8
JB		 5965static void valleyview_crtc_enable(struct drm_crtc *crtc)
5966{
5967 struct drm_device *dev = crtc->dev;
a72e4c9f 5968 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5970 struct intel_encoder *encoder;
5971 int pipe = intel_crtc->pipe;
23538ef1 5972 bool is_dsi;
89b667f8 5973
53d9f4e9 5974 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 5975 return;
5976
409ee761 5977 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5978
6e3c9717 5979 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5980 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5981
5982 intel_set_pipe_timings(intel_crtc);
5983
c14b0485
VS		 5984 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5985 struct drm_i915_private *dev_priv = dev->dev_private;
5986
5987 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5988 I915_WRITE(CHV_CANVAS(pipe), 0);
5989 }
5990
5b18e57c
DV		 5991 i9xx_set_pipeconf(intel_crtc);
5992
89b667f8 5993 intel_crtc->active = true;
89b667f8 5994
a72e4c9f 5995 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5996
89b667f8
JB		 5997 for_each_encoder_on_crtc(dev, crtc, encoder)
5998 if (encoder->pre_pll_enable)
5999 encoder->pre_pll_enable(encoder);
6000
9d556c99 6001 if (!is_dsi) {
c0b4c660
VS		 6002 if (IS_CHERRYVIEW(dev)) {
6003 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6004 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6005 } else {
6006 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6007 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6008 }
9d556c99 6009 }
89b667f8
JB		 6010
6011 for_each_encoder_on_crtc(dev, crtc, encoder)
6012 if (encoder->pre_enable)
6013 encoder->pre_enable(encoder);
6014
2dd24552
JB		 6015 i9xx_pfit_enable(intel_crtc);
6016
63cbb074
VS		 6017 intel_crtc_load_lut(crtc);
6018
e1fdc473 6019 intel_enable_pipe(intel_crtc);
be6a6f8e 6020
4b3a9526
VS		 6021 assert_vblank_disabled(crtc);
6022 drm_crtc_vblank_on(crtc);
6023
f9b61ff6
DV		 6024 for_each_encoder_on_crtc(dev, crtc, encoder)
6025 encoder->enable(encoder);
89b667f8
JB		 6026}
6027
f13c2ef3
DV		 6028static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6029{
6030 struct drm_device *dev = crtc->base.dev;
6031 struct drm_i915_private *dev_priv = dev->dev_private;
6032
6e3c9717
ACO		 6033 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6034 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6035}
6036
0b8765c6 6037static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6038{
6039 struct drm_device *dev = crtc->dev;
a72e4c9f 6040 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6042 struct intel_encoder *encoder;
79e53945 6043 int pipe = intel_crtc->pipe;
79e53945 6044
53d9f4e9 6045 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6046 return;
6047
f13c2ef3
DV		 6048 i9xx_set_pll_dividers(intel_crtc);
6049
6e3c9717 6050 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6051 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6052
6053 intel_set_pipe_timings(intel_crtc);
6054
5b18e57c
DV		 6055 i9xx_set_pipeconf(intel_crtc);
6056
f7abfe8b 6057 intel_crtc->active = true;
6b383a7f 6058
4a3436e8 6059 if (!IS_GEN2(dev))
a72e4c9f 6060 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6061
9d6d9f19
MK		 6062 for_each_encoder_on_crtc(dev, crtc, encoder)
6063 if (encoder->pre_enable)
6064 encoder->pre_enable(encoder);
6065
f6736a1a
DV		 6066 i9xx_enable_pll(intel_crtc);
6067
2dd24552
JB		 6068 i9xx_pfit_enable(intel_crtc);
6069
63cbb074
VS		 6070 intel_crtc_load_lut(crtc);
6071
f37fcc2a 6072 intel_update_watermarks(crtc);
e1fdc473 6073 intel_enable_pipe(intel_crtc);
be6a6f8e 6074
4b3a9526
VS		 6075 assert_vblank_disabled(crtc);
6076 drm_crtc_vblank_on(crtc);
6077
f9b61ff6
DV		 6078 for_each_encoder_on_crtc(dev, crtc, encoder)
6079 encoder->enable(encoder);
0b8765c6 6080}
79e53945 6081
87476d63
DV		 6082static void i9xx_pfit_disable(struct intel_crtc *crtc)
6083{
6084 struct drm_device *dev = crtc->base.dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6086
6e3c9717 6087 if (!crtc->config->gmch_pfit.control)
328d8e82 6088 return;
87476d63 6089
328d8e82 6090 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6091
328d8e82
DV		 6092 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6093 I915_READ(PFIT_CONTROL));
6094 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6095}
6096
0b8765c6
JB		 6097static void i9xx_crtc_disable(struct drm_crtc *crtc)
6098{
6099 struct drm_device *dev = crtc->dev;
6100 struct drm_i915_private *dev_priv = dev->dev_private;
6101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6102 struct intel_encoder *encoder;
0b8765c6 6103 int pipe = intel_crtc->pipe;
ef9c3aee 6104
6304cd91
VS		 6105 /*
6106 * On gen2 planes are double buffered but the pipe isn't, so we must
6107 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6108 * We also need to wait on all gmch platforms because of the
6109 * self-refresh mode constraint explained above.
6304cd91 6110 */
564ed191 6111 intel_wait_for_vblank(dev, pipe);
6304cd91 6112
4b3a9526
VS		 6113 for_each_encoder_on_crtc(dev, crtc, encoder)
6114 encoder->disable(encoder);
6115
f9b61ff6
DV		 6116 drm_crtc_vblank_off(crtc);
6117 assert_vblank_disabled(crtc);
6118
575f7ab7 6119 intel_disable_pipe(intel_crtc);
24a1f16d 6120
87476d63 6121 i9xx_pfit_disable(intel_crtc);
24a1f16d 6122
89b667f8
JB		 6123 for_each_encoder_on_crtc(dev, crtc, encoder)
6124 if (encoder->post_disable)
6125 encoder->post_disable(encoder);
6126
409ee761 6127 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6128 if (IS_CHERRYVIEW(dev))
6129 chv_disable_pll(dev_priv, pipe);
6130 else if (IS_VALLEYVIEW(dev))
6131 vlv_disable_pll(dev_priv, pipe);
6132 else
1c4e0274 6133 i9xx_disable_pll(intel_crtc);
076ed3b2 6134 }
0b8765c6 6135
d6db995f
VS		 6136 for_each_encoder_on_crtc(dev, crtc, encoder)
6137 if (encoder->post_pll_disable)
6138 encoder->post_pll_disable(encoder);
6139
4a3436e8 6140 if (!IS_GEN2(dev))
a72e4c9f 6141 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6142
6143 intel_crtc->active = false;
6144 intel_update_watermarks(crtc);
0b8765c6
JB		 6145}
6146
b17d48e2
ML		 6147static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6148{
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6150 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6151 enum intel_display_power_domain domain;
6152 unsigned long domains;
6153
6154 if (!intel_crtc->active)
6155 return;
6156
a539205a
ML		 6157 if (to_intel_plane_state(crtc->primary->state)->visible) {
6158 intel_crtc_wait_for_pending_flips(crtc);
6159 intel_pre_disable_primary(crtc);
6160 }
6161
d032ffa0 6162 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6163 dev_priv->display.crtc_disable(crtc);
1f7457b1 6164 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6165
6166 domains = intel_crtc->enabled_power_domains;
6167 for_each_power_domain(domain, domains)
6168 intel_display_power_put(dev_priv, domain);
6169 intel_crtc->enabled_power_domains = 0;
6170}
6171
6b72d486
ML		 6172/*
6173 * turn all crtc's off, but do not adjust state
6174 * This has to be paired with a call to intel_modeset_setup_hw_state.
6175 */
70e0bd74 6176int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6177{
70e0bd74
ML		 6178 struct drm_mode_config *config = &dev->mode_config;
6179 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6180 struct drm_atomic_state *state;
6b72d486 6181 struct drm_crtc *crtc;
70e0bd74
ML		 6182 unsigned crtc_mask = 0;
6183 int ret = 0;
6184
6185 if (WARN_ON(!ctx))
6186 return 0;
6187
6188 lockdep_assert_held(&ctx->ww_ctx);
6189 state = drm_atomic_state_alloc(dev);
6190 if (WARN_ON(!state))
6191 return -ENOMEM;
6192
6193 state->acquire_ctx = ctx;
6194 state->allow_modeset = true;
6195
6196 for_each_crtc(dev, crtc) {
6197 struct drm_crtc_state *crtc_state =
6198 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6199
70e0bd74
ML		 6200 ret = PTR_ERR_OR_ZERO(crtc_state);
6201 if (ret)
6202 goto free;
6203
6204 if (!crtc_state->active)
6205 continue;
6206
6207 crtc_state->active = false;
6208 crtc_mask |= 1 << drm_crtc_index(crtc);
6209 }
6210
6211 if (crtc_mask) {
74c090b1 6212 ret = drm_atomic_commit(state);
70e0bd74
ML		 6213
6214 if (!ret) {
6215 for_each_crtc(dev, crtc)
6216 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6217 crtc->state->active = true;
6218
6219 return ret;
6220 }
6221 }
6222
6223free:
6224 if (ret)
6225 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6226 drm_atomic_state_free(state);
6227 return ret;
ee7b9f93
JB		 6228}
6229
ea5b213a 6230void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6231{
4ef69c7a 6232 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6233
ea5b213a
CW		 6234 drm_encoder_cleanup(encoder);
6235 kfree(intel_encoder);
7e7d76c3
JB		 6236}
6237
0a91ca29
DV		 6238/* Cross check the actual hw state with our own modeset state tracking (and it's
6239 * internal consistency). */
b980514c 6240static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6241{
35dd3c64
ML		 6242 struct drm_crtc *crtc = connector->base.state->crtc;
6243
6244 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6245 connector->base.base.id,
6246 connector->base.name);
6247
0a91ca29 6248 if (connector->get_hw_state(connector)) {
35dd3c64
ML		 6249 struct drm_encoder *encoder = &connector->encoder->base;
6250 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6251
35dd3c64
ML		 6252 I915_STATE_WARN(!crtc,
6253 "connector enabled without attached crtc\n");
0a91ca29 6254
35dd3c64
ML		 6255 if (!crtc)
6256 return;
6257
6258 I915_STATE_WARN(!crtc->state->active,
6259 "connector is active, but attached crtc isn't\n");
6260
6261 if (!encoder)
6262 return;
6263
6264 I915_STATE_WARN(conn_state->best_encoder != encoder,
6265 "atomic encoder doesn't match attached encoder\n");
6266
6267 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6268 "attached encoder crtc differs from connector crtc\n");
6269 } else {
4d688a2a
ML		 6270 I915_STATE_WARN(crtc && crtc->state->active,
6271 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6272 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6273 "best encoder set without crtc!\n");
0a91ca29 6274 }
79e53945
JB		 6275}
6276
08d9bc92
ACO		 6277int intel_connector_init(struct intel_connector *connector)
6278{
6279 struct drm_connector_state *connector_state;
6280
6281 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6282 if (!connector_state)
6283 return -ENOMEM;
6284
6285 connector->base.state = connector_state;
6286 return 0;
6287}
6288
6289struct intel_connector *intel_connector_alloc(void)
6290{
6291 struct intel_connector *connector;
6292
6293 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6294 if (!connector)
6295 return NULL;
6296
6297 if (intel_connector_init(connector) < 0) {
6298 kfree(connector);
6299 return NULL;
6300 }
6301
6302 return connector;
6303}
6304
f0947c37
DV		 6305/* Simple connector->get_hw_state implementation for encoders that support only
6306 * one connector and no cloning and hence the encoder state determines the state
6307 * of the connector. */
6308bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6309{
24929352 6310 enum pipe pipe = 0;
f0947c37 6311 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6312
f0947c37 6313 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6314}
6315
6d293983 6316static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6317{
6d293983
ACO		 6318 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6319 return crtc_state->fdi_lanes;
d272ddfa
VS		 6320
6321 return 0;
6322}
6323
6d293983 6324static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6325 struct intel_crtc_state *pipe_config)
1857e1da 6326{
6d293983
ACO		 6327 struct drm_atomic_state *state = pipe_config->base.state;
6328 struct intel_crtc *other_crtc;
6329 struct intel_crtc_state *other_crtc_state;
6330
1857e1da
DV		 6331 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6332 pipe_name(pipe), pipe_config->fdi_lanes);
6333 if (pipe_config->fdi_lanes > 4) {
6334 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6335 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6336 return -EINVAL;
1857e1da
DV		 6337 }
6338
bafb6553 6339 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6340 if (pipe_config->fdi_lanes > 2) {
6341 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6342 pipe_config->fdi_lanes);
6d293983 6343 return -EINVAL;
1857e1da 6344 } else {
6d293983 6345 return 0;
1857e1da
DV		 6346 }
6347 }
6348
6349 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6350 return 0;
1857e1da
DV		 6351
6352 /* Ivybridge 3 pipe is really complicated */
6353 switch (pipe) {
6354 case PIPE_A:
6d293983 6355 return 0;
1857e1da 6356 case PIPE_B:
6d293983
ACO		 6357 if (pipe_config->fdi_lanes <= 2)
6358 return 0;
6359
6360 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6361 other_crtc_state =
6362 intel_atomic_get_crtc_state(state, other_crtc);
6363 if (IS_ERR(other_crtc_state))
6364 return PTR_ERR(other_crtc_state);
6365
6366 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6367 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6368 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6369 return -EINVAL;
1857e1da 6370 }
6d293983 6371 return 0;
1857e1da 6372 case PIPE_C:
251cc67c
VS		 6373 if (pipe_config->fdi_lanes > 2) {
6374 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6375 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6376 return -EINVAL;
251cc67c 6377 }
6d293983
ACO		 6378
6379 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6380 other_crtc_state =
6381 intel_atomic_get_crtc_state(state, other_crtc);
6382 if (IS_ERR(other_crtc_state))
6383 return PTR_ERR(other_crtc_state);
6384
6385 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6386 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6387 return -EINVAL;
1857e1da 6388 }
6d293983 6389 return 0;
1857e1da
DV		 6390 default:
6391 BUG();
6392 }
6393}
6394
e29c22c0
DV		 6395#define RETRY 1
6396static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6397 struct intel_crtc_state *pipe_config)
877d48d5 6398{
1857e1da 6399 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6400 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6401 int lane, link_bw, fdi_dotclock, ret;
6402 bool needs_recompute = false;
877d48d5 6403
e29c22c0 6404retry:
877d48d5
DV		 6405 /* FDI is a binary signal running at ~2.7GHz, encoding
6406 * each output octet as 10 bits. The actual frequency
6407 * is stored as a divider into a 100MHz clock, and the
6408 * mode pixel clock is stored in units of 1KHz.
6409 * Hence the bw of each lane in terms of the mode signal
6410 * is:
6411 */
6412 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6413
241bfc38 6414 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6415
2bd89a07 6416 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6417 pipe_config->pipe_bpp);
6418
6419 pipe_config->fdi_lanes = lane;
6420
2bd89a07 6421 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6422 link_bw, &pipe_config->fdi_m_n);
1857e1da 6423
6d293983
ACO		 6424 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6425 intel_crtc->pipe, pipe_config);
6426 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6427 pipe_config->pipe_bpp -= 2*3;
6428 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6429 pipe_config->pipe_bpp);
6430 needs_recompute = true;
6431 pipe_config->bw_constrained = true;
6432
6433 goto retry;
6434 }
6435
6436 if (needs_recompute)
6437 return RETRY;
6438
6d293983 6439 return ret;
877d48d5
DV		 6440}
6441
8cfb3407
VS		 6442static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6443 struct intel_crtc_state *pipe_config)
6444{
6445 if (pipe_config->pipe_bpp > 24)
6446 return false;
6447
6448 /* HSW can handle pixel rate up to cdclk? */
6449 if (IS_HASWELL(dev_priv->dev))
6450 return true;
6451
6452 /*
b432e5cf
VS		 6453 * We compare against max which means we must take
6454 * the increased cdclk requirement into account when
6455 * calculating the new cdclk.
6456 *
6457 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6458 */
6459 return ilk_pipe_pixel_rate(pipe_config) <=
6460 dev_priv->max_cdclk_freq * 95 / 100;
6461}
6462
42db64ef 6463static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6464 struct intel_crtc_state *pipe_config)
42db64ef 6465{
8cfb3407
VS		 6466 struct drm_device *dev = crtc->base.dev;
6467 struct drm_i915_private *dev_priv = dev->dev_private;
6468
d330a953 6469 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6470 hsw_crtc_supports_ips(crtc) &&
6471 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6472}
6473
a43f6e0f 6474static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6475 struct intel_crtc_state *pipe_config)
79e53945 6476{
a43f6e0f 6477 struct drm_device *dev = crtc->base.dev;
8bd31e67 6478 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6479 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6480
ad3a4479 6481 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6482 if (INTEL_INFO(dev)->gen < 4) {
44913155 6483 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6484
6485 /*
6486 * Enable pixel doubling when the dot clock
6487 * is > 90% of the (display) core speed.
6488 *
b397c96b
VS		 6489 * GDG double wide on either pipe,
6490 * otherwise pipe A only.
cf532bb2 6491 */
b397c96b 6492 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6493 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6494 clock_limit *= 2;
cf532bb2 6495 pipe_config->double_wide = true;
ad3a4479
VS		 6496 }
6497
241bfc38 6498 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6499 return -EINVAL;
2c07245f 6500 }
89749350 6501
1d1d0e27
VS		 6502 /*
6503 * Pipe horizontal size must be even in:
6504 * - DVO ganged mode
6505 * - LVDS dual channel mode
6506 * - Double wide pipe
6507 */
a93e255f 6508 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6509 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6510 pipe_config->pipe_src_w &= ~1;
6511
8693a824
DL		 6512 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6513 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6514 */
6515 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6516 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6517 return -EINVAL;
44f46b42 6518
f5adf94e 6519 if (HAS_IPS(dev))
a43f6e0f
DV		 6520 hsw_compute_ips_config(crtc, pipe_config);
6521
877d48d5 6522 if (pipe_config->has_pch_encoder)
a43f6e0f 6523 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6524
cf5a15be 6525 return 0;
79e53945
JB		 6526}
6527
1652d19e
VS		 6528static int skylake_get_display_clock_speed(struct drm_device *dev)
6529{
6530 struct drm_i915_private *dev_priv = to_i915(dev);
6531 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6532 uint32_t cdctl = I915_READ(CDCLK_CTL);
6533 uint32_t linkrate;
6534
414355a7 6535 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6536 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6537
6538 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6539 return 540000;
6540
6541 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6542 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6543
71cd8423
DL		 6544 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6545 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6546 /* vco 8640 */
6547 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6548 case CDCLK_FREQ_450_432:
6549 return 432000;
6550 case CDCLK_FREQ_337_308:
6551 return 308570;
6552 case CDCLK_FREQ_675_617:
6553 return 617140;
6554 default:
6555 WARN(1, "Unknown cd freq selection\n");
6556 }
6557 } else {
6558 /* vco 8100 */
6559 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6560 case CDCLK_FREQ_450_432:
6561 return 450000;
6562 case CDCLK_FREQ_337_308:
6563 return 337500;
6564 case CDCLK_FREQ_675_617:
6565 return 675000;
6566 default:
6567 WARN(1, "Unknown cd freq selection\n");
6568 }
6569 }
6570
6571 /* error case, do as if DPLL0 isn't enabled */
6572 return 24000;
6573}
6574
acd3f3d3
BP		 6575static int broxton_get_display_clock_speed(struct drm_device *dev)
6576{
6577 struct drm_i915_private *dev_priv = to_i915(dev);
6578 uint32_t cdctl = I915_READ(CDCLK_CTL);
6579 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6580 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6581 int cdclk;
6582
6583 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6584 return 19200;
6585
6586 cdclk = 19200 * pll_ratio / 2;
6587
6588 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6589 case BXT_CDCLK_CD2X_DIV_SEL_1:
6590 return cdclk; /* 576MHz or 624MHz */
6591 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6592 return cdclk * 2 / 3; /* 384MHz */
6593 case BXT_CDCLK_CD2X_DIV_SEL_2:
6594 return cdclk / 2; /* 288MHz */
6595 case BXT_CDCLK_CD2X_DIV_SEL_4:
6596 return cdclk / 4; /* 144MHz */
6597 }
6598
6599 /* error case, do as if DE PLL isn't enabled */
6600 return 19200;
6601}
6602
1652d19e
VS		 6603static int broadwell_get_display_clock_speed(struct drm_device *dev)
6604{
6605 struct drm_i915_private *dev_priv = dev->dev_private;
6606 uint32_t lcpll = I915_READ(LCPLL_CTL);
6607 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6608
6609 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6610 return 800000;
6611 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6612 return 450000;
6613 else if (freq == LCPLL_CLK_FREQ_450)
6614 return 450000;
6615 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6616 return 540000;
6617 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6618 return 337500;
6619 else
6620 return 675000;
6621}
6622
6623static int haswell_get_display_clock_speed(struct drm_device *dev)
6624{
6625 struct drm_i915_private *dev_priv = dev->dev_private;
6626 uint32_t lcpll = I915_READ(LCPLL_CTL);
6627 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6628
6629 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6630 return 800000;
6631 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6632 return 450000;
6633 else if (freq == LCPLL_CLK_FREQ_450)
6634 return 450000;
6635 else if (IS_HSW_ULT(dev))
6636 return 337500;
6637 else
6638 return 540000;
79e53945
JB		 6639}
6640
25eb05fc
JB		 6641static int valleyview_get_display_clock_speed(struct drm_device *dev)
6642{
d197b7d3 6643 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6644 u32 val;
6645 int divider;
6646
6bcda4f0
VS		 6647 if (dev_priv->hpll_freq == 0)
6648 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6649
a580516d 6650 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6651 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6652 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6653
6654 divider = val & DISPLAY_FREQUENCY_VALUES;
6655
7d007f40
VS		 6656 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6657 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6658 "cdclk change in progress\n");
6659
6bcda4f0 6660 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6661}
6662
b37a6434
VS		 6663static int ilk_get_display_clock_speed(struct drm_device *dev)
6664{
6665 return 450000;
6666}
6667
e70236a8
JB		 6668static int i945_get_display_clock_speed(struct drm_device *dev)
6669{
6670 return 400000;
6671}
79e53945 6672
e70236a8 6673static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6674{
e907f170 6675 return 333333;
e70236a8 6676}
79e53945 6677
e70236a8
JB		 6678static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6679{
6680 return 200000;
6681}
79e53945 6682
257a7ffc
DV		 6683static int pnv_get_display_clock_speed(struct drm_device *dev)
6684{
6685 u16 gcfgc = 0;
6686
6687 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6688
6689 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6690 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6691 return 266667;
257a7ffc 6692 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6693 return 333333;
257a7ffc 6694 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6695 return 444444;
257a7ffc
DV		 6696 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6697 return 200000;
6698 default:
6699 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6700 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6701 return 133333;
257a7ffc 6702 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6703 return 166667;
257a7ffc
DV		 6704 }
6705}
6706
e70236a8
JB		 6707static int i915gm_get_display_clock_speed(struct drm_device *dev)
6708{
6709 u16 gcfgc = 0;
79e53945 6710
e70236a8
JB		 6711 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6712
6713 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6714 return 133333;
e70236a8
JB		 6715 else {
6716 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6717 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6718 return 333333;
e70236a8
JB		 6719 default:
6720 case GC_DISPLAY_CLOCK_190_200_MHZ:
6721 return 190000;
79e53945 6722 }
e70236a8
JB		 6723 }
6724}
6725
6726static int i865_get_display_clock_speed(struct drm_device *dev)
6727{
e907f170 6728 return 266667;
e70236a8
JB		 6729}
6730
1b1d2716 6731static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6732{
6733 u16 hpllcc = 0;
1b1d2716 6734
65cd2b3f
VS		 6735 /*
6736 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6737 * encoding is different :(
6738 * FIXME is this the right way to detect 852GM/852GMV?
6739 */
6740 if (dev->pdev->revision == 0x1)
6741 return 133333;
6742
1b1d2716
VS		 6743 pci_bus_read_config_word(dev->pdev->bus,
6744 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6745
e70236a8
JB		 6746 /* Assume that the hardware is in the high speed state. This
6747 * should be the default.
6748 */
6749 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6750 case GC_CLOCK_133_200:
1b1d2716 6751 case GC_CLOCK_133_200_2:
e70236a8
JB		 6752 case GC_CLOCK_100_200:
6753 return 200000;
6754 case GC_CLOCK_166_250:
6755 return 250000;
6756 case GC_CLOCK_100_133:
e907f170 6757 return 133333;
1b1d2716
VS		 6758 case GC_CLOCK_133_266:
6759 case GC_CLOCK_133_266_2:
6760 case GC_CLOCK_166_266:
6761 return 266667;
e70236a8 6762 }
79e53945 6763
e70236a8
JB		 6764 /* Shouldn't happen */
6765 return 0;
6766}
79e53945 6767
e70236a8
JB		 6768static int i830_get_display_clock_speed(struct drm_device *dev)
6769{
e907f170 6770 return 133333;
79e53945
JB		 6771}
6772
34edce2f
VS		 6773static unsigned int intel_hpll_vco(struct drm_device *dev)
6774{
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 static const unsigned int blb_vco[8] = {
6777 [0] = 3200000,
6778 [1] = 4000000,
6779 [2] = 5333333,
6780 [3] = 4800000,
6781 [4] = 6400000,
6782 };
6783 static const unsigned int pnv_vco[8] = {
6784 [0] = 3200000,
6785 [1] = 4000000,
6786 [2] = 5333333,
6787 [3] = 4800000,
6788 [4] = 2666667,
6789 };
6790 static const unsigned int cl_vco[8] = {
6791 [0] = 3200000,
6792 [1] = 4000000,
6793 [2] = 5333333,
6794 [3] = 6400000,
6795 [4] = 3333333,
6796 [5] = 3566667,
6797 [6] = 4266667,
6798 };
6799 static const unsigned int elk_vco[8] = {
6800 [0] = 3200000,
6801 [1] = 4000000,
6802 [2] = 5333333,
6803 [3] = 4800000,
6804 };
6805 static const unsigned int ctg_vco[8] = {
6806 [0] = 3200000,
6807 [1] = 4000000,
6808 [2] = 5333333,
6809 [3] = 6400000,
6810 [4] = 2666667,
6811 [5] = 4266667,
6812 };
6813 const unsigned int *vco_table;
6814 unsigned int vco;
6815 uint8_t tmp = 0;
6816
6817 /* FIXME other chipsets? */
6818 if (IS_GM45(dev))
6819 vco_table = ctg_vco;
6820 else if (IS_G4X(dev))
6821 vco_table = elk_vco;
6822 else if (IS_CRESTLINE(dev))
6823 vco_table = cl_vco;
6824 else if (IS_PINEVIEW(dev))
6825 vco_table = pnv_vco;
6826 else if (IS_G33(dev))
6827 vco_table = blb_vco;
6828 else
6829 return 0;
6830
6831 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6832
6833 vco = vco_table[tmp & 0x7];
6834 if (vco == 0)
6835 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6836 else
6837 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6838
6839 return vco;
6840}
6841
6842static int gm45_get_display_clock_speed(struct drm_device *dev)
6843{
6844 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6845 uint16_t tmp = 0;
6846
6847 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6848
6849 cdclk_sel = (tmp >> 12) & 0x1;
6850
6851 switch (vco) {
6852 case 2666667:
6853 case 4000000:
6854 case 5333333:
6855 return cdclk_sel ? 333333 : 222222;
6856 case 3200000:
6857 return cdclk_sel ? 320000 : 228571;
6858 default:
6859 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6860 return 222222;
6861 }
6862}
6863
6864static int i965gm_get_display_clock_speed(struct drm_device *dev)
6865{
6866 static const uint8_t div_3200[] = { 16, 10, 8 };
6867 static const uint8_t div_4000[] = { 20, 12, 10 };
6868 static const uint8_t div_5333[] = { 24, 16, 14 };
6869 const uint8_t *div_table;
6870 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6871 uint16_t tmp = 0;
6872
6873 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6874
6875 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6876
6877 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6878 goto fail;
6879
6880 switch (vco) {
6881 case 3200000:
6882 div_table = div_3200;
6883 break;
6884 case 4000000:
6885 div_table = div_4000;
6886 break;
6887 case 5333333:
6888 div_table = div_5333;
6889 break;
6890 default:
6891 goto fail;
6892 }
6893
6894 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6895
caf4e252 6896fail:
34edce2f
VS		 6897 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6898 return 200000;
6899}
6900
6901static int g33_get_display_clock_speed(struct drm_device *dev)
6902{
6903 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6904 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6905 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6906 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6907 const uint8_t *div_table;
6908 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6909 uint16_t tmp = 0;
6910
6911 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6912
6913 cdclk_sel = (tmp >> 4) & 0x7;
6914
6915 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6916 goto fail;
6917
6918 switch (vco) {
6919 case 3200000:
6920 div_table = div_3200;
6921 break;
6922 case 4000000:
6923 div_table = div_4000;
6924 break;
6925 case 4800000:
6926 div_table = div_4800;
6927 break;
6928 case 5333333:
6929 div_table = div_5333;
6930 break;
6931 default:
6932 goto fail;
6933 }
6934
6935 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6936
caf4e252 6937fail:
34edce2f
VS		 6938 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6939 return 190476;
6940}
6941
2c07245f 6942static void
a65851af 6943intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6944{
a65851af
VS		 6945 while (*num > DATA_LINK_M_N_MASK ||
6946 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6947 *num >>= 1;
6948 *den >>= 1;
6949 }
6950}
6951
a65851af
VS		 6952static void compute_m_n(unsigned int m, unsigned int n,
6953 uint32_t *ret_m, uint32_t *ret_n)
6954{
6955 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6956 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6957 intel_reduce_m_n_ratio(ret_m, ret_n);
6958}
6959
e69d0bc1
DV		 6960void
6961intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6962 int pixel_clock, int link_clock,
6963 struct intel_link_m_n *m_n)
2c07245f 6964{
e69d0bc1 6965 m_n->tu = 64;
a65851af
VS		 6966
6967 compute_m_n(bits_per_pixel * pixel_clock,
6968 link_clock * nlanes * 8,
6969 &m_n->gmch_m, &m_n->gmch_n);
6970
6971 compute_m_n(pixel_clock, link_clock,
6972 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6973}
6974
a7615030
CW		 6975static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6976{
d330a953
JN		 6977 if (i915.panel_use_ssc >= 0)
6978 return i915.panel_use_ssc != 0;
41aa3448 6979 return dev_priv->vbt.lvds_use_ssc
435793df 6980 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6981}
6982
a93e255f
ACO		 6983static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6984 int num_connectors)
c65d77d8 6985{
a93e255f 6986 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6987 struct drm_i915_private *dev_priv = dev->dev_private;
6988 int refclk;
6989
a93e255f
ACO		 6990 WARN_ON(!crtc_state->base.state);
6991
5ab7b0b7 6992 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6993 refclk = 100000;
a93e255f 6994 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6995 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6996 refclk = dev_priv->vbt.lvds_ssc_freq;
6997 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6998 } else if (!IS_GEN2(dev)) {
6999 refclk = 96000;
7000 } else {
7001 refclk = 48000;
7002 }
7003
7004 return refclk;
7005}
7006
7429e9d4 7007static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7008{
7df00d7a 7009 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7010}
f47709a9 7011
7429e9d4
DV		 7012static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7013{
7014 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7015}
7016
f47709a9 7017static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7018 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7019 intel_clock_t *reduced_clock)
7020{
f47709a9 7021 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7022 u32 fp, fp2 = 0;
7023
7024 if (IS_PINEVIEW(dev)) {
190f68c5 7025 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7026 if (reduced_clock)
7429e9d4 7027 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7028 } else {
190f68c5 7029 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7030 if (reduced_clock)
7429e9d4 7031 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7032 }
7033
190f68c5 7034 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7035
f47709a9 7036 crtc->lowfreq_avail = false;
a93e255f 7037 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7038 reduced_clock) {
190f68c5 7039 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7040 crtc->lowfreq_avail = true;
a7516a05 7041 } else {
190f68c5 7042 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7043 }
7044}
7045
5e69f97f
CML		 7046static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7047 pipe)
89b667f8
JB		 7048{
7049 u32 reg_val;
7050
7051 /*
7052 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7053 * and set it to a reasonable value instead.
7054 */
ab3c759a 7055 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7056 reg_val &= 0xffffff00;
7057 reg_val |= 0x00000030;
ab3c759a 7058 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7059
ab3c759a 7060 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7061 reg_val &= 0x8cffffff;
7062 reg_val = 0x8c000000;
ab3c759a 7063 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7064
ab3c759a 7065 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7066 reg_val &= 0xffffff00;
ab3c759a 7067 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7068
ab3c759a 7069 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7070 reg_val &= 0x00ffffff;
7071 reg_val |= 0xb0000000;
ab3c759a 7072 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7073}
7074
b551842d
DV		 7075static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7076 struct intel_link_m_n *m_n)
7077{
7078 struct drm_device *dev = crtc->base.dev;
7079 struct drm_i915_private *dev_priv = dev->dev_private;
7080 int pipe = crtc->pipe;
7081
e3b95f1e
DV		 7082 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7083 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7084 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7085 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7086}
7087
7088static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7089 struct intel_link_m_n *m_n,
7090 struct intel_link_m_n *m2_n2)
b551842d
DV		 7091{
7092 struct drm_device *dev = crtc->base.dev;
7093 struct drm_i915_private *dev_priv = dev->dev_private;
7094 int pipe = crtc->pipe;
6e3c9717 7095 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7096
7097 if (INTEL_INFO(dev)->gen >= 5) {
7098 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7099 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7100 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7101 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7102 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7103 * for gen < 8) and if DRRS is supported (to make sure the
7104 * registers are not unnecessarily accessed).
7105 */
44395bfe 7106 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7107 crtc->config->has_drrs) {
f769cd24
VK		 7108 I915_WRITE(PIPE_DATA_M2(transcoder),
7109 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7110 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7111 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7112 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7113 }
b551842d 7114 } else {
e3b95f1e
DV		 7115 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7116 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7117 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7118 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7119 }
7120}
7121
fe3cd48d 7122void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7123{
fe3cd48d
R		 7124 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7125
7126 if (m_n == M1_N1) {
7127 dp_m_n = &crtc->config->dp_m_n;
7128 dp_m2_n2 = &crtc->config->dp_m2_n2;
7129 } else if (m_n == M2_N2) {
7130
7131 /*
7132 * M2_N2 registers are not supported. Hence m2_n2 divider value
7133 * needs to be programmed into M1_N1.
7134 */
7135 dp_m_n = &crtc->config->dp_m2_n2;
7136 } else {
7137 DRM_ERROR("Unsupported divider value\n");
7138 return;
7139 }
7140
6e3c9717
ACO		 7141 if (crtc->config->has_pch_encoder)
7142 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7143 else
fe3cd48d 7144 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7145}
7146
251ac862
DV		 7147static void vlv_compute_dpll(struct intel_crtc *crtc,
7148 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7149{
7150 u32 dpll, dpll_md;
7151
7152 /*
7153 * Enable DPIO clock input. We should never disable the reference
7154 * clock for pipe B, since VGA hotplug / manual detection depends
7155 * on it.
7156 */
60bfe44f
VS		 7157 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7158 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7159 /* We should never disable this, set it here for state tracking */
7160 if (crtc->pipe == PIPE_B)
7161 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7162 dpll |= DPLL_VCO_ENABLE;
d288f65f 7163 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7164
d288f65f 7165 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7166 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7167 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7168}
7169
d288f65f 7170static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7171 const struct intel_crtc_state *pipe_config)
a0c4da24 7172{
f47709a9 7173 struct drm_device *dev = crtc->base.dev;
a0c4da24 7174 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7175 int pipe = crtc->pipe;
bdd4b6a6 7176 u32 mdiv;
a0c4da24 7177 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7178 u32 coreclk, reg_val;
a0c4da24 7179
a580516d 7180 mutex_lock(&dev_priv->sb_lock);
09153000 7181
d288f65f
VS		 7182 bestn = pipe_config->dpll.n;
7183 bestm1 = pipe_config->dpll.m1;
7184 bestm2 = pipe_config->dpll.m2;
7185 bestp1 = pipe_config->dpll.p1;
7186 bestp2 = pipe_config->dpll.p2;
a0c4da24 7187
89b667f8
JB		 7188 /* See eDP HDMI DPIO driver vbios notes doc */
7189
7190 /* PLL B needs special handling */
bdd4b6a6 7191 if (pipe == PIPE_B)
5e69f97f 7192 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7193
7194 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7195 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7196
7197 /* Disable target IRef on PLL */
ab3c759a 7198 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7199 reg_val &= 0x00ffffff;
ab3c759a 7200 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7201
7202 /* Disable fast lock */
ab3c759a 7203 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7204
7205 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7206 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7207 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7208 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7209 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7210
7211 /*
7212 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7213 * but we don't support that).
7214 * Note: don't use the DAC post divider as it seems unstable.
7215 */
7216 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7217 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7218
a0c4da24 7219 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7220 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7221
89b667f8 7222 /* Set HBR and RBR LPF coefficients */
d288f65f 7223 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7224 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7225 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7226 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7227 0x009f0003);
89b667f8 7228 else
ab3c759a 7229 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7230 0x00d0000f);
7231
681a8504 7232 if (pipe_config->has_dp_encoder) {
89b667f8 7233 /* Use SSC source */
bdd4b6a6 7234 if (pipe == PIPE_A)
ab3c759a 7235 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7236 0x0df40000);
7237 else
ab3c759a 7238 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7239 0x0df70000);
7240 } else { /* HDMI or VGA */
7241 /* Use bend source */
bdd4b6a6 7242 if (pipe == PIPE_A)
ab3c759a 7243 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7244 0x0df70000);
7245 else
ab3c759a 7246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7247 0x0df40000);
7248 }
a0c4da24 7249
ab3c759a 7250 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7251 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7252 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7253 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7254 coreclk |= 0x01000000;
ab3c759a 7255 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7256
ab3c759a 7257 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7258 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7259}
7260
251ac862
DV		 7261static void chv_compute_dpll(struct intel_crtc *crtc,
7262 struct intel_crtc_state *pipe_config)
1ae0d137 7263{
60bfe44f
VS		 7264 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7265 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7266 DPLL_VCO_ENABLE;
7267 if (crtc->pipe != PIPE_A)
d288f65f 7268 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7269
d288f65f
VS		 7270 pipe_config->dpll_hw_state.dpll_md =
7271 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7272}
7273
d288f65f 7274static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7275 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7276{
7277 struct drm_device *dev = crtc->base.dev;
7278 struct drm_i915_private *dev_priv = dev->dev_private;
7279 int pipe = crtc->pipe;
7280 int dpll_reg = DPLL(crtc->pipe);
7281 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7282 u32 loopfilter, tribuf_calcntr;
9d556c99 7283 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7284 u32 dpio_val;
9cbe40c1 7285 int vco;
9d556c99 7286
d288f65f
VS		 7287 bestn = pipe_config->dpll.n;
7288 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7289 bestm1 = pipe_config->dpll.m1;
7290 bestm2 = pipe_config->dpll.m2 >> 22;
7291 bestp1 = pipe_config->dpll.p1;
7292 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7293 vco = pipe_config->dpll.vco;
a945ce7e 7294 dpio_val = 0;
9cbe40c1 7295 loopfilter = 0;
9d556c99
CML		 7296
7297 /*
7298 * Enable Refclk and SSC
7299 */
a11b0703 7300 I915_WRITE(dpll_reg,
d288f65f 7301 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7302
a580516d 7303 mutex_lock(&dev_priv->sb_lock);
9d556c99 7304
9d556c99
CML		 7305 /* p1 and p2 divider */
7306 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7307 5 << DPIO_CHV_S1_DIV_SHIFT |
7308 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7309 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7310 1 << DPIO_CHV_K_DIV_SHIFT);
7311
7312 /* Feedback post-divider - m2 */
7313 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7314
7315 /* Feedback refclk divider - n and m1 */
7316 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7317 DPIO_CHV_M1_DIV_BY_2 |
7318 1 << DPIO_CHV_N_DIV_SHIFT);
7319
7320 /* M2 fraction division */
25a25dfc 7321 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7322
7323 /* M2 fraction division enable */
a945ce7e
VP		 7324 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7325 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7326 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7327 if (bestm2_frac)
7328 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7329 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7330
de3a0fde
VP		 7331 /* Program digital lock detect threshold */
7332 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7333 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7334 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7335 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7336 if (!bestm2_frac)
7337 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7338 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7339
9d556c99 7340 /* Loop filter */
9cbe40c1
VP		 7341 if (vco == 5400000) {
7342 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7343 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7344 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7345 tribuf_calcntr = 0x9;
7346 } else if (vco <= 6200000) {
7347 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7348 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7349 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7350 tribuf_calcntr = 0x9;
7351 } else if (vco <= 6480000) {
7352 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7353 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7354 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7355 tribuf_calcntr = 0x8;
7356 } else {
7357 /* Not supported. Apply the same limits as in the max case */
7358 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7359 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7360 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7361 tribuf_calcntr = 0;
7362 }
9d556c99
CML		 7363 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7364
968040b2 7365 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7366 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7367 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7369
9d556c99
CML		 7370 /* AFC Recal */
7371 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7372 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7373 DPIO_AFC_RECAL);
7374
a580516d 7375 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7376}
7377
d288f65f
VS		 7378/**
7379 * vlv_force_pll_on - forcibly enable just the PLL
7380 * @dev_priv: i915 private structure
7381 * @pipe: pipe PLL to enable
7382 * @dpll: PLL configuration
7383 *
7384 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7385 * in cases where we need the PLL enabled even when @pipe is not going to
7386 * be enabled.
7387 */
7388void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7389 const struct dpll *dpll)
7390{
7391 struct intel_crtc *crtc =
7392 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7393 struct intel_crtc_state pipe_config = {
a93e255f 7394 .base.crtc = &crtc->base,
d288f65f
VS		 7395 .pixel_multiplier = 1,
7396 .dpll = *dpll,
7397 };
7398
7399 if (IS_CHERRYVIEW(dev)) {
251ac862 7400 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7401 chv_prepare_pll(crtc, &pipe_config);
7402 chv_enable_pll(crtc, &pipe_config);
7403 } else {
251ac862 7404 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7405 vlv_prepare_pll(crtc, &pipe_config);
7406 vlv_enable_pll(crtc, &pipe_config);
7407 }
7408}
7409
7410/**
7411 * vlv_force_pll_off - forcibly disable just the PLL
7412 * @dev_priv: i915 private structure
7413 * @pipe: pipe PLL to disable
7414 *
7415 * Disable the PLL for @pipe. To be used in cases where we need
7416 * the PLL enabled even when @pipe is not going to be enabled.
7417 */
7418void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7419{
7420 if (IS_CHERRYVIEW(dev))
7421 chv_disable_pll(to_i915(dev), pipe);
7422 else
7423 vlv_disable_pll(to_i915(dev), pipe);
7424}
7425
251ac862
DV		 7426static void i9xx_compute_dpll(struct intel_crtc *crtc,
7427 struct intel_crtc_state *crtc_state,
7428 intel_clock_t *reduced_clock,
7429 int num_connectors)
eb1cbe48 7430{
f47709a9 7431 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7432 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7433 u32 dpll;
7434 bool is_sdvo;
190f68c5 7435 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7436
190f68c5 7437 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7438
a93e255f
ACO		 7439 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7440 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7441
7442 dpll = DPLL_VGA_MODE_DIS;
7443
a93e255f 7444 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7445 dpll |= DPLLB_MODE_LVDS;
7446 else
7447 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7448
ef1b460d 7449 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7450 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7451 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7452 }
198a037f
DV		 7453
7454 if (is_sdvo)
4a33e48d 7455 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7456
190f68c5 7457 if (crtc_state->has_dp_encoder)
4a33e48d 7458 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7459
7460 /* compute bitmask from p1 value */
7461 if (IS_PINEVIEW(dev))
7462 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7463 else {
7464 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7465 if (IS_G4X(dev) && reduced_clock)
7466 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7467 }
7468 switch (clock->p2) {
7469 case 5:
7470 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7471 break;
7472 case 7:
7473 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7474 break;
7475 case 10:
7476 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7477 break;
7478 case 14:
7479 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7480 break;
7481 }
7482 if (INTEL_INFO(dev)->gen >= 4)
7483 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7484
190f68c5 7485 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7486 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7487 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7488 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7489 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7490 else
7491 dpll |= PLL_REF_INPUT_DREFCLK;
7492
7493 dpll |= DPLL_VCO_ENABLE;
190f68c5 7494 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7495
eb1cbe48 7496 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7497 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7498 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7499 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7500 }
7501}
7502
251ac862
DV		 7503static void i8xx_compute_dpll(struct intel_crtc *crtc,
7504 struct intel_crtc_state *crtc_state,
7505 intel_clock_t *reduced_clock,
7506 int num_connectors)
eb1cbe48 7507{
f47709a9 7508 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7509 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7510 u32 dpll;
190f68c5 7511 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7512
190f68c5 7513 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7514
eb1cbe48
DV		 7515 dpll = DPLL_VGA_MODE_DIS;
7516
a93e255f 7517 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7518 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7519 } else {
7520 if (clock->p1 == 2)
7521 dpll |= PLL_P1_DIVIDE_BY_TWO;
7522 else
7523 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7524 if (clock->p2 == 4)
7525 dpll |= PLL_P2_DIVIDE_BY_4;
7526 }
7527
a93e255f 7528 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7529 dpll |= DPLL_DVO_2X_MODE;
7530
a93e255f 7531 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7532 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7533 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7534 else
7535 dpll |= PLL_REF_INPUT_DREFCLK;
7536
7537 dpll |= DPLL_VCO_ENABLE;
190f68c5 7538 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7539}
7540
8a654f3b 7541static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7542{
7543 struct drm_device *dev = intel_crtc->base.dev;
7544 struct drm_i915_private *dev_priv = dev->dev_private;
7545 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7546 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7547 struct drm_display_mode *adjusted_mode =
6e3c9717 7548 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7549 uint32_t crtc_vtotal, crtc_vblank_end;
7550 int vsyncshift = 0;
4d8a62ea
DV		 7551
7552 /* We need to be careful not to changed the adjusted mode, for otherwise
7553 * the hw state checker will get angry at the mismatch. */
7554 crtc_vtotal = adjusted_mode->crtc_vtotal;
7555 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7556
609aeaca 7557 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7558 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7559 crtc_vtotal -= 1;
7560 crtc_vblank_end -= 1;
609aeaca 7561
409ee761 7562 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7563 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7564 else
7565 vsyncshift = adjusted_mode->crtc_hsync_start -
7566 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7567 if (vsyncshift < 0)
7568 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7569 }
7570
7571 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7572 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7573
fe2b8f9d 7574 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7575 (adjusted_mode->crtc_hdisplay - 1) |
7576 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7577 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7578 (adjusted_mode->crtc_hblank_start - 1) |
7579 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7580 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7581 (adjusted_mode->crtc_hsync_start - 1) |
7582 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7583
fe2b8f9d 7584 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7585 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7586 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7587 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7588 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7589 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7590 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7591 (adjusted_mode->crtc_vsync_start - 1) |
7592 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7593
b5e508d4
PZ		 7594 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7595 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7596 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7597 * bits. */
7598 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7599 (pipe == PIPE_B || pipe == PIPE_C))
7600 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7601
b0e77b9c
PZ		 7602 /* pipesrc controls the size that is scaled from, which should
7603 * always be the user's requested size.
7604 */
7605 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7606 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7607 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7608}
7609
1bd1bd80 7610static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7611 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7612{
7613 struct drm_device *dev = crtc->base.dev;
7614 struct drm_i915_private *dev_priv = dev->dev_private;
7615 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7616 uint32_t tmp;
7617
7618 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7619 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7620 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7621 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7622 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7623 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7624 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7625 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7626 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7627
7628 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7629 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7630 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7631 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7632 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7633 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7634 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7635 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7636 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7637
7638 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7639 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7640 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7641 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7642 }
7643
7644 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7645 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7646 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7647
2d112de7
ACO		 7648 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7649 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7650}
7651
f6a83288 7652void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7653 struct intel_crtc_state *pipe_config)
babea61d 7654{
2d112de7
ACO		 7655 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7656 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7657 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7658 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7659
2d112de7
ACO		 7660 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7661 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7662 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7663 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7664
2d112de7 7665 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7666 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7667
2d112de7
ACO		 7668 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7669 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7670
7671 mode->hsync = drm_mode_hsync(mode);
7672 mode->vrefresh = drm_mode_vrefresh(mode);
7673 drm_mode_set_name(mode);
babea61d
JB		 7674}
7675
84b046f3
DV		 7676static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7677{
7678 struct drm_device *dev = intel_crtc->base.dev;
7679 struct drm_i915_private *dev_priv = dev->dev_private;
7680 uint32_t pipeconf;
7681
9f11a9e4 7682 pipeconf = 0;
84b046f3 7683
b6b5d049
VS		 7684 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7685 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7686 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7687
6e3c9717 7688 if (intel_crtc->config->double_wide)
cf532bb2 7689 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7690
ff9ce46e
DV		 7691 /* only g4x and later have fancy bpc/dither controls */
7692 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7693 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7694 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7695 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7696 PIPECONF_DITHER_TYPE_SP;
84b046f3 7697
6e3c9717 7698 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7699 case 18:
7700 pipeconf |= PIPECONF_6BPC;
7701 break;
7702 case 24:
7703 pipeconf |= PIPECONF_8BPC;
7704 break;
7705 case 30:
7706 pipeconf |= PIPECONF_10BPC;
7707 break;
7708 default:
7709 /* Case prevented by intel_choose_pipe_bpp_dither. */
7710 BUG();
84b046f3
DV		 7711 }
7712 }
7713
7714 if (HAS_PIPE_CXSR(dev)) {
7715 if (intel_crtc->lowfreq_avail) {
7716 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7717 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7718 } else {
7719 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7720 }
7721 }
7722
6e3c9717 7723 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7724 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7725 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7726 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7727 else
7728 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7729 } else
84b046f3
DV		 7730 pipeconf |= PIPECONF_PROGRESSIVE;
7731
6e3c9717 7732 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7733 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7734
84b046f3
DV		 7735 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7736 POSTING_READ(PIPECONF(intel_crtc->pipe));
7737}
7738
190f68c5
ACO		 7739static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7740 struct intel_crtc_state *crtc_state)
79e53945 7741{
c7653199 7742 struct drm_device *dev = crtc->base.dev;
79e53945 7743 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7744 int refclk, num_connectors = 0;
c329a4ec
DV		 7745 intel_clock_t clock;
7746 bool ok;
7747 bool is_dsi = false;
5eddb70b 7748 struct intel_encoder *encoder;
d4906093 7749 const intel_limit_t *limit;
55bb9992 7750 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7751 struct drm_connector *connector;
55bb9992
ACO		 7752 struct drm_connector_state *connector_state;
7753 int i;
79e53945 7754
dd3cd74a
ACO		 7755 memset(&crtc_state->dpll_hw_state, 0,
7756 sizeof(crtc_state->dpll_hw_state));
7757
da3ced29 7758 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7759 if (connector_state->crtc != &crtc->base)
7760 continue;
7761
7762 encoder = to_intel_encoder(connector_state->best_encoder);
7763
5eddb70b 7764 switch (encoder->type) {
e9fd1c02
JN		 7765 case INTEL_OUTPUT_DSI:
7766 is_dsi = true;
7767 break;
6847d71b
PZ		 7768 default:
7769 break;
79e53945 7770 }
43565a06 7771
c751ce4f 7772 num_connectors++;
79e53945
JB		 7773 }
7774
f2335330 7775 if (is_dsi)
5b18e57c 7776 return 0;
f2335330 7777
190f68c5 7778 if (!crtc_state->clock_set) {
a93e255f 7779 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7780
e9fd1c02
JN		 7781 /*
7782 * Returns a set of divisors for the desired target clock with
7783 * the given refclk, or FALSE. The returned values represent
7784 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7785 * 2) / p1 / p2.
7786 */
a93e255f
ACO		 7787 limit = intel_limit(crtc_state, refclk);
7788 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7789 crtc_state->port_clock,
e9fd1c02 7790 refclk, NULL, &clock);
f2335330 7791 if (!ok) {
e9fd1c02
JN		 7792 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7793 return -EINVAL;
7794 }
79e53945 7795
f2335330 7796 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7797 crtc_state->dpll.n = clock.n;
7798 crtc_state->dpll.m1 = clock.m1;
7799 crtc_state->dpll.m2 = clock.m2;
7800 crtc_state->dpll.p1 = clock.p1;
7801 crtc_state->dpll.p2 = clock.p2;
f47709a9 7802 }
7026d4ac 7803
e9fd1c02 7804 if (IS_GEN2(dev)) {
c329a4ec 7805 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7806 num_connectors);
9d556c99 7807 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7808 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7809 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7810 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7811 } else {
c329a4ec 7812 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7813 num_connectors);
e9fd1c02 7814 }
79e53945 7815
c8f7a0db 7816 return 0;
f564048e
EA		 7817}
7818
2fa2fe9a 7819static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7820 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7821{
7822 struct drm_device *dev = crtc->base.dev;
7823 struct drm_i915_private *dev_priv = dev->dev_private;
7824 uint32_t tmp;
7825
dc9e7dec
VS		 7826 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7827 return;
7828
2fa2fe9a 7829 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7830 if (!(tmp & PFIT_ENABLE))
7831 return;
2fa2fe9a 7832
06922821 7833 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7834 if (INTEL_INFO(dev)->gen < 4) {
7835 if (crtc->pipe != PIPE_B)
7836 return;
2fa2fe9a
DV		 7837 } else {
7838 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7839 return;
7840 }
7841
06922821 7842 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7843 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7844 if (INTEL_INFO(dev)->gen < 5)
7845 pipe_config->gmch_pfit.lvds_border_bits =
7846 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7847}
7848
acbec814 7849static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7850 struct intel_crtc_state *pipe_config)
acbec814
JB		 7851{
7852 struct drm_device *dev = crtc->base.dev;
7853 struct drm_i915_private *dev_priv = dev->dev_private;
7854 int pipe = pipe_config->cpu_transcoder;
7855 intel_clock_t clock;
7856 u32 mdiv;
662c6ecb 7857 int refclk = 100000;
acbec814 7858
f573de5a
SK		 7859 /* In case of MIPI DPLL will not even be used */
7860 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7861 return;
7862
a580516d 7863 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7864 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7865 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7866
7867 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7868 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7869 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7870 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7871 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7872
dccbea3b 7873 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7874}
7875
5724dbd1
DL		 7876static void
7877i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7878 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7879{
7880 struct drm_device *dev = crtc->base.dev;
7881 struct drm_i915_private *dev_priv = dev->dev_private;
7882 u32 val, base, offset;
7883 int pipe = crtc->pipe, plane = crtc->plane;
7884 int fourcc, pixel_format;
6761dd31 7885 unsigned int aligned_height;
b113d5ee 7886 struct drm_framebuffer *fb;
1b842c89 7887 struct intel_framebuffer *intel_fb;
1ad292b5 7888
42a7b088
DL		 7889 val = I915_READ(DSPCNTR(plane));
7890 if (!(val & DISPLAY_PLANE_ENABLE))
7891 return;
7892
d9806c9f 7893 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7894 if (!intel_fb) {
1ad292b5
JB		 7895 DRM_DEBUG_KMS("failed to alloc fb\n");
7896 return;
7897 }
7898
1b842c89
DL		 7899 fb = &intel_fb->base;
7900
18c5247e
DV		 7901 if (INTEL_INFO(dev)->gen >= 4) {
7902 if (val & DISPPLANE_TILED) {
49af449b 7903 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7904 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7905 }
7906 }
1ad292b5
JB		 7907
7908 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7909 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7910 fb->pixel_format = fourcc;
7911 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7912
7913 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7914 if (plane_config->tiling)
1ad292b5
JB		 7915 offset = I915_READ(DSPTILEOFF(plane));
7916 else
7917 offset = I915_READ(DSPLINOFF(plane));
7918 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7919 } else {
7920 base = I915_READ(DSPADDR(plane));
7921 }
7922 plane_config->base = base;
7923
7924 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7925 fb->width = ((val >> 16) & 0xfff) + 1;
7926 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7927
7928 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7929 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7930
b113d5ee 7931 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7932 fb->pixel_format,
7933 fb->modifier[0]);
1ad292b5 7934
f37b5c2b 7935 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7936
2844a921
DL		 7937 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7938 pipe_name(pipe), plane, fb->width, fb->height,
7939 fb->bits_per_pixel, base, fb->pitches[0],
7940 plane_config->size);
1ad292b5 7941
2d14030b 7942 plane_config->fb = intel_fb;
1ad292b5
JB		 7943}
7944
70b23a98 7945static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7946 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7947{
7948 struct drm_device *dev = crtc->base.dev;
7949 struct drm_i915_private *dev_priv = dev->dev_private;
7950 int pipe = pipe_config->cpu_transcoder;
7951 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7952 intel_clock_t clock;
0d7b6b11 7953 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 7954 int refclk = 100000;
7955
a580516d 7956 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 7957 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7958 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7959 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7960 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 7961 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 7962 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 7963
7964 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 7965 clock.m2 = (pll_dw0 & 0xff) << 22;
7966 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7967 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 7968 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7969 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7970 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7971
dccbea3b 7972 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 7973}
7974
0e8ffe1b 7975static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7976 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7977{
7978 struct drm_device *dev = crtc->base.dev;
7979 struct drm_i915_private *dev_priv = dev->dev_private;
7980 uint32_t tmp;
7981
f458ebbc
DV		 7982 if (!intel_display_power_is_enabled(dev_priv,
7983 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7984 return false;
7985
e143a21c 7986 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7987 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7988
0e8ffe1b
DV		 7989 tmp = I915_READ(PIPECONF(crtc->pipe));
7990 if (!(tmp & PIPECONF_ENABLE))
7991 return false;
7992
42571aef
VS		 7993 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7994 switch (tmp & PIPECONF_BPC_MASK) {
7995 case PIPECONF_6BPC:
7996 pipe_config->pipe_bpp = 18;
7997 break;
7998 case PIPECONF_8BPC:
7999 pipe_config->pipe_bpp = 24;
8000 break;
8001 case PIPECONF_10BPC:
8002 pipe_config->pipe_bpp = 30;
8003 break;
8004 default:
8005 break;
8006 }
8007 }
8008
b5a9fa09
DV		 8009 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8010 pipe_config->limited_color_range = true;
8011
282740f7
VS		 8012 if (INTEL_INFO(dev)->gen < 4)
8013 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8014
1bd1bd80
DV		 8015 intel_get_pipe_timings(crtc, pipe_config);
8016
2fa2fe9a
DV		 8017 i9xx_get_pfit_config(crtc, pipe_config);
8018
6c49f241
DV		 8019 if (INTEL_INFO(dev)->gen >= 4) {
8020 tmp = I915_READ(DPLL_MD(crtc->pipe));
8021 pipe_config->pixel_multiplier =
8022 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8023 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8024 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8025 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8026 tmp = I915_READ(DPLL(crtc->pipe));
8027 pipe_config->pixel_multiplier =
8028 ((tmp & SDVO_MULTIPLIER_MASK)
8029 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8030 } else {
8031 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8032 * port and will be fixed up in the encoder->get_config
8033 * function. */
8034 pipe_config->pixel_multiplier = 1;
8035 }
8bcc2795
DV		 8036 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8037 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8038 /*
8039 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8040 * on 830. Filter it out here so that we don't
8041 * report errors due to that.
8042 */
8043 if (IS_I830(dev))
8044 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8045
8bcc2795
DV		 8046 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8047 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8048 } else {
8049 /* Mask out read-only status bits. */
8050 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8051 DPLL_PORTC_READY_MASK |
8052 DPLL_PORTB_READY_MASK);
8bcc2795 8053 }
6c49f241 8054
70b23a98
VS		 8055 if (IS_CHERRYVIEW(dev))
8056 chv_crtc_clock_get(crtc, pipe_config);
8057 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8058 vlv_crtc_clock_get(crtc, pipe_config);
8059 else
8060 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8061
0f64614d
VS		 8062 /*
8063 * Normally the dotclock is filled in by the encoder .get_config()
8064 * but in case the pipe is enabled w/o any ports we need a sane
8065 * default.
8066 */
8067 pipe_config->base.adjusted_mode.crtc_clock =
8068 pipe_config->port_clock / pipe_config->pixel_multiplier;
8069
0e8ffe1b
DV		 8070 return true;
8071}
8072
dde86e2d 8073static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8074{
8075 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8076 struct intel_encoder *encoder;
74cfd7ac 8077 u32 val, final;
13d83a67 8078 bool has_lvds = false;
199e5d79 8079 bool has_cpu_edp = false;
199e5d79 8080 bool has_panel = false;
99eb6a01
KP		 8081 bool has_ck505 = false;
8082 bool can_ssc = false;
13d83a67
JB		 8083
8084 /* We need to take the global config into account */
b2784e15 8085 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8086 switch (encoder->type) {
8087 case INTEL_OUTPUT_LVDS:
8088 has_panel = true;
8089 has_lvds = true;
8090 break;
8091 case INTEL_OUTPUT_EDP:
8092 has_panel = true;
2de6905f 8093 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8094 has_cpu_edp = true;
8095 break;
6847d71b
PZ		 8096 default:
8097 break;
13d83a67
JB		 8098 }
8099 }
8100
99eb6a01 8101 if (HAS_PCH_IBX(dev)) {
41aa3448 8102 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8103 can_ssc = has_ck505;
8104 } else {
8105 has_ck505 = false;
8106 can_ssc = true;
8107 }
8108
2de6905f
ID		 8109 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8110 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8111
8112 /* Ironlake: try to setup display ref clock before DPLL
8113 * enabling. This is only under driver's control after
8114 * PCH B stepping, previous chipset stepping should be
8115 * ignoring this setting.
8116 */
74cfd7ac
CW		 8117 val = I915_READ(PCH_DREF_CONTROL);
8118
8119 /* As we must carefully and slowly disable/enable each source in turn,
8120 * compute the final state we want first and check if we need to
8121 * make any changes at all.
8122 */
8123 final = val;
8124 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8125 if (has_ck505)
8126 final |= DREF_NONSPREAD_CK505_ENABLE;
8127 else
8128 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8129
8130 final &= ~DREF_SSC_SOURCE_MASK;
8131 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8132 final &= ~DREF_SSC1_ENABLE;
8133
8134 if (has_panel) {
8135 final |= DREF_SSC_SOURCE_ENABLE;
8136
8137 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8138 final |= DREF_SSC1_ENABLE;
8139
8140 if (has_cpu_edp) {
8141 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8142 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8143 else
8144 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8145 } else
8146 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8147 } else {
8148 final |= DREF_SSC_SOURCE_DISABLE;
8149 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8150 }
8151
8152 if (final == val)
8153 return;
8154
13d83a67 8155 /* Always enable nonspread source */
74cfd7ac 8156 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8157
99eb6a01 8158 if (has_ck505)
74cfd7ac 8159 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8160 else
74cfd7ac 8161 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8162
199e5d79 8163 if (has_panel) {
74cfd7ac
CW		 8164 val &= ~DREF_SSC_SOURCE_MASK;
8165 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8166
199e5d79 8167 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8168 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8169 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8170 val |= DREF_SSC1_ENABLE;
e77166b5 8171 } else
74cfd7ac 8172 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8173
8174 /* Get SSC going before enabling the outputs */
74cfd7ac 8175 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8176 POSTING_READ(PCH_DREF_CONTROL);
8177 udelay(200);
8178
74cfd7ac 8179 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8180
8181 /* Enable CPU source on CPU attached eDP */
199e5d79 8182 if (has_cpu_edp) {
99eb6a01 8183 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8184 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8185 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8186 } else
74cfd7ac 8187 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8188 } else
74cfd7ac 8189 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8190
74cfd7ac 8191 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8192 POSTING_READ(PCH_DREF_CONTROL);
8193 udelay(200);
8194 } else {
8195 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8196
74cfd7ac 8197 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8198
8199 /* Turn off CPU output */
74cfd7ac 8200 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8201
74cfd7ac 8202 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8203 POSTING_READ(PCH_DREF_CONTROL);
8204 udelay(200);
8205
8206 /* Turn off the SSC source */
74cfd7ac
CW		 8207 val &= ~DREF_SSC_SOURCE_MASK;
8208 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8209
8210 /* Turn off SSC1 */
74cfd7ac 8211 val &= ~DREF_SSC1_ENABLE;
199e5d79 8212
74cfd7ac 8213 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8214 POSTING_READ(PCH_DREF_CONTROL);
8215 udelay(200);
8216 }
74cfd7ac
CW		 8217
8218 BUG_ON(val != final);
13d83a67
JB		 8219}
8220
f31f2d55 8221static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8222{
f31f2d55 8223 uint32_t tmp;
dde86e2d 8224
0ff066a9
PZ		 8225 tmp = I915_READ(SOUTH_CHICKEN2);
8226 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8227 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8228
0ff066a9
PZ		 8229 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8230 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8231 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8232
0ff066a9
PZ		 8233 tmp = I915_READ(SOUTH_CHICKEN2);
8234 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8235 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8236
0ff066a9
PZ		 8237 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8238 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8239 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8240}
8241
8242/* WaMPhyProgramming:hsw */
8243static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8244{
8245 uint32_t tmp;
dde86e2d
PZ		 8246
8247 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8248 tmp &= ~(0xFF << 24);
8249 tmp |= (0x12 << 24);
8250 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8251
dde86e2d
PZ		 8252 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8253 tmp |= (1 << 11);
8254 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8255
8256 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8257 tmp |= (1 << 11);
8258 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8259
dde86e2d
PZ		 8260 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8261 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8262 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8263
8264 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8265 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8266 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8267
0ff066a9
PZ		 8268 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8269 tmp &= ~(7 << 13);
8270 tmp |= (5 << 13);
8271 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8272
0ff066a9
PZ		 8273 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8274 tmp &= ~(7 << 13);
8275 tmp |= (5 << 13);
8276 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8277
8278 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8279 tmp &= ~0xFF;
8280 tmp |= 0x1C;
8281 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8282
8283 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8284 tmp &= ~0xFF;
8285 tmp |= 0x1C;
8286 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8287
8288 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8289 tmp &= ~(0xFF << 16);
8290 tmp |= (0x1C << 16);
8291 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8292
8293 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8294 tmp &= ~(0xFF << 16);
8295 tmp |= (0x1C << 16);
8296 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8297
0ff066a9
PZ		 8298 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8299 tmp |= (1 << 27);
8300 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8301
0ff066a9
PZ		 8302 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8303 tmp |= (1 << 27);
8304 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8305
0ff066a9
PZ		 8306 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8307 tmp &= ~(0xF << 28);
8308 tmp |= (4 << 28);
8309 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8310
0ff066a9
PZ		 8311 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8312 tmp &= ~(0xF << 28);
8313 tmp |= (4 << 28);
8314 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8315}
8316
2fa86a1f
PZ		 8317/* Implements 3 different sequences from BSpec chapter "Display iCLK
8318 * Programming" based on the parameters passed:
8319 * - Sequence to enable CLKOUT_DP
8320 * - Sequence to enable CLKOUT_DP without spread
8321 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8322 */
8323static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8324 bool with_fdi)
f31f2d55
PZ		 8325{
8326 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8327 uint32_t reg, tmp;
8328
8329 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8330 with_spread = true;
8331 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8332 with_fdi, "LP PCH doesn't have FDI\n"))
8333 with_fdi = false;
f31f2d55 8334
a580516d 8335 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8336
8337 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8338 tmp &= ~SBI_SSCCTL_DISABLE;
8339 tmp |= SBI_SSCCTL_PATHALT;
8340 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8341
8342 udelay(24);
8343
2fa86a1f
PZ		 8344 if (with_spread) {
8345 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8346 tmp &= ~SBI_SSCCTL_PATHALT;
8347 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8348
2fa86a1f
PZ		 8349 if (with_fdi) {
8350 lpt_reset_fdi_mphy(dev_priv);
8351 lpt_program_fdi_mphy(dev_priv);
8352 }
8353 }
dde86e2d 8354
2fa86a1f
PZ		 8355 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8356 SBI_GEN0 : SBI_DBUFF0;
8357 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8358 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8359 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8360
a580516d 8361 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8362}
8363
47701c3b
PZ		 8364/* Sequence to disable CLKOUT_DP */
8365static void lpt_disable_clkout_dp(struct drm_device *dev)
8366{
8367 struct drm_i915_private *dev_priv = dev->dev_private;
8368 uint32_t reg, tmp;
8369
a580516d 8370 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8371
8372 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8373 SBI_GEN0 : SBI_DBUFF0;
8374 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8375 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8376 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8377
8378 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8379 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8380 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8381 tmp |= SBI_SSCCTL_PATHALT;
8382 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8383 udelay(32);
8384 }
8385 tmp |= SBI_SSCCTL_DISABLE;
8386 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8387 }
8388
a580516d 8389 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8390}
8391
bf8fa3d3
PZ		 8392static void lpt_init_pch_refclk(struct drm_device *dev)
8393{
bf8fa3d3
PZ		 8394 struct intel_encoder *encoder;
8395 bool has_vga = false;
8396
b2784e15 8397 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8398 switch (encoder->type) {
8399 case INTEL_OUTPUT_ANALOG:
8400 has_vga = true;
8401 break;
6847d71b
PZ		 8402 default:
8403 break;
bf8fa3d3
PZ		 8404 }
8405 }
8406
47701c3b
PZ		 8407 if (has_vga)
8408 lpt_enable_clkout_dp(dev, true, true);
8409 else
8410 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8411}
8412
dde86e2d
PZ		 8413/*
8414 * Initialize reference clocks when the driver loads
8415 */
8416void intel_init_pch_refclk(struct drm_device *dev)
8417{
8418 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8419 ironlake_init_pch_refclk(dev);
8420 else if (HAS_PCH_LPT(dev))
8421 lpt_init_pch_refclk(dev);
8422}
8423
55bb9992 8424static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8425{
55bb9992 8426 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8427 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8428 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8429 struct drm_connector *connector;
55bb9992 8430 struct drm_connector_state *connector_state;
d9d444cb 8431 struct intel_encoder *encoder;
55bb9992 8432 int num_connectors = 0, i;
d9d444cb
JB		 8433 bool is_lvds = false;
8434
da3ced29 8435 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8436 if (connector_state->crtc != crtc_state->base.crtc)
8437 continue;
8438
8439 encoder = to_intel_encoder(connector_state->best_encoder);
8440
d9d444cb
JB		 8441 switch (encoder->type) {
8442 case INTEL_OUTPUT_LVDS:
8443 is_lvds = true;
8444 break;
6847d71b
PZ		 8445 default:
8446 break;
d9d444cb
JB		 8447 }
8448 num_connectors++;
8449 }
8450
8451 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8452 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8453 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8454 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8455 }
8456
8457 return 120000;
8458}
8459
6ff93609 8460static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8461{
c8203565 8462 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8464 int pipe = intel_crtc->pipe;
c8203565
PZ		 8465 uint32_t val;
8466
78114071 8467 val = 0;
c8203565 8468
6e3c9717 8469 switch (intel_crtc->config->pipe_bpp) {
c8203565 8470 case 18:
dfd07d72 8471 val |= PIPECONF_6BPC;
c8203565
PZ		 8472 break;
8473 case 24:
dfd07d72 8474 val |= PIPECONF_8BPC;
c8203565
PZ		 8475 break;
8476 case 30:
dfd07d72 8477 val |= PIPECONF_10BPC;
c8203565
PZ		 8478 break;
8479 case 36:
dfd07d72 8480 val |= PIPECONF_12BPC;
c8203565
PZ		 8481 break;
8482 default:
cc769b62
PZ		 8483 /* Case prevented by intel_choose_pipe_bpp_dither. */
8484 BUG();
c8203565
PZ		 8485 }
8486
6e3c9717 8487 if (intel_crtc->config->dither)
c8203565
PZ		 8488 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8489
6e3c9717 8490 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8491 val |= PIPECONF_INTERLACED_ILK;
8492 else
8493 val |= PIPECONF_PROGRESSIVE;
8494
6e3c9717 8495 if (intel_crtc->config->limited_color_range)
3685a8f3 8496 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8497
c8203565
PZ		 8498 I915_WRITE(PIPECONF(pipe), val);
8499 POSTING_READ(PIPECONF(pipe));
8500}
8501
86d3efce
VS		 8502/*
8503 * Set up the pipe CSC unit.
8504 *
8505 * Currently only full range RGB to limited range RGB conversion
8506 * is supported, but eventually this should handle various
8507 * RGB<->YCbCr scenarios as well.
8508 */
50f3b016 8509static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8510{
8511 struct drm_device *dev = crtc->dev;
8512 struct drm_i915_private *dev_priv = dev->dev_private;
8513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8514 int pipe = intel_crtc->pipe;
8515 uint16_t coeff = 0x7800; /* 1.0 */
8516
8517 /*
8518 * TODO: Check what kind of values actually come out of the pipe
8519 * with these coeff/postoff values and adjust to get the best
8520 * accuracy. Perhaps we even need to take the bpc value into
8521 * consideration.
8522 */
8523
6e3c9717 8524 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8525 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8526
8527 /*
8528 * GY/GU and RY/RU should be the other way around according
8529 * to BSpec, but reality doesn't agree. Just set them up in
8530 * a way that results in the correct picture.
8531 */
8532 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8533 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8534
8535 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8536 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8537
8538 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8539 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8540
8541 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8542 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8543 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8544
8545 if (INTEL_INFO(dev)->gen > 6) {
8546 uint16_t postoff = 0;
8547
6e3c9717 8548 if (intel_crtc->config->limited_color_range)
32cf0cb0 8549 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8550
8551 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8552 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8553 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8554
8555 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8556 } else {
8557 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8558
6e3c9717 8559 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8560 mode |= CSC_BLACK_SCREEN_OFFSET;
8561
8562 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8563 }
8564}
8565
6ff93609 8566static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8567{
756f85cf
PZ		 8568 struct drm_device *dev = crtc->dev;
8569 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8571 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8572 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8573 uint32_t val;
8574
3eff4faa 8575 val = 0;
ee2b0b38 8576
6e3c9717 8577 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8578 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8579
6e3c9717 8580 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8581 val |= PIPECONF_INTERLACED_ILK;
8582 else
8583 val |= PIPECONF_PROGRESSIVE;
8584
702e7a56
PZ		 8585 I915_WRITE(PIPECONF(cpu_transcoder), val);
8586 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8587
8588 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8589 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8590
3cdf122c 8591 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8592 val = 0;
8593
6e3c9717 8594 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8595 case 18:
8596 val |= PIPEMISC_DITHER_6_BPC;
8597 break;
8598 case 24:
8599 val |= PIPEMISC_DITHER_8_BPC;
8600 break;
8601 case 30:
8602 val |= PIPEMISC_DITHER_10_BPC;
8603 break;
8604 case 36:
8605 val |= PIPEMISC_DITHER_12_BPC;
8606 break;
8607 default:
8608 /* Case prevented by pipe_config_set_bpp. */
8609 BUG();
8610 }
8611
6e3c9717 8612 if (intel_crtc->config->dither)
756f85cf
PZ		 8613 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8614
8615 I915_WRITE(PIPEMISC(pipe), val);
8616 }
ee2b0b38
PZ		 8617}
8618
6591c6e4 8619static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8620 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8621 intel_clock_t *clock,
8622 bool *has_reduced_clock,
8623 intel_clock_t *reduced_clock)
8624{
8625 struct drm_device *dev = crtc->dev;
8626 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8627 int refclk;
d4906093 8628 const intel_limit_t *limit;
c329a4ec 8629 bool ret;
79e53945 8630
55bb9992 8631 refclk = ironlake_get_refclk(crtc_state);
79e53945 8632
d4906093
ML		 8633 /*
8634 * Returns a set of divisors for the desired target clock with the given
8635 * refclk, or FALSE. The returned values represent the clock equation:
8636 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8637 */
a93e255f
ACO		 8638 limit = intel_limit(crtc_state, refclk);
8639 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8640 crtc_state->port_clock,
ee9300bb 8641 refclk, NULL, clock);
6591c6e4
PZ		 8642 if (!ret)
8643 return false;
cda4b7d3 8644
6591c6e4
PZ		 8645 return true;
8646}
8647
d4b1931c
PZ		 8648int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8649{
8650 /*
8651 * Account for spread spectrum to avoid
8652 * oversubscribing the link. Max center spread
8653 * is 2.5%; use 5% for safety's sake.
8654 */
8655 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8656 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8657}
8658
7429e9d4 8659static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8660{
7429e9d4 8661 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8662}
8663
de13a2e3 8664static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8665 struct intel_crtc_state *crtc_state,
7429e9d4 8666 u32 *fp,
9a7c7890 8667 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8668{
de13a2e3 8669 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8670 struct drm_device *dev = crtc->dev;
8671 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8672 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8673 struct drm_connector *connector;
55bb9992
ACO		 8674 struct drm_connector_state *connector_state;
8675 struct intel_encoder *encoder;
de13a2e3 8676 uint32_t dpll;
55bb9992 8677 int factor, num_connectors = 0, i;
09ede541 8678 bool is_lvds = false, is_sdvo = false;
79e53945 8679
da3ced29 8680 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8681 if (connector_state->crtc != crtc_state->base.crtc)
8682 continue;
8683
8684 encoder = to_intel_encoder(connector_state->best_encoder);
8685
8686 switch (encoder->type) {
79e53945
JB		 8687 case INTEL_OUTPUT_LVDS:
8688 is_lvds = true;
8689 break;
8690 case INTEL_OUTPUT_SDVO:
7d57382e 8691 case INTEL_OUTPUT_HDMI:
79e53945 8692 is_sdvo = true;
79e53945 8693 break;
6847d71b
PZ		 8694 default:
8695 break;
79e53945 8696 }
43565a06 8697
c751ce4f 8698 num_connectors++;
79e53945 8699 }
79e53945 8700
c1858123 8701 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8702 factor = 21;
8703 if (is_lvds) {
8704 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8705 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8706 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8707 factor = 25;
190f68c5 8708 } else if (crtc_state->sdvo_tv_clock)
8febb297 8709 factor = 20;
c1858123 8710
190f68c5 8711 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8712 *fp |= FP_CB_TUNE;
2c07245f 8713
9a7c7890
DV		 8714 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8715 *fp2 |= FP_CB_TUNE;
8716
5eddb70b 8717 dpll = 0;
2c07245f 8718
a07d6787
EA		 8719 if (is_lvds)
8720 dpll |= DPLLB_MODE_LVDS;
8721 else
8722 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8723
190f68c5 8724 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8725 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8726
8727 if (is_sdvo)
4a33e48d 8728 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8729 if (crtc_state->has_dp_encoder)
4a33e48d 8730 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8731
a07d6787 8732 /* compute bitmask from p1 value */
190f68c5 8733 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8734 /* also FPA1 */
190f68c5 8735 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8736
190f68c5 8737 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8738 case 5:
8739 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8740 break;
8741 case 7:
8742 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8743 break;
8744 case 10:
8745 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8746 break;
8747 case 14:
8748 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8749 break;
79e53945
JB		 8750 }
8751
b4c09f3b 8752 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8753 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8754 else
8755 dpll |= PLL_REF_INPUT_DREFCLK;
8756
959e16d6 8757 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8758}
8759
190f68c5
ACO		 8760static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8761 struct intel_crtc_state *crtc_state)
de13a2e3 8762{
c7653199 8763 struct drm_device *dev = crtc->base.dev;
de13a2e3 8764 intel_clock_t clock, reduced_clock;
cbbab5bd 8765 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8766 bool ok, has_reduced_clock = false;
8b47047b 8767 bool is_lvds = false;
e2b78267 8768 struct intel_shared_dpll *pll;
de13a2e3 8769
dd3cd74a
ACO		 8770 memset(&crtc_state->dpll_hw_state, 0,
8771 sizeof(crtc_state->dpll_hw_state));
8772
409ee761 8773 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8774
5dc5298b
PZ		 8775 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8776 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8777
190f68c5 8778 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8779 &has_reduced_clock, &reduced_clock);
190f68c5 8780 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8781 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8782 return -EINVAL;
79e53945 8783 }
f47709a9 8784 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8785 if (!crtc_state->clock_set) {
8786 crtc_state->dpll.n = clock.n;
8787 crtc_state->dpll.m1 = clock.m1;
8788 crtc_state->dpll.m2 = clock.m2;
8789 crtc_state->dpll.p1 = clock.p1;
8790 crtc_state->dpll.p2 = clock.p2;
f47709a9 8791 }
79e53945 8792
5dc5298b 8793 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8794 if (crtc_state->has_pch_encoder) {
8795 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8796 if (has_reduced_clock)
7429e9d4 8797 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8798
190f68c5 8799 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8800 &fp, &reduced_clock,
8801 has_reduced_clock ? &fp2 : NULL);
8802
190f68c5
ACO		 8803 crtc_state->dpll_hw_state.dpll = dpll;
8804 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8805 if (has_reduced_clock)
190f68c5 8806 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8807 else
190f68c5 8808 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8809
190f68c5 8810 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8811 if (pll == NULL) {
84f44ce7 8812 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8813 pipe_name(crtc->pipe));
4b645f14
JB		 8814 return -EINVAL;
8815 }
3fb37703 8816 }
79e53945 8817
ab585dea 8818 if (is_lvds && has_reduced_clock)
c7653199 8819 crtc->lowfreq_avail = true;
bcd644e0 8820 else
c7653199 8821 crtc->lowfreq_avail = false;
e2b78267 8822
c8f7a0db 8823 return 0;
79e53945
JB		 8824}
8825
eb14cb74
VS		 8826static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8827 struct intel_link_m_n *m_n)
8828{
8829 struct drm_device *dev = crtc->base.dev;
8830 struct drm_i915_private *dev_priv = dev->dev_private;
8831 enum pipe pipe = crtc->pipe;
8832
8833 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8834 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8835 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8836 & ~TU_SIZE_MASK;
8837 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8838 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8839 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8840}
8841
8842static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8843 enum transcoder transcoder,
b95af8be
VK		 8844 struct intel_link_m_n *m_n,
8845 struct intel_link_m_n *m2_n2)
72419203
DV		 8846{
8847 struct drm_device *dev = crtc->base.dev;
8848 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8849 enum pipe pipe = crtc->pipe;
72419203 8850
eb14cb74
VS		 8851 if (INTEL_INFO(dev)->gen >= 5) {
8852 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8853 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8854 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8855 & ~TU_SIZE_MASK;
8856 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8857 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8858 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8859 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8860 * gen < 8) and if DRRS is supported (to make sure the
8861 * registers are not unnecessarily read).
8862 */
8863 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8864 crtc->config->has_drrs) {
b95af8be
VK		 8865 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8866 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8867 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8868 & ~TU_SIZE_MASK;
8869 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8870 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8871 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8872 }
eb14cb74
VS		 8873 } else {
8874 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8875 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8876 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8877 & ~TU_SIZE_MASK;
8878 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8879 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8880 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8881 }
8882}
8883
8884void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8885 struct intel_crtc_state *pipe_config)
eb14cb74 8886{
681a8504 8887 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8888 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8889 else
8890 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8891 &pipe_config->dp_m_n,
8892 &pipe_config->dp_m2_n2);
eb14cb74 8893}
72419203 8894
eb14cb74 8895static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8896 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8897{
8898 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8899 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8900}
8901
bd2e244f 8902static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8903 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8904{
8905 struct drm_device *dev = crtc->base.dev;
8906 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8907 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8908 uint32_t ps_ctrl = 0;
8909 int id = -1;
8910 int i;
bd2e244f 8911
a1b2278e
CK		 8912 /* find scaler attached to this pipe */
8913 for (i = 0; i < crtc->num_scalers; i++) {
8914 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8915 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8916 id = i;
8917 pipe_config->pch_pfit.enabled = true;
8918 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8919 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8920 break;
8921 }
8922 }
bd2e244f 8923
a1b2278e
CK		 8924 scaler_state->scaler_id = id;
8925 if (id >= 0) {
8926 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8927 } else {
8928 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8929 }
8930}
8931
5724dbd1
DL		 8932static void
8933skylake_get_initial_plane_config(struct intel_crtc *crtc,
8934 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8935{
8936 struct drm_device *dev = crtc->base.dev;
8937 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8938 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8939 int pipe = crtc->pipe;
8940 int fourcc, pixel_format;
6761dd31 8941 unsigned int aligned_height;
bc8d7dff 8942 struct drm_framebuffer *fb;
1b842c89 8943 struct intel_framebuffer *intel_fb;
bc8d7dff 8944
d9806c9f 8945 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8946 if (!intel_fb) {
bc8d7dff
DL		 8947 DRM_DEBUG_KMS("failed to alloc fb\n");
8948 return;
8949 }
8950
1b842c89
DL		 8951 fb = &intel_fb->base;
8952
bc8d7dff 8953 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8954 if (!(val & PLANE_CTL_ENABLE))
8955 goto error;
8956
bc8d7dff
DL		 8957 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8958 fourcc = skl_format_to_fourcc(pixel_format,
8959 val & PLANE_CTL_ORDER_RGBX,
8960 val & PLANE_CTL_ALPHA_MASK);
8961 fb->pixel_format = fourcc;
8962 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8963
40f46283
DL		 8964 tiling = val & PLANE_CTL_TILED_MASK;
8965 switch (tiling) {
8966 case PLANE_CTL_TILED_LINEAR:
8967 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8968 break;
8969 case PLANE_CTL_TILED_X:
8970 plane_config->tiling = I915_TILING_X;
8971 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8972 break;
8973 case PLANE_CTL_TILED_Y:
8974 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8975 break;
8976 case PLANE_CTL_TILED_YF:
8977 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8978 break;
8979 default:
8980 MISSING_CASE(tiling);
8981 goto error;
8982 }
8983
bc8d7dff
DL		 8984 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8985 plane_config->base = base;
8986
8987 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8988
8989 val = I915_READ(PLANE_SIZE(pipe, 0));
8990 fb->height = ((val >> 16) & 0xfff) + 1;
8991 fb->width = ((val >> 0) & 0x1fff) + 1;
8992
8993 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8994 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8995 fb->pixel_format);
bc8d7dff
DL		 8996 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8997
8998 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8999 fb->pixel_format,
9000 fb->modifier[0]);
bc8d7dff 9001
f37b5c2b 9002 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9003
9004 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9005 pipe_name(pipe), fb->width, fb->height,
9006 fb->bits_per_pixel, base, fb->pitches[0],
9007 plane_config->size);
9008
2d14030b 9009 plane_config->fb = intel_fb;
bc8d7dff
DL		 9010 return;
9011
9012error:
9013 kfree(fb);
9014}
9015
2fa2fe9a 9016static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9017 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9018{
9019 struct drm_device *dev = crtc->base.dev;
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021 uint32_t tmp;
9022
9023 tmp = I915_READ(PF_CTL(crtc->pipe));
9024
9025 if (tmp & PF_ENABLE) {
fd4daa9c 9026 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9027 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9028 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9029
9030 /* We currently do not free assignements of panel fitters on
9031 * ivb/hsw (since we don't use the higher upscaling modes which
9032 * differentiates them) so just WARN about this case for now. */
9033 if (IS_GEN7(dev)) {
9034 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9035 PF_PIPE_SEL_IVB(crtc->pipe));
9036 }
2fa2fe9a 9037 }
79e53945
JB		 9038}
9039
5724dbd1
DL		 9040static void
9041ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9042 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9043{
9044 struct drm_device *dev = crtc->base.dev;
9045 struct drm_i915_private *dev_priv = dev->dev_private;
9046 u32 val, base, offset;
aeee5a49 9047 int pipe = crtc->pipe;
4c6baa59 9048 int fourcc, pixel_format;
6761dd31 9049 unsigned int aligned_height;
b113d5ee 9050 struct drm_framebuffer *fb;
1b842c89 9051 struct intel_framebuffer *intel_fb;
4c6baa59 9052
42a7b088
DL		 9053 val = I915_READ(DSPCNTR(pipe));
9054 if (!(val & DISPLAY_PLANE_ENABLE))
9055 return;
9056
d9806c9f 9057 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9058 if (!intel_fb) {
4c6baa59
JB		 9059 DRM_DEBUG_KMS("failed to alloc fb\n");
9060 return;
9061 }
9062
1b842c89
DL		 9063 fb = &intel_fb->base;
9064
18c5247e
DV		 9065 if (INTEL_INFO(dev)->gen >= 4) {
9066 if (val & DISPPLANE_TILED) {
49af449b 9067 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9068 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9069 }
9070 }
4c6baa59
JB		 9071
9072 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9073 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9074 fb->pixel_format = fourcc;
9075 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9076
aeee5a49 9077 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9078 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9079 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9080 } else {
49af449b 9081 if (plane_config->tiling)
aeee5a49 9082 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9083 else
aeee5a49 9084 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9085 }
9086 plane_config->base = base;
9087
9088 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9089 fb->width = ((val >> 16) & 0xfff) + 1;
9090 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9091
9092 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9093 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9094
b113d5ee 9095 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9096 fb->pixel_format,
9097 fb->modifier[0]);
4c6baa59 9098
f37b5c2b 9099 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9100
2844a921
DL		 9101 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9102 pipe_name(pipe), fb->width, fb->height,
9103 fb->bits_per_pixel, base, fb->pitches[0],
9104 plane_config->size);
b113d5ee 9105
2d14030b 9106 plane_config->fb = intel_fb;
4c6baa59
JB		 9107}
9108
0e8ffe1b 9109static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9110 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9111{
9112 struct drm_device *dev = crtc->base.dev;
9113 struct drm_i915_private *dev_priv = dev->dev_private;
9114 uint32_t tmp;
9115
f458ebbc
DV		 9116 if (!intel_display_power_is_enabled(dev_priv,
9117 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9118 return false;
9119
e143a21c 9120 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9121 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9122
0e8ffe1b
DV		 9123 tmp = I915_READ(PIPECONF(crtc->pipe));
9124 if (!(tmp & PIPECONF_ENABLE))
9125 return false;
9126
42571aef
VS		 9127 switch (tmp & PIPECONF_BPC_MASK) {
9128 case PIPECONF_6BPC:
9129 pipe_config->pipe_bpp = 18;
9130 break;
9131 case PIPECONF_8BPC:
9132 pipe_config->pipe_bpp = 24;
9133 break;
9134 case PIPECONF_10BPC:
9135 pipe_config->pipe_bpp = 30;
9136 break;
9137 case PIPECONF_12BPC:
9138 pipe_config->pipe_bpp = 36;
9139 break;
9140 default:
9141 break;
9142 }
9143
b5a9fa09
DV		 9144 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9145 pipe_config->limited_color_range = true;
9146
ab9412ba 9147 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9148 struct intel_shared_dpll *pll;
9149
88adfff1
DV		 9150 pipe_config->has_pch_encoder = true;
9151
627eb5a3
DV		 9152 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9153 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9154 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9155
9156 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9157
c0d43d62 9158 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9159 pipe_config->shared_dpll =
9160 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9161 } else {
9162 tmp = I915_READ(PCH_DPLL_SEL);
9163 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9164 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9165 else
9166 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9167 }
66e985c0
DV		 9168
9169 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9170
9171 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9172 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9173
9174 tmp = pipe_config->dpll_hw_state.dpll;
9175 pipe_config->pixel_multiplier =
9176 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9177 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9178
9179 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9180 } else {
9181 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9182 }
9183
1bd1bd80
DV		 9184 intel_get_pipe_timings(crtc, pipe_config);
9185
2fa2fe9a
DV		 9186 ironlake_get_pfit_config(crtc, pipe_config);
9187
0e8ffe1b
DV		 9188 return true;
9189}
9190
be256dc7
PZ		 9191static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9192{
9193 struct drm_device *dev = dev_priv->dev;
be256dc7 9194 struct intel_crtc *crtc;
be256dc7 9195
d3fcc808 9196 for_each_intel_crtc(dev, crtc)
e2c719b7 9197 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9198 pipe_name(crtc->pipe));
9199
e2c719b7
RC		 9200 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9201 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9202 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9203 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9204 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9205 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9206 "CPU PWM1 enabled\n");
c5107b87 9207 if (IS_HASWELL(dev))
e2c719b7 9208 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9209 "CPU PWM2 enabled\n");
e2c719b7 9210 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9211 "PCH PWM1 enabled\n");
e2c719b7 9212 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9213 "Utility pin enabled\n");
e2c719b7 9214 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9215
9926ada1
PZ		 9216 /*
9217 * In theory we can still leave IRQs enabled, as long as only the HPD
9218 * interrupts remain enabled. We used to check for that, but since it's
9219 * gen-specific and since we only disable LCPLL after we fully disable
9220 * the interrupts, the check below should be enough.
9221 */
e2c719b7 9222 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9223}
9224
9ccd5aeb
PZ		 9225static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9226{
9227 struct drm_device *dev = dev_priv->dev;
9228
9229 if (IS_HASWELL(dev))
9230 return I915_READ(D_COMP_HSW);
9231 else
9232 return I915_READ(D_COMP_BDW);
9233}
9234
3c4c9b81
PZ		 9235static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9236{
9237 struct drm_device *dev = dev_priv->dev;
9238
9239 if (IS_HASWELL(dev)) {
9240 mutex_lock(&dev_priv->rps.hw_lock);
9241 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9242 val))
f475dadf 9243 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9244 mutex_unlock(&dev_priv->rps.hw_lock);
9245 } else {
9ccd5aeb
PZ		 9246 I915_WRITE(D_COMP_BDW, val);
9247 POSTING_READ(D_COMP_BDW);
3c4c9b81 9248 }
be256dc7
PZ		 9249}
9250
9251/*
9252 * This function implements pieces of two sequences from BSpec:
9253 * - Sequence for display software to disable LCPLL
9254 * - Sequence for display software to allow package C8+
9255 * The steps implemented here are just the steps that actually touch the LCPLL
9256 * register. Callers should take care of disabling all the display engine
9257 * functions, doing the mode unset, fixing interrupts, etc.
9258 */
6ff58d53
PZ		 9259static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9260 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9261{
9262 uint32_t val;
9263
9264 assert_can_disable_lcpll(dev_priv);
9265
9266 val = I915_READ(LCPLL_CTL);
9267
9268 if (switch_to_fclk) {
9269 val |= LCPLL_CD_SOURCE_FCLK;
9270 I915_WRITE(LCPLL_CTL, val);
9271
9272 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9273 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9274 DRM_ERROR("Switching to FCLK failed\n");
9275
9276 val = I915_READ(LCPLL_CTL);
9277 }
9278
9279 val |= LCPLL_PLL_DISABLE;
9280 I915_WRITE(LCPLL_CTL, val);
9281 POSTING_READ(LCPLL_CTL);
9282
9283 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9284 DRM_ERROR("LCPLL still locked\n");
9285
9ccd5aeb 9286 val = hsw_read_dcomp(dev_priv);
be256dc7 9287 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9288 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9289 ndelay(100);
9290
9ccd5aeb
PZ		 9291 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9292 1))
be256dc7
PZ		 9293 DRM_ERROR("D_COMP RCOMP still in progress\n");
9294
9295 if (allow_power_down) {
9296 val = I915_READ(LCPLL_CTL);
9297 val |= LCPLL_POWER_DOWN_ALLOW;
9298 I915_WRITE(LCPLL_CTL, val);
9299 POSTING_READ(LCPLL_CTL);
9300 }
9301}
9302
9303/*
9304 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9305 * source.
9306 */
6ff58d53 9307static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9308{
9309 uint32_t val;
9310
9311 val = I915_READ(LCPLL_CTL);
9312
9313 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9314 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9315 return;
9316
a8a8bd54
PZ		 9317 /*
9318 * Make sure we're not on PC8 state before disabling PC8, otherwise
9319 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9320 */
59bad947 9321 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9322
be256dc7
PZ		 9323 if (val & LCPLL_POWER_DOWN_ALLOW) {
9324 val &= ~LCPLL_POWER_DOWN_ALLOW;
9325 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9326 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9327 }
9328
9ccd5aeb 9329 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9330 val |= D_COMP_COMP_FORCE;
9331 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9332 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9333
9334 val = I915_READ(LCPLL_CTL);
9335 val &= ~LCPLL_PLL_DISABLE;
9336 I915_WRITE(LCPLL_CTL, val);
9337
9338 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9339 DRM_ERROR("LCPLL not locked yet\n");
9340
9341 if (val & LCPLL_CD_SOURCE_FCLK) {
9342 val = I915_READ(LCPLL_CTL);
9343 val &= ~LCPLL_CD_SOURCE_FCLK;
9344 I915_WRITE(LCPLL_CTL, val);
9345
9346 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9347 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9348 DRM_ERROR("Switching back to LCPLL failed\n");
9349 }
215733fa 9350
59bad947 9351 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9352 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9353}
9354
765dab67
PZ		 9355/*
9356 * Package states C8 and deeper are really deep PC states that can only be
9357 * reached when all the devices on the system allow it, so even if the graphics
9358 * device allows PC8+, it doesn't mean the system will actually get to these
9359 * states. Our driver only allows PC8+ when going into runtime PM.
9360 *
9361 * The requirements for PC8+ are that all the outputs are disabled, the power
9362 * well is disabled and most interrupts are disabled, and these are also
9363 * requirements for runtime PM. When these conditions are met, we manually do
9364 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9365 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9366 * hang the machine.
9367 *
9368 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9369 * the state of some registers, so when we come back from PC8+ we need to
9370 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9371 * need to take care of the registers kept by RC6. Notice that this happens even
9372 * if we don't put the device in PCI D3 state (which is what currently happens
9373 * because of the runtime PM support).
9374 *
9375 * For more, read "Display Sequences for Package C8" on the hardware
9376 * documentation.
9377 */
a14cb6fc 9378void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9379{
c67a470b
PZ		 9380 struct drm_device *dev = dev_priv->dev;
9381 uint32_t val;
9382
c67a470b
PZ		 9383 DRM_DEBUG_KMS("Enabling package C8+\n");
9384
c67a470b
PZ		 9385 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9386 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9387 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9388 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9389 }
9390
9391 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9392 hsw_disable_lcpll(dev_priv, true, true);
9393}
9394
a14cb6fc 9395void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9396{
9397 struct drm_device *dev = dev_priv->dev;
9398 uint32_t val;
9399
c67a470b
PZ		 9400 DRM_DEBUG_KMS("Disabling package C8+\n");
9401
9402 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9403 lpt_init_pch_refclk(dev);
9404
9405 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9406 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9407 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9408 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9409 }
9410
9411 intel_prepare_ddi(dev);
c67a470b
PZ		 9412}
9413
27c329ed 9414static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9415{
a821fc46 9416 struct drm_device *dev = old_state->dev;
27c329ed 9417 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9418
27c329ed 9419 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9420}
9421
b432e5cf 9422/* compute the max rate for new configuration */
27c329ed 9423static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9424{
b432e5cf 9425 struct intel_crtc *intel_crtc;
27c329ed 9426 struct intel_crtc_state *crtc_state;
b432e5cf 9427 int max_pixel_rate = 0;
b432e5cf 9428
27c329ed
ML		 9429 for_each_intel_crtc(state->dev, intel_crtc) {
9430 int pixel_rate;
9431
9432 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9433 if (IS_ERR(crtc_state))
9434 return PTR_ERR(crtc_state);
9435
9436 if (!crtc_state->base.enable)
b432e5cf
VS		 9437 continue;
9438
27c329ed 9439 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9440
9441 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9442 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9443 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9444
9445 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9446 }
9447
9448 return max_pixel_rate;
9449}
9450
9451static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9452{
9453 struct drm_i915_private *dev_priv = dev->dev_private;
9454 uint32_t val, data;
9455 int ret;
9456
9457 if (WARN((I915_READ(LCPLL_CTL) &
9458 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9459 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9460 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9461 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9462 "trying to change cdclk frequency with cdclk not enabled\n"))
9463 return;
9464
9465 mutex_lock(&dev_priv->rps.hw_lock);
9466 ret = sandybridge_pcode_write(dev_priv,
9467 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9468 mutex_unlock(&dev_priv->rps.hw_lock);
9469 if (ret) {
9470 DRM_ERROR("failed to inform pcode about cdclk change\n");
9471 return;
9472 }
9473
9474 val = I915_READ(LCPLL_CTL);
9475 val |= LCPLL_CD_SOURCE_FCLK;
9476 I915_WRITE(LCPLL_CTL, val);
9477
9478 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9479 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9480 DRM_ERROR("Switching to FCLK failed\n");
9481
9482 val = I915_READ(LCPLL_CTL);
9483 val &= ~LCPLL_CLK_FREQ_MASK;
9484
9485 switch (cdclk) {
9486 case 450000:
9487 val |= LCPLL_CLK_FREQ_450;
9488 data = 0;
9489 break;
9490 case 540000:
9491 val |= LCPLL_CLK_FREQ_54O_BDW;
9492 data = 1;
9493 break;
9494 case 337500:
9495 val |= LCPLL_CLK_FREQ_337_5_BDW;
9496 data = 2;
9497 break;
9498 case 675000:
9499 val |= LCPLL_CLK_FREQ_675_BDW;
9500 data = 3;
9501 break;
9502 default:
9503 WARN(1, "invalid cdclk frequency\n");
9504 return;
9505 }
9506
9507 I915_WRITE(LCPLL_CTL, val);
9508
9509 val = I915_READ(LCPLL_CTL);
9510 val &= ~LCPLL_CD_SOURCE_FCLK;
9511 I915_WRITE(LCPLL_CTL, val);
9512
9513 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9514 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9515 DRM_ERROR("Switching back to LCPLL failed\n");
9516
9517 mutex_lock(&dev_priv->rps.hw_lock);
9518 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9519 mutex_unlock(&dev_priv->rps.hw_lock);
9520
9521 intel_update_cdclk(dev);
9522
9523 WARN(cdclk != dev_priv->cdclk_freq,
9524 "cdclk requested %d kHz but got %d kHz\n",
9525 cdclk, dev_priv->cdclk_freq);
9526}
9527
27c329ed 9528static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9529{
27c329ed
ML		 9530 struct drm_i915_private *dev_priv = to_i915(state->dev);
9531 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9532 int cdclk;
9533
9534 /*
9535 * FIXME should also account for plane ratio
9536 * once 64bpp pixel formats are supported.
9537 */
27c329ed 9538 if (max_pixclk > 540000)
b432e5cf 9539 cdclk = 675000;
27c329ed 9540 else if (max_pixclk > 450000)
b432e5cf 9541 cdclk = 540000;
27c329ed 9542 else if (max_pixclk > 337500)
b432e5cf
VS		 9543 cdclk = 450000;
9544 else
9545 cdclk = 337500;
9546
9547 /*
9548 * FIXME move the cdclk caclulation to
9549 * compute_config() so we can fail gracegully.
9550 */
9551 if (cdclk > dev_priv->max_cdclk_freq) {
9552 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9553 cdclk, dev_priv->max_cdclk_freq);
9554 cdclk = dev_priv->max_cdclk_freq;
9555 }
9556
27c329ed 9557 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9558
9559 return 0;
9560}
9561
27c329ed 9562static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9563{
27c329ed
ML		 9564 struct drm_device *dev = old_state->dev;
9565 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9566
27c329ed 9567 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9568}
9569
190f68c5
ACO		 9570static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9571 struct intel_crtc_state *crtc_state)
09b4ddf9 9572{
190f68c5 9573 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9574 return -EINVAL;
716c2e55 9575
c7653199 9576 crtc->lowfreq_avail = false;
644cef34 9577
c8f7a0db 9578 return 0;
79e53945
JB		 9579}
9580
3760b59c
S		 9581static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9582 enum port port,
9583 struct intel_crtc_state *pipe_config)
9584{
9585 switch (port) {
9586 case PORT_A:
9587 pipe_config->ddi_pll_sel = SKL_DPLL0;
9588 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9589 break;
9590 case PORT_B:
9591 pipe_config->ddi_pll_sel = SKL_DPLL1;
9592 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9593 break;
9594 case PORT_C:
9595 pipe_config->ddi_pll_sel = SKL_DPLL2;
9596 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9597 break;
9598 default:
9599 DRM_ERROR("Incorrect port type\n");
9600 }
9601}
9602
96b7dfb7
S		 9603static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9604 enum port port,
5cec258b 9605 struct intel_crtc_state *pipe_config)
96b7dfb7 9606{
3148ade7 9607 u32 temp, dpll_ctl1;
96b7dfb7
S		 9608
9609 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9610 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9611
9612 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9613 case SKL_DPLL0:
9614 /*
9615 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9616 * of the shared DPLL framework and thus needs to be read out
9617 * separately
9618 */
9619 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9620 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9621 break;
96b7dfb7
S		 9622 case SKL_DPLL1:
9623 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9624 break;
9625 case SKL_DPLL2:
9626 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9627 break;
9628 case SKL_DPLL3:
9629 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9630 break;
96b7dfb7
S		 9631 }
9632}
9633
7d2c8175
DL		 9634static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9635 enum port port,
5cec258b 9636 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9637{
9638 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9639
9640 switch (pipe_config->ddi_pll_sel) {
9641 case PORT_CLK_SEL_WRPLL1:
9642 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9643 break;
9644 case PORT_CLK_SEL_WRPLL2:
9645 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9646 break;
9647 }
9648}
9649
26804afd 9650static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9651 struct intel_crtc_state *pipe_config)
26804afd
DV		 9652{
9653 struct drm_device *dev = crtc->base.dev;
9654 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9655 struct intel_shared_dpll *pll;
26804afd
DV		 9656 enum port port;
9657 uint32_t tmp;
9658
9659 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9660
9661 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9662
96b7dfb7
S		 9663 if (IS_SKYLAKE(dev))
9664 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9665 else if (IS_BROXTON(dev))
9666 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9667 else
9668 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9669
d452c5b6
DV		 9670 if (pipe_config->shared_dpll >= 0) {
9671 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9672
9673 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9674 &pipe_config->dpll_hw_state));
9675 }
9676
26804afd
DV		 9677 /*
9678 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9679 * DDI E. So just check whether this pipe is wired to DDI E and whether
9680 * the PCH transcoder is on.
9681 */
ca370455
DL		 9682 if (INTEL_INFO(dev)->gen < 9 &&
9683 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9684 pipe_config->has_pch_encoder = true;
9685
9686 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9687 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9688 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9689
9690 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9691 }
9692}
9693
0e8ffe1b 9694static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9695 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9696{
9697 struct drm_device *dev = crtc->base.dev;
9698 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9699 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9700 uint32_t tmp;
9701
f458ebbc 9702 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9703 POWER_DOMAIN_PIPE(crtc->pipe)))
9704 return false;
9705
e143a21c 9706 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9707 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9708
eccb140b
DV		 9709 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9710 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9711 enum pipe trans_edp_pipe;
9712 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9713 default:
9714 WARN(1, "unknown pipe linked to edp transcoder\n");
9715 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9716 case TRANS_DDI_EDP_INPUT_A_ON:
9717 trans_edp_pipe = PIPE_A;
9718 break;
9719 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9720 trans_edp_pipe = PIPE_B;
9721 break;
9722 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9723 trans_edp_pipe = PIPE_C;
9724 break;
9725 }
9726
9727 if (trans_edp_pipe == crtc->pipe)
9728 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9729 }
9730
f458ebbc 9731 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9732 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9733 return false;
9734
eccb140b 9735 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9736 if (!(tmp & PIPECONF_ENABLE))
9737 return false;
9738
26804afd 9739 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9740
1bd1bd80
DV		 9741 intel_get_pipe_timings(crtc, pipe_config);
9742
a1b2278e
CK		 9743 if (INTEL_INFO(dev)->gen >= 9) {
9744 skl_init_scalers(dev, crtc, pipe_config);
9745 }
9746
2fa2fe9a 9747 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9748
9749 if (INTEL_INFO(dev)->gen >= 9) {
9750 pipe_config->scaler_state.scaler_id = -1;
9751 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9752 }
9753
bd2e244f 9754 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9755 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9756 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9757 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9758 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9759 else
9760 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9761 }
88adfff1 9762
e59150dc
JB		 9763 if (IS_HASWELL(dev))
9764 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9765 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9766
ebb69c95
CT		 9767 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9768 pipe_config->pixel_multiplier =
9769 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9770 } else {
9771 pipe_config->pixel_multiplier = 1;
9772 }
6c49f241 9773
0e8ffe1b
DV		 9774 return true;
9775}
9776
560b85bb
CW		 9777static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9778{
9779 struct drm_device *dev = crtc->dev;
9780 struct drm_i915_private *dev_priv = dev->dev_private;
9781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9782 uint32_t cntl = 0, size = 0;
560b85bb 9783
dc41c154 9784 if (base) {
3dd512fb
MR		 9785 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9786 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9787 unsigned int stride = roundup_pow_of_two(width) * 4;
9788
9789 switch (stride) {
9790 default:
9791 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9792 width, stride);
9793 stride = 256;
9794 /* fallthrough */
9795 case 256:
9796 case 512:
9797 case 1024:
9798 case 2048:
9799 break;
4b0e333e
CW		 9800 }
9801
dc41c154
VS		 9802 cntl |= CURSOR_ENABLE |
9803 CURSOR_GAMMA_ENABLE |
9804 CURSOR_FORMAT_ARGB |
9805 CURSOR_STRIDE(stride);
9806
9807 size = (height << 12) | width;
4b0e333e 9808 }
560b85bb 9809
dc41c154
VS		 9810 if (intel_crtc->cursor_cntl != 0 &&
9811 (intel_crtc->cursor_base != base ||
9812 intel_crtc->cursor_size != size ||
9813 intel_crtc->cursor_cntl != cntl)) {
9814 /* On these chipsets we can only modify the base/size/stride
9815 * whilst the cursor is disabled.
9816 */
9817 I915_WRITE(_CURACNTR, 0);
4b0e333e 9818 POSTING_READ(_CURACNTR);
dc41c154 9819 intel_crtc->cursor_cntl = 0;
4b0e333e 9820 }
560b85bb 9821
99d1f387 9822 if (intel_crtc->cursor_base != base) {
9db4a9c7 9823 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9824 intel_crtc->cursor_base = base;
9825 }
4726e0b0 9826
dc41c154
VS		 9827 if (intel_crtc->cursor_size != size) {
9828 I915_WRITE(CURSIZE, size);
9829 intel_crtc->cursor_size = size;
4b0e333e 9830 }
560b85bb 9831
4b0e333e 9832 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9833 I915_WRITE(_CURACNTR, cntl);
9834 POSTING_READ(_CURACNTR);
4b0e333e 9835 intel_crtc->cursor_cntl = cntl;
560b85bb 9836 }
560b85bb
CW		 9837}
9838
560b85bb 9839static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9840{
9841 struct drm_device *dev = crtc->dev;
9842 struct drm_i915_private *dev_priv = dev->dev_private;
9843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9844 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9845 uint32_t cntl;
9846
9847 cntl = 0;
9848 if (base) {
9849 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9850 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9851 case 64:
9852 cntl |= CURSOR_MODE_64_ARGB_AX;
9853 break;
9854 case 128:
9855 cntl |= CURSOR_MODE_128_ARGB_AX;
9856 break;
9857 case 256:
9858 cntl |= CURSOR_MODE_256_ARGB_AX;
9859 break;
9860 default:
3dd512fb 9861 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9862 return;
65a21cd6 9863 }
4b0e333e 9864 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9865
9866 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9867 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9868 }
65a21cd6 9869
8e7d688b 9870 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9871 cntl |= CURSOR_ROTATE_180;
9872
4b0e333e
CW		 9873 if (intel_crtc->cursor_cntl != cntl) {
9874 I915_WRITE(CURCNTR(pipe), cntl);
9875 POSTING_READ(CURCNTR(pipe));
9876 intel_crtc->cursor_cntl = cntl;
65a21cd6 9877 }
4b0e333e 9878
65a21cd6 9879 /* and commit changes on next vblank */
5efb3e28
VS		 9880 I915_WRITE(CURBASE(pipe), base);
9881 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9882
9883 intel_crtc->cursor_base = base;
65a21cd6
JB		 9884}
9885
cda4b7d3 9886/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9887static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9888 bool on)
cda4b7d3
CW		 9889{
9890 struct drm_device *dev = crtc->dev;
9891 struct drm_i915_private *dev_priv = dev->dev_private;
9892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9893 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9894 int x = crtc->cursor_x;
9895 int y = crtc->cursor_y;
d6e4db15 9896 u32 base = 0, pos = 0;
cda4b7d3 9897
d6e4db15 9898 if (on)
cda4b7d3 9899 base = intel_crtc->cursor_addr;
cda4b7d3 9900
6e3c9717 9901 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9902 base = 0;
9903
6e3c9717 9904 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9905 base = 0;
9906
9907 if (x < 0) {
3dd512fb 9908 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9909 base = 0;
9910
9911 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9912 x = -x;
9913 }
9914 pos |= x << CURSOR_X_SHIFT;
9915
9916 if (y < 0) {
3dd512fb 9917 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9918 base = 0;
9919
9920 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9921 y = -y;
9922 }
9923 pos |= y << CURSOR_Y_SHIFT;
9924
4b0e333e 9925 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9926 return;
9927
5efb3e28
VS		 9928 I915_WRITE(CURPOS(pipe), pos);
9929
4398ad45
VS		 9930 /* ILK+ do this automagically */
9931 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9932 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9933 base += (intel_crtc->base.cursor->state->crtc_h *
9934 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9935 }
9936
8ac54669 9937 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9938 i845_update_cursor(crtc, base);
9939 else
9940 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9941}
9942
dc41c154
VS		 9943static bool cursor_size_ok(struct drm_device *dev,
9944 uint32_t width, uint32_t height)
9945{
9946 if (width == 0 || height == 0)
9947 return false;
9948
9949 /*
9950 * 845g/865g are special in that they are only limited by
9951 * the width of their cursors, the height is arbitrary up to
9952 * the precision of the register. Everything else requires
9953 * square cursors, limited to a few power-of-two sizes.
9954 */
9955 if (IS_845G(dev) || IS_I865G(dev)) {
9956 if ((width & 63) != 0)
9957 return false;
9958
9959 if (width > (IS_845G(dev) ? 64 : 512))
9960 return false;
9961
9962 if (height > 1023)
9963 return false;
9964 } else {
9965 switch (width | height) {
9966 case 256:
9967 case 128:
9968 if (IS_GEN2(dev))
9969 return false;
9970 case 64:
9971 break;
9972 default:
9973 return false;
9974 }
9975 }
9976
9977 return true;
9978}
9979
79e53945 9980static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9981 u16 *blue, uint32_t start, uint32_t size)
79e53945 9982{
7203425a 9983 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9985
7203425a 9986 for (i = start; i < end; i++) {
79e53945
JB		 9987 intel_crtc->lut_r[i] = red[i] >> 8;
9988 intel_crtc->lut_g[i] = green[i] >> 8;
9989 intel_crtc->lut_b[i] = blue[i] >> 8;
9990 }
9991
9992 intel_crtc_load_lut(crtc);
9993}
9994
79e53945
JB		 9995/* VESA 640x480x72Hz mode to set on the pipe */
9996static struct drm_display_mode load_detect_mode = {
9997 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9998 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9999};
10000
a8bb6818
DV		 10001struct drm_framebuffer *
10002__intel_framebuffer_create(struct drm_device *dev,
10003 struct drm_mode_fb_cmd2 *mode_cmd,
10004 struct drm_i915_gem_object *obj)
d2dff872
CW		 10005{
10006 struct intel_framebuffer *intel_fb;
10007 int ret;
10008
10009 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10010 if (!intel_fb) {
6ccb81f2 10011 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10012 return ERR_PTR(-ENOMEM);
10013 }
10014
10015 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10016 if (ret)
10017 goto err;
d2dff872
CW		 10018
10019 return &intel_fb->base;
dd4916c5 10020err:
6ccb81f2 10021 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10022 kfree(intel_fb);
10023
10024 return ERR_PTR(ret);
d2dff872
CW		 10025}
10026
b5ea642a 10027static struct drm_framebuffer *
a8bb6818
DV		 10028intel_framebuffer_create(struct drm_device *dev,
10029 struct drm_mode_fb_cmd2 *mode_cmd,
10030 struct drm_i915_gem_object *obj)
10031{
10032 struct drm_framebuffer *fb;
10033 int ret;
10034
10035 ret = i915_mutex_lock_interruptible(dev);
10036 if (ret)
10037 return ERR_PTR(ret);
10038 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10039 mutex_unlock(&dev->struct_mutex);
10040
10041 return fb;
10042}
10043
d2dff872
CW		 10044static u32
10045intel_framebuffer_pitch_for_width(int width, int bpp)
10046{
10047 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10048 return ALIGN(pitch, 64);
10049}
10050
10051static u32
10052intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10053{
10054 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10055 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10056}
10057
10058static struct drm_framebuffer *
10059intel_framebuffer_create_for_mode(struct drm_device *dev,
10060 struct drm_display_mode *mode,
10061 int depth, int bpp)
10062{
10063 struct drm_i915_gem_object *obj;
0fed39bd 10064 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10065
10066 obj = i915_gem_alloc_object(dev,
10067 intel_framebuffer_size_for_mode(mode, bpp));
10068 if (obj == NULL)
10069 return ERR_PTR(-ENOMEM);
10070
10071 mode_cmd.width = mode->hdisplay;
10072 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10073 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10074 bpp);
5ca0c34a 10075 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10076
10077 return intel_framebuffer_create(dev, &mode_cmd, obj);
10078}
10079
10080static struct drm_framebuffer *
10081mode_fits_in_fbdev(struct drm_device *dev,
10082 struct drm_display_mode *mode)
10083{
4520f53a 10084#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10085 struct drm_i915_private *dev_priv = dev->dev_private;
10086 struct drm_i915_gem_object *obj;
10087 struct drm_framebuffer *fb;
10088
4c0e5528 10089 if (!dev_priv->fbdev)
d2dff872
CW		 10090 return NULL;
10091
4c0e5528 10092 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10093 return NULL;
10094
4c0e5528
DV		 10095 obj = dev_priv->fbdev->fb->obj;
10096 BUG_ON(!obj);
10097
8bcd4553 10098 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10099 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10100 fb->bits_per_pixel))
d2dff872
CW		 10101 return NULL;
10102
01f2c773 10103 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10104 return NULL;
10105
10106 return fb;
4520f53a
DV		 10107#else
10108 return NULL;
10109#endif
d2dff872
CW		 10110}
10111
d3a40d1b
ACO		 10112static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10113 struct drm_crtc *crtc,
10114 struct drm_display_mode *mode,
10115 struct drm_framebuffer *fb,
10116 int x, int y)
10117{
10118 struct drm_plane_state *plane_state;
10119 int hdisplay, vdisplay;
10120 int ret;
10121
10122 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10123 if (IS_ERR(plane_state))
10124 return PTR_ERR(plane_state);
10125
10126 if (mode)
10127 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10128 else
10129 hdisplay = vdisplay = 0;
10130
10131 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10132 if (ret)
10133 return ret;
10134 drm_atomic_set_fb_for_plane(plane_state, fb);
10135 plane_state->crtc_x = 0;
10136 plane_state->crtc_y = 0;
10137 plane_state->crtc_w = hdisplay;
10138 plane_state->crtc_h = vdisplay;
10139 plane_state->src_x = x << 16;
10140 plane_state->src_y = y << 16;
10141 plane_state->src_w = hdisplay << 16;
10142 plane_state->src_h = vdisplay << 16;
10143
10144 return 0;
10145}
10146
d2434ab7 10147bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10148 struct drm_display_mode *mode,
51fd371b
RC		 10149 struct intel_load_detect_pipe *old,
10150 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10151{
10152 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10153 struct intel_encoder *intel_encoder =
10154 intel_attached_encoder(connector);
79e53945 10155 struct drm_crtc *possible_crtc;
4ef69c7a 10156 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10157 struct drm_crtc *crtc = NULL;
10158 struct drm_device *dev = encoder->dev;
94352cf9 10159 struct drm_framebuffer *fb;
51fd371b 10160 struct drm_mode_config *config = &dev->mode_config;
83a57153 10161 struct drm_atomic_state *state = NULL;
944b0c76 10162 struct drm_connector_state *connector_state;
4be07317 10163 struct intel_crtc_state *crtc_state;
51fd371b 10164 int ret, i = -1;
79e53945 10165
d2dff872 10166 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10167 connector->base.id, connector->name,
8e329a03 10168 encoder->base.id, encoder->name);
d2dff872 10169
51fd371b
RC		 10170retry:
10171 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10172 if (ret)
ad3c558f 10173 goto fail;
6e9f798d 10174
79e53945
JB		 10175 /*
10176 * Algorithm gets a little messy:
7a5e4805 10177 *
79e53945
JB		 10178 * - if the connector already has an assigned crtc, use it (but make
10179 * sure it's on first)
7a5e4805 10180 *
79e53945
JB		 10181 * - try to find the first unused crtc that can drive this connector,
10182 * and use that if we find one
79e53945
JB		 10183 */
10184
10185 /* See if we already have a CRTC for this connector */
10186 if (encoder->crtc) {
10187 crtc = encoder->crtc;
8261b191 10188
51fd371b 10189 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10190 if (ret)
ad3c558f 10191 goto fail;
4d02e2de 10192 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10193 if (ret)
ad3c558f 10194 goto fail;
7b24056b 10195
24218aac 10196 old->dpms_mode = connector->dpms;
8261b191
CW		 10197 old->load_detect_temp = false;
10198
10199 /* Make sure the crtc and connector are running */
24218aac
DV		 10200 if (connector->dpms != DRM_MODE_DPMS_ON)
10201 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10202
7173188d 10203 return true;
79e53945
JB		 10204 }
10205
10206 /* Find an unused one (if possible) */
70e1e0ec 10207 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10208 i++;
10209 if (!(encoder->possible_crtcs & (1 << i)))
10210 continue;
83d65738 10211 if (possible_crtc->state->enable)
a459249c 10212 continue;
a459249c
VS		 10213
10214 crtc = possible_crtc;
10215 break;
79e53945
JB		 10216 }
10217
10218 /*
10219 * If we didn't find an unused CRTC, don't use any.
10220 */
10221 if (!crtc) {
7173188d 10222 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10223 goto fail;
79e53945
JB		 10224 }
10225
51fd371b
RC		 10226 ret = drm_modeset_lock(&crtc->mutex, ctx);
10227 if (ret)
ad3c558f 10228 goto fail;
4d02e2de
DV		 10229 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10230 if (ret)
ad3c558f 10231 goto fail;
79e53945
JB		 10232
10233 intel_crtc = to_intel_crtc(crtc);
24218aac 10234 old->dpms_mode = connector->dpms;
8261b191 10235 old->load_detect_temp = true;
d2dff872 10236 old->release_fb = NULL;
79e53945 10237
83a57153
ACO		 10238 state = drm_atomic_state_alloc(dev);
10239 if (!state)
10240 return false;
10241
10242 state->acquire_ctx = ctx;
10243
944b0c76
ACO		 10244 connector_state = drm_atomic_get_connector_state(state, connector);
10245 if (IS_ERR(connector_state)) {
10246 ret = PTR_ERR(connector_state);
10247 goto fail;
10248 }
10249
10250 connector_state->crtc = crtc;
10251 connector_state->best_encoder = &intel_encoder->base;
10252
4be07317
ACO		 10253 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10254 if (IS_ERR(crtc_state)) {
10255 ret = PTR_ERR(crtc_state);
10256 goto fail;
10257 }
10258
49d6fa21 10259 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10260
6492711d
CW		 10261 if (!mode)
10262 mode = &load_detect_mode;
79e53945 10263
d2dff872
CW		 10264 /* We need a framebuffer large enough to accommodate all accesses
10265 * that the plane may generate whilst we perform load detection.
10266 * We can not rely on the fbcon either being present (we get called
10267 * during its initialisation to detect all boot displays, or it may
10268 * not even exist) or that it is large enough to satisfy the
10269 * requested mode.
10270 */
94352cf9
DV		 10271 fb = mode_fits_in_fbdev(dev, mode);
10272 if (fb == NULL) {
d2dff872 10273 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10274 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10275 old->release_fb = fb;
d2dff872
CW		 10276 } else
10277 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10278 if (IS_ERR(fb)) {
d2dff872 10279 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10280 goto fail;
79e53945 10281 }
79e53945 10282
d3a40d1b
ACO		 10283 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10284 if (ret)
10285 goto fail;
10286
8c7b5ccb
ACO		 10287 drm_mode_copy(&crtc_state->base.mode, mode);
10288
74c090b1 10289 if (drm_atomic_commit(state)) {
6492711d 10290 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10291 if (old->release_fb)
10292 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10293 goto fail;
79e53945 10294 }
9128b040 10295 crtc->primary->crtc = crtc;
7173188d 10296
79e53945 10297 /* let the connector get through one full cycle before testing */
9d0498a2 10298 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10299 return true;
412b61d8 10300
ad3c558f 10301fail:
e5d958ef
ACO		 10302 drm_atomic_state_free(state);
10303 state = NULL;
83a57153 10304
51fd371b
RC		 10305 if (ret == -EDEADLK) {
10306 drm_modeset_backoff(ctx);
10307 goto retry;
10308 }
10309
412b61d8 10310 return false;
79e53945
JB		 10311}
10312
d2434ab7 10313void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10314 struct intel_load_detect_pipe *old,
10315 struct drm_modeset_acquire_ctx *ctx)
79e53945 10316{
83a57153 10317 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10318 struct intel_encoder *intel_encoder =
10319 intel_attached_encoder(connector);
4ef69c7a 10320 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10321 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10323 struct drm_atomic_state *state;
944b0c76 10324 struct drm_connector_state *connector_state;
4be07317 10325 struct intel_crtc_state *crtc_state;
d3a40d1b 10326 int ret;
79e53945 10327
d2dff872 10328 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10329 connector->base.id, connector->name,
8e329a03 10330 encoder->base.id, encoder->name);
d2dff872 10331
8261b191 10332 if (old->load_detect_temp) {
83a57153 10333 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10334 if (!state)
10335 goto fail;
83a57153
ACO		 10336
10337 state->acquire_ctx = ctx;
10338
944b0c76
ACO		 10339 connector_state = drm_atomic_get_connector_state(state, connector);
10340 if (IS_ERR(connector_state))
10341 goto fail;
10342
4be07317
ACO		 10343 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10344 if (IS_ERR(crtc_state))
10345 goto fail;
10346
944b0c76
ACO		 10347 connector_state->best_encoder = NULL;
10348 connector_state->crtc = NULL;
10349
49d6fa21 10350 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10351
d3a40d1b
ACO		 10352 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10353 0, 0);
10354 if (ret)
10355 goto fail;
10356
74c090b1 10357 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10358 if (ret)
10359 goto fail;
d2dff872 10360
36206361
DV		 10361 if (old->release_fb) {
10362 drm_framebuffer_unregister_private(old->release_fb);
10363 drm_framebuffer_unreference(old->release_fb);
10364 }
d2dff872 10365
0622a53c 10366 return;
79e53945
JB		 10367 }
10368
c751ce4f 10369 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10370 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10371 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10372
10373 return;
10374fail:
10375 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10376 drm_atomic_state_free(state);
79e53945
JB		 10377}
10378
da4a1efa 10379static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10380 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10381{
10382 struct drm_i915_private *dev_priv = dev->dev_private;
10383 u32 dpll = pipe_config->dpll_hw_state.dpll;
10384
10385 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10386 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10387 else if (HAS_PCH_SPLIT(dev))
10388 return 120000;
10389 else if (!IS_GEN2(dev))
10390 return 96000;
10391 else
10392 return 48000;
10393}
10394
79e53945 10395/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10396static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10397 struct intel_crtc_state *pipe_config)
79e53945 10398{
f1f644dc 10399 struct drm_device *dev = crtc->base.dev;
79e53945 10400 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10401 int pipe = pipe_config->cpu_transcoder;
293623f7 10402 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10403 u32 fp;
10404 intel_clock_t clock;
dccbea3b 10405 int port_clock;
da4a1efa 10406 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10407
10408 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10409 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10410 else
293623f7 10411 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10412
10413 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10414 if (IS_PINEVIEW(dev)) {
10415 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10416 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10417 } else {
10418 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10419 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10420 }
10421
a6c45cf0 10422 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10423 if (IS_PINEVIEW(dev))
10424 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10425 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10426 else
10427 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10428 DPLL_FPA01_P1_POST_DIV_SHIFT);
10429
10430 switch (dpll & DPLL_MODE_MASK) {
10431 case DPLLB_MODE_DAC_SERIAL:
10432 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10433 5 : 10;
10434 break;
10435 case DPLLB_MODE_LVDS:
10436 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10437 7 : 14;
10438 break;
10439 default:
28c97730 10440 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10441 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10442 return;
79e53945
JB		 10443 }
10444
ac58c3f0 10445 if (IS_PINEVIEW(dev))
dccbea3b 10446 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10447 else
dccbea3b 10448 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10449 } else {
0fb58223 10450 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10451 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10452
10453 if (is_lvds) {
10454 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10455 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10456
10457 if (lvds & LVDS_CLKB_POWER_UP)
10458 clock.p2 = 7;
10459 else
10460 clock.p2 = 14;
79e53945
JB		 10461 } else {
10462 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10463 clock.p1 = 2;
10464 else {
10465 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10466 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10467 }
10468 if (dpll & PLL_P2_DIVIDE_BY_4)
10469 clock.p2 = 4;
10470 else
10471 clock.p2 = 2;
79e53945 10472 }
da4a1efa 10473
dccbea3b 10474 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10475 }
10476
18442d08
VS		 10477 /*
10478 * This value includes pixel_multiplier. We will use
241bfc38 10479 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10480 * encoder's get_config() function.
10481 */
dccbea3b 10482 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10483}
10484
6878da05
VS		 10485int intel_dotclock_calculate(int link_freq,
10486 const struct intel_link_m_n *m_n)
f1f644dc 10487{
f1f644dc
JB		 10488 /*
10489 * The calculation for the data clock is:
1041a02f 10490 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10491 * But we want to avoid losing precison if possible, so:
1041a02f 10492 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10493 *
10494 * and the link clock is simpler:
1041a02f 10495 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10496 */
10497
6878da05
VS		 10498 if (!m_n->link_n)
10499 return 0;
f1f644dc 10500
6878da05
VS		 10501 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10502}
f1f644dc 10503
18442d08 10504static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10505 struct intel_crtc_state *pipe_config)
6878da05
VS		 10506{
10507 struct drm_device *dev = crtc->base.dev;
79e53945 10508
18442d08
VS		 10509 /* read out port_clock from the DPLL */
10510 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10511
f1f644dc 10512 /*
18442d08 10513 * This value does not include pixel_multiplier.
241bfc38 10514 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10515 * agree once we know their relationship in the encoder's
10516 * get_config() function.
79e53945 10517 */
2d112de7 10518 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10519 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10520 &pipe_config->fdi_m_n);
79e53945
JB		 10521}
10522
10523/** Returns the currently programmed mode of the given pipe. */
10524struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10525 struct drm_crtc *crtc)
10526{
548f245b 10527 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10529 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10530 struct drm_display_mode *mode;
5cec258b 10531 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10532 int htot = I915_READ(HTOTAL(cpu_transcoder));
10533 int hsync = I915_READ(HSYNC(cpu_transcoder));
10534 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10535 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10536 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10537
10538 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10539 if (!mode)
10540 return NULL;
10541
f1f644dc
JB		 10542 /*
10543 * Construct a pipe_config sufficient for getting the clock info
10544 * back out of crtc_clock_get.
10545 *
10546 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10547 * to use a real value here instead.
10548 */
293623f7 10549 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10550 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10551 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10552 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10553 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10554 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10555
773ae034 10556 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10557 mode->hdisplay = (htot & 0xffff) + 1;
10558 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10559 mode->hsync_start = (hsync & 0xffff) + 1;
10560 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10561 mode->vdisplay = (vtot & 0xffff) + 1;
10562 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10563 mode->vsync_start = (vsync & 0xffff) + 1;
10564 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10565
10566 drm_mode_set_name(mode);
79e53945
JB		 10567
10568 return mode;
10569}
10570
f047e395
CW		 10571void intel_mark_busy(struct drm_device *dev)
10572{
c67a470b
PZ		 10573 struct drm_i915_private *dev_priv = dev->dev_private;
10574
f62a0076
CW		 10575 if (dev_priv->mm.busy)
10576 return;
10577
43694d69 10578 intel_runtime_pm_get(dev_priv);
c67a470b 10579 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10580 if (INTEL_INFO(dev)->gen >= 6)
10581 gen6_rps_busy(dev_priv);
f62a0076 10582 dev_priv->mm.busy = true;
f047e395
CW		 10583}
10584
10585void intel_mark_idle(struct drm_device *dev)
652c393a 10586{
c67a470b 10587 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10588
f62a0076
CW		 10589 if (!dev_priv->mm.busy)
10590 return;
10591
10592 dev_priv->mm.busy = false;
10593
3d13ef2e 10594 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10595 gen6_rps_idle(dev->dev_private);
bb4cdd53 10596
43694d69 10597 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10598}
10599
79e53945
JB		 10600static void intel_crtc_destroy(struct drm_crtc *crtc)
10601{
10602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10603 struct drm_device *dev = crtc->dev;
10604 struct intel_unpin_work *work;
67e77c5a 10605
5e2d7afc 10606 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10607 work = intel_crtc->unpin_work;
10608 intel_crtc->unpin_work = NULL;
5e2d7afc 10609 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10610
10611 if (work) {
10612 cancel_work_sync(&work->work);
10613 kfree(work);
10614 }
79e53945
JB		 10615
10616 drm_crtc_cleanup(crtc);
67e77c5a 10617
79e53945
JB		 10618 kfree(intel_crtc);
10619}
10620
6b95a207
KH		 10621static void intel_unpin_work_fn(struct work_struct *__work)
10622{
10623 struct intel_unpin_work *work =
10624 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10625 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10626 struct drm_device *dev = crtc->base.dev;
10627 struct drm_plane *primary = crtc->base.primary;
6b95a207 10628
b4a98e57 10629 mutex_lock(&dev->struct_mutex);
a9ff8714 10630 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10631 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10632
f06cc1b9 10633 if (work->flip_queued_req)
146d84f0 10634 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10635 mutex_unlock(&dev->struct_mutex);
10636
a9ff8714 10637 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10638 drm_framebuffer_unreference(work->old_fb);
f99d7069 10639
a9ff8714
VS		 10640 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10641 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10642
6b95a207
KH		 10643 kfree(work);
10644}
10645
1afe3e9d 10646static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10647 struct drm_crtc *crtc)
6b95a207 10648{
6b95a207
KH		 10649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10650 struct intel_unpin_work *work;
6b95a207
KH		 10651 unsigned long flags;
10652
10653 /* Ignore early vblank irqs */
10654 if (intel_crtc == NULL)
10655 return;
10656
f326038a
DV		 10657 /*
10658 * This is called both by irq handlers and the reset code (to complete
10659 * lost pageflips) so needs the full irqsave spinlocks.
10660 */
6b95a207
KH		 10661 spin_lock_irqsave(&dev->event_lock, flags);
10662 work = intel_crtc->unpin_work;
e7d841ca
CW		 10663
10664 /* Ensure we don't miss a work->pending update ... */
10665 smp_rmb();
10666
10667 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10668 spin_unlock_irqrestore(&dev->event_lock, flags);
10669 return;
10670 }
10671
d6bbafa1 10672 page_flip_completed(intel_crtc);
0af7e4df 10673
6b95a207 10674 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10675}
10676
1afe3e9d
JB		 10677void intel_finish_page_flip(struct drm_device *dev, int pipe)
10678{
fbee40df 10679 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10680 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10681
49b14a5c 10682 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10683}
10684
10685void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10686{
fbee40df 10687 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10688 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10689
49b14a5c 10690 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10691}
10692
75f7f3ec
VS		 10693/* Is 'a' after or equal to 'b'? */
10694static bool g4x_flip_count_after_eq(u32 a, u32 b)
10695{
10696 return !((a - b) & 0x80000000);
10697}
10698
10699static bool page_flip_finished(struct intel_crtc *crtc)
10700{
10701 struct drm_device *dev = crtc->base.dev;
10702 struct drm_i915_private *dev_priv = dev->dev_private;
10703
bdfa7542
VS		 10704 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10705 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10706 return true;
10707
75f7f3ec
VS		 10708 /*
10709 * The relevant registers doen't exist on pre-ctg.
10710 * As the flip done interrupt doesn't trigger for mmio
10711 * flips on gmch platforms, a flip count check isn't
10712 * really needed there. But since ctg has the registers,
10713 * include it in the check anyway.
10714 */
10715 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10716 return true;
10717
10718 /*
10719 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10720 * used the same base address. In that case the mmio flip might
10721 * have completed, but the CS hasn't even executed the flip yet.
10722 *
10723 * A flip count check isn't enough as the CS might have updated
10724 * the base address just after start of vblank, but before we
10725 * managed to process the interrupt. This means we'd complete the
10726 * CS flip too soon.
10727 *
10728 * Combining both checks should get us a good enough result. It may
10729 * still happen that the CS flip has been executed, but has not
10730 * yet actually completed. But in case the base address is the same
10731 * anyway, we don't really care.
10732 */
10733 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10734 crtc->unpin_work->gtt_offset &&
10735 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10736 crtc->unpin_work->flip_count);
10737}
10738
6b95a207
KH		 10739void intel_prepare_page_flip(struct drm_device *dev, int plane)
10740{
fbee40df 10741 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10742 struct intel_crtc *intel_crtc =
10743 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10744 unsigned long flags;
10745
f326038a
DV		 10746
10747 /*
10748 * This is called both by irq handlers and the reset code (to complete
10749 * lost pageflips) so needs the full irqsave spinlocks.
10750 *
10751 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10752 * generate a page-flip completion irq, i.e. every modeset
10753 * is also accompanied by a spurious intel_prepare_page_flip().
10754 */
6b95a207 10755 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10756 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10757 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10758 spin_unlock_irqrestore(&dev->event_lock, flags);
10759}
10760
eba905b2 10761static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10762{
10763 /* Ensure that the work item is consistent when activating it ... */
10764 smp_wmb();
10765 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10766 /* and that it is marked active as soon as the irq could fire. */
10767 smp_wmb();
10768}
10769
8c9f3aaf
JB		 10770static int intel_gen2_queue_flip(struct drm_device *dev,
10771 struct drm_crtc *crtc,
10772 struct drm_framebuffer *fb,
ed8d1975 10773 struct drm_i915_gem_object *obj,
6258fbe2 10774 struct drm_i915_gem_request *req,
ed8d1975 10775 uint32_t flags)
8c9f3aaf 10776{
6258fbe2 10777 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10779 u32 flip_mask;
10780 int ret;
10781
5fb9de1a 10782 ret = intel_ring_begin(req, 6);
8c9f3aaf 10783 if (ret)
4fa62c89 10784 return ret;
8c9f3aaf
JB		 10785
10786 /* Can't queue multiple flips, so wait for the previous
10787 * one to finish before executing the next.
10788 */
10789 if (intel_crtc->plane)
10790 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10791 else
10792 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10793 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10794 intel_ring_emit(ring, MI_NOOP);
10795 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10796 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10797 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10798 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10799 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10800
10801 intel_mark_page_flip_active(intel_crtc);
83d4092b 10802 return 0;
8c9f3aaf
JB		 10803}
10804
10805static int intel_gen3_queue_flip(struct drm_device *dev,
10806 struct drm_crtc *crtc,
10807 struct drm_framebuffer *fb,
ed8d1975 10808 struct drm_i915_gem_object *obj,
6258fbe2 10809 struct drm_i915_gem_request *req,
ed8d1975 10810 uint32_t flags)
8c9f3aaf 10811{
6258fbe2 10812 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10814 u32 flip_mask;
10815 int ret;
10816
5fb9de1a 10817 ret = intel_ring_begin(req, 6);
8c9f3aaf 10818 if (ret)
4fa62c89 10819 return ret;
8c9f3aaf
JB		 10820
10821 if (intel_crtc->plane)
10822 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10823 else
10824 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10825 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10826 intel_ring_emit(ring, MI_NOOP);
10827 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10828 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10829 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10830 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10831 intel_ring_emit(ring, MI_NOOP);
10832
e7d841ca 10833 intel_mark_page_flip_active(intel_crtc);
83d4092b 10834 return 0;
8c9f3aaf
JB		 10835}
10836
10837static int intel_gen4_queue_flip(struct drm_device *dev,
10838 struct drm_crtc *crtc,
10839 struct drm_framebuffer *fb,
ed8d1975 10840 struct drm_i915_gem_object *obj,
6258fbe2 10841 struct drm_i915_gem_request *req,
ed8d1975 10842 uint32_t flags)
8c9f3aaf 10843{
6258fbe2 10844 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10845 struct drm_i915_private *dev_priv = dev->dev_private;
10846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10847 uint32_t pf, pipesrc;
10848 int ret;
10849
5fb9de1a 10850 ret = intel_ring_begin(req, 4);
8c9f3aaf 10851 if (ret)
4fa62c89 10852 return ret;
8c9f3aaf
JB		 10853
10854 /* i965+ uses the linear or tiled offsets from the
10855 * Display Registers (which do not change across a page-flip)
10856 * so we need only reprogram the base address.
10857 */
6d90c952
DV		 10858 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10859 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10860 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10861 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10862 obj->tiling_mode);
8c9f3aaf
JB		 10863
10864 /* XXX Enabling the panel-fitter across page-flip is so far
10865 * untested on non-native modes, so ignore it for now.
10866 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10867 */
10868 pf = 0;
10869 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10870 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10871
10872 intel_mark_page_flip_active(intel_crtc);
83d4092b 10873 return 0;
8c9f3aaf
JB		 10874}
10875
10876static int intel_gen6_queue_flip(struct drm_device *dev,
10877 struct drm_crtc *crtc,
10878 struct drm_framebuffer *fb,
ed8d1975 10879 struct drm_i915_gem_object *obj,
6258fbe2 10880 struct drm_i915_gem_request *req,
ed8d1975 10881 uint32_t flags)
8c9f3aaf 10882{
6258fbe2 10883 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10884 struct drm_i915_private *dev_priv = dev->dev_private;
10885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10886 uint32_t pf, pipesrc;
10887 int ret;
10888
5fb9de1a 10889 ret = intel_ring_begin(req, 4);
8c9f3aaf 10890 if (ret)
4fa62c89 10891 return ret;
8c9f3aaf 10892
6d90c952
DV		 10893 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10894 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10895 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10896 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10897
dc257cf1
DV		 10898 /* Contrary to the suggestions in the documentation,
10899 * "Enable Panel Fitter" does not seem to be required when page
10900 * flipping with a non-native mode, and worse causes a normal
10901 * modeset to fail.
10902 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10903 */
10904 pf = 0;
8c9f3aaf 10905 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10906 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10907
10908 intel_mark_page_flip_active(intel_crtc);
83d4092b 10909 return 0;
8c9f3aaf
JB		 10910}
10911
7c9017e5
JB		 10912static int intel_gen7_queue_flip(struct drm_device *dev,
10913 struct drm_crtc *crtc,
10914 struct drm_framebuffer *fb,
ed8d1975 10915 struct drm_i915_gem_object *obj,
6258fbe2 10916 struct drm_i915_gem_request *req,
ed8d1975 10917 uint32_t flags)
7c9017e5 10918{
6258fbe2 10919 struct intel_engine_cs *ring = req->ring;
7c9017e5 10920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10921 uint32_t plane_bit = 0;
ffe74d75
CW		 10922 int len, ret;
10923
eba905b2 10924 switch (intel_crtc->plane) {
cb05d8de
DV		 10925 case PLANE_A:
10926 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10927 break;
10928 case PLANE_B:
10929 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10930 break;
10931 case PLANE_C:
10932 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10933 break;
10934 default:
10935 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10936 return -ENODEV;
cb05d8de
DV		 10937 }
10938
ffe74d75 10939 len = 4;
f476828a 10940 if (ring->id == RCS) {
ffe74d75 10941 len += 6;
f476828a
DL		 10942 /*
10943 * On Gen 8, SRM is now taking an extra dword to accommodate
10944 * 48bits addresses, and we need a NOOP for the batch size to
10945 * stay even.
10946 */
10947 if (IS_GEN8(dev))
10948 len += 2;
10949 }
ffe74d75 10950
f66fab8e
VS		 10951 /*
10952 * BSpec MI_DISPLAY_FLIP for IVB:
10953 * "The full packet must be contained within the same cache line."
10954 *
10955 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10956 * cacheline, if we ever start emitting more commands before
10957 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10958 * then do the cacheline alignment, and finally emit the
10959 * MI_DISPLAY_FLIP.
10960 */
bba09b12 10961 ret = intel_ring_cacheline_align(req);
f66fab8e 10962 if (ret)
4fa62c89 10963 return ret;
f66fab8e 10964
5fb9de1a 10965 ret = intel_ring_begin(req, len);
7c9017e5 10966 if (ret)
4fa62c89 10967 return ret;
7c9017e5 10968
ffe74d75
CW		 10969 /* Unmask the flip-done completion message. Note that the bspec says that
10970 * we should do this for both the BCS and RCS, and that we must not unmask
10971 * more than one flip event at any time (or ensure that one flip message
10972 * can be sent by waiting for flip-done prior to queueing new flips).
10973 * Experimentation says that BCS works despite DERRMR masking all
10974 * flip-done completion events and that unmasking all planes at once
10975 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10976 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10977 */
10978 if (ring->id == RCS) {
10979 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10980 intel_ring_emit(ring, DERRMR);
10981 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10982 DERRMR_PIPEB_PRI_FLIP_DONE |
10983 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 10984 if (IS_GEN8(dev))
f1afe24f 10985 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 10986 MI_SRM_LRM_GLOBAL_GTT);
10987 else
f1afe24f 10988 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 10989 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10990 intel_ring_emit(ring, DERRMR);
10991 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10992 if (IS_GEN8(dev)) {
10993 intel_ring_emit(ring, 0);
10994 intel_ring_emit(ring, MI_NOOP);
10995 }
ffe74d75
CW		 10996 }
10997
cb05d8de 10998 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10999 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11000 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11001 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11002
11003 intel_mark_page_flip_active(intel_crtc);
83d4092b 11004 return 0;
7c9017e5
JB		 11005}
11006
84c33a64
SG		 11007static bool use_mmio_flip(struct intel_engine_cs *ring,
11008 struct drm_i915_gem_object *obj)
11009{
11010 /*
11011 * This is not being used for older platforms, because
11012 * non-availability of flip done interrupt forces us to use
11013 * CS flips. Older platforms derive flip done using some clever
11014 * tricks involving the flip_pending status bits and vblank irqs.
11015 * So using MMIO flips there would disrupt this mechanism.
11016 */
11017
8e09bf83
CW		 11018 if (ring == NULL)
11019 return true;
11020
84c33a64
SG		 11021 if (INTEL_INFO(ring->dev)->gen < 5)
11022 return false;
11023
11024 if (i915.use_mmio_flip < 0)
11025 return false;
11026 else if (i915.use_mmio_flip > 0)
11027 return true;
14bf993e
OM		 11028 else if (i915.enable_execlists)
11029 return true;
84c33a64 11030 else
b4716185 11031 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11032}
11033
ff944564
DL		 11034static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11035{
11036 struct drm_device *dev = intel_crtc->base.dev;
11037 struct drm_i915_private *dev_priv = dev->dev_private;
11038 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11039 const enum pipe pipe = intel_crtc->pipe;
11040 u32 ctl, stride;
11041
11042 ctl = I915_READ(PLANE_CTL(pipe, 0));
11043 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11044 switch (fb->modifier[0]) {
11045 case DRM_FORMAT_MOD_NONE:
11046 break;
11047 case I915_FORMAT_MOD_X_TILED:
ff944564 11048 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11049 break;
11050 case I915_FORMAT_MOD_Y_TILED:
11051 ctl |= PLANE_CTL_TILED_Y;
11052 break;
11053 case I915_FORMAT_MOD_Yf_TILED:
11054 ctl |= PLANE_CTL_TILED_YF;
11055 break;
11056 default:
11057 MISSING_CASE(fb->modifier[0]);
11058 }
ff944564
DL		 11059
11060 /*
11061 * The stride is either expressed as a multiple of 64 bytes chunks for
11062 * linear buffers or in number of tiles for tiled buffers.
11063 */
2ebef630
TU		 11064 stride = fb->pitches[0] /
11065 intel_fb_stride_alignment(dev, fb->modifier[0],
11066 fb->pixel_format);
ff944564
DL		 11067
11068 /*
11069 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11070 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11071 */
11072 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11073 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11074
11075 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11076 POSTING_READ(PLANE_SURF(pipe, 0));
11077}
11078
11079static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11080{
11081 struct drm_device *dev = intel_crtc->base.dev;
11082 struct drm_i915_private *dev_priv = dev->dev_private;
11083 struct intel_framebuffer *intel_fb =
11084 to_intel_framebuffer(intel_crtc->base.primary->fb);
11085 struct drm_i915_gem_object *obj = intel_fb->obj;
11086 u32 dspcntr;
11087 u32 reg;
11088
84c33a64
SG		 11089 reg = DSPCNTR(intel_crtc->plane);
11090 dspcntr = I915_READ(reg);
11091
c5d97472
DL		 11092 if (obj->tiling_mode != I915_TILING_NONE)
11093 dspcntr |= DISPPLANE_TILED;
11094 else
11095 dspcntr &= ~DISPPLANE_TILED;
11096
84c33a64
SG		 11097 I915_WRITE(reg, dspcntr);
11098
11099 I915_WRITE(DSPSURF(intel_crtc->plane),
11100 intel_crtc->unpin_work->gtt_offset);
11101 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11102
ff944564
DL		 11103}
11104
11105/*
11106 * XXX: This is the temporary way to update the plane registers until we get
11107 * around to using the usual plane update functions for MMIO flips
11108 */
11109static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11110{
11111 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11112 u32 start_vbl_count;
11113
11114 intel_mark_page_flip_active(intel_crtc);
11115
8f539a83 11116 intel_pipe_update_start(intel_crtc, &start_vbl_count);
ff944564
DL		 11117
11118 if (INTEL_INFO(dev)->gen >= 9)
11119 skl_do_mmio_flip(intel_crtc);
11120 else
11121 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11122 ilk_do_mmio_flip(intel_crtc);
11123
8f539a83 11124 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11125}
11126
9362c7c5 11127static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11128{
b2cfe0ab
CW		 11129 struct intel_mmio_flip *mmio_flip =
11130 container_of(work, struct intel_mmio_flip, work);
84c33a64 11131
eed29a5b
DV		 11132 if (mmio_flip->req)
11133 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11134 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11135 false, NULL,
11136 &mmio_flip->i915->rps.mmioflips));
84c33a64 11137
b2cfe0ab
CW		 11138 intel_do_mmio_flip(mmio_flip->crtc);
11139
eed29a5b 11140 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11141 kfree(mmio_flip);
84c33a64
SG		 11142}
11143
11144static int intel_queue_mmio_flip(struct drm_device *dev,
11145 struct drm_crtc *crtc,
11146 struct drm_framebuffer *fb,
11147 struct drm_i915_gem_object *obj,
11148 struct intel_engine_cs *ring,
11149 uint32_t flags)
11150{
b2cfe0ab
CW		 11151 struct intel_mmio_flip *mmio_flip;
11152
11153 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11154 if (mmio_flip == NULL)
11155 return -ENOMEM;
84c33a64 11156
bcafc4e3 11157 mmio_flip->i915 = to_i915(dev);
eed29a5b 11158 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11159 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11160
b2cfe0ab
CW		 11161 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11162 schedule_work(&mmio_flip->work);
84c33a64 11163
84c33a64
SG		 11164 return 0;
11165}
11166
8c9f3aaf
JB		 11167static int intel_default_queue_flip(struct drm_device *dev,
11168 struct drm_crtc *crtc,
11169 struct drm_framebuffer *fb,
ed8d1975 11170 struct drm_i915_gem_object *obj,
6258fbe2 11171 struct drm_i915_gem_request *req,
ed8d1975 11172 uint32_t flags)
8c9f3aaf
JB		 11173{
11174 return -ENODEV;
11175}
11176
d6bbafa1
CW		 11177static bool __intel_pageflip_stall_check(struct drm_device *dev,
11178 struct drm_crtc *crtc)
11179{
11180 struct drm_i915_private *dev_priv = dev->dev_private;
11181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11182 struct intel_unpin_work *work = intel_crtc->unpin_work;
11183 u32 addr;
11184
11185 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11186 return true;
11187
908565c2
CW		 11188 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11189 return false;
11190
d6bbafa1
CW		 11191 if (!work->enable_stall_check)
11192 return false;
11193
11194 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11195 if (work->flip_queued_req &&
11196 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11197 return false;
11198
1e3feefd 11199 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11200 }
11201
1e3feefd 11202 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11203 return false;
11204
11205 /* Potential stall - if we see that the flip has happened,
11206 * assume a missed interrupt. */
11207 if (INTEL_INFO(dev)->gen >= 4)
11208 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11209 else
11210 addr = I915_READ(DSPADDR(intel_crtc->plane));
11211
11212 /* There is a potential issue here with a false positive after a flip
11213 * to the same address. We could address this by checking for a
11214 * non-incrementing frame counter.
11215 */
11216 return addr == work->gtt_offset;
11217}
11218
11219void intel_check_page_flip(struct drm_device *dev, int pipe)
11220{
11221 struct drm_i915_private *dev_priv = dev->dev_private;
11222 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11224 struct intel_unpin_work *work;
f326038a 11225
6c51d46f 11226 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11227
11228 if (crtc == NULL)
11229 return;
11230
f326038a 11231 spin_lock(&dev->event_lock);
6ad790c0
CW		 11232 work = intel_crtc->unpin_work;
11233 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11234 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11235 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11236 page_flip_completed(intel_crtc);
6ad790c0 11237 work = NULL;
d6bbafa1 11238 }
6ad790c0
CW		 11239 if (work != NULL &&
11240 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11241 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11242 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11243}
11244
6b95a207
KH		 11245static int intel_crtc_page_flip(struct drm_crtc *crtc,
11246 struct drm_framebuffer *fb,
ed8d1975
KP		 11247 struct drm_pending_vblank_event *event,
11248 uint32_t page_flip_flags)
6b95a207
KH		 11249{
11250 struct drm_device *dev = crtc->dev;
11251 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11252 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11253 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11255 struct drm_plane *primary = crtc->primary;
a071fa00 11256 enum pipe pipe = intel_crtc->pipe;
6b95a207 11257 struct intel_unpin_work *work;
a4872ba6 11258 struct intel_engine_cs *ring;
cf5d8a46 11259 bool mmio_flip;
91af127f 11260 struct drm_i915_gem_request *request = NULL;
52e68630 11261 int ret;
6b95a207 11262
2ff8fde1
MR		 11263 /*
11264 * drm_mode_page_flip_ioctl() should already catch this, but double
11265 * check to be safe. In the future we may enable pageflipping from
11266 * a disabled primary plane.
11267 */
11268 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11269 return -EBUSY;
11270
e6a595d2 11271 /* Can't change pixel format via MI display flips. */
f4510a27 11272 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11273 return -EINVAL;
11274
11275 /*
11276 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11277 * Note that pitch changes could also affect these register.
11278 */
11279 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11280 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11281 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11282 return -EINVAL;
11283
f900db47
CW		 11284 if (i915_terminally_wedged(&dev_priv->gpu_error))
11285 goto out_hang;
11286
b14c5679 11287 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11288 if (work == NULL)
11289 return -ENOMEM;
11290
6b95a207 11291 work->event = event;
b4a98e57 11292 work->crtc = crtc;
ab8d6675 11293 work->old_fb = old_fb;
6b95a207
KH		 11294 INIT_WORK(&work->work, intel_unpin_work_fn);
11295
87b6b101 11296 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11297 if (ret)
11298 goto free_work;
11299
6b95a207 11300 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11301 spin_lock_irq(&dev->event_lock);
6b95a207 11302 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11303 /* Before declaring the flip queue wedged, check if
11304 * the hardware completed the operation behind our backs.
11305 */
11306 if (__intel_pageflip_stall_check(dev, crtc)) {
11307 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11308 page_flip_completed(intel_crtc);
11309 } else {
11310 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11311 spin_unlock_irq(&dev->event_lock);
468f0b44 11312
d6bbafa1
CW		 11313 drm_crtc_vblank_put(crtc);
11314 kfree(work);
11315 return -EBUSY;
11316 }
6b95a207
KH		 11317 }
11318 intel_crtc->unpin_work = work;
5e2d7afc 11319 spin_unlock_irq(&dev->event_lock);
6b95a207 11320
b4a98e57
CW		 11321 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11322 flush_workqueue(dev_priv->wq);
11323
75dfca80 11324 /* Reference the objects for the scheduled work. */
ab8d6675 11325 drm_framebuffer_reference(work->old_fb);
05394f39 11326 drm_gem_object_reference(&obj->base);
6b95a207 11327
f4510a27 11328 crtc->primary->fb = fb;
afd65eb4 11329 update_state_fb(crtc->primary);
1ed1f968 11330
e1f99ce6 11331 work->pending_flip_obj = obj;
e1f99ce6 11332
89ed88ba
CW		 11333 ret = i915_mutex_lock_interruptible(dev);
11334 if (ret)
11335 goto cleanup;
11336
b4a98e57 11337 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11338 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11339
75f7f3ec 11340 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11341 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11342
4fa62c89
VS		 11343 if (IS_VALLEYVIEW(dev)) {
11344 ring = &dev_priv->ring[BCS];
ab8d6675 11345 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11346 /* vlv: DISPLAY_FLIP fails to change tiling */
11347 ring = NULL;
48bf5b2d 11348 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11349 ring = &dev_priv->ring[BCS];
4fa62c89 11350 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11351 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11352 if (ring == NULL || ring->id != RCS)
11353 ring = &dev_priv->ring[BCS];
11354 } else {
11355 ring = &dev_priv->ring[RCS];
11356 }
11357
cf5d8a46
CW		 11358 mmio_flip = use_mmio_flip(ring, obj);
11359
11360 /* When using CS flips, we want to emit semaphores between rings.
11361 * However, when using mmio flips we will create a task to do the
11362 * synchronisation, so all we want here is to pin the framebuffer
11363 * into the display plane and skip any waits.
11364 */
82bc3b2d 11365 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11366 crtc->primary->state,
91af127f 11367 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11368 if (ret)
11369 goto cleanup_pending;
6b95a207 11370
121920fa
TU		 11371 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11372 + intel_crtc->dspaddr_offset;
4fa62c89 11373
cf5d8a46 11374 if (mmio_flip) {
84c33a64
SG		 11375 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11376 page_flip_flags);
d6bbafa1
CW		 11377 if (ret)
11378 goto cleanup_unpin;
11379
f06cc1b9
JH		 11380 i915_gem_request_assign(&work->flip_queued_req,
11381 obj->last_write_req);
d6bbafa1 11382 } else {
6258fbe2
JH		 11383 if (!request) {
11384 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11385 if (ret)
11386 goto cleanup_unpin;
11387 }
11388
11389 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11390 page_flip_flags);
11391 if (ret)
11392 goto cleanup_unpin;
11393
6258fbe2 11394 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11395 }
11396
91af127f 11397 if (request)
75289874 11398 i915_add_request_no_flush(request);
91af127f 11399
1e3feefd 11400 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11401 work->enable_stall_check = true;
4fa62c89 11402
ab8d6675 11403 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11404 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11405 mutex_unlock(&dev->struct_mutex);
a071fa00 11406
4e1e26f1 11407 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11408 intel_frontbuffer_flip_prepare(dev,
11409 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11410
e5510fac
JB		 11411 trace_i915_flip_request(intel_crtc->plane, obj);
11412
6b95a207 11413 return 0;
96b099fd 11414
4fa62c89 11415cleanup_unpin:
82bc3b2d 11416 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11417cleanup_pending:
91af127f
JH		 11418 if (request)
11419 i915_gem_request_cancel(request);
b4a98e57 11420 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11421 mutex_unlock(&dev->struct_mutex);
11422cleanup:
f4510a27 11423 crtc->primary->fb = old_fb;
afd65eb4 11424 update_state_fb(crtc->primary);
89ed88ba
CW		 11425
11426 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11427 drm_framebuffer_unreference(work->old_fb);
96b099fd 11428
5e2d7afc 11429 spin_lock_irq(&dev->event_lock);
96b099fd 11430 intel_crtc->unpin_work = NULL;
5e2d7afc 11431 spin_unlock_irq(&dev->event_lock);
96b099fd 11432
87b6b101 11433 drm_crtc_vblank_put(crtc);
7317c75e 11434free_work:
96b099fd
CW		 11435 kfree(work);
11436
f900db47 11437 if (ret == -EIO) {
02e0efb5
ML		 11438 struct drm_atomic_state *state;
11439 struct drm_plane_state *plane_state;
11440
f900db47 11441out_hang:
02e0efb5
ML		 11442 state = drm_atomic_state_alloc(dev);
11443 if (!state)
11444 return -ENOMEM;
11445 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11446
11447retry:
11448 plane_state = drm_atomic_get_plane_state(state, primary);
11449 ret = PTR_ERR_OR_ZERO(plane_state);
11450 if (!ret) {
11451 drm_atomic_set_fb_for_plane(plane_state, fb);
11452
11453 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11454 if (!ret)
11455 ret = drm_atomic_commit(state);
11456 }
11457
11458 if (ret == -EDEADLK) {
11459 drm_modeset_backoff(state->acquire_ctx);
11460 drm_atomic_state_clear(state);
11461 goto retry;
11462 }
11463
11464 if (ret)
11465 drm_atomic_state_free(state);
11466
f0d3dad3 11467 if (ret == 0 && event) {
5e2d7afc 11468 spin_lock_irq(&dev->event_lock);
a071fa00 11469 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11470 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11471 }
f900db47 11472 }
96b099fd 11473 return ret;
6b95a207
KH		 11474}
11475
da20eabd
ML		 11476
11477/**
11478 * intel_wm_need_update - Check whether watermarks need updating
11479 * @plane: drm plane
11480 * @state: new plane state
11481 *
11482 * Check current plane state versus the new one to determine whether
11483 * watermarks need to be recalculated.
11484 *
11485 * Returns true or false.
11486 */
11487static bool intel_wm_need_update(struct drm_plane *plane,
11488 struct drm_plane_state *state)
11489{
11490 /* Update watermarks on tiling changes. */
11491 if (!plane->state->fb || !state->fb ||
11492 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11493 plane->state->rotation != state->rotation)
11494 return true;
11495
11496 if (plane->state->crtc_w != state->crtc_w)
11497 return true;
11498
11499 return false;
11500}
11501
11502int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11503 struct drm_plane_state *plane_state)
11504{
11505 struct drm_crtc *crtc = crtc_state->crtc;
11506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11507 struct drm_plane *plane = plane_state->plane;
11508 struct drm_device *dev = crtc->dev;
11509 struct drm_i915_private *dev_priv = dev->dev_private;
11510 struct intel_plane_state *old_plane_state =
11511 to_intel_plane_state(plane->state);
11512 int idx = intel_crtc->base.base.id, ret;
11513 int i = drm_plane_index(plane);
11514 bool mode_changed = needs_modeset(crtc_state);
11515 bool was_crtc_enabled = crtc->state->active;
11516 bool is_crtc_enabled = crtc_state->active;
11517
11518 bool turn_off, turn_on, visible, was_visible;
11519 struct drm_framebuffer *fb = plane_state->fb;
11520
11521 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11522 plane->type != DRM_PLANE_TYPE_CURSOR) {
11523 ret = skl_update_scaler_plane(
11524 to_intel_crtc_state(crtc_state),
11525 to_intel_plane_state(plane_state));
11526 if (ret)
11527 return ret;
11528 }
11529
11530 /*
11531 * Disabling a plane is always okay; we just need to update
11532 * fb tracking in a special way since cleanup_fb() won't
11533 * get called by the plane helpers.
11534 */
11535 if (old_plane_state->base.fb && !fb)
11536 intel_crtc->atomic.disabled_planes |= 1 << i;
11537
da20eabd
ML		 11538 was_visible = old_plane_state->visible;
11539 visible = to_intel_plane_state(plane_state)->visible;
11540
11541 if (!was_crtc_enabled && WARN_ON(was_visible))
11542 was_visible = false;
11543
11544 if (!is_crtc_enabled && WARN_ON(visible))
11545 visible = false;
11546
11547 if (!was_visible && !visible)
11548 return 0;
11549
11550 turn_off = was_visible && (!visible || mode_changed);
11551 turn_on = visible && (!was_visible || mode_changed);
11552
11553 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11554 plane->base.id, fb ? fb->base.id : -1);
11555
11556 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11557 plane->base.id, was_visible, visible,
11558 turn_off, turn_on, mode_changed);
11559
852eb00d 11560 if (turn_on) {
f015c551 11561 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11562 /* must disable cxsr around plane enable/disable */
11563 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11564 intel_crtc->atomic.disable_cxsr = true;
11565 /* to potentially re-enable cxsr */
11566 intel_crtc->atomic.wait_vblank = true;
11567 intel_crtc->atomic.update_wm_post = true;
11568 }
11569 } else if (turn_off) {
f015c551 11570 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11571 /* must disable cxsr around plane enable/disable */
11572 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11573 if (is_crtc_enabled)
11574 intel_crtc->atomic.wait_vblank = true;
11575 intel_crtc->atomic.disable_cxsr = true;
11576 }
11577 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11578 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11579 }
da20eabd 11580
8be6ca85 11581 if (visible || was_visible)
a9ff8714
VS		 11582 intel_crtc->atomic.fb_bits |=
11583 to_intel_plane(plane)->frontbuffer_bit;
11584
da20eabd
ML		 11585 switch (plane->type) {
11586 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11587 intel_crtc->atomic.wait_for_flips = true;
11588 intel_crtc->atomic.pre_disable_primary = turn_off;
11589 intel_crtc->atomic.post_enable_primary = turn_on;
11590
066cf55b
RV		 11591 if (turn_off) {
11592 /*
11593 * FIXME: Actually if we will still have any other
11594 * plane enabled on the pipe we could let IPS enabled
11595 * still, but for now lets consider that when we make
11596 * primary invisible by setting DSPCNTR to 0 on
11597 * update_primary_plane function IPS needs to be
11598 * disable.
11599 */
11600 intel_crtc->atomic.disable_ips = true;
11601
da20eabd 11602 intel_crtc->atomic.disable_fbc = true;
066cf55b 11603 }
da20eabd
ML		 11604
11605 /*
11606 * FBC does not work on some platforms for rotated
11607 * planes, so disable it when rotation is not 0 and
11608 * update it when rotation is set back to 0.
11609 *
11610 * FIXME: This is redundant with the fbc update done in
11611 * the primary plane enable function except that that
11612 * one is done too late. We eventually need to unify
11613 * this.
11614 */
11615
11616 if (visible &&
11617 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11618 dev_priv->fbc.crtc == intel_crtc &&
11619 plane_state->rotation != BIT(DRM_ROTATE_0))
11620 intel_crtc->atomic.disable_fbc = true;
11621
11622 /*
11623 * BDW signals flip done immediately if the plane
11624 * is disabled, even if the plane enable is already
11625 * armed to occur at the next vblank :(
11626 */
11627 if (turn_on && IS_BROADWELL(dev))
11628 intel_crtc->atomic.wait_vblank = true;
11629
11630 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11631 break;
11632 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11633 break;
11634 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11635 if (turn_off && !mode_changed) {
da20eabd
ML		 11636 intel_crtc->atomic.wait_vblank = true;
11637 intel_crtc->atomic.update_sprite_watermarks |=
11638 1 << i;
11639 }
da20eabd
ML		 11640 }
11641 return 0;
11642}
11643
6d3a1ce7
ML		 11644static bool encoders_cloneable(const struct intel_encoder *a,
11645 const struct intel_encoder *b)
11646{
11647 /* masks could be asymmetric, so check both ways */
11648 return a == b || (a->cloneable & (1 << b->type) &&
11649 b->cloneable & (1 << a->type));
11650}
11651
11652static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11653 struct intel_crtc *crtc,
11654 struct intel_encoder *encoder)
11655{
11656 struct intel_encoder *source_encoder;
11657 struct drm_connector *connector;
11658 struct drm_connector_state *connector_state;
11659 int i;
11660
11661 for_each_connector_in_state(state, connector, connector_state, i) {
11662 if (connector_state->crtc != &crtc->base)
11663 continue;
11664
11665 source_encoder =
11666 to_intel_encoder(connector_state->best_encoder);
11667 if (!encoders_cloneable(encoder, source_encoder))
11668 return false;
11669 }
11670
11671 return true;
11672}
11673
11674static bool check_encoder_cloning(struct drm_atomic_state *state,
11675 struct intel_crtc *crtc)
11676{
11677 struct intel_encoder *encoder;
11678 struct drm_connector *connector;
11679 struct drm_connector_state *connector_state;
11680 int i;
11681
11682 for_each_connector_in_state(state, connector, connector_state, i) {
11683 if (connector_state->crtc != &crtc->base)
11684 continue;
11685
11686 encoder = to_intel_encoder(connector_state->best_encoder);
11687 if (!check_single_encoder_cloning(state, crtc, encoder))
11688 return false;
11689 }
11690
11691 return true;
11692}
11693
11694static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11695 struct drm_crtc_state *crtc_state)
11696{
cf5a15be 11697 struct drm_device *dev = crtc->dev;
ad421372 11698 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11700 struct intel_crtc_state *pipe_config =
11701 to_intel_crtc_state(crtc_state);
6d3a1ce7 11702 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11703 int ret;
6d3a1ce7
ML		 11704 bool mode_changed = needs_modeset(crtc_state);
11705
11706 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11707 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11708 return -EINVAL;
11709 }
11710
852eb00d
VS		 11711 if (mode_changed && !crtc_state->active)
11712 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11713
ad421372
ML		 11714 if (mode_changed && crtc_state->enable &&
11715 dev_priv->display.crtc_compute_clock &&
11716 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11717 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11718 pipe_config);
11719 if (ret)
11720 return ret;
11721 }
11722
e435d6e5
ML		 11723 ret = 0;
11724 if (INTEL_INFO(dev)->gen >= 9) {
11725 if (mode_changed)
11726 ret = skl_update_scaler_crtc(pipe_config);
11727
11728 if (!ret)
11729 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11730 pipe_config);
11731 }
11732
11733 return ret;
6d3a1ce7
ML		 11734}
11735
65b38e0d 11736static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11737 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11738 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11739 .atomic_begin = intel_begin_crtc_commit,
11740 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11741 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11742};
11743
d29b2f9d
ACO		 11744static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11745{
11746 struct intel_connector *connector;
11747
11748 for_each_intel_connector(dev, connector) {
11749 if (connector->base.encoder) {
11750 connector->base.state->best_encoder =
11751 connector->base.encoder;
11752 connector->base.state->crtc =
11753 connector->base.encoder->crtc;
11754 } else {
11755 connector->base.state->best_encoder = NULL;
11756 connector->base.state->crtc = NULL;
11757 }
11758 }
11759}
11760
050f7aeb 11761static void
eba905b2 11762connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11763 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11764{
11765 int bpp = pipe_config->pipe_bpp;
11766
11767 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11768 connector->base.base.id,
c23cc417 11769 connector->base.name);
050f7aeb
DV		 11770
11771 /* Don't use an invalid EDID bpc value */
11772 if (connector->base.display_info.bpc &&
11773 connector->base.display_info.bpc * 3 < bpp) {
11774 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11775 bpp, connector->base.display_info.bpc*3);
11776 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11777 }
11778
11779 /* Clamp bpp to 8 on screens without EDID 1.4 */
11780 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11781 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11782 bpp);
11783 pipe_config->pipe_bpp = 24;
11784 }
11785}
11786
4e53c2e0 11787static int
050f7aeb 11788compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11789 struct intel_crtc_state *pipe_config)
4e53c2e0 11790{
050f7aeb 11791 struct drm_device *dev = crtc->base.dev;
1486017f 11792 struct drm_atomic_state *state;
da3ced29
ACO		 11793 struct drm_connector *connector;
11794 struct drm_connector_state *connector_state;
1486017f 11795 int bpp, i;
4e53c2e0 11796
d328c9d7 11797 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11798 bpp = 10*3;
d328c9d7
DV		 11799 else if (INTEL_INFO(dev)->gen >= 5)
11800 bpp = 12*3;
11801 else
11802 bpp = 8*3;
11803
4e53c2e0 11804
4e53c2e0
DV		 11805 pipe_config->pipe_bpp = bpp;
11806
1486017f
ACO		 11807 state = pipe_config->base.state;
11808
4e53c2e0 11809 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11810 for_each_connector_in_state(state, connector, connector_state, i) {
11811 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11812 continue;
11813
da3ced29
ACO		 11814 connected_sink_compute_bpp(to_intel_connector(connector),
11815 pipe_config);
4e53c2e0
DV		 11816 }
11817
11818 return bpp;
11819}
11820
644db711
DV		 11821static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11822{
11823 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11824 "type: 0x%x flags: 0x%x\n",
1342830c 11825 mode->crtc_clock,
644db711
DV		 11826 mode->crtc_hdisplay, mode->crtc_hsync_start,
11827 mode->crtc_hsync_end, mode->crtc_htotal,
11828 mode->crtc_vdisplay, mode->crtc_vsync_start,
11829 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11830}
11831
c0b03411 11832static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11833 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11834 const char *context)
11835{
6a60cd87
CK		 11836 struct drm_device *dev = crtc->base.dev;
11837 struct drm_plane *plane;
11838 struct intel_plane *intel_plane;
11839 struct intel_plane_state *state;
11840 struct drm_framebuffer *fb;
11841
11842 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11843 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11844
11845 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11846 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11847 pipe_config->pipe_bpp, pipe_config->dither);
11848 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11849 pipe_config->has_pch_encoder,
11850 pipe_config->fdi_lanes,
11851 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11852 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11853 pipe_config->fdi_m_n.tu);
90a6b7b0 11854 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11855 pipe_config->has_dp_encoder,
90a6b7b0 11856 pipe_config->lane_count,
eb14cb74
VS		 11857 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11858 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11859 pipe_config->dp_m_n.tu);
b95af8be 11860
90a6b7b0 11861 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11862 pipe_config->has_dp_encoder,
90a6b7b0 11863 pipe_config->lane_count,
b95af8be
VK		 11864 pipe_config->dp_m2_n2.gmch_m,
11865 pipe_config->dp_m2_n2.gmch_n,
11866 pipe_config->dp_m2_n2.link_m,
11867 pipe_config->dp_m2_n2.link_n,
11868 pipe_config->dp_m2_n2.tu);
11869
55072d19
DV		 11870 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11871 pipe_config->has_audio,
11872 pipe_config->has_infoframe);
11873
c0b03411 11874 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11875 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11876 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11877 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11878 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11879 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11880 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11881 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11882 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11883 crtc->num_scalers,
11884 pipe_config->scaler_state.scaler_users,
11885 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11886 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11887 pipe_config->gmch_pfit.control,
11888 pipe_config->gmch_pfit.pgm_ratios,
11889 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11890 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11891 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11892 pipe_config->pch_pfit.size,
11893 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11894 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11895 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11896
415ff0f6 11897 if (IS_BROXTON(dev)) {
05712c15 11898 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11899 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11900 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11901 pipe_config->ddi_pll_sel,
11902 pipe_config->dpll_hw_state.ebb0,
05712c15 11903 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11904 pipe_config->dpll_hw_state.pll0,
11905 pipe_config->dpll_hw_state.pll1,
11906 pipe_config->dpll_hw_state.pll2,
11907 pipe_config->dpll_hw_state.pll3,
11908 pipe_config->dpll_hw_state.pll6,
11909 pipe_config->dpll_hw_state.pll8,
05712c15 11910 pipe_config->dpll_hw_state.pll9,
c8453338 11911 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 11912 pipe_config->dpll_hw_state.pcsdw12);
11913 } else if (IS_SKYLAKE(dev)) {
11914 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11915 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11916 pipe_config->ddi_pll_sel,
11917 pipe_config->dpll_hw_state.ctrl1,
11918 pipe_config->dpll_hw_state.cfgcr1,
11919 pipe_config->dpll_hw_state.cfgcr2);
11920 } else if (HAS_DDI(dev)) {
11921 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11922 pipe_config->ddi_pll_sel,
11923 pipe_config->dpll_hw_state.wrpll);
11924 } else {
11925 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11926 "fp0: 0x%x, fp1: 0x%x\n",
11927 pipe_config->dpll_hw_state.dpll,
11928 pipe_config->dpll_hw_state.dpll_md,
11929 pipe_config->dpll_hw_state.fp0,
11930 pipe_config->dpll_hw_state.fp1);
11931 }
11932
6a60cd87
CK		 11933 DRM_DEBUG_KMS("planes on this crtc\n");
11934 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11935 intel_plane = to_intel_plane(plane);
11936 if (intel_plane->pipe != crtc->pipe)
11937 continue;
11938
11939 state = to_intel_plane_state(plane->state);
11940 fb = state->base.fb;
11941 if (!fb) {
11942 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11943 "disabled, scaler_id = %d\n",
11944 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11945 plane->base.id, intel_plane->pipe,
11946 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11947 drm_plane_index(plane), state->scaler_id);
11948 continue;
11949 }
11950
11951 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11952 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11953 plane->base.id, intel_plane->pipe,
11954 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11955 drm_plane_index(plane));
11956 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11957 fb->base.id, fb->width, fb->height, fb->pixel_format);
11958 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11959 state->scaler_id,
11960 state->src.x1 >> 16, state->src.y1 >> 16,
11961 drm_rect_width(&state->src) >> 16,
11962 drm_rect_height(&state->src) >> 16,
11963 state->dst.x1, state->dst.y1,
11964 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11965 }
c0b03411
DV		 11966}
11967
5448a00d 11968static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11969{
5448a00d
ACO		 11970 struct drm_device *dev = state->dev;
11971 struct intel_encoder *encoder;
da3ced29 11972 struct drm_connector *connector;
5448a00d 11973 struct drm_connector_state *connector_state;
00f0b378 11974 unsigned int used_ports = 0;
5448a00d 11975 int i;
00f0b378
VS		 11976
11977 /*
11978 * Walk the connector list instead of the encoder
11979 * list to detect the problem on ddi platforms
11980 * where there's just one encoder per digital port.
11981 */
da3ced29 11982 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11983 if (!connector_state->best_encoder)
00f0b378
VS		 11984 continue;
11985
5448a00d
ACO		 11986 encoder = to_intel_encoder(connector_state->best_encoder);
11987
11988 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11989
11990 switch (encoder->type) {
11991 unsigned int port_mask;
11992 case INTEL_OUTPUT_UNKNOWN:
11993 if (WARN_ON(!HAS_DDI(dev)))
11994 break;
11995 case INTEL_OUTPUT_DISPLAYPORT:
11996 case INTEL_OUTPUT_HDMI:
11997 case INTEL_OUTPUT_EDP:
11998 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11999
12000 /* the same port mustn't appear more than once */
12001 if (used_ports & port_mask)
12002 return false;
12003
12004 used_ports |= port_mask;
12005 default:
12006 break;
12007 }
12008 }
12009
12010 return true;
12011}
12012
83a57153
ACO		 12013static void
12014clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12015{
12016 struct drm_crtc_state tmp_state;
663a3640 12017 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12018 struct intel_dpll_hw_state dpll_hw_state;
12019 enum intel_dpll_id shared_dpll;
8504c74c 12020 uint32_t ddi_pll_sel;
c4e2d043 12021 bool force_thru;
83a57153 12022
7546a384
ACO		 12023 /* FIXME: before the switch to atomic started, a new pipe_config was
12024 * kzalloc'd. Code that depends on any field being zero should be
12025 * fixed, so that the crtc_state can be safely duplicated. For now,
12026 * only fields that are know to not cause problems are preserved. */
12027
83a57153 12028 tmp_state = crtc_state->base;
663a3640 12029 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12030 shared_dpll = crtc_state->shared_dpll;
12031 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12032 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12033 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12034
83a57153 12035 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12036
83a57153 12037 crtc_state->base = tmp_state;
663a3640 12038 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12039 crtc_state->shared_dpll = shared_dpll;
12040 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12041 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12042 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12043}
12044
548ee15b 12045static int
b8cecdf5 12046intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12047 struct intel_crtc_state *pipe_config)
ee7b9f93 12048{
b359283a 12049 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12050 struct intel_encoder *encoder;
da3ced29 12051 struct drm_connector *connector;
0b901879 12052 struct drm_connector_state *connector_state;
d328c9d7 12053 int base_bpp, ret = -EINVAL;
0b901879 12054 int i;
e29c22c0 12055 bool retry = true;
ee7b9f93 12056
83a57153 12057 clear_intel_crtc_state(pipe_config);
7758a113 12058
e143a21c
DV		 12059 pipe_config->cpu_transcoder =
12060 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12061
2960bc9c
ID		 12062 /*
12063 * Sanitize sync polarity flags based on requested ones. If neither
12064 * positive or negative polarity is requested, treat this as meaning
12065 * negative polarity.
12066 */
2d112de7 12067 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12068 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12069 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12070
2d112de7 12071 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12072 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12073 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12074
050f7aeb
DV		 12075 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12076 * plane pixel format and any sink constraints into account. Returns the
12077 * source plane bpp so that dithering can be selected on mismatches
12078 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12079 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12080 pipe_config);
12081 if (base_bpp < 0)
4e53c2e0
DV		 12082 goto fail;
12083
e41a56be
VS		 12084 /*
12085 * Determine the real pipe dimensions. Note that stereo modes can
12086 * increase the actual pipe size due to the frame doubling and
12087 * insertion of additional space for blanks between the frame. This
12088 * is stored in the crtc timings. We use the requested mode to do this
12089 * computation to clearly distinguish it from the adjusted mode, which
12090 * can be changed by the connectors in the below retry loop.
12091 */
2d112de7 12092 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12093 &pipe_config->pipe_src_w,
12094 &pipe_config->pipe_src_h);
e41a56be 12095
e29c22c0 12096encoder_retry:
ef1b460d 12097 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12098 pipe_config->port_clock = 0;
ef1b460d 12099 pipe_config->pixel_multiplier = 1;
ff9a6750 12100
135c81b8 12101 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12102 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12103 CRTC_STEREO_DOUBLE);
135c81b8 12104
7758a113
DV		 12105 /* Pass our mode to the connectors and the CRTC to give them a chance to
12106 * adjust it according to limitations or connector properties, and also
12107 * a chance to reject the mode entirely.
47f1c6c9 12108 */
da3ced29 12109 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12110 if (connector_state->crtc != crtc)
7758a113 12111 continue;
7ae89233 12112
0b901879
ACO		 12113 encoder = to_intel_encoder(connector_state->best_encoder);
12114
efea6e8e
DV		 12115 if (!(encoder->compute_config(encoder, pipe_config))) {
12116 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12117 goto fail;
12118 }
ee7b9f93 12119 }
47f1c6c9 12120
ff9a6750
DV		 12121 /* Set default port clock if not overwritten by the encoder. Needs to be
12122 * done afterwards in case the encoder adjusts the mode. */
12123 if (!pipe_config->port_clock)
2d112de7 12124 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12125 * pipe_config->pixel_multiplier;
ff9a6750 12126
a43f6e0f 12127 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12128 if (ret < 0) {
7758a113
DV		 12129 DRM_DEBUG_KMS("CRTC fixup failed\n");
12130 goto fail;
ee7b9f93 12131 }
e29c22c0
DV		 12132
12133 if (ret == RETRY) {
12134 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12135 ret = -EINVAL;
12136 goto fail;
12137 }
12138
12139 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12140 retry = false;
12141 goto encoder_retry;
12142 }
12143
e8fa4270
DV		 12144 /* Dithering seems to not pass-through bits correctly when it should, so
12145 * only enable it on 6bpc panels. */
12146 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
4e53c2e0 12147 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12148 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12149
7758a113 12150fail:
548ee15b 12151 return ret;
ee7b9f93 12152}
47f1c6c9 12153
ea9d758d 12154static void
4740b0f2 12155intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12156{
0a9ab303
ACO		 12157 struct drm_crtc *crtc;
12158 struct drm_crtc_state *crtc_state;
8a75d157 12159 int i;
ea9d758d 12160
7668851f 12161 /* Double check state. */
8a75d157 12162 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12163 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12164
12165 /* Update hwmode for vblank functions */
12166 if (crtc->state->active)
12167 crtc->hwmode = crtc->state->adjusted_mode;
12168 else
12169 crtc->hwmode.crtc_clock = 0;
ea9d758d 12170 }
ea9d758d
DV		 12171}
12172
3bd26263 12173static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12174{
3bd26263 12175 int diff;
f1f644dc
JB		 12176
12177 if (clock1 == clock2)
12178 return true;
12179
12180 if (!clock1 || !clock2)
12181 return false;
12182
12183 diff = abs(clock1 - clock2);
12184
12185 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12186 return true;
12187
12188 return false;
12189}
12190
25c5b266
DV		 12191#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12192 list_for_each_entry((intel_crtc), \
12193 &(dev)->mode_config.crtc_list, \
12194 base.head) \
0973f18f 12195 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12196
cfb23ed6
ML		 12197
12198static bool
12199intel_compare_m_n(unsigned int m, unsigned int n,
12200 unsigned int m2, unsigned int n2,
12201 bool exact)
12202{
12203 if (m == m2 && n == n2)
12204 return true;
12205
12206 if (exact || !m || !n || !m2 || !n2)
12207 return false;
12208
12209 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12210
12211 if (m > m2) {
12212 while (m > m2) {
12213 m2 <<= 1;
12214 n2 <<= 1;
12215 }
12216 } else if (m < m2) {
12217 while (m < m2) {
12218 m <<= 1;
12219 n <<= 1;
12220 }
12221 }
12222
12223 return m == m2 && n == n2;
12224}
12225
12226static bool
12227intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12228 struct intel_link_m_n *m2_n2,
12229 bool adjust)
12230{
12231 if (m_n->tu == m2_n2->tu &&
12232 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12233 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12234 intel_compare_m_n(m_n->link_m, m_n->link_n,
12235 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12236 if (adjust)
12237 *m2_n2 = *m_n;
12238
12239 return true;
12240 }
12241
12242 return false;
12243}
12244
0e8ffe1b 12245static bool
2fa2fe9a 12246intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12247 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12248 struct intel_crtc_state *pipe_config,
12249 bool adjust)
0e8ffe1b 12250{
cfb23ed6
ML		 12251 bool ret = true;
12252
12253#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12254 do { \
12255 if (!adjust) \
12256 DRM_ERROR(fmt, ##__VA_ARGS__); \
12257 else \
12258 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12259 } while (0)
12260
66e985c0
DV		 12261#define PIPE_CONF_CHECK_X(name) \
12262 if (current_config->name != pipe_config->name) { \
cfb23ed6 12263 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12264 "(expected 0x%08x, found 0x%08x)\n", \
12265 current_config->name, \
12266 pipe_config->name); \
cfb23ed6 12267 ret = false; \
66e985c0
DV		 12268 }
12269
08a24034
DV		 12270#define PIPE_CONF_CHECK_I(name) \
12271 if (current_config->name != pipe_config->name) { \
cfb23ed6 12272 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12273 "(expected %i, found %i)\n", \
12274 current_config->name, \
12275 pipe_config->name); \
cfb23ed6
ML		 12276 ret = false; \
12277 }
12278
12279#define PIPE_CONF_CHECK_M_N(name) \
12280 if (!intel_compare_link_m_n(&current_config->name, \
12281 &pipe_config->name,\
12282 adjust)) { \
12283 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12284 "(expected tu %i gmch %i/%i link %i/%i, " \
12285 "found tu %i, gmch %i/%i link %i/%i)\n", \
12286 current_config->name.tu, \
12287 current_config->name.gmch_m, \
12288 current_config->name.gmch_n, \
12289 current_config->name.link_m, \
12290 current_config->name.link_n, \
12291 pipe_config->name.tu, \
12292 pipe_config->name.gmch_m, \
12293 pipe_config->name.gmch_n, \
12294 pipe_config->name.link_m, \
12295 pipe_config->name.link_n); \
12296 ret = false; \
12297 }
12298
12299#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12300 if (!intel_compare_link_m_n(&current_config->name, \
12301 &pipe_config->name, adjust) && \
12302 !intel_compare_link_m_n(&current_config->alt_name, \
12303 &pipe_config->name, adjust)) { \
12304 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12305 "(expected tu %i gmch %i/%i link %i/%i, " \
12306 "or tu %i gmch %i/%i link %i/%i, " \
12307 "found tu %i, gmch %i/%i link %i/%i)\n", \
12308 current_config->name.tu, \
12309 current_config->name.gmch_m, \
12310 current_config->name.gmch_n, \
12311 current_config->name.link_m, \
12312 current_config->name.link_n, \
12313 current_config->alt_name.tu, \
12314 current_config->alt_name.gmch_m, \
12315 current_config->alt_name.gmch_n, \
12316 current_config->alt_name.link_m, \
12317 current_config->alt_name.link_n, \
12318 pipe_config->name.tu, \
12319 pipe_config->name.gmch_m, \
12320 pipe_config->name.gmch_n, \
12321 pipe_config->name.link_m, \
12322 pipe_config->name.link_n); \
12323 ret = false; \
88adfff1
DV		 12324 }
12325
b95af8be
VK		 12326/* This is required for BDW+ where there is only one set of registers for
12327 * switching between high and low RR.
12328 * This macro can be used whenever a comparison has to be made between one
12329 * hw state and multiple sw state variables.
12330 */
12331#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12332 if ((current_config->name != pipe_config->name) && \
12333 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12334 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12335 "(expected %i or %i, found %i)\n", \
12336 current_config->name, \
12337 current_config->alt_name, \
12338 pipe_config->name); \
cfb23ed6 12339 ret = false; \
b95af8be
VK		 12340 }
12341
1bd1bd80
DV		 12342#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12343 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12344 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12345 "(expected %i, found %i)\n", \
12346 current_config->name & (mask), \
12347 pipe_config->name & (mask)); \
cfb23ed6 12348 ret = false; \
1bd1bd80
DV		 12349 }
12350
5e550656
VS		 12351#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12352 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12353 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12354 "(expected %i, found %i)\n", \
12355 current_config->name, \
12356 pipe_config->name); \
cfb23ed6 12357 ret = false; \
5e550656
VS		 12358 }
12359
bb760063
DV		 12360#define PIPE_CONF_QUIRK(quirk) \
12361 ((current_config->quirks | pipe_config->quirks) & (quirk))
12362
eccb140b
DV		 12363 PIPE_CONF_CHECK_I(cpu_transcoder);
12364
08a24034
DV		 12365 PIPE_CONF_CHECK_I(has_pch_encoder);
12366 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12367 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12368
eb14cb74 12369 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12370 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12371
12372 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12373 PIPE_CONF_CHECK_M_N(dp_m_n);
12374
12375 PIPE_CONF_CHECK_I(has_drrs);
12376 if (current_config->has_drrs)
12377 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12378 } else
12379 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12380
2d112de7
ACO		 12381 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12382 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12383 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12384 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12385 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12386 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12387
2d112de7
ACO		 12388 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12389 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12390 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12391 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12392 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12393 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12394
c93f54cf 12395 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12396 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12397 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12398 IS_VALLEYVIEW(dev))
12399 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12400 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12401
9ed109a7
DV		 12402 PIPE_CONF_CHECK_I(has_audio);
12403
2d112de7 12404 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12405 DRM_MODE_FLAG_INTERLACE);
12406
bb760063 12407 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12408 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12409 DRM_MODE_FLAG_PHSYNC);
2d112de7 12410 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12411 DRM_MODE_FLAG_NHSYNC);
2d112de7 12412 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12413 DRM_MODE_FLAG_PVSYNC);
2d112de7 12414 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12415 DRM_MODE_FLAG_NVSYNC);
12416 }
045ac3b5 12417
37327abd
VS		 12418 PIPE_CONF_CHECK_I(pipe_src_w);
12419 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12420
e2ff2d4a
DV		 12421 PIPE_CONF_CHECK_I(gmch_pfit.control);
12422 /* pfit ratios are autocomputed by the hw on gen4+ */
12423 if (INTEL_INFO(dev)->gen < 4)
12424 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12425 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9953599b 12426
fd4daa9c
CW		 12427 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12428 if (current_config->pch_pfit.enabled) {
12429 PIPE_CONF_CHECK_I(pch_pfit.pos);
12430 PIPE_CONF_CHECK_I(pch_pfit.size);
12431 }
2fa2fe9a 12432
a1b2278e
CK		 12433 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12434
e59150dc
JB		 12435 /* BDW+ don't expose a synchronous way to read the state */
12436 if (IS_HASWELL(dev))
12437 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12438
282740f7
VS		 12439 PIPE_CONF_CHECK_I(double_wide);
12440
26804afd
DV		 12441 PIPE_CONF_CHECK_X(ddi_pll_sel);
12442
c0d43d62 12443 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12444 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12445 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12446 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12447 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12448 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12449 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12450 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12451 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12452
42571aef
VS		 12453 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12454 PIPE_CONF_CHECK_I(pipe_bpp);
12455
2d112de7 12456 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12457 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12458
66e985c0 12459#undef PIPE_CONF_CHECK_X
08a24034 12460#undef PIPE_CONF_CHECK_I
b95af8be 12461#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12462#undef PIPE_CONF_CHECK_FLAGS
5e550656 12463#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12464#undef PIPE_CONF_QUIRK
cfb23ed6 12465#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12466
cfb23ed6 12467 return ret;
0e8ffe1b
DV		 12468}
12469
08db6652
DL		 12470static void check_wm_state(struct drm_device *dev)
12471{
12472 struct drm_i915_private *dev_priv = dev->dev_private;
12473 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12474 struct intel_crtc *intel_crtc;
12475 int plane;
12476
12477 if (INTEL_INFO(dev)->gen < 9)
12478 return;
12479
12480 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12481 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12482
12483 for_each_intel_crtc(dev, intel_crtc) {
12484 struct skl_ddb_entry *hw_entry, *sw_entry;
12485 const enum pipe pipe = intel_crtc->pipe;
12486
12487 if (!intel_crtc->active)
12488 continue;
12489
12490 /* planes */
dd740780 12491 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12492 hw_entry = &hw_ddb.plane[pipe][plane];
12493 sw_entry = &sw_ddb->plane[pipe][plane];
12494
12495 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12496 continue;
12497
12498 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12499 "(expected (%u,%u), found (%u,%u))\n",
12500 pipe_name(pipe), plane + 1,
12501 sw_entry->start, sw_entry->end,
12502 hw_entry->start, hw_entry->end);
12503 }
12504
12505 /* cursor */
12506 hw_entry = &hw_ddb.cursor[pipe];
12507 sw_entry = &sw_ddb->cursor[pipe];
12508
12509 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12510 continue;
12511
12512 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12513 "(expected (%u,%u), found (%u,%u))\n",
12514 pipe_name(pipe),
12515 sw_entry->start, sw_entry->end,
12516 hw_entry->start, hw_entry->end);
12517 }
12518}
12519
91d1b4bd 12520static void
35dd3c64
ML		 12521check_connector_state(struct drm_device *dev,
12522 struct drm_atomic_state *old_state)
8af6cf88 12523{
35dd3c64
ML		 12524 struct drm_connector_state *old_conn_state;
12525 struct drm_connector *connector;
12526 int i;
8af6cf88 12527
35dd3c64
ML		 12528 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12529 struct drm_encoder *encoder = connector->encoder;
12530 struct drm_connector_state *state = connector->state;
ad3c558f 12531
8af6cf88
DV		 12532 /* This also checks the encoder/connector hw state with the
12533 * ->get_hw_state callbacks. */
35dd3c64 12534 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12535
ad3c558f 12536 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12537 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12538 }
91d1b4bd
DV		 12539}
12540
12541static void
12542check_encoder_state(struct drm_device *dev)
12543{
12544 struct intel_encoder *encoder;
12545 struct intel_connector *connector;
8af6cf88 12546
b2784e15 12547 for_each_intel_encoder(dev, encoder) {
8af6cf88 12548 bool enabled = false;
4d20cd86 12549 enum pipe pipe;
8af6cf88
DV		 12550
12551 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12552 encoder->base.base.id,
8e329a03 12553 encoder->base.name);
8af6cf88 12554
3a3371ff 12555 for_each_intel_connector(dev, connector) {
4d20cd86 12556 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12557 continue;
12558 enabled = true;
ad3c558f
ML		 12559
12560 I915_STATE_WARN(connector->base.state->crtc !=
12561 encoder->base.crtc,
12562 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12563 }
0e32b39c 12564
e2c719b7 12565 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12566 "encoder's enabled state mismatch "
12567 "(expected %i, found %i)\n",
12568 !!encoder->base.crtc, enabled);
7c60d198
ML		 12569
12570 if (!encoder->base.crtc) {
4d20cd86 12571 bool active;
7c60d198 12572
4d20cd86
ML		 12573 active = encoder->get_hw_state(encoder, &pipe);
12574 I915_STATE_WARN(active,
12575 "encoder detached but still enabled on pipe %c.\n",
12576 pipe_name(pipe));
7c60d198 12577 }
8af6cf88 12578 }
91d1b4bd
DV		 12579}
12580
12581static void
4d20cd86 12582check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12583{
fbee40df 12584 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12585 struct intel_encoder *encoder;
4d20cd86
ML		 12586 struct drm_crtc_state *old_crtc_state;
12587 struct drm_crtc *crtc;
12588 int i;
8af6cf88 12589
4d20cd86
ML		 12590 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12592 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12593 bool active;
8af6cf88 12594
4d20cd86
ML		 12595 if (!needs_modeset(crtc->state))
12596 continue;
045ac3b5 12597
4d20cd86
ML		 12598 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12599 pipe_config = to_intel_crtc_state(old_crtc_state);
12600 memset(pipe_config, 0, sizeof(*pipe_config));
12601 pipe_config->base.crtc = crtc;
12602 pipe_config->base.state = old_state;
8af6cf88 12603
4d20cd86
ML		 12604 DRM_DEBUG_KMS("[CRTC:%d]\n",
12605 crtc->base.id);
8af6cf88 12606
4d20cd86
ML		 12607 active = dev_priv->display.get_pipe_config(intel_crtc,
12608 pipe_config);
d62cf62a 12609
b6b5d049 12610 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12611 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12612 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12613 active = crtc->state->active;
6c49f241 12614
4d20cd86 12615 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12616 "crtc active state doesn't match with hw state "
4d20cd86 12617 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12618
4d20cd86 12619 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12620 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12621 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12622
12623 for_each_encoder_on_crtc(dev, crtc, encoder) {
12624 enum pipe pipe;
12625
12626 active = encoder->get_hw_state(encoder, &pipe);
12627 I915_STATE_WARN(active != crtc->state->active,
12628 "[ENCODER:%i] active %i with crtc active %i\n",
12629 encoder->base.base.id, active, crtc->state->active);
12630
12631 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12632 "Encoder connected to wrong pipe %c\n",
12633 pipe_name(pipe));
12634
12635 if (active)
12636 encoder->get_config(encoder, pipe_config);
12637 }
53d9f4e9 12638
4d20cd86 12639 if (!crtc->state->active)
cfb23ed6
ML		 12640 continue;
12641
4d20cd86
ML		 12642 sw_config = to_intel_crtc_state(crtc->state);
12643 if (!intel_pipe_config_compare(dev, sw_config,
12644 pipe_config, false)) {
e2c719b7 12645 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12646 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12647 "[hw state]");
4d20cd86 12648 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12649 "[sw state]");
12650 }
8af6cf88
DV		 12651 }
12652}
12653
91d1b4bd
DV		 12654static void
12655check_shared_dpll_state(struct drm_device *dev)
12656{
fbee40df 12657 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12658 struct intel_crtc *crtc;
12659 struct intel_dpll_hw_state dpll_hw_state;
12660 int i;
5358901f
DV		 12661
12662 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12663 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12664 int enabled_crtcs = 0, active_crtcs = 0;
12665 bool active;
12666
12667 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12668
12669 DRM_DEBUG_KMS("%s\n", pll->name);
12670
12671 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12672
e2c719b7 12673 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12674 "more active pll users than references: %i vs %i\n",
3e369b76 12675 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12676 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12677 "pll in active use but not on in sw tracking\n");
e2c719b7 12678 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12679 "pll in on but not on in use in sw tracking\n");
e2c719b7 12680 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12681 "pll on state mismatch (expected %i, found %i)\n",
12682 pll->on, active);
12683
d3fcc808 12684 for_each_intel_crtc(dev, crtc) {
83d65738 12685 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12686 enabled_crtcs++;
12687 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12688 active_crtcs++;
12689 }
e2c719b7 12690 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12691 "pll active crtcs mismatch (expected %i, found %i)\n",
12692 pll->active, active_crtcs);
e2c719b7 12693 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12694 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12695 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12696
e2c719b7 12697 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12698 sizeof(dpll_hw_state)),
12699 "pll hw state mismatch\n");
5358901f 12700 }
8af6cf88
DV		 12701}
12702
ee165b1a
ML		 12703static void
12704intel_modeset_check_state(struct drm_device *dev,
12705 struct drm_atomic_state *old_state)
91d1b4bd 12706{
08db6652 12707 check_wm_state(dev);
35dd3c64 12708 check_connector_state(dev, old_state);
91d1b4bd 12709 check_encoder_state(dev);
4d20cd86 12710 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12711 check_shared_dpll_state(dev);
12712}
12713
5cec258b 12714void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12715 int dotclock)
12716{
12717 /*
12718 * FDI already provided one idea for the dotclock.
12719 * Yell if the encoder disagrees.
12720 */
2d112de7 12721 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12722 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12723 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12724}
12725
80715b2f
VS		 12726static void update_scanline_offset(struct intel_crtc *crtc)
12727{
12728 struct drm_device *dev = crtc->base.dev;
12729
12730 /*
12731 * The scanline counter increments at the leading edge of hsync.
12732 *
12733 * On most platforms it starts counting from vtotal-1 on the
12734 * first active line. That means the scanline counter value is
12735 * always one less than what we would expect. Ie. just after
12736 * start of vblank, which also occurs at start of hsync (on the
12737 * last active line), the scanline counter will read vblank_start-1.
12738 *
12739 * On gen2 the scanline counter starts counting from 1 instead
12740 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12741 * to keep the value positive), instead of adding one.
12742 *
12743 * On HSW+ the behaviour of the scanline counter depends on the output
12744 * type. For DP ports it behaves like most other platforms, but on HDMI
12745 * there's an extra 1 line difference. So we need to add two instead of
12746 * one to the value.
12747 */
12748 if (IS_GEN2(dev)) {
6e3c9717 12749 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12750 int vtotal;
12751
12752 vtotal = mode->crtc_vtotal;
12753 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12754 vtotal /= 2;
12755
12756 crtc->scanline_offset = vtotal - 1;
12757 } else if (HAS_DDI(dev) &&
409ee761 12758 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12759 crtc->scanline_offset = 2;
12760 } else
12761 crtc->scanline_offset = 1;
12762}
12763
ad421372 12764static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12765{
225da59b 12766 struct drm_device *dev = state->dev;
ed6739ef 12767 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12768 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12769 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12770 struct intel_crtc_state *intel_crtc_state;
12771 struct drm_crtc *crtc;
12772 struct drm_crtc_state *crtc_state;
0a9ab303 12773 int i;
ed6739ef
ACO		 12774
12775 if (!dev_priv->display.crtc_compute_clock)
ad421372 12776 return;
ed6739ef 12777
0a9ab303 12778 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12779 int dpll;
12780
0a9ab303 12781 intel_crtc = to_intel_crtc(crtc);
4978cc93 12782 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12783 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12784
ad421372 12785 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12786 continue;
12787
ad421372 12788 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12789
ad421372
ML		 12790 if (!shared_dpll)
12791 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12792
ad421372
ML		 12793 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12794 }
ed6739ef
ACO		 12795}
12796
99d736a2
ML		 12797/*
12798 * This implements the workaround described in the "notes" section of the mode
12799 * set sequence documentation. When going from no pipes or single pipe to
12800 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12801 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12802 */
12803static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12804{
12805 struct drm_crtc_state *crtc_state;
12806 struct intel_crtc *intel_crtc;
12807 struct drm_crtc *crtc;
12808 struct intel_crtc_state *first_crtc_state = NULL;
12809 struct intel_crtc_state *other_crtc_state = NULL;
12810 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12811 int i;
12812
12813 /* look at all crtc's that are going to be enabled in during modeset */
12814 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12815 intel_crtc = to_intel_crtc(crtc);
12816
12817 if (!crtc_state->active || !needs_modeset(crtc_state))
12818 continue;
12819
12820 if (first_crtc_state) {
12821 other_crtc_state = to_intel_crtc_state(crtc_state);
12822 break;
12823 } else {
12824 first_crtc_state = to_intel_crtc_state(crtc_state);
12825 first_pipe = intel_crtc->pipe;
12826 }
12827 }
12828
12829 /* No workaround needed? */
12830 if (!first_crtc_state)
12831 return 0;
12832
12833 /* w/a possibly needed, check how many crtc's are already enabled. */
12834 for_each_intel_crtc(state->dev, intel_crtc) {
12835 struct intel_crtc_state *pipe_config;
12836
12837 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12838 if (IS_ERR(pipe_config))
12839 return PTR_ERR(pipe_config);
12840
12841 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12842
12843 if (!pipe_config->base.active ||
12844 needs_modeset(&pipe_config->base))
12845 continue;
12846
12847 /* 2 or more enabled crtcs means no need for w/a */
12848 if (enabled_pipe != INVALID_PIPE)
12849 return 0;
12850
12851 enabled_pipe = intel_crtc->pipe;
12852 }
12853
12854 if (enabled_pipe != INVALID_PIPE)
12855 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12856 else if (other_crtc_state)
12857 other_crtc_state->hsw_workaround_pipe = first_pipe;
12858
12859 return 0;
12860}
12861
27c329ed
ML		 12862static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12863{
12864 struct drm_crtc *crtc;
12865 struct drm_crtc_state *crtc_state;
12866 int ret = 0;
12867
12868 /* add all active pipes to the state */
12869 for_each_crtc(state->dev, crtc) {
12870 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12871 if (IS_ERR(crtc_state))
12872 return PTR_ERR(crtc_state);
12873
12874 if (!crtc_state->active || needs_modeset(crtc_state))
12875 continue;
12876
12877 crtc_state->mode_changed = true;
12878
12879 ret = drm_atomic_add_affected_connectors(state, crtc);
12880 if (ret)
12881 break;
12882
12883 ret = drm_atomic_add_affected_planes(state, crtc);
12884 if (ret)
12885 break;
12886 }
12887
12888 return ret;
12889}
12890
12891
c347a676 12892static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12893{
12894 struct drm_device *dev = state->dev;
27c329ed 12895 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12896 int ret;
12897
b359283a
ML		 12898 if (!check_digital_port_conflicts(state)) {
12899 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12900 return -EINVAL;
12901 }
12902
054518dd
ACO		 12903 /*
12904 * See if the config requires any additional preparation, e.g.
12905 * to adjust global state with pipes off. We need to do this
12906 * here so we can get the modeset_pipe updated config for the new
12907 * mode set on this crtc. For other crtcs we need to use the
12908 * adjusted_mode bits in the crtc directly.
12909 */
27c329ed
ML		 12910 if (dev_priv->display.modeset_calc_cdclk) {
12911 unsigned int cdclk;
b432e5cf 12912
27c329ed
ML		 12913 ret = dev_priv->display.modeset_calc_cdclk(state);
12914
12915 cdclk = to_intel_atomic_state(state)->cdclk;
12916 if (!ret && cdclk != dev_priv->cdclk_freq)
12917 ret = intel_modeset_all_pipes(state);
12918
12919 if (ret < 0)
054518dd 12920 return ret;
27c329ed
ML		 12921 } else
12922 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 12923
ad421372 12924 intel_modeset_clear_plls(state);
054518dd 12925
99d736a2 12926 if (IS_HASWELL(dev))
ad421372 12927 return haswell_mode_set_planes_workaround(state);
99d736a2 12928
ad421372 12929 return 0;
c347a676
ACO		 12930}
12931
74c090b1
ML		 12932/**
12933 * intel_atomic_check - validate state object
12934 * @dev: drm device
12935 * @state: state to validate
12936 */
12937static int intel_atomic_check(struct drm_device *dev,
12938 struct drm_atomic_state *state)
c347a676
ACO		 12939{
12940 struct drm_crtc *crtc;
12941 struct drm_crtc_state *crtc_state;
12942 int ret, i;
61333b60 12943 bool any_ms = false;
c347a676 12944
74c090b1 12945 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 12946 if (ret)
12947 return ret;
12948
c347a676 12949 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 12950 struct intel_crtc_state *pipe_config =
12951 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 12952
12953 /* Catch I915_MODE_FLAG_INHERITED */
12954 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12955 crtc_state->mode_changed = true;
cfb23ed6 12956
61333b60
ML		 12957 if (!crtc_state->enable) {
12958 if (needs_modeset(crtc_state))
12959 any_ms = true;
c347a676 12960 continue;
61333b60 12961 }
c347a676 12962
26495481 12963 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 12964 continue;
12965
26495481
DV		 12966 /* FIXME: For only active_changed we shouldn't need to do any
12967 * state recomputation at all. */
12968
1ed51de9
DV		 12969 ret = drm_atomic_add_affected_connectors(state, crtc);
12970 if (ret)
12971 return ret;
b359283a 12972
cfb23ed6 12973 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 12974 if (ret)
12975 return ret;
12976
26495481
DV		 12977 if (i915.fastboot &&
12978 intel_pipe_config_compare(state->dev,
cfb23ed6 12979 to_intel_crtc_state(crtc->state),
1ed51de9 12980 pipe_config, true)) {
26495481
DV		 12981 crtc_state->mode_changed = false;
12982 }
12983
12984 if (needs_modeset(crtc_state)) {
12985 any_ms = true;
cfb23ed6
ML		 12986
12987 ret = drm_atomic_add_affected_planes(state, crtc);
12988 if (ret)
12989 return ret;
12990 }
61333b60 12991
26495481
DV		 12992 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12993 needs_modeset(crtc_state) ?
12994 "[modeset]" : "[fastset]");
c347a676
ACO		 12995 }
12996
61333b60
ML		 12997 if (any_ms) {
12998 ret = intel_modeset_checks(state);
12999
13000 if (ret)
13001 return ret;
27c329ed
ML		 13002 } else
13003 to_intel_atomic_state(state)->cdclk =
13004 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13005
13006 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13007}
13008
74c090b1
ML		 13009/**
13010 * intel_atomic_commit - commit validated state object
13011 * @dev: DRM device
13012 * @state: the top-level driver state object
13013 * @async: asynchronous commit
13014 *
13015 * This function commits a top-level state object that has been validated
13016 * with drm_atomic_helper_check().
13017 *
13018 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13019 * we can only handle plane-related operations and do not yet support
13020 * asynchronous commit.
13021 *
13022 * RETURNS
13023 * Zero for success or -errno.
13024 */
13025static int intel_atomic_commit(struct drm_device *dev,
13026 struct drm_atomic_state *state,
13027 bool async)
a6778b3c 13028{
fbee40df 13029 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13030 struct drm_crtc *crtc;
13031 struct drm_crtc_state *crtc_state;
c0c36b94 13032 int ret = 0;
0a9ab303 13033 int i;
61333b60 13034 bool any_ms = false;
a6778b3c 13035
74c090b1
ML		 13036 if (async) {
13037 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13038 return -EINVAL;
13039 }
13040
d4afb8cc
ACO		 13041 ret = drm_atomic_helper_prepare_planes(dev, state);
13042 if (ret)
13043 return ret;
13044
1c5e19f8
ML		 13045 drm_atomic_helper_swap_state(dev, state);
13046
0a9ab303 13047 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13049
61333b60
ML		 13050 if (!needs_modeset(crtc->state))
13051 continue;
13052
13053 any_ms = true;
a539205a 13054 intel_pre_plane_update(intel_crtc);
460da916 13055
a539205a
ML		 13056 if (crtc_state->active) {
13057 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13058 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13059 intel_crtc->active = false;
13060 intel_disable_shared_dpll(intel_crtc);
a539205a 13061 }
b8cecdf5 13062 }
7758a113 13063
ea9d758d
DV		 13064 /* Only after disabling all output pipelines that will be changed can we
13065 * update the the output configuration. */
4740b0f2 13066 intel_modeset_update_crtc_state(state);
f6e5b160 13067
4740b0f2
ML		 13068 if (any_ms) {
13069 intel_shared_dpll_commit(state);
13070
13071 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13072 modeset_update_crtc_power_domains(state);
4740b0f2 13073 }
47fab737 13074
a6778b3c 13075 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13076 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13078 bool modeset = needs_modeset(crtc->state);
13079
13080 if (modeset && crtc->state->active) {
a539205a
ML		 13081 update_scanline_offset(to_intel_crtc(crtc));
13082 dev_priv->display.crtc_enable(crtc);
13083 }
80715b2f 13084
f6ac4b2a
ML		 13085 if (!modeset)
13086 intel_pre_plane_update(intel_crtc);
13087
a539205a 13088 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
f6ac4b2a 13089 intel_post_plane_update(intel_crtc);
80715b2f 13090 }
a6778b3c 13091
a6778b3c 13092 /* FIXME: add subpixel order */
83a57153 13093
74c090b1 13094 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13095 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13096
74c090b1 13097 if (any_ms)
ee165b1a
ML		 13098 intel_modeset_check_state(dev, state);
13099
13100 drm_atomic_state_free(state);
f30da187 13101
74c090b1 13102 return 0;
7f27126e
JB		 13103}
13104
c0c36b94
CW		 13105void intel_crtc_restore_mode(struct drm_crtc *crtc)
13106{
83a57153
ACO		 13107 struct drm_device *dev = crtc->dev;
13108 struct drm_atomic_state *state;
e694eb02 13109 struct drm_crtc_state *crtc_state;
2bfb4627 13110 int ret;
83a57153
ACO		 13111
13112 state = drm_atomic_state_alloc(dev);
13113 if (!state) {
e694eb02 13114 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13115 crtc->base.id);
13116 return;
13117 }
13118
e694eb02 13119 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13120
e694eb02
ML		 13121retry:
13122 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13123 ret = PTR_ERR_OR_ZERO(crtc_state);
13124 if (!ret) {
13125 if (!crtc_state->active)
13126 goto out;
83a57153 13127
e694eb02 13128 crtc_state->mode_changed = true;
74c090b1 13129 ret = drm_atomic_commit(state);
83a57153
ACO		 13130 }
13131
e694eb02
ML		 13132 if (ret == -EDEADLK) {
13133 drm_atomic_state_clear(state);
13134 drm_modeset_backoff(state->acquire_ctx);
13135 goto retry;
4ed9fb37 13136 }
4be07317 13137
2bfb4627 13138 if (ret)
e694eb02 13139out:
2bfb4627 13140 drm_atomic_state_free(state);
c0c36b94
CW		 13141}
13142
25c5b266
DV		 13143#undef for_each_intel_crtc_masked
13144
f6e5b160 13145static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13146 .gamma_set = intel_crtc_gamma_set,
74c090b1 13147 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13148 .destroy = intel_crtc_destroy,
13149 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13150 .atomic_duplicate_state = intel_crtc_duplicate_state,
13151 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13152};
13153
5358901f
DV		 13154static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13155 struct intel_shared_dpll *pll,
13156 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13157{
5358901f 13158 uint32_t val;
ee7b9f93 13159
f458ebbc 13160 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13161 return false;
13162
5358901f 13163 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13164 hw_state->dpll = val;
13165 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13166 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13167
13168 return val & DPLL_VCO_ENABLE;
13169}
13170
15bdd4cf
DV		 13171static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13172 struct intel_shared_dpll *pll)
13173{
3e369b76
ACO		 13174 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13175 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13176}
13177
e7b903d2
DV		 13178static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13179 struct intel_shared_dpll *pll)
13180{
e7b903d2 13181 /* PCH refclock must be enabled first */
89eff4be 13182 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13183
3e369b76 13184 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13185
13186 /* Wait for the clocks to stabilize. */
13187 POSTING_READ(PCH_DPLL(pll->id));
13188 udelay(150);
13189
13190 /* The pixel multiplier can only be updated once the
13191 * DPLL is enabled and the clocks are stable.
13192 *
13193 * So write it again.
13194 */
3e369b76 13195 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13196 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13197 udelay(200);
13198}
13199
13200static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13201 struct intel_shared_dpll *pll)
13202{
13203 struct drm_device *dev = dev_priv->dev;
13204 struct intel_crtc *crtc;
e7b903d2
DV		 13205
13206 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13207 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13208 if (intel_crtc_to_shared_dpll(crtc) == pll)
13209 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13210 }
13211
15bdd4cf
DV		 13212 I915_WRITE(PCH_DPLL(pll->id), 0);
13213 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13214 udelay(200);
13215}
13216
46edb027
DV		 13217static char *ibx_pch_dpll_names[] = {
13218 "PCH DPLL A",
13219 "PCH DPLL B",
13220};
13221
7c74ade1 13222static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13223{
e7b903d2 13224 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13225 int i;
13226
7c74ade1 13227 dev_priv->num_shared_dpll = 2;
ee7b9f93 13228
e72f9fbf 13229 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13230 dev_priv->shared_dplls[i].id = i;
13231 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13232 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13233 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13234 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13235 dev_priv->shared_dplls[i].get_hw_state =
13236 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13237 }
13238}
13239
7c74ade1
DV		 13240static void intel_shared_dpll_init(struct drm_device *dev)
13241{
e7b903d2 13242 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13243
b6283055
VS		 13244 intel_update_cdclk(dev);
13245
9cd86933
DV		 13246 if (HAS_DDI(dev))
13247 intel_ddi_pll_init(dev);
13248 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13249 ibx_pch_dpll_init(dev);
13250 else
13251 dev_priv->num_shared_dpll = 0;
13252
13253 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13254}
13255
6beb8c23
MR		 13256/**
13257 * intel_prepare_plane_fb - Prepare fb for usage on plane
13258 * @plane: drm plane to prepare for
13259 * @fb: framebuffer to prepare for presentation
13260 *
13261 * Prepares a framebuffer for usage on a display plane. Generally this
13262 * involves pinning the underlying object and updating the frontbuffer tracking
13263 * bits. Some older platforms need special physical address handling for
13264 * cursor planes.
13265 *
13266 * Returns 0 on success, negative error code on failure.
13267 */
13268int
13269intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13270 struct drm_framebuffer *fb,
13271 const struct drm_plane_state *new_state)
465c120c
MR		 13272{
13273 struct drm_device *dev = plane->dev;
6beb8c23 13274 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13275 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13276 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13277 int ret = 0;
465c120c 13278
ea2c67bb 13279 if (!obj)
465c120c
MR		 13280 return 0;
13281
6beb8c23 13282 mutex_lock(&dev->struct_mutex);
465c120c 13283
6beb8c23
MR		 13284 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13285 INTEL_INFO(dev)->cursor_needs_physical) {
13286 int align = IS_I830(dev) ? 16 * 1024 : 256;
13287 ret = i915_gem_object_attach_phys(obj, align);
13288 if (ret)
13289 DRM_DEBUG_KMS("failed to attach phys object\n");
13290 } else {
91af127f 13291 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13292 }
465c120c 13293
6beb8c23 13294 if (ret == 0)
a9ff8714 13295 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13296
4c34574f 13297 mutex_unlock(&dev->struct_mutex);
465c120c 13298
6beb8c23
MR		 13299 return ret;
13300}
13301
38f3ce3a
MR		 13302/**
13303 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13304 * @plane: drm plane to clean up for
13305 * @fb: old framebuffer that was on plane
13306 *
13307 * Cleans up a framebuffer that has just been removed from a plane.
13308 */
13309void
13310intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13311 struct drm_framebuffer *fb,
13312 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13313{
13314 struct drm_device *dev = plane->dev;
13315 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13316
13317 if (WARN_ON(!obj))
13318 return;
13319
13320 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13321 !INTEL_INFO(dev)->cursor_needs_physical) {
13322 mutex_lock(&dev->struct_mutex);
82bc3b2d 13323 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13324 mutex_unlock(&dev->struct_mutex);
13325 }
465c120c
MR		 13326}
13327
6156a456
CK		 13328int
13329skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13330{
13331 int max_scale;
13332 struct drm_device *dev;
13333 struct drm_i915_private *dev_priv;
13334 int crtc_clock, cdclk;
13335
13336 if (!intel_crtc || !crtc_state)
13337 return DRM_PLANE_HELPER_NO_SCALING;
13338
13339 dev = intel_crtc->base.dev;
13340 dev_priv = dev->dev_private;
13341 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13342 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13343
13344 if (!crtc_clock || !cdclk)
13345 return DRM_PLANE_HELPER_NO_SCALING;
13346
13347 /*
13348 * skl max scale is lower of:
13349 * close to 3 but not 3, -1 is for that purpose
13350 * or
13351 * cdclk/crtc_clock
13352 */
13353 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13354
13355 return max_scale;
13356}
13357
465c120c 13358static int
3c692a41 13359intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13360 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13361 struct intel_plane_state *state)
13362{
2b875c22
MR		 13363 struct drm_crtc *crtc = state->base.crtc;
13364 struct drm_framebuffer *fb = state->base.fb;
6156a456 13365 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13366 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13367 bool can_position = false;
465c120c 13368
061e4b8d
ML		 13369 /* use scaler when colorkey is not required */
13370 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13371 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13372 min_scale = 1;
13373 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13374 can_position = true;
6156a456 13375 }
d8106366 13376
061e4b8d
ML		 13377 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13378 &state->dst, &state->clip,
da20eabd
ML		 13379 min_scale, max_scale,
13380 can_position, true,
13381 &state->visible);
14af293f
GP		 13382}
13383
13384static void
13385intel_commit_primary_plane(struct drm_plane *plane,
13386 struct intel_plane_state *state)
13387{
2b875c22
MR		 13388 struct drm_crtc *crtc = state->base.crtc;
13389 struct drm_framebuffer *fb = state->base.fb;
13390 struct drm_device *dev = plane->dev;
14af293f 13391 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13392 struct intel_crtc *intel_crtc;
14af293f
GP		 13393 struct drm_rect *src = &state->src;
13394
ea2c67bb
MR		 13395 crtc = crtc ? crtc : plane->crtc;
13396 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13397
13398 plane->fb = fb;
9dc806fc
MR		 13399 crtc->x = src->x1 >> 16;
13400 crtc->y = src->y1 >> 16;
ccc759dc 13401
a539205a 13402 if (!crtc->state->active)
302d19ac 13403 return;
465c120c 13404
302d19ac
ML		 13405 if (state->visible)
13406 /* FIXME: kill this fastboot hack */
13407 intel_update_pipe_size(intel_crtc);
13408
13409 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13410}
13411
a8ad0d8e
ML		 13412static void
13413intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13414 struct drm_crtc *crtc)
a8ad0d8e
ML		 13415{
13416 struct drm_device *dev = plane->dev;
13417 struct drm_i915_private *dev_priv = dev->dev_private;
13418
a8ad0d8e
ML		 13419 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13420}
13421
613d2b27
ML		 13422static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13423 struct drm_crtc_state *old_crtc_state)
3c692a41 13424{
32b7eeec 13425 struct drm_device *dev = crtc->dev;
3c692a41 13426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13427
f015c551 13428 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13429 intel_update_watermarks(crtc);
3c692a41 13430
c34c9ee4 13431 /* Perform vblank evasion around commit operation */
a539205a 13432 if (crtc->state->active)
8f539a83 13433 intel_pipe_update_start(intel_crtc, &intel_crtc->start_vbl_count);
0583236e
ML		 13434
13435 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13436 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13437}
13438
613d2b27
ML		 13439static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13440 struct drm_crtc_state *old_crtc_state)
32b7eeec 13441{
32b7eeec 13442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13443
8f539a83
ML		 13444 if (crtc->state->active)
13445 intel_pipe_update_end(intel_crtc, intel_crtc->start_vbl_count);
3c692a41
GP		 13446}
13447
cf4c7c12 13448/**
4a3b8769
MR		 13449 * intel_plane_destroy - destroy a plane
13450 * @plane: plane to destroy
cf4c7c12 13451 *
4a3b8769
MR		 13452 * Common destruction function for all types of planes (primary, cursor,
13453 * sprite).
cf4c7c12 13454 */
4a3b8769 13455void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13456{
13457 struct intel_plane *intel_plane = to_intel_plane(plane);
13458 drm_plane_cleanup(plane);
13459 kfree(intel_plane);
13460}
13461
65a3fea0 13462const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13463 .update_plane = drm_atomic_helper_update_plane,
13464 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13465 .destroy = intel_plane_destroy,
c196e1d6 13466 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13467 .atomic_get_property = intel_plane_atomic_get_property,
13468 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13469 .atomic_duplicate_state = intel_plane_duplicate_state,
13470 .atomic_destroy_state = intel_plane_destroy_state,
13471
465c120c
MR		 13472};
13473
13474static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13475 int pipe)
13476{
13477 struct intel_plane *primary;
8e7d688b 13478 struct intel_plane_state *state;
465c120c
MR		 13479 const uint32_t *intel_primary_formats;
13480 int num_formats;
13481
13482 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13483 if (primary == NULL)
13484 return NULL;
13485
8e7d688b
MR		 13486 state = intel_create_plane_state(&primary->base);
13487 if (!state) {
ea2c67bb
MR		 13488 kfree(primary);
13489 return NULL;
13490 }
8e7d688b 13491 primary->base.state = &state->base;
ea2c67bb 13492
465c120c
MR		 13493 primary->can_scale = false;
13494 primary->max_downscale = 1;
6156a456
CK		 13495 if (INTEL_INFO(dev)->gen >= 9) {
13496 primary->can_scale = true;
af99ceda 13497 state->scaler_id = -1;
6156a456 13498 }
465c120c
MR		 13499 primary->pipe = pipe;
13500 primary->plane = pipe;
a9ff8714 13501 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13502 primary->check_plane = intel_check_primary_plane;
13503 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13504 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13505 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13506 primary->plane = !pipe;
13507
6c0fd451
DL		 13508 if (INTEL_INFO(dev)->gen >= 9) {
13509 intel_primary_formats = skl_primary_formats;
13510 num_formats = ARRAY_SIZE(skl_primary_formats);
13511 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13512 intel_primary_formats = i965_primary_formats;
13513 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13514 } else {
13515 intel_primary_formats = i8xx_primary_formats;
13516 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13517 }
13518
13519 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13520 &intel_plane_funcs,
465c120c
MR		 13521 intel_primary_formats, num_formats,
13522 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13523
3b7a5119
SJ		 13524 if (INTEL_INFO(dev)->gen >= 4)
13525 intel_create_rotation_property(dev, primary);
48404c1e 13526
ea2c67bb
MR		 13527 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13528
465c120c
MR		 13529 return &primary->base;
13530}
13531
3b7a5119
SJ		 13532void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13533{
13534 if (!dev->mode_config.rotation_property) {
13535 unsigned long flags = BIT(DRM_ROTATE_0) |
13536 BIT(DRM_ROTATE_180);
13537
13538 if (INTEL_INFO(dev)->gen >= 9)
13539 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13540
13541 dev->mode_config.rotation_property =
13542 drm_mode_create_rotation_property(dev, flags);
13543 }
13544 if (dev->mode_config.rotation_property)
13545 drm_object_attach_property(&plane->base.base,
13546 dev->mode_config.rotation_property,
13547 plane->base.state->rotation);
13548}
13549
3d7d6510 13550static int
852e787c 13551intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13552 struct intel_crtc_state *crtc_state,
852e787c 13553 struct intel_plane_state *state)
3d7d6510 13554{
061e4b8d 13555 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13556 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13557 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13558 unsigned stride;
13559 int ret;
3d7d6510 13560
061e4b8d
ML		 13561 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13562 &state->dst, &state->clip,
3d7d6510
MR		 13563 DRM_PLANE_HELPER_NO_SCALING,
13564 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13565 true, true, &state->visible);
757f9a3e
GP		 13566 if (ret)
13567 return ret;
13568
757f9a3e
GP		 13569 /* if we want to turn off the cursor ignore width and height */
13570 if (!obj)
da20eabd 13571 return 0;
757f9a3e 13572
757f9a3e 13573 /* Check for which cursor types we support */
061e4b8d 13574 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13575 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13576 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13577 return -EINVAL;
13578 }
13579
ea2c67bb
MR		 13580 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13581 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13582 DRM_DEBUG_KMS("buffer is too small\n");
13583 return -ENOMEM;
13584 }
13585
3a656b54 13586 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13587 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13588 return -EINVAL;
32b7eeec
MR		 13589 }
13590
da20eabd 13591 return 0;
852e787c 13592}
3d7d6510 13593
a8ad0d8e
ML		 13594static void
13595intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13596 struct drm_crtc *crtc)
a8ad0d8e 13597{
a8ad0d8e
ML		 13598 intel_crtc_update_cursor(crtc, false);
13599}
13600
f4a2cf29 13601static void
852e787c
GP		 13602intel_commit_cursor_plane(struct drm_plane *plane,
13603 struct intel_plane_state *state)
13604{
2b875c22 13605 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13606 struct drm_device *dev = plane->dev;
13607 struct intel_crtc *intel_crtc;
2b875c22 13608 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13609 uint32_t addr;
852e787c 13610
ea2c67bb
MR		 13611 crtc = crtc ? crtc : plane->crtc;
13612 intel_crtc = to_intel_crtc(crtc);
13613
2b875c22 13614 plane->fb = state->base.fb;
ea2c67bb
MR		 13615 crtc->cursor_x = state->base.crtc_x;
13616 crtc->cursor_y = state->base.crtc_y;
13617
a912f12f
GP		 13618 if (intel_crtc->cursor_bo == obj)
13619 goto update;
4ed91096 13620
f4a2cf29 13621 if (!obj)
a912f12f 13622 addr = 0;
f4a2cf29 13623 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13624 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13625 else
a912f12f 13626 addr = obj->phys_handle->busaddr;
852e787c 13627
a912f12f
GP		 13628 intel_crtc->cursor_addr = addr;
13629 intel_crtc->cursor_bo = obj;
852e787c 13630
302d19ac 13631update:
a539205a 13632 if (crtc->state->active)
a912f12f 13633 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13634}
13635
3d7d6510
MR		 13636static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13637 int pipe)
13638{
13639 struct intel_plane *cursor;
8e7d688b 13640 struct intel_plane_state *state;
3d7d6510
MR		 13641
13642 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13643 if (cursor == NULL)
13644 return NULL;
13645
8e7d688b
MR		 13646 state = intel_create_plane_state(&cursor->base);
13647 if (!state) {
ea2c67bb
MR		 13648 kfree(cursor);
13649 return NULL;
13650 }
8e7d688b 13651 cursor->base.state = &state->base;
ea2c67bb 13652
3d7d6510
MR		 13653 cursor->can_scale = false;
13654 cursor->max_downscale = 1;
13655 cursor->pipe = pipe;
13656 cursor->plane = pipe;
a9ff8714 13657 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13658 cursor->check_plane = intel_check_cursor_plane;
13659 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13660 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13661
13662 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13663 &intel_plane_funcs,
3d7d6510
MR		 13664 intel_cursor_formats,
13665 ARRAY_SIZE(intel_cursor_formats),
13666 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13667
13668 if (INTEL_INFO(dev)->gen >= 4) {
13669 if (!dev->mode_config.rotation_property)
13670 dev->mode_config.rotation_property =
13671 drm_mode_create_rotation_property(dev,
13672 BIT(DRM_ROTATE_0) |
13673 BIT(DRM_ROTATE_180));
13674 if (dev->mode_config.rotation_property)
13675 drm_object_attach_property(&cursor->base.base,
13676 dev->mode_config.rotation_property,
8e7d688b 13677 state->base.rotation);
4398ad45
VS		 13678 }
13679
af99ceda
CK		 13680 if (INTEL_INFO(dev)->gen >=9)
13681 state->scaler_id = -1;
13682
ea2c67bb
MR		 13683 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13684
3d7d6510
MR		 13685 return &cursor->base;
13686}
13687
549e2bfb
CK		 13688static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13689 struct intel_crtc_state *crtc_state)
13690{
13691 int i;
13692 struct intel_scaler *intel_scaler;
13693 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13694
13695 for (i = 0; i < intel_crtc->num_scalers; i++) {
13696 intel_scaler = &scaler_state->scalers[i];
13697 intel_scaler->in_use = 0;
549e2bfb
CK		 13698 intel_scaler->mode = PS_SCALER_MODE_DYN;
13699 }
13700
13701 scaler_state->scaler_id = -1;
13702}
13703
b358d0a6 13704static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13705{
fbee40df 13706 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13707 struct intel_crtc *intel_crtc;
f5de6e07 13708 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13709 struct drm_plane *primary = NULL;
13710 struct drm_plane *cursor = NULL;
465c120c 13711 int i, ret;
79e53945 13712
955382f3 13713 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13714 if (intel_crtc == NULL)
13715 return;
13716
f5de6e07
ACO		 13717 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13718 if (!crtc_state)
13719 goto fail;
550acefd
ACO		 13720 intel_crtc->config = crtc_state;
13721 intel_crtc->base.state = &crtc_state->base;
07878248 13722 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13723
549e2bfb
CK		 13724 /* initialize shared scalers */
13725 if (INTEL_INFO(dev)->gen >= 9) {
13726 if (pipe == PIPE_C)
13727 intel_crtc->num_scalers = 1;
13728 else
13729 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13730
13731 skl_init_scalers(dev, intel_crtc, crtc_state);
13732 }
13733
465c120c 13734 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13735 if (!primary)
13736 goto fail;
13737
13738 cursor = intel_cursor_plane_create(dev, pipe);
13739 if (!cursor)
13740 goto fail;
13741
465c120c 13742 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13743 cursor, &intel_crtc_funcs);
13744 if (ret)
13745 goto fail;
79e53945
JB		 13746
13747 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13748 for (i = 0; i < 256; i++) {
13749 intel_crtc->lut_r[i] = i;
13750 intel_crtc->lut_g[i] = i;
13751 intel_crtc->lut_b[i] = i;
13752 }
13753
1f1c2e24
VS		 13754 /*
13755 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13756 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13757 */
80824003
JB		 13758 intel_crtc->pipe = pipe;
13759 intel_crtc->plane = pipe;
3a77c4c4 13760 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13761 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13762 intel_crtc->plane = !pipe;
80824003
JB		 13763 }
13764
4b0e333e
CW		 13765 intel_crtc->cursor_base = ~0;
13766 intel_crtc->cursor_cntl = ~0;
dc41c154 13767 intel_crtc->cursor_size = ~0;
8d7849db 13768
852eb00d
VS		 13769 intel_crtc->wm.cxsr_allowed = true;
13770
22fd0fab
JB		 13771 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13772 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13773 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13774 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13775
79e53945 13776 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13777
13778 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13779 return;
13780
13781fail:
13782 if (primary)
13783 drm_plane_cleanup(primary);
13784 if (cursor)
13785 drm_plane_cleanup(cursor);
f5de6e07 13786 kfree(crtc_state);
3d7d6510 13787 kfree(intel_crtc);
79e53945
JB		 13788}
13789
752aa88a
JB		 13790enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13791{
13792 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13793 struct drm_device *dev = connector->base.dev;
752aa88a 13794
51fd371b 13795 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13796
d3babd3f 13797 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13798 return INVALID_PIPE;
13799
13800 return to_intel_crtc(encoder->crtc)->pipe;
13801}
13802
08d7b3d1 13803int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13804 struct drm_file *file)
08d7b3d1 13805{
08d7b3d1 13806 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13807 struct drm_crtc *drmmode_crtc;
c05422d5 13808 struct intel_crtc *crtc;
08d7b3d1 13809
7707e653 13810 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13811
7707e653 13812 if (!drmmode_crtc) {
08d7b3d1 13813 DRM_ERROR("no such CRTC id\n");
3f2c2057 13814 return -ENOENT;
08d7b3d1
CW		 13815 }
13816
7707e653 13817 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13818 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13819
c05422d5 13820 return 0;
08d7b3d1
CW		 13821}
13822
66a9278e 13823static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13824{
66a9278e
DV		 13825 struct drm_device *dev = encoder->base.dev;
13826 struct intel_encoder *source_encoder;
79e53945 13827 int index_mask = 0;
79e53945
JB		 13828 int entry = 0;
13829
b2784e15 13830 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13831 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13832 index_mask |= (1 << entry);
13833
79e53945
JB		 13834 entry++;
13835 }
4ef69c7a 13836
79e53945
JB		 13837 return index_mask;
13838}
13839
4d302442
CW		 13840static bool has_edp_a(struct drm_device *dev)
13841{
13842 struct drm_i915_private *dev_priv = dev->dev_private;
13843
13844 if (!IS_MOBILE(dev))
13845 return false;
13846
13847 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13848 return false;
13849
e3589908 13850 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13851 return false;
13852
13853 return true;
13854}
13855
84b4e042
JB		 13856static bool intel_crt_present(struct drm_device *dev)
13857{
13858 struct drm_i915_private *dev_priv = dev->dev_private;
13859
884497ed
DL		 13860 if (INTEL_INFO(dev)->gen >= 9)
13861 return false;
13862
cf404ce4 13863 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13864 return false;
13865
13866 if (IS_CHERRYVIEW(dev))
13867 return false;
13868
13869 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13870 return false;
13871
13872 return true;
13873}
13874
79e53945
JB		 13875static void intel_setup_outputs(struct drm_device *dev)
13876{
725e30ad 13877 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13878 struct intel_encoder *encoder;
cb0953d7 13879 bool dpd_is_edp = false;
79e53945 13880
c9093354 13881 intel_lvds_init(dev);
79e53945 13882
84b4e042 13883 if (intel_crt_present(dev))
79935fca 13884 intel_crt_init(dev);
cb0953d7 13885
c776eb2e
VK		 13886 if (IS_BROXTON(dev)) {
13887 /*
13888 * FIXME: Broxton doesn't support port detection via the
13889 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13890 * detect the ports.
13891 */
13892 intel_ddi_init(dev, PORT_A);
13893 intel_ddi_init(dev, PORT_B);
13894 intel_ddi_init(dev, PORT_C);
13895 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13896 int found;
13897
de31facd
JB		 13898 /*
13899 * Haswell uses DDI functions to detect digital outputs.
13900 * On SKL pre-D0 the strap isn't connected, so we assume
13901 * it's there.
13902 */
0e72a5b5 13903 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd 13904 /* WaIgnoreDDIAStrap: skl */
5a2376d1 13905 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 13906 intel_ddi_init(dev, PORT_A);
13907
13908 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13909 * register */
13910 found = I915_READ(SFUSE_STRAP);
13911
13912 if (found & SFUSE_STRAP_DDIB_DETECTED)
13913 intel_ddi_init(dev, PORT_B);
13914 if (found & SFUSE_STRAP_DDIC_DETECTED)
13915 intel_ddi_init(dev, PORT_C);
13916 if (found & SFUSE_STRAP_DDID_DETECTED)
13917 intel_ddi_init(dev, PORT_D);
13918 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13919 int found;
5d8a7752 13920 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13921
13922 if (has_edp_a(dev))
13923 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13924
dc0fa718 13925 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13926 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13927 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13928 if (!found)
e2debe91 13929 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13930 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13931 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13932 }
13933
dc0fa718 13934 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13935 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13936
dc0fa718 13937 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13938 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13939
5eb08b69 13940 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13941 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13942
270b3042 13943 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13944 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13945 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13946 /*
13947 * The DP_DETECTED bit is the latched state of the DDC
13948 * SDA pin at boot. However since eDP doesn't require DDC
13949 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13950 * eDP ports may have been muxed to an alternate function.
13951 * Thus we can't rely on the DP_DETECTED bit alone to detect
13952 * eDP ports. Consult the VBT as well as DP_DETECTED to
13953 * detect eDP ports.
13954 */
d2182a66
VS		 13955 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13956 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13957 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13958 PORT_B);
e17ac6db
VS		 13959 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13960 intel_dp_is_edp(dev, PORT_B))
13961 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13962
d2182a66
VS		 13963 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13964 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13965 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13966 PORT_C);
e17ac6db
VS		 13967 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13968 intel_dp_is_edp(dev, PORT_C))
13969 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13970
9418c1f1 13971 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13972 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13973 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13974 PORT_D);
e17ac6db
VS		 13975 /* eDP not supported on port D, so don't check VBT */
13976 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13977 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13978 }
13979
3cfca973 13980 intel_dsi_init(dev);
09da55dc 13981 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 13982 bool found = false;
7d57382e 13983
e2debe91 13984 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13985 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13986 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 13987 if (!found && IS_G4X(dev)) {
b01f2c3a 13988 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13989 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13990 }
27185ae1 13991
3fec3d2f 13992 if (!found && IS_G4X(dev))
ab9d7c30 13993 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13994 }
13520b05
KH		 13995
13996 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13997
e2debe91 13998 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13999 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14000 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14001 }
27185ae1 14002
e2debe91 14003 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14004
3fec3d2f 14005 if (IS_G4X(dev)) {
b01f2c3a 14006 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14007 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14008 }
3fec3d2f 14009 if (IS_G4X(dev))
ab9d7c30 14010 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14011 }
27185ae1 14012
3fec3d2f 14013 if (IS_G4X(dev) &&
e7281eab 14014 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14015 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14016 } else if (IS_GEN2(dev))
79e53945
JB		 14017 intel_dvo_init(dev);
14018
103a196f 14019 if (SUPPORTS_TV(dev))
79e53945
JB		 14020 intel_tv_init(dev);
14021
0bc12bcb 14022 intel_psr_init(dev);
7c8f8a70 14023
b2784e15 14024 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14025 encoder->base.possible_crtcs = encoder->crtc_mask;
14026 encoder->base.possible_clones =
66a9278e 14027 intel_encoder_clones(encoder);
79e53945 14028 }
47356eb6 14029
dde86e2d 14030 intel_init_pch_refclk(dev);
270b3042
DV		 14031
14032 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14033}
14034
14035static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14036{
60a5ca01 14037 struct drm_device *dev = fb->dev;
79e53945 14038 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14039
ef2d633e 14040 drm_framebuffer_cleanup(fb);
60a5ca01 14041 mutex_lock(&dev->struct_mutex);
ef2d633e 14042 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14043 drm_gem_object_unreference(&intel_fb->obj->base);
14044 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14045 kfree(intel_fb);
14046}
14047
14048static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14049 struct drm_file *file,
79e53945
JB		 14050 unsigned int *handle)
14051{
14052 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14053 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14054
05394f39 14055 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14056}
14057
86c98588
RV		 14058static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14059 struct drm_file *file,
14060 unsigned flags, unsigned color,
14061 struct drm_clip_rect *clips,
14062 unsigned num_clips)
14063{
14064 struct drm_device *dev = fb->dev;
14065 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14066 struct drm_i915_gem_object *obj = intel_fb->obj;
14067
14068 mutex_lock(&dev->struct_mutex);
74b4ea1e 14069 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14070 mutex_unlock(&dev->struct_mutex);
14071
14072 return 0;
14073}
14074
79e53945
JB		 14075static const struct drm_framebuffer_funcs intel_fb_funcs = {
14076 .destroy = intel_user_framebuffer_destroy,
14077 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14078 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14079};
14080
b321803d
DL		 14081static
14082u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14083 uint32_t pixel_format)
14084{
14085 u32 gen = INTEL_INFO(dev)->gen;
14086
14087 if (gen >= 9) {
14088 /* "The stride in bytes must not exceed the of the size of 8K
14089 * pixels and 32K bytes."
14090 */
14091 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14092 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14093 return 32*1024;
14094 } else if (gen >= 4) {
14095 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14096 return 16*1024;
14097 else
14098 return 32*1024;
14099 } else if (gen >= 3) {
14100 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14101 return 8*1024;
14102 else
14103 return 16*1024;
14104 } else {
14105 /* XXX DSPC is limited to 4k tiled */
14106 return 8*1024;
14107 }
14108}
14109
b5ea642a
DV		 14110static int intel_framebuffer_init(struct drm_device *dev,
14111 struct intel_framebuffer *intel_fb,
14112 struct drm_mode_fb_cmd2 *mode_cmd,
14113 struct drm_i915_gem_object *obj)
79e53945 14114{
6761dd31 14115 unsigned int aligned_height;
79e53945 14116 int ret;
b321803d 14117 u32 pitch_limit, stride_alignment;
79e53945 14118
dd4916c5
DV		 14119 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14120
2a80eada
DV		 14121 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14122 /* Enforce that fb modifier and tiling mode match, but only for
14123 * X-tiled. This is needed for FBC. */
14124 if (!!(obj->tiling_mode == I915_TILING_X) !=
14125 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14126 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14127 return -EINVAL;
14128 }
14129 } else {
14130 if (obj->tiling_mode == I915_TILING_X)
14131 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14132 else if (obj->tiling_mode == I915_TILING_Y) {
14133 DRM_DEBUG("No Y tiling for legacy addfb\n");
14134 return -EINVAL;
14135 }
14136 }
14137
9a8f0a12
TU		 14138 /* Passed in modifier sanity checking. */
14139 switch (mode_cmd->modifier[0]) {
14140 case I915_FORMAT_MOD_Y_TILED:
14141 case I915_FORMAT_MOD_Yf_TILED:
14142 if (INTEL_INFO(dev)->gen < 9) {
14143 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14144 mode_cmd->modifier[0]);
14145 return -EINVAL;
14146 }
14147 case DRM_FORMAT_MOD_NONE:
14148 case I915_FORMAT_MOD_X_TILED:
14149 break;
14150 default:
c0f40428
JB		 14151 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14152 mode_cmd->modifier[0]);
57cd6508 14153 return -EINVAL;
c16ed4be 14154 }
57cd6508 14155
b321803d
DL		 14156 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14157 mode_cmd->pixel_format);
14158 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14159 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14160 mode_cmd->pitches[0], stride_alignment);
57cd6508 14161 return -EINVAL;
c16ed4be 14162 }
57cd6508 14163
b321803d
DL		 14164 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14165 mode_cmd->pixel_format);
a35cdaa0 14166 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14167 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14168 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14169 "tiled" : "linear",
a35cdaa0 14170 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14171 return -EINVAL;
c16ed4be 14172 }
5d7bd705 14173
2a80eada 14174 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14175 mode_cmd->pitches[0] != obj->stride) {
14176 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14177 mode_cmd->pitches[0], obj->stride);
5d7bd705 14178 return -EINVAL;
c16ed4be 14179 }
5d7bd705 14180
57779d06 14181 /* Reject formats not supported by any plane early. */
308e5bcb 14182 switch (mode_cmd->pixel_format) {
57779d06 14183 case DRM_FORMAT_C8:
04b3924d
VS		 14184 case DRM_FORMAT_RGB565:
14185 case DRM_FORMAT_XRGB8888:
14186 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14187 break;
14188 case DRM_FORMAT_XRGB1555:
c16ed4be 14189 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14190 DRM_DEBUG("unsupported pixel format: %s\n",
14191 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14192 return -EINVAL;
c16ed4be 14193 }
57779d06 14194 break;
57779d06 14195 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14196 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14197 DRM_DEBUG("unsupported pixel format: %s\n",
14198 drm_get_format_name(mode_cmd->pixel_format));
14199 return -EINVAL;
14200 }
14201 break;
14202 case DRM_FORMAT_XBGR8888:
04b3924d 14203 case DRM_FORMAT_XRGB2101010:
57779d06 14204 case DRM_FORMAT_XBGR2101010:
c16ed4be 14205 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14206 DRM_DEBUG("unsupported pixel format: %s\n",
14207 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14208 return -EINVAL;
c16ed4be 14209 }
b5626747 14210 break;
7531208b
DL		 14211 case DRM_FORMAT_ABGR2101010:
14212 if (!IS_VALLEYVIEW(dev)) {
14213 DRM_DEBUG("unsupported pixel format: %s\n",
14214 drm_get_format_name(mode_cmd->pixel_format));
14215 return -EINVAL;
14216 }
14217 break;
04b3924d
VS		 14218 case DRM_FORMAT_YUYV:
14219 case DRM_FORMAT_UYVY:
14220 case DRM_FORMAT_YVYU:
14221 case DRM_FORMAT_VYUY:
c16ed4be 14222 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14223 DRM_DEBUG("unsupported pixel format: %s\n",
14224 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14225 return -EINVAL;
c16ed4be 14226 }
57cd6508
CW		 14227 break;
14228 default:
4ee62c76
VS		 14229 DRM_DEBUG("unsupported pixel format: %s\n",
14230 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14231 return -EINVAL;
14232 }
14233
90f9a336
VS		 14234 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14235 if (mode_cmd->offsets[0] != 0)
14236 return -EINVAL;
14237
ec2c981e 14238 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14239 mode_cmd->pixel_format,
14240 mode_cmd->modifier[0]);
53155c0a
DV		 14241 /* FIXME drm helper for size checks (especially planar formats)? */
14242 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14243 return -EINVAL;
14244
c7d73f6a
DV		 14245 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14246 intel_fb->obj = obj;
80075d49 14247 intel_fb->obj->framebuffer_references++;
c7d73f6a 14248
79e53945
JB		 14249 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14250 if (ret) {
14251 DRM_ERROR("framebuffer init failed %d\n", ret);
14252 return ret;
14253 }
14254
79e53945
JB		 14255 return 0;
14256}
14257
79e53945
JB		 14258static struct drm_framebuffer *
14259intel_user_framebuffer_create(struct drm_device *dev,
14260 struct drm_file *filp,
308e5bcb 14261 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14262{
05394f39 14263 struct drm_i915_gem_object *obj;
79e53945 14264
308e5bcb
JB		 14265 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14266 mode_cmd->handles[0]));
c8725226 14267 if (&obj->base == NULL)
cce13ff7 14268 return ERR_PTR(-ENOENT);
79e53945 14269
d2dff872 14270 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14271}
14272
4520f53a 14273#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14274static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14275{
14276}
14277#endif
14278
79e53945 14279static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14280 .fb_create = intel_user_framebuffer_create,
0632fef6 14281 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14282 .atomic_check = intel_atomic_check,
14283 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14284 .atomic_state_alloc = intel_atomic_state_alloc,
14285 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14286};
14287
e70236a8
JB		 14288/* Set up chip specific display functions */
14289static void intel_init_display(struct drm_device *dev)
14290{
14291 struct drm_i915_private *dev_priv = dev->dev_private;
14292
ee9300bb
DV		 14293 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14294 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14295 else if (IS_CHERRYVIEW(dev))
14296 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14297 else if (IS_VALLEYVIEW(dev))
14298 dev_priv->display.find_dpll = vlv_find_best_dpll;
14299 else if (IS_PINEVIEW(dev))
14300 dev_priv->display.find_dpll = pnv_find_best_dpll;
14301 else
14302 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14303
bc8d7dff
DL		 14304 if (INTEL_INFO(dev)->gen >= 9) {
14305 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14306 dev_priv->display.get_initial_plane_config =
14307 skylake_get_initial_plane_config;
bc8d7dff
DL		 14308 dev_priv->display.crtc_compute_clock =
14309 haswell_crtc_compute_clock;
14310 dev_priv->display.crtc_enable = haswell_crtc_enable;
14311 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14312 dev_priv->display.update_primary_plane =
14313 skylake_update_primary_plane;
14314 } else if (HAS_DDI(dev)) {
0e8ffe1b 14315 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14316 dev_priv->display.get_initial_plane_config =
14317 ironlake_get_initial_plane_config;
797d0259
ACO		 14318 dev_priv->display.crtc_compute_clock =
14319 haswell_crtc_compute_clock;
4f771f10
PZ		 14320 dev_priv->display.crtc_enable = haswell_crtc_enable;
14321 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14322 dev_priv->display.update_primary_plane =
14323 ironlake_update_primary_plane;
09b4ddf9 14324 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14325 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14326 dev_priv->display.get_initial_plane_config =
14327 ironlake_get_initial_plane_config;
3fb37703
ACO		 14328 dev_priv->display.crtc_compute_clock =
14329 ironlake_crtc_compute_clock;
76e5a89c
DV		 14330 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14331 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14332 dev_priv->display.update_primary_plane =
14333 ironlake_update_primary_plane;
89b667f8
JB		 14334 } else if (IS_VALLEYVIEW(dev)) {
14335 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14336 dev_priv->display.get_initial_plane_config =
14337 i9xx_get_initial_plane_config;
d6dfee7a 14338 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14339 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14340 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14341 dev_priv->display.update_primary_plane =
14342 i9xx_update_primary_plane;
f564048e 14343 } else {
0e8ffe1b 14344 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14345 dev_priv->display.get_initial_plane_config =
14346 i9xx_get_initial_plane_config;
d6dfee7a 14347 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14348 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14349 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14350 dev_priv->display.update_primary_plane =
14351 i9xx_update_primary_plane;
f564048e 14352 }
e70236a8 14353
e70236a8 14354 /* Returns the core display clock speed */
1652d19e
VS		 14355 if (IS_SKYLAKE(dev))
14356 dev_priv->display.get_display_clock_speed =
14357 skylake_get_display_clock_speed;
acd3f3d3
BP		 14358 else if (IS_BROXTON(dev))
14359 dev_priv->display.get_display_clock_speed =
14360 broxton_get_display_clock_speed;
1652d19e
VS		 14361 else if (IS_BROADWELL(dev))
14362 dev_priv->display.get_display_clock_speed =
14363 broadwell_get_display_clock_speed;
14364 else if (IS_HASWELL(dev))
14365 dev_priv->display.get_display_clock_speed =
14366 haswell_get_display_clock_speed;
14367 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14368 dev_priv->display.get_display_clock_speed =
14369 valleyview_get_display_clock_speed;
b37a6434
VS		 14370 else if (IS_GEN5(dev))
14371 dev_priv->display.get_display_clock_speed =
14372 ilk_get_display_clock_speed;
a7c66cd8 14373 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14374 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14375 dev_priv->display.get_display_clock_speed =
14376 i945_get_display_clock_speed;
34edce2f
VS		 14377 else if (IS_GM45(dev))
14378 dev_priv->display.get_display_clock_speed =
14379 gm45_get_display_clock_speed;
14380 else if (IS_CRESTLINE(dev))
14381 dev_priv->display.get_display_clock_speed =
14382 i965gm_get_display_clock_speed;
14383 else if (IS_PINEVIEW(dev))
14384 dev_priv->display.get_display_clock_speed =
14385 pnv_get_display_clock_speed;
14386 else if (IS_G33(dev) || IS_G4X(dev))
14387 dev_priv->display.get_display_clock_speed =
14388 g33_get_display_clock_speed;
e70236a8
JB		 14389 else if (IS_I915G(dev))
14390 dev_priv->display.get_display_clock_speed =
14391 i915_get_display_clock_speed;
257a7ffc 14392 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14393 dev_priv->display.get_display_clock_speed =
14394 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14395 else if (IS_PINEVIEW(dev))
14396 dev_priv->display.get_display_clock_speed =
14397 pnv_get_display_clock_speed;
e70236a8
JB		 14398 else if (IS_I915GM(dev))
14399 dev_priv->display.get_display_clock_speed =
14400 i915gm_get_display_clock_speed;
14401 else if (IS_I865G(dev))
14402 dev_priv->display.get_display_clock_speed =
14403 i865_get_display_clock_speed;
f0f8a9ce 14404 else if (IS_I85X(dev))
e70236a8 14405 dev_priv->display.get_display_clock_speed =
1b1d2716 14406 i85x_get_display_clock_speed;
623e01e5
VS		 14407 else { /* 830 */
14408 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14409 dev_priv->display.get_display_clock_speed =
14410 i830_get_display_clock_speed;
623e01e5 14411 }
e70236a8 14412
7c10a2b5 14413 if (IS_GEN5(dev)) {
3bb11b53 14414 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14415 } else if (IS_GEN6(dev)) {
14416 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14417 } else if (IS_IVYBRIDGE(dev)) {
14418 /* FIXME: detect B0+ stepping and use auto training */
14419 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14420 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14421 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14422 if (IS_BROADWELL(dev)) {
14423 dev_priv->display.modeset_commit_cdclk =
14424 broadwell_modeset_commit_cdclk;
14425 dev_priv->display.modeset_calc_cdclk =
14426 broadwell_modeset_calc_cdclk;
14427 }
30a970c6 14428 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14429 dev_priv->display.modeset_commit_cdclk =
14430 valleyview_modeset_commit_cdclk;
14431 dev_priv->display.modeset_calc_cdclk =
14432 valleyview_modeset_calc_cdclk;
f8437dd1 14433 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14434 dev_priv->display.modeset_commit_cdclk =
14435 broxton_modeset_commit_cdclk;
14436 dev_priv->display.modeset_calc_cdclk =
14437 broxton_modeset_calc_cdclk;
e70236a8 14438 }
8c9f3aaf 14439
8c9f3aaf
JB		 14440 switch (INTEL_INFO(dev)->gen) {
14441 case 2:
14442 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14443 break;
14444
14445 case 3:
14446 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14447 break;
14448
14449 case 4:
14450 case 5:
14451 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14452 break;
14453
14454 case 6:
14455 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14456 break;
7c9017e5 14457 case 7:
4e0bbc31 14458 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14459 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14460 break;
830c81db 14461 case 9:
ba343e02
TU		 14462 /* Drop through - unsupported since execlist only. */
14463 default:
14464 /* Default just returns -ENODEV to indicate unsupported */
14465 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14466 }
7bd688cd
JN		 14467
14468 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14469
14470 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14471}
14472
b690e96c
JB		 14473/*
14474 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14475 * resume, or other times. This quirk makes sure that's the case for
14476 * affected systems.
14477 */
0206e353 14478static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14479{
14480 struct drm_i915_private *dev_priv = dev->dev_private;
14481
14482 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14483 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14484}
14485
b6b5d049
VS		 14486static void quirk_pipeb_force(struct drm_device *dev)
14487{
14488 struct drm_i915_private *dev_priv = dev->dev_private;
14489
14490 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14491 DRM_INFO("applying pipe b force quirk\n");
14492}
14493
435793df
KP		 14494/*
14495 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14496 */
14497static void quirk_ssc_force_disable(struct drm_device *dev)
14498{
14499 struct drm_i915_private *dev_priv = dev->dev_private;
14500 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14501 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14502}
14503
4dca20ef 14504/*
5a15ab5b
CE		 14505 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14506 * brightness value
4dca20ef
CE		 14507 */
14508static void quirk_invert_brightness(struct drm_device *dev)
14509{
14510 struct drm_i915_private *dev_priv = dev->dev_private;
14511 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14512 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14513}
14514
9c72cc6f
SD		 14515/* Some VBT's incorrectly indicate no backlight is present */
14516static void quirk_backlight_present(struct drm_device *dev)
14517{
14518 struct drm_i915_private *dev_priv = dev->dev_private;
14519 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14520 DRM_INFO("applying backlight present quirk\n");
14521}
14522
b690e96c
JB		 14523struct intel_quirk {
14524 int device;
14525 int subsystem_vendor;
14526 int subsystem_device;
14527 void (*hook)(struct drm_device *dev);
14528};
14529
5f85f176
EE		 14530/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14531struct intel_dmi_quirk {
14532 void (*hook)(struct drm_device *dev);
14533 const struct dmi_system_id (*dmi_id_list)[];
14534};
14535
14536static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14537{
14538 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14539 return 1;
14540}
14541
14542static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14543 {
14544 .dmi_id_list = &(const struct dmi_system_id[]) {
14545 {
14546 .callback = intel_dmi_reverse_brightness,
14547 .ident = "NCR Corporation",
14548 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14549 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14550 },
14551 },
14552 { } /* terminating entry */
14553 },
14554 .hook = quirk_invert_brightness,
14555 },
14556};
14557
c43b5634 14558static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14559 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14560 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14561
b690e96c
JB		 14562 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14563 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14564
5f080c0f
VS		 14565 /* 830 needs to leave pipe A & dpll A up */
14566 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14567
b6b5d049
VS		 14568 /* 830 needs to leave pipe B & dpll B up */
14569 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14570
435793df
KP		 14571 /* Lenovo U160 cannot use SSC on LVDS */
14572 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14573
14574 /* Sony Vaio Y cannot use SSC on LVDS */
14575 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14576
be505f64
AH		 14577 /* Acer Aspire 5734Z must invert backlight brightness */
14578 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14579
14580 /* Acer/eMachines G725 */
14581 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14582
14583 /* Acer/eMachines e725 */
14584 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14585
14586 /* Acer/Packard Bell NCL20 */
14587 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14588
14589 /* Acer Aspire 4736Z */
14590 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14591
14592 /* Acer Aspire 5336 */
14593 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14594
14595 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14596 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14597
dfb3d47b
SD		 14598 /* Acer C720 Chromebook (Core i3 4005U) */
14599 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14600
b2a9601c 14601 /* Apple Macbook 2,1 (Core 2 T7400) */
14602 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14603
d4967d8c
SD		 14604 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14605 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14606
14607 /* HP Chromebook 14 (Celeron 2955U) */
14608 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14609
14610 /* Dell Chromebook 11 */
14611 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14612};
14613
14614static void intel_init_quirks(struct drm_device *dev)
14615{
14616 struct pci_dev *d = dev->pdev;
14617 int i;
14618
14619 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14620 struct intel_quirk *q = &intel_quirks[i];
14621
14622 if (d->device == q->device &&
14623 (d->subsystem_vendor == q->subsystem_vendor ||
14624 q->subsystem_vendor == PCI_ANY_ID) &&
14625 (d->subsystem_device == q->subsystem_device ||
14626 q->subsystem_device == PCI_ANY_ID))
14627 q->hook(dev);
14628 }
5f85f176
EE		 14629 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14630 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14631 intel_dmi_quirks[i].hook(dev);
14632 }
b690e96c
JB		 14633}
14634
9cce37f4
JB		 14635/* Disable the VGA plane that we never use */
14636static void i915_disable_vga(struct drm_device *dev)
14637{
14638 struct drm_i915_private *dev_priv = dev->dev_private;
14639 u8 sr1;
766aa1c4 14640 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14641
2b37c616 14642 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14643 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14644 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14645 sr1 = inb(VGA_SR_DATA);
14646 outb(sr1 | 1<<5, VGA_SR_DATA);
14647 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14648 udelay(300);
14649
01f5a626 14650 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14651 POSTING_READ(vga_reg);
14652}
14653
f817586c
DV		 14654void intel_modeset_init_hw(struct drm_device *dev)
14655{
b6283055 14656 intel_update_cdclk(dev);
a8f78b58 14657 intel_prepare_ddi(dev);
f817586c 14658 intel_init_clock_gating(dev);
8090c6b9 14659 intel_enable_gt_powersave(dev);
f817586c
DV		 14660}
14661
79e53945
JB		 14662void intel_modeset_init(struct drm_device *dev)
14663{
652c393a 14664 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14665 int sprite, ret;
8cc87b75 14666 enum pipe pipe;
46f297fb 14667 struct intel_crtc *crtc;
79e53945
JB		 14668
14669 drm_mode_config_init(dev);
14670
14671 dev->mode_config.min_width = 0;
14672 dev->mode_config.min_height = 0;
14673
019d96cb
DA		 14674 dev->mode_config.preferred_depth = 24;
14675 dev->mode_config.prefer_shadow = 1;
14676
25bab385
TU		 14677 dev->mode_config.allow_fb_modifiers = true;
14678
e6ecefaa 14679 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14680
b690e96c
JB		 14681 intel_init_quirks(dev);
14682
1fa61106
ED		 14683 intel_init_pm(dev);
14684
e3c74757
BW		 14685 if (INTEL_INFO(dev)->num_pipes == 0)
14686 return;
14687
e70236a8 14688 intel_init_display(dev);
7c10a2b5 14689 intel_init_audio(dev);
e70236a8 14690
a6c45cf0
CW		 14691 if (IS_GEN2(dev)) {
14692 dev->mode_config.max_width = 2048;
14693 dev->mode_config.max_height = 2048;
14694 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14695 dev->mode_config.max_width = 4096;
14696 dev->mode_config.max_height = 4096;
79e53945 14697 } else {
a6c45cf0
CW		 14698 dev->mode_config.max_width = 8192;
14699 dev->mode_config.max_height = 8192;
79e53945 14700 }
068be561 14701
dc41c154
VS		 14702 if (IS_845G(dev) || IS_I865G(dev)) {
14703 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14704 dev->mode_config.cursor_height = 1023;
14705 } else if (IS_GEN2(dev)) {
068be561
DL		 14706 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14707 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14708 } else {
14709 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14710 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14711 }
14712
5d4545ae 14713 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14714
28c97730 14715 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14716 INTEL_INFO(dev)->num_pipes,
14717 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14718
055e393f 14719 for_each_pipe(dev_priv, pipe) {
8cc87b75 14720 intel_crtc_init(dev, pipe);
3bdcfc0c 14721 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14722 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14723 if (ret)
06da8da2 14724 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14725 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14726 }
79e53945
JB		 14727 }
14728
e72f9fbf 14729 intel_shared_dpll_init(dev);
ee7b9f93 14730
9cce37f4
JB		 14731 /* Just disable it once at startup */
14732 i915_disable_vga(dev);
79e53945 14733 intel_setup_outputs(dev);
11be49eb
CW		 14734
14735 /* Just in case the BIOS is doing something questionable. */
7733b49b 14736 intel_fbc_disable(dev_priv);
fa9fa083 14737
6e9f798d 14738 drm_modeset_lock_all(dev);
043e9bda 14739 intel_modeset_setup_hw_state(dev);
6e9f798d 14740 drm_modeset_unlock_all(dev);
46f297fb 14741
d3fcc808 14742 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14743 struct intel_initial_plane_config plane_config = {};
14744
46f297fb
JB		 14745 if (!crtc->active)
14746 continue;
14747
46f297fb 14748 /*
46f297fb
JB		 14749 * Note that reserving the BIOS fb up front prevents us
14750 * from stuffing other stolen allocations like the ring
14751 * on top. This prevents some ugliness at boot time, and
14752 * can even allow for smooth boot transitions if the BIOS
14753 * fb is large enough for the active pipe configuration.
14754 */
eeebeac5
ML		 14755 dev_priv->display.get_initial_plane_config(crtc,
14756 &plane_config);
14757
14758 /*
14759 * If the fb is shared between multiple heads, we'll
14760 * just get the first one.
14761 */
14762 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14763 }
2c7111db
CW		 14764}
14765
7fad798e
DV		 14766static void intel_enable_pipe_a(struct drm_device *dev)
14767{
14768 struct intel_connector *connector;
14769 struct drm_connector *crt = NULL;
14770 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14771 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14772
14773 /* We can't just switch on the pipe A, we need to set things up with a
14774 * proper mode and output configuration. As a gross hack, enable pipe A
14775 * by enabling the load detect pipe once. */
3a3371ff 14776 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14777 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14778 crt = &connector->base;
14779 break;
14780 }
14781 }
14782
14783 if (!crt)
14784 return;
14785
208bf9fd 14786 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14787 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14788}
14789
fa555837
DV		 14790static bool
14791intel_check_plane_mapping(struct intel_crtc *crtc)
14792{
7eb552ae
BW		 14793 struct drm_device *dev = crtc->base.dev;
14794 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14795 u32 reg, val;
14796
7eb552ae 14797 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14798 return true;
14799
14800 reg = DSPCNTR(!crtc->plane);
14801 val = I915_READ(reg);
14802
14803 if ((val & DISPLAY_PLANE_ENABLE) &&
14804 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14805 return false;
14806
14807 return true;
14808}
14809
02e93c35
VS		 14810static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14811{
14812 struct drm_device *dev = crtc->base.dev;
14813 struct intel_encoder *encoder;
14814
14815 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14816 return true;
14817
14818 return false;
14819}
14820
24929352
DV		 14821static void intel_sanitize_crtc(struct intel_crtc *crtc)
14822{
14823 struct drm_device *dev = crtc->base.dev;
14824 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14825 u32 reg;
24929352 14826
24929352 14827 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14828 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14829 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14830
d3eaf884 14831 /* restore vblank interrupts to correct state */
9625604c 14832 drm_crtc_vblank_reset(&crtc->base);
d297e103 14833 if (crtc->active) {
3a03dfb0 14834 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 14835 update_scanline_offset(crtc);
9625604c
DV		 14836 drm_crtc_vblank_on(&crtc->base);
14837 }
d3eaf884 14838
24929352 14839 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14840 * disable the crtc (and hence change the state) if it is wrong. Note
14841 * that gen4+ has a fixed plane -> pipe mapping. */
14842 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14843 bool plane;
14844
24929352
DV		 14845 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14846 crtc->base.base.id);
14847
14848 /* Pipe has the wrong plane attached and the plane is active.
14849 * Temporarily change the plane mapping and disable everything
14850 * ... */
14851 plane = crtc->plane;
b70709a6 14852 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14853 crtc->plane = !plane;
b17d48e2 14854 intel_crtc_disable_noatomic(&crtc->base);
24929352 14855 crtc->plane = plane;
24929352 14856 }
24929352 14857
7fad798e
DV		 14858 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14859 crtc->pipe == PIPE_A && !crtc->active) {
14860 /* BIOS forgot to enable pipe A, this mostly happens after
14861 * resume. Force-enable the pipe to fix this, the update_dpms
14862 * call below we restore the pipe to the right state, but leave
14863 * the required bits on. */
14864 intel_enable_pipe_a(dev);
14865 }
14866
24929352
DV		 14867 /* Adjust the state of the output pipe according to whether we
14868 * have active connectors/encoders. */
02e93c35 14869 if (!intel_crtc_has_encoders(crtc))
b17d48e2 14870 intel_crtc_disable_noatomic(&crtc->base);
24929352 14871
53d9f4e9 14872 if (crtc->active != crtc->base.state->active) {
02e93c35 14873 struct intel_encoder *encoder;
24929352
DV		 14874
14875 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 14876 * functions or because of calls to intel_crtc_disable_noatomic,
14877 * or because the pipe is force-enabled due to the
24929352
DV		 14878 * pipe A quirk. */
14879 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14880 crtc->base.base.id,
83d65738 14881 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14882 crtc->active ? "enabled" : "disabled");
14883
4be40c98 14884 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 14885 crtc->base.state->active = crtc->active;
24929352
DV		 14886 crtc->base.enabled = crtc->active;
14887
14888 /* Because we only establish the connector -> encoder ->
14889 * crtc links if something is active, this means the
14890 * crtc is now deactivated. Break the links. connector
14891 * -> encoder links are only establish when things are
14892 * actually up, hence no need to break them. */
14893 WARN_ON(crtc->active);
14894
2d406bb0 14895 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 14896 encoder->base.crtc = NULL;
24929352 14897 }
c5ab3bc0 14898
a3ed6aad 14899 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14900 /*
14901 * We start out with underrun reporting disabled to avoid races.
14902 * For correct bookkeeping mark this on active crtcs.
14903 *
c5ab3bc0
DV		 14904 * Also on gmch platforms we dont have any hardware bits to
14905 * disable the underrun reporting. Which means we need to start
14906 * out with underrun reporting disabled also on inactive pipes,
14907 * since otherwise we'll complain about the garbage we read when
14908 * e.g. coming up after runtime pm.
14909 *
4cc31489
DV		 14910 * No protection against concurrent access is required - at
14911 * worst a fifo underrun happens which also sets this to false.
14912 */
14913 crtc->cpu_fifo_underrun_disabled = true;
14914 crtc->pch_fifo_underrun_disabled = true;
14915 }
24929352
DV		 14916}
14917
14918static void intel_sanitize_encoder(struct intel_encoder *encoder)
14919{
14920 struct intel_connector *connector;
14921 struct drm_device *dev = encoder->base.dev;
873ffe69 14922 bool active = false;
24929352
DV		 14923
14924 /* We need to check both for a crtc link (meaning that the
14925 * encoder is active and trying to read from a pipe) and the
14926 * pipe itself being active. */
14927 bool has_active_crtc = encoder->base.crtc &&
14928 to_intel_crtc(encoder->base.crtc)->active;
14929
873ffe69
ML		 14930 for_each_intel_connector(dev, connector) {
14931 if (connector->base.encoder != &encoder->base)
14932 continue;
14933
14934 active = true;
14935 break;
14936 }
14937
14938 if (active && !has_active_crtc) {
24929352
DV		 14939 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14940 encoder->base.base.id,
8e329a03 14941 encoder->base.name);
24929352
DV		 14942
14943 /* Connector is active, but has no active pipe. This is
14944 * fallout from our resume register restoring. Disable
14945 * the encoder manually again. */
14946 if (encoder->base.crtc) {
14947 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14948 encoder->base.base.id,
8e329a03 14949 encoder->base.name);
24929352 14950 encoder->disable(encoder);
a62d1497
VS		 14951 if (encoder->post_disable)
14952 encoder->post_disable(encoder);
24929352 14953 }
7f1950fb 14954 encoder->base.crtc = NULL;
24929352
DV		 14955
14956 /* Inconsistent output/port/pipe state happens presumably due to
14957 * a bug in one of the get_hw_state functions. Or someplace else
14958 * in our code, like the register restore mess on resume. Clamp
14959 * things to off as a safer default. */
3a3371ff 14960 for_each_intel_connector(dev, connector) {
24929352
DV		 14961 if (connector->encoder != encoder)
14962 continue;
7f1950fb
EE		 14963 connector->base.dpms = DRM_MODE_DPMS_OFF;
14964 connector->base.encoder = NULL;
24929352
DV		 14965 }
14966 }
14967 /* Enabled encoders without active connectors will be fixed in
14968 * the crtc fixup. */
14969}
14970
04098753 14971void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14972{
14973 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14974 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14975
04098753
ID		 14976 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14977 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14978 i915_disable_vga(dev);
14979 }
14980}
14981
14982void i915_redisable_vga(struct drm_device *dev)
14983{
14984 struct drm_i915_private *dev_priv = dev->dev_private;
14985
8dc8a27c
PZ		 14986 /* This function can be called both from intel_modeset_setup_hw_state or
14987 * at a very early point in our resume sequence, where the power well
14988 * structures are not yet restored. Since this function is at a very
14989 * paranoid "someone might have enabled VGA while we were not looking"
14990 * level, just check if the power well is enabled instead of trying to
14991 * follow the "don't touch the power well if we don't need it" policy
14992 * the rest of the driver uses. */
f458ebbc 14993 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14994 return;
14995
04098753 14996 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14997}
14998
98ec7739
VS		 14999static bool primary_get_hw_state(struct intel_crtc *crtc)
15000{
15001 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15002
d032ffa0
ML		 15003 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15004}
15005
15006static void readout_plane_state(struct intel_crtc *crtc,
15007 struct intel_crtc_state *crtc_state)
15008{
15009 struct intel_plane *p;
4cf0ebbd 15010 struct intel_plane_state *plane_state;
d032ffa0
ML		 15011 bool active = crtc_state->base.active;
15012
d032ffa0 15013 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15014 if (crtc->pipe != p->pipe)
15015 continue;
15016
4cf0ebbd 15017 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15018
4cf0ebbd
ML		 15019 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15020 plane_state->visible = primary_get_hw_state(crtc);
15021 else {
15022 if (active)
15023 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15024
4cf0ebbd 15025 plane_state->visible = false;
d032ffa0
ML		 15026 }
15027 }
98ec7739
VS		 15028}
15029
30e984df 15030static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15031{
15032 struct drm_i915_private *dev_priv = dev->dev_private;
15033 enum pipe pipe;
24929352
DV		 15034 struct intel_crtc *crtc;
15035 struct intel_encoder *encoder;
15036 struct intel_connector *connector;
5358901f 15037 int i;
24929352 15038
d3fcc808 15039 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15040 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15041 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15042 crtc->config->base.crtc = &crtc->base;
3b117c8f 15043
0e8ffe1b 15044 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15045 crtc->config);
24929352 15046
49d6fa21 15047 crtc->base.state->active = crtc->active;
24929352 15048 crtc->base.enabled = crtc->active;
b70709a6 15049
5c1e3426
ML		 15050 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15051 if (crtc->base.state->active) {
15052 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15053 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15054 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15055
15056 /*
15057 * The initial mode needs to be set in order to keep
15058 * the atomic core happy. It wants a valid mode if the
15059 * crtc's enabled, so we do the above call.
15060 *
15061 * At this point some state updated by the connectors
15062 * in their ->detect() callback has not run yet, so
15063 * no recalculation can be done yet.
15064 *
15065 * Even if we could do a recalculation and modeset
15066 * right now it would cause a double modeset if
15067 * fbdev or userspace chooses a different initial mode.
15068 *
5c1e3426
ML		 15069 * If that happens, someone indicated they wanted a
15070 * mode change, which means it's safe to do a full
15071 * recalculation.
15072 */
1ed51de9 15073 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
5c1e3426
ML		 15074 }
15075
15076 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15077 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15078
15079 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15080 crtc->base.base.id,
15081 crtc->active ? "enabled" : "disabled");
15082 }
15083
5358901f
DV		 15084 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15085 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15086
3e369b76
ACO		 15087 pll->on = pll->get_hw_state(dev_priv, pll,
15088 &pll->config.hw_state);
5358901f 15089 pll->active = 0;
3e369b76 15090 pll->config.crtc_mask = 0;
d3fcc808 15091 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15092 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15093 pll->active++;
3e369b76 15094 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15095 }
5358901f 15096 }
5358901f 15097
1e6f2ddc 15098 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15099 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15100
3e369b76 15101 if (pll->config.crtc_mask)
bd2bb1b9 15102 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15103 }
15104
b2784e15 15105 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15106 pipe = 0;
15107
15108 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15109 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15110 encoder->base.crtc = &crtc->base;
6e3c9717 15111 encoder->get_config(encoder, crtc->config);
24929352
DV		 15112 } else {
15113 encoder->base.crtc = NULL;
15114 }
15115
6f2bcceb 15116 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15117 encoder->base.base.id,
8e329a03 15118 encoder->base.name,
24929352 15119 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15120 pipe_name(pipe));
24929352
DV		 15121 }
15122
3a3371ff 15123 for_each_intel_connector(dev, connector) {
24929352
DV		 15124 if (connector->get_hw_state(connector)) {
15125 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15126 connector->base.encoder = &connector->encoder->base;
15127 } else {
15128 connector->base.dpms = DRM_MODE_DPMS_OFF;
15129 connector->base.encoder = NULL;
15130 }
15131 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15132 connector->base.base.id,
c23cc417 15133 connector->base.name,
24929352
DV		 15134 connector->base.encoder ? "enabled" : "disabled");
15135 }
30e984df
DV		 15136}
15137
043e9bda
ML		 15138/* Scan out the current hw modeset state,
15139 * and sanitizes it to the current state
15140 */
15141static void
15142intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15143{
15144 struct drm_i915_private *dev_priv = dev->dev_private;
15145 enum pipe pipe;
30e984df
DV		 15146 struct intel_crtc *crtc;
15147 struct intel_encoder *encoder;
35c95375 15148 int i;
30e984df
DV		 15149
15150 intel_modeset_readout_hw_state(dev);
24929352
DV		 15151
15152 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15153 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15154 intel_sanitize_encoder(encoder);
15155 }
15156
055e393f 15157 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15158 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15159 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15160 intel_dump_pipe_config(crtc, crtc->config,
15161 "[setup_hw_state]");
24929352 15162 }
9a935856 15163
d29b2f9d
ACO		 15164 intel_modeset_update_connector_atomic_state(dev);
15165
35c95375
DV		 15166 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15167 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15168
15169 if (!pll->on || pll->active)
15170 continue;
15171
15172 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15173
15174 pll->disable(dev_priv, pll);
15175 pll->on = false;
15176 }
15177
26e1fe4f 15178 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15179 vlv_wm_get_hw_state(dev);
15180 else if (IS_GEN9(dev))
3078999f
PB		 15181 skl_wm_get_hw_state(dev);
15182 else if (HAS_PCH_SPLIT(dev))
243e6a44 15183 ilk_wm_get_hw_state(dev);
292b990e
ML		 15184
15185 for_each_intel_crtc(dev, crtc) {
15186 unsigned long put_domains;
15187
15188 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15189 if (WARN_ON(put_domains))
15190 modeset_put_power_domains(dev_priv, put_domains);
15191 }
15192 intel_display_set_init_power(dev_priv, false);
043e9bda 15193}
7d0bc1ea 15194
043e9bda
ML		 15195void intel_display_resume(struct drm_device *dev)
15196{
15197 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15198 struct intel_connector *conn;
15199 struct intel_plane *plane;
15200 struct drm_crtc *crtc;
15201 int ret;
f30da187 15202
043e9bda
ML		 15203 if (!state)
15204 return;
15205
15206 state->acquire_ctx = dev->mode_config.acquire_ctx;
15207
15208 /* preserve complete old state, including dpll */
15209 intel_atomic_get_shared_dpll_state(state);
15210
15211 for_each_crtc(dev, crtc) {
15212 struct drm_crtc_state *crtc_state =
15213 drm_atomic_get_crtc_state(state, crtc);
15214
15215 ret = PTR_ERR_OR_ZERO(crtc_state);
15216 if (ret)
15217 goto err;
15218
15219 /* force a restore */
15220 crtc_state->mode_changed = true;
45e2b5f6 15221 }
8af6cf88 15222
043e9bda
ML		 15223 for_each_intel_plane(dev, plane) {
15224 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15225 if (ret)
15226 goto err;
15227 }
15228
15229 for_each_intel_connector(dev, conn) {
15230 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15231 if (ret)
15232 goto err;
15233 }
15234
15235 intel_modeset_setup_hw_state(dev);
15236
15237 i915_redisable_vga(dev);
74c090b1 15238 ret = drm_atomic_commit(state);
043e9bda
ML		 15239 if (!ret)
15240 return;
15241
15242err:
15243 DRM_ERROR("Restoring old state failed with %i\n", ret);
15244 drm_atomic_state_free(state);
2c7111db
CW		 15245}
15246
15247void intel_modeset_gem_init(struct drm_device *dev)
15248{
92122789 15249 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15250 struct drm_crtc *c;
2ff8fde1 15251 struct drm_i915_gem_object *obj;
e0d6149b 15252 int ret;
484b41dd 15253
ae48434c
ID		 15254 mutex_lock(&dev->struct_mutex);
15255 intel_init_gt_powersave(dev);
15256 mutex_unlock(&dev->struct_mutex);
15257
92122789
JB		 15258 /*
15259 * There may be no VBT; and if the BIOS enabled SSC we can
15260 * just keep using it to avoid unnecessary flicker. Whereas if the
15261 * BIOS isn't using it, don't assume it will work even if the VBT
15262 * indicates as much.
15263 */
15264 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15265 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15266 DREF_SSC1_ENABLE);
15267
1833b134 15268 intel_modeset_init_hw(dev);
02e792fb
DV		 15269
15270 intel_setup_overlay(dev);
484b41dd
JB		 15271
15272 /*
15273 * Make sure any fbs we allocated at startup are properly
15274 * pinned & fenced. When we do the allocation it's too early
15275 * for this.
15276 */
70e1e0ec 15277 for_each_crtc(dev, c) {
2ff8fde1
MR		 15278 obj = intel_fb_obj(c->primary->fb);
15279 if (obj == NULL)
484b41dd
JB		 15280 continue;
15281
e0d6149b
TU		 15282 mutex_lock(&dev->struct_mutex);
15283 ret = intel_pin_and_fence_fb_obj(c->primary,
15284 c->primary->fb,
15285 c->primary->state,
91af127f 15286 NULL, NULL);
e0d6149b
TU		 15287 mutex_unlock(&dev->struct_mutex);
15288 if (ret) {
484b41dd
JB		 15289 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15290 to_intel_crtc(c)->pipe);
66e514c1
DA		 15291 drm_framebuffer_unreference(c->primary->fb);
15292 c->primary->fb = NULL;
36750f28 15293 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15294 update_state_fb(c->primary);
36750f28 15295 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15296 }
15297 }
0962c3c9
VS		 15298
15299 intel_backlight_register(dev);
79e53945
JB		 15300}
15301
4932e2c3
ID		 15302void intel_connector_unregister(struct intel_connector *intel_connector)
15303{
15304 struct drm_connector *connector = &intel_connector->base;
15305
15306 intel_panel_destroy_backlight(connector);
34ea3d38 15307 drm_connector_unregister(connector);
4932e2c3
ID		 15308}
15309
79e53945
JB		 15310void intel_modeset_cleanup(struct drm_device *dev)
15311{
652c393a 15312 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15313 struct drm_connector *connector;
652c393a 15314
2eb5252e
ID		 15315 intel_disable_gt_powersave(dev);
15316
0962c3c9
VS		 15317 intel_backlight_unregister(dev);
15318
fd0c0642
DV		 15319 /*
15320 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15321 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15322 * experience fancy races otherwise.
15323 */
2aeb7d3a 15324 intel_irq_uninstall(dev_priv);
eb21b92b 15325
fd0c0642
DV		 15326 /*
15327 * Due to the hpd irq storm handling the hotplug work can re-arm the
15328 * poll handlers. Hence disable polling after hpd handling is shut down.
15329 */
f87ea761 15330 drm_kms_helper_poll_fini(dev);
fd0c0642 15331
723bfd70
JB		 15332 intel_unregister_dsm_handler();
15333
7733b49b 15334 intel_fbc_disable(dev_priv);
69341a5e 15335
1630fe75
CW		 15336 /* flush any delayed tasks or pending work */
15337 flush_scheduled_work();
15338
db31af1d
JN		 15339 /* destroy the backlight and sysfs files before encoders/connectors */
15340 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15341 struct intel_connector *intel_connector;
15342
15343 intel_connector = to_intel_connector(connector);
15344 intel_connector->unregister(intel_connector);
db31af1d 15345 }
d9255d57 15346
79e53945 15347 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15348
15349 intel_cleanup_overlay(dev);
ae48434c
ID		 15350
15351 mutex_lock(&dev->struct_mutex);
15352 intel_cleanup_gt_powersave(dev);
15353 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15354}
15355
f1c79df3
ZW		 15356/*
15357 * Return which encoder is currently attached for connector.
15358 */
df0e9248 15359struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15360{
df0e9248
CW		 15361 return &intel_attached_encoder(connector)->base;
15362}
f1c79df3 15363
df0e9248
CW		 15364void intel_connector_attach_encoder(struct intel_connector *connector,
15365 struct intel_encoder *encoder)
15366{
15367 connector->encoder = encoder;
15368 drm_mode_connector_attach_encoder(&connector->base,
15369 &encoder->base);
79e53945 15370}
28d52043
DA		 15371
15372/*
15373 * set vga decode state - true == enable VGA decode
15374 */
15375int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15376{
15377 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15378 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15379 u16 gmch_ctrl;
15380
75fa041d
CW		 15381 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15382 DRM_ERROR("failed to read control word\n");
15383 return -EIO;
15384 }
15385
c0cc8a55
CW		 15386 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15387 return 0;
15388
28d52043
DA		 15389 if (state)
15390 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15391 else
15392 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15393
15394 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15395 DRM_ERROR("failed to write control word\n");
15396 return -EIO;
15397 }
15398
28d52043
DA		 15399 return 0;
15400}
c4a1d9e4 15401
c4a1d9e4 15402struct intel_display_error_state {
ff57f1b0
PZ		 15403
15404 u32 power_well_driver;
15405
63b66e5b
CW		 15406 int num_transcoders;
15407
c4a1d9e4
CW		 15408 struct intel_cursor_error_state {
15409 u32 control;
15410 u32 position;
15411 u32 base;
15412 u32 size;
52331309 15413 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15414
15415 struct intel_pipe_error_state {
ddf9c536 15416 bool power_domain_on;
c4a1d9e4 15417 u32 source;
f301b1e1 15418 u32 stat;
52331309 15419 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15420
15421 struct intel_plane_error_state {
15422 u32 control;
15423 u32 stride;
15424 u32 size;
15425 u32 pos;
15426 u32 addr;
15427 u32 surface;
15428 u32 tile_offset;
52331309 15429 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15430
15431 struct intel_transcoder_error_state {
ddf9c536 15432 bool power_domain_on;
63b66e5b
CW		 15433 enum transcoder cpu_transcoder;
15434
15435 u32 conf;
15436
15437 u32 htotal;
15438 u32 hblank;
15439 u32 hsync;
15440 u32 vtotal;
15441 u32 vblank;
15442 u32 vsync;
15443 } transcoder[4];
c4a1d9e4
CW		 15444};
15445
15446struct intel_display_error_state *
15447intel_display_capture_error_state(struct drm_device *dev)
15448{
fbee40df 15449 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15450 struct intel_display_error_state *error;
63b66e5b
CW		 15451 int transcoders[] = {
15452 TRANSCODER_A,
15453 TRANSCODER_B,
15454 TRANSCODER_C,
15455 TRANSCODER_EDP,
15456 };
c4a1d9e4
CW		 15457 int i;
15458
63b66e5b
CW		 15459 if (INTEL_INFO(dev)->num_pipes == 0)
15460 return NULL;
15461
9d1cb914 15462 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15463 if (error == NULL)
15464 return NULL;
15465
190be112 15466 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15467 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15468
055e393f 15469 for_each_pipe(dev_priv, i) {
ddf9c536 15470 error->pipe[i].power_domain_on =
f458ebbc
DV		 15471 __intel_display_power_is_enabled(dev_priv,
15472 POWER_DOMAIN_PIPE(i));
ddf9c536 15473 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15474 continue;
15475
5efb3e28
VS		 15476 error->cursor[i].control = I915_READ(CURCNTR(i));
15477 error->cursor[i].position = I915_READ(CURPOS(i));
15478 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15479
15480 error->plane[i].control = I915_READ(DSPCNTR(i));
15481 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15482 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15483 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15484 error->plane[i].pos = I915_READ(DSPPOS(i));
15485 }
ca291363
PZ		 15486 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15487 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15488 if (INTEL_INFO(dev)->gen >= 4) {
15489 error->plane[i].surface = I915_READ(DSPSURF(i));
15490 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15491 }
15492
c4a1d9e4 15493 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15494
3abfce77 15495 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15496 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15497 }
15498
15499 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15500 if (HAS_DDI(dev_priv->dev))
15501 error->num_transcoders++; /* Account for eDP. */
15502
15503 for (i = 0; i < error->num_transcoders; i++) {
15504 enum transcoder cpu_transcoder = transcoders[i];
15505
ddf9c536 15506 error->transcoder[i].power_domain_on =
f458ebbc 15507 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15508 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15509 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15510 continue;
15511
63b66e5b
CW		 15512 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15513
15514 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15515 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15516 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15517 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15518 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15519 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15520 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15521 }
15522
15523 return error;
15524}
15525
edc3d884
MK		 15526#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15527
c4a1d9e4 15528void
edc3d884 15529intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15530 struct drm_device *dev,
15531 struct intel_display_error_state *error)
15532{
055e393f 15533 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15534 int i;
15535
63b66e5b
CW		 15536 if (!error)
15537 return;
15538
edc3d884 15539 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15540 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15541 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15542 error->power_well_driver);
055e393f 15543 for_each_pipe(dev_priv, i) {
edc3d884 15544 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15545 err_printf(m, " Power: %s\n",
15546 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15547 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15548 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15549
15550 err_printf(m, "Plane [%d]:\n", i);
15551 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15552 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15553 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15554 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15555 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15556 }
4b71a570 15557 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15558 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15559 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15560 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15561 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15562 }
15563
edc3d884
MK		 15564 err_printf(m, "Cursor [%d]:\n", i);
15565 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15566 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15567 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15568 }
63b66e5b
CW		 15569
15570 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15571 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15572 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15573 err_printf(m, " Power: %s\n",
15574 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15575 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15576 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15577 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15578 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15579 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15580 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15581 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15582 }
c4a1d9e4 15583}
e2fcdaa9
VS		 15584
15585void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15586{
15587 struct intel_crtc *crtc;
15588
15589 for_each_intel_crtc(dev, crtc) {
15590 struct intel_unpin_work *work;
e2fcdaa9 15591
5e2d7afc 15592 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15593
15594 work = crtc->unpin_work;
15595
15596 if (work && work->event &&
15597 work->event->base.file_priv == file) {
15598 kfree(work->event);
15599 work->event = NULL;
15600 }
15601
5e2d7afc 15602 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15603 }
15604}
Linux kernel - Deliverables
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