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drm/i915: Update DRIVER_DATE to 20150911
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
ea916ea0
KM		 75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
465c120c
MR		 79};
80
3d7d6510
MR		 81/* Cursor formats */
82static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84};
85
6b383a7f 86static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 87
f1f644dc 88static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 89 struct intel_crtc_state *pipe_config);
18442d08 90static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 91 struct intel_crtc_state *pipe_config);
f1f644dc 92
eb1bfe80
JB		 93static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
5b18e57c
DV		 97static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 99static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
29407aab 102static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 103static void haswell_set_pipeconf(struct drm_crtc *crtc);
104static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 105static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
d288f65f 107static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 108 const struct intel_crtc_state *pipe_config);
613d2b27
ML		 109static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
549e2bfb
CK		 111static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
043e9bda 115static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 116
79e53945 117typedef struct {
0206e353 118 int min, max;
79e53945
JB		 119} intel_range_t;
120
121typedef struct {
0206e353
AJ		 122 int dot_limit;
123 int p2_slow, p2_fast;
79e53945
JB		 124} intel_p2_t;
125
d4906093
ML		 126typedef struct intel_limit intel_limit_t;
127struct intel_limit {
0206e353
AJ		 128 intel_range_t dot, vco, n, m, m1, m2, p, p1;
129 intel_p2_t p2;
d4906093 130};
79e53945 131
d2acd215
DV		 132int
133intel_pch_rawclk(struct drm_device *dev)
134{
135 struct drm_i915_private *dev_priv = dev->dev_private;
136
137 WARN_ON(!HAS_PCH_SPLIT(dev));
138
139 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
140}
141
79e50a4f
JN		 142/* hrawclock is 1/4 the FSB frequency */
143int intel_hrawclk(struct drm_device *dev)
144{
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 uint32_t clkcfg;
147
148 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
149 if (IS_VALLEYVIEW(dev))
150 return 200;
151
152 clkcfg = I915_READ(CLKCFG);
153 switch (clkcfg & CLKCFG_FSB_MASK) {
154 case CLKCFG_FSB_400:
155 return 100;
156 case CLKCFG_FSB_533:
157 return 133;
158 case CLKCFG_FSB_667:
159 return 166;
160 case CLKCFG_FSB_800:
161 return 200;
162 case CLKCFG_FSB_1067:
163 return 266;
164 case CLKCFG_FSB_1333:
165 return 333;
166 /* these two are just a guess; one of them might be right */
167 case CLKCFG_FSB_1600:
168 case CLKCFG_FSB_1600_ALT:
169 return 400;
170 default:
171 return 133;
172 }
173}
174
021357ac
CW		 175static inline u32 /* units of 100MHz */
176intel_fdi_link_freq(struct drm_device *dev)
177{
8b99e68c
CW		 178 if (IS_GEN5(dev)) {
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
181 } else
182 return 27;
021357ac
CW		 183}
184
5d536e28 185static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 196};
197
5d536e28
DV		 198static const intel_limit_t intel_limits_i8xx_dvo = {
199 .dot = { .min = 25000, .max = 350000 },
9c333719 200 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 201 .n = { .min = 2, .max = 16 },
5d536e28
DV		 202 .m = { .min = 96, .max = 140 },
203 .m1 = { .min = 18, .max = 26 },
204 .m2 = { .min = 6, .max = 16 },
205 .p = { .min = 4, .max = 128 },
206 .p1 = { .min = 2, .max = 33 },
207 .p2 = { .dot_limit = 165000,
208 .p2_slow = 4, .p2_fast = 4 },
209};
210
e4b36699 211static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 212 .dot = { .min = 25000, .max = 350000 },
9c333719 213 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 214 .n = { .min = 2, .max = 16 },
0206e353
AJ		 215 .m = { .min = 96, .max = 140 },
216 .m1 = { .min = 18, .max = 26 },
217 .m2 = { .min = 6, .max = 16 },
218 .p = { .min = 4, .max = 128 },
219 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 220 .p2 = { .dot_limit = 165000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699 222};
273e27ca 223
e4b36699 224static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 225 .dot = { .min = 20000, .max = 400000 },
226 .vco = { .min = 1400000, .max = 2800000 },
227 .n = { .min = 1, .max = 6 },
228 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 229 .m1 = { .min = 8, .max = 18 },
230 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 231 .p = { .min = 5, .max = 80 },
232 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 233 .p2 = { .dot_limit = 200000,
234 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 238 .dot = { .min = 20000, .max = 400000 },
239 .vco = { .min = 1400000, .max = 2800000 },
240 .n = { .min = 1, .max = 6 },
241 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 242 .m1 = { .min = 8, .max = 18 },
243 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 244 .p = { .min = 7, .max = 98 },
245 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 246 .p2 = { .dot_limit = 112000,
247 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 248};
249
273e27ca 250
e4b36699 251static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 252 .dot = { .min = 25000, .max = 270000 },
253 .vco = { .min = 1750000, .max = 3500000},
254 .n = { .min = 1, .max = 4 },
255 .m = { .min = 104, .max = 138 },
256 .m1 = { .min = 17, .max = 23 },
257 .m2 = { .min = 5, .max = 11 },
258 .p = { .min = 10, .max = 30 },
259 .p1 = { .min = 1, .max = 3},
260 .p2 = { .dot_limit = 270000,
261 .p2_slow = 10,
262 .p2_fast = 10
044c7c41 263 },
e4b36699
KP		 264};
265
266static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 267 .dot = { .min = 22000, .max = 400000 },
268 .vco = { .min = 1750000, .max = 3500000},
269 .n = { .min = 1, .max = 4 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 16, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 5, .max = 80 },
274 .p1 = { .min = 1, .max = 8},
275 .p2 = { .dot_limit = 165000,
276 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 277};
278
279static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 280 .dot = { .min = 20000, .max = 115000 },
281 .vco = { .min = 1750000, .max = 3500000 },
282 .n = { .min = 1, .max = 3 },
283 .m = { .min = 104, .max = 138 },
284 .m1 = { .min = 17, .max = 23 },
285 .m2 = { .min = 5, .max = 11 },
286 .p = { .min = 28, .max = 112 },
287 .p1 = { .min = 2, .max = 8 },
288 .p2 = { .dot_limit = 0,
289 .p2_slow = 14, .p2_fast = 14
044c7c41 290 },
e4b36699
KP		 291};
292
293static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 294 .dot = { .min = 80000, .max = 224000 },
295 .vco = { .min = 1750000, .max = 3500000 },
296 .n = { .min = 1, .max = 3 },
297 .m = { .min = 104, .max = 138 },
298 .m1 = { .min = 17, .max = 23 },
299 .m2 = { .min = 5, .max = 11 },
300 .p = { .min = 14, .max = 42 },
301 .p1 = { .min = 2, .max = 6 },
302 .p2 = { .dot_limit = 0,
303 .p2_slow = 7, .p2_fast = 7
044c7c41 304 },
e4b36699
KP		 305};
306
f2b115e6 307static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 308 .dot = { .min = 20000, .max = 400000},
309 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 310 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 311 .n = { .min = 3, .max = 6 },
312 .m = { .min = 2, .max = 256 },
273e27ca 313 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 314 .m1 = { .min = 0, .max = 0 },
315 .m2 = { .min = 0, .max = 254 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 318 .p2 = { .dot_limit = 200000,
319 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 320};
321
f2b115e6 322static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 323 .dot = { .min = 20000, .max = 400000 },
324 .vco = { .min = 1700000, .max = 3500000 },
325 .n = { .min = 3, .max = 6 },
326 .m = { .min = 2, .max = 256 },
327 .m1 = { .min = 0, .max = 0 },
328 .m2 = { .min = 0, .max = 254 },
329 .p = { .min = 7, .max = 112 },
330 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 331 .p2 = { .dot_limit = 112000,
332 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 333};
334
273e27ca
EA		 335/* Ironlake / Sandybridge
336 *
337 * We calculate clock using (register_value + 2) for N/M1/M2, so here
338 * the range value for them is (actual_value - 2).
339 */
b91ad0ec 340static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 5 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 5, .max = 80 },
348 .p1 = { .min = 1, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 351};
352
b91ad0ec 353static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 118 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
361 .p1 = { .min = 2, .max = 8 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 364};
365
366static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 127 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 56 },
374 .p1 = { .min = 2, .max = 8 },
375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 377};
378
273e27ca 379/* LVDS 100mhz refclk limits. */
b91ad0ec 380static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 381 .dot = { .min = 25000, .max = 350000 },
382 .vco = { .min = 1760000, .max = 3510000 },
383 .n = { .min = 1, .max = 2 },
384 .m = { .min = 79, .max = 126 },
385 .m1 = { .min = 12, .max = 22 },
386 .m2 = { .min = 5, .max = 9 },
387 .p = { .min = 28, .max = 112 },
0206e353 388 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 389 .p2 = { .dot_limit = 225000,
390 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 391};
392
393static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 394 .dot = { .min = 25000, .max = 350000 },
395 .vco = { .min = 1760000, .max = 3510000 },
396 .n = { .min = 1, .max = 3 },
397 .m = { .min = 79, .max = 126 },
398 .m1 = { .min = 12, .max = 22 },
399 .m2 = { .min = 5, .max = 9 },
400 .p = { .min = 14, .max = 42 },
0206e353 401 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 402 .p2 = { .dot_limit = 225000,
403 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 404};
405
dc730512 406static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 407 /*
408 * These are the data rate limits (measured in fast clocks)
409 * since those are the strictest limits we have. The fast
410 * clock and actual rate limits are more relaxed, so checking
411 * them would make no difference.
412 */
413 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 414 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 415 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 416 .m1 = { .min = 2, .max = 3 },
417 .m2 = { .min = 11, .max = 156 },
b99ab663 418 .p1 = { .min = 2, .max = 3 },
5fdc9c49 419 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 420};
421
ef9348c8
CML		 422static const intel_limit_t intel_limits_chv = {
423 /*
424 * These are the data rate limits (measured in fast clocks)
425 * since those are the strictest limits we have. The fast
426 * clock and actual rate limits are more relaxed, so checking
427 * them would make no difference.
428 */
429 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 430 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 431 .n = { .min = 1, .max = 1 },
432 .m1 = { .min = 2, .max = 2 },
433 .m2 = { .min = 24 << 22, .max = 175 << 22 },
434 .p1 = { .min = 2, .max = 4 },
435 .p2 = { .p2_slow = 1, .p2_fast = 14 },
436};
437
5ab7b0b7
ID		 438static const intel_limit_t intel_limits_bxt = {
439 /* FIXME: find real dot limits */
440 .dot = { .min = 0, .max = INT_MAX },
e6292556 441 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 442 .n = { .min = 1, .max = 1 },
443 .m1 = { .min = 2, .max = 2 },
444 /* FIXME: find real m2 limits */
445 .m2 = { .min = 2 << 22, .max = 255 << 22 },
446 .p1 = { .min = 2, .max = 4 },
447 .p2 = { .p2_slow = 1, .p2_fast = 20 },
448};
449
cdba954e
ACO		 450static bool
451needs_modeset(struct drm_crtc_state *state)
452{
fc596660 453 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO		 454}
455
e0638cdf
PZ		 456/**
457 * Returns whether any output on the specified pipe is of the specified type
458 */
4093561b 459bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 460{
409ee761 461 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 462 struct intel_encoder *encoder;
463
409ee761 464 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 465 if (encoder->type == type)
466 return true;
467
468 return false;
469}
470
d0737e1d
ACO		 471/**
472 * Returns whether any output on the specified pipe will have the specified
473 * type after a staged modeset is complete, i.e., the same as
474 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
475 * encoder->crtc.
476 */
a93e255f
ACO		 477static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
478 int type)
d0737e1d 479{
a93e255f 480 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 481 struct drm_connector *connector;
a93e255f 482 struct drm_connector_state *connector_state;
d0737e1d 483 struct intel_encoder *encoder;
a93e255f
ACO		 484 int i, num_connectors = 0;
485
da3ced29 486 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 487 if (connector_state->crtc != crtc_state->base.crtc)
488 continue;
489
490 num_connectors++;
d0737e1d 491
a93e255f
ACO		 492 encoder = to_intel_encoder(connector_state->best_encoder);
493 if (encoder->type == type)
d0737e1d 494 return true;
a93e255f
ACO		 495 }
496
497 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 498
499 return false;
500}
501
a93e255f
ACO		 502static const intel_limit_t *
503intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 504{
a93e255f 505 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 506 const intel_limit_t *limit;
b91ad0ec 507
a93e255f 508 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 509 if (intel_is_dual_link_lvds(dev)) {
1b894b59 510 if (refclk == 100000)
b91ad0ec
ZW		 511 limit = &intel_limits_ironlake_dual_lvds_100m;
512 else
513 limit = &intel_limits_ironlake_dual_lvds;
514 } else {
1b894b59 515 if (refclk == 100000)
b91ad0ec
ZW		 516 limit = &intel_limits_ironlake_single_lvds_100m;
517 else
518 limit = &intel_limits_ironlake_single_lvds;
519 }
c6bb3538 520 } else
b91ad0ec 521 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 530 const intel_limit_t *limit;
531
a93e255f 532 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 533 if (intel_is_dual_link_lvds(dev))
e4b36699 534 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 535 else
e4b36699 536 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 537 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
538 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 539 limit = &intel_limits_g4x_hdmi;
a93e255f 540 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 541 limit = &intel_limits_g4x_sdvo;
044c7c41 542 } else /* The option is for other outputs */
e4b36699 543 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 544
545 return limit;
546}
547
a93e255f
ACO		 548static const intel_limit_t *
549intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 550{
a93e255f 551 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 552 const intel_limit_t *limit;
553
5ab7b0b7
ID		 554 if (IS_BROXTON(dev))
555 limit = &intel_limits_bxt;
556 else if (HAS_PCH_SPLIT(dev))
a93e255f 557 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 558 else if (IS_G4X(dev)) {
a93e255f 559 limit = intel_g4x_limit(crtc_state);
f2b115e6 560 } else if (IS_PINEVIEW(dev)) {
a93e255f 561 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 562 limit = &intel_limits_pineview_lvds;
2177832f 563 else
f2b115e6 564 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 565 } else if (IS_CHERRYVIEW(dev)) {
566 limit = &intel_limits_chv;
a0c4da24 567 } else if (IS_VALLEYVIEW(dev)) {
dc730512 568 limit = &intel_limits_vlv;
a6c45cf0 569 } else if (!IS_GEN2(dev)) {
a93e255f 570 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 571 limit = &intel_limits_i9xx_lvds;
572 else
573 limit = &intel_limits_i9xx_sdvo;
79e53945 574 } else {
a93e255f 575 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 576 limit = &intel_limits_i8xx_lvds;
a93e255f 577 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 578 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 579 else
580 limit = &intel_limits_i8xx_dac;
79e53945
JB		 581 }
582 return limit;
583}
584
dccbea3b
ID		 585/*
586 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
587 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
588 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
589 * The helpers' return value is the rate of the clock that is fed to the
590 * display engine's pipe which can be the above fast dot clock rate or a
591 * divided-down version of it.
592 */
f2b115e6 593/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 594static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 595{
2177832f
SL		 596 clock->m = clock->m2 + 2;
597 clock->p = clock->p1 * clock->p2;
ed5ca77e 598 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 599 return 0;
fb03ac01
VS		 600 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
601 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 602
603 return clock->dot;
2177832f
SL		 604}
605
7429e9d4
DV		 606static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
607{
608 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
609}
610
dccbea3b 611static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 612{
7429e9d4 613 clock->m = i9xx_dpll_compute_m(clock);
79e53945 614 clock->p = clock->p1 * clock->p2;
ed5ca77e 615 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 616 return 0;
fb03ac01
VS		 617 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
618 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 619
620 return clock->dot;
79e53945
JB		 621}
622
dccbea3b 623static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 624{
625 clock->m = clock->m1 * clock->m2;
626 clock->p = clock->p1 * clock->p2;
627 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 628 return 0;
589eca67
ID		 629 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
630 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 631
632 return clock->dot / 5;
589eca67
ID		 633}
634
dccbea3b 635int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 636{
637 clock->m = clock->m1 * clock->m2;
638 clock->p = clock->p1 * clock->p2;
639 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 640 return 0;
ef9348c8
CML		 641 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
642 clock->n << 22);
643 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 644
645 return clock->dot / 5;
ef9348c8
CML		 646}
647
7c04d1d9 648#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 649/**
650 * Returns whether the given set of divisors are valid for a given refclk with
651 * the given connectors.
652 */
653
1b894b59
CW		 654static bool intel_PLL_is_valid(struct drm_device *dev,
655 const intel_limit_t *limit,
656 const intel_clock_t *clock)
79e53945 657{
f01b7962
VS		 658 if (clock->n < limit->n.min || limit->n.max < clock->n)
659 INTELPllInvalid("n out of range\n");
79e53945 660 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 661 INTELPllInvalid("p1 out of range\n");
79e53945 662 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 663 INTELPllInvalid("m2 out of range\n");
79e53945 664 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 665 INTELPllInvalid("m1 out of range\n");
f01b7962 666
5ab7b0b7 667 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 668 if (clock->m1 <= clock->m2)
669 INTELPllInvalid("m1 <= m2\n");
670
5ab7b0b7 671 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 672 if (clock->p < limit->p.min || limit->p.max < clock->p)
673 INTELPllInvalid("p out of range\n");
674 if (clock->m < limit->m.min || limit->m.max < clock->m)
675 INTELPllInvalid("m out of range\n");
676 }
677
79e53945 678 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 679 INTELPllInvalid("vco out of range\n");
79e53945
JB		 680 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
681 * connector, etc., rather than just a single range.
682 */
683 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 684 INTELPllInvalid("dot out of range\n");
79e53945
JB		 685
686 return true;
687}
688
3b1429d9
VS		 689static int
690i9xx_select_p2_div(const intel_limit_t *limit,
691 const struct intel_crtc_state *crtc_state,
692 int target)
79e53945 693{
3b1429d9 694 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 695
a93e255f 696 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 697 /*
a210b028
DV		 698 * For LVDS just rely on its current settings for dual-channel.
699 * We haven't figured out how to reliably set up different
700 * single/dual channel state, if we even can.
79e53945 701 */
1974cad0 702 if (intel_is_dual_link_lvds(dev))
3b1429d9 703 return limit->p2.p2_fast;
79e53945 704 else
3b1429d9 705 return limit->p2.p2_slow;
79e53945
JB		 706 } else {
707 if (target < limit->p2.dot_limit)
3b1429d9 708 return limit->p2.p2_slow;
79e53945 709 else
3b1429d9 710 return limit->p2.p2_fast;
79e53945 711 }
3b1429d9
VS		 712}
713
714static bool
715i9xx_find_best_dpll(const intel_limit_t *limit,
716 struct intel_crtc_state *crtc_state,
717 int target, int refclk, intel_clock_t *match_clock,
718 intel_clock_t *best_clock)
719{
720 struct drm_device *dev = crtc_state->base.crtc->dev;
721 intel_clock_t clock;
722 int err = target;
79e53945 723
0206e353 724 memset(best_clock, 0, sizeof(*best_clock));
79e53945 725
3b1429d9
VS		 726 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
727
42158660
ZY		 728 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
729 clock.m1++) {
730 for (clock.m2 = limit->m2.min;
731 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 732 if (clock.m2 >= clock.m1)
42158660
ZY		 733 break;
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 738 int this_err;
739
dccbea3b 740 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759}
760
761static bool
a93e255f
ACO		 762pnv_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
79e53945 766{
3b1429d9 767 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 768 intel_clock_t clock;
79e53945
JB		 769 int err = target;
770
0206e353 771 memset(best_clock, 0, sizeof(*best_clock));
79e53945 772
3b1429d9
VS		 773 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
774
42158660
ZY		 775 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
776 clock.m1++) {
777 for (clock.m2 = limit->m2.min;
778 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 779 for (clock.n = limit->n.min;
780 clock.n <= limit->n.max; clock.n++) {
781 for (clock.p1 = limit->p1.min;
782 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 783 int this_err;
784
dccbea3b 785 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 786 if (!intel_PLL_is_valid(dev, limit,
787 &clock))
79e53945 788 continue;
cec2f356
SP		 789 if (match_clock &&
790 clock.p != match_clock->p)
791 continue;
79e53945
JB		 792
793 this_err = abs(clock.dot - target);
794 if (this_err < err) {
795 *best_clock = clock;
796 err = this_err;
797 }
798 }
799 }
800 }
801 }
802
803 return (err != target);
804}
805
d4906093 806static bool
a93e255f
ACO		 807g4x_find_best_dpll(const intel_limit_t *limit,
808 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
d4906093 811{
3b1429d9 812 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 813 intel_clock_t clock;
814 int max_n;
3b1429d9 815 bool found = false;
6ba770dc
AJ		 816 /* approximately equals target * 0.00585 */
817 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 818
819 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 820
821 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
822
d4906093 823 max_n = limit->n.max;
f77f13e2 824 /* based on hardware requirement, prefer smaller n to precision */
d4906093 825 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 826 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 827 for (clock.m1 = limit->m1.max;
828 clock.m1 >= limit->m1.min; clock.m1--) {
829 for (clock.m2 = limit->m2.max;
830 clock.m2 >= limit->m2.min; clock.m2--) {
831 for (clock.p1 = limit->p1.max;
832 clock.p1 >= limit->p1.min; clock.p1--) {
833 int this_err;
834
dccbea3b 835 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
d4906093 838 continue;
1b894b59
CW		 839
840 this_err = abs(clock.dot - target);
d4906093
ML		 841 if (this_err < err_most) {
842 *best_clock = clock;
843 err_most = this_err;
844 max_n = clock.n;
845 found = true;
846 }
847 }
848 }
849 }
850 }
2c07245f
ZW		 851 return found;
852}
853
d5dd62bd
ID		 854/*
855 * Check if the calculated PLL configuration is more optimal compared to the
856 * best configuration and error found so far. Return the calculated error.
857 */
858static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
859 const intel_clock_t *calculated_clock,
860 const intel_clock_t *best_clock,
861 unsigned int best_error_ppm,
862 unsigned int *error_ppm)
863{
9ca3ba01
ID		 864 /*
865 * For CHV ignore the error and consider only the P value.
866 * Prefer a bigger P value based on HW requirements.
867 */
868 if (IS_CHERRYVIEW(dev)) {
869 *error_ppm = 0;
870
871 return calculated_clock->p > best_clock->p;
872 }
873
24be4e46
ID		 874 if (WARN_ON_ONCE(!target_freq))
875 return false;
876
d5dd62bd
ID		 877 *error_ppm = div_u64(1000000ULL *
878 abs(target_freq - calculated_clock->dot),
879 target_freq);
880 /*
881 * Prefer a better P value over a better (smaller) error if the error
882 * is small. Ensure this preference for future configurations too by
883 * setting the error to 0.
884 */
885 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
886 *error_ppm = 0;
887
888 return true;
889 }
890
891 return *error_ppm + 10 < best_error_ppm;
892}
893
a0c4da24 894static bool
a93e255f
ACO		 895vlv_find_best_dpll(const intel_limit_t *limit,
896 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 897 int target, int refclk, intel_clock_t *match_clock,
898 intel_clock_t *best_clock)
a0c4da24 899{
a93e255f 900 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 901 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 902 intel_clock_t clock;
69e4f900 903 unsigned int bestppm = 1000000;
27e639bf
VS		 904 /* min update 19.2 MHz */
905 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 906 bool found = false;
a0c4da24 907
6b4bf1c4
VS		 908 target *= 5; /* fast clock */
909
910 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 911
912 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 913 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 914 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 915 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 916 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 917 clock.p = clock.p1 * clock.p2;
a0c4da24 918 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 919 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 920 unsigned int ppm;
69e4f900 921
6b4bf1c4
VS		 922 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
923 refclk * clock.m1);
924
dccbea3b 925 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 926
f01b7962
VS		 927 if (!intel_PLL_is_valid(dev, limit,
928 &clock))
43b0ac53
VS		 929 continue;
930
d5dd62bd
ID		 931 if (!vlv_PLL_is_optimal(dev, target,
932 &clock,
933 best_clock,
934 bestppm, &ppm))
935 continue;
6b4bf1c4 936
d5dd62bd
ID		 937 *best_clock = clock;
938 bestppm = ppm;
939 found = true;
a0c4da24
JB		 940 }
941 }
942 }
943 }
a0c4da24 944
49e497ef 945 return found;
a0c4da24 946}
a4fc5ed6 947
ef9348c8 948static bool
a93e255f
ACO		 949chv_find_best_dpll(const intel_limit_t *limit,
950 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 951 int target, int refclk, intel_clock_t *match_clock,
952 intel_clock_t *best_clock)
953{
a93e255f 954 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 955 struct drm_device *dev = crtc->base.dev;
9ca3ba01 956 unsigned int best_error_ppm;
ef9348c8
CML		 957 intel_clock_t clock;
958 uint64_t m2;
959 int found = false;
960
961 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 962 best_error_ppm = 1000000;
ef9348c8
CML		 963
964 /*
965 * Based on hardware doc, the n always set to 1, and m1 always
966 * set to 2. If requires to support 200Mhz refclk, we need to
967 * revisit this because n may not 1 anymore.
968 */
969 clock.n = 1, clock.m1 = 2;
970 target *= 5; /* fast clock */
971
972 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
973 for (clock.p2 = limit->p2.p2_fast;
974 clock.p2 >= limit->p2.p2_slow;
975 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 976 unsigned int error_ppm;
ef9348c8
CML		 977
978 clock.p = clock.p1 * clock.p2;
979
980 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
981 clock.n) << 22, refclk * clock.m1);
982
983 if (m2 > INT_MAX/clock.m1)
984 continue;
985
986 clock.m2 = m2;
987
dccbea3b 988 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 989
990 if (!intel_PLL_is_valid(dev, limit, &clock))
991 continue;
992
9ca3ba01
ID		 993 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
994 best_error_ppm, &error_ppm))
995 continue;
996
997 *best_clock = clock;
998 best_error_ppm = error_ppm;
999 found = true;
ef9348c8
CML		 1000 }
1001 }
1002
1003 return found;
1004}
1005
5ab7b0b7
ID		 1006bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1007 intel_clock_t *best_clock)
1008{
1009 int refclk = i9xx_get_refclk(crtc_state, 0);
1010
1011 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1012 target_clock, refclk, NULL, best_clock);
1013}
1014
20ddf665
VS		 1015bool intel_crtc_active(struct drm_crtc *crtc)
1016{
1017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1018
1019 /* Be paranoid as we can arrive here with only partial
1020 * state retrieved from the hardware during setup.
1021 *
241bfc38 1022 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 1023 * as Haswell has gained clock readout/fastboot support.
1024 *
66e514c1 1025 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1026 * properly reconstruct framebuffers.
c3d1f436
MR		 1027 *
1028 * FIXME: The intel_crtc->active here should be switched to
1029 * crtc->state->active once we have proper CRTC states wired up
1030 * for atomic.
20ddf665 1031 */
c3d1f436 1032 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1033 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1034}
1035
a5c961d1
PZ		 1036enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1037 enum pipe pipe)
1038{
1039 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1041
6e3c9717 1042 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1043}
1044
fbf49ea2
VS		 1045static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1046{
1047 struct drm_i915_private *dev_priv = dev->dev_private;
1048 u32 reg = PIPEDSL(pipe);
1049 u32 line1, line2;
1050 u32 line_mask;
1051
1052 if (IS_GEN2(dev))
1053 line_mask = DSL_LINEMASK_GEN2;
1054 else
1055 line_mask = DSL_LINEMASK_GEN3;
1056
1057 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1058 msleep(5);
fbf49ea2
VS		 1059 line2 = I915_READ(reg) & line_mask;
1060
1061 return line1 == line2;
1062}
1063
ab7ad7f6
KP		 1064/*
1065 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1066 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1067 *
1068 * After disabling a pipe, we can't wait for vblank in the usual way,
1069 * spinning on the vblank interrupt status bit, since we won't actually
1070 * see an interrupt when the pipe is disabled.
1071 *
ab7ad7f6
KP		 1072 * On Gen4 and above:
1073 * wait for the pipe register state bit to turn off
1074 *
1075 * Otherwise:
1076 * wait for the display line value to settle (it usually
1077 * ends up stopping at the start of the next frame).
58e10eb9 1078 *
9d0498a2 1079 */
575f7ab7 1080static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1081{
575f7ab7 1082 struct drm_device *dev = crtc->base.dev;
9d0498a2 1083 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1084 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1085 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1086
1087 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1088 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1089
1090 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1091 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1092 100))
284637d9 1093 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1094 } else {
ab7ad7f6 1095 /* Wait for the display line to settle */
fbf49ea2 1096 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1097 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1098 }
79e53945
JB		 1099}
1100
b24e7179
JB		 1101static const char *state_string(bool enabled)
1102{
1103 return enabled ? "on" : "off";
1104}
1105
1106/* Only for pre-ILK configs */
55607e8a
DV		 1107void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
b24e7179
JB		 1109{
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = DPLL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1117 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1118 "PLL state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
b24e7179 1121
23538ef1
JN		 1122/* XXX: the dsi pll is shared between MIPI DSI ports */
1123static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124{
1125 u32 val;
1126 bool cur_state;
1127
a580516d 1128 mutex_lock(&dev_priv->sb_lock);
23538ef1 1129 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1130 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1131
1132 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1133 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1134 "DSI PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136}
1137#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1139
55607e8a 1140struct intel_shared_dpll *
e2b78267
DV		 1141intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1142{
1143 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1144
6e3c9717 1145 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1146 return NULL;
1147
6e3c9717 1148 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1149}
1150
040484af 1151/* For ILK+ */
55607e8a
DV		 1152void assert_shared_dpll(struct drm_i915_private *dev_priv,
1153 struct intel_shared_dpll *pll,
1154 bool state)
040484af 1155{
040484af 1156 bool cur_state;
5358901f 1157 struct intel_dpll_hw_state hw_state;
040484af 1158
92b27b08 1159 if (WARN (!pll,
46edb027 1160 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1161 return;
ee7b9f93 1162
5358901f 1163 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1164 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1165 "%s assertion failure (expected %s, current %s)\n",
1166 pll->name, state_string(state), state_string(cur_state));
040484af 1167}
040484af
JB		 1168
1169static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171{
1172 int reg;
1173 u32 val;
1174 bool cur_state;
ad80a810
PZ		 1175 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1176 pipe);
040484af 1177
affa9354
PZ		 1178 if (HAS_DDI(dev_priv->dev)) {
1179 /* DDI does not have a specific FDI_TX register */
ad80a810 1180 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1181 val = I915_READ(reg);
ad80a810 1182 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1183 } else {
1184 reg = FDI_TX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_TX_ENABLE);
1187 }
e2c719b7 1188 I915_STATE_WARN(cur_state != state,
040484af
JB		 1189 "FDI TX state assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191}
1192#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1194
1195static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197{
1198 int reg;
1199 u32 val;
1200 bool cur_state;
1201
d63fa0dc
PZ		 1202 reg = FDI_RX_CTL(pipe);
1203 val = I915_READ(reg);
1204 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1205 I915_STATE_WARN(cur_state != state,
040484af
JB		 1206 "FDI RX state assertion failure (expected %s, current %s)\n",
1207 state_string(state), state_string(cur_state));
1208}
1209#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1211
1212static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1213 enum pipe pipe)
1214{
1215 int reg;
1216 u32 val;
1217
1218 /* ILK FDI PLL is always enabled */
3d13ef2e 1219 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1220 return;
1221
bf507ef7 1222 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1223 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1224 return;
1225
040484af
JB		 1226 reg = FDI_TX_CTL(pipe);
1227 val = I915_READ(reg);
e2c719b7 1228 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1229}
1230
55607e8a
DV		 1231void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
040484af
JB		 1233{
1234 int reg;
1235 u32 val;
55607e8a 1236 bool cur_state;
040484af
JB		 1237
1238 reg = FDI_RX_CTL(pipe);
1239 val = I915_READ(reg);
55607e8a 1240 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1241 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1242 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243 state_string(state), state_string(cur_state));
040484af
JB		 1244}
1245
b680c37a
DV		 1246void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
ea0760cf 1248{
bedd4dba
JN		 1249 struct drm_device *dev = dev_priv->dev;
1250 int pp_reg;
ea0760cf
JB		 1251 u32 val;
1252 enum pipe panel_pipe = PIPE_A;
0de3b485 1253 bool locked = true;
ea0760cf 1254
bedd4dba
JN		 1255 if (WARN_ON(HAS_DDI(dev)))
1256 return;
1257
1258 if (HAS_PCH_SPLIT(dev)) {
1259 u32 port_sel;
1260
ea0760cf 1261 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1262 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1263
1264 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1265 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1266 panel_pipe = PIPE_B;
1267 /* XXX: else fix for eDP */
1268 } else if (IS_VALLEYVIEW(dev)) {
1269 /* presumably write lock depends on pipe, not port select */
1270 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1271 panel_pipe = pipe;
ea0760cf
JB		 1272 } else {
1273 pp_reg = PP_CONTROL;
bedd4dba
JN		 1274 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1275 panel_pipe = PIPE_B;
ea0760cf
JB		 1276 }
1277
1278 val = I915_READ(pp_reg);
1279 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1280 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1281 locked = false;
1282
e2c719b7 1283 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1284 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1285 pipe_name(pipe));
ea0760cf
JB		 1286}
1287
93ce0ba6
JN		 1288static void assert_cursor(struct drm_i915_private *dev_priv,
1289 enum pipe pipe, bool state)
1290{
1291 struct drm_device *dev = dev_priv->dev;
1292 bool cur_state;
1293
d9d82081 1294 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1295 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1296 else
5efb3e28 1297 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1298
e2c719b7 1299 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1300 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301 pipe_name(pipe), state_string(state), state_string(cur_state));
1302}
1303#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1305
b840d907
JB		 1306void assert_pipe(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, bool state)
b24e7179
JB		 1308{
1309 int reg;
1310 u32 val;
63d7bbe9 1311 bool cur_state;
702e7a56
PZ		 1312 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1313 pipe);
b24e7179 1314
b6b5d049
VS		 1315 /* if we need the pipe quirk it must be always on */
1316 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1317 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1318 state = true;
1319
f458ebbc 1320 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1321 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1322 cur_state = false;
1323 } else {
1324 reg = PIPECONF(cpu_transcoder);
1325 val = I915_READ(reg);
1326 cur_state = !!(val & PIPECONF_ENABLE);
1327 }
1328
e2c719b7 1329 I915_STATE_WARN(cur_state != state,
63d7bbe9 1330 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1331 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1332}
1333
931872fc
CW		 1334static void assert_plane(struct drm_i915_private *dev_priv,
1335 enum plane plane, bool state)
b24e7179
JB		 1336{
1337 int reg;
1338 u32 val;
931872fc 1339 bool cur_state;
b24e7179
JB		 1340
1341 reg = DSPCNTR(plane);
1342 val = I915_READ(reg);
931872fc 1343 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1345 "plane %c assertion failure (expected %s, current %s)\n",
1346 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1351
b24e7179
JB		 1352static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1353 enum pipe pipe)
1354{
653e1026 1355 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1356 int reg, i;
1357 u32 val;
1358 int cur_pipe;
1359
653e1026
VS		 1360 /* Primary planes are fixed to pipes on gen4+ */
1361 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1362 reg = DSPCNTR(pipe);
1363 val = I915_READ(reg);
e2c719b7 1364 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1365 "plane %c assertion failure, should be disabled but not\n",
1366 plane_name(pipe));
19ec1358 1367 return;
28c05794 1368 }
19ec1358 1369
b24e7179 1370 /* Need to check both planes against the pipe */
055e393f 1371 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1372 reg = DSPCNTR(i);
1373 val = I915_READ(reg);
1374 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1375 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1376 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1377 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1379 }
1380}
1381
19332d7a
JB		 1382static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1383 enum pipe pipe)
1384{
20674eef 1385 struct drm_device *dev = dev_priv->dev;
1fe47785 1386 int reg, sprite;
19332d7a
JB		 1387 u32 val;
1388
7feb8b88 1389 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1390 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1391 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1392 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1393 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394 sprite, pipe_name(pipe));
1395 }
1396 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1397 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1398 reg = SPCNTR(pipe, sprite);
20674eef 1399 val = I915_READ(reg);
e2c719b7 1400 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1401 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1402 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1403 }
1404 } else if (INTEL_INFO(dev)->gen >= 7) {
1405 reg = SPRCTL(pipe);
19332d7a 1406 val = I915_READ(reg);
e2c719b7 1407 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1408 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1409 plane_name(pipe), pipe_name(pipe));
1410 } else if (INTEL_INFO(dev)->gen >= 5) {
1411 reg = DVSCNTR(pipe);
19332d7a 1412 val = I915_READ(reg);
e2c719b7 1413 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1415 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1416 }
1417}
1418
08c71e5e
VS		 1419static void assert_vblank_disabled(struct drm_crtc *crtc)
1420{
e2c719b7 1421 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1422 drm_crtc_vblank_put(crtc);
1423}
1424
89eff4be 1425static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1426{
1427 u32 val;
1428 bool enabled;
1429
e2c719b7 1430 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1431
92f2584a
JB		 1432 val = I915_READ(PCH_DREF_CONTROL);
1433 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1434 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1435 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1436}
1437
ab9412ba
DV		 1438static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe)
92f2584a
JB		 1440{
1441 int reg;
1442 u32 val;
1443 bool enabled;
1444
ab9412ba 1445 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1446 val = I915_READ(reg);
1447 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1448 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1449 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1450 pipe_name(pipe));
92f2584a
JB		 1451}
1452
4e634389
KP		 1453static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1455{
1456 if ((val & DP_PORT_EN) == 0)
1457 return false;
1458
1459 if (HAS_PCH_CPT(dev_priv->dev)) {
1460 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1461 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1462 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1463 return false;
44f37d1f
CML		 1464 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1465 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1466 return false;
f0575e92
KP		 1467 } else {
1468 if ((val & DP_PIPE_MASK) != (pipe << 30))
1469 return false;
1470 }
1471 return true;
1472}
1473
1519b995
KP		 1474static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, u32 val)
1476{
dc0fa718 1477 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1478 return false;
1479
1480 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1481 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1482 return false;
44f37d1f
CML		 1483 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1484 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1485 return false;
1519b995 1486 } else {
dc0fa718 1487 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1488 return false;
1489 }
1490 return true;
1491}
1492
1493static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1494 enum pipe pipe, u32 val)
1495{
1496 if ((val & LVDS_PORT_EN) == 0)
1497 return false;
1498
1499 if (HAS_PCH_CPT(dev_priv->dev)) {
1500 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1501 return false;
1502 } else {
1503 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1504 return false;
1505 }
1506 return true;
1507}
1508
1509static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511{
1512 if ((val & ADPA_DAC_ENABLE) == 0)
1513 return false;
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
291906f1 1524static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1525 enum pipe pipe, int reg, u32 port_sel)
291906f1 1526{
47a05eca 1527 u32 val = I915_READ(reg);
e2c719b7 1528 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1529 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1530 reg, pipe_name(pipe));
de9a35ab 1531
e2c719b7 1532 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1533 && (val & DP_PIPEB_SELECT),
de9a35ab 1534 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1535}
1536
1537static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1538 enum pipe pipe, int reg)
1539{
47a05eca 1540 u32 val = I915_READ(reg);
e2c719b7 1541 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1542 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1543 reg, pipe_name(pipe));
de9a35ab 1544
e2c719b7 1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1546 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1547 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1548}
1549
1550static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe)
1552{
1553 int reg;
1554 u32 val;
291906f1 1555
f0575e92
KP		 1556 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1557 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1558 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1559
1560 reg = PCH_ADPA;
1561 val = I915_READ(reg);
e2c719b7 1562 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1563 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1564 pipe_name(pipe));
291906f1
JB		 1565
1566 reg = PCH_LVDS;
1567 val = I915_READ(reg);
e2c719b7 1568 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1569 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1570 pipe_name(pipe));
291906f1 1571
e2debe91
PZ		 1572 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1573 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1574 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1575}
1576
d288f65f 1577static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1578 const struct intel_crtc_state *pipe_config)
87442f73 1579{
426115cf
DV		 1580 struct drm_device *dev = crtc->base.dev;
1581 struct drm_i915_private *dev_priv = dev->dev_private;
1582 int reg = DPLL(crtc->pipe);
d288f65f 1583 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1584
426115cf 1585 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1586
1587 /* No really, not for ILK+ */
1588 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1589
1590 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1591 if (IS_MOBILE(dev_priv->dev))
426115cf 1592 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1593
426115cf
DV		 1594 I915_WRITE(reg, dpll);
1595 POSTING_READ(reg);
1596 udelay(150);
1597
1598 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1599 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1600
d288f65f 1601 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1602 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1603
1604 /* We do this three times for luck */
426115cf 1605 I915_WRITE(reg, dpll);
87442f73
DV		 1606 POSTING_READ(reg);
1607 udelay(150); /* wait for warmup */
426115cf 1608 I915_WRITE(reg, dpll);
87442f73
DV		 1609 POSTING_READ(reg);
1610 udelay(150); /* wait for warmup */
426115cf 1611 I915_WRITE(reg, dpll);
87442f73
DV		 1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
1614}
1615
d288f65f 1616static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1617 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1618{
1619 struct drm_device *dev = crtc->base.dev;
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 int pipe = crtc->pipe;
1622 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1623 u32 tmp;
1624
1625 assert_pipe_disabled(dev_priv, crtc->pipe);
1626
1627 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1628
a580516d 1629 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1630
1631 /* Enable back the 10bit clock to display controller */
1632 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1633 tmp |= DPIO_DCLKP_EN;
1634 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1635
54433e91
VS		 1636 mutex_unlock(&dev_priv->sb_lock);
1637
9d556c99
CML		 1638 /*
1639 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1640 */
1641 udelay(1);
1642
1643 /* Enable PLL */
d288f65f 1644 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1645
1646 /* Check PLL is locked */
a11b0703 1647 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1648 DRM_ERROR("PLL %d failed to lock\n", pipe);
1649
a11b0703 1650 /* not sure when this should be written */
d288f65f 1651 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1652 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1653}
1654
1c4e0274
VS		 1655static int intel_num_dvo_pipes(struct drm_device *dev)
1656{
1657 struct intel_crtc *crtc;
1658 int count = 0;
1659
1660 for_each_intel_crtc(dev, crtc)
3538b9df 1661 count += crtc->base.state->active &&
409ee761 1662 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1663
1664 return count;
1665}
1666
66e3d5c0 1667static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1668{
66e3d5c0
DV		 1669 struct drm_device *dev = crtc->base.dev;
1670 struct drm_i915_private *dev_priv = dev->dev_private;
1671 int reg = DPLL(crtc->pipe);
6e3c9717 1672 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1673
66e3d5c0 1674 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1675
63d7bbe9 1676 /* No really, not for ILK+ */
3d13ef2e 1677 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1678
1679 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1680 if (IS_MOBILE(dev) && !IS_I830(dev))
1681 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1682
1c4e0274
VS		 1683 /* Enable DVO 2x clock on both PLLs if necessary */
1684 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1685 /*
1686 * It appears to be important that we don't enable this
1687 * for the current pipe before otherwise configuring the
1688 * PLL. No idea how this should be handled if multiple
1689 * DVO outputs are enabled simultaneosly.
1690 */
1691 dpll |= DPLL_DVO_2X_MODE;
1692 I915_WRITE(DPLL(!crtc->pipe),
1693 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1694 }
66e3d5c0
DV		 1695
1696 /* Wait for the clocks to stabilize. */
1697 POSTING_READ(reg);
1698 udelay(150);
1699
1700 if (INTEL_INFO(dev)->gen >= 4) {
1701 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1702 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1703 } else {
1704 /* The pixel multiplier can only be updated once the
1705 * DPLL is enabled and the clocks are stable.
1706 *
1707 * So write it again.
1708 */
1709 I915_WRITE(reg, dpll);
1710 }
63d7bbe9
JB		 1711
1712 /* We do this three times for luck */
66e3d5c0 1713 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1714 POSTING_READ(reg);
1715 udelay(150); /* wait for warmup */
66e3d5c0 1716 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1717 POSTING_READ(reg);
1718 udelay(150); /* wait for warmup */
66e3d5c0 1719 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
1722}
1723
1724/**
50b44a44 1725 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1726 * @dev_priv: i915 private structure
1727 * @pipe: pipe PLL to disable
1728 *
1729 * Disable the PLL for @pipe, making sure the pipe is off first.
1730 *
1731 * Note! This is for pre-ILK only.
1732 */
1c4e0274 1733static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1734{
1c4e0274
VS		 1735 struct drm_device *dev = crtc->base.dev;
1736 struct drm_i915_private *dev_priv = dev->dev_private;
1737 enum pipe pipe = crtc->pipe;
1738
1739 /* Disable DVO 2x clock on both PLLs if necessary */
1740 if (IS_I830(dev) &&
409ee761 1741 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1742 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1743 I915_WRITE(DPLL(PIPE_B),
1744 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1745 I915_WRITE(DPLL(PIPE_A),
1746 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1747 }
1748
b6b5d049
VS		 1749 /* Don't disable pipe or pipe PLLs if needed */
1750 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1751 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1752 return;
1753
1754 /* Make sure the pipe isn't still relying on us */
1755 assert_pipe_disabled(dev_priv, pipe);
1756
b8afb911 1757 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1758 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1759}
1760
f6071166
JB		 1761static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1762{
b8afb911 1763 u32 val;
f6071166
JB		 1764
1765 /* Make sure the pipe isn't still relying on us */
1766 assert_pipe_disabled(dev_priv, pipe);
1767
e5cbfbfb
ID		 1768 /*
1769 * Leave integrated clock source and reference clock enabled for pipe B.
1770 * The latter is needed for VGA hotplug / manual detection.
1771 */
b8afb911 1772 val = DPLL_VGA_MODE_DIS;
f6071166 1773 if (pipe == PIPE_B)
60bfe44f 1774 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1775 I915_WRITE(DPLL(pipe), val);
1776 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1777
1778}
1779
1780static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1781{
d752048d 1782 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1783 u32 val;
1784
a11b0703
VS		 1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1787
a11b0703 1788 /* Set PLL en = 0 */
60bfe44f
VS		 1789 val = DPLL_SSC_REF_CLK_CHV |
1790 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1791 if (pipe != PIPE_A)
1792 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1793 I915_WRITE(DPLL(pipe), val);
1794 POSTING_READ(DPLL(pipe));
d752048d 1795
a580516d 1796 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1797
1798 /* Disable 10bit clock to display controller */
1799 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1800 val &= ~DPIO_DCLKP_EN;
1801 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1802
a580516d 1803 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1804}
1805
e4607fcf 1806void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1807 struct intel_digital_port *dport,
1808 unsigned int expected_mask)
89b667f8
JB		 1809{
1810 u32 port_mask;
00fc31b7 1811 int dpll_reg;
89b667f8 1812
e4607fcf
CML		 1813 switch (dport->port) {
1814 case PORT_B:
89b667f8 1815 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1816 dpll_reg = DPLL(0);
e4607fcf
CML		 1817 break;
1818 case PORT_C:
89b667f8 1819 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1820 dpll_reg = DPLL(0);
9b6de0a1 1821 expected_mask <<= 4;
00fc31b7
CML		 1822 break;
1823 case PORT_D:
1824 port_mask = DPLL_PORTD_READY_MASK;
1825 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1826 break;
1827 default:
1828 BUG();
1829 }
89b667f8 1830
9b6de0a1
VS		 1831 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1832 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1833 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1834}
1835
b14b1055
DV		 1836static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1837{
1838 struct drm_device *dev = crtc->base.dev;
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1841
be19f0ff
CW		 1842 if (WARN_ON(pll == NULL))
1843 return;
1844
3e369b76 1845 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1846 if (pll->active == 0) {
1847 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1848 WARN_ON(pll->on);
1849 assert_shared_dpll_disabled(dev_priv, pll);
1850
1851 pll->mode_set(dev_priv, pll);
1852 }
1853}
1854
92f2584a 1855/**
85b3894f 1856 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1857 * @dev_priv: i915 private structure
1858 * @pipe: pipe PLL to enable
1859 *
1860 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1861 * drives the transcoder clock.
1862 */
85b3894f 1863static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1864{
3d13ef2e
DL		 1865 struct drm_device *dev = crtc->base.dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1867 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1868
87a875bb 1869 if (WARN_ON(pll == NULL))
48da64a8
CW		 1870 return;
1871
3e369b76 1872 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1873 return;
ee7b9f93 1874
74dd6928 1875 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1876 pll->name, pll->active, pll->on,
e2b78267 1877 crtc->base.base.id);
92f2584a 1878
cdbd2316
DV		 1879 if (pll->active++) {
1880 WARN_ON(!pll->on);
e9d6944e 1881 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1882 return;
1883 }
f4a091c7 1884 WARN_ON(pll->on);
ee7b9f93 1885
bd2bb1b9
PZ		 1886 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1887
46edb027 1888 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1889 pll->enable(dev_priv, pll);
ee7b9f93 1890 pll->on = true;
92f2584a
JB		 1891}
1892
f6daaec2 1893static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1894{
3d13ef2e
DL		 1895 struct drm_device *dev = crtc->base.dev;
1896 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1897 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1898
92f2584a 1899 /* PCH only available on ILK+ */
80aa9312
JB		 1900 if (INTEL_INFO(dev)->gen < 5)
1901 return;
1902
eddfcbcd
ML		 1903 if (pll == NULL)
1904 return;
92f2584a 1905
eddfcbcd 1906 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1907 return;
7a419866 1908
46edb027
DV		 1909 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1910 pll->name, pll->active, pll->on,
e2b78267 1911 crtc->base.base.id);
7a419866 1912
48da64a8 1913 if (WARN_ON(pll->active == 0)) {
e9d6944e 1914 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1915 return;
1916 }
1917
e9d6944e 1918 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1919 WARN_ON(!pll->on);
cdbd2316 1920 if (--pll->active)
7a419866 1921 return;
ee7b9f93 1922
46edb027 1923 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1924 pll->disable(dev_priv, pll);
ee7b9f93 1925 pll->on = false;
bd2bb1b9
PZ		 1926
1927 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1928}
1929
b8a4f404
PZ		 1930static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1931 enum pipe pipe)
040484af 1932{
23670b32 1933 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1934 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1936 uint32_t reg, val, pipeconf_val;
040484af
JB		 1937
1938 /* PCH only available on ILK+ */
55522f37 1939 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1940
1941 /* Make sure PCH DPLL is enabled */
e72f9fbf 1942 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1943 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1944
1945 /* FDI must be feeding us bits for PCH ports */
1946 assert_fdi_tx_enabled(dev_priv, pipe);
1947 assert_fdi_rx_enabled(dev_priv, pipe);
1948
23670b32
DV		 1949 if (HAS_PCH_CPT(dev)) {
1950 /* Workaround: Set the timing override bit before enabling the
1951 * pch transcoder. */
1952 reg = TRANS_CHICKEN2(pipe);
1953 val = I915_READ(reg);
1954 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1955 I915_WRITE(reg, val);
59c859d6 1956 }
23670b32 1957
ab9412ba 1958 reg = PCH_TRANSCONF(pipe);
040484af 1959 val = I915_READ(reg);
5f7f726d 1960 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1961
1962 if (HAS_PCH_IBX(dev_priv->dev)) {
1963 /*
c5de7c6f
VS		 1964 * Make the BPC in transcoder be consistent with
1965 * that in pipeconf reg. For HDMI we must use 8bpc
1966 * here for both 8bpc and 12bpc.
e9bcff5c 1967 */
dfd07d72 1968 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1969 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1970 val |= PIPECONF_8BPC;
1971 else
1972 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1973 }
5f7f726d
PZ		 1974
1975 val &= ~TRANS_INTERLACE_MASK;
1976 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1977 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1978 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1979 val |= TRANS_LEGACY_INTERLACED_ILK;
1980 else
1981 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1982 else
1983 val |= TRANS_PROGRESSIVE;
1984
040484af
JB		 1985 I915_WRITE(reg, val | TRANS_ENABLE);
1986 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1987 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1988}
1989
8fb033d7 1990static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1991 enum transcoder cpu_transcoder)
040484af 1992{
8fb033d7 1993 u32 val, pipeconf_val;
8fb033d7
PZ		 1994
1995 /* PCH only available on ILK+ */
55522f37 1996 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 1997
8fb033d7 1998 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1999 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2000 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2001
223a6fdf
PZ		 2002 /* Workaround: set timing override bit. */
2003 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2004 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2005 I915_WRITE(_TRANSA_CHICKEN2, val);
2006
25f3ef11 2007 val = TRANS_ENABLE;
937bb610 2008 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2009
9a76b1c6
PZ		 2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2011 PIPECONF_INTERLACED_ILK)
a35f2679 2012 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2013 else
2014 val |= TRANS_PROGRESSIVE;
2015
ab9412ba
DV		 2016 I915_WRITE(LPT_TRANSCONF, val);
2017 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2018 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2019}
2020
b8a4f404
PZ		 2021static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2022 enum pipe pipe)
040484af 2023{
23670b32
DV		 2024 struct drm_device *dev = dev_priv->dev;
2025 uint32_t reg, val;
040484af
JB		 2026
2027 /* FDI relies on the transcoder */
2028 assert_fdi_tx_disabled(dev_priv, pipe);
2029 assert_fdi_rx_disabled(dev_priv, pipe);
2030
291906f1
JB		 2031 /* Ports must be off as well */
2032 assert_pch_ports_disabled(dev_priv, pipe);
2033
ab9412ba 2034 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2035 val = I915_READ(reg);
2036 val &= ~TRANS_ENABLE;
2037 I915_WRITE(reg, val);
2038 /* wait for PCH transcoder off, transcoder state */
2039 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2040 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2041
2042 if (!HAS_PCH_IBX(dev)) {
2043 /* Workaround: Clear the timing override chicken bit again. */
2044 reg = TRANS_CHICKEN2(pipe);
2045 val = I915_READ(reg);
2046 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2047 I915_WRITE(reg, val);
2048 }
040484af
JB		 2049}
2050
ab4d966c 2051static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2052{
8fb033d7
PZ		 2053 u32 val;
2054
ab9412ba 2055 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2056 val &= ~TRANS_ENABLE;
ab9412ba 2057 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2058 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2059 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2060 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2061
2062 /* Workaround: clear timing override bit. */
2063 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2064 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2065 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2066}
2067
b24e7179 2068/**
309cfea8 2069 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2070 * @crtc: crtc responsible for the pipe
b24e7179 2071 *
0372264a 2072 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2073 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2074 */
e1fdc473 2075static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2076{
0372264a
PZ		 2077 struct drm_device *dev = crtc->base.dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2080 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2081 pipe);
1a240d4d 2082 enum pipe pch_transcoder;
b24e7179
JB		 2083 int reg;
2084 u32 val;
2085
9e2ee2dd
VS		 2086 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2087
58c6eaa2 2088 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2089 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2090 assert_sprites_disabled(dev_priv, pipe);
2091
681e5811 2092 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2093 pch_transcoder = TRANSCODER_A;
2094 else
2095 pch_transcoder = pipe;
2096
b24e7179
JB		 2097 /*
2098 * A pipe without a PLL won't actually be able to drive bits from
2099 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2100 * need the check.
2101 */
50360403 2102 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2103 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2104 assert_dsi_pll_enabled(dev_priv);
2105 else
2106 assert_pll_enabled(dev_priv, pipe);
040484af 2107 else {
6e3c9717 2108 if (crtc->config->has_pch_encoder) {
040484af 2109 /* if driving the PCH, we need FDI enabled */
cc391bbb 2110 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2111 assert_fdi_tx_pll_enabled(dev_priv,
2112 (enum pipe) cpu_transcoder);
040484af
JB		 2113 }
2114 /* FIXME: assert CPU port conditions for SNB+ */
2115 }
b24e7179 2116
702e7a56 2117 reg = PIPECONF(cpu_transcoder);
b24e7179 2118 val = I915_READ(reg);
7ad25d48 2119 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2120 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2121 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2122 return;
7ad25d48 2123 }
00d70b15
CW		 2124
2125 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2126 POSTING_READ(reg);
b24e7179
JB		 2127}
2128
2129/**
309cfea8 2130 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2131 * @crtc: crtc whose pipes is to be disabled
b24e7179 2132 *
575f7ab7
VS		 2133 * Disable the pipe of @crtc, making sure that various hardware
2134 * specific requirements are met, if applicable, e.g. plane
2135 * disabled, panel fitter off, etc.
b24e7179
JB		 2136 *
2137 * Will wait until the pipe has shut down before returning.
2138 */
575f7ab7 2139static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2140{
575f7ab7 2141 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2142 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2143 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2144 int reg;
2145 u32 val;
2146
9e2ee2dd
VS		 2147 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2148
b24e7179
JB		 2149 /*
2150 * Make sure planes won't keep trying to pump pixels to us,
2151 * or we might hang the display.
2152 */
2153 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2154 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2155 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2156
702e7a56 2157 reg = PIPECONF(cpu_transcoder);
b24e7179 2158 val = I915_READ(reg);
00d70b15
CW		 2159 if ((val & PIPECONF_ENABLE) == 0)
2160 return;
2161
67adc644
VS		 2162 /*
2163 * Double wide has implications for planes
2164 * so best keep it disabled when not needed.
2165 */
6e3c9717 2166 if (crtc->config->double_wide)
67adc644
VS		 2167 val &= ~PIPECONF_DOUBLE_WIDE;
2168
2169 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2170 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2171 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2172 val &= ~PIPECONF_ENABLE;
2173
2174 I915_WRITE(reg, val);
2175 if ((val & PIPECONF_ENABLE) == 0)
2176 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2177}
2178
693db184
CW		 2179static bool need_vtd_wa(struct drm_device *dev)
2180{
2181#ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184#endif
2185 return false;
2186}
2187
50470bb0 2188unsigned int
6761dd31
TU		 2189intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2190 uint64_t fb_format_modifier)
a57ce0b2 2191{
6761dd31
TU		 2192 unsigned int tile_height;
2193 uint32_t pixel_bytes;
a57ce0b2 2194
b5d0e9bf
DL		 2195 switch (fb_format_modifier) {
2196 case DRM_FORMAT_MOD_NONE:
2197 tile_height = 1;
2198 break;
2199 case I915_FORMAT_MOD_X_TILED:
2200 tile_height = IS_GEN2(dev) ? 16 : 8;
2201 break;
2202 case I915_FORMAT_MOD_Y_TILED:
2203 tile_height = 32;
2204 break;
2205 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2206 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2207 switch (pixel_bytes) {
b5d0e9bf 2208 default:
6761dd31 2209 case 1:
b5d0e9bf
DL		 2210 tile_height = 64;
2211 break;
6761dd31
TU		 2212 case 2:
2213 case 4:
b5d0e9bf
DL		 2214 tile_height = 32;
2215 break;
6761dd31 2216 case 8:
b5d0e9bf
DL		 2217 tile_height = 16;
2218 break;
6761dd31 2219 case 16:
b5d0e9bf
DL		 2220 WARN_ONCE(1,
2221 "128-bit pixels are not supported for display!");
2222 tile_height = 16;
2223 break;
2224 }
2225 break;
2226 default:
2227 MISSING_CASE(fb_format_modifier);
2228 tile_height = 1;
2229 break;
2230 }
091df6cb 2231
6761dd31
TU		 2232 return tile_height;
2233}
2234
2235unsigned int
2236intel_fb_align_height(struct drm_device *dev, unsigned int height,
2237 uint32_t pixel_format, uint64_t fb_format_modifier)
2238{
2239 return ALIGN(height, intel_tile_height(dev, pixel_format,
2240 fb_format_modifier));
a57ce0b2
JB		 2241}
2242
f64b98cd
TU		 2243static int
2244intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2245 const struct drm_plane_state *plane_state)
2246{
50470bb0 2247 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2248 unsigned int tile_height, tile_pitch;
50470bb0 2249
f64b98cd
TU		 2250 *view = i915_ggtt_view_normal;
2251
50470bb0
TU		 2252 if (!plane_state)
2253 return 0;
2254
121920fa 2255 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2256 return 0;
2257
9abc4648 2258 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2259
2260 info->height = fb->height;
2261 info->pixel_format = fb->pixel_format;
2262 info->pitch = fb->pitches[0];
2263 info->fb_modifier = fb->modifier[0];
2264
84fe03f7
TU		 2265 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2266 fb->modifier[0]);
2267 tile_pitch = PAGE_SIZE / tile_height;
2268 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2269 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2270 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2271
f64b98cd
TU		 2272 return 0;
2273}
2274
4e9a86b6
VS		 2275static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2276{
2277 if (INTEL_INFO(dev_priv)->gen >= 9)
2278 return 256 * 1024;
985b8bb4
VS		 2279 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2280 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2281 return 128 * 1024;
2282 else if (INTEL_INFO(dev_priv)->gen >= 4)
2283 return 4 * 1024;
2284 else
44c5905e 2285 return 0;
4e9a86b6
VS		 2286}
2287
127bd2ac 2288int
850c4cdc
TU		 2289intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2290 struct drm_framebuffer *fb,
82bc3b2d 2291 const struct drm_plane_state *plane_state,
91af127f
JH		 2292 struct intel_engine_cs *pipelined,
2293 struct drm_i915_gem_request **pipelined_request)
6b95a207 2294{
850c4cdc 2295 struct drm_device *dev = fb->dev;
ce453d81 2296 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2297 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2298 struct i915_ggtt_view view;
6b95a207
KH		 2299 u32 alignment;
2300 int ret;
2301
ebcdd39e
MR		 2302 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2303
7b911adc
TU		 2304 switch (fb->modifier[0]) {
2305 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2306 alignment = intel_linear_alignment(dev_priv);
6b95a207 2307 break;
7b911adc 2308 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2309 if (INTEL_INFO(dev)->gen >= 9)
2310 alignment = 256 * 1024;
2311 else {
2312 /* pin() will align the object as required by fence */
2313 alignment = 0;
2314 }
6b95a207 2315 break;
7b911adc 2316 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2317 case I915_FORMAT_MOD_Yf_TILED:
2318 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2319 "Y tiling bo slipped through, driver bug!\n"))
2320 return -EINVAL;
2321 alignment = 1 * 1024 * 1024;
2322 break;
6b95a207 2323 default:
7b911adc
TU		 2324 MISSING_CASE(fb->modifier[0]);
2325 return -EINVAL;
6b95a207
KH		 2326 }
2327
f64b98cd
TU		 2328 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2329 if (ret)
2330 return ret;
2331
693db184
CW		 2332 /* Note that the w/a also requires 64 PTE of padding following the
2333 * bo. We currently fill all unused PTE with the shadow page and so
2334 * we should always have valid PTE following the scanout preventing
2335 * the VT-d warning.
2336 */
2337 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2338 alignment = 256 * 1024;
2339
d6dd6843
PZ		 2340 /*
2341 * Global gtt pte registers are special registers which actually forward
2342 * writes to a chunk of system memory. Which means that there is no risk
2343 * that the register values disappear as soon as we call
2344 * intel_runtime_pm_put(), so it is correct to wrap only the
2345 * pin/unpin/fence and not more.
2346 */
2347 intel_runtime_pm_get(dev_priv);
2348
ce453d81 2349 dev_priv->mm.interruptible = false;
e6617330 2350 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2351 pipelined_request, &view);
48b956c5 2352 if (ret)
ce453d81 2353 goto err_interruptible;
6b95a207
KH		 2354
2355 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2356 * fence, whereas 965+ only requires a fence if using
2357 * framebuffer compression. For simplicity, we always install
2358 * a fence as the cost is not that onerous.
2359 */
06d98131 2360 ret = i915_gem_object_get_fence(obj);
842315ee
ML		 2361 if (ret == -EDEADLK) {
2362 /*
2363 * -EDEADLK means there are no free fences
2364 * no pending flips.
2365 *
2366 * This is propagated to atomic, but it uses
2367 * -EDEADLK to force a locking recovery, so
2368 * change the returned error to -EBUSY.
2369 */
2370 ret = -EBUSY;
2371 goto err_unpin;
2372 } else if (ret)
9a5a53b3 2373 goto err_unpin;
1690e1eb 2374
9a5a53b3 2375 i915_gem_object_pin_fence(obj);
6b95a207 2376
ce453d81 2377 dev_priv->mm.interruptible = true;
d6dd6843 2378 intel_runtime_pm_put(dev_priv);
6b95a207 2379 return 0;
48b956c5
CW		 2380
2381err_unpin:
f64b98cd 2382 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2383err_interruptible:
2384 dev_priv->mm.interruptible = true;
d6dd6843 2385 intel_runtime_pm_put(dev_priv);
48b956c5 2386 return ret;
6b95a207
KH		 2387}
2388
82bc3b2d
TU		 2389static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2390 const struct drm_plane_state *plane_state)
1690e1eb 2391{
82bc3b2d 2392 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2393 struct i915_ggtt_view view;
2394 int ret;
82bc3b2d 2395
ebcdd39e
MR		 2396 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2397
f64b98cd
TU		 2398 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2399 WARN_ONCE(ret, "Couldn't get view from plane state!");
2400
1690e1eb 2401 i915_gem_object_unpin_fence(obj);
f64b98cd 2402 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2403}
2404
c2c75131
DV		 2405/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2406 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2407unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2408 int *x, int *y,
bc752862
CW		 2409 unsigned int tiling_mode,
2410 unsigned int cpp,
2411 unsigned int pitch)
c2c75131 2412{
bc752862
CW		 2413 if (tiling_mode != I915_TILING_NONE) {
2414 unsigned int tile_rows, tiles;
c2c75131 2415
bc752862
CW		 2416 tile_rows = *y / 8;
2417 *y %= 8;
c2c75131 2418
bc752862
CW		 2419 tiles = *x / (512/cpp);
2420 *x %= 512/cpp;
2421
2422 return tile_rows * pitch * 8 + tiles * 4096;
2423 } else {
4e9a86b6 2424 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2425 unsigned int offset;
2426
2427 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2428 *y = (offset & alignment) / pitch;
2429 *x = ((offset & alignment) - *y * pitch) / cpp;
2430 return offset & ~alignment;
bc752862 2431 }
c2c75131
DV		 2432}
2433
b35d63fa 2434static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2435{
2436 switch (format) {
2437 case DISPPLANE_8BPP:
2438 return DRM_FORMAT_C8;
2439 case DISPPLANE_BGRX555:
2440 return DRM_FORMAT_XRGB1555;
2441 case DISPPLANE_BGRX565:
2442 return DRM_FORMAT_RGB565;
2443 default:
2444 case DISPPLANE_BGRX888:
2445 return DRM_FORMAT_XRGB8888;
2446 case DISPPLANE_RGBX888:
2447 return DRM_FORMAT_XBGR8888;
2448 case DISPPLANE_BGRX101010:
2449 return DRM_FORMAT_XRGB2101010;
2450 case DISPPLANE_RGBX101010:
2451 return DRM_FORMAT_XBGR2101010;
2452 }
2453}
2454
bc8d7dff
DL		 2455static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2456{
2457 switch (format) {
2458 case PLANE_CTL_FORMAT_RGB_565:
2459 return DRM_FORMAT_RGB565;
2460 default:
2461 case PLANE_CTL_FORMAT_XRGB_8888:
2462 if (rgb_order) {
2463 if (alpha)
2464 return DRM_FORMAT_ABGR8888;
2465 else
2466 return DRM_FORMAT_XBGR8888;
2467 } else {
2468 if (alpha)
2469 return DRM_FORMAT_ARGB8888;
2470 else
2471 return DRM_FORMAT_XRGB8888;
2472 }
2473 case PLANE_CTL_FORMAT_XRGB_2101010:
2474 if (rgb_order)
2475 return DRM_FORMAT_XBGR2101010;
2476 else
2477 return DRM_FORMAT_XRGB2101010;
2478 }
2479}
2480
5724dbd1 2481static bool
f6936e29
DV		 2482intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2483 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2484{
2485 struct drm_device *dev = crtc->base.dev;
2486 struct drm_i915_gem_object *obj = NULL;
2487 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2488 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2489 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2490 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2491 PAGE_SIZE);
2492
2493 size_aligned -= base_aligned;
46f297fb 2494
ff2652ea
CW		 2495 if (plane_config->size == 0)
2496 return false;
2497
f37b5c2b
DV		 2498 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2499 base_aligned,
2500 base_aligned,
2501 size_aligned);
46f297fb 2502 if (!obj)
484b41dd 2503 return false;
46f297fb 2504
49af449b
DL		 2505 obj->tiling_mode = plane_config->tiling;
2506 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2507 obj->stride = fb->pitches[0];
46f297fb 2508
6bf129df
DL		 2509 mode_cmd.pixel_format = fb->pixel_format;
2510 mode_cmd.width = fb->width;
2511 mode_cmd.height = fb->height;
2512 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2513 mode_cmd.modifier[0] = fb->modifier[0];
2514 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2515
2516 mutex_lock(&dev->struct_mutex);
6bf129df 2517 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2518 &mode_cmd, obj)) {
46f297fb
JB		 2519 DRM_DEBUG_KMS("intel fb init failed\n");
2520 goto out_unref_obj;
2521 }
46f297fb 2522 mutex_unlock(&dev->struct_mutex);
484b41dd 2523
f6936e29 2524 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2525 return true;
46f297fb
JB		 2526
2527out_unref_obj:
2528 drm_gem_object_unreference(&obj->base);
2529 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2530 return false;
2531}
2532
afd65eb4
MR		 2533/* Update plane->state->fb to match plane->fb after driver-internal updates */
2534static void
2535update_state_fb(struct drm_plane *plane)
2536{
2537 if (plane->fb == plane->state->fb)
2538 return;
2539
2540 if (plane->state->fb)
2541 drm_framebuffer_unreference(plane->state->fb);
2542 plane->state->fb = plane->fb;
2543 if (plane->state->fb)
2544 drm_framebuffer_reference(plane->state->fb);
2545}
2546
5724dbd1 2547static void
f6936e29
DV		 2548intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2549 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2550{
2551 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2552 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2553 struct drm_crtc *c;
2554 struct intel_crtc *i;
2ff8fde1 2555 struct drm_i915_gem_object *obj;
88595ac9 2556 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2557 struct drm_plane_state *plane_state = primary->state;
88595ac9 2558 struct drm_framebuffer *fb;
484b41dd 2559
2d14030b 2560 if (!plane_config->fb)
484b41dd
JB		 2561 return;
2562
f6936e29 2563 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2564 fb = &plane_config->fb->base;
2565 goto valid_fb;
f55548b5 2566 }
484b41dd 2567
2d14030b 2568 kfree(plane_config->fb);
484b41dd
JB		 2569
2570 /*
2571 * Failed to alloc the obj, check to see if we should share
2572 * an fb with another CRTC instead
2573 */
70e1e0ec 2574 for_each_crtc(dev, c) {
484b41dd
JB		 2575 i = to_intel_crtc(c);
2576
2577 if (c == &intel_crtc->base)
2578 continue;
2579
2ff8fde1
MR		 2580 if (!i->active)
2581 continue;
2582
88595ac9
DV		 2583 fb = c->primary->fb;
2584 if (!fb)
484b41dd
JB		 2585 continue;
2586
88595ac9 2587 obj = intel_fb_obj(fb);
2ff8fde1 2588 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2589 drm_framebuffer_reference(fb);
2590 goto valid_fb;
484b41dd
JB		 2591 }
2592 }
88595ac9
DV		 2593
2594 return;
2595
2596valid_fb:
be5651f2
ML		 2597 plane_state->src_x = plane_state->src_y = 0;
2598 plane_state->src_w = fb->width << 16;
2599 plane_state->src_h = fb->height << 16;
2600
2601 plane_state->crtc_x = plane_state->src_y = 0;
2602 plane_state->crtc_w = fb->width;
2603 plane_state->crtc_h = fb->height;
2604
88595ac9
DV		 2605 obj = intel_fb_obj(fb);
2606 if (obj->tiling_mode != I915_TILING_NONE)
2607 dev_priv->preserve_bios_swizzle = true;
2608
be5651f2
ML		 2609 drm_framebuffer_reference(fb);
2610 primary->fb = primary->state->fb = fb;
36750f28 2611 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2612 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2613 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2614}
2615
29b9bde6
DV		 2616static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2617 struct drm_framebuffer *fb,
2618 int x, int y)
81255565
JB		 2619{
2620 struct drm_device *dev = crtc->dev;
2621 struct drm_i915_private *dev_priv = dev->dev_private;
2622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2623 struct drm_plane *primary = crtc->primary;
2624 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2625 struct drm_i915_gem_object *obj;
81255565 2626 int plane = intel_crtc->plane;
e506a0c6 2627 unsigned long linear_offset;
81255565 2628 u32 dspcntr;
f45651ba 2629 u32 reg = DSPCNTR(plane);
48404c1e 2630 int pixel_size;
f45651ba 2631
b70709a6 2632 if (!visible || !fb) {
fdd508a6
VS		 2633 I915_WRITE(reg, 0);
2634 if (INTEL_INFO(dev)->gen >= 4)
2635 I915_WRITE(DSPSURF(plane), 0);
2636 else
2637 I915_WRITE(DSPADDR(plane), 0);
2638 POSTING_READ(reg);
2639 return;
2640 }
2641
c9ba6fad
VS		 2642 obj = intel_fb_obj(fb);
2643 if (WARN_ON(obj == NULL))
2644 return;
2645
2646 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2647
f45651ba
VS		 2648 dspcntr = DISPPLANE_GAMMA_ENABLE;
2649
fdd508a6 2650 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2651
2652 if (INTEL_INFO(dev)->gen < 4) {
2653 if (intel_crtc->pipe == PIPE_B)
2654 dspcntr |= DISPPLANE_SEL_PIPE_B;
2655
2656 /* pipesrc and dspsize control the size that is scaled from,
2657 * which should always be the user's requested size.
2658 */
2659 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2660 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2661 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2662 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2663 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2664 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2665 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2666 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2667 I915_WRITE(PRIMPOS(plane), 0);
2668 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2669 }
81255565 2670
57779d06
VS		 2671 switch (fb->pixel_format) {
2672 case DRM_FORMAT_C8:
81255565
JB		 2673 dspcntr |= DISPPLANE_8BPP;
2674 break;
57779d06 2675 case DRM_FORMAT_XRGB1555:
57779d06 2676 dspcntr |= DISPPLANE_BGRX555;
81255565 2677 break;
57779d06
VS		 2678 case DRM_FORMAT_RGB565:
2679 dspcntr |= DISPPLANE_BGRX565;
2680 break;
2681 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2682 dspcntr |= DISPPLANE_BGRX888;
2683 break;
2684 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2685 dspcntr |= DISPPLANE_RGBX888;
2686 break;
2687 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2688 dspcntr |= DISPPLANE_BGRX101010;
2689 break;
2690 case DRM_FORMAT_XBGR2101010:
57779d06 2691 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2692 break;
2693 default:
baba133a 2694 BUG();
81255565 2695 }
57779d06 2696
f45651ba
VS		 2697 if (INTEL_INFO(dev)->gen >= 4 &&
2698 obj->tiling_mode != I915_TILING_NONE)
2699 dspcntr |= DISPPLANE_TILED;
81255565 2700
de1aa629
VS		 2701 if (IS_G4X(dev))
2702 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2703
b9897127 2704 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2705
c2c75131
DV		 2706 if (INTEL_INFO(dev)->gen >= 4) {
2707 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2708 intel_gen4_compute_page_offset(dev_priv,
2709 &x, &y, obj->tiling_mode,
b9897127 2710 pixel_size,
bc752862 2711 fb->pitches[0]);
c2c75131
DV		 2712 linear_offset -= intel_crtc->dspaddr_offset;
2713 } else {
e506a0c6 2714 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2715 }
e506a0c6 2716
8e7d688b 2717 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2718 dspcntr |= DISPPLANE_ROTATE_180;
2719
6e3c9717
ACO		 2720 x += (intel_crtc->config->pipe_src_w - 1);
2721 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2722
2723 /* Finding the last pixel of the last line of the display
2724 data and adding to linear_offset*/
2725 linear_offset +=
6e3c9717
ACO		 2726 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2727 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2728 }
2729
2730 I915_WRITE(reg, dspcntr);
2731
01f2c773 2732 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2733 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2734 I915_WRITE(DSPSURF(plane),
2735 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2736 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2737 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2738 } else
f343c5f6 2739 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2740 POSTING_READ(reg);
17638cd6
JB		 2741}
2742
29b9bde6
DV		 2743static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2744 struct drm_framebuffer *fb,
2745 int x, int y)
17638cd6
JB		 2746{
2747 struct drm_device *dev = crtc->dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2750 struct drm_plane *primary = crtc->primary;
2751 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2752 struct drm_i915_gem_object *obj;
17638cd6 2753 int plane = intel_crtc->plane;
e506a0c6 2754 unsigned long linear_offset;
17638cd6 2755 u32 dspcntr;
f45651ba 2756 u32 reg = DSPCNTR(plane);
48404c1e 2757 int pixel_size;
f45651ba 2758
b70709a6 2759 if (!visible || !fb) {
fdd508a6
VS		 2760 I915_WRITE(reg, 0);
2761 I915_WRITE(DSPSURF(plane), 0);
2762 POSTING_READ(reg);
2763 return;
2764 }
2765
c9ba6fad
VS		 2766 obj = intel_fb_obj(fb);
2767 if (WARN_ON(obj == NULL))
2768 return;
2769
2770 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2771
f45651ba
VS		 2772 dspcntr = DISPPLANE_GAMMA_ENABLE;
2773
fdd508a6 2774 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2775
2776 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2777 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2778
57779d06
VS		 2779 switch (fb->pixel_format) {
2780 case DRM_FORMAT_C8:
17638cd6
JB		 2781 dspcntr |= DISPPLANE_8BPP;
2782 break;
57779d06
VS		 2783 case DRM_FORMAT_RGB565:
2784 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2785 break;
57779d06 2786 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2787 dspcntr |= DISPPLANE_BGRX888;
2788 break;
2789 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2790 dspcntr |= DISPPLANE_RGBX888;
2791 break;
2792 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2793 dspcntr |= DISPPLANE_BGRX101010;
2794 break;
2795 case DRM_FORMAT_XBGR2101010:
57779d06 2796 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2797 break;
2798 default:
baba133a 2799 BUG();
17638cd6
JB		 2800 }
2801
2802 if (obj->tiling_mode != I915_TILING_NONE)
2803 dspcntr |= DISPPLANE_TILED;
17638cd6 2804
f45651ba 2805 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2806 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2807
b9897127 2808 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2809 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2810 intel_gen4_compute_page_offset(dev_priv,
2811 &x, &y, obj->tiling_mode,
b9897127 2812 pixel_size,
bc752862 2813 fb->pitches[0]);
c2c75131 2814 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2815 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2816 dspcntr |= DISPPLANE_ROTATE_180;
2817
2818 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2819 x += (intel_crtc->config->pipe_src_w - 1);
2820 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2821
2822 /* Finding the last pixel of the last line of the display
2823 data and adding to linear_offset*/
2824 linear_offset +=
6e3c9717
ACO		 2825 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2826 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2827 }
2828 }
2829
2830 I915_WRITE(reg, dspcntr);
17638cd6 2831
01f2c773 2832 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2833 I915_WRITE(DSPSURF(plane),
2834 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2835 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2836 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2837 } else {
2838 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2839 I915_WRITE(DSPLINOFF(plane), linear_offset);
2840 }
17638cd6 2841 POSTING_READ(reg);
17638cd6
JB		 2842}
2843
b321803d
DL		 2844u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2845 uint32_t pixel_format)
2846{
2847 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2848
2849 /*
2850 * The stride is either expressed as a multiple of 64 bytes
2851 * chunks for linear buffers or in number of tiles for tiled
2852 * buffers.
2853 */
2854 switch (fb_modifier) {
2855 case DRM_FORMAT_MOD_NONE:
2856 return 64;
2857 case I915_FORMAT_MOD_X_TILED:
2858 if (INTEL_INFO(dev)->gen == 2)
2859 return 128;
2860 return 512;
2861 case I915_FORMAT_MOD_Y_TILED:
2862 /* No need to check for old gens and Y tiling since this is
2863 * about the display engine and those will be blocked before
2864 * we get here.
2865 */
2866 return 128;
2867 case I915_FORMAT_MOD_Yf_TILED:
2868 if (bits_per_pixel == 8)
2869 return 64;
2870 else
2871 return 128;
2872 default:
2873 MISSING_CASE(fb_modifier);
2874 return 64;
2875 }
2876}
2877
121920fa
TU		 2878unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2879 struct drm_i915_gem_object *obj)
2880{
9abc4648 2881 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2882
2883 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2884 view = &i915_ggtt_view_rotated;
121920fa
TU		 2885
2886 return i915_gem_obj_ggtt_offset_view(obj, view);
2887}
2888
e435d6e5
ML		 2889static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2890{
2891 struct drm_device *dev = intel_crtc->base.dev;
2892 struct drm_i915_private *dev_priv = dev->dev_private;
2893
2894 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2895 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2896 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML		 2897}
2898
a1b2278e
CK		 2899/*
2900 * This function detaches (aka. unbinds) unused scalers in hardware
2901 */
0583236e 2902static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2903{
a1b2278e
CK		 2904 struct intel_crtc_scaler_state *scaler_state;
2905 int i;
2906
a1b2278e
CK		 2907 scaler_state = &intel_crtc->config->scaler_state;
2908
2909 /* loop through and disable scalers that aren't in use */
2910 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2911 if (!scaler_state->scalers[i].in_use)
2912 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2913 }
2914}
2915
6156a456 2916u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2917{
6156a456 2918 switch (pixel_format) {
d161cf7a 2919 case DRM_FORMAT_C8:
c34ce3d1 2920 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2921 case DRM_FORMAT_RGB565:
c34ce3d1 2922 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2923 case DRM_FORMAT_XBGR8888:
c34ce3d1 2924 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2925 case DRM_FORMAT_XRGB8888:
c34ce3d1 2926 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2927 /*
2928 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2929 * to be already pre-multiplied. We need to add a knob (or a different
2930 * DRM_FORMAT) for user-space to configure that.
2931 */
f75fb42a 2932 case DRM_FORMAT_ABGR8888:
c34ce3d1 2933 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2934 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2935 case DRM_FORMAT_ARGB8888:
c34ce3d1 2936 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2937 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2938 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2939 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2940 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2941 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2942 case DRM_FORMAT_YUYV:
c34ce3d1 2943 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2944 case DRM_FORMAT_YVYU:
c34ce3d1 2945 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2946 case DRM_FORMAT_UYVY:
c34ce3d1 2947 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2948 case DRM_FORMAT_VYUY:
c34ce3d1 2949 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2950 default:
4249eeef 2951 MISSING_CASE(pixel_format);
70d21f0e 2952 }
8cfcba41 2953
c34ce3d1 2954 return 0;
6156a456 2955}
70d21f0e 2956
6156a456
CK		 2957u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2958{
6156a456 2959 switch (fb_modifier) {
30af77c4 2960 case DRM_FORMAT_MOD_NONE:
70d21f0e 2961 break;
30af77c4 2962 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2963 return PLANE_CTL_TILED_X;
b321803d 2964 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2965 return PLANE_CTL_TILED_Y;
b321803d 2966 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2967 return PLANE_CTL_TILED_YF;
70d21f0e 2968 default:
6156a456 2969 MISSING_CASE(fb_modifier);
70d21f0e 2970 }
8cfcba41 2971
c34ce3d1 2972 return 0;
6156a456 2973}
70d21f0e 2974
6156a456
CK		 2975u32 skl_plane_ctl_rotation(unsigned int rotation)
2976{
3b7a5119 2977 switch (rotation) {
6156a456
CK		 2978 case BIT(DRM_ROTATE_0):
2979 break;
1e8df167
SJ		 2980 /*
2981 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2982 * while i915 HW rotation is clockwise, thats why this swapping.
2983 */
3b7a5119 2984 case BIT(DRM_ROTATE_90):
1e8df167 2985 return PLANE_CTL_ROTATE_270;
3b7a5119 2986 case BIT(DRM_ROTATE_180):
c34ce3d1 2987 return PLANE_CTL_ROTATE_180;
3b7a5119 2988 case BIT(DRM_ROTATE_270):
1e8df167 2989 return PLANE_CTL_ROTATE_90;
6156a456
CK		 2990 default:
2991 MISSING_CASE(rotation);
2992 }
2993
c34ce3d1 2994 return 0;
6156a456
CK		 2995}
2996
2997static void skylake_update_primary_plane(struct drm_crtc *crtc,
2998 struct drm_framebuffer *fb,
2999 int x, int y)
3000{
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3004 struct drm_plane *plane = crtc->primary;
3005 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3006 struct drm_i915_gem_object *obj;
3007 int pipe = intel_crtc->pipe;
3008 u32 plane_ctl, stride_div, stride;
3009 u32 tile_height, plane_offset, plane_size;
3010 unsigned int rotation;
3011 int x_offset, y_offset;
3012 unsigned long surf_addr;
6156a456
CK		 3013 struct intel_crtc_state *crtc_state = intel_crtc->config;
3014 struct intel_plane_state *plane_state;
3015 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3016 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3017 int scaler_id = -1;
3018
6156a456
CK		 3019 plane_state = to_intel_plane_state(plane->state);
3020
b70709a6 3021 if (!visible || !fb) {
6156a456
CK		 3022 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3023 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3024 POSTING_READ(PLANE_CTL(pipe, 0));
3025 return;
3b7a5119 3026 }
70d21f0e 3027
6156a456
CK		 3028 plane_ctl = PLANE_CTL_ENABLE |
3029 PLANE_CTL_PIPE_GAMMA_ENABLE |
3030 PLANE_CTL_PIPE_CSC_ENABLE;
3031
3032 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3033 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3034 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3035
3036 rotation = plane->state->rotation;
3037 plane_ctl |= skl_plane_ctl_rotation(rotation);
3038
b321803d
DL		 3039 obj = intel_fb_obj(fb);
3040 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3041 fb->pixel_format);
3b7a5119
SJ		 3042 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3043
6156a456
CK		 3044 /*
3045 * FIXME: intel_plane_state->src, dst aren't set when transitional
3046 * update_plane helpers are called from legacy paths.
3047 * Once full atomic crtc is available, below check can be avoided.
3048 */
3049 if (drm_rect_width(&plane_state->src)) {
3050 scaler_id = plane_state->scaler_id;
3051 src_x = plane_state->src.x1 >> 16;
3052 src_y = plane_state->src.y1 >> 16;
3053 src_w = drm_rect_width(&plane_state->src) >> 16;
3054 src_h = drm_rect_height(&plane_state->src) >> 16;
3055 dst_x = plane_state->dst.x1;
3056 dst_y = plane_state->dst.y1;
3057 dst_w = drm_rect_width(&plane_state->dst);
3058 dst_h = drm_rect_height(&plane_state->dst);
3059
3060 WARN_ON(x != src_x || y != src_y);
3061 } else {
3062 src_w = intel_crtc->config->pipe_src_w;
3063 src_h = intel_crtc->config->pipe_src_h;
3064 }
3065
3b7a5119
SJ		 3066 if (intel_rotation_90_or_270(rotation)) {
3067 /* stride = Surface height in tiles */
2614f17d 3068 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3069 fb->modifier[0]);
3070 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3071 x_offset = stride * tile_height - y - src_h;
3b7a5119 3072 y_offset = x;
6156a456 3073 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3074 } else {
3075 stride = fb->pitches[0] / stride_div;
3076 x_offset = x;
3077 y_offset = y;
6156a456 3078 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3079 }
3080 plane_offset = y_offset << 16 | x_offset;
b321803d 3081
70d21f0e 3082 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3083 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3084 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3085 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3086
3087 if (scaler_id >= 0) {
3088 uint32_t ps_ctrl = 0;
3089
3090 WARN_ON(!dst_w || !dst_h);
3091 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3092 crtc_state->scaler_state.scalers[scaler_id].mode;
3093 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3094 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3095 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3096 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3097 I915_WRITE(PLANE_POS(pipe, 0), 0);
3098 } else {
3099 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3100 }
3101
121920fa 3102 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3103
3104 POSTING_READ(PLANE_SURF(pipe, 0));
3105}
3106
17638cd6
JB		 3107/* Assume fb object is pinned & idle & fenced and just update base pointers */
3108static int
3109intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3110 int x, int y, enum mode_set_atomic state)
3111{
3112 struct drm_device *dev = crtc->dev;
3113 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3114
ff2a3117 3115 if (dev_priv->fbc.disable_fbc)
7733b49b 3116 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3117
29b9bde6
DV		 3118 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3119
3120 return 0;
81255565
JB		 3121}
3122
7514747d 3123static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3124{
96a02917
VS		 3125 struct drm_crtc *crtc;
3126
70e1e0ec 3127 for_each_crtc(dev, crtc) {
96a02917
VS		 3128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3129 enum plane plane = intel_crtc->plane;
3130
3131 intel_prepare_page_flip(dev, plane);
3132 intel_finish_page_flip_plane(dev, plane);
3133 }
7514747d
VS		 3134}
3135
3136static void intel_update_primary_planes(struct drm_device *dev)
3137{
7514747d 3138 struct drm_crtc *crtc;
96a02917 3139
70e1e0ec 3140 for_each_crtc(dev, crtc) {
11c22da6
ML		 3141 struct intel_plane *plane = to_intel_plane(crtc->primary);
3142 struct intel_plane_state *plane_state;
96a02917 3143
11c22da6
ML		 3144 drm_modeset_lock_crtc(crtc, &plane->base);
3145
3146 plane_state = to_intel_plane_state(plane->base.state);
3147
3148 if (plane_state->base.fb)
3149 plane->commit_plane(&plane->base, plane_state);
3150
3151 drm_modeset_unlock_crtc(crtc);
96a02917
VS		 3152 }
3153}
3154
7514747d
VS		 3155void intel_prepare_reset(struct drm_device *dev)
3156{
3157 /* no reset support for gen2 */
3158 if (IS_GEN2(dev))
3159 return;
3160
3161 /* reset doesn't touch the display */
3162 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3163 return;
3164
3165 drm_modeset_lock_all(dev);
f98ce92f
VS		 3166 /*
3167 * Disabling the crtcs gracefully seems nicer. Also the
3168 * g33 docs say we should at least disable all the planes.
3169 */
6b72d486 3170 intel_display_suspend(dev);
7514747d
VS		 3171}
3172
3173void intel_finish_reset(struct drm_device *dev)
3174{
3175 struct drm_i915_private *dev_priv = to_i915(dev);
3176
3177 /*
3178 * Flips in the rings will be nuked by the reset,
3179 * so complete all pending flips so that user space
3180 * will get its events and not get stuck.
3181 */
3182 intel_complete_page_flips(dev);
3183
3184 /* no reset support for gen2 */
3185 if (IS_GEN2(dev))
3186 return;
3187
3188 /* reset doesn't touch the display */
3189 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3190 /*
3191 * Flips in the rings have been nuked by the reset,
3192 * so update the base address of all primary
3193 * planes to the the last fb to make sure we're
3194 * showing the correct fb after a reset.
11c22da6
ML		 3195 *
3196 * FIXME: Atomic will make this obsolete since we won't schedule
3197 * CS-based flips (which might get lost in gpu resets) any more.
7514747d
VS		 3198 */
3199 intel_update_primary_planes(dev);
3200 return;
3201 }
3202
3203 /*
3204 * The display has been reset as well,
3205 * so need a full re-initialization.
3206 */
3207 intel_runtime_pm_disable_interrupts(dev_priv);
3208 intel_runtime_pm_enable_interrupts(dev_priv);
3209
3210 intel_modeset_init_hw(dev);
3211
3212 spin_lock_irq(&dev_priv->irq_lock);
3213 if (dev_priv->display.hpd_irq_setup)
3214 dev_priv->display.hpd_irq_setup(dev);
3215 spin_unlock_irq(&dev_priv->irq_lock);
3216
043e9bda 3217 intel_display_resume(dev);
7514747d
VS		 3218
3219 intel_hpd_init(dev_priv);
3220
3221 drm_modeset_unlock_all(dev);
3222}
3223
2e2f351d 3224static void
14667a4b
CW		 3225intel_finish_fb(struct drm_framebuffer *old_fb)
3226{
2ff8fde1 3227 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3228 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3229 bool was_interruptible = dev_priv->mm.interruptible;
3230 int ret;
3231
14667a4b
CW		 3232 /* Big Hammer, we also need to ensure that any pending
3233 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3234 * current scanout is retired before unpinning the old
2e2f351d
CW		 3235 * framebuffer. Note that we rely on userspace rendering
3236 * into the buffer attached to the pipe they are waiting
3237 * on. If not, userspace generates a GPU hang with IPEHR
3238 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3239 *
3240 * This should only fail upon a hung GPU, in which case we
3241 * can safely continue.
3242 */
3243 dev_priv->mm.interruptible = false;
2e2f351d 3244 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3245 dev_priv->mm.interruptible = was_interruptible;
3246
2e2f351d 3247 WARN_ON(ret);
14667a4b
CW		 3248}
3249
7d5e3799
CW		 3250static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3251{
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3255 bool pending;
3256
3257 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3258 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3259 return false;
3260
5e2d7afc 3261 spin_lock_irq(&dev->event_lock);
7d5e3799 3262 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3263 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3264
3265 return pending;
3266}
3267
e30e8f75
GP		 3268static void intel_update_pipe_size(struct intel_crtc *crtc)
3269{
3270 struct drm_device *dev = crtc->base.dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 const struct drm_display_mode *adjusted_mode;
3273
3274 if (!i915.fastboot)
3275 return;
3276
3277 /*
3278 * Update pipe size and adjust fitter if needed: the reason for this is
3279 * that in compute_mode_changes we check the native mode (not the pfit
3280 * mode) to see if we can flip rather than do a full mode set. In the
3281 * fastboot case, we'll flip, but if we don't update the pipesrc and
3282 * pfit state, we'll end up with a big fb scanned out into the wrong
3283 * sized surface.
3284 *
3285 * To fix this properly, we need to hoist the checks up into
3286 * compute_mode_changes (or above), check the actual pfit state and
3287 * whether the platform allows pfit disable with pipe active, and only
3288 * then update the pipesrc and pfit state, even on the flip path.
3289 */
3290
6e3c9717 3291 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3292
3293 I915_WRITE(PIPESRC(crtc->pipe),
3294 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3295 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3296 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3297 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3298 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3299 I915_WRITE(PF_CTL(crtc->pipe), 0);
3300 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3301 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3302 }
6e3c9717
ACO		 3303 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3304 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3305}
3306
5e84e1a4
ZW		 3307static void intel_fdi_normal_train(struct drm_crtc *crtc)
3308{
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312 int pipe = intel_crtc->pipe;
3313 u32 reg, temp;
3314
3315 /* enable normal train */
3316 reg = FDI_TX_CTL(pipe);
3317 temp = I915_READ(reg);
61e499bf 3318 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3319 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3320 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3321 } else {
3322 temp &= ~FDI_LINK_TRAIN_NONE;
3323 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3324 }
5e84e1a4
ZW		 3325 I915_WRITE(reg, temp);
3326
3327 reg = FDI_RX_CTL(pipe);
3328 temp = I915_READ(reg);
3329 if (HAS_PCH_CPT(dev)) {
3330 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3331 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3332 } else {
3333 temp &= ~FDI_LINK_TRAIN_NONE;
3334 temp |= FDI_LINK_TRAIN_NONE;
3335 }
3336 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3337
3338 /* wait one idle pattern time */
3339 POSTING_READ(reg);
3340 udelay(1000);
357555c0
JB		 3341
3342 /* IVB wants error correction enabled */
3343 if (IS_IVYBRIDGE(dev))
3344 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3345 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3346}
3347
8db9d77b
ZW		 3348/* The FDI link training functions for ILK/Ibexpeak. */
3349static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3350{
3351 struct drm_device *dev = crtc->dev;
3352 struct drm_i915_private *dev_priv = dev->dev_private;
3353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3354 int pipe = intel_crtc->pipe;
5eddb70b 3355 u32 reg, temp, tries;
8db9d77b 3356
1c8562f6 3357 /* FDI needs bits from pipe first */
0fc932b8 3358 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3359
e1a44743
AJ		 3360 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3361 for train result */
5eddb70b
CW		 3362 reg = FDI_RX_IMR(pipe);
3363 temp = I915_READ(reg);
e1a44743
AJ		 3364 temp &= ~FDI_RX_SYMBOL_LOCK;
3365 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3366 I915_WRITE(reg, temp);
3367 I915_READ(reg);
e1a44743
AJ		 3368 udelay(150);
3369
8db9d77b 3370 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3371 reg = FDI_TX_CTL(pipe);
3372 temp = I915_READ(reg);
627eb5a3 3373 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3374 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3377 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3378
5eddb70b
CW		 3379 reg = FDI_RX_CTL(pipe);
3380 temp = I915_READ(reg);
8db9d77b
ZW		 3381 temp &= ~FDI_LINK_TRAIN_NONE;
3382 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3383 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3384
3385 POSTING_READ(reg);
8db9d77b
ZW		 3386 udelay(150);
3387
5b2adf89 3388 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3389 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3390 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3391 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3392
5eddb70b 3393 reg = FDI_RX_IIR(pipe);
e1a44743 3394 for (tries = 0; tries < 5; tries++) {
5eddb70b 3395 temp = I915_READ(reg);
8db9d77b
ZW		 3396 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3397
3398 if ((temp & FDI_RX_BIT_LOCK)) {
3399 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3400 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3401 break;
3402 }
8db9d77b 3403 }
e1a44743 3404 if (tries == 5)
5eddb70b 3405 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3406
3407 /* Train 2 */
5eddb70b
CW		 3408 reg = FDI_TX_CTL(pipe);
3409 temp = I915_READ(reg);
8db9d77b
ZW		 3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3412 I915_WRITE(reg, temp);
8db9d77b 3413
5eddb70b
CW		 3414 reg = FDI_RX_CTL(pipe);
3415 temp = I915_READ(reg);
8db9d77b
ZW		 3416 temp &= ~FDI_LINK_TRAIN_NONE;
3417 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3418 I915_WRITE(reg, temp);
8db9d77b 3419
5eddb70b
CW		 3420 POSTING_READ(reg);
3421 udelay(150);
8db9d77b 3422
5eddb70b 3423 reg = FDI_RX_IIR(pipe);
e1a44743 3424 for (tries = 0; tries < 5; tries++) {
5eddb70b 3425 temp = I915_READ(reg);
8db9d77b
ZW		 3426 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3427
3428 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3429 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3430 DRM_DEBUG_KMS("FDI train 2 done.\n");
3431 break;
3432 }
8db9d77b 3433 }
e1a44743 3434 if (tries == 5)
5eddb70b 3435 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3436
3437 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3438
8db9d77b
ZW		 3439}
3440
0206e353 3441static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3442 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3443 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3444 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3445 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3446};
3447
3448/* The FDI link training functions for SNB/Cougarpoint. */
3449static void gen6_fdi_link_train(struct drm_crtc *crtc)
3450{
3451 struct drm_device *dev = crtc->dev;
3452 struct drm_i915_private *dev_priv = dev->dev_private;
3453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3454 int pipe = intel_crtc->pipe;
fa37d39e 3455 u32 reg, temp, i, retry;
8db9d77b 3456
e1a44743
AJ		 3457 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3458 for train result */
5eddb70b
CW		 3459 reg = FDI_RX_IMR(pipe);
3460 temp = I915_READ(reg);
e1a44743
AJ		 3461 temp &= ~FDI_RX_SYMBOL_LOCK;
3462 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3463 I915_WRITE(reg, temp);
3464
3465 POSTING_READ(reg);
e1a44743
AJ		 3466 udelay(150);
3467
8db9d77b 3468 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3469 reg = FDI_TX_CTL(pipe);
3470 temp = I915_READ(reg);
627eb5a3 3471 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3472 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_1;
3475 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3476 /* SNB-B */
3477 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3478 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3479
d74cf324
DV		 3480 I915_WRITE(FDI_RX_MISC(pipe),
3481 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3482
5eddb70b
CW		 3483 reg = FDI_RX_CTL(pipe);
3484 temp = I915_READ(reg);
8db9d77b
ZW		 3485 if (HAS_PCH_CPT(dev)) {
3486 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3487 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3488 } else {
3489 temp &= ~FDI_LINK_TRAIN_NONE;
3490 temp |= FDI_LINK_TRAIN_PATTERN_1;
3491 }
5eddb70b
CW		 3492 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3493
3494 POSTING_READ(reg);
8db9d77b
ZW		 3495 udelay(150);
3496
0206e353 3497 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3498 reg = FDI_TX_CTL(pipe);
3499 temp = I915_READ(reg);
8db9d77b
ZW		 3500 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3501 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3502 I915_WRITE(reg, temp);
3503
3504 POSTING_READ(reg);
8db9d77b
ZW		 3505 udelay(500);
3506
fa37d39e
SP		 3507 for (retry = 0; retry < 5; retry++) {
3508 reg = FDI_RX_IIR(pipe);
3509 temp = I915_READ(reg);
3510 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3511 if (temp & FDI_RX_BIT_LOCK) {
3512 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3513 DRM_DEBUG_KMS("FDI train 1 done.\n");
3514 break;
3515 }
3516 udelay(50);
8db9d77b 3517 }
fa37d39e
SP		 3518 if (retry < 5)
3519 break;
8db9d77b
ZW		 3520 }
3521 if (i == 4)
5eddb70b 3522 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3523
3524 /* Train 2 */
5eddb70b
CW		 3525 reg = FDI_TX_CTL(pipe);
3526 temp = I915_READ(reg);
8db9d77b
ZW		 3527 temp &= ~FDI_LINK_TRAIN_NONE;
3528 temp |= FDI_LINK_TRAIN_PATTERN_2;
3529 if (IS_GEN6(dev)) {
3530 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3531 /* SNB-B */
3532 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3533 }
5eddb70b 3534 I915_WRITE(reg, temp);
8db9d77b 3535
5eddb70b
CW		 3536 reg = FDI_RX_CTL(pipe);
3537 temp = I915_READ(reg);
8db9d77b
ZW		 3538 if (HAS_PCH_CPT(dev)) {
3539 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3540 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3541 } else {
3542 temp &= ~FDI_LINK_TRAIN_NONE;
3543 temp |= FDI_LINK_TRAIN_PATTERN_2;
3544 }
5eddb70b
CW		 3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
8db9d77b
ZW		 3548 udelay(150);
3549
0206e353 3550 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3551 reg = FDI_TX_CTL(pipe);
3552 temp = I915_READ(reg);
8db9d77b
ZW		 3553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3554 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3555 I915_WRITE(reg, temp);
3556
3557 POSTING_READ(reg);
8db9d77b
ZW		 3558 udelay(500);
3559
fa37d39e
SP		 3560 for (retry = 0; retry < 5; retry++) {
3561 reg = FDI_RX_IIR(pipe);
3562 temp = I915_READ(reg);
3563 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3564 if (temp & FDI_RX_SYMBOL_LOCK) {
3565 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3566 DRM_DEBUG_KMS("FDI train 2 done.\n");
3567 break;
3568 }
3569 udelay(50);
8db9d77b 3570 }
fa37d39e
SP		 3571 if (retry < 5)
3572 break;
8db9d77b
ZW		 3573 }
3574 if (i == 4)
5eddb70b 3575 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3576
3577 DRM_DEBUG_KMS("FDI train done.\n");
3578}
3579
357555c0
JB		 3580/* Manual link training for Ivy Bridge A0 parts */
3581static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3582{
3583 struct drm_device *dev = crtc->dev;
3584 struct drm_i915_private *dev_priv = dev->dev_private;
3585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3586 int pipe = intel_crtc->pipe;
139ccd3f 3587 u32 reg, temp, i, j;
357555c0
JB		 3588
3589 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3590 for train result */
3591 reg = FDI_RX_IMR(pipe);
3592 temp = I915_READ(reg);
3593 temp &= ~FDI_RX_SYMBOL_LOCK;
3594 temp &= ~FDI_RX_BIT_LOCK;
3595 I915_WRITE(reg, temp);
3596
3597 POSTING_READ(reg);
3598 udelay(150);
3599
01a415fd
DV		 3600 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3601 I915_READ(FDI_RX_IIR(pipe)));
3602
139ccd3f
JB		 3603 /* Try each vswing and preemphasis setting twice before moving on */
3604 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3605 /* disable first in case we need to retry */
3606 reg = FDI_TX_CTL(pipe);
3607 temp = I915_READ(reg);
3608 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3609 temp &= ~FDI_TX_ENABLE;
3610 I915_WRITE(reg, temp);
357555c0 3611
139ccd3f
JB		 3612 reg = FDI_RX_CTL(pipe);
3613 temp = I915_READ(reg);
3614 temp &= ~FDI_LINK_TRAIN_AUTO;
3615 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3616 temp &= ~FDI_RX_ENABLE;
3617 I915_WRITE(reg, temp);
357555c0 3618
139ccd3f 3619 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3620 reg = FDI_TX_CTL(pipe);
3621 temp = I915_READ(reg);
139ccd3f 3622 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3623 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3626 temp |= snb_b_fdi_train_param[j/2];
3627 temp |= FDI_COMPOSITE_SYNC;
3628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3629
139ccd3f
JB		 3630 I915_WRITE(FDI_RX_MISC(pipe),
3631 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3632
139ccd3f 3633 reg = FDI_RX_CTL(pipe);
357555c0 3634 temp = I915_READ(reg);
139ccd3f
JB		 3635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3636 temp |= FDI_COMPOSITE_SYNC;
3637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3638
139ccd3f
JB		 3639 POSTING_READ(reg);
3640 udelay(1); /* should be 0.5us */
357555c0 3641
139ccd3f
JB		 3642 for (i = 0; i < 4; i++) {
3643 reg = FDI_RX_IIR(pipe);
3644 temp = I915_READ(reg);
3645 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3646
139ccd3f
JB		 3647 if (temp & FDI_RX_BIT_LOCK ||
3648 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3649 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3650 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3651 i);
3652 break;
3653 }
3654 udelay(1); /* should be 0.5us */
3655 }
3656 if (i == 4) {
3657 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3658 continue;
3659 }
357555c0 3660
139ccd3f 3661 /* Train 2 */
357555c0
JB		 3662 reg = FDI_TX_CTL(pipe);
3663 temp = I915_READ(reg);
139ccd3f
JB		 3664 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3665 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3666 I915_WRITE(reg, temp);
3667
3668 reg = FDI_RX_CTL(pipe);
3669 temp = I915_READ(reg);
3670 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3671 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3672 I915_WRITE(reg, temp);
3673
3674 POSTING_READ(reg);
139ccd3f 3675 udelay(2); /* should be 1.5us */
357555c0 3676
139ccd3f
JB		 3677 for (i = 0; i < 4; i++) {
3678 reg = FDI_RX_IIR(pipe);
3679 temp = I915_READ(reg);
3680 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3681
139ccd3f
JB		 3682 if (temp & FDI_RX_SYMBOL_LOCK ||
3683 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3684 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3685 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3686 i);
3687 goto train_done;
3688 }
3689 udelay(2); /* should be 1.5us */
357555c0 3690 }
139ccd3f
JB		 3691 if (i == 4)
3692 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3693 }
357555c0 3694
139ccd3f 3695train_done:
357555c0
JB		 3696 DRM_DEBUG_KMS("FDI train done.\n");
3697}
3698
88cefb6c 3699static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3700{
88cefb6c 3701 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3702 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3703 int pipe = intel_crtc->pipe;
5eddb70b 3704 u32 reg, temp;
79e53945 3705
c64e311e 3706
c98e9dcf 3707 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3708 reg = FDI_RX_CTL(pipe);
3709 temp = I915_READ(reg);
627eb5a3 3710 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3711 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3713 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3714
3715 POSTING_READ(reg);
c98e9dcf
JB		 3716 udelay(200);
3717
3718 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3719 temp = I915_READ(reg);
3720 I915_WRITE(reg, temp | FDI_PCDCLK);
3721
3722 POSTING_READ(reg);
c98e9dcf
JB		 3723 udelay(200);
3724
20749730
PZ		 3725 /* Enable CPU FDI TX PLL, always on for Ironlake */
3726 reg = FDI_TX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3729 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3730
20749730
PZ		 3731 POSTING_READ(reg);
3732 udelay(100);
6be4a607 3733 }
0e23b99d
JB		 3734}
3735
88cefb6c
DV		 3736static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3737{
3738 struct drm_device *dev = intel_crtc->base.dev;
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 int pipe = intel_crtc->pipe;
3741 u32 reg, temp;
3742
3743 /* Switch from PCDclk to Rawclk */
3744 reg = FDI_RX_CTL(pipe);
3745 temp = I915_READ(reg);
3746 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3747
3748 /* Disable CPU FDI TX PLL */
3749 reg = FDI_TX_CTL(pipe);
3750 temp = I915_READ(reg);
3751 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3752
3753 POSTING_READ(reg);
3754 udelay(100);
3755
3756 reg = FDI_RX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3759
3760 /* Wait for the clocks to turn off. */
3761 POSTING_READ(reg);
3762 udelay(100);
3763}
3764
0fc932b8
JB		 3765static void ironlake_fdi_disable(struct drm_crtc *crtc)
3766{
3767 struct drm_device *dev = crtc->dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3770 int pipe = intel_crtc->pipe;
3771 u32 reg, temp;
3772
3773 /* disable CPU FDI tx and PCH FDI rx */
3774 reg = FDI_TX_CTL(pipe);
3775 temp = I915_READ(reg);
3776 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3777 POSTING_READ(reg);
3778
3779 reg = FDI_RX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 temp &= ~(0x7 << 16);
dfd07d72 3782 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3783 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3784
3785 POSTING_READ(reg);
3786 udelay(100);
3787
3788 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3789 if (HAS_PCH_IBX(dev))
6f06ce18 3790 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3791
3792 /* still set train pattern 1 */
3793 reg = FDI_TX_CTL(pipe);
3794 temp = I915_READ(reg);
3795 temp &= ~FDI_LINK_TRAIN_NONE;
3796 temp |= FDI_LINK_TRAIN_PATTERN_1;
3797 I915_WRITE(reg, temp);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 if (HAS_PCH_CPT(dev)) {
3802 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3803 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3804 } else {
3805 temp &= ~FDI_LINK_TRAIN_NONE;
3806 temp |= FDI_LINK_TRAIN_PATTERN_1;
3807 }
3808 /* BPC in FDI rx is consistent with that in PIPECONF */
3809 temp &= ~(0x07 << 16);
dfd07d72 3810 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3811 I915_WRITE(reg, temp);
3812
3813 POSTING_READ(reg);
3814 udelay(100);
3815}
3816
5dce5b93
CW		 3817bool intel_has_pending_fb_unpin(struct drm_device *dev)
3818{
3819 struct intel_crtc *crtc;
3820
3821 /* Note that we don't need to be called with mode_config.lock here
3822 * as our list of CRTC objects is static for the lifetime of the
3823 * device and so cannot disappear as we iterate. Similarly, we can
3824 * happily treat the predicates as racy, atomic checks as userspace
3825 * cannot claim and pin a new fb without at least acquring the
3826 * struct_mutex and so serialising with us.
3827 */
d3fcc808 3828 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3829 if (atomic_read(&crtc->unpin_work_count) == 0)
3830 continue;
3831
3832 if (crtc->unpin_work)
3833 intel_wait_for_vblank(dev, crtc->pipe);
3834
3835 return true;
3836 }
3837
3838 return false;
3839}
3840
d6bbafa1
CW		 3841static void page_flip_completed(struct intel_crtc *intel_crtc)
3842{
3843 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3844 struct intel_unpin_work *work = intel_crtc->unpin_work;
3845
3846 /* ensure that the unpin work is consistent wrt ->pending. */
3847 smp_rmb();
3848 intel_crtc->unpin_work = NULL;
3849
3850 if (work->event)
3851 drm_send_vblank_event(intel_crtc->base.dev,
3852 intel_crtc->pipe,
3853 work->event);
3854
3855 drm_crtc_vblank_put(&intel_crtc->base);
3856
3857 wake_up_all(&dev_priv->pending_flip_queue);
3858 queue_work(dev_priv->wq, &work->work);
3859
3860 trace_i915_flip_complete(intel_crtc->plane,
3861 work->pending_flip_obj);
3862}
3863
46a55d30 3864void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3865{
0f91128d 3866 struct drm_device *dev = crtc->dev;
5bb61643 3867 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3868
2c10d571 3869 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3870 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3871 !intel_crtc_has_pending_flip(crtc),
3872 60*HZ) == 0)) {
3873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3874
5e2d7afc 3875 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3876 if (intel_crtc->unpin_work) {
3877 WARN_ONCE(1, "Removing stuck page flip\n");
3878 page_flip_completed(intel_crtc);
3879 }
5e2d7afc 3880 spin_unlock_irq(&dev->event_lock);
9c787942 3881 }
5bb61643 3882
975d568a
CW		 3883 if (crtc->primary->fb) {
3884 mutex_lock(&dev->struct_mutex);
3885 intel_finish_fb(crtc->primary->fb);
3886 mutex_unlock(&dev->struct_mutex);
3887 }
e6c3a2a6
CW		 3888}
3889
e615efe4
ED		 3890/* Program iCLKIP clock to the desired frequency */
3891static void lpt_program_iclkip(struct drm_crtc *crtc)
3892{
3893 struct drm_device *dev = crtc->dev;
3894 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3895 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3896 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3897 u32 temp;
3898
a580516d 3899 mutex_lock(&dev_priv->sb_lock);
09153000 3900
e615efe4
ED		 3901 /* It is necessary to ungate the pixclk gate prior to programming
3902 * the divisors, and gate it back when it is done.
3903 */
3904 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3905
3906 /* Disable SSCCTL */
3907 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3908 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3909 SBI_SSCCTL_DISABLE,
3910 SBI_ICLK);
e615efe4
ED		 3911
3912 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3913 if (clock == 20000) {
e615efe4
ED		 3914 auxdiv = 1;
3915 divsel = 0x41;
3916 phaseinc = 0x20;
3917 } else {
3918 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3919 * but the adjusted_mode->crtc_clock in in KHz. To get the
3920 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3921 * convert the virtual clock precision to KHz here for higher
3922 * precision.
3923 */
3924 u32 iclk_virtual_root_freq = 172800 * 1000;
3925 u32 iclk_pi_range = 64;
3926 u32 desired_divisor, msb_divisor_value, pi_value;
3927
12d7ceed 3928 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3929 msb_divisor_value = desired_divisor / iclk_pi_range;
3930 pi_value = desired_divisor % iclk_pi_range;
3931
3932 auxdiv = 0;
3933 divsel = msb_divisor_value - 2;
3934 phaseinc = pi_value;
3935 }
3936
3937 /* This should not happen with any sane values */
3938 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3939 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3940 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3941 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3942
3943 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3944 clock,
e615efe4
ED		 3945 auxdiv,
3946 divsel,
3947 phasedir,
3948 phaseinc);
3949
3950 /* Program SSCDIVINTPHASE6 */
988d6ee8 3951 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3952 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3953 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3954 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3955 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3956 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3957 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3958 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3959
3960 /* Program SSCAUXDIV */
988d6ee8 3961 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3962 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3963 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3964 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3965
3966 /* Enable modulator and associated divider */
988d6ee8 3967 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3968 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3969 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3970
3971 /* Wait for initialization time */
3972 udelay(24);
3973
3974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3975
a580516d 3976 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 3977}
3978
275f01b2
DV		 3979static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3980 enum pipe pch_transcoder)
3981{
3982 struct drm_device *dev = crtc->base.dev;
3983 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3984 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3985
3986 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3987 I915_READ(HTOTAL(cpu_transcoder)));
3988 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3989 I915_READ(HBLANK(cpu_transcoder)));
3990 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3991 I915_READ(HSYNC(cpu_transcoder)));
3992
3993 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3994 I915_READ(VTOTAL(cpu_transcoder)));
3995 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3996 I915_READ(VBLANK(cpu_transcoder)));
3997 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3998 I915_READ(VSYNC(cpu_transcoder)));
3999 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4000 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4001}
4002
003632d9 4003static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4004{
4005 struct drm_i915_private *dev_priv = dev->dev_private;
4006 uint32_t temp;
4007
4008 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4009 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4010 return;
4011
4012 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4013 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4014
003632d9
ACO		 4015 temp &= ~FDI_BC_BIFURCATION_SELECT;
4016 if (enable)
4017 temp |= FDI_BC_BIFURCATION_SELECT;
4018
4019 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4020 I915_WRITE(SOUTH_CHICKEN1, temp);
4021 POSTING_READ(SOUTH_CHICKEN1);
4022}
4023
4024static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4025{
4026 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4027
4028 switch (intel_crtc->pipe) {
4029 case PIPE_A:
4030 break;
4031 case PIPE_B:
6e3c9717 4032 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4033 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4034 else
003632d9 4035 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4036
4037 break;
4038 case PIPE_C:
003632d9 4039 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4040
4041 break;
4042 default:
4043 BUG();
4044 }
4045}
4046
f67a559d
JB		 4047/*
4048 * Enable PCH resources required for PCH ports:
4049 * - PCH PLLs
4050 * - FDI training & RX/TX
4051 * - update transcoder timings
4052 * - DP transcoding bits
4053 * - transcoder
4054 */
4055static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4056{
4057 struct drm_device *dev = crtc->dev;
4058 struct drm_i915_private *dev_priv = dev->dev_private;
4059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4060 int pipe = intel_crtc->pipe;
ee7b9f93 4061 u32 reg, temp;
2c07245f 4062
ab9412ba 4063 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4064
1fbc0d78
DV		 4065 if (IS_IVYBRIDGE(dev))
4066 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4067
cd986abb
DV		 4068 /* Write the TU size bits before fdi link training, so that error
4069 * detection works. */
4070 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4071 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4072
c98e9dcf 4073 /* For PCH output, training FDI link */
674cf967 4074 dev_priv->display.fdi_link_train(crtc);
2c07245f 4075
3ad8a208
DV		 4076 /* We need to program the right clock selection before writing the pixel
4077 * mutliplier into the DPLL. */
303b81e0 4078 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4079 u32 sel;
4b645f14 4080
c98e9dcf 4081 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4082 temp |= TRANS_DPLL_ENABLE(pipe);
4083 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4084 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4085 temp |= sel;
4086 else
4087 temp &= ~sel;
c98e9dcf 4088 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4089 }
5eddb70b 4090
3ad8a208
DV		 4091 /* XXX: pch pll's can be enabled any time before we enable the PCH
4092 * transcoder, and we actually should do this to not upset any PCH
4093 * transcoder that already use the clock when we share it.
4094 *
4095 * Note that enable_shared_dpll tries to do the right thing, but
4096 * get_shared_dpll unconditionally resets the pll - we need that to have
4097 * the right LVDS enable sequence. */
85b3894f 4098 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4099
d9b6cb56
JB		 4100 /* set transcoder timing, panel must allow it */
4101 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4102 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4103
303b81e0 4104 intel_fdi_normal_train(crtc);
5e84e1a4 4105
c98e9dcf 4106 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4107 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4108 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4109 reg = TRANS_DP_CTL(pipe);
4110 temp = I915_READ(reg);
4111 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4112 TRANS_DP_SYNC_MASK |
4113 TRANS_DP_BPC_MASK);
e3ef4479 4114 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4115 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4116
4117 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4118 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4119 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4120 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4121
4122 switch (intel_trans_dp_port_sel(crtc)) {
4123 case PCH_DP_B:
5eddb70b 4124 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4125 break;
4126 case PCH_DP_C:
5eddb70b 4127 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4128 break;
4129 case PCH_DP_D:
5eddb70b 4130 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4131 break;
4132 default:
e95d41e1 4133 BUG();
32f9d658 4134 }
2c07245f 4135
5eddb70b 4136 I915_WRITE(reg, temp);
6be4a607 4137 }
b52eb4dc 4138
b8a4f404 4139 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4140}
4141
1507e5bd
PZ		 4142static void lpt_pch_enable(struct drm_crtc *crtc)
4143{
4144 struct drm_device *dev = crtc->dev;
4145 struct drm_i915_private *dev_priv = dev->dev_private;
4146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4147 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4148
ab9412ba 4149 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4150
8c52b5e8 4151 lpt_program_iclkip(crtc);
1507e5bd 4152
0540e488 4153 /* Set transcoder timing. */
275f01b2 4154 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4155
937bb610 4156 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4157}
4158
190f68c5
ACO		 4159struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4160 struct intel_crtc_state *crtc_state)
ee7b9f93 4161{
e2b78267 4162 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4163 struct intel_shared_dpll *pll;
de419ab6 4164 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4165 enum intel_dpll_id i;
ee7b9f93 4166
de419ab6
ML		 4167 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4168
98b6bd99
DV		 4169 if (HAS_PCH_IBX(dev_priv->dev)) {
4170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4171 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4172 pll = &dev_priv->shared_dplls[i];
98b6bd99 4173
46edb027
DV		 4174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4175 crtc->base.base.id, pll->name);
98b6bd99 4176
de419ab6 4177 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4178
98b6bd99
DV		 4179 goto found;
4180 }
4181
bcddf610
S		 4182 if (IS_BROXTON(dev_priv->dev)) {
4183 /* PLL is attached to port in bxt */
4184 struct intel_encoder *encoder;
4185 struct intel_digital_port *intel_dig_port;
4186
4187 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4188 if (WARN_ON(!encoder))
4189 return NULL;
4190
4191 intel_dig_port = enc_to_dig_port(&encoder->base);
4192 /* 1:1 mapping between ports and PLLs */
4193 i = (enum intel_dpll_id)intel_dig_port->port;
4194 pll = &dev_priv->shared_dplls[i];
4195 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4196 crtc->base.base.id, pll->name);
de419ab6 4197 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4198
4199 goto found;
4200 }
4201
e72f9fbf
DV		 4202 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4203 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4204
4205 /* Only want to check enabled timings first */
de419ab6 4206 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4207 continue;
4208
190f68c5 4209 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4210 &shared_dpll[i].hw_state,
4211 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4212 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4213 crtc->base.base.id, pll->name,
de419ab6 4214 shared_dpll[i].crtc_mask,
8bd31e67 4215 pll->active);
ee7b9f93
JB		 4216 goto found;
4217 }
4218 }
4219
4220 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4221 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4222 pll = &dev_priv->shared_dplls[i];
de419ab6 4223 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4224 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4225 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4226 goto found;
4227 }
4228 }
4229
4230 return NULL;
4231
4232found:
de419ab6
ML		 4233 if (shared_dpll[i].crtc_mask == 0)
4234 shared_dpll[i].hw_state =
4235 crtc_state->dpll_hw_state;
f2a69f44 4236
190f68c5 4237 crtc_state->shared_dpll = i;
46edb027
DV		 4238 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4239 pipe_name(crtc->pipe));
ee7b9f93 4240
de419ab6 4241 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4242
ee7b9f93
JB		 4243 return pll;
4244}
4245
de419ab6 4246static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4247{
de419ab6
ML		 4248 struct drm_i915_private *dev_priv = to_i915(state->dev);
4249 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4250 struct intel_shared_dpll *pll;
4251 enum intel_dpll_id i;
4252
de419ab6
ML		 4253 if (!to_intel_atomic_state(state)->dpll_set)
4254 return;
8bd31e67 4255
de419ab6 4256 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4257 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4258 pll = &dev_priv->shared_dplls[i];
de419ab6 4259 pll->config = shared_dpll[i];
8bd31e67
ACO		 4260 }
4261}
4262
a1520318 4263static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4264{
4265 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4266 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4267 u32 temp;
4268
4269 temp = I915_READ(dslreg);
4270 udelay(500);
4271 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4272 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4273 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4274 }
4275}
4276
86adf9d7
ML		 4277static int
4278skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4279 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4280 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4281{
86adf9d7
ML		 4282 struct intel_crtc_scaler_state *scaler_state =
4283 &crtc_state->scaler_state;
4284 struct intel_crtc *intel_crtc =
4285 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4286 int need_scaling;
6156a456
CK		 4287
4288 need_scaling = intel_rotation_90_or_270(rotation) ?
4289 (src_h != dst_w || src_w != dst_h):
4290 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4291
4292 /*
4293 * if plane is being disabled or scaler is no more required or force detach
4294 * - free scaler binded to this plane/crtc
4295 * - in order to do this, update crtc->scaler_usage
4296 *
4297 * Here scaler state in crtc_state is set free so that
4298 * scaler can be assigned to other user. Actual register
4299 * update to free the scaler is done in plane/panel-fit programming.
4300 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4301 */
86adf9d7 4302 if (force_detach || !need_scaling) {
a1b2278e 4303 if (*scaler_id >= 0) {
86adf9d7 4304 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4305 scaler_state->scalers[*scaler_id].in_use = 0;
4306
86adf9d7
ML		 4307 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4308 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4309 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4310 scaler_state->scaler_users);
4311 *scaler_id = -1;
4312 }
4313 return 0;
4314 }
4315
4316 /* range checks */
4317 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4318 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4319
4320 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4321 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4322 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4323 "size is out of scaler range\n",
86adf9d7 4324 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4325 return -EINVAL;
4326 }
4327
86adf9d7
ML		 4328 /* mark this plane as a scaler user in crtc_state */
4329 scaler_state->scaler_users |= (1 << scaler_user);
4330 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4331 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4332 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4333 scaler_state->scaler_users);
4334
4335 return 0;
4336}
4337
4338/**
4339 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4340 *
4341 * @state: crtc's scaler state
86adf9d7
ML		 4342 *
4343 * Return
4344 * 0 - scaler_usage updated successfully
4345 * error - requested scaling cannot be supported or other error condition
4346 */
e435d6e5 4347int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4348{
4349 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4350 struct drm_display_mode *adjusted_mode =
4351 &state->base.adjusted_mode;
4352
4353 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4354 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4355
e435d6e5 4356 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4357 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4358 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4359 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4360}
4361
4362/**
4363 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4364 *
4365 * @state: crtc's scaler state
86adf9d7
ML		 4366 * @plane_state: atomic plane state to update
4367 *
4368 * Return
4369 * 0 - scaler_usage updated successfully
4370 * error - requested scaling cannot be supported or other error condition
4371 */
da20eabd
ML		 4372static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4373 struct intel_plane_state *plane_state)
86adf9d7
ML		 4374{
4375
4376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4377 struct intel_plane *intel_plane =
4378 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4379 struct drm_framebuffer *fb = plane_state->base.fb;
4380 int ret;
4381
4382 bool force_detach = !fb || !plane_state->visible;
4383
4384 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4385 intel_plane->base.base.id, intel_crtc->pipe,
4386 drm_plane_index(&intel_plane->base));
4387
4388 ret = skl_update_scaler(crtc_state, force_detach,
4389 drm_plane_index(&intel_plane->base),
4390 &plane_state->scaler_id,
4391 plane_state->base.rotation,
4392 drm_rect_width(&plane_state->src) >> 16,
4393 drm_rect_height(&plane_state->src) >> 16,
4394 drm_rect_width(&plane_state->dst),
4395 drm_rect_height(&plane_state->dst));
4396
4397 if (ret || plane_state->scaler_id < 0)
4398 return ret;
4399
a1b2278e 4400 /* check colorkey */
818ed961 4401 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4402 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4403 intel_plane->base.base.id);
a1b2278e
CK		 4404 return -EINVAL;
4405 }
4406
4407 /* Check src format */
86adf9d7
ML		 4408 switch (fb->pixel_format) {
4409 case DRM_FORMAT_RGB565:
4410 case DRM_FORMAT_XBGR8888:
4411 case DRM_FORMAT_XRGB8888:
4412 case DRM_FORMAT_ABGR8888:
4413 case DRM_FORMAT_ARGB8888:
4414 case DRM_FORMAT_XRGB2101010:
4415 case DRM_FORMAT_XBGR2101010:
4416 case DRM_FORMAT_YUYV:
4417 case DRM_FORMAT_YVYU:
4418 case DRM_FORMAT_UYVY:
4419 case DRM_FORMAT_VYUY:
4420 break;
4421 default:
4422 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4423 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4424 return -EINVAL;
a1b2278e
CK		 4425 }
4426
a1b2278e
CK		 4427 return 0;
4428}
4429
e435d6e5
ML		 4430static void skylake_scaler_disable(struct intel_crtc *crtc)
4431{
4432 int i;
4433
4434 for (i = 0; i < crtc->num_scalers; i++)
4435 skl_detach_scaler(crtc, i);
4436}
4437
4438static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4439{
4440 struct drm_device *dev = crtc->base.dev;
4441 struct drm_i915_private *dev_priv = dev->dev_private;
4442 int pipe = crtc->pipe;
a1b2278e
CK		 4443 struct intel_crtc_scaler_state *scaler_state =
4444 &crtc->config->scaler_state;
4445
4446 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4447
6e3c9717 4448 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4449 int id;
4450
4451 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4452 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4453 return;
4454 }
4455
4456 id = scaler_state->scaler_id;
4457 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4458 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4459 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4460 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4461
4462 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4463 }
4464}
4465
b074cec8
JB		 4466static void ironlake_pfit_enable(struct intel_crtc *crtc)
4467{
4468 struct drm_device *dev = crtc->base.dev;
4469 struct drm_i915_private *dev_priv = dev->dev_private;
4470 int pipe = crtc->pipe;
4471
6e3c9717 4472 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4473 /* Force use of hard-coded filter coefficients
4474 * as some pre-programmed values are broken,
4475 * e.g. x201.
4476 */
4477 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4478 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4479 PF_PIPE_SEL_IVB(pipe));
4480 else
4481 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4482 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4483 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4484 }
4485}
4486
20bc8673 4487void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4488{
cea165c3
VS		 4489 struct drm_device *dev = crtc->base.dev;
4490 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4491
6e3c9717 4492 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4493 return;
4494
cea165c3
VS		 4495 /* We can only enable IPS after we enable a plane and wait for a vblank */
4496 intel_wait_for_vblank(dev, crtc->pipe);
4497
d77e4531 4498 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4499 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4500 mutex_lock(&dev_priv->rps.hw_lock);
4501 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4502 mutex_unlock(&dev_priv->rps.hw_lock);
4503 /* Quoting Art Runyan: "its not safe to expect any particular
4504 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4505 * mailbox." Moreover, the mailbox may return a bogus state,
4506 * so we need to just enable it and continue on.
2a114cc1
BW		 4507 */
4508 } else {
4509 I915_WRITE(IPS_CTL, IPS_ENABLE);
4510 /* The bit only becomes 1 in the next vblank, so this wait here
4511 * is essentially intel_wait_for_vblank. If we don't have this
4512 * and don't wait for vblanks until the end of crtc_enable, then
4513 * the HW state readout code will complain that the expected
4514 * IPS_CTL value is not the one we read. */
4515 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4516 DRM_ERROR("Timed out waiting for IPS enable\n");
4517 }
d77e4531
PZ		 4518}
4519
20bc8673 4520void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4521{
4522 struct drm_device *dev = crtc->base.dev;
4523 struct drm_i915_private *dev_priv = dev->dev_private;
4524
6e3c9717 4525 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4526 return;
4527
4528 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4529 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4530 mutex_lock(&dev_priv->rps.hw_lock);
4531 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4532 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4533 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4534 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4535 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4536 } else {
2a114cc1 4537 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4538 POSTING_READ(IPS_CTL);
4539 }
d77e4531
PZ		 4540
4541 /* We need to wait for a vblank before we can disable the plane. */
4542 intel_wait_for_vblank(dev, crtc->pipe);
4543}
4544
4545/** Loads the palette/gamma unit for the CRTC with the prepared values */
4546static void intel_crtc_load_lut(struct drm_crtc *crtc)
4547{
4548 struct drm_device *dev = crtc->dev;
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4551 enum pipe pipe = intel_crtc->pipe;
4552 int palreg = PALETTE(pipe);
4553 int i;
4554 bool reenable_ips = false;
4555
4556 /* The clocks have to be on to load the palette. */
53d9f4e9 4557 if (!crtc->state->active)
d77e4531
PZ		 4558 return;
4559
50360403 4560 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4561 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4562 assert_dsi_pll_enabled(dev_priv);
4563 else
4564 assert_pll_enabled(dev_priv, pipe);
4565 }
4566
4567 /* use legacy palette for Ironlake */
7a1db49a 4568 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4569 palreg = LGC_PALETTE(pipe);
4570
4571 /* Workaround : Do not read or write the pipe palette/gamma data while
4572 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4573 */
6e3c9717 4574 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4575 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4576 GAMMA_MODE_MODE_SPLIT)) {
4577 hsw_disable_ips(intel_crtc);
4578 reenable_ips = true;
4579 }
4580
4581 for (i = 0; i < 256; i++) {
4582 I915_WRITE(palreg + 4 * i,
4583 (intel_crtc->lut_r[i] << 16) |
4584 (intel_crtc->lut_g[i] << 8) |
4585 intel_crtc->lut_b[i]);
4586 }
4587
4588 if (reenable_ips)
4589 hsw_enable_ips(intel_crtc);
4590}
4591
7cac945f 4592static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4593{
7cac945f 4594 if (intel_crtc->overlay) {
d3eedb1a
VS		 4595 struct drm_device *dev = intel_crtc->base.dev;
4596 struct drm_i915_private *dev_priv = dev->dev_private;
4597
4598 mutex_lock(&dev->struct_mutex);
4599 dev_priv->mm.interruptible = false;
4600 (void) intel_overlay_switch_off(intel_crtc->overlay);
4601 dev_priv->mm.interruptible = true;
4602 mutex_unlock(&dev->struct_mutex);
4603 }
4604
4605 /* Let userspace switch the overlay on again. In most cases userspace
4606 * has to recompute where to put it anyway.
4607 */
4608}
4609
87d4300a
ML		 4610/**
4611 * intel_post_enable_primary - Perform operations after enabling primary plane
4612 * @crtc: the CRTC whose primary plane was just enabled
4613 *
4614 * Performs potentially sleeping operations that must be done after the primary
4615 * plane is enabled, such as updating FBC and IPS. Note that this may be
4616 * called due to an explicit primary plane update, or due to an implicit
4617 * re-enable that is caused when a sprite plane is updated to no longer
4618 * completely hide the primary plane.
4619 */
4620static void
4621intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4622{
4623 struct drm_device *dev = crtc->dev;
87d4300a 4624 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626 int pipe = intel_crtc->pipe;
a5c4d7bc 4627
87d4300a
ML		 4628 /*
4629 * BDW signals flip done immediately if the plane
4630 * is disabled, even if the plane enable is already
4631 * armed to occur at the next vblank :(
4632 */
4633 if (IS_BROADWELL(dev))
4634 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4635
87d4300a
ML		 4636 /*
4637 * FIXME IPS should be fine as long as one plane is
4638 * enabled, but in practice it seems to have problems
4639 * when going from primary only to sprite only and vice
4640 * versa.
4641 */
a5c4d7bc
VS		 4642 hsw_enable_ips(intel_crtc);
4643
f99d7069 4644 /*
87d4300a
ML		 4645 * Gen2 reports pipe underruns whenever all planes are disabled.
4646 * So don't enable underrun reporting before at least some planes
4647 * are enabled.
4648 * FIXME: Need to fix the logic to work when we turn off all planes
4649 * but leave the pipe running.
f99d7069 4650 */
87d4300a
ML		 4651 if (IS_GEN2(dev))
4652 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4653
4654 /* Underruns don't raise interrupts, so check manually. */
4655 if (HAS_GMCH_DISPLAY(dev))
4656 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4657}
4658
87d4300a
ML		 4659/**
4660 * intel_pre_disable_primary - Perform operations before disabling primary plane
4661 * @crtc: the CRTC whose primary plane is to be disabled
4662 *
4663 * Performs potentially sleeping operations that must be done before the
4664 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4665 * be called due to an explicit primary plane update, or due to an implicit
4666 * disable that is caused when a sprite plane completely hides the primary
4667 * plane.
4668 */
4669static void
4670intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4671{
4672 struct drm_device *dev = crtc->dev;
4673 struct drm_i915_private *dev_priv = dev->dev_private;
4674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4675 int pipe = intel_crtc->pipe;
a5c4d7bc 4676
87d4300a
ML		 4677 /*
4678 * Gen2 reports pipe underruns whenever all planes are disabled.
4679 * So diasble underrun reporting before all the planes get disabled.
4680 * FIXME: Need to fix the logic to work when we turn off all planes
4681 * but leave the pipe running.
4682 */
4683 if (IS_GEN2(dev))
4684 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4685
87d4300a
ML		 4686 /*
4687 * Vblank time updates from the shadow to live plane control register
4688 * are blocked if the memory self-refresh mode is active at that
4689 * moment. So to make sure the plane gets truly disabled, disable
4690 * first the self-refresh mode. The self-refresh enable bit in turn
4691 * will be checked/applied by the HW only at the next frame start
4692 * event which is after the vblank start event, so we need to have a
4693 * wait-for-vblank between disabling the plane and the pipe.
4694 */
262cd2e1 4695 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4696 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4697 dev_priv->wm.vlv.cxsr = false;
4698 intel_wait_for_vblank(dev, pipe);
4699 }
87d4300a 4700
87d4300a
ML		 4701 /*
4702 * FIXME IPS should be fine as long as one plane is
4703 * enabled, but in practice it seems to have problems
4704 * when going from primary only to sprite only and vice
4705 * versa.
4706 */
a5c4d7bc 4707 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4708}
4709
ac21b225
ML		 4710static void intel_post_plane_update(struct intel_crtc *crtc)
4711{
4712 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4713 struct drm_device *dev = crtc->base.dev;
7733b49b 4714 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4715 struct drm_plane *plane;
4716
4717 if (atomic->wait_vblank)
4718 intel_wait_for_vblank(dev, crtc->pipe);
4719
4720 intel_frontbuffer_flip(dev, atomic->fb_bits);
4721
852eb00d
VS		 4722 if (atomic->disable_cxsr)
4723 crtc->wm.cxsr_allowed = true;
4724
f015c551
VS		 4725 if (crtc->atomic.update_wm_post)
4726 intel_update_watermarks(&crtc->base);
4727
c80ac854 4728 if (atomic->update_fbc)
7733b49b 4729 intel_fbc_update(dev_priv);
ac21b225
ML		 4730
4731 if (atomic->post_enable_primary)
4732 intel_post_enable_primary(&crtc->base);
4733
4734 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4735 intel_update_sprite_watermarks(plane, &crtc->base,
4736 0, 0, 0, false, false);
4737
4738 memset(atomic, 0, sizeof(*atomic));
4739}
4740
4741static void intel_pre_plane_update(struct intel_crtc *crtc)
4742{
4743 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4744 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4745 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4746 struct drm_plane *p;
4747
4748 /* Track fb's for any planes being disabled */
ac21b225
ML		 4749 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4750 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4751
4752 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4753 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4754 plane->frontbuffer_bit);
ac21b225
ML		 4755 mutex_unlock(&dev->struct_mutex);
4756 }
4757
4758 if (atomic->wait_for_flips)
4759 intel_crtc_wait_for_pending_flips(&crtc->base);
4760
c80ac854 4761 if (atomic->disable_fbc)
25ad93fd 4762 intel_fbc_disable_crtc(crtc);
ac21b225 4763
066cf55b
RV		 4764 if (crtc->atomic.disable_ips)
4765 hsw_disable_ips(crtc);
4766
ac21b225
ML		 4767 if (atomic->pre_disable_primary)
4768 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4769
4770 if (atomic->disable_cxsr) {
4771 crtc->wm.cxsr_allowed = false;
4772 intel_set_memory_cxsr(dev_priv, false);
4773 }
ac21b225
ML		 4774}
4775
d032ffa0 4776static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4777{
4778 struct drm_device *dev = crtc->dev;
4779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4780 struct drm_plane *p;
87d4300a
ML		 4781 int pipe = intel_crtc->pipe;
4782
7cac945f 4783 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4784
d032ffa0
ML		 4785 drm_for_each_plane_mask(p, dev, plane_mask)
4786 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4787
f99d7069
DV		 4788 /*
4789 * FIXME: Once we grow proper nuclear flip support out of this we need
4790 * to compute the mask of flip planes precisely. For the time being
4791 * consider this a flip to a NULL plane.
4792 */
4793 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4794}
4795
f67a559d
JB		 4796static void ironlake_crtc_enable(struct drm_crtc *crtc)
4797{
4798 struct drm_device *dev = crtc->dev;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4801 struct intel_encoder *encoder;
f67a559d 4802 int pipe = intel_crtc->pipe;
f67a559d 4803
53d9f4e9 4804 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4805 return;
4806
6e3c9717 4807 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4808 intel_prepare_shared_dpll(intel_crtc);
4809
6e3c9717 4810 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4811 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4812
4813 intel_set_pipe_timings(intel_crtc);
4814
6e3c9717 4815 if (intel_crtc->config->has_pch_encoder) {
29407aab 4816 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4817 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4818 }
4819
4820 ironlake_set_pipeconf(crtc);
4821
f67a559d 4822 intel_crtc->active = true;
8664281b 4823
a72e4c9f
DV		 4824 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4825 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4826
f6736a1a 4827 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4828 if (encoder->pre_enable)
4829 encoder->pre_enable(encoder);
f67a559d 4830
6e3c9717 4831 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4832 /* Note: FDI PLL enabling _must_ be done before we enable the
4833 * cpu pipes, hence this is separate from all the other fdi/pch
4834 * enabling. */
88cefb6c 4835 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4836 } else {
4837 assert_fdi_tx_disabled(dev_priv, pipe);
4838 assert_fdi_rx_disabled(dev_priv, pipe);
4839 }
f67a559d 4840
b074cec8 4841 ironlake_pfit_enable(intel_crtc);
f67a559d 4842
9c54c0dd
JB		 4843 /*
4844 * On ILK+ LUT must be loaded before the pipe is running but with
4845 * clocks enabled
4846 */
4847 intel_crtc_load_lut(crtc);
4848
f37fcc2a 4849 intel_update_watermarks(crtc);
e1fdc473 4850 intel_enable_pipe(intel_crtc);
f67a559d 4851
6e3c9717 4852 if (intel_crtc->config->has_pch_encoder)
f67a559d 4853 ironlake_pch_enable(crtc);
c98e9dcf 4854
f9b61ff6
DV		 4855 assert_vblank_disabled(crtc);
4856 drm_crtc_vblank_on(crtc);
4857
fa5c73b1
DV		 4858 for_each_encoder_on_crtc(dev, crtc, encoder)
4859 encoder->enable(encoder);
61b77ddd
DV		 4860
4861 if (HAS_PCH_CPT(dev))
a1520318 4862 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4863}
4864
42db64ef
PZ		 4865/* IPS only exists on ULT machines and is tied to pipe A. */
4866static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4867{
f5adf94e 4868 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4869}
4870
4f771f10
PZ		 4871static void haswell_crtc_enable(struct drm_crtc *crtc)
4872{
4873 struct drm_device *dev = crtc->dev;
4874 struct drm_i915_private *dev_priv = dev->dev_private;
4875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4876 struct intel_encoder *encoder;
99d736a2
ML		 4877 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4878 struct intel_crtc_state *pipe_config =
4879 to_intel_crtc_state(crtc->state);
4f771f10 4880
53d9f4e9 4881 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4882 return;
4883
df8ad70c
DV		 4884 if (intel_crtc_to_shared_dpll(intel_crtc))
4885 intel_enable_shared_dpll(intel_crtc);
4886
6e3c9717 4887 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4888 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4889
4890 intel_set_pipe_timings(intel_crtc);
4891
6e3c9717
ACO		 4892 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4893 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4894 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4895 }
4896
6e3c9717 4897 if (intel_crtc->config->has_pch_encoder) {
229fca97 4898 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4899 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4900 }
4901
4902 haswell_set_pipeconf(crtc);
4903
4904 intel_set_pipe_csc(crtc);
4905
4f771f10 4906 intel_crtc->active = true;
8664281b 4907
a72e4c9f 4908 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4909 for_each_encoder_on_crtc(dev, crtc, encoder)
4910 if (encoder->pre_enable)
4911 encoder->pre_enable(encoder);
4912
6e3c9717 4913 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4914 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4915 true);
4fe9467d
ID		 4916 dev_priv->display.fdi_link_train(crtc);
4917 }
4918
1f544388 4919 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4920
1c132b44 4921 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 4922 skylake_pfit_enable(intel_crtc);
ff6d9f55 4923 else
1c132b44 4924 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4925
4926 /*
4927 * On ILK+ LUT must be loaded before the pipe is running but with
4928 * clocks enabled
4929 */
4930 intel_crtc_load_lut(crtc);
4931
1f544388 4932 intel_ddi_set_pipe_settings(crtc);
8228c251 4933 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4934
f37fcc2a 4935 intel_update_watermarks(crtc);
e1fdc473 4936 intel_enable_pipe(intel_crtc);
42db64ef 4937
6e3c9717 4938 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4939 lpt_pch_enable(crtc);
4f771f10 4940
6e3c9717 4941 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4942 intel_ddi_set_vc_payload_alloc(crtc, true);
4943
f9b61ff6
DV		 4944 assert_vblank_disabled(crtc);
4945 drm_crtc_vblank_on(crtc);
4946
8807e55b 4947 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4948 encoder->enable(encoder);
8807e55b
JN		 4949 intel_opregion_notify_encoder(encoder, true);
4950 }
4f771f10 4951
e4916946
PZ		 4952 /* If we change the relative order between pipe/planes enabling, we need
4953 * to change the workaround. */
99d736a2
ML		 4954 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4955 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4956 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4957 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4958 }
4f771f10
PZ		 4959}
4960
3f8dce3a
DV		 4961static void ironlake_pfit_disable(struct intel_crtc *crtc)
4962{
4963 struct drm_device *dev = crtc->base.dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 int pipe = crtc->pipe;
4966
4967 /* To avoid upsetting the power well on haswell only disable the pfit if
4968 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4969 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4970 I915_WRITE(PF_CTL(pipe), 0);
4971 I915_WRITE(PF_WIN_POS(pipe), 0);
4972 I915_WRITE(PF_WIN_SZ(pipe), 0);
4973 }
4974}
4975
6be4a607
JB		 4976static void ironlake_crtc_disable(struct drm_crtc *crtc)
4977{
4978 struct drm_device *dev = crtc->dev;
4979 struct drm_i915_private *dev_priv = dev->dev_private;
4980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4981 struct intel_encoder *encoder;
6be4a607 4982 int pipe = intel_crtc->pipe;
5eddb70b 4983 u32 reg, temp;
b52eb4dc 4984
ea9d758d
DV		 4985 for_each_encoder_on_crtc(dev, crtc, encoder)
4986 encoder->disable(encoder);
4987
f9b61ff6
DV		 4988 drm_crtc_vblank_off(crtc);
4989 assert_vblank_disabled(crtc);
4990
6e3c9717 4991 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4992 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4993
575f7ab7 4994 intel_disable_pipe(intel_crtc);
32f9d658 4995
3f8dce3a 4996 ironlake_pfit_disable(intel_crtc);
2c07245f 4997
5a74f70a
VS		 4998 if (intel_crtc->config->has_pch_encoder)
4999 ironlake_fdi_disable(crtc);
5000
bf49ec8c
DV		 5001 for_each_encoder_on_crtc(dev, crtc, encoder)
5002 if (encoder->post_disable)
5003 encoder->post_disable(encoder);
2c07245f 5004
6e3c9717 5005 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5006 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5007
d925c59a
DV		 5008 if (HAS_PCH_CPT(dev)) {
5009 /* disable TRANS_DP_CTL */
5010 reg = TRANS_DP_CTL(pipe);
5011 temp = I915_READ(reg);
5012 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5013 TRANS_DP_PORT_SEL_MASK);
5014 temp |= TRANS_DP_PORT_SEL_NONE;
5015 I915_WRITE(reg, temp);
5016
5017 /* disable DPLL_SEL */
5018 temp = I915_READ(PCH_DPLL_SEL);
11887397 5019 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5020 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5021 }
e3421a18 5022
d925c59a
DV		 5023 ironlake_fdi_pll_disable(intel_crtc);
5024 }
e4ca0612
PJ		 5025
5026 intel_crtc->active = false;
5027 intel_update_watermarks(crtc);
6be4a607 5028}
1b3c7a47 5029
4f771f10 5030static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5031{
4f771f10
PZ		 5032 struct drm_device *dev = crtc->dev;
5033 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5035 struct intel_encoder *encoder;
6e3c9717 5036 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5037
8807e55b
JN		 5038 for_each_encoder_on_crtc(dev, crtc, encoder) {
5039 intel_opregion_notify_encoder(encoder, false);
4f771f10 5040 encoder->disable(encoder);
8807e55b 5041 }
4f771f10 5042
f9b61ff6
DV		 5043 drm_crtc_vblank_off(crtc);
5044 assert_vblank_disabled(crtc);
5045
6e3c9717 5046 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5047 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5048 false);
575f7ab7 5049 intel_disable_pipe(intel_crtc);
4f771f10 5050
6e3c9717 5051 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5052 intel_ddi_set_vc_payload_alloc(crtc, false);
5053
ad80a810 5054 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5055
1c132b44 5056 if (INTEL_INFO(dev)->gen >= 9)
e435d6e5 5057 skylake_scaler_disable(intel_crtc);
ff6d9f55 5058 else
1c132b44 5059 ironlake_pfit_disable(intel_crtc);
4f771f10 5060
1f544388 5061 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5062
6e3c9717 5063 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5064 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5065 intel_ddi_fdi_disable(crtc);
83616634 5066 }
4f771f10 5067
97b040aa
ID		 5068 for_each_encoder_on_crtc(dev, crtc, encoder)
5069 if (encoder->post_disable)
5070 encoder->post_disable(encoder);
e4ca0612
PJ		 5071
5072 intel_crtc->active = false;
5073 intel_update_watermarks(crtc);
4f771f10
PZ		 5074}
5075
2dd24552
JB		 5076static void i9xx_pfit_enable(struct intel_crtc *crtc)
5077{
5078 struct drm_device *dev = crtc->base.dev;
5079 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5080 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5081
681a8504 5082 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5083 return;
5084
2dd24552 5085 /*
c0b03411
DV		 5086 * The panel fitter should only be adjusted whilst the pipe is disabled,
5087 * according to register description and PRM.
2dd24552 5088 */
c0b03411
DV		 5089 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5090 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5091
b074cec8
JB		 5092 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5093 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5094
5095 /* Border color in case we don't scale up to the full screen. Black by
5096 * default, change to something else for debugging. */
5097 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5098}
5099
d05410f9
DA		 5100static enum intel_display_power_domain port_to_power_domain(enum port port)
5101{
5102 switch (port) {
5103 case PORT_A:
5104 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5105 case PORT_B:
5106 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5107 case PORT_C:
5108 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5109 case PORT_D:
5110 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
d8e19f99
XZ		 5111 case PORT_E:
5112 return POWER_DOMAIN_PORT_DDI_E_2_LANES;
d05410f9
DA		 5113 default:
5114 WARN_ON_ONCE(1);
5115 return POWER_DOMAIN_PORT_OTHER;
5116 }
5117}
5118
77d22dca
ID		 5119#define for_each_power_domain(domain, mask) \
5120 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5121 if ((1 << (domain)) & (mask))
5122
319be8ae
ID		 5123enum intel_display_power_domain
5124intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5125{
5126 struct drm_device *dev = intel_encoder->base.dev;
5127 struct intel_digital_port *intel_dig_port;
5128
5129 switch (intel_encoder->type) {
5130 case INTEL_OUTPUT_UNKNOWN:
5131 /* Only DDI platforms should ever use this output type */
5132 WARN_ON_ONCE(!HAS_DDI(dev));
5133 case INTEL_OUTPUT_DISPLAYPORT:
5134 case INTEL_OUTPUT_HDMI:
5135 case INTEL_OUTPUT_EDP:
5136 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5137 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5138 case INTEL_OUTPUT_DP_MST:
5139 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5140 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5141 case INTEL_OUTPUT_ANALOG:
5142 return POWER_DOMAIN_PORT_CRT;
5143 case INTEL_OUTPUT_DSI:
5144 return POWER_DOMAIN_PORT_DSI;
5145 default:
5146 return POWER_DOMAIN_PORT_OTHER;
5147 }
5148}
5149
5150static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5151{
319be8ae
ID		 5152 struct drm_device *dev = crtc->dev;
5153 struct intel_encoder *intel_encoder;
5154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5155 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5156 unsigned long mask;
5157 enum transcoder transcoder;
5158
292b990e
ML		 5159 if (!crtc->state->active)
5160 return 0;
5161
77d22dca
ID		 5162 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5163
5164 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5165 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5166 if (intel_crtc->config->pch_pfit.enabled ||
5167 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5168 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5169
319be8ae
ID		 5170 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5171 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5172
77d22dca
ID		 5173 return mask;
5174}
5175
292b990e 5176static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5177{
292b990e
ML		 5178 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5180 enum intel_display_power_domain domain;
5181 unsigned long domains, new_domains, old_domains;
77d22dca 5182
292b990e
ML		 5183 old_domains = intel_crtc->enabled_power_domains;
5184 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5185
292b990e
ML		 5186 domains = new_domains & ~old_domains;
5187
5188 for_each_power_domain(domain, domains)
5189 intel_display_power_get(dev_priv, domain);
5190
5191 return old_domains & ~new_domains;
5192}
5193
5194static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5195 unsigned long domains)
5196{
5197 enum intel_display_power_domain domain;
5198
5199 for_each_power_domain(domain, domains)
5200 intel_display_power_put(dev_priv, domain);
5201}
77d22dca 5202
292b990e
ML		 5203static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5204{
5205 struct drm_device *dev = state->dev;
5206 struct drm_i915_private *dev_priv = dev->dev_private;
5207 unsigned long put_domains[I915_MAX_PIPES] = {};
5208 struct drm_crtc_state *crtc_state;
5209 struct drm_crtc *crtc;
5210 int i;
77d22dca 5211
292b990e
ML		 5212 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5213 if (needs_modeset(crtc->state))
5214 put_domains[to_intel_crtc(crtc)->pipe] =
5215 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5216 }
5217
27c329ed
ML		 5218 if (dev_priv->display.modeset_commit_cdclk) {
5219 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5220
5221 if (cdclk != dev_priv->cdclk_freq &&
5222 !WARN_ON(!state->allow_modeset))
5223 dev_priv->display.modeset_commit_cdclk(state);
5224 }
50f6e502 5225
292b990e
ML		 5226 for (i = 0; i < I915_MAX_PIPES; i++)
5227 if (put_domains[i])
5228 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5229}
5230
adafdc6f
MK		 5231static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5232{
5233 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5234
5235 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5236 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5237 return max_cdclk_freq;
5238 else if (IS_CHERRYVIEW(dev_priv))
5239 return max_cdclk_freq*95/100;
5240 else if (INTEL_INFO(dev_priv)->gen < 4)
5241 return 2*max_cdclk_freq*90/100;
5242 else
5243 return max_cdclk_freq*90/100;
5244}
5245
560a7ae4
DL		 5246static void intel_update_max_cdclk(struct drm_device *dev)
5247{
5248 struct drm_i915_private *dev_priv = dev->dev_private;
5249
5250 if (IS_SKYLAKE(dev)) {
5251 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5252
5253 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5254 dev_priv->max_cdclk_freq = 675000;
5255 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5256 dev_priv->max_cdclk_freq = 540000;
5257 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5258 dev_priv->max_cdclk_freq = 450000;
5259 else
5260 dev_priv->max_cdclk_freq = 337500;
5261 } else if (IS_BROADWELL(dev)) {
5262 /*
5263 * FIXME with extra cooling we can allow
5264 * 540 MHz for ULX and 675 Mhz for ULT.
5265 * How can we know if extra cooling is
5266 * available? PCI ID, VTB, something else?
5267 */
5268 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5269 dev_priv->max_cdclk_freq = 450000;
5270 else if (IS_BDW_ULX(dev))
5271 dev_priv->max_cdclk_freq = 450000;
5272 else if (IS_BDW_ULT(dev))
5273 dev_priv->max_cdclk_freq = 540000;
5274 else
5275 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5276 } else if (IS_CHERRYVIEW(dev)) {
5277 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5278 } else if (IS_VALLEYVIEW(dev)) {
5279 dev_priv->max_cdclk_freq = 400000;
5280 } else {
5281 /* otherwise assume cdclk is fixed */
5282 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5283 }
5284
adafdc6f
MK		 5285 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5286
560a7ae4
DL		 5287 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5288 dev_priv->max_cdclk_freq);
adafdc6f
MK		 5289
5290 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5291 dev_priv->max_dotclk_freq);
560a7ae4
DL		 5292}
5293
5294static void intel_update_cdclk(struct drm_device *dev)
5295{
5296 struct drm_i915_private *dev_priv = dev->dev_private;
5297
5298 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5299 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5300 dev_priv->cdclk_freq);
5301
5302 /*
5303 * Program the gmbus_freq based on the cdclk frequency.
5304 * BSpec erroneously claims we should aim for 4MHz, but
5305 * in fact 1MHz is the correct frequency.
5306 */
5307 if (IS_VALLEYVIEW(dev)) {
5308 /*
5309 * Program the gmbus_freq based on the cdclk frequency.
5310 * BSpec erroneously claims we should aim for 4MHz, but
5311 * in fact 1MHz is the correct frequency.
5312 */
5313 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5314 }
5315
5316 if (dev_priv->max_cdclk_freq == 0)
5317 intel_update_max_cdclk(dev);
5318}
5319
70d0c574 5320static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5321{
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 uint32_t divider;
5324 uint32_t ratio;
5325 uint32_t current_freq;
5326 int ret;
5327
5328 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5329 switch (frequency) {
5330 case 144000:
5331 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5332 ratio = BXT_DE_PLL_RATIO(60);
5333 break;
5334 case 288000:
5335 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5336 ratio = BXT_DE_PLL_RATIO(60);
5337 break;
5338 case 384000:
5339 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5340 ratio = BXT_DE_PLL_RATIO(60);
5341 break;
5342 case 576000:
5343 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5344 ratio = BXT_DE_PLL_RATIO(60);
5345 break;
5346 case 624000:
5347 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5348 ratio = BXT_DE_PLL_RATIO(65);
5349 break;
5350 case 19200:
5351 /*
5352 * Bypass frequency with DE PLL disabled. Init ratio, divider
5353 * to suppress GCC warning.
5354 */
5355 ratio = 0;
5356 divider = 0;
5357 break;
5358 default:
5359 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5360
5361 return;
5362 }
5363
5364 mutex_lock(&dev_priv->rps.hw_lock);
5365 /* Inform power controller of upcoming frequency change */
5366 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5367 0x80000000);
5368 mutex_unlock(&dev_priv->rps.hw_lock);
5369
5370 if (ret) {
5371 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5372 ret, frequency);
5373 return;
5374 }
5375
5376 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5377 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5378 current_freq = current_freq * 500 + 1000;
5379
5380 /*
5381 * DE PLL has to be disabled when
5382 * - setting to 19.2MHz (bypass, PLL isn't used)
5383 * - before setting to 624MHz (PLL needs toggling)
5384 * - before setting to any frequency from 624MHz (PLL needs toggling)
5385 */
5386 if (frequency == 19200 || frequency == 624000 ||
5387 current_freq == 624000) {
5388 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5389 /* Timeout 200us */
5390 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5391 1))
5392 DRM_ERROR("timout waiting for DE PLL unlock\n");
5393 }
5394
5395 if (frequency != 19200) {
5396 uint32_t val;
5397
5398 val = I915_READ(BXT_DE_PLL_CTL);
5399 val &= ~BXT_DE_PLL_RATIO_MASK;
5400 val |= ratio;
5401 I915_WRITE(BXT_DE_PLL_CTL, val);
5402
5403 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5404 /* Timeout 200us */
5405 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5406 DRM_ERROR("timeout waiting for DE PLL lock\n");
5407
5408 val = I915_READ(CDCLK_CTL);
5409 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5410 val |= divider;
5411 /*
5412 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5413 * enable otherwise.
5414 */
5415 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5416 if (frequency >= 500000)
5417 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5418
5419 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5420 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5421 val |= (frequency - 1000) / 500;
5422 I915_WRITE(CDCLK_CTL, val);
5423 }
5424
5425 mutex_lock(&dev_priv->rps.hw_lock);
5426 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5427 DIV_ROUND_UP(frequency, 25000));
5428 mutex_unlock(&dev_priv->rps.hw_lock);
5429
5430 if (ret) {
5431 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5432 ret, frequency);
5433 return;
5434 }
5435
a47871bd 5436 intel_update_cdclk(dev);
f8437dd1
VK		 5437}
5438
5439void broxton_init_cdclk(struct drm_device *dev)
5440{
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442 uint32_t val;
5443
5444 /*
5445 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5446 * or else the reset will hang because there is no PCH to respond.
5447 * Move the handshake programming to initialization sequence.
5448 * Previously was left up to BIOS.
5449 */
5450 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5451 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5452 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5453
5454 /* Enable PG1 for cdclk */
5455 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5456
5457 /* check if cd clock is enabled */
5458 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5459 DRM_DEBUG_KMS("Display already initialized\n");
5460 return;
5461 }
5462
5463 /*
5464 * FIXME:
5465 * - The initial CDCLK needs to be read from VBT.
5466 * Need to make this change after VBT has changes for BXT.
5467 * - check if setting the max (or any) cdclk freq is really necessary
5468 * here, it belongs to modeset time
5469 */
5470 broxton_set_cdclk(dev, 624000);
5471
5472 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5473 POSTING_READ(DBUF_CTL);
5474
f8437dd1
VK		 5475 udelay(10);
5476
5477 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5478 DRM_ERROR("DBuf power enable timeout!\n");
5479}
5480
5481void broxton_uninit_cdclk(struct drm_device *dev)
5482{
5483 struct drm_i915_private *dev_priv = dev->dev_private;
5484
5485 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5486 POSTING_READ(DBUF_CTL);
5487
f8437dd1
VK		 5488 udelay(10);
5489
5490 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5491 DRM_ERROR("DBuf power disable timeout!\n");
5492
5493 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5494 broxton_set_cdclk(dev, 19200);
5495
5496 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5497}
5498
5d96d8af
DL		 5499static const struct skl_cdclk_entry {
5500 unsigned int freq;
5501 unsigned int vco;
5502} skl_cdclk_frequencies[] = {
5503 { .freq = 308570, .vco = 8640 },
5504 { .freq = 337500, .vco = 8100 },
5505 { .freq = 432000, .vco = 8640 },
5506 { .freq = 450000, .vco = 8100 },
5507 { .freq = 540000, .vco = 8100 },
5508 { .freq = 617140, .vco = 8640 },
5509 { .freq = 675000, .vco = 8100 },
5510};
5511
5512static unsigned int skl_cdclk_decimal(unsigned int freq)
5513{
5514 return (freq - 1000) / 500;
5515}
5516
5517static unsigned int skl_cdclk_get_vco(unsigned int freq)
5518{
5519 unsigned int i;
5520
5521 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5522 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5523
5524 if (e->freq == freq)
5525 return e->vco;
5526 }
5527
5528 return 8100;
5529}
5530
5531static void
5532skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5533{
5534 unsigned int min_freq;
5535 u32 val;
5536
5537 /* select the minimum CDCLK before enabling DPLL 0 */
5538 val = I915_READ(CDCLK_CTL);
5539 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5540 val |= CDCLK_FREQ_337_308;
5541
5542 if (required_vco == 8640)
5543 min_freq = 308570;
5544 else
5545 min_freq = 337500;
5546
5547 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5548
5549 I915_WRITE(CDCLK_CTL, val);
5550 POSTING_READ(CDCLK_CTL);
5551
5552 /*
5553 * We always enable DPLL0 with the lowest link rate possible, but still
5554 * taking into account the VCO required to operate the eDP panel at the
5555 * desired frequency. The usual DP link rates operate with a VCO of
5556 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5557 * The modeset code is responsible for the selection of the exact link
5558 * rate later on, with the constraint of choosing a frequency that
5559 * works with required_vco.
5560 */
5561 val = I915_READ(DPLL_CTRL1);
5562
5563 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5564 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5565 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5566 if (required_vco == 8640)
5567 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5568 SKL_DPLL0);
5569 else
5570 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5571 SKL_DPLL0);
5572
5573 I915_WRITE(DPLL_CTRL1, val);
5574 POSTING_READ(DPLL_CTRL1);
5575
5576 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5577
5578 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5579 DRM_ERROR("DPLL0 not locked\n");
5580}
5581
5582static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5583{
5584 int ret;
5585 u32 val;
5586
5587 /* inform PCU we want to change CDCLK */
5588 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5589 mutex_lock(&dev_priv->rps.hw_lock);
5590 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5591 mutex_unlock(&dev_priv->rps.hw_lock);
5592
5593 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5594}
5595
5596static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5597{
5598 unsigned int i;
5599
5600 for (i = 0; i < 15; i++) {
5601 if (skl_cdclk_pcu_ready(dev_priv))
5602 return true;
5603 udelay(10);
5604 }
5605
5606 return false;
5607}
5608
5609static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5610{
560a7ae4 5611 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5612 u32 freq_select, pcu_ack;
5613
5614 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5615
5616 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5617 DRM_ERROR("failed to inform PCU about cdclk change\n");
5618 return;
5619 }
5620
5621 /* set CDCLK_CTL */
5622 switch(freq) {
5623 case 450000:
5624 case 432000:
5625 freq_select = CDCLK_FREQ_450_432;
5626 pcu_ack = 1;
5627 break;
5628 case 540000:
5629 freq_select = CDCLK_FREQ_540;
5630 pcu_ack = 2;
5631 break;
5632 case 308570:
5633 case 337500:
5634 default:
5635 freq_select = CDCLK_FREQ_337_308;
5636 pcu_ack = 0;
5637 break;
5638 case 617140:
5639 case 675000:
5640 freq_select = CDCLK_FREQ_675_617;
5641 pcu_ack = 3;
5642 break;
5643 }
5644
5645 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5646 POSTING_READ(CDCLK_CTL);
5647
5648 /* inform PCU of the change */
5649 mutex_lock(&dev_priv->rps.hw_lock);
5650 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5651 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5652
5653 intel_update_cdclk(dev);
5d96d8af
DL		 5654}
5655
5656void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5657{
5658 /* disable DBUF power */
5659 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5660 POSTING_READ(DBUF_CTL);
5661
5662 udelay(10);
5663
5664 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5665 DRM_ERROR("DBuf power disable timeout\n");
5666
5667 /* disable DPLL0 */
5668 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5669 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5670 DRM_ERROR("Couldn't disable DPLL0\n");
5671
5672 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5673}
5674
5675void skl_init_cdclk(struct drm_i915_private *dev_priv)
5676{
5677 u32 val;
5678 unsigned int required_vco;
5679
5680 /* enable PCH reset handshake */
5681 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5682 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5683
5684 /* enable PG1 and Misc I/O */
5685 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5686
39d9b85a
GW		 5687 /* DPLL0 not enabled (happens on early BIOS versions) */
5688 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5689 /* enable DPLL0 */
5690 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5691 skl_dpll0_enable(dev_priv, required_vco);
5d96d8af
DL		 5692 }
5693
5d96d8af
DL		 5694 /* set CDCLK to the frequency the BIOS chose */
5695 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5696
5697 /* enable DBUF power */
5698 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5699 POSTING_READ(DBUF_CTL);
5700
5701 udelay(10);
5702
5703 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5704 DRM_ERROR("DBuf power enable timeout\n");
5705}
5706
dfcab17e 5707/* returns HPLL frequency in kHz */
f8bf63fd 5708static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5709{
586f49dc 5710 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5711
586f49dc 5712 /* Obtain SKU information */
a580516d 5713 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5714 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5715 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5716 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5717
dfcab17e 5718 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5719}
5720
5721/* Adjust CDclk dividers to allow high res or save power if possible */
5722static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5723{
5724 struct drm_i915_private *dev_priv = dev->dev_private;
5725 u32 val, cmd;
5726
164dfd28
VK		 5727 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5728 != dev_priv->cdclk_freq);
d60c4473 5729
dfcab17e 5730 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5731 cmd = 2;
dfcab17e 5732 else if (cdclk == 266667)
30a970c6
JB		 5733 cmd = 1;
5734 else
5735 cmd = 0;
5736
5737 mutex_lock(&dev_priv->rps.hw_lock);
5738 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5739 val &= ~DSPFREQGUAR_MASK;
5740 val |= (cmd << DSPFREQGUAR_SHIFT);
5741 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5742 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5743 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5744 50)) {
5745 DRM_ERROR("timed out waiting for CDclk change\n");
5746 }
5747 mutex_unlock(&dev_priv->rps.hw_lock);
5748
54433e91
VS		 5749 mutex_lock(&dev_priv->sb_lock);
5750
dfcab17e 5751 if (cdclk == 400000) {
6bcda4f0 5752 u32 divider;
30a970c6 5753
6bcda4f0 5754 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5755
30a970c6
JB		 5756 /* adjust cdclk divider */
5757 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5758 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5759 val |= divider;
5760 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5761
5762 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5763 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5764 50))
5765 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5766 }
5767
30a970c6
JB		 5768 /* adjust self-refresh exit latency value */
5769 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5770 val &= ~0x7f;
5771
5772 /*
5773 * For high bandwidth configs, we set a higher latency in the bunit
5774 * so that the core display fetch happens in time to avoid underruns.
5775 */
dfcab17e 5776 if (cdclk == 400000)
30a970c6
JB		 5777 val |= 4500 / 250; /* 4.5 usec */
5778 else
5779 val |= 3000 / 250; /* 3.0 usec */
5780 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5781
a580516d 5782 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5783
b6283055 5784 intel_update_cdclk(dev);
30a970c6
JB		 5785}
5786
383c5a6a
VS		 5787static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5788{
5789 struct drm_i915_private *dev_priv = dev->dev_private;
5790 u32 val, cmd;
5791
164dfd28
VK		 5792 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5793 != dev_priv->cdclk_freq);
383c5a6a
VS		 5794
5795 switch (cdclk) {
383c5a6a
VS		 5796 case 333333:
5797 case 320000:
383c5a6a 5798 case 266667:
383c5a6a 5799 case 200000:
383c5a6a
VS		 5800 break;
5801 default:
5f77eeb0 5802 MISSING_CASE(cdclk);
383c5a6a
VS		 5803 return;
5804 }
5805
9d0d3fda
VS		 5806 /*
5807 * Specs are full of misinformation, but testing on actual
5808 * hardware has shown that we just need to write the desired
5809 * CCK divider into the Punit register.
5810 */
5811 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5812
383c5a6a
VS		 5813 mutex_lock(&dev_priv->rps.hw_lock);
5814 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5815 val &= ~DSPFREQGUAR_MASK_CHV;
5816 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5817 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5818 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5819 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5820 50)) {
5821 DRM_ERROR("timed out waiting for CDclk change\n");
5822 }
5823 mutex_unlock(&dev_priv->rps.hw_lock);
5824
b6283055 5825 intel_update_cdclk(dev);
383c5a6a
VS		 5826}
5827
30a970c6
JB		 5828static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5829 int max_pixclk)
5830{
6bcda4f0 5831 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5832 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5833
30a970c6
JB		 5834 /*
5835 * Really only a few cases to deal with, as only 4 CDclks are supported:
5836 * 200MHz
5837 * 267MHz
29dc7ef3 5838 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5839 * 400MHz (VLV only)
5840 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5841 * of the lower bin and adjust if needed.
e37c67a1
VS		 5842 *
5843 * We seem to get an unstable or solid color picture at 200MHz.
5844 * Not sure what's wrong. For now use 200MHz only when all pipes
5845 * are off.
30a970c6 5846 */
6cca3195
VS		 5847 if (!IS_CHERRYVIEW(dev_priv) &&
5848 max_pixclk > freq_320*limit/100)
dfcab17e 5849 return 400000;
6cca3195 5850 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5851 return freq_320;
e37c67a1 5852 else if (max_pixclk > 0)
dfcab17e 5853 return 266667;
e37c67a1
VS		 5854 else
5855 return 200000;
30a970c6
JB		 5856}
5857
f8437dd1
VK		 5858static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5859 int max_pixclk)
5860{
5861 /*
5862 * FIXME:
5863 * - remove the guardband, it's not needed on BXT
5864 * - set 19.2MHz bypass frequency if there are no active pipes
5865 */
5866 if (max_pixclk > 576000*9/10)
5867 return 624000;
5868 else if (max_pixclk > 384000*9/10)
5869 return 576000;
5870 else if (max_pixclk > 288000*9/10)
5871 return 384000;
5872 else if (max_pixclk > 144000*9/10)
5873 return 288000;
5874 else
5875 return 144000;
5876}
5877
a821fc46
ACO		 5878/* Compute the max pixel clock for new configuration. Uses atomic state if
5879 * that's non-NULL, look at current state otherwise. */
5880static int intel_mode_max_pixclk(struct drm_device *dev,
5881 struct drm_atomic_state *state)
30a970c6 5882{
30a970c6 5883 struct intel_crtc *intel_crtc;
304603f4 5884 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5885 int max_pixclk = 0;
5886
d3fcc808 5887 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5888 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5889 if (IS_ERR(crtc_state))
5890 return PTR_ERR(crtc_state);
5891
5892 if (!crtc_state->base.enable)
5893 continue;
5894
5895 max_pixclk = max(max_pixclk,
5896 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5897 }
5898
5899 return max_pixclk;
5900}
5901
27c329ed 5902static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5903{
27c329ed
ML		 5904 struct drm_device *dev = state->dev;
5905 struct drm_i915_private *dev_priv = dev->dev_private;
5906 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5907
304603f4
ACO		 5908 if (max_pixclk < 0)
5909 return max_pixclk;
30a970c6 5910
27c329ed
ML		 5911 to_intel_atomic_state(state)->cdclk =
5912 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5913
27c329ed
ML		 5914 return 0;
5915}
304603f4 5916
27c329ed
ML		 5917static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5918{
5919 struct drm_device *dev = state->dev;
5920 struct drm_i915_private *dev_priv = dev->dev_private;
5921 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5922
27c329ed
ML		 5923 if (max_pixclk < 0)
5924 return max_pixclk;
85a96e7a 5925
27c329ed
ML		 5926 to_intel_atomic_state(state)->cdclk =
5927 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5928
27c329ed 5929 return 0;
30a970c6
JB		 5930}
5931
1e69cd74
VS		 5932static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5933{
5934 unsigned int credits, default_credits;
5935
5936 if (IS_CHERRYVIEW(dev_priv))
5937 default_credits = PFI_CREDIT(12);
5938 else
5939 default_credits = PFI_CREDIT(8);
5940
164dfd28 5941 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5942 /* CHV suggested value is 31 or 63 */
5943 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5944 credits = PFI_CREDIT_63;
1e69cd74
VS		 5945 else
5946 credits = PFI_CREDIT(15);
5947 } else {
5948 credits = default_credits;
5949 }
5950
5951 /*
5952 * WA - write default credits before re-programming
5953 * FIXME: should we also set the resend bit here?
5954 */
5955 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5956 default_credits);
5957
5958 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5959 credits | PFI_CREDIT_RESEND);
5960
5961 /*
5962 * FIXME is this guaranteed to clear
5963 * immediately or should we poll for it?
5964 */
5965 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5966}
5967
27c329ed 5968static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5969{
a821fc46 5970 struct drm_device *dev = old_state->dev;
27c329ed 5971 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5972 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5973
27c329ed
ML		 5974 /*
5975 * FIXME: We can end up here with all power domains off, yet
5976 * with a CDCLK frequency other than the minimum. To account
5977 * for this take the PIPE-A power domain, which covers the HW
5978 * blocks needed for the following programming. This can be
5979 * removed once it's guaranteed that we get here either with
5980 * the minimum CDCLK set, or the required power domains
5981 * enabled.
5982 */
5983 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5984
27c329ed
ML		 5985 if (IS_CHERRYVIEW(dev))
5986 cherryview_set_cdclk(dev, req_cdclk);
5987 else
5988 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5989
27c329ed 5990 vlv_program_pfi_credits(dev_priv);
1e69cd74 5991
27c329ed 5992 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 5993}
5994
89b667f8
JB		 5995static void valleyview_crtc_enable(struct drm_crtc *crtc)
5996{
5997 struct drm_device *dev = crtc->dev;
a72e4c9f 5998 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000 struct intel_encoder *encoder;
6001 int pipe = intel_crtc->pipe;
23538ef1 6002 bool is_dsi;
89b667f8 6003
53d9f4e9 6004 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6005 return;
6006
409ee761 6007 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6008
6e3c9717 6009 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6010 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6011
6012 intel_set_pipe_timings(intel_crtc);
6013
c14b0485
VS		 6014 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6015 struct drm_i915_private *dev_priv = dev->dev_private;
6016
6017 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6018 I915_WRITE(CHV_CANVAS(pipe), 0);
6019 }
6020
5b18e57c
DV		 6021 i9xx_set_pipeconf(intel_crtc);
6022
89b667f8 6023 intel_crtc->active = true;
89b667f8 6024
a72e4c9f 6025 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6026
89b667f8
JB		 6027 for_each_encoder_on_crtc(dev, crtc, encoder)
6028 if (encoder->pre_pll_enable)
6029 encoder->pre_pll_enable(encoder);
6030
9d556c99 6031 if (!is_dsi) {
c0b4c660
VS		 6032 if (IS_CHERRYVIEW(dev)) {
6033 chv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6034 chv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660
VS		 6035 } else {
6036 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6e3c9717 6037 vlv_enable_pll(intel_crtc, intel_crtc->config);
c0b4c660 6038 }
9d556c99 6039 }
89b667f8
JB		 6040
6041 for_each_encoder_on_crtc(dev, crtc, encoder)
6042 if (encoder->pre_enable)
6043 encoder->pre_enable(encoder);
6044
2dd24552
JB		 6045 i9xx_pfit_enable(intel_crtc);
6046
63cbb074
VS		 6047 intel_crtc_load_lut(crtc);
6048
e1fdc473 6049 intel_enable_pipe(intel_crtc);
be6a6f8e 6050
4b3a9526
VS		 6051 assert_vblank_disabled(crtc);
6052 drm_crtc_vblank_on(crtc);
6053
f9b61ff6
DV		 6054 for_each_encoder_on_crtc(dev, crtc, encoder)
6055 encoder->enable(encoder);
89b667f8
JB		 6056}
6057
f13c2ef3
DV		 6058static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6059{
6060 struct drm_device *dev = crtc->base.dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062
6e3c9717
ACO		 6063 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6064 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6065}
6066
0b8765c6 6067static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6068{
6069 struct drm_device *dev = crtc->dev;
a72e4c9f 6070 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6072 struct intel_encoder *encoder;
79e53945 6073 int pipe = intel_crtc->pipe;
79e53945 6074
53d9f4e9 6075 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6076 return;
6077
f13c2ef3
DV		 6078 i9xx_set_pll_dividers(intel_crtc);
6079
6e3c9717 6080 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6081 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6082
6083 intel_set_pipe_timings(intel_crtc);
6084
5b18e57c
DV		 6085 i9xx_set_pipeconf(intel_crtc);
6086
f7abfe8b 6087 intel_crtc->active = true;
6b383a7f 6088
4a3436e8 6089 if (!IS_GEN2(dev))
a72e4c9f 6090 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6091
9d6d9f19
MK		 6092 for_each_encoder_on_crtc(dev, crtc, encoder)
6093 if (encoder->pre_enable)
6094 encoder->pre_enable(encoder);
6095
f6736a1a
DV		 6096 i9xx_enable_pll(intel_crtc);
6097
2dd24552
JB		 6098 i9xx_pfit_enable(intel_crtc);
6099
63cbb074
VS		 6100 intel_crtc_load_lut(crtc);
6101
f37fcc2a 6102 intel_update_watermarks(crtc);
e1fdc473 6103 intel_enable_pipe(intel_crtc);
be6a6f8e 6104
4b3a9526
VS		 6105 assert_vblank_disabled(crtc);
6106 drm_crtc_vblank_on(crtc);
6107
f9b61ff6
DV		 6108 for_each_encoder_on_crtc(dev, crtc, encoder)
6109 encoder->enable(encoder);
0b8765c6 6110}
79e53945 6111
87476d63
DV		 6112static void i9xx_pfit_disable(struct intel_crtc *crtc)
6113{
6114 struct drm_device *dev = crtc->base.dev;
6115 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6116
6e3c9717 6117 if (!crtc->config->gmch_pfit.control)
328d8e82 6118 return;
87476d63 6119
328d8e82 6120 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6121
328d8e82
DV		 6122 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6123 I915_READ(PFIT_CONTROL));
6124 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6125}
6126
0b8765c6
JB		 6127static void i9xx_crtc_disable(struct drm_crtc *crtc)
6128{
6129 struct drm_device *dev = crtc->dev;
6130 struct drm_i915_private *dev_priv = dev->dev_private;
6131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6132 struct intel_encoder *encoder;
0b8765c6 6133 int pipe = intel_crtc->pipe;
ef9c3aee 6134
6304cd91
VS		 6135 /*
6136 * On gen2 planes are double buffered but the pipe isn't, so we must
6137 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6138 * We also need to wait on all gmch platforms because of the
6139 * self-refresh mode constraint explained above.
6304cd91 6140 */
564ed191 6141 intel_wait_for_vblank(dev, pipe);
6304cd91 6142
4b3a9526
VS		 6143 for_each_encoder_on_crtc(dev, crtc, encoder)
6144 encoder->disable(encoder);
6145
f9b61ff6
DV		 6146 drm_crtc_vblank_off(crtc);
6147 assert_vblank_disabled(crtc);
6148
575f7ab7 6149 intel_disable_pipe(intel_crtc);
24a1f16d 6150
87476d63 6151 i9xx_pfit_disable(intel_crtc);
24a1f16d 6152
89b667f8
JB		 6153 for_each_encoder_on_crtc(dev, crtc, encoder)
6154 if (encoder->post_disable)
6155 encoder->post_disable(encoder);
6156
409ee761 6157 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6158 if (IS_CHERRYVIEW(dev))
6159 chv_disable_pll(dev_priv, pipe);
6160 else if (IS_VALLEYVIEW(dev))
6161 vlv_disable_pll(dev_priv, pipe);
6162 else
1c4e0274 6163 i9xx_disable_pll(intel_crtc);
076ed3b2 6164 }
0b8765c6 6165
d6db995f
VS		 6166 for_each_encoder_on_crtc(dev, crtc, encoder)
6167 if (encoder->post_pll_disable)
6168 encoder->post_pll_disable(encoder);
6169
4a3436e8 6170 if (!IS_GEN2(dev))
a72e4c9f 6171 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6172
6173 intel_crtc->active = false;
6174 intel_update_watermarks(crtc);
0b8765c6
JB		 6175}
6176
b17d48e2
ML		 6177static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6178{
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6181 enum intel_display_power_domain domain;
6182 unsigned long domains;
6183
6184 if (!intel_crtc->active)
6185 return;
6186
a539205a
ML		 6187 if (to_intel_plane_state(crtc->primary->state)->visible) {
6188 intel_crtc_wait_for_pending_flips(crtc);
6189 intel_pre_disable_primary(crtc);
6190 }
6191
d032ffa0 6192 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6193 dev_priv->display.crtc_disable(crtc);
1f7457b1 6194 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6195
6196 domains = intel_crtc->enabled_power_domains;
6197 for_each_power_domain(domain, domains)
6198 intel_display_power_put(dev_priv, domain);
6199 intel_crtc->enabled_power_domains = 0;
6200}
6201
6b72d486
ML		 6202/*
6203 * turn all crtc's off, but do not adjust state
6204 * This has to be paired with a call to intel_modeset_setup_hw_state.
6205 */
70e0bd74 6206int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6207{
70e0bd74
ML		 6208 struct drm_mode_config *config = &dev->mode_config;
6209 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6210 struct drm_atomic_state *state;
6b72d486 6211 struct drm_crtc *crtc;
70e0bd74
ML		 6212 unsigned crtc_mask = 0;
6213 int ret = 0;
6214
6215 if (WARN_ON(!ctx))
6216 return 0;
6217
6218 lockdep_assert_held(&ctx->ww_ctx);
6219 state = drm_atomic_state_alloc(dev);
6220 if (WARN_ON(!state))
6221 return -ENOMEM;
6222
6223 state->acquire_ctx = ctx;
6224 state->allow_modeset = true;
6225
6226 for_each_crtc(dev, crtc) {
6227 struct drm_crtc_state *crtc_state =
6228 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6229
70e0bd74
ML		 6230 ret = PTR_ERR_OR_ZERO(crtc_state);
6231 if (ret)
6232 goto free;
6233
6234 if (!crtc_state->active)
6235 continue;
6236
6237 crtc_state->active = false;
6238 crtc_mask |= 1 << drm_crtc_index(crtc);
6239 }
6240
6241 if (crtc_mask) {
74c090b1 6242 ret = drm_atomic_commit(state);
70e0bd74
ML		 6243
6244 if (!ret) {
6245 for_each_crtc(dev, crtc)
6246 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6247 crtc->state->active = true;
6248
6249 return ret;
6250 }
6251 }
6252
6253free:
6254 if (ret)
6255 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6256 drm_atomic_state_free(state);
6257 return ret;
ee7b9f93
JB		 6258}
6259
ea5b213a 6260void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6261{
4ef69c7a 6262 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6263
ea5b213a
CW		 6264 drm_encoder_cleanup(encoder);
6265 kfree(intel_encoder);
7e7d76c3
JB		 6266}
6267
0a91ca29
DV		 6268/* Cross check the actual hw state with our own modeset state tracking (and it's
6269 * internal consistency). */
b980514c 6270static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6271{
35dd3c64
ML		 6272 struct drm_crtc *crtc = connector->base.state->crtc;
6273
6274 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6275 connector->base.base.id,
6276 connector->base.name);
6277
0a91ca29 6278 if (connector->get_hw_state(connector)) {
35dd3c64
ML		 6279 struct drm_encoder *encoder = &connector->encoder->base;
6280 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 6281
35dd3c64
ML		 6282 I915_STATE_WARN(!crtc,
6283 "connector enabled without attached crtc\n");
0a91ca29 6284
35dd3c64
ML		 6285 if (!crtc)
6286 return;
6287
6288 I915_STATE_WARN(!crtc->state->active,
6289 "connector is active, but attached crtc isn't\n");
6290
6291 if (!encoder)
6292 return;
6293
6294 I915_STATE_WARN(conn_state->best_encoder != encoder,
6295 "atomic encoder doesn't match attached encoder\n");
6296
6297 I915_STATE_WARN(conn_state->crtc != encoder->crtc,
6298 "attached encoder crtc differs from connector crtc\n");
6299 } else {
4d688a2a
ML		 6300 I915_STATE_WARN(crtc && crtc->state->active,
6301 "attached crtc is active, but connector isn't\n");
35dd3c64
ML		 6302 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6303 "best encoder set without crtc!\n");
0a91ca29 6304 }
79e53945
JB		 6305}
6306
08d9bc92
ACO		 6307int intel_connector_init(struct intel_connector *connector)
6308{
6309 struct drm_connector_state *connector_state;
6310
6311 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6312 if (!connector_state)
6313 return -ENOMEM;
6314
6315 connector->base.state = connector_state;
6316 return 0;
6317}
6318
6319struct intel_connector *intel_connector_alloc(void)
6320{
6321 struct intel_connector *connector;
6322
6323 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6324 if (!connector)
6325 return NULL;
6326
6327 if (intel_connector_init(connector) < 0) {
6328 kfree(connector);
6329 return NULL;
6330 }
6331
6332 return connector;
6333}
6334
f0947c37
DV		 6335/* Simple connector->get_hw_state implementation for encoders that support only
6336 * one connector and no cloning and hence the encoder state determines the state
6337 * of the connector. */
6338bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6339{
24929352 6340 enum pipe pipe = 0;
f0947c37 6341 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6342
f0947c37 6343 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6344}
6345
6d293983 6346static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6347{
6d293983
ACO		 6348 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6349 return crtc_state->fdi_lanes;
d272ddfa
VS		 6350
6351 return 0;
6352}
6353
6d293983 6354static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6355 struct intel_crtc_state *pipe_config)
1857e1da 6356{
6d293983
ACO		 6357 struct drm_atomic_state *state = pipe_config->base.state;
6358 struct intel_crtc *other_crtc;
6359 struct intel_crtc_state *other_crtc_state;
6360
1857e1da
DV		 6361 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6362 pipe_name(pipe), pipe_config->fdi_lanes);
6363 if (pipe_config->fdi_lanes > 4) {
6364 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6365 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6366 return -EINVAL;
1857e1da
DV		 6367 }
6368
bafb6553 6369 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6370 if (pipe_config->fdi_lanes > 2) {
6371 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6372 pipe_config->fdi_lanes);
6d293983 6373 return -EINVAL;
1857e1da 6374 } else {
6d293983 6375 return 0;
1857e1da
DV		 6376 }
6377 }
6378
6379 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6380 return 0;
1857e1da
DV		 6381
6382 /* Ivybridge 3 pipe is really complicated */
6383 switch (pipe) {
6384 case PIPE_A:
6d293983 6385 return 0;
1857e1da 6386 case PIPE_B:
6d293983
ACO		 6387 if (pipe_config->fdi_lanes <= 2)
6388 return 0;
6389
6390 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6391 other_crtc_state =
6392 intel_atomic_get_crtc_state(state, other_crtc);
6393 if (IS_ERR(other_crtc_state))
6394 return PTR_ERR(other_crtc_state);
6395
6396 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6397 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6398 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6399 return -EINVAL;
1857e1da 6400 }
6d293983 6401 return 0;
1857e1da 6402 case PIPE_C:
251cc67c
VS		 6403 if (pipe_config->fdi_lanes > 2) {
6404 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6405 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6406 return -EINVAL;
251cc67c 6407 }
6d293983
ACO		 6408
6409 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6410 other_crtc_state =
6411 intel_atomic_get_crtc_state(state, other_crtc);
6412 if (IS_ERR(other_crtc_state))
6413 return PTR_ERR(other_crtc_state);
6414
6415 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6416 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6417 return -EINVAL;
1857e1da 6418 }
6d293983 6419 return 0;
1857e1da
DV		 6420 default:
6421 BUG();
6422 }
6423}
6424
e29c22c0
DV		 6425#define RETRY 1
6426static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6427 struct intel_crtc_state *pipe_config)
877d48d5 6428{
1857e1da 6429 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6430 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6431 int lane, link_bw, fdi_dotclock, ret;
6432 bool needs_recompute = false;
877d48d5 6433
e29c22c0 6434retry:
877d48d5
DV		 6435 /* FDI is a binary signal running at ~2.7GHz, encoding
6436 * each output octet as 10 bits. The actual frequency
6437 * is stored as a divider into a 100MHz clock, and the
6438 * mode pixel clock is stored in units of 1KHz.
6439 * Hence the bw of each lane in terms of the mode signal
6440 * is:
6441 */
6442 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6443
241bfc38 6444 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6445
2bd89a07 6446 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6447 pipe_config->pipe_bpp);
6448
6449 pipe_config->fdi_lanes = lane;
6450
2bd89a07 6451 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6452 link_bw, &pipe_config->fdi_m_n);
1857e1da 6453
6d293983
ACO		 6454 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6455 intel_crtc->pipe, pipe_config);
6456 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6457 pipe_config->pipe_bpp -= 2*3;
6458 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6459 pipe_config->pipe_bpp);
6460 needs_recompute = true;
6461 pipe_config->bw_constrained = true;
6462
6463 goto retry;
6464 }
6465
6466 if (needs_recompute)
6467 return RETRY;
6468
6d293983 6469 return ret;
877d48d5
DV		 6470}
6471
8cfb3407
VS		 6472static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6473 struct intel_crtc_state *pipe_config)
6474{
6475 if (pipe_config->pipe_bpp > 24)
6476 return false;
6477
6478 /* HSW can handle pixel rate up to cdclk? */
6479 if (IS_HASWELL(dev_priv->dev))
6480 return true;
6481
6482 /*
b432e5cf
VS		 6483 * We compare against max which means we must take
6484 * the increased cdclk requirement into account when
6485 * calculating the new cdclk.
6486 *
6487 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6488 */
6489 return ilk_pipe_pixel_rate(pipe_config) <=
6490 dev_priv->max_cdclk_freq * 95 / 100;
6491}
6492
42db64ef 6493static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6494 struct intel_crtc_state *pipe_config)
42db64ef 6495{
8cfb3407
VS		 6496 struct drm_device *dev = crtc->base.dev;
6497 struct drm_i915_private *dev_priv = dev->dev_private;
6498
d330a953 6499 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6500 hsw_crtc_supports_ips(crtc) &&
6501 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6502}
6503
a43f6e0f 6504static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6505 struct intel_crtc_state *pipe_config)
79e53945 6506{
a43f6e0f 6507 struct drm_device *dev = crtc->base.dev;
8bd31e67 6508 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6509 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6510
ad3a4479 6511 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6512 if (INTEL_INFO(dev)->gen < 4) {
44913155 6513 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6514
6515 /*
6516 * Enable pixel doubling when the dot clock
6517 * is > 90% of the (display) core speed.
6518 *
b397c96b
VS		 6519 * GDG double wide on either pipe,
6520 * otherwise pipe A only.
cf532bb2 6521 */
b397c96b 6522 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6523 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6524 clock_limit *= 2;
cf532bb2 6525 pipe_config->double_wide = true;
ad3a4479
VS		 6526 }
6527
241bfc38 6528 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6529 return -EINVAL;
2c07245f 6530 }
89749350 6531
1d1d0e27
VS		 6532 /*
6533 * Pipe horizontal size must be even in:
6534 * - DVO ganged mode
6535 * - LVDS dual channel mode
6536 * - Double wide pipe
6537 */
a93e255f 6538 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6539 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6540 pipe_config->pipe_src_w &= ~1;
6541
8693a824
DL		 6542 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6543 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6544 */
6545 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6546 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6547 return -EINVAL;
44f46b42 6548
f5adf94e 6549 if (HAS_IPS(dev))
a43f6e0f
DV		 6550 hsw_compute_ips_config(crtc, pipe_config);
6551
877d48d5 6552 if (pipe_config->has_pch_encoder)
a43f6e0f 6553 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6554
cf5a15be 6555 return 0;
79e53945
JB		 6556}
6557
1652d19e
VS		 6558static int skylake_get_display_clock_speed(struct drm_device *dev)
6559{
6560 struct drm_i915_private *dev_priv = to_i915(dev);
6561 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6562 uint32_t cdctl = I915_READ(CDCLK_CTL);
6563 uint32_t linkrate;
6564
414355a7 6565 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6566 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6567
6568 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6569 return 540000;
6570
6571 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6572 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6573
71cd8423
DL		 6574 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6575 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6576 /* vco 8640 */
6577 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6578 case CDCLK_FREQ_450_432:
6579 return 432000;
6580 case CDCLK_FREQ_337_308:
6581 return 308570;
6582 case CDCLK_FREQ_675_617:
6583 return 617140;
6584 default:
6585 WARN(1, "Unknown cd freq selection\n");
6586 }
6587 } else {
6588 /* vco 8100 */
6589 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6590 case CDCLK_FREQ_450_432:
6591 return 450000;
6592 case CDCLK_FREQ_337_308:
6593 return 337500;
6594 case CDCLK_FREQ_675_617:
6595 return 675000;
6596 default:
6597 WARN(1, "Unknown cd freq selection\n");
6598 }
6599 }
6600
6601 /* error case, do as if DPLL0 isn't enabled */
6602 return 24000;
6603}
6604
acd3f3d3
BP		 6605static int broxton_get_display_clock_speed(struct drm_device *dev)
6606{
6607 struct drm_i915_private *dev_priv = to_i915(dev);
6608 uint32_t cdctl = I915_READ(CDCLK_CTL);
6609 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6610 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6611 int cdclk;
6612
6613 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6614 return 19200;
6615
6616 cdclk = 19200 * pll_ratio / 2;
6617
6618 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6619 case BXT_CDCLK_CD2X_DIV_SEL_1:
6620 return cdclk; /* 576MHz or 624MHz */
6621 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6622 return cdclk * 2 / 3; /* 384MHz */
6623 case BXT_CDCLK_CD2X_DIV_SEL_2:
6624 return cdclk / 2; /* 288MHz */
6625 case BXT_CDCLK_CD2X_DIV_SEL_4:
6626 return cdclk / 4; /* 144MHz */
6627 }
6628
6629 /* error case, do as if DE PLL isn't enabled */
6630 return 19200;
6631}
6632
1652d19e
VS		 6633static int broadwell_get_display_clock_speed(struct drm_device *dev)
6634{
6635 struct drm_i915_private *dev_priv = dev->dev_private;
6636 uint32_t lcpll = I915_READ(LCPLL_CTL);
6637 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6638
6639 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6640 return 800000;
6641 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6642 return 450000;
6643 else if (freq == LCPLL_CLK_FREQ_450)
6644 return 450000;
6645 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6646 return 540000;
6647 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6648 return 337500;
6649 else
6650 return 675000;
6651}
6652
6653static int haswell_get_display_clock_speed(struct drm_device *dev)
6654{
6655 struct drm_i915_private *dev_priv = dev->dev_private;
6656 uint32_t lcpll = I915_READ(LCPLL_CTL);
6657 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6658
6659 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6660 return 800000;
6661 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6662 return 450000;
6663 else if (freq == LCPLL_CLK_FREQ_450)
6664 return 450000;
6665 else if (IS_HSW_ULT(dev))
6666 return 337500;
6667 else
6668 return 540000;
79e53945
JB		 6669}
6670
25eb05fc
JB		 6671static int valleyview_get_display_clock_speed(struct drm_device *dev)
6672{
d197b7d3 6673 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6674 u32 val;
6675 int divider;
6676
6bcda4f0
VS		 6677 if (dev_priv->hpll_freq == 0)
6678 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6679
a580516d 6680 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6681 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6682 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6683
6684 divider = val & DISPLAY_FREQUENCY_VALUES;
6685
7d007f40
VS		 6686 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6687 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6688 "cdclk change in progress\n");
6689
6bcda4f0 6690 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6691}
6692
b37a6434
VS		 6693static int ilk_get_display_clock_speed(struct drm_device *dev)
6694{
6695 return 450000;
6696}
6697
e70236a8
JB		 6698static int i945_get_display_clock_speed(struct drm_device *dev)
6699{
6700 return 400000;
6701}
79e53945 6702
e70236a8 6703static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6704{
e907f170 6705 return 333333;
e70236a8 6706}
79e53945 6707
e70236a8
JB		 6708static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6709{
6710 return 200000;
6711}
79e53945 6712
257a7ffc
DV		 6713static int pnv_get_display_clock_speed(struct drm_device *dev)
6714{
6715 u16 gcfgc = 0;
6716
6717 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6718
6719 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6720 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6721 return 266667;
257a7ffc 6722 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6723 return 333333;
257a7ffc 6724 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6725 return 444444;
257a7ffc
DV		 6726 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6727 return 200000;
6728 default:
6729 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6730 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6731 return 133333;
257a7ffc 6732 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6733 return 166667;
257a7ffc
DV		 6734 }
6735}
6736
e70236a8
JB		 6737static int i915gm_get_display_clock_speed(struct drm_device *dev)
6738{
6739 u16 gcfgc = 0;
79e53945 6740
e70236a8
JB		 6741 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6742
6743 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6744 return 133333;
e70236a8
JB		 6745 else {
6746 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6747 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6748 return 333333;
e70236a8
JB		 6749 default:
6750 case GC_DISPLAY_CLOCK_190_200_MHZ:
6751 return 190000;
79e53945 6752 }
e70236a8
JB		 6753 }
6754}
6755
6756static int i865_get_display_clock_speed(struct drm_device *dev)
6757{
e907f170 6758 return 266667;
e70236a8
JB		 6759}
6760
1b1d2716 6761static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6762{
6763 u16 hpllcc = 0;
1b1d2716 6764
65cd2b3f
VS		 6765 /*
6766 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6767 * encoding is different :(
6768 * FIXME is this the right way to detect 852GM/852GMV?
6769 */
6770 if (dev->pdev->revision == 0x1)
6771 return 133333;
6772
1b1d2716
VS		 6773 pci_bus_read_config_word(dev->pdev->bus,
6774 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6775
e70236a8
JB		 6776 /* Assume that the hardware is in the high speed state. This
6777 * should be the default.
6778 */
6779 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6780 case GC_CLOCK_133_200:
1b1d2716 6781 case GC_CLOCK_133_200_2:
e70236a8
JB		 6782 case GC_CLOCK_100_200:
6783 return 200000;
6784 case GC_CLOCK_166_250:
6785 return 250000;
6786 case GC_CLOCK_100_133:
e907f170 6787 return 133333;
1b1d2716
VS		 6788 case GC_CLOCK_133_266:
6789 case GC_CLOCK_133_266_2:
6790 case GC_CLOCK_166_266:
6791 return 266667;
e70236a8 6792 }
79e53945 6793
e70236a8
JB		 6794 /* Shouldn't happen */
6795 return 0;
6796}
79e53945 6797
e70236a8
JB		 6798static int i830_get_display_clock_speed(struct drm_device *dev)
6799{
e907f170 6800 return 133333;
79e53945
JB		 6801}
6802
34edce2f
VS		 6803static unsigned int intel_hpll_vco(struct drm_device *dev)
6804{
6805 struct drm_i915_private *dev_priv = dev->dev_private;
6806 static const unsigned int blb_vco[8] = {
6807 [0] = 3200000,
6808 [1] = 4000000,
6809 [2] = 5333333,
6810 [3] = 4800000,
6811 [4] = 6400000,
6812 };
6813 static const unsigned int pnv_vco[8] = {
6814 [0] = 3200000,
6815 [1] = 4000000,
6816 [2] = 5333333,
6817 [3] = 4800000,
6818 [4] = 2666667,
6819 };
6820 static const unsigned int cl_vco[8] = {
6821 [0] = 3200000,
6822 [1] = 4000000,
6823 [2] = 5333333,
6824 [3] = 6400000,
6825 [4] = 3333333,
6826 [5] = 3566667,
6827 [6] = 4266667,
6828 };
6829 static const unsigned int elk_vco[8] = {
6830 [0] = 3200000,
6831 [1] = 4000000,
6832 [2] = 5333333,
6833 [3] = 4800000,
6834 };
6835 static const unsigned int ctg_vco[8] = {
6836 [0] = 3200000,
6837 [1] = 4000000,
6838 [2] = 5333333,
6839 [3] = 6400000,
6840 [4] = 2666667,
6841 [5] = 4266667,
6842 };
6843 const unsigned int *vco_table;
6844 unsigned int vco;
6845 uint8_t tmp = 0;
6846
6847 /* FIXME other chipsets? */
6848 if (IS_GM45(dev))
6849 vco_table = ctg_vco;
6850 else if (IS_G4X(dev))
6851 vco_table = elk_vco;
6852 else if (IS_CRESTLINE(dev))
6853 vco_table = cl_vco;
6854 else if (IS_PINEVIEW(dev))
6855 vco_table = pnv_vco;
6856 else if (IS_G33(dev))
6857 vco_table = blb_vco;
6858 else
6859 return 0;
6860
6861 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6862
6863 vco = vco_table[tmp & 0x7];
6864 if (vco == 0)
6865 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6866 else
6867 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6868
6869 return vco;
6870}
6871
6872static int gm45_get_display_clock_speed(struct drm_device *dev)
6873{
6874 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6875 uint16_t tmp = 0;
6876
6877 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6878
6879 cdclk_sel = (tmp >> 12) & 0x1;
6880
6881 switch (vco) {
6882 case 2666667:
6883 case 4000000:
6884 case 5333333:
6885 return cdclk_sel ? 333333 : 222222;
6886 case 3200000:
6887 return cdclk_sel ? 320000 : 228571;
6888 default:
6889 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6890 return 222222;
6891 }
6892}
6893
6894static int i965gm_get_display_clock_speed(struct drm_device *dev)
6895{
6896 static const uint8_t div_3200[] = { 16, 10, 8 };
6897 static const uint8_t div_4000[] = { 20, 12, 10 };
6898 static const uint8_t div_5333[] = { 24, 16, 14 };
6899 const uint8_t *div_table;
6900 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6901 uint16_t tmp = 0;
6902
6903 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6904
6905 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6906
6907 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6908 goto fail;
6909
6910 switch (vco) {
6911 case 3200000:
6912 div_table = div_3200;
6913 break;
6914 case 4000000:
6915 div_table = div_4000;
6916 break;
6917 case 5333333:
6918 div_table = div_5333;
6919 break;
6920 default:
6921 goto fail;
6922 }
6923
6924 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6925
caf4e252 6926fail:
34edce2f
VS		 6927 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6928 return 200000;
6929}
6930
6931static int g33_get_display_clock_speed(struct drm_device *dev)
6932{
6933 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6934 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6935 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6936 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6937 const uint8_t *div_table;
6938 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6939 uint16_t tmp = 0;
6940
6941 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6942
6943 cdclk_sel = (tmp >> 4) & 0x7;
6944
6945 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6946 goto fail;
6947
6948 switch (vco) {
6949 case 3200000:
6950 div_table = div_3200;
6951 break;
6952 case 4000000:
6953 div_table = div_4000;
6954 break;
6955 case 4800000:
6956 div_table = div_4800;
6957 break;
6958 case 5333333:
6959 div_table = div_5333;
6960 break;
6961 default:
6962 goto fail;
6963 }
6964
6965 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6966
caf4e252 6967fail:
34edce2f
VS		 6968 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6969 return 190476;
6970}
6971
2c07245f 6972static void
a65851af 6973intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6974{
a65851af
VS		 6975 while (*num > DATA_LINK_M_N_MASK ||
6976 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6977 *num >>= 1;
6978 *den >>= 1;
6979 }
6980}
6981
a65851af
VS		 6982static void compute_m_n(unsigned int m, unsigned int n,
6983 uint32_t *ret_m, uint32_t *ret_n)
6984{
6985 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6986 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6987 intel_reduce_m_n_ratio(ret_m, ret_n);
6988}
6989
e69d0bc1
DV		 6990void
6991intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6992 int pixel_clock, int link_clock,
6993 struct intel_link_m_n *m_n)
2c07245f 6994{
e69d0bc1 6995 m_n->tu = 64;
a65851af
VS		 6996
6997 compute_m_n(bits_per_pixel * pixel_clock,
6998 link_clock * nlanes * 8,
6999 &m_n->gmch_m, &m_n->gmch_n);
7000
7001 compute_m_n(pixel_clock, link_clock,
7002 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7003}
7004
a7615030
CW		 7005static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7006{
d330a953
JN		 7007 if (i915.panel_use_ssc >= 0)
7008 return i915.panel_use_ssc != 0;
41aa3448 7009 return dev_priv->vbt.lvds_use_ssc
435793df 7010 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7011}
7012
a93e255f
ACO		 7013static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7014 int num_connectors)
c65d77d8 7015{
a93e255f 7016 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7017 struct drm_i915_private *dev_priv = dev->dev_private;
7018 int refclk;
7019
a93e255f
ACO		 7020 WARN_ON(!crtc_state->base.state);
7021
5ab7b0b7 7022 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7023 refclk = 100000;
a93e255f 7024 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7025 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7026 refclk = dev_priv->vbt.lvds_ssc_freq;
7027 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7028 } else if (!IS_GEN2(dev)) {
7029 refclk = 96000;
7030 } else {
7031 refclk = 48000;
7032 }
7033
7034 return refclk;
7035}
7036
7429e9d4 7037static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7038{
7df00d7a 7039 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7040}
f47709a9 7041
7429e9d4
DV		 7042static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7043{
7044 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7045}
7046
f47709a9 7047static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7048 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7049 intel_clock_t *reduced_clock)
7050{
f47709a9 7051 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7052 u32 fp, fp2 = 0;
7053
7054 if (IS_PINEVIEW(dev)) {
190f68c5 7055 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7056 if (reduced_clock)
7429e9d4 7057 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7058 } else {
190f68c5 7059 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7060 if (reduced_clock)
7429e9d4 7061 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7062 }
7063
190f68c5 7064 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7065
f47709a9 7066 crtc->lowfreq_avail = false;
a93e255f 7067 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7068 reduced_clock) {
190f68c5 7069 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7070 crtc->lowfreq_avail = true;
a7516a05 7071 } else {
190f68c5 7072 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7073 }
7074}
7075
5e69f97f
CML		 7076static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7077 pipe)
89b667f8
JB		 7078{
7079 u32 reg_val;
7080
7081 /*
7082 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7083 * and set it to a reasonable value instead.
7084 */
ab3c759a 7085 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7086 reg_val &= 0xffffff00;
7087 reg_val |= 0x00000030;
ab3c759a 7088 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7089
ab3c759a 7090 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7091 reg_val &= 0x8cffffff;
7092 reg_val = 0x8c000000;
ab3c759a 7093 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7094
ab3c759a 7095 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7096 reg_val &= 0xffffff00;
ab3c759a 7097 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7098
ab3c759a 7099 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7100 reg_val &= 0x00ffffff;
7101 reg_val |= 0xb0000000;
ab3c759a 7102 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7103}
7104
b551842d
DV		 7105static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7106 struct intel_link_m_n *m_n)
7107{
7108 struct drm_device *dev = crtc->base.dev;
7109 struct drm_i915_private *dev_priv = dev->dev_private;
7110 int pipe = crtc->pipe;
7111
e3b95f1e
DV		 7112 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7113 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7114 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7115 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7116}
7117
7118static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7119 struct intel_link_m_n *m_n,
7120 struct intel_link_m_n *m2_n2)
b551842d
DV		 7121{
7122 struct drm_device *dev = crtc->base.dev;
7123 struct drm_i915_private *dev_priv = dev->dev_private;
7124 int pipe = crtc->pipe;
6e3c9717 7125 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7126
7127 if (INTEL_INFO(dev)->gen >= 5) {
7128 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7129 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7130 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7131 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7132 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7133 * for gen < 8) and if DRRS is supported (to make sure the
7134 * registers are not unnecessarily accessed).
7135 */
44395bfe 7136 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7137 crtc->config->has_drrs) {
f769cd24
VK		 7138 I915_WRITE(PIPE_DATA_M2(transcoder),
7139 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7140 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7141 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7142 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7143 }
b551842d 7144 } else {
e3b95f1e
DV		 7145 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7146 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7147 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7148 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7149 }
7150}
7151
fe3cd48d 7152void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7153{
fe3cd48d
R		 7154 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7155
7156 if (m_n == M1_N1) {
7157 dp_m_n = &crtc->config->dp_m_n;
7158 dp_m2_n2 = &crtc->config->dp_m2_n2;
7159 } else if (m_n == M2_N2) {
7160
7161 /*
7162 * M2_N2 registers are not supported. Hence m2_n2 divider value
7163 * needs to be programmed into M1_N1.
7164 */
7165 dp_m_n = &crtc->config->dp_m2_n2;
7166 } else {
7167 DRM_ERROR("Unsupported divider value\n");
7168 return;
7169 }
7170
6e3c9717
ACO		 7171 if (crtc->config->has_pch_encoder)
7172 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7173 else
fe3cd48d 7174 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7175}
7176
251ac862
DV		 7177static void vlv_compute_dpll(struct intel_crtc *crtc,
7178 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7179{
7180 u32 dpll, dpll_md;
7181
7182 /*
7183 * Enable DPIO clock input. We should never disable the reference
7184 * clock for pipe B, since VGA hotplug / manual detection depends
7185 * on it.
7186 */
60bfe44f
VS		 7187 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7188 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7189 /* We should never disable this, set it here for state tracking */
7190 if (crtc->pipe == PIPE_B)
7191 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7192 dpll |= DPLL_VCO_ENABLE;
d288f65f 7193 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7194
d288f65f 7195 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7196 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7197 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7198}
7199
d288f65f 7200static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7201 const struct intel_crtc_state *pipe_config)
a0c4da24 7202{
f47709a9 7203 struct drm_device *dev = crtc->base.dev;
a0c4da24 7204 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7205 int pipe = crtc->pipe;
bdd4b6a6 7206 u32 mdiv;
a0c4da24 7207 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7208 u32 coreclk, reg_val;
a0c4da24 7209
a580516d 7210 mutex_lock(&dev_priv->sb_lock);
09153000 7211
d288f65f
VS		 7212 bestn = pipe_config->dpll.n;
7213 bestm1 = pipe_config->dpll.m1;
7214 bestm2 = pipe_config->dpll.m2;
7215 bestp1 = pipe_config->dpll.p1;
7216 bestp2 = pipe_config->dpll.p2;
a0c4da24 7217
89b667f8
JB		 7218 /* See eDP HDMI DPIO driver vbios notes doc */
7219
7220 /* PLL B needs special handling */
bdd4b6a6 7221 if (pipe == PIPE_B)
5e69f97f 7222 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7223
7224 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7225 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7226
7227 /* Disable target IRef on PLL */
ab3c759a 7228 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7229 reg_val &= 0x00ffffff;
ab3c759a 7230 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7231
7232 /* Disable fast lock */
ab3c759a 7233 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7234
7235 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7236 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7237 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7238 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7239 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7240
7241 /*
7242 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7243 * but we don't support that).
7244 * Note: don't use the DAC post divider as it seems unstable.
7245 */
7246 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7247 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7248
a0c4da24 7249 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7250 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7251
89b667f8 7252 /* Set HBR and RBR LPF coefficients */
d288f65f 7253 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7254 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7255 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7256 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7257 0x009f0003);
89b667f8 7258 else
ab3c759a 7259 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7260 0x00d0000f);
7261
681a8504 7262 if (pipe_config->has_dp_encoder) {
89b667f8 7263 /* Use SSC source */
bdd4b6a6 7264 if (pipe == PIPE_A)
ab3c759a 7265 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7266 0x0df40000);
7267 else
ab3c759a 7268 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7269 0x0df70000);
7270 } else { /* HDMI or VGA */
7271 /* Use bend source */
bdd4b6a6 7272 if (pipe == PIPE_A)
ab3c759a 7273 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7274 0x0df70000);
7275 else
ab3c759a 7276 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7277 0x0df40000);
7278 }
a0c4da24 7279
ab3c759a 7280 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7281 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7282 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7283 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7284 coreclk |= 0x01000000;
ab3c759a 7285 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7286
ab3c759a 7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7288 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7289}
7290
251ac862
DV		 7291static void chv_compute_dpll(struct intel_crtc *crtc,
7292 struct intel_crtc_state *pipe_config)
1ae0d137 7293{
60bfe44f
VS		 7294 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7295 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7296 DPLL_VCO_ENABLE;
7297 if (crtc->pipe != PIPE_A)
d288f65f 7298 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7299
d288f65f
VS		 7300 pipe_config->dpll_hw_state.dpll_md =
7301 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7302}
7303
d288f65f 7304static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7305 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7306{
7307 struct drm_device *dev = crtc->base.dev;
7308 struct drm_i915_private *dev_priv = dev->dev_private;
7309 int pipe = crtc->pipe;
7310 int dpll_reg = DPLL(crtc->pipe);
7311 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7312 u32 loopfilter, tribuf_calcntr;
9d556c99 7313 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7314 u32 dpio_val;
9cbe40c1 7315 int vco;
9d556c99 7316
d288f65f
VS		 7317 bestn = pipe_config->dpll.n;
7318 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7319 bestm1 = pipe_config->dpll.m1;
7320 bestm2 = pipe_config->dpll.m2 >> 22;
7321 bestp1 = pipe_config->dpll.p1;
7322 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7323 vco = pipe_config->dpll.vco;
a945ce7e 7324 dpio_val = 0;
9cbe40c1 7325 loopfilter = 0;
9d556c99
CML		 7326
7327 /*
7328 * Enable Refclk and SSC
7329 */
a11b0703 7330 I915_WRITE(dpll_reg,
d288f65f 7331 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7332
a580516d 7333 mutex_lock(&dev_priv->sb_lock);
9d556c99 7334
9d556c99
CML		 7335 /* p1 and p2 divider */
7336 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7337 5 << DPIO_CHV_S1_DIV_SHIFT |
7338 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7339 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7340 1 << DPIO_CHV_K_DIV_SHIFT);
7341
7342 /* Feedback post-divider - m2 */
7343 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7344
7345 /* Feedback refclk divider - n and m1 */
7346 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7347 DPIO_CHV_M1_DIV_BY_2 |
7348 1 << DPIO_CHV_N_DIV_SHIFT);
7349
7350 /* M2 fraction division */
25a25dfc 7351 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7352
7353 /* M2 fraction division enable */
a945ce7e
VP		 7354 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7355 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7356 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7357 if (bestm2_frac)
7358 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7359 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7360
de3a0fde
VP		 7361 /* Program digital lock detect threshold */
7362 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7363 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7364 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7365 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7366 if (!bestm2_frac)
7367 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7369
9d556c99 7370 /* Loop filter */
9cbe40c1
VP		 7371 if (vco == 5400000) {
7372 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7373 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7374 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7375 tribuf_calcntr = 0x9;
7376 } else if (vco <= 6200000) {
7377 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7378 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7379 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7380 tribuf_calcntr = 0x9;
7381 } else if (vco <= 6480000) {
7382 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7383 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7384 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7385 tribuf_calcntr = 0x8;
7386 } else {
7387 /* Not supported. Apply the same limits as in the max case */
7388 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7389 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7390 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7391 tribuf_calcntr = 0;
7392 }
9d556c99
CML		 7393 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7394
968040b2 7395 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7396 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7397 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7398 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7399
9d556c99
CML		 7400 /* AFC Recal */
7401 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7402 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7403 DPIO_AFC_RECAL);
7404
a580516d 7405 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7406}
7407
d288f65f
VS		 7408/**
7409 * vlv_force_pll_on - forcibly enable just the PLL
7410 * @dev_priv: i915 private structure
7411 * @pipe: pipe PLL to enable
7412 * @dpll: PLL configuration
7413 *
7414 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7415 * in cases where we need the PLL enabled even when @pipe is not going to
7416 * be enabled.
7417 */
7418void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7419 const struct dpll *dpll)
7420{
7421 struct intel_crtc *crtc =
7422 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7423 struct intel_crtc_state pipe_config = {
a93e255f 7424 .base.crtc = &crtc->base,
d288f65f
VS		 7425 .pixel_multiplier = 1,
7426 .dpll = *dpll,
7427 };
7428
7429 if (IS_CHERRYVIEW(dev)) {
251ac862 7430 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7431 chv_prepare_pll(crtc, &pipe_config);
7432 chv_enable_pll(crtc, &pipe_config);
7433 } else {
251ac862 7434 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7435 vlv_prepare_pll(crtc, &pipe_config);
7436 vlv_enable_pll(crtc, &pipe_config);
7437 }
7438}
7439
7440/**
7441 * vlv_force_pll_off - forcibly disable just the PLL
7442 * @dev_priv: i915 private structure
7443 * @pipe: pipe PLL to disable
7444 *
7445 * Disable the PLL for @pipe. To be used in cases where we need
7446 * the PLL enabled even when @pipe is not going to be enabled.
7447 */
7448void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7449{
7450 if (IS_CHERRYVIEW(dev))
7451 chv_disable_pll(to_i915(dev), pipe);
7452 else
7453 vlv_disable_pll(to_i915(dev), pipe);
7454}
7455
251ac862
DV		 7456static void i9xx_compute_dpll(struct intel_crtc *crtc,
7457 struct intel_crtc_state *crtc_state,
7458 intel_clock_t *reduced_clock,
7459 int num_connectors)
eb1cbe48 7460{
f47709a9 7461 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7462 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7463 u32 dpll;
7464 bool is_sdvo;
190f68c5 7465 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7466
190f68c5 7467 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7468
a93e255f
ACO		 7469 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7470 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7471
7472 dpll = DPLL_VGA_MODE_DIS;
7473
a93e255f 7474 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7475 dpll |= DPLLB_MODE_LVDS;
7476 else
7477 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7478
ef1b460d 7479 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7480 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7481 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7482 }
198a037f
DV		 7483
7484 if (is_sdvo)
4a33e48d 7485 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7486
190f68c5 7487 if (crtc_state->has_dp_encoder)
4a33e48d 7488 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7489
7490 /* compute bitmask from p1 value */
7491 if (IS_PINEVIEW(dev))
7492 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7493 else {
7494 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7495 if (IS_G4X(dev) && reduced_clock)
7496 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7497 }
7498 switch (clock->p2) {
7499 case 5:
7500 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7501 break;
7502 case 7:
7503 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7504 break;
7505 case 10:
7506 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7507 break;
7508 case 14:
7509 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7510 break;
7511 }
7512 if (INTEL_INFO(dev)->gen >= 4)
7513 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7514
190f68c5 7515 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7516 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7517 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7518 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7519 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7520 else
7521 dpll |= PLL_REF_INPUT_DREFCLK;
7522
7523 dpll |= DPLL_VCO_ENABLE;
190f68c5 7524 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7525
eb1cbe48 7526 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7527 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7528 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7529 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7530 }
7531}
7532
251ac862
DV		 7533static void i8xx_compute_dpll(struct intel_crtc *crtc,
7534 struct intel_crtc_state *crtc_state,
7535 intel_clock_t *reduced_clock,
7536 int num_connectors)
eb1cbe48 7537{
f47709a9 7538 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7539 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7540 u32 dpll;
190f68c5 7541 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7542
190f68c5 7543 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7544
eb1cbe48
DV		 7545 dpll = DPLL_VGA_MODE_DIS;
7546
a93e255f 7547 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7548 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7549 } else {
7550 if (clock->p1 == 2)
7551 dpll |= PLL_P1_DIVIDE_BY_TWO;
7552 else
7553 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7554 if (clock->p2 == 4)
7555 dpll |= PLL_P2_DIVIDE_BY_4;
7556 }
7557
a93e255f 7558 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7559 dpll |= DPLL_DVO_2X_MODE;
7560
a93e255f 7561 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7562 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7563 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7564 else
7565 dpll |= PLL_REF_INPUT_DREFCLK;
7566
7567 dpll |= DPLL_VCO_ENABLE;
190f68c5 7568 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7569}
7570
8a654f3b 7571static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7572{
7573 struct drm_device *dev = intel_crtc->base.dev;
7574 struct drm_i915_private *dev_priv = dev->dev_private;
7575 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7576 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7577 struct drm_display_mode *adjusted_mode =
6e3c9717 7578 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7579 uint32_t crtc_vtotal, crtc_vblank_end;
7580 int vsyncshift = 0;
4d8a62ea
DV		 7581
7582 /* We need to be careful not to changed the adjusted mode, for otherwise
7583 * the hw state checker will get angry at the mismatch. */
7584 crtc_vtotal = adjusted_mode->crtc_vtotal;
7585 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7586
609aeaca 7587 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7588 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7589 crtc_vtotal -= 1;
7590 crtc_vblank_end -= 1;
609aeaca 7591
409ee761 7592 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7593 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7594 else
7595 vsyncshift = adjusted_mode->crtc_hsync_start -
7596 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7597 if (vsyncshift < 0)
7598 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7599 }
7600
7601 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7602 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7603
fe2b8f9d 7604 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7605 (adjusted_mode->crtc_hdisplay - 1) |
7606 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7607 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7608 (adjusted_mode->crtc_hblank_start - 1) |
7609 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7610 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7611 (adjusted_mode->crtc_hsync_start - 1) |
7612 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7613
fe2b8f9d 7614 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7615 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7616 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7617 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7618 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7619 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7620 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7621 (adjusted_mode->crtc_vsync_start - 1) |
7622 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7623
b5e508d4
PZ		 7624 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7625 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7626 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7627 * bits. */
7628 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7629 (pipe == PIPE_B || pipe == PIPE_C))
7630 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7631
b0e77b9c
PZ		 7632 /* pipesrc controls the size that is scaled from, which should
7633 * always be the user's requested size.
7634 */
7635 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7636 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7637 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7638}
7639
1bd1bd80 7640static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7641 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7642{
7643 struct drm_device *dev = crtc->base.dev;
7644 struct drm_i915_private *dev_priv = dev->dev_private;
7645 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7646 uint32_t tmp;
7647
7648 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7649 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7650 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7651 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7652 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7653 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7654 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7655 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7656 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7657
7658 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7659 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7660 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7661 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7662 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7663 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7664 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7665 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7666 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7667
7668 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7669 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7670 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7671 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7672 }
7673
7674 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7675 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7676 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7677
2d112de7
ACO		 7678 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7679 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7680}
7681
f6a83288 7682void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7683 struct intel_crtc_state *pipe_config)
babea61d 7684{
2d112de7
ACO		 7685 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7686 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7687 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7688 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7689
2d112de7
ACO		 7690 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7691 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7692 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7693 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7694
2d112de7 7695 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7696 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7697
2d112de7
ACO		 7698 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7699 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7700
7701 mode->hsync = drm_mode_hsync(mode);
7702 mode->vrefresh = drm_mode_vrefresh(mode);
7703 drm_mode_set_name(mode);
babea61d
JB		 7704}
7705
84b046f3
DV		 7706static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7707{
7708 struct drm_device *dev = intel_crtc->base.dev;
7709 struct drm_i915_private *dev_priv = dev->dev_private;
7710 uint32_t pipeconf;
7711
9f11a9e4 7712 pipeconf = 0;
84b046f3 7713
b6b5d049
VS		 7714 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7715 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7716 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7717
6e3c9717 7718 if (intel_crtc->config->double_wide)
cf532bb2 7719 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7720
ff9ce46e
DV		 7721 /* only g4x and later have fancy bpc/dither controls */
7722 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7723 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7724 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7725 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7726 PIPECONF_DITHER_TYPE_SP;
84b046f3 7727
6e3c9717 7728 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7729 case 18:
7730 pipeconf |= PIPECONF_6BPC;
7731 break;
7732 case 24:
7733 pipeconf |= PIPECONF_8BPC;
7734 break;
7735 case 30:
7736 pipeconf |= PIPECONF_10BPC;
7737 break;
7738 default:
7739 /* Case prevented by intel_choose_pipe_bpp_dither. */
7740 BUG();
84b046f3
DV		 7741 }
7742 }
7743
7744 if (HAS_PIPE_CXSR(dev)) {
7745 if (intel_crtc->lowfreq_avail) {
7746 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7747 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7748 } else {
7749 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7750 }
7751 }
7752
6e3c9717 7753 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7754 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7755 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7756 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7757 else
7758 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7759 } else
84b046f3
DV		 7760 pipeconf |= PIPECONF_PROGRESSIVE;
7761
6e3c9717 7762 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7763 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7764
84b046f3
DV		 7765 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7766 POSTING_READ(PIPECONF(intel_crtc->pipe));
7767}
7768
190f68c5
ACO		 7769static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7770 struct intel_crtc_state *crtc_state)
79e53945 7771{
c7653199 7772 struct drm_device *dev = crtc->base.dev;
79e53945 7773 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7774 int refclk, num_connectors = 0;
c329a4ec
DV		 7775 intel_clock_t clock;
7776 bool ok;
7777 bool is_dsi = false;
5eddb70b 7778 struct intel_encoder *encoder;
d4906093 7779 const intel_limit_t *limit;
55bb9992 7780 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7781 struct drm_connector *connector;
55bb9992
ACO		 7782 struct drm_connector_state *connector_state;
7783 int i;
79e53945 7784
dd3cd74a
ACO		 7785 memset(&crtc_state->dpll_hw_state, 0,
7786 sizeof(crtc_state->dpll_hw_state));
7787
da3ced29 7788 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7789 if (connector_state->crtc != &crtc->base)
7790 continue;
7791
7792 encoder = to_intel_encoder(connector_state->best_encoder);
7793
5eddb70b 7794 switch (encoder->type) {
e9fd1c02
JN		 7795 case INTEL_OUTPUT_DSI:
7796 is_dsi = true;
7797 break;
6847d71b
PZ		 7798 default:
7799 break;
79e53945 7800 }
43565a06 7801
c751ce4f 7802 num_connectors++;
79e53945
JB		 7803 }
7804
f2335330 7805 if (is_dsi)
5b18e57c 7806 return 0;
f2335330 7807
190f68c5 7808 if (!crtc_state->clock_set) {
a93e255f 7809 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7810
e9fd1c02
JN		 7811 /*
7812 * Returns a set of divisors for the desired target clock with
7813 * the given refclk, or FALSE. The returned values represent
7814 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7815 * 2) / p1 / p2.
7816 */
a93e255f
ACO		 7817 limit = intel_limit(crtc_state, refclk);
7818 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7819 crtc_state->port_clock,
e9fd1c02 7820 refclk, NULL, &clock);
f2335330 7821 if (!ok) {
e9fd1c02
JN		 7822 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7823 return -EINVAL;
7824 }
79e53945 7825
f2335330 7826 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7827 crtc_state->dpll.n = clock.n;
7828 crtc_state->dpll.m1 = clock.m1;
7829 crtc_state->dpll.m2 = clock.m2;
7830 crtc_state->dpll.p1 = clock.p1;
7831 crtc_state->dpll.p2 = clock.p2;
f47709a9 7832 }
7026d4ac 7833
e9fd1c02 7834 if (IS_GEN2(dev)) {
c329a4ec 7835 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7836 num_connectors);
9d556c99 7837 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7838 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7839 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7840 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7841 } else {
c329a4ec 7842 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7843 num_connectors);
e9fd1c02 7844 }
79e53945 7845
c8f7a0db 7846 return 0;
f564048e
EA		 7847}
7848
2fa2fe9a 7849static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7850 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7851{
7852 struct drm_device *dev = crtc->base.dev;
7853 struct drm_i915_private *dev_priv = dev->dev_private;
7854 uint32_t tmp;
7855
dc9e7dec
VS		 7856 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7857 return;
7858
2fa2fe9a 7859 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7860 if (!(tmp & PFIT_ENABLE))
7861 return;
2fa2fe9a 7862
06922821 7863 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7864 if (INTEL_INFO(dev)->gen < 4) {
7865 if (crtc->pipe != PIPE_B)
7866 return;
2fa2fe9a
DV		 7867 } else {
7868 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7869 return;
7870 }
7871
06922821 7872 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7873 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7874 if (INTEL_INFO(dev)->gen < 5)
7875 pipe_config->gmch_pfit.lvds_border_bits =
7876 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7877}
7878
acbec814 7879static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7880 struct intel_crtc_state *pipe_config)
acbec814
JB		 7881{
7882 struct drm_device *dev = crtc->base.dev;
7883 struct drm_i915_private *dev_priv = dev->dev_private;
7884 int pipe = pipe_config->cpu_transcoder;
7885 intel_clock_t clock;
7886 u32 mdiv;
662c6ecb 7887 int refclk = 100000;
acbec814 7888
f573de5a
SK		 7889 /* In case of MIPI DPLL will not even be used */
7890 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7891 return;
7892
a580516d 7893 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7894 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7895 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7896
7897 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7898 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7899 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7900 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7901 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7902
dccbea3b 7903 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7904}
7905
5724dbd1
DL		 7906static void
7907i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7908 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7909{
7910 struct drm_device *dev = crtc->base.dev;
7911 struct drm_i915_private *dev_priv = dev->dev_private;
7912 u32 val, base, offset;
7913 int pipe = crtc->pipe, plane = crtc->plane;
7914 int fourcc, pixel_format;
6761dd31 7915 unsigned int aligned_height;
b113d5ee 7916 struct drm_framebuffer *fb;
1b842c89 7917 struct intel_framebuffer *intel_fb;
1ad292b5 7918
42a7b088
DL		 7919 val = I915_READ(DSPCNTR(plane));
7920 if (!(val & DISPLAY_PLANE_ENABLE))
7921 return;
7922
d9806c9f 7923 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7924 if (!intel_fb) {
1ad292b5
JB		 7925 DRM_DEBUG_KMS("failed to alloc fb\n");
7926 return;
7927 }
7928
1b842c89
DL		 7929 fb = &intel_fb->base;
7930
18c5247e
DV		 7931 if (INTEL_INFO(dev)->gen >= 4) {
7932 if (val & DISPPLANE_TILED) {
49af449b 7933 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7934 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7935 }
7936 }
1ad292b5
JB		 7937
7938 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7939 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7940 fb->pixel_format = fourcc;
7941 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7942
7943 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7944 if (plane_config->tiling)
1ad292b5
JB		 7945 offset = I915_READ(DSPTILEOFF(plane));
7946 else
7947 offset = I915_READ(DSPLINOFF(plane));
7948 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7949 } else {
7950 base = I915_READ(DSPADDR(plane));
7951 }
7952 plane_config->base = base;
7953
7954 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7955 fb->width = ((val >> 16) & 0xfff) + 1;
7956 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7957
7958 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7959 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7960
b113d5ee 7961 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7962 fb->pixel_format,
7963 fb->modifier[0]);
1ad292b5 7964
f37b5c2b 7965 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7966
2844a921
DL		 7967 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7968 pipe_name(pipe), plane, fb->width, fb->height,
7969 fb->bits_per_pixel, base, fb->pitches[0],
7970 plane_config->size);
1ad292b5 7971
2d14030b 7972 plane_config->fb = intel_fb;
1ad292b5
JB		 7973}
7974
70b23a98 7975static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7976 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7977{
7978 struct drm_device *dev = crtc->base.dev;
7979 struct drm_i915_private *dev_priv = dev->dev_private;
7980 int pipe = pipe_config->cpu_transcoder;
7981 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7982 intel_clock_t clock;
0d7b6b11 7983 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS		 7984 int refclk = 100000;
7985
a580516d 7986 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 7987 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7988 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7989 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7990 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 7991 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 7992 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 7993
7994 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID		 7995 clock.m2 = (pll_dw0 & 0xff) << 22;
7996 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7997 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS		 7998 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7999 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8000 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8001
dccbea3b 8002 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8003}
8004
0e8ffe1b 8005static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8006 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8007{
8008 struct drm_device *dev = crtc->base.dev;
8009 struct drm_i915_private *dev_priv = dev->dev_private;
8010 uint32_t tmp;
8011
f458ebbc
DV		 8012 if (!intel_display_power_is_enabled(dev_priv,
8013 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8014 return false;
8015
e143a21c 8016 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8017 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8018
0e8ffe1b
DV		 8019 tmp = I915_READ(PIPECONF(crtc->pipe));
8020 if (!(tmp & PIPECONF_ENABLE))
8021 return false;
8022
42571aef
VS		 8023 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8024 switch (tmp & PIPECONF_BPC_MASK) {
8025 case PIPECONF_6BPC:
8026 pipe_config->pipe_bpp = 18;
8027 break;
8028 case PIPECONF_8BPC:
8029 pipe_config->pipe_bpp = 24;
8030 break;
8031 case PIPECONF_10BPC:
8032 pipe_config->pipe_bpp = 30;
8033 break;
8034 default:
8035 break;
8036 }
8037 }
8038
b5a9fa09
DV		 8039 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8040 pipe_config->limited_color_range = true;
8041
282740f7
VS		 8042 if (INTEL_INFO(dev)->gen < 4)
8043 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8044
1bd1bd80
DV		 8045 intel_get_pipe_timings(crtc, pipe_config);
8046
2fa2fe9a
DV		 8047 i9xx_get_pfit_config(crtc, pipe_config);
8048
6c49f241
DV		 8049 if (INTEL_INFO(dev)->gen >= 4) {
8050 tmp = I915_READ(DPLL_MD(crtc->pipe));
8051 pipe_config->pixel_multiplier =
8052 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8053 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8054 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8055 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8056 tmp = I915_READ(DPLL(crtc->pipe));
8057 pipe_config->pixel_multiplier =
8058 ((tmp & SDVO_MULTIPLIER_MASK)
8059 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8060 } else {
8061 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8062 * port and will be fixed up in the encoder->get_config
8063 * function. */
8064 pipe_config->pixel_multiplier = 1;
8065 }
8bcc2795
DV		 8066 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8067 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8068 /*
8069 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8070 * on 830. Filter it out here so that we don't
8071 * report errors due to that.
8072 */
8073 if (IS_I830(dev))
8074 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8075
8bcc2795
DV		 8076 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8077 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8078 } else {
8079 /* Mask out read-only status bits. */
8080 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8081 DPLL_PORTC_READY_MASK |
8082 DPLL_PORTB_READY_MASK);
8bcc2795 8083 }
6c49f241 8084
70b23a98
VS		 8085 if (IS_CHERRYVIEW(dev))
8086 chv_crtc_clock_get(crtc, pipe_config);
8087 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8088 vlv_crtc_clock_get(crtc, pipe_config);
8089 else
8090 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8091
0f64614d
VS		 8092 /*
8093 * Normally the dotclock is filled in by the encoder .get_config()
8094 * but in case the pipe is enabled w/o any ports we need a sane
8095 * default.
8096 */
8097 pipe_config->base.adjusted_mode.crtc_clock =
8098 pipe_config->port_clock / pipe_config->pixel_multiplier;
8099
0e8ffe1b
DV		 8100 return true;
8101}
8102
dde86e2d 8103static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8104{
8105 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8106 struct intel_encoder *encoder;
74cfd7ac 8107 u32 val, final;
13d83a67 8108 bool has_lvds = false;
199e5d79 8109 bool has_cpu_edp = false;
199e5d79 8110 bool has_panel = false;
99eb6a01
KP		 8111 bool has_ck505 = false;
8112 bool can_ssc = false;
13d83a67
JB		 8113
8114 /* We need to take the global config into account */
b2784e15 8115 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8116 switch (encoder->type) {
8117 case INTEL_OUTPUT_LVDS:
8118 has_panel = true;
8119 has_lvds = true;
8120 break;
8121 case INTEL_OUTPUT_EDP:
8122 has_panel = true;
2de6905f 8123 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8124 has_cpu_edp = true;
8125 break;
6847d71b
PZ		 8126 default:
8127 break;
13d83a67
JB		 8128 }
8129 }
8130
99eb6a01 8131 if (HAS_PCH_IBX(dev)) {
41aa3448 8132 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8133 can_ssc = has_ck505;
8134 } else {
8135 has_ck505 = false;
8136 can_ssc = true;
8137 }
8138
2de6905f
ID		 8139 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8140 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8141
8142 /* Ironlake: try to setup display ref clock before DPLL
8143 * enabling. This is only under driver's control after
8144 * PCH B stepping, previous chipset stepping should be
8145 * ignoring this setting.
8146 */
74cfd7ac
CW		 8147 val = I915_READ(PCH_DREF_CONTROL);
8148
8149 /* As we must carefully and slowly disable/enable each source in turn,
8150 * compute the final state we want first and check if we need to
8151 * make any changes at all.
8152 */
8153 final = val;
8154 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8155 if (has_ck505)
8156 final |= DREF_NONSPREAD_CK505_ENABLE;
8157 else
8158 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8159
8160 final &= ~DREF_SSC_SOURCE_MASK;
8161 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8162 final &= ~DREF_SSC1_ENABLE;
8163
8164 if (has_panel) {
8165 final |= DREF_SSC_SOURCE_ENABLE;
8166
8167 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8168 final |= DREF_SSC1_ENABLE;
8169
8170 if (has_cpu_edp) {
8171 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8172 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8173 else
8174 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8175 } else
8176 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8177 } else {
8178 final |= DREF_SSC_SOURCE_DISABLE;
8179 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8180 }
8181
8182 if (final == val)
8183 return;
8184
13d83a67 8185 /* Always enable nonspread source */
74cfd7ac 8186 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8187
99eb6a01 8188 if (has_ck505)
74cfd7ac 8189 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8190 else
74cfd7ac 8191 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8192
199e5d79 8193 if (has_panel) {
74cfd7ac
CW		 8194 val &= ~DREF_SSC_SOURCE_MASK;
8195 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8196
199e5d79 8197 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8198 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8199 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8200 val |= DREF_SSC1_ENABLE;
e77166b5 8201 } else
74cfd7ac 8202 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8203
8204 /* Get SSC going before enabling the outputs */
74cfd7ac 8205 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8206 POSTING_READ(PCH_DREF_CONTROL);
8207 udelay(200);
8208
74cfd7ac 8209 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8210
8211 /* Enable CPU source on CPU attached eDP */
199e5d79 8212 if (has_cpu_edp) {
99eb6a01 8213 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8214 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8215 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8216 } else
74cfd7ac 8217 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8218 } else
74cfd7ac 8219 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8220
74cfd7ac 8221 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8222 POSTING_READ(PCH_DREF_CONTROL);
8223 udelay(200);
8224 } else {
8225 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8226
74cfd7ac 8227 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8228
8229 /* Turn off CPU output */
74cfd7ac 8230 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8231
74cfd7ac 8232 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8233 POSTING_READ(PCH_DREF_CONTROL);
8234 udelay(200);
8235
8236 /* Turn off the SSC source */
74cfd7ac
CW		 8237 val &= ~DREF_SSC_SOURCE_MASK;
8238 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8239
8240 /* Turn off SSC1 */
74cfd7ac 8241 val &= ~DREF_SSC1_ENABLE;
199e5d79 8242
74cfd7ac 8243 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8244 POSTING_READ(PCH_DREF_CONTROL);
8245 udelay(200);
8246 }
74cfd7ac
CW		 8247
8248 BUG_ON(val != final);
13d83a67
JB		 8249}
8250
f31f2d55 8251static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8252{
f31f2d55 8253 uint32_t tmp;
dde86e2d 8254
0ff066a9
PZ		 8255 tmp = I915_READ(SOUTH_CHICKEN2);
8256 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8257 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8258
0ff066a9
PZ		 8259 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8260 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8261 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8262
0ff066a9
PZ		 8263 tmp = I915_READ(SOUTH_CHICKEN2);
8264 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8265 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8266
0ff066a9
PZ		 8267 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8268 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8269 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8270}
8271
8272/* WaMPhyProgramming:hsw */
8273static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8274{
8275 uint32_t tmp;
dde86e2d
PZ		 8276
8277 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8278 tmp &= ~(0xFF << 24);
8279 tmp |= (0x12 << 24);
8280 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8281
dde86e2d
PZ		 8282 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8283 tmp |= (1 << 11);
8284 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8285
8286 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8287 tmp |= (1 << 11);
8288 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8289
dde86e2d
PZ		 8290 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8291 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8292 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8293
8294 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8295 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8296 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8297
0ff066a9
PZ		 8298 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8299 tmp &= ~(7 << 13);
8300 tmp |= (5 << 13);
8301 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8302
0ff066a9
PZ		 8303 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8304 tmp &= ~(7 << 13);
8305 tmp |= (5 << 13);
8306 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8307
8308 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8309 tmp &= ~0xFF;
8310 tmp |= 0x1C;
8311 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8312
8313 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8314 tmp &= ~0xFF;
8315 tmp |= 0x1C;
8316 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8317
8318 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8319 tmp &= ~(0xFF << 16);
8320 tmp |= (0x1C << 16);
8321 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8322
8323 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8324 tmp &= ~(0xFF << 16);
8325 tmp |= (0x1C << 16);
8326 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8327
0ff066a9
PZ		 8328 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8329 tmp |= (1 << 27);
8330 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8331
0ff066a9
PZ		 8332 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8333 tmp |= (1 << 27);
8334 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8335
0ff066a9
PZ		 8336 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8337 tmp &= ~(0xF << 28);
8338 tmp |= (4 << 28);
8339 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8340
0ff066a9
PZ		 8341 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8342 tmp &= ~(0xF << 28);
8343 tmp |= (4 << 28);
8344 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8345}
8346
2fa86a1f
PZ		 8347/* Implements 3 different sequences from BSpec chapter "Display iCLK
8348 * Programming" based on the parameters passed:
8349 * - Sequence to enable CLKOUT_DP
8350 * - Sequence to enable CLKOUT_DP without spread
8351 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8352 */
8353static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8354 bool with_fdi)
f31f2d55
PZ		 8355{
8356 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8357 uint32_t reg, tmp;
8358
8359 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8360 with_spread = true;
c2699524 8361 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 8362 with_fdi = false;
f31f2d55 8363
a580516d 8364 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8365
8366 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8367 tmp &= ~SBI_SSCCTL_DISABLE;
8368 tmp |= SBI_SSCCTL_PATHALT;
8369 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8370
8371 udelay(24);
8372
2fa86a1f
PZ		 8373 if (with_spread) {
8374 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8375 tmp &= ~SBI_SSCCTL_PATHALT;
8376 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8377
2fa86a1f
PZ		 8378 if (with_fdi) {
8379 lpt_reset_fdi_mphy(dev_priv);
8380 lpt_program_fdi_mphy(dev_priv);
8381 }
8382 }
dde86e2d 8383
c2699524 8384 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ		 8385 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8386 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8387 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8388
a580516d 8389 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8390}
8391
47701c3b
PZ		 8392/* Sequence to disable CLKOUT_DP */
8393static void lpt_disable_clkout_dp(struct drm_device *dev)
8394{
8395 struct drm_i915_private *dev_priv = dev->dev_private;
8396 uint32_t reg, tmp;
8397
a580516d 8398 mutex_lock(&dev_priv->sb_lock);
47701c3b 8399
c2699524 8400 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ		 8401 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8402 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8403 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8404
8405 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8406 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8407 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8408 tmp |= SBI_SSCCTL_PATHALT;
8409 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8410 udelay(32);
8411 }
8412 tmp |= SBI_SSCCTL_DISABLE;
8413 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8414 }
8415
a580516d 8416 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8417}
8418
bf8fa3d3
PZ		 8419static void lpt_init_pch_refclk(struct drm_device *dev)
8420{
bf8fa3d3
PZ		 8421 struct intel_encoder *encoder;
8422 bool has_vga = false;
8423
b2784e15 8424 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8425 switch (encoder->type) {
8426 case INTEL_OUTPUT_ANALOG:
8427 has_vga = true;
8428 break;
6847d71b
PZ		 8429 default:
8430 break;
bf8fa3d3
PZ		 8431 }
8432 }
8433
47701c3b
PZ		 8434 if (has_vga)
8435 lpt_enable_clkout_dp(dev, true, true);
8436 else
8437 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8438}
8439
dde86e2d
PZ		 8440/*
8441 * Initialize reference clocks when the driver loads
8442 */
8443void intel_init_pch_refclk(struct drm_device *dev)
8444{
8445 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8446 ironlake_init_pch_refclk(dev);
8447 else if (HAS_PCH_LPT(dev))
8448 lpt_init_pch_refclk(dev);
8449}
8450
55bb9992 8451static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8452{
55bb9992 8453 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8454 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8455 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8456 struct drm_connector *connector;
55bb9992 8457 struct drm_connector_state *connector_state;
d9d444cb 8458 struct intel_encoder *encoder;
55bb9992 8459 int num_connectors = 0, i;
d9d444cb
JB		 8460 bool is_lvds = false;
8461
da3ced29 8462 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8463 if (connector_state->crtc != crtc_state->base.crtc)
8464 continue;
8465
8466 encoder = to_intel_encoder(connector_state->best_encoder);
8467
d9d444cb
JB		 8468 switch (encoder->type) {
8469 case INTEL_OUTPUT_LVDS:
8470 is_lvds = true;
8471 break;
6847d71b
PZ		 8472 default:
8473 break;
d9d444cb
JB		 8474 }
8475 num_connectors++;
8476 }
8477
8478 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8479 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8480 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8481 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8482 }
8483
8484 return 120000;
8485}
8486
6ff93609 8487static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8488{
c8203565 8489 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8491 int pipe = intel_crtc->pipe;
c8203565
PZ		 8492 uint32_t val;
8493
78114071 8494 val = 0;
c8203565 8495
6e3c9717 8496 switch (intel_crtc->config->pipe_bpp) {
c8203565 8497 case 18:
dfd07d72 8498 val |= PIPECONF_6BPC;
c8203565
PZ		 8499 break;
8500 case 24:
dfd07d72 8501 val |= PIPECONF_8BPC;
c8203565
PZ		 8502 break;
8503 case 30:
dfd07d72 8504 val |= PIPECONF_10BPC;
c8203565
PZ		 8505 break;
8506 case 36:
dfd07d72 8507 val |= PIPECONF_12BPC;
c8203565
PZ		 8508 break;
8509 default:
cc769b62
PZ		 8510 /* Case prevented by intel_choose_pipe_bpp_dither. */
8511 BUG();
c8203565
PZ		 8512 }
8513
6e3c9717 8514 if (intel_crtc->config->dither)
c8203565
PZ		 8515 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8516
6e3c9717 8517 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8518 val |= PIPECONF_INTERLACED_ILK;
8519 else
8520 val |= PIPECONF_PROGRESSIVE;
8521
6e3c9717 8522 if (intel_crtc->config->limited_color_range)
3685a8f3 8523 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8524
c8203565
PZ		 8525 I915_WRITE(PIPECONF(pipe), val);
8526 POSTING_READ(PIPECONF(pipe));
8527}
8528
86d3efce
VS		 8529/*
8530 * Set up the pipe CSC unit.
8531 *
8532 * Currently only full range RGB to limited range RGB conversion
8533 * is supported, but eventually this should handle various
8534 * RGB<->YCbCr scenarios as well.
8535 */
50f3b016 8536static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8537{
8538 struct drm_device *dev = crtc->dev;
8539 struct drm_i915_private *dev_priv = dev->dev_private;
8540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8541 int pipe = intel_crtc->pipe;
8542 uint16_t coeff = 0x7800; /* 1.0 */
8543
8544 /*
8545 * TODO: Check what kind of values actually come out of the pipe
8546 * with these coeff/postoff values and adjust to get the best
8547 * accuracy. Perhaps we even need to take the bpc value into
8548 * consideration.
8549 */
8550
6e3c9717 8551 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8552 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8553
8554 /*
8555 * GY/GU and RY/RU should be the other way around according
8556 * to BSpec, but reality doesn't agree. Just set them up in
8557 * a way that results in the correct picture.
8558 */
8559 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8560 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8561
8562 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8563 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8564
8565 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8566 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8567
8568 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8569 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8570 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8571
8572 if (INTEL_INFO(dev)->gen > 6) {
8573 uint16_t postoff = 0;
8574
6e3c9717 8575 if (intel_crtc->config->limited_color_range)
32cf0cb0 8576 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8577
8578 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8579 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8580 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8581
8582 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8583 } else {
8584 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8585
6e3c9717 8586 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8587 mode |= CSC_BLACK_SCREEN_OFFSET;
8588
8589 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8590 }
8591}
8592
6ff93609 8593static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8594{
756f85cf
PZ		 8595 struct drm_device *dev = crtc->dev;
8596 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8598 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8599 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8600 uint32_t val;
8601
3eff4faa 8602 val = 0;
ee2b0b38 8603
6e3c9717 8604 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8605 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8606
6e3c9717 8607 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8608 val |= PIPECONF_INTERLACED_ILK;
8609 else
8610 val |= PIPECONF_PROGRESSIVE;
8611
702e7a56
PZ		 8612 I915_WRITE(PIPECONF(cpu_transcoder), val);
8613 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8614
8615 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8616 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8617
3cdf122c 8618 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8619 val = 0;
8620
6e3c9717 8621 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8622 case 18:
8623 val |= PIPEMISC_DITHER_6_BPC;
8624 break;
8625 case 24:
8626 val |= PIPEMISC_DITHER_8_BPC;
8627 break;
8628 case 30:
8629 val |= PIPEMISC_DITHER_10_BPC;
8630 break;
8631 case 36:
8632 val |= PIPEMISC_DITHER_12_BPC;
8633 break;
8634 default:
8635 /* Case prevented by pipe_config_set_bpp. */
8636 BUG();
8637 }
8638
6e3c9717 8639 if (intel_crtc->config->dither)
756f85cf
PZ		 8640 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8641
8642 I915_WRITE(PIPEMISC(pipe), val);
8643 }
ee2b0b38
PZ		 8644}
8645
6591c6e4 8646static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8647 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8648 intel_clock_t *clock,
8649 bool *has_reduced_clock,
8650 intel_clock_t *reduced_clock)
8651{
8652 struct drm_device *dev = crtc->dev;
8653 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8654 int refclk;
d4906093 8655 const intel_limit_t *limit;
c329a4ec 8656 bool ret;
79e53945 8657
55bb9992 8658 refclk = ironlake_get_refclk(crtc_state);
79e53945 8659
d4906093
ML		 8660 /*
8661 * Returns a set of divisors for the desired target clock with the given
8662 * refclk, or FALSE. The returned values represent the clock equation:
8663 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8664 */
a93e255f
ACO		 8665 limit = intel_limit(crtc_state, refclk);
8666 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8667 crtc_state->port_clock,
ee9300bb 8668 refclk, NULL, clock);
6591c6e4
PZ		 8669 if (!ret)
8670 return false;
cda4b7d3 8671
6591c6e4
PZ		 8672 return true;
8673}
8674
d4b1931c
PZ		 8675int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8676{
8677 /*
8678 * Account for spread spectrum to avoid
8679 * oversubscribing the link. Max center spread
8680 * is 2.5%; use 5% for safety's sake.
8681 */
8682 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8683 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8684}
8685
7429e9d4 8686static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8687{
7429e9d4 8688 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8689}
8690
de13a2e3 8691static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8692 struct intel_crtc_state *crtc_state,
7429e9d4 8693 u32 *fp,
9a7c7890 8694 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8695{
de13a2e3 8696 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8697 struct drm_device *dev = crtc->dev;
8698 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8699 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8700 struct drm_connector *connector;
55bb9992
ACO		 8701 struct drm_connector_state *connector_state;
8702 struct intel_encoder *encoder;
de13a2e3 8703 uint32_t dpll;
55bb9992 8704 int factor, num_connectors = 0, i;
09ede541 8705 bool is_lvds = false, is_sdvo = false;
79e53945 8706
da3ced29 8707 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8708 if (connector_state->crtc != crtc_state->base.crtc)
8709 continue;
8710
8711 encoder = to_intel_encoder(connector_state->best_encoder);
8712
8713 switch (encoder->type) {
79e53945
JB		 8714 case INTEL_OUTPUT_LVDS:
8715 is_lvds = true;
8716 break;
8717 case INTEL_OUTPUT_SDVO:
7d57382e 8718 case INTEL_OUTPUT_HDMI:
79e53945 8719 is_sdvo = true;
79e53945 8720 break;
6847d71b
PZ		 8721 default:
8722 break;
79e53945 8723 }
43565a06 8724
c751ce4f 8725 num_connectors++;
79e53945 8726 }
79e53945 8727
c1858123 8728 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8729 factor = 21;
8730 if (is_lvds) {
8731 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8732 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8733 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8734 factor = 25;
190f68c5 8735 } else if (crtc_state->sdvo_tv_clock)
8febb297 8736 factor = 20;
c1858123 8737
190f68c5 8738 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8739 *fp |= FP_CB_TUNE;
2c07245f 8740
9a7c7890
DV		 8741 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8742 *fp2 |= FP_CB_TUNE;
8743
5eddb70b 8744 dpll = 0;
2c07245f 8745
a07d6787
EA		 8746 if (is_lvds)
8747 dpll |= DPLLB_MODE_LVDS;
8748 else
8749 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8750
190f68c5 8751 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8752 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8753
8754 if (is_sdvo)
4a33e48d 8755 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8756 if (crtc_state->has_dp_encoder)
4a33e48d 8757 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8758
a07d6787 8759 /* compute bitmask from p1 value */
190f68c5 8760 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8761 /* also FPA1 */
190f68c5 8762 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8763
190f68c5 8764 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8765 case 5:
8766 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8767 break;
8768 case 7:
8769 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8770 break;
8771 case 10:
8772 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8773 break;
8774 case 14:
8775 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8776 break;
79e53945
JB		 8777 }
8778
b4c09f3b 8779 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8780 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8781 else
8782 dpll |= PLL_REF_INPUT_DREFCLK;
8783
959e16d6 8784 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8785}
8786
190f68c5
ACO		 8787static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8788 struct intel_crtc_state *crtc_state)
de13a2e3 8789{
c7653199 8790 struct drm_device *dev = crtc->base.dev;
de13a2e3 8791 intel_clock_t clock, reduced_clock;
cbbab5bd 8792 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8793 bool ok, has_reduced_clock = false;
8b47047b 8794 bool is_lvds = false;
e2b78267 8795 struct intel_shared_dpll *pll;
de13a2e3 8796
dd3cd74a
ACO		 8797 memset(&crtc_state->dpll_hw_state, 0,
8798 sizeof(crtc_state->dpll_hw_state));
8799
409ee761 8800 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8801
5dc5298b
PZ		 8802 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8803 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8804
190f68c5 8805 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8806 &has_reduced_clock, &reduced_clock);
190f68c5 8807 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8808 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8809 return -EINVAL;
79e53945 8810 }
f47709a9 8811 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8812 if (!crtc_state->clock_set) {
8813 crtc_state->dpll.n = clock.n;
8814 crtc_state->dpll.m1 = clock.m1;
8815 crtc_state->dpll.m2 = clock.m2;
8816 crtc_state->dpll.p1 = clock.p1;
8817 crtc_state->dpll.p2 = clock.p2;
f47709a9 8818 }
79e53945 8819
5dc5298b 8820 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8821 if (crtc_state->has_pch_encoder) {
8822 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8823 if (has_reduced_clock)
7429e9d4 8824 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8825
190f68c5 8826 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8827 &fp, &reduced_clock,
8828 has_reduced_clock ? &fp2 : NULL);
8829
190f68c5
ACO		 8830 crtc_state->dpll_hw_state.dpll = dpll;
8831 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8832 if (has_reduced_clock)
190f68c5 8833 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8834 else
190f68c5 8835 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8836
190f68c5 8837 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8838 if (pll == NULL) {
84f44ce7 8839 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8840 pipe_name(crtc->pipe));
4b645f14
JB		 8841 return -EINVAL;
8842 }
3fb37703 8843 }
79e53945 8844
ab585dea 8845 if (is_lvds && has_reduced_clock)
c7653199 8846 crtc->lowfreq_avail = true;
bcd644e0 8847 else
c7653199 8848 crtc->lowfreq_avail = false;
e2b78267 8849
c8f7a0db 8850 return 0;
79e53945
JB		 8851}
8852
eb14cb74
VS		 8853static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8854 struct intel_link_m_n *m_n)
8855{
8856 struct drm_device *dev = crtc->base.dev;
8857 struct drm_i915_private *dev_priv = dev->dev_private;
8858 enum pipe pipe = crtc->pipe;
8859
8860 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8861 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8862 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8863 & ~TU_SIZE_MASK;
8864 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8865 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8866 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8867}
8868
8869static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8870 enum transcoder transcoder,
b95af8be
VK		 8871 struct intel_link_m_n *m_n,
8872 struct intel_link_m_n *m2_n2)
72419203
DV		 8873{
8874 struct drm_device *dev = crtc->base.dev;
8875 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8876 enum pipe pipe = crtc->pipe;
72419203 8877
eb14cb74
VS		 8878 if (INTEL_INFO(dev)->gen >= 5) {
8879 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8880 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8881 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8882 & ~TU_SIZE_MASK;
8883 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8884 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8885 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8886 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8887 * gen < 8) and if DRRS is supported (to make sure the
8888 * registers are not unnecessarily read).
8889 */
8890 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8891 crtc->config->has_drrs) {
b95af8be
VK		 8892 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8893 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8894 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8895 & ~TU_SIZE_MASK;
8896 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8897 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8898 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8899 }
eb14cb74
VS		 8900 } else {
8901 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8902 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8903 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8904 & ~TU_SIZE_MASK;
8905 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8906 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8907 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8908 }
8909}
8910
8911void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8912 struct intel_crtc_state *pipe_config)
eb14cb74 8913{
681a8504 8914 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8915 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8916 else
8917 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8918 &pipe_config->dp_m_n,
8919 &pipe_config->dp_m2_n2);
eb14cb74 8920}
72419203 8921
eb14cb74 8922static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8923 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8924{
8925 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8926 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8927}
8928
bd2e244f 8929static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8930 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8931{
8932 struct drm_device *dev = crtc->base.dev;
8933 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8934 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8935 uint32_t ps_ctrl = 0;
8936 int id = -1;
8937 int i;
bd2e244f 8938
a1b2278e
CK		 8939 /* find scaler attached to this pipe */
8940 for (i = 0; i < crtc->num_scalers; i++) {
8941 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8942 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8943 id = i;
8944 pipe_config->pch_pfit.enabled = true;
8945 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8946 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8947 break;
8948 }
8949 }
bd2e244f 8950
a1b2278e
CK		 8951 scaler_state->scaler_id = id;
8952 if (id >= 0) {
8953 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8954 } else {
8955 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8956 }
8957}
8958
5724dbd1
DL		 8959static void
8960skylake_get_initial_plane_config(struct intel_crtc *crtc,
8961 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8962{
8963 struct drm_device *dev = crtc->base.dev;
8964 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8965 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8966 int pipe = crtc->pipe;
8967 int fourcc, pixel_format;
6761dd31 8968 unsigned int aligned_height;
bc8d7dff 8969 struct drm_framebuffer *fb;
1b842c89 8970 struct intel_framebuffer *intel_fb;
bc8d7dff 8971
d9806c9f 8972 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8973 if (!intel_fb) {
bc8d7dff
DL		 8974 DRM_DEBUG_KMS("failed to alloc fb\n");
8975 return;
8976 }
8977
1b842c89
DL		 8978 fb = &intel_fb->base;
8979
bc8d7dff 8980 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8981 if (!(val & PLANE_CTL_ENABLE))
8982 goto error;
8983
bc8d7dff
DL		 8984 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8985 fourcc = skl_format_to_fourcc(pixel_format,
8986 val & PLANE_CTL_ORDER_RGBX,
8987 val & PLANE_CTL_ALPHA_MASK);
8988 fb->pixel_format = fourcc;
8989 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8990
40f46283
DL		 8991 tiling = val & PLANE_CTL_TILED_MASK;
8992 switch (tiling) {
8993 case PLANE_CTL_TILED_LINEAR:
8994 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8995 break;
8996 case PLANE_CTL_TILED_X:
8997 plane_config->tiling = I915_TILING_X;
8998 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8999 break;
9000 case PLANE_CTL_TILED_Y:
9001 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9002 break;
9003 case PLANE_CTL_TILED_YF:
9004 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9005 break;
9006 default:
9007 MISSING_CASE(tiling);
9008 goto error;
9009 }
9010
bc8d7dff
DL		 9011 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9012 plane_config->base = base;
9013
9014 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9015
9016 val = I915_READ(PLANE_SIZE(pipe, 0));
9017 fb->height = ((val >> 16) & 0xfff) + 1;
9018 fb->width = ((val >> 0) & 0x1fff) + 1;
9019
9020 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9021 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9022 fb->pixel_format);
bc8d7dff
DL		 9023 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9024
9025 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9026 fb->pixel_format,
9027 fb->modifier[0]);
bc8d7dff 9028
f37b5c2b 9029 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9030
9031 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9032 pipe_name(pipe), fb->width, fb->height,
9033 fb->bits_per_pixel, base, fb->pitches[0],
9034 plane_config->size);
9035
2d14030b 9036 plane_config->fb = intel_fb;
bc8d7dff
DL		 9037 return;
9038
9039error:
9040 kfree(fb);
9041}
9042
2fa2fe9a 9043static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9044 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9045{
9046 struct drm_device *dev = crtc->base.dev;
9047 struct drm_i915_private *dev_priv = dev->dev_private;
9048 uint32_t tmp;
9049
9050 tmp = I915_READ(PF_CTL(crtc->pipe));
9051
9052 if (tmp & PF_ENABLE) {
fd4daa9c 9053 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9054 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9055 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9056
9057 /* We currently do not free assignements of panel fitters on
9058 * ivb/hsw (since we don't use the higher upscaling modes which
9059 * differentiates them) so just WARN about this case for now. */
9060 if (IS_GEN7(dev)) {
9061 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9062 PF_PIPE_SEL_IVB(crtc->pipe));
9063 }
2fa2fe9a 9064 }
79e53945
JB		 9065}
9066
5724dbd1
DL		 9067static void
9068ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9069 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9070{
9071 struct drm_device *dev = crtc->base.dev;
9072 struct drm_i915_private *dev_priv = dev->dev_private;
9073 u32 val, base, offset;
aeee5a49 9074 int pipe = crtc->pipe;
4c6baa59 9075 int fourcc, pixel_format;
6761dd31 9076 unsigned int aligned_height;
b113d5ee 9077 struct drm_framebuffer *fb;
1b842c89 9078 struct intel_framebuffer *intel_fb;
4c6baa59 9079
42a7b088
DL		 9080 val = I915_READ(DSPCNTR(pipe));
9081 if (!(val & DISPLAY_PLANE_ENABLE))
9082 return;
9083
d9806c9f 9084 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9085 if (!intel_fb) {
4c6baa59
JB		 9086 DRM_DEBUG_KMS("failed to alloc fb\n");
9087 return;
9088 }
9089
1b842c89
DL		 9090 fb = &intel_fb->base;
9091
18c5247e
DV		 9092 if (INTEL_INFO(dev)->gen >= 4) {
9093 if (val & DISPPLANE_TILED) {
49af449b 9094 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9095 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9096 }
9097 }
4c6baa59
JB		 9098
9099 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9100 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9101 fb->pixel_format = fourcc;
9102 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9103
aeee5a49 9104 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9105 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9106 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9107 } else {
49af449b 9108 if (plane_config->tiling)
aeee5a49 9109 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9110 else
aeee5a49 9111 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9112 }
9113 plane_config->base = base;
9114
9115 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9116 fb->width = ((val >> 16) & 0xfff) + 1;
9117 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9118
9119 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9120 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9121
b113d5ee 9122 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9123 fb->pixel_format,
9124 fb->modifier[0]);
4c6baa59 9125
f37b5c2b 9126 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9127
2844a921
DL		 9128 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9129 pipe_name(pipe), fb->width, fb->height,
9130 fb->bits_per_pixel, base, fb->pitches[0],
9131 plane_config->size);
b113d5ee 9132
2d14030b 9133 plane_config->fb = intel_fb;
4c6baa59
JB		 9134}
9135
0e8ffe1b 9136static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9137 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9138{
9139 struct drm_device *dev = crtc->base.dev;
9140 struct drm_i915_private *dev_priv = dev->dev_private;
9141 uint32_t tmp;
9142
f458ebbc
DV		 9143 if (!intel_display_power_is_enabled(dev_priv,
9144 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9145 return false;
9146
e143a21c 9147 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9148 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9149
0e8ffe1b
DV		 9150 tmp = I915_READ(PIPECONF(crtc->pipe));
9151 if (!(tmp & PIPECONF_ENABLE))
9152 return false;
9153
42571aef
VS		 9154 switch (tmp & PIPECONF_BPC_MASK) {
9155 case PIPECONF_6BPC:
9156 pipe_config->pipe_bpp = 18;
9157 break;
9158 case PIPECONF_8BPC:
9159 pipe_config->pipe_bpp = 24;
9160 break;
9161 case PIPECONF_10BPC:
9162 pipe_config->pipe_bpp = 30;
9163 break;
9164 case PIPECONF_12BPC:
9165 pipe_config->pipe_bpp = 36;
9166 break;
9167 default:
9168 break;
9169 }
9170
b5a9fa09
DV		 9171 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9172 pipe_config->limited_color_range = true;
9173
ab9412ba 9174 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9175 struct intel_shared_dpll *pll;
9176
88adfff1
DV		 9177 pipe_config->has_pch_encoder = true;
9178
627eb5a3
DV		 9179 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9180 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9181 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9182
9183 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9184
c0d43d62 9185 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9186 pipe_config->shared_dpll =
9187 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9188 } else {
9189 tmp = I915_READ(PCH_DPLL_SEL);
9190 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9191 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9192 else
9193 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9194 }
66e985c0
DV		 9195
9196 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9197
9198 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9199 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9200
9201 tmp = pipe_config->dpll_hw_state.dpll;
9202 pipe_config->pixel_multiplier =
9203 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9204 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9205
9206 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9207 } else {
9208 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9209 }
9210
1bd1bd80
DV		 9211 intel_get_pipe_timings(crtc, pipe_config);
9212
2fa2fe9a
DV		 9213 ironlake_get_pfit_config(crtc, pipe_config);
9214
0e8ffe1b
DV		 9215 return true;
9216}
9217
be256dc7
PZ		 9218static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9219{
9220 struct drm_device *dev = dev_priv->dev;
be256dc7 9221 struct intel_crtc *crtc;
be256dc7 9222
d3fcc808 9223 for_each_intel_crtc(dev, crtc)
e2c719b7 9224 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9225 pipe_name(crtc->pipe));
9226
e2c719b7
RC		 9227 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9228 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9229 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9230 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9231 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9232 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9233 "CPU PWM1 enabled\n");
c5107b87 9234 if (IS_HASWELL(dev))
e2c719b7 9235 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9236 "CPU PWM2 enabled\n");
e2c719b7 9237 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9238 "PCH PWM1 enabled\n");
e2c719b7 9239 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9240 "Utility pin enabled\n");
e2c719b7 9241 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9242
9926ada1
PZ		 9243 /*
9244 * In theory we can still leave IRQs enabled, as long as only the HPD
9245 * interrupts remain enabled. We used to check for that, but since it's
9246 * gen-specific and since we only disable LCPLL after we fully disable
9247 * the interrupts, the check below should be enough.
9248 */
e2c719b7 9249 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9250}
9251
9ccd5aeb
PZ		 9252static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9253{
9254 struct drm_device *dev = dev_priv->dev;
9255
9256 if (IS_HASWELL(dev))
9257 return I915_READ(D_COMP_HSW);
9258 else
9259 return I915_READ(D_COMP_BDW);
9260}
9261
3c4c9b81
PZ		 9262static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9263{
9264 struct drm_device *dev = dev_priv->dev;
9265
9266 if (IS_HASWELL(dev)) {
9267 mutex_lock(&dev_priv->rps.hw_lock);
9268 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9269 val))
f475dadf 9270 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9271 mutex_unlock(&dev_priv->rps.hw_lock);
9272 } else {
9ccd5aeb
PZ		 9273 I915_WRITE(D_COMP_BDW, val);
9274 POSTING_READ(D_COMP_BDW);
3c4c9b81 9275 }
be256dc7
PZ		 9276}
9277
9278/*
9279 * This function implements pieces of two sequences from BSpec:
9280 * - Sequence for display software to disable LCPLL
9281 * - Sequence for display software to allow package C8+
9282 * The steps implemented here are just the steps that actually touch the LCPLL
9283 * register. Callers should take care of disabling all the display engine
9284 * functions, doing the mode unset, fixing interrupts, etc.
9285 */
6ff58d53
PZ		 9286static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9287 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9288{
9289 uint32_t val;
9290
9291 assert_can_disable_lcpll(dev_priv);
9292
9293 val = I915_READ(LCPLL_CTL);
9294
9295 if (switch_to_fclk) {
9296 val |= LCPLL_CD_SOURCE_FCLK;
9297 I915_WRITE(LCPLL_CTL, val);
9298
9299 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9300 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9301 DRM_ERROR("Switching to FCLK failed\n");
9302
9303 val = I915_READ(LCPLL_CTL);
9304 }
9305
9306 val |= LCPLL_PLL_DISABLE;
9307 I915_WRITE(LCPLL_CTL, val);
9308 POSTING_READ(LCPLL_CTL);
9309
9310 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9311 DRM_ERROR("LCPLL still locked\n");
9312
9ccd5aeb 9313 val = hsw_read_dcomp(dev_priv);
be256dc7 9314 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9315 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9316 ndelay(100);
9317
9ccd5aeb
PZ		 9318 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9319 1))
be256dc7
PZ		 9320 DRM_ERROR("D_COMP RCOMP still in progress\n");
9321
9322 if (allow_power_down) {
9323 val = I915_READ(LCPLL_CTL);
9324 val |= LCPLL_POWER_DOWN_ALLOW;
9325 I915_WRITE(LCPLL_CTL, val);
9326 POSTING_READ(LCPLL_CTL);
9327 }
9328}
9329
9330/*
9331 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9332 * source.
9333 */
6ff58d53 9334static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9335{
9336 uint32_t val;
9337
9338 val = I915_READ(LCPLL_CTL);
9339
9340 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9341 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9342 return;
9343
a8a8bd54
PZ		 9344 /*
9345 * Make sure we're not on PC8 state before disabling PC8, otherwise
9346 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9347 */
59bad947 9348 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9349
be256dc7
PZ		 9350 if (val & LCPLL_POWER_DOWN_ALLOW) {
9351 val &= ~LCPLL_POWER_DOWN_ALLOW;
9352 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9353 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9354 }
9355
9ccd5aeb 9356 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9357 val |= D_COMP_COMP_FORCE;
9358 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9359 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9360
9361 val = I915_READ(LCPLL_CTL);
9362 val &= ~LCPLL_PLL_DISABLE;
9363 I915_WRITE(LCPLL_CTL, val);
9364
9365 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9366 DRM_ERROR("LCPLL not locked yet\n");
9367
9368 if (val & LCPLL_CD_SOURCE_FCLK) {
9369 val = I915_READ(LCPLL_CTL);
9370 val &= ~LCPLL_CD_SOURCE_FCLK;
9371 I915_WRITE(LCPLL_CTL, val);
9372
9373 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9374 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9375 DRM_ERROR("Switching back to LCPLL failed\n");
9376 }
215733fa 9377
59bad947 9378 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9379 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9380}
9381
765dab67
PZ		 9382/*
9383 * Package states C8 and deeper are really deep PC states that can only be
9384 * reached when all the devices on the system allow it, so even if the graphics
9385 * device allows PC8+, it doesn't mean the system will actually get to these
9386 * states. Our driver only allows PC8+ when going into runtime PM.
9387 *
9388 * The requirements for PC8+ are that all the outputs are disabled, the power
9389 * well is disabled and most interrupts are disabled, and these are also
9390 * requirements for runtime PM. When these conditions are met, we manually do
9391 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9392 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9393 * hang the machine.
9394 *
9395 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9396 * the state of some registers, so when we come back from PC8+ we need to
9397 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9398 * need to take care of the registers kept by RC6. Notice that this happens even
9399 * if we don't put the device in PCI D3 state (which is what currently happens
9400 * because of the runtime PM support).
9401 *
9402 * For more, read "Display Sequences for Package C8" on the hardware
9403 * documentation.
9404 */
a14cb6fc 9405void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9406{
c67a470b
PZ		 9407 struct drm_device *dev = dev_priv->dev;
9408 uint32_t val;
9409
c67a470b
PZ		 9410 DRM_DEBUG_KMS("Enabling package C8+\n");
9411
c2699524 9412 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9413 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9414 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9415 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9416 }
9417
9418 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9419 hsw_disable_lcpll(dev_priv, true, true);
9420}
9421
a14cb6fc 9422void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9423{
9424 struct drm_device *dev = dev_priv->dev;
9425 uint32_t val;
9426
c67a470b
PZ		 9427 DRM_DEBUG_KMS("Disabling package C8+\n");
9428
9429 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9430 lpt_init_pch_refclk(dev);
9431
c2699524 9432 if (HAS_PCH_LPT_LP(dev)) {
c67a470b
PZ		 9433 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9434 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9435 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9436 }
9437
9438 intel_prepare_ddi(dev);
c67a470b
PZ		 9439}
9440
27c329ed 9441static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9442{
a821fc46 9443 struct drm_device *dev = old_state->dev;
27c329ed 9444 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9445
27c329ed 9446 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9447}
9448
b432e5cf 9449/* compute the max rate for new configuration */
27c329ed 9450static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9451{
b432e5cf 9452 struct intel_crtc *intel_crtc;
27c329ed 9453 struct intel_crtc_state *crtc_state;
b432e5cf 9454 int max_pixel_rate = 0;
b432e5cf 9455
27c329ed
ML		 9456 for_each_intel_crtc(state->dev, intel_crtc) {
9457 int pixel_rate;
9458
9459 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9460 if (IS_ERR(crtc_state))
9461 return PTR_ERR(crtc_state);
9462
9463 if (!crtc_state->base.enable)
b432e5cf
VS		 9464 continue;
9465
27c329ed 9466 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9467
9468 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9469 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9470 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9471
9472 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9473 }
9474
9475 return max_pixel_rate;
9476}
9477
9478static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9479{
9480 struct drm_i915_private *dev_priv = dev->dev_private;
9481 uint32_t val, data;
9482 int ret;
9483
9484 if (WARN((I915_READ(LCPLL_CTL) &
9485 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9486 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9487 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9488 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9489 "trying to change cdclk frequency with cdclk not enabled\n"))
9490 return;
9491
9492 mutex_lock(&dev_priv->rps.hw_lock);
9493 ret = sandybridge_pcode_write(dev_priv,
9494 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9495 mutex_unlock(&dev_priv->rps.hw_lock);
9496 if (ret) {
9497 DRM_ERROR("failed to inform pcode about cdclk change\n");
9498 return;
9499 }
9500
9501 val = I915_READ(LCPLL_CTL);
9502 val |= LCPLL_CD_SOURCE_FCLK;
9503 I915_WRITE(LCPLL_CTL, val);
9504
9505 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9506 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9507 DRM_ERROR("Switching to FCLK failed\n");
9508
9509 val = I915_READ(LCPLL_CTL);
9510 val &= ~LCPLL_CLK_FREQ_MASK;
9511
9512 switch (cdclk) {
9513 case 450000:
9514 val |= LCPLL_CLK_FREQ_450;
9515 data = 0;
9516 break;
9517 case 540000:
9518 val |= LCPLL_CLK_FREQ_54O_BDW;
9519 data = 1;
9520 break;
9521 case 337500:
9522 val |= LCPLL_CLK_FREQ_337_5_BDW;
9523 data = 2;
9524 break;
9525 case 675000:
9526 val |= LCPLL_CLK_FREQ_675_BDW;
9527 data = 3;
9528 break;
9529 default:
9530 WARN(1, "invalid cdclk frequency\n");
9531 return;
9532 }
9533
9534 I915_WRITE(LCPLL_CTL, val);
9535
9536 val = I915_READ(LCPLL_CTL);
9537 val &= ~LCPLL_CD_SOURCE_FCLK;
9538 I915_WRITE(LCPLL_CTL, val);
9539
9540 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9541 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9542 DRM_ERROR("Switching back to LCPLL failed\n");
9543
9544 mutex_lock(&dev_priv->rps.hw_lock);
9545 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9546 mutex_unlock(&dev_priv->rps.hw_lock);
9547
9548 intel_update_cdclk(dev);
9549
9550 WARN(cdclk != dev_priv->cdclk_freq,
9551 "cdclk requested %d kHz but got %d kHz\n",
9552 cdclk, dev_priv->cdclk_freq);
9553}
9554
27c329ed 9555static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9556{
27c329ed
ML		 9557 struct drm_i915_private *dev_priv = to_i915(state->dev);
9558 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9559 int cdclk;
9560
9561 /*
9562 * FIXME should also account for plane ratio
9563 * once 64bpp pixel formats are supported.
9564 */
27c329ed 9565 if (max_pixclk > 540000)
b432e5cf 9566 cdclk = 675000;
27c329ed 9567 else if (max_pixclk > 450000)
b432e5cf 9568 cdclk = 540000;
27c329ed 9569 else if (max_pixclk > 337500)
b432e5cf
VS		 9570 cdclk = 450000;
9571 else
9572 cdclk = 337500;
9573
9574 /*
9575 * FIXME move the cdclk caclulation to
9576 * compute_config() so we can fail gracegully.
9577 */
9578 if (cdclk > dev_priv->max_cdclk_freq) {
9579 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9580 cdclk, dev_priv->max_cdclk_freq);
9581 cdclk = dev_priv->max_cdclk_freq;
9582 }
9583
27c329ed 9584 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9585
9586 return 0;
9587}
9588
27c329ed 9589static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9590{
27c329ed
ML		 9591 struct drm_device *dev = old_state->dev;
9592 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9593
27c329ed 9594 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9595}
9596
190f68c5
ACO		 9597static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9598 struct intel_crtc_state *crtc_state)
09b4ddf9 9599{
190f68c5 9600 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9601 return -EINVAL;
716c2e55 9602
c7653199 9603 crtc->lowfreq_avail = false;
644cef34 9604
c8f7a0db 9605 return 0;
79e53945
JB		 9606}
9607
3760b59c
S		 9608static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9609 enum port port,
9610 struct intel_crtc_state *pipe_config)
9611{
9612 switch (port) {
9613 case PORT_A:
9614 pipe_config->ddi_pll_sel = SKL_DPLL0;
9615 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9616 break;
9617 case PORT_B:
9618 pipe_config->ddi_pll_sel = SKL_DPLL1;
9619 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9620 break;
9621 case PORT_C:
9622 pipe_config->ddi_pll_sel = SKL_DPLL2;
9623 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9624 break;
9625 default:
9626 DRM_ERROR("Incorrect port type\n");
9627 }
9628}
9629
96b7dfb7
S		 9630static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9631 enum port port,
5cec258b 9632 struct intel_crtc_state *pipe_config)
96b7dfb7 9633{
3148ade7 9634 u32 temp, dpll_ctl1;
96b7dfb7
S		 9635
9636 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9637 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9638
9639 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9640 case SKL_DPLL0:
9641 /*
9642 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9643 * of the shared DPLL framework and thus needs to be read out
9644 * separately
9645 */
9646 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9647 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9648 break;
96b7dfb7
S		 9649 case SKL_DPLL1:
9650 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9651 break;
9652 case SKL_DPLL2:
9653 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9654 break;
9655 case SKL_DPLL3:
9656 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9657 break;
96b7dfb7
S		 9658 }
9659}
9660
7d2c8175
DL		 9661static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9662 enum port port,
5cec258b 9663 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9664{
9665 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9666
9667 switch (pipe_config->ddi_pll_sel) {
9668 case PORT_CLK_SEL_WRPLL1:
9669 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9670 break;
9671 case PORT_CLK_SEL_WRPLL2:
9672 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9673 break;
9674 }
9675}
9676
26804afd 9677static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9678 struct intel_crtc_state *pipe_config)
26804afd
DV		 9679{
9680 struct drm_device *dev = crtc->base.dev;
9681 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9682 struct intel_shared_dpll *pll;
26804afd
DV		 9683 enum port port;
9684 uint32_t tmp;
9685
9686 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9687
9688 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9689
96b7dfb7
S		 9690 if (IS_SKYLAKE(dev))
9691 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9692 else if (IS_BROXTON(dev))
9693 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9694 else
9695 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9696
d452c5b6
DV		 9697 if (pipe_config->shared_dpll >= 0) {
9698 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9699
9700 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9701 &pipe_config->dpll_hw_state));
9702 }
9703
26804afd
DV		 9704 /*
9705 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9706 * DDI E. So just check whether this pipe is wired to DDI E and whether
9707 * the PCH transcoder is on.
9708 */
ca370455
DL		 9709 if (INTEL_INFO(dev)->gen < 9 &&
9710 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9711 pipe_config->has_pch_encoder = true;
9712
9713 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9714 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9715 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9716
9717 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9718 }
9719}
9720
0e8ffe1b 9721static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9722 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9723{
9724 struct drm_device *dev = crtc->base.dev;
9725 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9726 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9727 uint32_t tmp;
9728
f458ebbc 9729 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9730 POWER_DOMAIN_PIPE(crtc->pipe)))
9731 return false;
9732
e143a21c 9733 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9734 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9735
eccb140b
DV		 9736 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9737 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9738 enum pipe trans_edp_pipe;
9739 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9740 default:
9741 WARN(1, "unknown pipe linked to edp transcoder\n");
9742 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9743 case TRANS_DDI_EDP_INPUT_A_ON:
9744 trans_edp_pipe = PIPE_A;
9745 break;
9746 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9747 trans_edp_pipe = PIPE_B;
9748 break;
9749 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9750 trans_edp_pipe = PIPE_C;
9751 break;
9752 }
9753
9754 if (trans_edp_pipe == crtc->pipe)
9755 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9756 }
9757
f458ebbc 9758 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9759 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9760 return false;
9761
eccb140b 9762 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9763 if (!(tmp & PIPECONF_ENABLE))
9764 return false;
9765
26804afd 9766 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9767
1bd1bd80
DV		 9768 intel_get_pipe_timings(crtc, pipe_config);
9769
a1b2278e
CK		 9770 if (INTEL_INFO(dev)->gen >= 9) {
9771 skl_init_scalers(dev, crtc, pipe_config);
9772 }
9773
2fa2fe9a 9774 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9775
9776 if (INTEL_INFO(dev)->gen >= 9) {
9777 pipe_config->scaler_state.scaler_id = -1;
9778 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9779 }
9780
bd2e244f 9781 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
1c132b44 9782 if (INTEL_INFO(dev)->gen >= 9)
bd2e244f 9783 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9784 else
1c132b44 9785 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9786 }
88adfff1 9787
e59150dc
JB		 9788 if (IS_HASWELL(dev))
9789 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9790 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9791
ebb69c95
CT		 9792 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9793 pipe_config->pixel_multiplier =
9794 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9795 } else {
9796 pipe_config->pixel_multiplier = 1;
9797 }
6c49f241 9798
0e8ffe1b
DV		 9799 return true;
9800}
9801
560b85bb
CW		 9802static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9803{
9804 struct drm_device *dev = crtc->dev;
9805 struct drm_i915_private *dev_priv = dev->dev_private;
9806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9807 uint32_t cntl = 0, size = 0;
560b85bb 9808
dc41c154 9809 if (base) {
3dd512fb
MR		 9810 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9811 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9812 unsigned int stride = roundup_pow_of_two(width) * 4;
9813
9814 switch (stride) {
9815 default:
9816 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9817 width, stride);
9818 stride = 256;
9819 /* fallthrough */
9820 case 256:
9821 case 512:
9822 case 1024:
9823 case 2048:
9824 break;
4b0e333e
CW		 9825 }
9826
dc41c154
VS		 9827 cntl |= CURSOR_ENABLE |
9828 CURSOR_GAMMA_ENABLE |
9829 CURSOR_FORMAT_ARGB |
9830 CURSOR_STRIDE(stride);
9831
9832 size = (height << 12) | width;
4b0e333e 9833 }
560b85bb 9834
dc41c154
VS		 9835 if (intel_crtc->cursor_cntl != 0 &&
9836 (intel_crtc->cursor_base != base ||
9837 intel_crtc->cursor_size != size ||
9838 intel_crtc->cursor_cntl != cntl)) {
9839 /* On these chipsets we can only modify the base/size/stride
9840 * whilst the cursor is disabled.
9841 */
9842 I915_WRITE(_CURACNTR, 0);
4b0e333e 9843 POSTING_READ(_CURACNTR);
dc41c154 9844 intel_crtc->cursor_cntl = 0;
4b0e333e 9845 }
560b85bb 9846
99d1f387 9847 if (intel_crtc->cursor_base != base) {
9db4a9c7 9848 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9849 intel_crtc->cursor_base = base;
9850 }
4726e0b0 9851
dc41c154
VS		 9852 if (intel_crtc->cursor_size != size) {
9853 I915_WRITE(CURSIZE, size);
9854 intel_crtc->cursor_size = size;
4b0e333e 9855 }
560b85bb 9856
4b0e333e 9857 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9858 I915_WRITE(_CURACNTR, cntl);
9859 POSTING_READ(_CURACNTR);
4b0e333e 9860 intel_crtc->cursor_cntl = cntl;
560b85bb 9861 }
560b85bb
CW		 9862}
9863
560b85bb 9864static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9865{
9866 struct drm_device *dev = crtc->dev;
9867 struct drm_i915_private *dev_priv = dev->dev_private;
9868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9869 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9870 uint32_t cntl;
9871
9872 cntl = 0;
9873 if (base) {
9874 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9875 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9876 case 64:
9877 cntl |= CURSOR_MODE_64_ARGB_AX;
9878 break;
9879 case 128:
9880 cntl |= CURSOR_MODE_128_ARGB_AX;
9881 break;
9882 case 256:
9883 cntl |= CURSOR_MODE_256_ARGB_AX;
9884 break;
9885 default:
3dd512fb 9886 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9887 return;
65a21cd6 9888 }
4b0e333e 9889 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9890
9891 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9892 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9893 }
65a21cd6 9894
8e7d688b 9895 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9896 cntl |= CURSOR_ROTATE_180;
9897
4b0e333e
CW		 9898 if (intel_crtc->cursor_cntl != cntl) {
9899 I915_WRITE(CURCNTR(pipe), cntl);
9900 POSTING_READ(CURCNTR(pipe));
9901 intel_crtc->cursor_cntl = cntl;
65a21cd6 9902 }
4b0e333e 9903
65a21cd6 9904 /* and commit changes on next vblank */
5efb3e28
VS		 9905 I915_WRITE(CURBASE(pipe), base);
9906 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9907
9908 intel_crtc->cursor_base = base;
65a21cd6
JB		 9909}
9910
cda4b7d3 9911/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9912static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9913 bool on)
cda4b7d3
CW		 9914{
9915 struct drm_device *dev = crtc->dev;
9916 struct drm_i915_private *dev_priv = dev->dev_private;
9917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9918 int pipe = intel_crtc->pipe;
9b4101be
ML		 9919 struct drm_plane_state *cursor_state = crtc->cursor->state;
9920 int x = cursor_state->crtc_x;
9921 int y = cursor_state->crtc_y;
d6e4db15 9922 u32 base = 0, pos = 0;
cda4b7d3 9923
d6e4db15 9924 if (on)
cda4b7d3 9925 base = intel_crtc->cursor_addr;
cda4b7d3 9926
6e3c9717 9927 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9928 base = 0;
9929
6e3c9717 9930 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9931 base = 0;
9932
9933 if (x < 0) {
9b4101be 9934 if (x + cursor_state->crtc_w <= 0)
cda4b7d3
CW		 9935 base = 0;
9936
9937 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9938 x = -x;
9939 }
9940 pos |= x << CURSOR_X_SHIFT;
9941
9942 if (y < 0) {
9b4101be 9943 if (y + cursor_state->crtc_h <= 0)
cda4b7d3
CW		 9944 base = 0;
9945
9946 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9947 y = -y;
9948 }
9949 pos |= y << CURSOR_Y_SHIFT;
9950
4b0e333e 9951 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9952 return;
9953
5efb3e28
VS		 9954 I915_WRITE(CURPOS(pipe), pos);
9955
4398ad45
VS		 9956 /* ILK+ do this automagically */
9957 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9958 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9b4101be
ML		 9959 base += (cursor_state->crtc_h *
9960 cursor_state->crtc_w - 1) * 4;
4398ad45
VS		 9961 }
9962
8ac54669 9963 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9964 i845_update_cursor(crtc, base);
9965 else
9966 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9967}
9968
dc41c154
VS		 9969static bool cursor_size_ok(struct drm_device *dev,
9970 uint32_t width, uint32_t height)
9971{
9972 if (width == 0 || height == 0)
9973 return false;
9974
9975 /*
9976 * 845g/865g are special in that they are only limited by
9977 * the width of their cursors, the height is arbitrary up to
9978 * the precision of the register. Everything else requires
9979 * square cursors, limited to a few power-of-two sizes.
9980 */
9981 if (IS_845G(dev) || IS_I865G(dev)) {
9982 if ((width & 63) != 0)
9983 return false;
9984
9985 if (width > (IS_845G(dev) ? 64 : 512))
9986 return false;
9987
9988 if (height > 1023)
9989 return false;
9990 } else {
9991 switch (width | height) {
9992 case 256:
9993 case 128:
9994 if (IS_GEN2(dev))
9995 return false;
9996 case 64:
9997 break;
9998 default:
9999 return false;
10000 }
10001 }
10002
10003 return true;
10004}
10005
79e53945 10006static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10007 u16 *blue, uint32_t start, uint32_t size)
79e53945 10008{
7203425a 10009 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10011
7203425a 10012 for (i = start; i < end; i++) {
79e53945
JB		 10013 intel_crtc->lut_r[i] = red[i] >> 8;
10014 intel_crtc->lut_g[i] = green[i] >> 8;
10015 intel_crtc->lut_b[i] = blue[i] >> 8;
10016 }
10017
10018 intel_crtc_load_lut(crtc);
10019}
10020
79e53945
JB		 10021/* VESA 640x480x72Hz mode to set on the pipe */
10022static struct drm_display_mode load_detect_mode = {
10023 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10024 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10025};
10026
a8bb6818
DV		 10027struct drm_framebuffer *
10028__intel_framebuffer_create(struct drm_device *dev,
10029 struct drm_mode_fb_cmd2 *mode_cmd,
10030 struct drm_i915_gem_object *obj)
d2dff872
CW		 10031{
10032 struct intel_framebuffer *intel_fb;
10033 int ret;
10034
10035 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10036 if (!intel_fb) {
6ccb81f2 10037 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10038 return ERR_PTR(-ENOMEM);
10039 }
10040
10041 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10042 if (ret)
10043 goto err;
d2dff872
CW		 10044
10045 return &intel_fb->base;
dd4916c5 10046err:
6ccb81f2 10047 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10048 kfree(intel_fb);
10049
10050 return ERR_PTR(ret);
d2dff872
CW		 10051}
10052
b5ea642a 10053static struct drm_framebuffer *
a8bb6818
DV		 10054intel_framebuffer_create(struct drm_device *dev,
10055 struct drm_mode_fb_cmd2 *mode_cmd,
10056 struct drm_i915_gem_object *obj)
10057{
10058 struct drm_framebuffer *fb;
10059 int ret;
10060
10061 ret = i915_mutex_lock_interruptible(dev);
10062 if (ret)
10063 return ERR_PTR(ret);
10064 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10065 mutex_unlock(&dev->struct_mutex);
10066
10067 return fb;
10068}
10069
d2dff872
CW		 10070static u32
10071intel_framebuffer_pitch_for_width(int width, int bpp)
10072{
10073 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10074 return ALIGN(pitch, 64);
10075}
10076
10077static u32
10078intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10079{
10080 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10081 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10082}
10083
10084static struct drm_framebuffer *
10085intel_framebuffer_create_for_mode(struct drm_device *dev,
10086 struct drm_display_mode *mode,
10087 int depth, int bpp)
10088{
10089 struct drm_i915_gem_object *obj;
0fed39bd 10090 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10091
10092 obj = i915_gem_alloc_object(dev,
10093 intel_framebuffer_size_for_mode(mode, bpp));
10094 if (obj == NULL)
10095 return ERR_PTR(-ENOMEM);
10096
10097 mode_cmd.width = mode->hdisplay;
10098 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10099 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10100 bpp);
5ca0c34a 10101 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10102
10103 return intel_framebuffer_create(dev, &mode_cmd, obj);
10104}
10105
10106static struct drm_framebuffer *
10107mode_fits_in_fbdev(struct drm_device *dev,
10108 struct drm_display_mode *mode)
10109{
0695726e 10110#ifdef CONFIG_DRM_FBDEV_EMULATION
d2dff872
CW		 10111 struct drm_i915_private *dev_priv = dev->dev_private;
10112 struct drm_i915_gem_object *obj;
10113 struct drm_framebuffer *fb;
10114
4c0e5528 10115 if (!dev_priv->fbdev)
d2dff872
CW		 10116 return NULL;
10117
4c0e5528 10118 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10119 return NULL;
10120
4c0e5528
DV		 10121 obj = dev_priv->fbdev->fb->obj;
10122 BUG_ON(!obj);
10123
8bcd4553 10124 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10125 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10126 fb->bits_per_pixel))
d2dff872
CW		 10127 return NULL;
10128
01f2c773 10129 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10130 return NULL;
10131
10132 return fb;
4520f53a
DV		 10133#else
10134 return NULL;
10135#endif
d2dff872
CW		 10136}
10137
d3a40d1b
ACO		 10138static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10139 struct drm_crtc *crtc,
10140 struct drm_display_mode *mode,
10141 struct drm_framebuffer *fb,
10142 int x, int y)
10143{
10144 struct drm_plane_state *plane_state;
10145 int hdisplay, vdisplay;
10146 int ret;
10147
10148 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10149 if (IS_ERR(plane_state))
10150 return PTR_ERR(plane_state);
10151
10152 if (mode)
10153 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10154 else
10155 hdisplay = vdisplay = 0;
10156
10157 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10158 if (ret)
10159 return ret;
10160 drm_atomic_set_fb_for_plane(plane_state, fb);
10161 plane_state->crtc_x = 0;
10162 plane_state->crtc_y = 0;
10163 plane_state->crtc_w = hdisplay;
10164 plane_state->crtc_h = vdisplay;
10165 plane_state->src_x = x << 16;
10166 plane_state->src_y = y << 16;
10167 plane_state->src_w = hdisplay << 16;
10168 plane_state->src_h = vdisplay << 16;
10169
10170 return 0;
10171}
10172
d2434ab7 10173bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10174 struct drm_display_mode *mode,
51fd371b
RC		 10175 struct intel_load_detect_pipe *old,
10176 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10177{
10178 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10179 struct intel_encoder *intel_encoder =
10180 intel_attached_encoder(connector);
79e53945 10181 struct drm_crtc *possible_crtc;
4ef69c7a 10182 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10183 struct drm_crtc *crtc = NULL;
10184 struct drm_device *dev = encoder->dev;
94352cf9 10185 struct drm_framebuffer *fb;
51fd371b 10186 struct drm_mode_config *config = &dev->mode_config;
83a57153 10187 struct drm_atomic_state *state = NULL;
944b0c76 10188 struct drm_connector_state *connector_state;
4be07317 10189 struct intel_crtc_state *crtc_state;
51fd371b 10190 int ret, i = -1;
79e53945 10191
d2dff872 10192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10193 connector->base.id, connector->name,
8e329a03 10194 encoder->base.id, encoder->name);
d2dff872 10195
51fd371b
RC		 10196retry:
10197 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10198 if (ret)
ad3c558f 10199 goto fail;
6e9f798d 10200
79e53945
JB		 10201 /*
10202 * Algorithm gets a little messy:
7a5e4805 10203 *
79e53945
JB		 10204 * - if the connector already has an assigned crtc, use it (but make
10205 * sure it's on first)
7a5e4805 10206 *
79e53945
JB		 10207 * - try to find the first unused crtc that can drive this connector,
10208 * and use that if we find one
79e53945
JB		 10209 */
10210
10211 /* See if we already have a CRTC for this connector */
10212 if (encoder->crtc) {
10213 crtc = encoder->crtc;
8261b191 10214
51fd371b 10215 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10216 if (ret)
ad3c558f 10217 goto fail;
4d02e2de 10218 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10219 if (ret)
ad3c558f 10220 goto fail;
7b24056b 10221
24218aac 10222 old->dpms_mode = connector->dpms;
8261b191
CW		 10223 old->load_detect_temp = false;
10224
10225 /* Make sure the crtc and connector are running */
24218aac
DV		 10226 if (connector->dpms != DRM_MODE_DPMS_ON)
10227 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10228
7173188d 10229 return true;
79e53945
JB		 10230 }
10231
10232 /* Find an unused one (if possible) */
70e1e0ec 10233 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10234 i++;
10235 if (!(encoder->possible_crtcs & (1 << i)))
10236 continue;
83d65738 10237 if (possible_crtc->state->enable)
a459249c 10238 continue;
a459249c
VS		 10239
10240 crtc = possible_crtc;
10241 break;
79e53945
JB		 10242 }
10243
10244 /*
10245 * If we didn't find an unused CRTC, don't use any.
10246 */
10247 if (!crtc) {
7173188d 10248 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10249 goto fail;
79e53945
JB		 10250 }
10251
51fd371b
RC		 10252 ret = drm_modeset_lock(&crtc->mutex, ctx);
10253 if (ret)
ad3c558f 10254 goto fail;
4d02e2de
DV		 10255 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10256 if (ret)
ad3c558f 10257 goto fail;
79e53945
JB		 10258
10259 intel_crtc = to_intel_crtc(crtc);
24218aac 10260 old->dpms_mode = connector->dpms;
8261b191 10261 old->load_detect_temp = true;
d2dff872 10262 old->release_fb = NULL;
79e53945 10263
83a57153
ACO		 10264 state = drm_atomic_state_alloc(dev);
10265 if (!state)
10266 return false;
10267
10268 state->acquire_ctx = ctx;
10269
944b0c76
ACO		 10270 connector_state = drm_atomic_get_connector_state(state, connector);
10271 if (IS_ERR(connector_state)) {
10272 ret = PTR_ERR(connector_state);
10273 goto fail;
10274 }
10275
10276 connector_state->crtc = crtc;
10277 connector_state->best_encoder = &intel_encoder->base;
10278
4be07317
ACO		 10279 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10280 if (IS_ERR(crtc_state)) {
10281 ret = PTR_ERR(crtc_state);
10282 goto fail;
10283 }
10284
49d6fa21 10285 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10286
6492711d
CW		 10287 if (!mode)
10288 mode = &load_detect_mode;
79e53945 10289
d2dff872
CW		 10290 /* We need a framebuffer large enough to accommodate all accesses
10291 * that the plane may generate whilst we perform load detection.
10292 * We can not rely on the fbcon either being present (we get called
10293 * during its initialisation to detect all boot displays, or it may
10294 * not even exist) or that it is large enough to satisfy the
10295 * requested mode.
10296 */
94352cf9
DV		 10297 fb = mode_fits_in_fbdev(dev, mode);
10298 if (fb == NULL) {
d2dff872 10299 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10300 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10301 old->release_fb = fb;
d2dff872
CW		 10302 } else
10303 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10304 if (IS_ERR(fb)) {
d2dff872 10305 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10306 goto fail;
79e53945 10307 }
79e53945 10308
d3a40d1b
ACO		 10309 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10310 if (ret)
10311 goto fail;
10312
8c7b5ccb
ACO		 10313 drm_mode_copy(&crtc_state->base.mode, mode);
10314
74c090b1 10315 if (drm_atomic_commit(state)) {
6492711d 10316 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10317 if (old->release_fb)
10318 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10319 goto fail;
79e53945 10320 }
9128b040 10321 crtc->primary->crtc = crtc;
7173188d 10322
79e53945 10323 /* let the connector get through one full cycle before testing */
9d0498a2 10324 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10325 return true;
412b61d8 10326
ad3c558f 10327fail:
e5d958ef
ACO		 10328 drm_atomic_state_free(state);
10329 state = NULL;
83a57153 10330
51fd371b
RC		 10331 if (ret == -EDEADLK) {
10332 drm_modeset_backoff(ctx);
10333 goto retry;
10334 }
10335
412b61d8 10336 return false;
79e53945
JB		 10337}
10338
d2434ab7 10339void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10340 struct intel_load_detect_pipe *old,
10341 struct drm_modeset_acquire_ctx *ctx)
79e53945 10342{
83a57153 10343 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10344 struct intel_encoder *intel_encoder =
10345 intel_attached_encoder(connector);
4ef69c7a 10346 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10347 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10349 struct drm_atomic_state *state;
944b0c76 10350 struct drm_connector_state *connector_state;
4be07317 10351 struct intel_crtc_state *crtc_state;
d3a40d1b 10352 int ret;
79e53945 10353
d2dff872 10354 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10355 connector->base.id, connector->name,
8e329a03 10356 encoder->base.id, encoder->name);
d2dff872 10357
8261b191 10358 if (old->load_detect_temp) {
83a57153 10359 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10360 if (!state)
10361 goto fail;
83a57153
ACO		 10362
10363 state->acquire_ctx = ctx;
10364
944b0c76
ACO		 10365 connector_state = drm_atomic_get_connector_state(state, connector);
10366 if (IS_ERR(connector_state))
10367 goto fail;
10368
4be07317
ACO		 10369 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10370 if (IS_ERR(crtc_state))
10371 goto fail;
10372
944b0c76
ACO		 10373 connector_state->best_encoder = NULL;
10374 connector_state->crtc = NULL;
10375
49d6fa21 10376 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10377
d3a40d1b
ACO		 10378 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10379 0, 0);
10380 if (ret)
10381 goto fail;
10382
74c090b1 10383 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10384 if (ret)
10385 goto fail;
d2dff872 10386
36206361
DV		 10387 if (old->release_fb) {
10388 drm_framebuffer_unregister_private(old->release_fb);
10389 drm_framebuffer_unreference(old->release_fb);
10390 }
d2dff872 10391
0622a53c 10392 return;
79e53945
JB		 10393 }
10394
c751ce4f 10395 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10396 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10397 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10398
10399 return;
10400fail:
10401 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10402 drm_atomic_state_free(state);
79e53945
JB		 10403}
10404
da4a1efa 10405static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10406 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10407{
10408 struct drm_i915_private *dev_priv = dev->dev_private;
10409 u32 dpll = pipe_config->dpll_hw_state.dpll;
10410
10411 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10412 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10413 else if (HAS_PCH_SPLIT(dev))
10414 return 120000;
10415 else if (!IS_GEN2(dev))
10416 return 96000;
10417 else
10418 return 48000;
10419}
10420
79e53945 10421/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10422static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10423 struct intel_crtc_state *pipe_config)
79e53945 10424{
f1f644dc 10425 struct drm_device *dev = crtc->base.dev;
79e53945 10426 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10427 int pipe = pipe_config->cpu_transcoder;
293623f7 10428 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10429 u32 fp;
10430 intel_clock_t clock;
dccbea3b 10431 int port_clock;
da4a1efa 10432 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10433
10434 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10435 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10436 else
293623f7 10437 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10438
10439 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10440 if (IS_PINEVIEW(dev)) {
10441 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10442 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10443 } else {
10444 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10445 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10446 }
10447
a6c45cf0 10448 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10449 if (IS_PINEVIEW(dev))
10450 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10451 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10452 else
10453 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10454 DPLL_FPA01_P1_POST_DIV_SHIFT);
10455
10456 switch (dpll & DPLL_MODE_MASK) {
10457 case DPLLB_MODE_DAC_SERIAL:
10458 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10459 5 : 10;
10460 break;
10461 case DPLLB_MODE_LVDS:
10462 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10463 7 : 14;
10464 break;
10465 default:
28c97730 10466 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10467 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10468 return;
79e53945
JB		 10469 }
10470
ac58c3f0 10471 if (IS_PINEVIEW(dev))
dccbea3b 10472 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10473 else
dccbea3b 10474 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10475 } else {
0fb58223 10476 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10477 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10478
10479 if (is_lvds) {
10480 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10481 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10482
10483 if (lvds & LVDS_CLKB_POWER_UP)
10484 clock.p2 = 7;
10485 else
10486 clock.p2 = 14;
79e53945
JB		 10487 } else {
10488 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10489 clock.p1 = 2;
10490 else {
10491 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10492 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10493 }
10494 if (dpll & PLL_P2_DIVIDE_BY_4)
10495 clock.p2 = 4;
10496 else
10497 clock.p2 = 2;
79e53945 10498 }
da4a1efa 10499
dccbea3b 10500 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10501 }
10502
18442d08
VS		 10503 /*
10504 * This value includes pixel_multiplier. We will use
241bfc38 10505 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10506 * encoder's get_config() function.
10507 */
dccbea3b 10508 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10509}
10510
6878da05
VS		 10511int intel_dotclock_calculate(int link_freq,
10512 const struct intel_link_m_n *m_n)
f1f644dc 10513{
f1f644dc
JB		 10514 /*
10515 * The calculation for the data clock is:
1041a02f 10516 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10517 * But we want to avoid losing precison if possible, so:
1041a02f 10518 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10519 *
10520 * and the link clock is simpler:
1041a02f 10521 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10522 */
10523
6878da05
VS		 10524 if (!m_n->link_n)
10525 return 0;
f1f644dc 10526
6878da05
VS		 10527 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10528}
f1f644dc 10529
18442d08 10530static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10531 struct intel_crtc_state *pipe_config)
6878da05
VS		 10532{
10533 struct drm_device *dev = crtc->base.dev;
79e53945 10534
18442d08
VS		 10535 /* read out port_clock from the DPLL */
10536 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10537
f1f644dc 10538 /*
18442d08 10539 * This value does not include pixel_multiplier.
241bfc38 10540 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10541 * agree once we know their relationship in the encoder's
10542 * get_config() function.
79e53945 10543 */
2d112de7 10544 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10545 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10546 &pipe_config->fdi_m_n);
79e53945
JB		 10547}
10548
10549/** Returns the currently programmed mode of the given pipe. */
10550struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10551 struct drm_crtc *crtc)
10552{
548f245b 10553 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10555 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10556 struct drm_display_mode *mode;
5cec258b 10557 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10558 int htot = I915_READ(HTOTAL(cpu_transcoder));
10559 int hsync = I915_READ(HSYNC(cpu_transcoder));
10560 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10561 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10562 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10563
10564 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10565 if (!mode)
10566 return NULL;
10567
f1f644dc
JB		 10568 /*
10569 * Construct a pipe_config sufficient for getting the clock info
10570 * back out of crtc_clock_get.
10571 *
10572 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10573 * to use a real value here instead.
10574 */
293623f7 10575 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10576 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10577 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10578 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10579 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10580 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10581
773ae034 10582 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10583 mode->hdisplay = (htot & 0xffff) + 1;
10584 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10585 mode->hsync_start = (hsync & 0xffff) + 1;
10586 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10587 mode->vdisplay = (vtot & 0xffff) + 1;
10588 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10589 mode->vsync_start = (vsync & 0xffff) + 1;
10590 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10591
10592 drm_mode_set_name(mode);
79e53945
JB		 10593
10594 return mode;
10595}
10596
f047e395
CW		 10597void intel_mark_busy(struct drm_device *dev)
10598{
c67a470b
PZ		 10599 struct drm_i915_private *dev_priv = dev->dev_private;
10600
f62a0076
CW		 10601 if (dev_priv->mm.busy)
10602 return;
10603
43694d69 10604 intel_runtime_pm_get(dev_priv);
c67a470b 10605 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10606 if (INTEL_INFO(dev)->gen >= 6)
10607 gen6_rps_busy(dev_priv);
f62a0076 10608 dev_priv->mm.busy = true;
f047e395
CW		 10609}
10610
10611void intel_mark_idle(struct drm_device *dev)
652c393a 10612{
c67a470b 10613 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10614
f62a0076
CW		 10615 if (!dev_priv->mm.busy)
10616 return;
10617
10618 dev_priv->mm.busy = false;
10619
3d13ef2e 10620 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10621 gen6_rps_idle(dev->dev_private);
bb4cdd53 10622
43694d69 10623 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10624}
10625
79e53945
JB		 10626static void intel_crtc_destroy(struct drm_crtc *crtc)
10627{
10628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10629 struct drm_device *dev = crtc->dev;
10630 struct intel_unpin_work *work;
67e77c5a 10631
5e2d7afc 10632 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10633 work = intel_crtc->unpin_work;
10634 intel_crtc->unpin_work = NULL;
5e2d7afc 10635 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10636
10637 if (work) {
10638 cancel_work_sync(&work->work);
10639 kfree(work);
10640 }
79e53945
JB		 10641
10642 drm_crtc_cleanup(crtc);
67e77c5a 10643
79e53945
JB		 10644 kfree(intel_crtc);
10645}
10646
6b95a207
KH		 10647static void intel_unpin_work_fn(struct work_struct *__work)
10648{
10649 struct intel_unpin_work *work =
10650 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10651 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10652 struct drm_device *dev = crtc->base.dev;
10653 struct drm_plane *primary = crtc->base.primary;
6b95a207 10654
b4a98e57 10655 mutex_lock(&dev->struct_mutex);
a9ff8714 10656 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10657 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10658
f06cc1b9 10659 if (work->flip_queued_req)
146d84f0 10660 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10661 mutex_unlock(&dev->struct_mutex);
10662
a9ff8714 10663 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10664 drm_framebuffer_unreference(work->old_fb);
f99d7069 10665
a9ff8714
VS		 10666 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10667 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10668
6b95a207
KH		 10669 kfree(work);
10670}
10671
1afe3e9d 10672static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10673 struct drm_crtc *crtc)
6b95a207 10674{
6b95a207
KH		 10675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10676 struct intel_unpin_work *work;
6b95a207
KH		 10677 unsigned long flags;
10678
10679 /* Ignore early vblank irqs */
10680 if (intel_crtc == NULL)
10681 return;
10682
f326038a
DV		 10683 /*
10684 * This is called both by irq handlers and the reset code (to complete
10685 * lost pageflips) so needs the full irqsave spinlocks.
10686 */
6b95a207
KH		 10687 spin_lock_irqsave(&dev->event_lock, flags);
10688 work = intel_crtc->unpin_work;
e7d841ca
CW		 10689
10690 /* Ensure we don't miss a work->pending update ... */
10691 smp_rmb();
10692
10693 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10694 spin_unlock_irqrestore(&dev->event_lock, flags);
10695 return;
10696 }
10697
d6bbafa1 10698 page_flip_completed(intel_crtc);
0af7e4df 10699
6b95a207 10700 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10701}
10702
1afe3e9d
JB		 10703void intel_finish_page_flip(struct drm_device *dev, int pipe)
10704{
fbee40df 10705 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10706 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10707
49b14a5c 10708 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10709}
10710
10711void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10712{
fbee40df 10713 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10714 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10715
49b14a5c 10716 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10717}
10718
75f7f3ec
VS		 10719/* Is 'a' after or equal to 'b'? */
10720static bool g4x_flip_count_after_eq(u32 a, u32 b)
10721{
10722 return !((a - b) & 0x80000000);
10723}
10724
10725static bool page_flip_finished(struct intel_crtc *crtc)
10726{
10727 struct drm_device *dev = crtc->base.dev;
10728 struct drm_i915_private *dev_priv = dev->dev_private;
10729
bdfa7542
VS		 10730 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10731 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10732 return true;
10733
75f7f3ec
VS		 10734 /*
10735 * The relevant registers doen't exist on pre-ctg.
10736 * As the flip done interrupt doesn't trigger for mmio
10737 * flips on gmch platforms, a flip count check isn't
10738 * really needed there. But since ctg has the registers,
10739 * include it in the check anyway.
10740 */
10741 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10742 return true;
10743
10744 /*
10745 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10746 * used the same base address. In that case the mmio flip might
10747 * have completed, but the CS hasn't even executed the flip yet.
10748 *
10749 * A flip count check isn't enough as the CS might have updated
10750 * the base address just after start of vblank, but before we
10751 * managed to process the interrupt. This means we'd complete the
10752 * CS flip too soon.
10753 *
10754 * Combining both checks should get us a good enough result. It may
10755 * still happen that the CS flip has been executed, but has not
10756 * yet actually completed. But in case the base address is the same
10757 * anyway, we don't really care.
10758 */
10759 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10760 crtc->unpin_work->gtt_offset &&
10761 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10762 crtc->unpin_work->flip_count);
10763}
10764
6b95a207
KH		 10765void intel_prepare_page_flip(struct drm_device *dev, int plane)
10766{
fbee40df 10767 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10768 struct intel_crtc *intel_crtc =
10769 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10770 unsigned long flags;
10771
f326038a
DV		 10772
10773 /*
10774 * This is called both by irq handlers and the reset code (to complete
10775 * lost pageflips) so needs the full irqsave spinlocks.
10776 *
10777 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10778 * generate a page-flip completion irq, i.e. every modeset
10779 * is also accompanied by a spurious intel_prepare_page_flip().
10780 */
6b95a207 10781 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10782 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10783 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10784 spin_unlock_irqrestore(&dev->event_lock, flags);
10785}
10786
eba905b2 10787static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10788{
10789 /* Ensure that the work item is consistent when activating it ... */
10790 smp_wmb();
10791 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10792 /* and that it is marked active as soon as the irq could fire. */
10793 smp_wmb();
10794}
10795
8c9f3aaf
JB		 10796static int intel_gen2_queue_flip(struct drm_device *dev,
10797 struct drm_crtc *crtc,
10798 struct drm_framebuffer *fb,
ed8d1975 10799 struct drm_i915_gem_object *obj,
6258fbe2 10800 struct drm_i915_gem_request *req,
ed8d1975 10801 uint32_t flags)
8c9f3aaf 10802{
6258fbe2 10803 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10805 u32 flip_mask;
10806 int ret;
10807
5fb9de1a 10808 ret = intel_ring_begin(req, 6);
8c9f3aaf 10809 if (ret)
4fa62c89 10810 return ret;
8c9f3aaf
JB		 10811
10812 /* Can't queue multiple flips, so wait for the previous
10813 * one to finish before executing the next.
10814 */
10815 if (intel_crtc->plane)
10816 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10817 else
10818 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10819 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10820 intel_ring_emit(ring, MI_NOOP);
10821 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10822 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10823 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10824 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10825 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10826
10827 intel_mark_page_flip_active(intel_crtc);
83d4092b 10828 return 0;
8c9f3aaf
JB		 10829}
10830
10831static int intel_gen3_queue_flip(struct drm_device *dev,
10832 struct drm_crtc *crtc,
10833 struct drm_framebuffer *fb,
ed8d1975 10834 struct drm_i915_gem_object *obj,
6258fbe2 10835 struct drm_i915_gem_request *req,
ed8d1975 10836 uint32_t flags)
8c9f3aaf 10837{
6258fbe2 10838 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10840 u32 flip_mask;
10841 int ret;
10842
5fb9de1a 10843 ret = intel_ring_begin(req, 6);
8c9f3aaf 10844 if (ret)
4fa62c89 10845 return ret;
8c9f3aaf
JB		 10846
10847 if (intel_crtc->plane)
10848 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10849 else
10850 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10851 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10852 intel_ring_emit(ring, MI_NOOP);
10853 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10854 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10855 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10856 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10857 intel_ring_emit(ring, MI_NOOP);
10858
e7d841ca 10859 intel_mark_page_flip_active(intel_crtc);
83d4092b 10860 return 0;
8c9f3aaf
JB		 10861}
10862
10863static int intel_gen4_queue_flip(struct drm_device *dev,
10864 struct drm_crtc *crtc,
10865 struct drm_framebuffer *fb,
ed8d1975 10866 struct drm_i915_gem_object *obj,
6258fbe2 10867 struct drm_i915_gem_request *req,
ed8d1975 10868 uint32_t flags)
8c9f3aaf 10869{
6258fbe2 10870 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10871 struct drm_i915_private *dev_priv = dev->dev_private;
10872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10873 uint32_t pf, pipesrc;
10874 int ret;
10875
5fb9de1a 10876 ret = intel_ring_begin(req, 4);
8c9f3aaf 10877 if (ret)
4fa62c89 10878 return ret;
8c9f3aaf
JB		 10879
10880 /* i965+ uses the linear or tiled offsets from the
10881 * Display Registers (which do not change across a page-flip)
10882 * so we need only reprogram the base address.
10883 */
6d90c952
DV		 10884 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10885 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10886 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10887 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10888 obj->tiling_mode);
8c9f3aaf
JB		 10889
10890 /* XXX Enabling the panel-fitter across page-flip is so far
10891 * untested on non-native modes, so ignore it for now.
10892 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10893 */
10894 pf = 0;
10895 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10896 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10897
10898 intel_mark_page_flip_active(intel_crtc);
83d4092b 10899 return 0;
8c9f3aaf
JB		 10900}
10901
10902static int intel_gen6_queue_flip(struct drm_device *dev,
10903 struct drm_crtc *crtc,
10904 struct drm_framebuffer *fb,
ed8d1975 10905 struct drm_i915_gem_object *obj,
6258fbe2 10906 struct drm_i915_gem_request *req,
ed8d1975 10907 uint32_t flags)
8c9f3aaf 10908{
6258fbe2 10909 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10910 struct drm_i915_private *dev_priv = dev->dev_private;
10911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10912 uint32_t pf, pipesrc;
10913 int ret;
10914
5fb9de1a 10915 ret = intel_ring_begin(req, 4);
8c9f3aaf 10916 if (ret)
4fa62c89 10917 return ret;
8c9f3aaf 10918
6d90c952
DV		 10919 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10920 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10921 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10922 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10923
dc257cf1
DV		 10924 /* Contrary to the suggestions in the documentation,
10925 * "Enable Panel Fitter" does not seem to be required when page
10926 * flipping with a non-native mode, and worse causes a normal
10927 * modeset to fail.
10928 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10929 */
10930 pf = 0;
8c9f3aaf 10931 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10932 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10933
10934 intel_mark_page_flip_active(intel_crtc);
83d4092b 10935 return 0;
8c9f3aaf
JB		 10936}
10937
7c9017e5
JB		 10938static int intel_gen7_queue_flip(struct drm_device *dev,
10939 struct drm_crtc *crtc,
10940 struct drm_framebuffer *fb,
ed8d1975 10941 struct drm_i915_gem_object *obj,
6258fbe2 10942 struct drm_i915_gem_request *req,
ed8d1975 10943 uint32_t flags)
7c9017e5 10944{
6258fbe2 10945 struct intel_engine_cs *ring = req->ring;
7c9017e5 10946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10947 uint32_t plane_bit = 0;
ffe74d75
CW		 10948 int len, ret;
10949
eba905b2 10950 switch (intel_crtc->plane) {
cb05d8de
DV		 10951 case PLANE_A:
10952 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10953 break;
10954 case PLANE_B:
10955 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10956 break;
10957 case PLANE_C:
10958 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10959 break;
10960 default:
10961 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10962 return -ENODEV;
cb05d8de
DV		 10963 }
10964
ffe74d75 10965 len = 4;
f476828a 10966 if (ring->id == RCS) {
ffe74d75 10967 len += 6;
f476828a
DL		 10968 /*
10969 * On Gen 8, SRM is now taking an extra dword to accommodate
10970 * 48bits addresses, and we need a NOOP for the batch size to
10971 * stay even.
10972 */
10973 if (IS_GEN8(dev))
10974 len += 2;
10975 }
ffe74d75 10976
f66fab8e
VS		 10977 /*
10978 * BSpec MI_DISPLAY_FLIP for IVB:
10979 * "The full packet must be contained within the same cache line."
10980 *
10981 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10982 * cacheline, if we ever start emitting more commands before
10983 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10984 * then do the cacheline alignment, and finally emit the
10985 * MI_DISPLAY_FLIP.
10986 */
bba09b12 10987 ret = intel_ring_cacheline_align(req);
f66fab8e 10988 if (ret)
4fa62c89 10989 return ret;
f66fab8e 10990
5fb9de1a 10991 ret = intel_ring_begin(req, len);
7c9017e5 10992 if (ret)
4fa62c89 10993 return ret;
7c9017e5 10994
ffe74d75
CW		 10995 /* Unmask the flip-done completion message. Note that the bspec says that
10996 * we should do this for both the BCS and RCS, and that we must not unmask
10997 * more than one flip event at any time (or ensure that one flip message
10998 * can be sent by waiting for flip-done prior to queueing new flips).
10999 * Experimentation says that BCS works despite DERRMR masking all
11000 * flip-done completion events and that unmasking all planes at once
11001 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11002 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11003 */
11004 if (ring->id == RCS) {
11005 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11006 intel_ring_emit(ring, DERRMR);
11007 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11008 DERRMR_PIPEB_PRI_FLIP_DONE |
11009 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a 11010 if (IS_GEN8(dev))
f1afe24f 11011 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
f476828a
DL		 11012 MI_SRM_LRM_GLOBAL_GTT);
11013 else
f1afe24f 11014 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
f476828a 11015 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11016 intel_ring_emit(ring, DERRMR);
11017 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11018 if (IS_GEN8(dev)) {
11019 intel_ring_emit(ring, 0);
11020 intel_ring_emit(ring, MI_NOOP);
11021 }
ffe74d75
CW		 11022 }
11023
cb05d8de 11024 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11025 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11026 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11027 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11028
11029 intel_mark_page_flip_active(intel_crtc);
83d4092b 11030 return 0;
7c9017e5
JB		 11031}
11032
84c33a64
SG		 11033static bool use_mmio_flip(struct intel_engine_cs *ring,
11034 struct drm_i915_gem_object *obj)
11035{
11036 /*
11037 * This is not being used for older platforms, because
11038 * non-availability of flip done interrupt forces us to use
11039 * CS flips. Older platforms derive flip done using some clever
11040 * tricks involving the flip_pending status bits and vblank irqs.
11041 * So using MMIO flips there would disrupt this mechanism.
11042 */
11043
8e09bf83
CW		 11044 if (ring == NULL)
11045 return true;
11046
84c33a64
SG		 11047 if (INTEL_INFO(ring->dev)->gen < 5)
11048 return false;
11049
11050 if (i915.use_mmio_flip < 0)
11051 return false;
11052 else if (i915.use_mmio_flip > 0)
11053 return true;
14bf993e
OM		 11054 else if (i915.enable_execlists)
11055 return true;
84c33a64 11056 else
b4716185 11057 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11058}
11059
ff944564
DL		 11060static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11061{
11062 struct drm_device *dev = intel_crtc->base.dev;
11063 struct drm_i915_private *dev_priv = dev->dev_private;
11064 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11065 const enum pipe pipe = intel_crtc->pipe;
11066 u32 ctl, stride;
11067
11068 ctl = I915_READ(PLANE_CTL(pipe, 0));
11069 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11070 switch (fb->modifier[0]) {
11071 case DRM_FORMAT_MOD_NONE:
11072 break;
11073 case I915_FORMAT_MOD_X_TILED:
ff944564 11074 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11075 break;
11076 case I915_FORMAT_MOD_Y_TILED:
11077 ctl |= PLANE_CTL_TILED_Y;
11078 break;
11079 case I915_FORMAT_MOD_Yf_TILED:
11080 ctl |= PLANE_CTL_TILED_YF;
11081 break;
11082 default:
11083 MISSING_CASE(fb->modifier[0]);
11084 }
ff944564
DL		 11085
11086 /*
11087 * The stride is either expressed as a multiple of 64 bytes chunks for
11088 * linear buffers or in number of tiles for tiled buffers.
11089 */
2ebef630
TU		 11090 stride = fb->pitches[0] /
11091 intel_fb_stride_alignment(dev, fb->modifier[0],
11092 fb->pixel_format);
ff944564
DL		 11093
11094 /*
11095 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11096 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11097 */
11098 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11099 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11100
11101 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11102 POSTING_READ(PLANE_SURF(pipe, 0));
11103}
11104
11105static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11106{
11107 struct drm_device *dev = intel_crtc->base.dev;
11108 struct drm_i915_private *dev_priv = dev->dev_private;
11109 struct intel_framebuffer *intel_fb =
11110 to_intel_framebuffer(intel_crtc->base.primary->fb);
11111 struct drm_i915_gem_object *obj = intel_fb->obj;
11112 u32 dspcntr;
11113 u32 reg;
11114
84c33a64
SG		 11115 reg = DSPCNTR(intel_crtc->plane);
11116 dspcntr = I915_READ(reg);
11117
c5d97472
DL		 11118 if (obj->tiling_mode != I915_TILING_NONE)
11119 dspcntr |= DISPPLANE_TILED;
11120 else
11121 dspcntr &= ~DISPPLANE_TILED;
11122
84c33a64
SG		 11123 I915_WRITE(reg, dspcntr);
11124
11125 I915_WRITE(DSPSURF(intel_crtc->plane),
11126 intel_crtc->unpin_work->gtt_offset);
11127 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11128
ff944564
DL		 11129}
11130
11131/*
11132 * XXX: This is the temporary way to update the plane registers until we get
11133 * around to using the usual plane update functions for MMIO flips
11134 */
11135static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11136{
11137 struct drm_device *dev = intel_crtc->base.dev;
ff944564
DL		 11138
11139 intel_mark_page_flip_active(intel_crtc);
11140
34e0adbb 11141 intel_pipe_update_start(intel_crtc);
ff944564
DL		 11142
11143 if (INTEL_INFO(dev)->gen >= 9)
11144 skl_do_mmio_flip(intel_crtc);
11145 else
11146 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11147 ilk_do_mmio_flip(intel_crtc);
11148
34e0adbb 11149 intel_pipe_update_end(intel_crtc);
84c33a64
SG		 11150}
11151
9362c7c5 11152static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11153{
b2cfe0ab
CW		 11154 struct intel_mmio_flip *mmio_flip =
11155 container_of(work, struct intel_mmio_flip, work);
84c33a64 11156
eed29a5b
DV		 11157 if (mmio_flip->req)
11158 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11159 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11160 false, NULL,
11161 &mmio_flip->i915->rps.mmioflips));
84c33a64 11162
b2cfe0ab
CW		 11163 intel_do_mmio_flip(mmio_flip->crtc);
11164
eed29a5b 11165 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11166 kfree(mmio_flip);
84c33a64
SG		 11167}
11168
11169static int intel_queue_mmio_flip(struct drm_device *dev,
11170 struct drm_crtc *crtc,
11171 struct drm_framebuffer *fb,
11172 struct drm_i915_gem_object *obj,
11173 struct intel_engine_cs *ring,
11174 uint32_t flags)
11175{
b2cfe0ab
CW		 11176 struct intel_mmio_flip *mmio_flip;
11177
11178 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11179 if (mmio_flip == NULL)
11180 return -ENOMEM;
84c33a64 11181
bcafc4e3 11182 mmio_flip->i915 = to_i915(dev);
eed29a5b 11183 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11184 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11185
b2cfe0ab
CW		 11186 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11187 schedule_work(&mmio_flip->work);
84c33a64 11188
84c33a64
SG		 11189 return 0;
11190}
11191
8c9f3aaf
JB		 11192static int intel_default_queue_flip(struct drm_device *dev,
11193 struct drm_crtc *crtc,
11194 struct drm_framebuffer *fb,
ed8d1975 11195 struct drm_i915_gem_object *obj,
6258fbe2 11196 struct drm_i915_gem_request *req,
ed8d1975 11197 uint32_t flags)
8c9f3aaf
JB		 11198{
11199 return -ENODEV;
11200}
11201
d6bbafa1
CW		 11202static bool __intel_pageflip_stall_check(struct drm_device *dev,
11203 struct drm_crtc *crtc)
11204{
11205 struct drm_i915_private *dev_priv = dev->dev_private;
11206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11207 struct intel_unpin_work *work = intel_crtc->unpin_work;
11208 u32 addr;
11209
11210 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11211 return true;
11212
908565c2
CW		 11213 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11214 return false;
11215
d6bbafa1
CW		 11216 if (!work->enable_stall_check)
11217 return false;
11218
11219 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11220 if (work->flip_queued_req &&
11221 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11222 return false;
11223
1e3feefd 11224 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11225 }
11226
1e3feefd 11227 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11228 return false;
11229
11230 /* Potential stall - if we see that the flip has happened,
11231 * assume a missed interrupt. */
11232 if (INTEL_INFO(dev)->gen >= 4)
11233 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11234 else
11235 addr = I915_READ(DSPADDR(intel_crtc->plane));
11236
11237 /* There is a potential issue here with a false positive after a flip
11238 * to the same address. We could address this by checking for a
11239 * non-incrementing frame counter.
11240 */
11241 return addr == work->gtt_offset;
11242}
11243
11244void intel_check_page_flip(struct drm_device *dev, int pipe)
11245{
11246 struct drm_i915_private *dev_priv = dev->dev_private;
11247 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11249 struct intel_unpin_work *work;
f326038a 11250
6c51d46f 11251 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11252
11253 if (crtc == NULL)
11254 return;
11255
f326038a 11256 spin_lock(&dev->event_lock);
6ad790c0
CW		 11257 work = intel_crtc->unpin_work;
11258 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11259 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11260 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11261 page_flip_completed(intel_crtc);
6ad790c0 11262 work = NULL;
d6bbafa1 11263 }
6ad790c0
CW		 11264 if (work != NULL &&
11265 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11266 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11267 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11268}
11269
6b95a207
KH		 11270static int intel_crtc_page_flip(struct drm_crtc *crtc,
11271 struct drm_framebuffer *fb,
ed8d1975
KP		 11272 struct drm_pending_vblank_event *event,
11273 uint32_t page_flip_flags)
6b95a207
KH		 11274{
11275 struct drm_device *dev = crtc->dev;
11276 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11277 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11278 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11280 struct drm_plane *primary = crtc->primary;
a071fa00 11281 enum pipe pipe = intel_crtc->pipe;
6b95a207 11282 struct intel_unpin_work *work;
a4872ba6 11283 struct intel_engine_cs *ring;
cf5d8a46 11284 bool mmio_flip;
91af127f 11285 struct drm_i915_gem_request *request = NULL;
52e68630 11286 int ret;
6b95a207 11287
2ff8fde1
MR		 11288 /*
11289 * drm_mode_page_flip_ioctl() should already catch this, but double
11290 * check to be safe. In the future we may enable pageflipping from
11291 * a disabled primary plane.
11292 */
11293 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11294 return -EBUSY;
11295
e6a595d2 11296 /* Can't change pixel format via MI display flips. */
f4510a27 11297 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11298 return -EINVAL;
11299
11300 /*
11301 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11302 * Note that pitch changes could also affect these register.
11303 */
11304 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11305 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11306 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11307 return -EINVAL;
11308
f900db47
CW		 11309 if (i915_terminally_wedged(&dev_priv->gpu_error))
11310 goto out_hang;
11311
b14c5679 11312 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11313 if (work == NULL)
11314 return -ENOMEM;
11315
6b95a207 11316 work->event = event;
b4a98e57 11317 work->crtc = crtc;
ab8d6675 11318 work->old_fb = old_fb;
6b95a207
KH		 11319 INIT_WORK(&work->work, intel_unpin_work_fn);
11320
87b6b101 11321 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11322 if (ret)
11323 goto free_work;
11324
6b95a207 11325 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11326 spin_lock_irq(&dev->event_lock);
6b95a207 11327 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11328 /* Before declaring the flip queue wedged, check if
11329 * the hardware completed the operation behind our backs.
11330 */
11331 if (__intel_pageflip_stall_check(dev, crtc)) {
11332 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11333 page_flip_completed(intel_crtc);
11334 } else {
11335 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11336 spin_unlock_irq(&dev->event_lock);
468f0b44 11337
d6bbafa1
CW		 11338 drm_crtc_vblank_put(crtc);
11339 kfree(work);
11340 return -EBUSY;
11341 }
6b95a207
KH		 11342 }
11343 intel_crtc->unpin_work = work;
5e2d7afc 11344 spin_unlock_irq(&dev->event_lock);
6b95a207 11345
b4a98e57
CW		 11346 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11347 flush_workqueue(dev_priv->wq);
11348
75dfca80 11349 /* Reference the objects for the scheduled work. */
ab8d6675 11350 drm_framebuffer_reference(work->old_fb);
05394f39 11351 drm_gem_object_reference(&obj->base);
6b95a207 11352
f4510a27 11353 crtc->primary->fb = fb;
afd65eb4 11354 update_state_fb(crtc->primary);
1ed1f968 11355
e1f99ce6 11356 work->pending_flip_obj = obj;
e1f99ce6 11357
89ed88ba
CW		 11358 ret = i915_mutex_lock_interruptible(dev);
11359 if (ret)
11360 goto cleanup;
11361
b4a98e57 11362 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11363 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11364
75f7f3ec 11365 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11366 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11367
4fa62c89
VS		 11368 if (IS_VALLEYVIEW(dev)) {
11369 ring = &dev_priv->ring[BCS];
ab8d6675 11370 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11371 /* vlv: DISPLAY_FLIP fails to change tiling */
11372 ring = NULL;
48bf5b2d 11373 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11374 ring = &dev_priv->ring[BCS];
4fa62c89 11375 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11376 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11377 if (ring == NULL || ring->id != RCS)
11378 ring = &dev_priv->ring[BCS];
11379 } else {
11380 ring = &dev_priv->ring[RCS];
11381 }
11382
cf5d8a46
CW		 11383 mmio_flip = use_mmio_flip(ring, obj);
11384
11385 /* When using CS flips, we want to emit semaphores between rings.
11386 * However, when using mmio flips we will create a task to do the
11387 * synchronisation, so all we want here is to pin the framebuffer
11388 * into the display plane and skip any waits.
11389 */
82bc3b2d 11390 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11391 crtc->primary->state,
91af127f 11392 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11393 if (ret)
11394 goto cleanup_pending;
6b95a207 11395
121920fa
TU		 11396 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11397 + intel_crtc->dspaddr_offset;
4fa62c89 11398
cf5d8a46 11399 if (mmio_flip) {
84c33a64
SG		 11400 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11401 page_flip_flags);
d6bbafa1
CW		 11402 if (ret)
11403 goto cleanup_unpin;
11404
f06cc1b9
JH		 11405 i915_gem_request_assign(&work->flip_queued_req,
11406 obj->last_write_req);
d6bbafa1 11407 } else {
6258fbe2
JH		 11408 if (!request) {
11409 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11410 if (ret)
11411 goto cleanup_unpin;
11412 }
11413
11414 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11415 page_flip_flags);
11416 if (ret)
11417 goto cleanup_unpin;
11418
6258fbe2 11419 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11420 }
11421
91af127f 11422 if (request)
75289874 11423 i915_add_request_no_flush(request);
91af127f 11424
1e3feefd 11425 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11426 work->enable_stall_check = true;
4fa62c89 11427
ab8d6675 11428 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11429 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11430 mutex_unlock(&dev->struct_mutex);
a071fa00 11431
4e1e26f1 11432 intel_fbc_disable_crtc(intel_crtc);
a9ff8714
VS		 11433 intel_frontbuffer_flip_prepare(dev,
11434 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11435
e5510fac
JB		 11436 trace_i915_flip_request(intel_crtc->plane, obj);
11437
6b95a207 11438 return 0;
96b099fd 11439
4fa62c89 11440cleanup_unpin:
82bc3b2d 11441 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11442cleanup_pending:
91af127f
JH		 11443 if (request)
11444 i915_gem_request_cancel(request);
b4a98e57 11445 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11446 mutex_unlock(&dev->struct_mutex);
11447cleanup:
f4510a27 11448 crtc->primary->fb = old_fb;
afd65eb4 11449 update_state_fb(crtc->primary);
89ed88ba
CW		 11450
11451 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11452 drm_framebuffer_unreference(work->old_fb);
96b099fd 11453
5e2d7afc 11454 spin_lock_irq(&dev->event_lock);
96b099fd 11455 intel_crtc->unpin_work = NULL;
5e2d7afc 11456 spin_unlock_irq(&dev->event_lock);
96b099fd 11457
87b6b101 11458 drm_crtc_vblank_put(crtc);
7317c75e 11459free_work:
96b099fd
CW		 11460 kfree(work);
11461
f900db47 11462 if (ret == -EIO) {
02e0efb5
ML		 11463 struct drm_atomic_state *state;
11464 struct drm_plane_state *plane_state;
11465
f900db47 11466out_hang:
02e0efb5
ML		 11467 state = drm_atomic_state_alloc(dev);
11468 if (!state)
11469 return -ENOMEM;
11470 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11471
11472retry:
11473 plane_state = drm_atomic_get_plane_state(state, primary);
11474 ret = PTR_ERR_OR_ZERO(plane_state);
11475 if (!ret) {
11476 drm_atomic_set_fb_for_plane(plane_state, fb);
11477
11478 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11479 if (!ret)
11480 ret = drm_atomic_commit(state);
11481 }
11482
11483 if (ret == -EDEADLK) {
11484 drm_modeset_backoff(state->acquire_ctx);
11485 drm_atomic_state_clear(state);
11486 goto retry;
11487 }
11488
11489 if (ret)
11490 drm_atomic_state_free(state);
11491
f0d3dad3 11492 if (ret == 0 && event) {
5e2d7afc 11493 spin_lock_irq(&dev->event_lock);
a071fa00 11494 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11495 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11496 }
f900db47 11497 }
96b099fd 11498 return ret;
6b95a207
KH		 11499}
11500
da20eabd
ML		 11501
11502/**
11503 * intel_wm_need_update - Check whether watermarks need updating
11504 * @plane: drm plane
11505 * @state: new plane state
11506 *
11507 * Check current plane state versus the new one to determine whether
11508 * watermarks need to be recalculated.
11509 *
11510 * Returns true or false.
11511 */
11512static bool intel_wm_need_update(struct drm_plane *plane,
11513 struct drm_plane_state *state)
11514{
11515 /* Update watermarks on tiling changes. */
11516 if (!plane->state->fb || !state->fb ||
11517 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11518 plane->state->rotation != state->rotation)
11519 return true;
11520
11521 if (plane->state->crtc_w != state->crtc_w)
11522 return true;
11523
11524 return false;
11525}
11526
11527int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11528 struct drm_plane_state *plane_state)
11529{
11530 struct drm_crtc *crtc = crtc_state->crtc;
11531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11532 struct drm_plane *plane = plane_state->plane;
11533 struct drm_device *dev = crtc->dev;
11534 struct drm_i915_private *dev_priv = dev->dev_private;
11535 struct intel_plane_state *old_plane_state =
11536 to_intel_plane_state(plane->state);
11537 int idx = intel_crtc->base.base.id, ret;
11538 int i = drm_plane_index(plane);
11539 bool mode_changed = needs_modeset(crtc_state);
11540 bool was_crtc_enabled = crtc->state->active;
11541 bool is_crtc_enabled = crtc_state->active;
11542
11543 bool turn_off, turn_on, visible, was_visible;
11544 struct drm_framebuffer *fb = plane_state->fb;
11545
11546 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11547 plane->type != DRM_PLANE_TYPE_CURSOR) {
11548 ret = skl_update_scaler_plane(
11549 to_intel_crtc_state(crtc_state),
11550 to_intel_plane_state(plane_state));
11551 if (ret)
11552 return ret;
11553 }
11554
11555 /*
11556 * Disabling a plane is always okay; we just need to update
11557 * fb tracking in a special way since cleanup_fb() won't
11558 * get called by the plane helpers.
11559 */
11560 if (old_plane_state->base.fb && !fb)
11561 intel_crtc->atomic.disabled_planes |= 1 << i;
11562
da20eabd
ML		 11563 was_visible = old_plane_state->visible;
11564 visible = to_intel_plane_state(plane_state)->visible;
11565
11566 if (!was_crtc_enabled && WARN_ON(was_visible))
11567 was_visible = false;
11568
11569 if (!is_crtc_enabled && WARN_ON(visible))
11570 visible = false;
11571
11572 if (!was_visible && !visible)
11573 return 0;
11574
11575 turn_off = was_visible && (!visible || mode_changed);
11576 turn_on = visible && (!was_visible || mode_changed);
11577
11578 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11579 plane->base.id, fb ? fb->base.id : -1);
11580
11581 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11582 plane->base.id, was_visible, visible,
11583 turn_off, turn_on, mode_changed);
11584
852eb00d 11585 if (turn_on) {
f015c551 11586 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11587 /* must disable cxsr around plane enable/disable */
11588 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11589 intel_crtc->atomic.disable_cxsr = true;
11590 /* to potentially re-enable cxsr */
11591 intel_crtc->atomic.wait_vblank = true;
11592 intel_crtc->atomic.update_wm_post = true;
11593 }
11594 } else if (turn_off) {
f015c551 11595 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11596 /* must disable cxsr around plane enable/disable */
11597 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11598 if (is_crtc_enabled)
11599 intel_crtc->atomic.wait_vblank = true;
11600 intel_crtc->atomic.disable_cxsr = true;
11601 }
11602 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11603 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11604 }
da20eabd 11605
8be6ca85 11606 if (visible || was_visible)
a9ff8714
VS		 11607 intel_crtc->atomic.fb_bits |=
11608 to_intel_plane(plane)->frontbuffer_bit;
11609
da20eabd
ML		 11610 switch (plane->type) {
11611 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11612 intel_crtc->atomic.wait_for_flips = true;
11613 intel_crtc->atomic.pre_disable_primary = turn_off;
11614 intel_crtc->atomic.post_enable_primary = turn_on;
11615
066cf55b
RV		 11616 if (turn_off) {
11617 /*
11618 * FIXME: Actually if we will still have any other
11619 * plane enabled on the pipe we could let IPS enabled
11620 * still, but for now lets consider that when we make
11621 * primary invisible by setting DSPCNTR to 0 on
11622 * update_primary_plane function IPS needs to be
11623 * disable.
11624 */
11625 intel_crtc->atomic.disable_ips = true;
11626
da20eabd 11627 intel_crtc->atomic.disable_fbc = true;
066cf55b 11628 }
da20eabd
ML		 11629
11630 /*
11631 * FBC does not work on some platforms for rotated
11632 * planes, so disable it when rotation is not 0 and
11633 * update it when rotation is set back to 0.
11634 *
11635 * FIXME: This is redundant with the fbc update done in
11636 * the primary plane enable function except that that
11637 * one is done too late. We eventually need to unify
11638 * this.
11639 */
11640
11641 if (visible &&
11642 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11643 dev_priv->fbc.crtc == intel_crtc &&
11644 plane_state->rotation != BIT(DRM_ROTATE_0))
11645 intel_crtc->atomic.disable_fbc = true;
11646
11647 /*
11648 * BDW signals flip done immediately if the plane
11649 * is disabled, even if the plane enable is already
11650 * armed to occur at the next vblank :(
11651 */
11652 if (turn_on && IS_BROADWELL(dev))
11653 intel_crtc->atomic.wait_vblank = true;
11654
11655 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11656 break;
11657 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11658 break;
11659 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11660 if (turn_off && !mode_changed) {
da20eabd
ML		 11661 intel_crtc->atomic.wait_vblank = true;
11662 intel_crtc->atomic.update_sprite_watermarks |=
11663 1 << i;
11664 }
da20eabd
ML		 11665 }
11666 return 0;
11667}
11668
6d3a1ce7
ML		 11669static bool encoders_cloneable(const struct intel_encoder *a,
11670 const struct intel_encoder *b)
11671{
11672 /* masks could be asymmetric, so check both ways */
11673 return a == b || (a->cloneable & (1 << b->type) &&
11674 b->cloneable & (1 << a->type));
11675}
11676
11677static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11678 struct intel_crtc *crtc,
11679 struct intel_encoder *encoder)
11680{
11681 struct intel_encoder *source_encoder;
11682 struct drm_connector *connector;
11683 struct drm_connector_state *connector_state;
11684 int i;
11685
11686 for_each_connector_in_state(state, connector, connector_state, i) {
11687 if (connector_state->crtc != &crtc->base)
11688 continue;
11689
11690 source_encoder =
11691 to_intel_encoder(connector_state->best_encoder);
11692 if (!encoders_cloneable(encoder, source_encoder))
11693 return false;
11694 }
11695
11696 return true;
11697}
11698
11699static bool check_encoder_cloning(struct drm_atomic_state *state,
11700 struct intel_crtc *crtc)
11701{
11702 struct intel_encoder *encoder;
11703 struct drm_connector *connector;
11704 struct drm_connector_state *connector_state;
11705 int i;
11706
11707 for_each_connector_in_state(state, connector, connector_state, i) {
11708 if (connector_state->crtc != &crtc->base)
11709 continue;
11710
11711 encoder = to_intel_encoder(connector_state->best_encoder);
11712 if (!check_single_encoder_cloning(state, crtc, encoder))
11713 return false;
11714 }
11715
11716 return true;
11717}
11718
11719static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11720 struct drm_crtc_state *crtc_state)
11721{
cf5a15be 11722 struct drm_device *dev = crtc->dev;
ad421372 11723 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11725 struct intel_crtc_state *pipe_config =
11726 to_intel_crtc_state(crtc_state);
6d3a1ce7 11727 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 11728 int ret;
6d3a1ce7
ML		 11729 bool mode_changed = needs_modeset(crtc_state);
11730
11731 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11732 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11733 return -EINVAL;
11734 }
11735
852eb00d
VS		 11736 if (mode_changed && !crtc_state->active)
11737 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11738
ad421372
ML		 11739 if (mode_changed && crtc_state->enable &&
11740 dev_priv->display.crtc_compute_clock &&
11741 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11742 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11743 pipe_config);
11744 if (ret)
11745 return ret;
11746 }
11747
e435d6e5
ML		 11748 ret = 0;
11749 if (INTEL_INFO(dev)->gen >= 9) {
11750 if (mode_changed)
11751 ret = skl_update_scaler_crtc(pipe_config);
11752
11753 if (!ret)
11754 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11755 pipe_config);
11756 }
11757
11758 return ret;
6d3a1ce7
ML		 11759}
11760
65b38e0d 11761static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11762 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11763 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11764 .atomic_begin = intel_begin_crtc_commit,
11765 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11766 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11767};
11768
d29b2f9d
ACO		 11769static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11770{
11771 struct intel_connector *connector;
11772
11773 for_each_intel_connector(dev, connector) {
11774 if (connector->base.encoder) {
11775 connector->base.state->best_encoder =
11776 connector->base.encoder;
11777 connector->base.state->crtc =
11778 connector->base.encoder->crtc;
11779 } else {
11780 connector->base.state->best_encoder = NULL;
11781 connector->base.state->crtc = NULL;
11782 }
11783 }
11784}
11785
050f7aeb 11786static void
eba905b2 11787connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11788 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11789{
11790 int bpp = pipe_config->pipe_bpp;
11791
11792 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11793 connector->base.base.id,
c23cc417 11794 connector->base.name);
050f7aeb
DV		 11795
11796 /* Don't use an invalid EDID bpc value */
11797 if (connector->base.display_info.bpc &&
11798 connector->base.display_info.bpc * 3 < bpp) {
11799 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11800 bpp, connector->base.display_info.bpc*3);
11801 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11802 }
11803
11804 /* Clamp bpp to 8 on screens without EDID 1.4 */
11805 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11806 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11807 bpp);
11808 pipe_config->pipe_bpp = 24;
11809 }
11810}
11811
4e53c2e0 11812static int
050f7aeb 11813compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11814 struct intel_crtc_state *pipe_config)
4e53c2e0 11815{
050f7aeb 11816 struct drm_device *dev = crtc->base.dev;
1486017f 11817 struct drm_atomic_state *state;
da3ced29
ACO		 11818 struct drm_connector *connector;
11819 struct drm_connector_state *connector_state;
1486017f 11820 int bpp, i;
4e53c2e0 11821
d328c9d7 11822 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11823 bpp = 10*3;
d328c9d7
DV		 11824 else if (INTEL_INFO(dev)->gen >= 5)
11825 bpp = 12*3;
11826 else
11827 bpp = 8*3;
11828
4e53c2e0 11829
4e53c2e0
DV		 11830 pipe_config->pipe_bpp = bpp;
11831
1486017f
ACO		 11832 state = pipe_config->base.state;
11833
4e53c2e0 11834 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11835 for_each_connector_in_state(state, connector, connector_state, i) {
11836 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11837 continue;
11838
da3ced29
ACO		 11839 connected_sink_compute_bpp(to_intel_connector(connector),
11840 pipe_config);
4e53c2e0
DV		 11841 }
11842
11843 return bpp;
11844}
11845
644db711
DV		 11846static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11847{
11848 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11849 "type: 0x%x flags: 0x%x\n",
1342830c 11850 mode->crtc_clock,
644db711
DV		 11851 mode->crtc_hdisplay, mode->crtc_hsync_start,
11852 mode->crtc_hsync_end, mode->crtc_htotal,
11853 mode->crtc_vdisplay, mode->crtc_vsync_start,
11854 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11855}
11856
c0b03411 11857static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11858 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11859 const char *context)
11860{
6a60cd87
CK		 11861 struct drm_device *dev = crtc->base.dev;
11862 struct drm_plane *plane;
11863 struct intel_plane *intel_plane;
11864 struct intel_plane_state *state;
11865 struct drm_framebuffer *fb;
11866
11867 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11868 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11869
11870 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11871 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11872 pipe_config->pipe_bpp, pipe_config->dither);
11873 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11874 pipe_config->has_pch_encoder,
11875 pipe_config->fdi_lanes,
11876 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11877 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11878 pipe_config->fdi_m_n.tu);
90a6b7b0 11879 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
eb14cb74 11880 pipe_config->has_dp_encoder,
90a6b7b0 11881 pipe_config->lane_count,
eb14cb74
VS		 11882 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11883 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11884 pipe_config->dp_m_n.tu);
b95af8be 11885
90a6b7b0 11886 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
b95af8be 11887 pipe_config->has_dp_encoder,
90a6b7b0 11888 pipe_config->lane_count,
b95af8be
VK		 11889 pipe_config->dp_m2_n2.gmch_m,
11890 pipe_config->dp_m2_n2.gmch_n,
11891 pipe_config->dp_m2_n2.link_m,
11892 pipe_config->dp_m2_n2.link_n,
11893 pipe_config->dp_m2_n2.tu);
11894
55072d19
DV		 11895 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11896 pipe_config->has_audio,
11897 pipe_config->has_infoframe);
11898
c0b03411 11899 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11900 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11901 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11902 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11903 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11904 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11905 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11906 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11907 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11908 crtc->num_scalers,
11909 pipe_config->scaler_state.scaler_users,
11910 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11911 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11912 pipe_config->gmch_pfit.control,
11913 pipe_config->gmch_pfit.pgm_ratios,
11914 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11915 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11916 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11917 pipe_config->pch_pfit.size,
11918 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11919 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11920 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11921
415ff0f6 11922 if (IS_BROXTON(dev)) {
05712c15 11923 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 11924 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 11925 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 11926 pipe_config->ddi_pll_sel,
11927 pipe_config->dpll_hw_state.ebb0,
05712c15 11928 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 11929 pipe_config->dpll_hw_state.pll0,
11930 pipe_config->dpll_hw_state.pll1,
11931 pipe_config->dpll_hw_state.pll2,
11932 pipe_config->dpll_hw_state.pll3,
11933 pipe_config->dpll_hw_state.pll6,
11934 pipe_config->dpll_hw_state.pll8,
05712c15 11935 pipe_config->dpll_hw_state.pll9,
c8453338 11936 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 11937 pipe_config->dpll_hw_state.pcsdw12);
11938 } else if (IS_SKYLAKE(dev)) {
11939 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11940 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11941 pipe_config->ddi_pll_sel,
11942 pipe_config->dpll_hw_state.ctrl1,
11943 pipe_config->dpll_hw_state.cfgcr1,
11944 pipe_config->dpll_hw_state.cfgcr2);
11945 } else if (HAS_DDI(dev)) {
11946 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11947 pipe_config->ddi_pll_sel,
11948 pipe_config->dpll_hw_state.wrpll);
11949 } else {
11950 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11951 "fp0: 0x%x, fp1: 0x%x\n",
11952 pipe_config->dpll_hw_state.dpll,
11953 pipe_config->dpll_hw_state.dpll_md,
11954 pipe_config->dpll_hw_state.fp0,
11955 pipe_config->dpll_hw_state.fp1);
11956 }
11957
6a60cd87
CK		 11958 DRM_DEBUG_KMS("planes on this crtc\n");
11959 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11960 intel_plane = to_intel_plane(plane);
11961 if (intel_plane->pipe != crtc->pipe)
11962 continue;
11963
11964 state = to_intel_plane_state(plane->state);
11965 fb = state->base.fb;
11966 if (!fb) {
11967 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11968 "disabled, scaler_id = %d\n",
11969 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11970 plane->base.id, intel_plane->pipe,
11971 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11972 drm_plane_index(plane), state->scaler_id);
11973 continue;
11974 }
11975
11976 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11977 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11978 plane->base.id, intel_plane->pipe,
11979 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11980 drm_plane_index(plane));
11981 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11982 fb->base.id, fb->width, fb->height, fb->pixel_format);
11983 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11984 state->scaler_id,
11985 state->src.x1 >> 16, state->src.y1 >> 16,
11986 drm_rect_width(&state->src) >> 16,
11987 drm_rect_height(&state->src) >> 16,
11988 state->dst.x1, state->dst.y1,
11989 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11990 }
c0b03411
DV		 11991}
11992
5448a00d 11993static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11994{
5448a00d
ACO		 11995 struct drm_device *dev = state->dev;
11996 struct intel_encoder *encoder;
da3ced29 11997 struct drm_connector *connector;
5448a00d 11998 struct drm_connector_state *connector_state;
00f0b378 11999 unsigned int used_ports = 0;
5448a00d 12000 int i;
00f0b378
VS		 12001
12002 /*
12003 * Walk the connector list instead of the encoder
12004 * list to detect the problem on ddi platforms
12005 * where there's just one encoder per digital port.
12006 */
da3ced29 12007 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12008 if (!connector_state->best_encoder)
00f0b378
VS		 12009 continue;
12010
5448a00d
ACO		 12011 encoder = to_intel_encoder(connector_state->best_encoder);
12012
12013 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12014
12015 switch (encoder->type) {
12016 unsigned int port_mask;
12017 case INTEL_OUTPUT_UNKNOWN:
12018 if (WARN_ON(!HAS_DDI(dev)))
12019 break;
12020 case INTEL_OUTPUT_DISPLAYPORT:
12021 case INTEL_OUTPUT_HDMI:
12022 case INTEL_OUTPUT_EDP:
12023 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12024
12025 /* the same port mustn't appear more than once */
12026 if (used_ports & port_mask)
12027 return false;
12028
12029 used_ports |= port_mask;
12030 default:
12031 break;
12032 }
12033 }
12034
12035 return true;
12036}
12037
83a57153
ACO		 12038static void
12039clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12040{
12041 struct drm_crtc_state tmp_state;
663a3640 12042 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12043 struct intel_dpll_hw_state dpll_hw_state;
12044 enum intel_dpll_id shared_dpll;
8504c74c 12045 uint32_t ddi_pll_sel;
c4e2d043 12046 bool force_thru;
83a57153 12047
7546a384
ACO		 12048 /* FIXME: before the switch to atomic started, a new pipe_config was
12049 * kzalloc'd. Code that depends on any field being zero should be
12050 * fixed, so that the crtc_state can be safely duplicated. For now,
12051 * only fields that are know to not cause problems are preserved. */
12052
83a57153 12053 tmp_state = crtc_state->base;
663a3640 12054 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12055 shared_dpll = crtc_state->shared_dpll;
12056 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12057 ddi_pll_sel = crtc_state->ddi_pll_sel;
c4e2d043 12058 force_thru = crtc_state->pch_pfit.force_thru;
4978cc93 12059
83a57153 12060 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12061
83a57153 12062 crtc_state->base = tmp_state;
663a3640 12063 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12064 crtc_state->shared_dpll = shared_dpll;
12065 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12066 crtc_state->ddi_pll_sel = ddi_pll_sel;
c4e2d043 12067 crtc_state->pch_pfit.force_thru = force_thru;
83a57153
ACO		 12068}
12069
548ee15b 12070static int
b8cecdf5 12071intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12072 struct intel_crtc_state *pipe_config)
ee7b9f93 12073{
b359283a 12074 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12075 struct intel_encoder *encoder;
da3ced29 12076 struct drm_connector *connector;
0b901879 12077 struct drm_connector_state *connector_state;
d328c9d7 12078 int base_bpp, ret = -EINVAL;
0b901879 12079 int i;
e29c22c0 12080 bool retry = true;
ee7b9f93 12081
83a57153 12082 clear_intel_crtc_state(pipe_config);
7758a113 12083
e143a21c
DV		 12084 pipe_config->cpu_transcoder =
12085 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12086
2960bc9c
ID		 12087 /*
12088 * Sanitize sync polarity flags based on requested ones. If neither
12089 * positive or negative polarity is requested, treat this as meaning
12090 * negative polarity.
12091 */
2d112de7 12092 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12093 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12094 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12095
2d112de7 12096 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12097 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12098 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12099
d328c9d7
DV		 12100 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12101 pipe_config);
12102 if (base_bpp < 0)
4e53c2e0
DV		 12103 goto fail;
12104
e41a56be
VS		 12105 /*
12106 * Determine the real pipe dimensions. Note that stereo modes can
12107 * increase the actual pipe size due to the frame doubling and
12108 * insertion of additional space for blanks between the frame. This
12109 * is stored in the crtc timings. We use the requested mode to do this
12110 * computation to clearly distinguish it from the adjusted mode, which
12111 * can be changed by the connectors in the below retry loop.
12112 */
2d112de7 12113 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12114 &pipe_config->pipe_src_w,
12115 &pipe_config->pipe_src_h);
e41a56be 12116
e29c22c0 12117encoder_retry:
ef1b460d 12118 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12119 pipe_config->port_clock = 0;
ef1b460d 12120 pipe_config->pixel_multiplier = 1;
ff9a6750 12121
135c81b8 12122 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12123 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12124 CRTC_STEREO_DOUBLE);
135c81b8 12125
7758a113
DV		 12126 /* Pass our mode to the connectors and the CRTC to give them a chance to
12127 * adjust it according to limitations or connector properties, and also
12128 * a chance to reject the mode entirely.
47f1c6c9 12129 */
da3ced29 12130 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12131 if (connector_state->crtc != crtc)
7758a113 12132 continue;
7ae89233 12133
0b901879
ACO		 12134 encoder = to_intel_encoder(connector_state->best_encoder);
12135
efea6e8e
DV		 12136 if (!(encoder->compute_config(encoder, pipe_config))) {
12137 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12138 goto fail;
12139 }
ee7b9f93 12140 }
47f1c6c9 12141
ff9a6750
DV		 12142 /* Set default port clock if not overwritten by the encoder. Needs to be
12143 * done afterwards in case the encoder adjusts the mode. */
12144 if (!pipe_config->port_clock)
2d112de7 12145 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12146 * pipe_config->pixel_multiplier;
ff9a6750 12147
a43f6e0f 12148 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12149 if (ret < 0) {
7758a113
DV		 12150 DRM_DEBUG_KMS("CRTC fixup failed\n");
12151 goto fail;
ee7b9f93 12152 }
e29c22c0
DV		 12153
12154 if (ret == RETRY) {
12155 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12156 ret = -EINVAL;
12157 goto fail;
12158 }
12159
12160 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12161 retry = false;
12162 goto encoder_retry;
12163 }
12164
e8fa4270
DV		 12165 /* Dithering seems to not pass-through bits correctly when it should, so
12166 * only enable it on 6bpc panels. */
12167 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
62f0ace5 12168 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12169 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12170
7758a113 12171fail:
548ee15b 12172 return ret;
ee7b9f93 12173}
47f1c6c9 12174
ea9d758d 12175static void
4740b0f2 12176intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 12177{
0a9ab303
ACO		 12178 struct drm_crtc *crtc;
12179 struct drm_crtc_state *crtc_state;
8a75d157 12180 int i;
ea9d758d 12181
7668851f 12182 /* Double check state. */
8a75d157 12183 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3cb480bc 12184 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12185
12186 /* Update hwmode for vblank functions */
12187 if (crtc->state->active)
12188 crtc->hwmode = crtc->state->adjusted_mode;
12189 else
12190 crtc->hwmode.crtc_clock = 0;
ea9d758d 12191 }
ea9d758d
DV		 12192}
12193
3bd26263 12194static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12195{
3bd26263 12196 int diff;
f1f644dc
JB		 12197
12198 if (clock1 == clock2)
12199 return true;
12200
12201 if (!clock1 || !clock2)
12202 return false;
12203
12204 diff = abs(clock1 - clock2);
12205
12206 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12207 return true;
12208
12209 return false;
12210}
12211
25c5b266
DV		 12212#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12213 list_for_each_entry((intel_crtc), \
12214 &(dev)->mode_config.crtc_list, \
12215 base.head) \
0973f18f 12216 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12217
cfb23ed6
ML		 12218
12219static bool
12220intel_compare_m_n(unsigned int m, unsigned int n,
12221 unsigned int m2, unsigned int n2,
12222 bool exact)
12223{
12224 if (m == m2 && n == n2)
12225 return true;
12226
12227 if (exact || !m || !n || !m2 || !n2)
12228 return false;
12229
12230 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12231
12232 if (m > m2) {
12233 while (m > m2) {
12234 m2 <<= 1;
12235 n2 <<= 1;
12236 }
12237 } else if (m < m2) {
12238 while (m < m2) {
12239 m <<= 1;
12240 n <<= 1;
12241 }
12242 }
12243
12244 return m == m2 && n == n2;
12245}
12246
12247static bool
12248intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12249 struct intel_link_m_n *m2_n2,
12250 bool adjust)
12251{
12252 if (m_n->tu == m2_n2->tu &&
12253 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12254 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12255 intel_compare_m_n(m_n->link_m, m_n->link_n,
12256 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12257 if (adjust)
12258 *m2_n2 = *m_n;
12259
12260 return true;
12261 }
12262
12263 return false;
12264}
12265
0e8ffe1b 12266static bool
2fa2fe9a 12267intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12268 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12269 struct intel_crtc_state *pipe_config,
12270 bool adjust)
0e8ffe1b 12271{
cfb23ed6
ML		 12272 bool ret = true;
12273
12274#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12275 do { \
12276 if (!adjust) \
12277 DRM_ERROR(fmt, ##__VA_ARGS__); \
12278 else \
12279 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12280 } while (0)
12281
66e985c0
DV		 12282#define PIPE_CONF_CHECK_X(name) \
12283 if (current_config->name != pipe_config->name) { \
cfb23ed6 12284 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12285 "(expected 0x%08x, found 0x%08x)\n", \
12286 current_config->name, \
12287 pipe_config->name); \
cfb23ed6 12288 ret = false; \
66e985c0
DV		 12289 }
12290
08a24034
DV		 12291#define PIPE_CONF_CHECK_I(name) \
12292 if (current_config->name != pipe_config->name) { \
cfb23ed6 12293 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12294 "(expected %i, found %i)\n", \
12295 current_config->name, \
12296 pipe_config->name); \
cfb23ed6
ML		 12297 ret = false; \
12298 }
12299
12300#define PIPE_CONF_CHECK_M_N(name) \
12301 if (!intel_compare_link_m_n(&current_config->name, \
12302 &pipe_config->name,\
12303 adjust)) { \
12304 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12305 "(expected tu %i gmch %i/%i link %i/%i, " \
12306 "found tu %i, gmch %i/%i link %i/%i)\n", \
12307 current_config->name.tu, \
12308 current_config->name.gmch_m, \
12309 current_config->name.gmch_n, \
12310 current_config->name.link_m, \
12311 current_config->name.link_n, \
12312 pipe_config->name.tu, \
12313 pipe_config->name.gmch_m, \
12314 pipe_config->name.gmch_n, \
12315 pipe_config->name.link_m, \
12316 pipe_config->name.link_n); \
12317 ret = false; \
12318 }
12319
12320#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12321 if (!intel_compare_link_m_n(&current_config->name, \
12322 &pipe_config->name, adjust) && \
12323 !intel_compare_link_m_n(&current_config->alt_name, \
12324 &pipe_config->name, adjust)) { \
12325 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12326 "(expected tu %i gmch %i/%i link %i/%i, " \
12327 "or tu %i gmch %i/%i link %i/%i, " \
12328 "found tu %i, gmch %i/%i link %i/%i)\n", \
12329 current_config->name.tu, \
12330 current_config->name.gmch_m, \
12331 current_config->name.gmch_n, \
12332 current_config->name.link_m, \
12333 current_config->name.link_n, \
12334 current_config->alt_name.tu, \
12335 current_config->alt_name.gmch_m, \
12336 current_config->alt_name.gmch_n, \
12337 current_config->alt_name.link_m, \
12338 current_config->alt_name.link_n, \
12339 pipe_config->name.tu, \
12340 pipe_config->name.gmch_m, \
12341 pipe_config->name.gmch_n, \
12342 pipe_config->name.link_m, \
12343 pipe_config->name.link_n); \
12344 ret = false; \
88adfff1
DV		 12345 }
12346
b95af8be
VK		 12347/* This is required for BDW+ where there is only one set of registers for
12348 * switching between high and low RR.
12349 * This macro can be used whenever a comparison has to be made between one
12350 * hw state and multiple sw state variables.
12351 */
12352#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12353 if ((current_config->name != pipe_config->name) && \
12354 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12355 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12356 "(expected %i or %i, found %i)\n", \
12357 current_config->name, \
12358 current_config->alt_name, \
12359 pipe_config->name); \
cfb23ed6 12360 ret = false; \
b95af8be
VK		 12361 }
12362
1bd1bd80
DV		 12363#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12364 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12365 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12366 "(expected %i, found %i)\n", \
12367 current_config->name & (mask), \
12368 pipe_config->name & (mask)); \
cfb23ed6 12369 ret = false; \
1bd1bd80
DV		 12370 }
12371
5e550656
VS		 12372#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12373 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12374 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12375 "(expected %i, found %i)\n", \
12376 current_config->name, \
12377 pipe_config->name); \
cfb23ed6 12378 ret = false; \
5e550656
VS		 12379 }
12380
bb760063
DV		 12381#define PIPE_CONF_QUIRK(quirk) \
12382 ((current_config->quirks | pipe_config->quirks) & (quirk))
12383
eccb140b
DV		 12384 PIPE_CONF_CHECK_I(cpu_transcoder);
12385
08a24034
DV		 12386 PIPE_CONF_CHECK_I(has_pch_encoder);
12387 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12388 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12389
eb14cb74 12390 PIPE_CONF_CHECK_I(has_dp_encoder);
90a6b7b0 12391 PIPE_CONF_CHECK_I(lane_count);
b95af8be
VK		 12392
12393 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12394 PIPE_CONF_CHECK_M_N(dp_m_n);
12395
12396 PIPE_CONF_CHECK_I(has_drrs);
12397 if (current_config->has_drrs)
12398 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12399 } else
12400 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12401
2d112de7
ACO		 12402 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12403 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12404 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12405 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12406 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12407 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12408
2d112de7
ACO		 12409 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12410 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12411 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12412 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12413 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12414 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12415
c93f54cf 12416 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12417 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12418 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12419 IS_VALLEYVIEW(dev))
12420 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12421 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12422
9ed109a7
DV		 12423 PIPE_CONF_CHECK_I(has_audio);
12424
2d112de7 12425 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12426 DRM_MODE_FLAG_INTERLACE);
12427
bb760063 12428 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12429 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12430 DRM_MODE_FLAG_PHSYNC);
2d112de7 12431 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12432 DRM_MODE_FLAG_NHSYNC);
2d112de7 12433 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12434 DRM_MODE_FLAG_PVSYNC);
2d112de7 12435 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12436 DRM_MODE_FLAG_NVSYNC);
12437 }
045ac3b5 12438
37327abd
VS		 12439 PIPE_CONF_CHECK_I(pipe_src_w);
12440 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12441
333b8ca8 12442 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a
DV		 12443 /* pfit ratios are autocomputed by the hw on gen4+ */
12444 if (INTEL_INFO(dev)->gen < 4)
12445 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
333b8ca8 12446 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 12447
fd4daa9c
CW		 12448 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12449 if (current_config->pch_pfit.enabled) {
333b8ca8
VS		 12450 PIPE_CONF_CHECK_X(pch_pfit.pos);
12451 PIPE_CONF_CHECK_X(pch_pfit.size);
fd4daa9c 12452 }
2fa2fe9a 12453
a1b2278e
CK		 12454 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12455
e59150dc
JB		 12456 /* BDW+ don't expose a synchronous way to read the state */
12457 if (IS_HASWELL(dev))
12458 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12459
282740f7
VS		 12460 PIPE_CONF_CHECK_I(double_wide);
12461
26804afd
DV		 12462 PIPE_CONF_CHECK_X(ddi_pll_sel);
12463
c0d43d62 12464 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12465 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12466 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12467 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12468 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12469 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12470 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12471 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12472 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12473
42571aef
VS		 12474 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12475 PIPE_CONF_CHECK_I(pipe_bpp);
12476
2d112de7 12477 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12478 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12479
66e985c0 12480#undef PIPE_CONF_CHECK_X
08a24034 12481#undef PIPE_CONF_CHECK_I
b95af8be 12482#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12483#undef PIPE_CONF_CHECK_FLAGS
5e550656 12484#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12485#undef PIPE_CONF_QUIRK
cfb23ed6 12486#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12487
cfb23ed6 12488 return ret;
0e8ffe1b
DV		 12489}
12490
08db6652
DL		 12491static void check_wm_state(struct drm_device *dev)
12492{
12493 struct drm_i915_private *dev_priv = dev->dev_private;
12494 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12495 struct intel_crtc *intel_crtc;
12496 int plane;
12497
12498 if (INTEL_INFO(dev)->gen < 9)
12499 return;
12500
12501 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12502 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12503
12504 for_each_intel_crtc(dev, intel_crtc) {
12505 struct skl_ddb_entry *hw_entry, *sw_entry;
12506 const enum pipe pipe = intel_crtc->pipe;
12507
12508 if (!intel_crtc->active)
12509 continue;
12510
12511 /* planes */
dd740780 12512 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12513 hw_entry = &hw_ddb.plane[pipe][plane];
12514 sw_entry = &sw_ddb->plane[pipe][plane];
12515
12516 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12517 continue;
12518
12519 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12520 "(expected (%u,%u), found (%u,%u))\n",
12521 pipe_name(pipe), plane + 1,
12522 sw_entry->start, sw_entry->end,
12523 hw_entry->start, hw_entry->end);
12524 }
12525
12526 /* cursor */
12527 hw_entry = &hw_ddb.cursor[pipe];
12528 sw_entry = &sw_ddb->cursor[pipe];
12529
12530 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12531 continue;
12532
12533 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12534 "(expected (%u,%u), found (%u,%u))\n",
12535 pipe_name(pipe),
12536 sw_entry->start, sw_entry->end,
12537 hw_entry->start, hw_entry->end);
12538 }
12539}
12540
91d1b4bd 12541static void
35dd3c64
ML		 12542check_connector_state(struct drm_device *dev,
12543 struct drm_atomic_state *old_state)
8af6cf88 12544{
35dd3c64
ML		 12545 struct drm_connector_state *old_conn_state;
12546 struct drm_connector *connector;
12547 int i;
8af6cf88 12548
35dd3c64
ML		 12549 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12550 struct drm_encoder *encoder = connector->encoder;
12551 struct drm_connector_state *state = connector->state;
ad3c558f 12552
8af6cf88
DV		 12553 /* This also checks the encoder/connector hw state with the
12554 * ->get_hw_state callbacks. */
35dd3c64 12555 intel_connector_check_state(to_intel_connector(connector));
8af6cf88 12556
ad3c558f 12557 I915_STATE_WARN(state->best_encoder != encoder,
35dd3c64 12558 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 12559 }
91d1b4bd
DV		 12560}
12561
12562static void
12563check_encoder_state(struct drm_device *dev)
12564{
12565 struct intel_encoder *encoder;
12566 struct intel_connector *connector;
8af6cf88 12567
b2784e15 12568 for_each_intel_encoder(dev, encoder) {
8af6cf88 12569 bool enabled = false;
4d20cd86 12570 enum pipe pipe;
8af6cf88
DV		 12571
12572 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12573 encoder->base.base.id,
8e329a03 12574 encoder->base.name);
8af6cf88 12575
3a3371ff 12576 for_each_intel_connector(dev, connector) {
4d20cd86 12577 if (connector->base.state->best_encoder != &encoder->base)
8af6cf88
DV		 12578 continue;
12579 enabled = true;
ad3c558f
ML		 12580
12581 I915_STATE_WARN(connector->base.state->crtc !=
12582 encoder->base.crtc,
12583 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12584 }
0e32b39c 12585
e2c719b7 12586 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12587 "encoder's enabled state mismatch "
12588 "(expected %i, found %i)\n",
12589 !!encoder->base.crtc, enabled);
7c60d198
ML		 12590
12591 if (!encoder->base.crtc) {
4d20cd86 12592 bool active;
7c60d198 12593
4d20cd86
ML		 12594 active = encoder->get_hw_state(encoder, &pipe);
12595 I915_STATE_WARN(active,
12596 "encoder detached but still enabled on pipe %c.\n",
12597 pipe_name(pipe));
7c60d198 12598 }
8af6cf88 12599 }
91d1b4bd
DV		 12600}
12601
12602static void
4d20cd86 12603check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
91d1b4bd 12604{
fbee40df 12605 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd 12606 struct intel_encoder *encoder;
4d20cd86
ML		 12607 struct drm_crtc_state *old_crtc_state;
12608 struct drm_crtc *crtc;
12609 int i;
8af6cf88 12610
4d20cd86
ML		 12611 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12613 struct intel_crtc_state *pipe_config, *sw_config;
7b89b8de 12614 bool active;
8af6cf88 12615
4d20cd86
ML		 12616 if (!needs_modeset(crtc->state))
12617 continue;
045ac3b5 12618
4d20cd86
ML		 12619 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12620 pipe_config = to_intel_crtc_state(old_crtc_state);
12621 memset(pipe_config, 0, sizeof(*pipe_config));
12622 pipe_config->base.crtc = crtc;
12623 pipe_config->base.state = old_state;
8af6cf88 12624
4d20cd86
ML		 12625 DRM_DEBUG_KMS("[CRTC:%d]\n",
12626 crtc->base.id);
8af6cf88 12627
4d20cd86
ML		 12628 active = dev_priv->display.get_pipe_config(intel_crtc,
12629 pipe_config);
d62cf62a 12630
b6b5d049 12631 /* hw state is inconsistent with the pipe quirk */
4d20cd86
ML		 12632 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12633 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12634 active = crtc->state->active;
6c49f241 12635
4d20cd86 12636 I915_STATE_WARN(crtc->state->active != active,
0e8ffe1b 12637 "crtc active state doesn't match with hw state "
4d20cd86 12638 "(expected %i, found %i)\n", crtc->state->active, active);
0e8ffe1b 12639
4d20cd86 12640 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
53d9f4e9 12641 "transitional active state does not match atomic hw state "
4d20cd86
ML		 12642 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12643
12644 for_each_encoder_on_crtc(dev, crtc, encoder) {
12645 enum pipe pipe;
12646
12647 active = encoder->get_hw_state(encoder, &pipe);
12648 I915_STATE_WARN(active != crtc->state->active,
12649 "[ENCODER:%i] active %i with crtc active %i\n",
12650 encoder->base.base.id, active, crtc->state->active);
12651
12652 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12653 "Encoder connected to wrong pipe %c\n",
12654 pipe_name(pipe));
12655
12656 if (active)
12657 encoder->get_config(encoder, pipe_config);
12658 }
53d9f4e9 12659
4d20cd86 12660 if (!crtc->state->active)
cfb23ed6
ML		 12661 continue;
12662
4d20cd86
ML		 12663 sw_config = to_intel_crtc_state(crtc->state);
12664 if (!intel_pipe_config_compare(dev, sw_config,
12665 pipe_config, false)) {
e2c719b7 12666 I915_STATE_WARN(1, "pipe state doesn't match!\n");
4d20cd86 12667 intel_dump_pipe_config(intel_crtc, pipe_config,
c0b03411 12668 "[hw state]");
4d20cd86 12669 intel_dump_pipe_config(intel_crtc, sw_config,
c0b03411
DV		 12670 "[sw state]");
12671 }
8af6cf88
DV		 12672 }
12673}
12674
91d1b4bd
DV		 12675static void
12676check_shared_dpll_state(struct drm_device *dev)
12677{
fbee40df 12678 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12679 struct intel_crtc *crtc;
12680 struct intel_dpll_hw_state dpll_hw_state;
12681 int i;
5358901f
DV		 12682
12683 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12684 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12685 int enabled_crtcs = 0, active_crtcs = 0;
12686 bool active;
12687
12688 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12689
12690 DRM_DEBUG_KMS("%s\n", pll->name);
12691
12692 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12693
e2c719b7 12694 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12695 "more active pll users than references: %i vs %i\n",
3e369b76 12696 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12697 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12698 "pll in active use but not on in sw tracking\n");
e2c719b7 12699 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12700 "pll in on but not on in use in sw tracking\n");
e2c719b7 12701 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12702 "pll on state mismatch (expected %i, found %i)\n",
12703 pll->on, active);
12704
d3fcc808 12705 for_each_intel_crtc(dev, crtc) {
83d65738 12706 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12707 enabled_crtcs++;
12708 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12709 active_crtcs++;
12710 }
e2c719b7 12711 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12712 "pll active crtcs mismatch (expected %i, found %i)\n",
12713 pll->active, active_crtcs);
e2c719b7 12714 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12715 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12716 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12717
e2c719b7 12718 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12719 sizeof(dpll_hw_state)),
12720 "pll hw state mismatch\n");
5358901f 12721 }
8af6cf88
DV		 12722}
12723
ee165b1a
ML		 12724static void
12725intel_modeset_check_state(struct drm_device *dev,
12726 struct drm_atomic_state *old_state)
91d1b4bd 12727{
08db6652 12728 check_wm_state(dev);
35dd3c64 12729 check_connector_state(dev, old_state);
91d1b4bd 12730 check_encoder_state(dev);
4d20cd86 12731 check_crtc_state(dev, old_state);
91d1b4bd
DV		 12732 check_shared_dpll_state(dev);
12733}
12734
5cec258b 12735void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12736 int dotclock)
12737{
12738 /*
12739 * FDI already provided one idea for the dotclock.
12740 * Yell if the encoder disagrees.
12741 */
2d112de7 12742 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12743 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12744 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12745}
12746
80715b2f
VS		 12747static void update_scanline_offset(struct intel_crtc *crtc)
12748{
12749 struct drm_device *dev = crtc->base.dev;
12750
12751 /*
12752 * The scanline counter increments at the leading edge of hsync.
12753 *
12754 * On most platforms it starts counting from vtotal-1 on the
12755 * first active line. That means the scanline counter value is
12756 * always one less than what we would expect. Ie. just after
12757 * start of vblank, which also occurs at start of hsync (on the
12758 * last active line), the scanline counter will read vblank_start-1.
12759 *
12760 * On gen2 the scanline counter starts counting from 1 instead
12761 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12762 * to keep the value positive), instead of adding one.
12763 *
12764 * On HSW+ the behaviour of the scanline counter depends on the output
12765 * type. For DP ports it behaves like most other platforms, but on HDMI
12766 * there's an extra 1 line difference. So we need to add two instead of
12767 * one to the value.
12768 */
12769 if (IS_GEN2(dev)) {
6e3c9717 12770 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12771 int vtotal;
12772
12773 vtotal = mode->crtc_vtotal;
12774 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12775 vtotal /= 2;
12776
12777 crtc->scanline_offset = vtotal - 1;
12778 } else if (HAS_DDI(dev) &&
409ee761 12779 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12780 crtc->scanline_offset = 2;
12781 } else
12782 crtc->scanline_offset = 1;
12783}
12784
ad421372 12785static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12786{
225da59b 12787 struct drm_device *dev = state->dev;
ed6739ef 12788 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12789 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12790 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12791 struct intel_crtc_state *intel_crtc_state;
12792 struct drm_crtc *crtc;
12793 struct drm_crtc_state *crtc_state;
0a9ab303 12794 int i;
ed6739ef
ACO		 12795
12796 if (!dev_priv->display.crtc_compute_clock)
ad421372 12797 return;
ed6739ef 12798
0a9ab303 12799 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12800 int dpll;
12801
0a9ab303 12802 intel_crtc = to_intel_crtc(crtc);
4978cc93 12803 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12804 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12805
ad421372 12806 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12807 continue;
12808
ad421372 12809 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12810
ad421372
ML		 12811 if (!shared_dpll)
12812 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12813
ad421372
ML		 12814 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12815 }
ed6739ef
ACO		 12816}
12817
99d736a2
ML		 12818/*
12819 * This implements the workaround described in the "notes" section of the mode
12820 * set sequence documentation. When going from no pipes or single pipe to
12821 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12822 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12823 */
12824static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12825{
12826 struct drm_crtc_state *crtc_state;
12827 struct intel_crtc *intel_crtc;
12828 struct drm_crtc *crtc;
12829 struct intel_crtc_state *first_crtc_state = NULL;
12830 struct intel_crtc_state *other_crtc_state = NULL;
12831 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12832 int i;
12833
12834 /* look at all crtc's that are going to be enabled in during modeset */
12835 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12836 intel_crtc = to_intel_crtc(crtc);
12837
12838 if (!crtc_state->active || !needs_modeset(crtc_state))
12839 continue;
12840
12841 if (first_crtc_state) {
12842 other_crtc_state = to_intel_crtc_state(crtc_state);
12843 break;
12844 } else {
12845 first_crtc_state = to_intel_crtc_state(crtc_state);
12846 first_pipe = intel_crtc->pipe;
12847 }
12848 }
12849
12850 /* No workaround needed? */
12851 if (!first_crtc_state)
12852 return 0;
12853
12854 /* w/a possibly needed, check how many crtc's are already enabled. */
12855 for_each_intel_crtc(state->dev, intel_crtc) {
12856 struct intel_crtc_state *pipe_config;
12857
12858 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12859 if (IS_ERR(pipe_config))
12860 return PTR_ERR(pipe_config);
12861
12862 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12863
12864 if (!pipe_config->base.active ||
12865 needs_modeset(&pipe_config->base))
12866 continue;
12867
12868 /* 2 or more enabled crtcs means no need for w/a */
12869 if (enabled_pipe != INVALID_PIPE)
12870 return 0;
12871
12872 enabled_pipe = intel_crtc->pipe;
12873 }
12874
12875 if (enabled_pipe != INVALID_PIPE)
12876 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12877 else if (other_crtc_state)
12878 other_crtc_state->hsw_workaround_pipe = first_pipe;
12879
12880 return 0;
12881}
12882
27c329ed
ML		 12883static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12884{
12885 struct drm_crtc *crtc;
12886 struct drm_crtc_state *crtc_state;
12887 int ret = 0;
12888
12889 /* add all active pipes to the state */
12890 for_each_crtc(state->dev, crtc) {
12891 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12892 if (IS_ERR(crtc_state))
12893 return PTR_ERR(crtc_state);
12894
12895 if (!crtc_state->active || needs_modeset(crtc_state))
12896 continue;
12897
12898 crtc_state->mode_changed = true;
12899
12900 ret = drm_atomic_add_affected_connectors(state, crtc);
12901 if (ret)
12902 break;
12903
12904 ret = drm_atomic_add_affected_planes(state, crtc);
12905 if (ret)
12906 break;
12907 }
12908
12909 return ret;
12910}
12911
12912
c347a676 12913static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12914{
12915 struct drm_device *dev = state->dev;
27c329ed 12916 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12917 int ret;
12918
b359283a
ML		 12919 if (!check_digital_port_conflicts(state)) {
12920 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12921 return -EINVAL;
12922 }
12923
054518dd
ACO		 12924 /*
12925 * See if the config requires any additional preparation, e.g.
12926 * to adjust global state with pipes off. We need to do this
12927 * here so we can get the modeset_pipe updated config for the new
12928 * mode set on this crtc. For other crtcs we need to use the
12929 * adjusted_mode bits in the crtc directly.
12930 */
27c329ed
ML		 12931 if (dev_priv->display.modeset_calc_cdclk) {
12932 unsigned int cdclk;
b432e5cf 12933
27c329ed
ML		 12934 ret = dev_priv->display.modeset_calc_cdclk(state);
12935
12936 cdclk = to_intel_atomic_state(state)->cdclk;
12937 if (!ret && cdclk != dev_priv->cdclk_freq)
12938 ret = intel_modeset_all_pipes(state);
12939
12940 if (ret < 0)
054518dd 12941 return ret;
27c329ed
ML		 12942 } else
12943 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 12944
ad421372 12945 intel_modeset_clear_plls(state);
054518dd 12946
99d736a2 12947 if (IS_HASWELL(dev))
ad421372 12948 return haswell_mode_set_planes_workaround(state);
99d736a2 12949
ad421372 12950 return 0;
c347a676
ACO		 12951}
12952
74c090b1
ML		 12953/**
12954 * intel_atomic_check - validate state object
12955 * @dev: drm device
12956 * @state: state to validate
12957 */
12958static int intel_atomic_check(struct drm_device *dev,
12959 struct drm_atomic_state *state)
c347a676
ACO		 12960{
12961 struct drm_crtc *crtc;
12962 struct drm_crtc_state *crtc_state;
12963 int ret, i;
61333b60 12964 bool any_ms = false;
c347a676 12965
74c090b1 12966 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 12967 if (ret)
12968 return ret;
12969
c347a676 12970 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 12971 struct intel_crtc_state *pipe_config =
12972 to_intel_crtc_state(crtc_state);
1ed51de9
DV		 12973
12974 /* Catch I915_MODE_FLAG_INHERITED */
12975 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
12976 crtc_state->mode_changed = true;
cfb23ed6 12977
61333b60
ML		 12978 if (!crtc_state->enable) {
12979 if (needs_modeset(crtc_state))
12980 any_ms = true;
c347a676 12981 continue;
61333b60 12982 }
c347a676 12983
26495481 12984 if (!needs_modeset(crtc_state))
cfb23ed6
ML		 12985 continue;
12986
26495481
DV		 12987 /* FIXME: For only active_changed we shouldn't need to do any
12988 * state recomputation at all. */
12989
1ed51de9
DV		 12990 ret = drm_atomic_add_affected_connectors(state, crtc);
12991 if (ret)
12992 return ret;
b359283a 12993
cfb23ed6 12994 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 12995 if (ret)
12996 return ret;
12997
26495481
DV		 12998 if (i915.fastboot &&
12999 intel_pipe_config_compare(state->dev,
cfb23ed6 13000 to_intel_crtc_state(crtc->state),
1ed51de9 13001 pipe_config, true)) {
26495481
DV		 13002 crtc_state->mode_changed = false;
13003 }
13004
13005 if (needs_modeset(crtc_state)) {
13006 any_ms = true;
cfb23ed6
ML		 13007
13008 ret = drm_atomic_add_affected_planes(state, crtc);
13009 if (ret)
13010 return ret;
13011 }
61333b60 13012
26495481
DV		 13013 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13014 needs_modeset(crtc_state) ?
13015 "[modeset]" : "[fastset]");
c347a676
ACO		 13016 }
13017
61333b60
ML		 13018 if (any_ms) {
13019 ret = intel_modeset_checks(state);
13020
13021 if (ret)
13022 return ret;
27c329ed
ML		 13023 } else
13024 to_intel_atomic_state(state)->cdclk =
13025 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13026
13027 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13028}
13029
74c090b1
ML		 13030/**
13031 * intel_atomic_commit - commit validated state object
13032 * @dev: DRM device
13033 * @state: the top-level driver state object
13034 * @async: asynchronous commit
13035 *
13036 * This function commits a top-level state object that has been validated
13037 * with drm_atomic_helper_check().
13038 *
13039 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13040 * we can only handle plane-related operations and do not yet support
13041 * asynchronous commit.
13042 *
13043 * RETURNS
13044 * Zero for success or -errno.
13045 */
13046static int intel_atomic_commit(struct drm_device *dev,
13047 struct drm_atomic_state *state,
13048 bool async)
a6778b3c 13049{
fbee40df 13050 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13051 struct drm_crtc *crtc;
13052 struct drm_crtc_state *crtc_state;
c0c36b94 13053 int ret = 0;
0a9ab303 13054 int i;
61333b60 13055 bool any_ms = false;
a6778b3c 13056
74c090b1
ML		 13057 if (async) {
13058 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13059 return -EINVAL;
13060 }
13061
d4afb8cc
ACO		 13062 ret = drm_atomic_helper_prepare_planes(dev, state);
13063 if (ret)
13064 return ret;
13065
1c5e19f8
ML		 13066 drm_atomic_helper_swap_state(dev, state);
13067
0a9ab303 13068 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13070
61333b60
ML		 13071 if (!needs_modeset(crtc->state))
13072 continue;
13073
13074 any_ms = true;
a539205a 13075 intel_pre_plane_update(intel_crtc);
460da916 13076
a539205a
ML		 13077 if (crtc_state->active) {
13078 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13079 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13080 intel_crtc->active = false;
13081 intel_disable_shared_dpll(intel_crtc);
a539205a 13082 }
b8cecdf5 13083 }
7758a113 13084
ea9d758d
DV		 13085 /* Only after disabling all output pipelines that will be changed can we
13086 * update the the output configuration. */
4740b0f2 13087 intel_modeset_update_crtc_state(state);
f6e5b160 13088
4740b0f2
ML		 13089 if (any_ms) {
13090 intel_shared_dpll_commit(state);
13091
13092 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
61333b60 13093 modeset_update_crtc_power_domains(state);
4740b0f2 13094 }
47fab737 13095
a6778b3c 13096 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13097 for_each_crtc_in_state(state, crtc, crtc_state, i) {
f6ac4b2a
ML		 13098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13099 bool modeset = needs_modeset(crtc->state);
13100
13101 if (modeset && crtc->state->active) {
a539205a
ML		 13102 update_scanline_offset(to_intel_crtc(crtc));
13103 dev_priv->display.crtc_enable(crtc);
13104 }
80715b2f 13105
f6ac4b2a
ML		 13106 if (!modeset)
13107 intel_pre_plane_update(intel_crtc);
13108
a539205a 13109 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
f6ac4b2a 13110 intel_post_plane_update(intel_crtc);
80715b2f 13111 }
a6778b3c 13112
a6778b3c 13113 /* FIXME: add subpixel order */
83a57153 13114
74c090b1 13115 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13116 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627 13117
74c090b1 13118 if (any_ms)
ee165b1a
ML		 13119 intel_modeset_check_state(dev, state);
13120
13121 drm_atomic_state_free(state);
f30da187 13122
74c090b1 13123 return 0;
7f27126e
JB		 13124}
13125
c0c36b94
CW		 13126void intel_crtc_restore_mode(struct drm_crtc *crtc)
13127{
83a57153
ACO		 13128 struct drm_device *dev = crtc->dev;
13129 struct drm_atomic_state *state;
e694eb02 13130 struct drm_crtc_state *crtc_state;
2bfb4627 13131 int ret;
83a57153
ACO		 13132
13133 state = drm_atomic_state_alloc(dev);
13134 if (!state) {
e694eb02 13135 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13136 crtc->base.id);
13137 return;
13138 }
13139
e694eb02 13140 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13141
e694eb02
ML		 13142retry:
13143 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13144 ret = PTR_ERR_OR_ZERO(crtc_state);
13145 if (!ret) {
13146 if (!crtc_state->active)
13147 goto out;
83a57153 13148
e694eb02 13149 crtc_state->mode_changed = true;
74c090b1 13150 ret = drm_atomic_commit(state);
83a57153
ACO		 13151 }
13152
e694eb02
ML		 13153 if (ret == -EDEADLK) {
13154 drm_atomic_state_clear(state);
13155 drm_modeset_backoff(state->acquire_ctx);
13156 goto retry;
4ed9fb37 13157 }
4be07317 13158
2bfb4627 13159 if (ret)
e694eb02 13160out:
2bfb4627 13161 drm_atomic_state_free(state);
c0c36b94
CW		 13162}
13163
25c5b266
DV		 13164#undef for_each_intel_crtc_masked
13165
f6e5b160 13166static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13167 .gamma_set = intel_crtc_gamma_set,
74c090b1 13168 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13169 .destroy = intel_crtc_destroy,
13170 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13171 .atomic_duplicate_state = intel_crtc_duplicate_state,
13172 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13173};
13174
5358901f
DV		 13175static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13176 struct intel_shared_dpll *pll,
13177 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13178{
5358901f 13179 uint32_t val;
ee7b9f93 13180
f458ebbc 13181 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13182 return false;
13183
5358901f 13184 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13185 hw_state->dpll = val;
13186 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13187 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13188
13189 return val & DPLL_VCO_ENABLE;
13190}
13191
15bdd4cf
DV		 13192static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13193 struct intel_shared_dpll *pll)
13194{
3e369b76
ACO		 13195 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13196 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13197}
13198
e7b903d2
DV		 13199static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13200 struct intel_shared_dpll *pll)
13201{
e7b903d2 13202 /* PCH refclock must be enabled first */
89eff4be 13203 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13204
3e369b76 13205 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13206
13207 /* Wait for the clocks to stabilize. */
13208 POSTING_READ(PCH_DPLL(pll->id));
13209 udelay(150);
13210
13211 /* The pixel multiplier can only be updated once the
13212 * DPLL is enabled and the clocks are stable.
13213 *
13214 * So write it again.
13215 */
3e369b76 13216 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13217 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13218 udelay(200);
13219}
13220
13221static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13222 struct intel_shared_dpll *pll)
13223{
13224 struct drm_device *dev = dev_priv->dev;
13225 struct intel_crtc *crtc;
e7b903d2
DV		 13226
13227 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13228 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13229 if (intel_crtc_to_shared_dpll(crtc) == pll)
13230 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13231 }
13232
15bdd4cf
DV		 13233 I915_WRITE(PCH_DPLL(pll->id), 0);
13234 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13235 udelay(200);
13236}
13237
46edb027
DV		 13238static char *ibx_pch_dpll_names[] = {
13239 "PCH DPLL A",
13240 "PCH DPLL B",
13241};
13242
7c74ade1 13243static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13244{
e7b903d2 13245 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13246 int i;
13247
7c74ade1 13248 dev_priv->num_shared_dpll = 2;
ee7b9f93 13249
e72f9fbf 13250 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13251 dev_priv->shared_dplls[i].id = i;
13252 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13253 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13254 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13255 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13256 dev_priv->shared_dplls[i].get_hw_state =
13257 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13258 }
13259}
13260
7c74ade1
DV		 13261static void intel_shared_dpll_init(struct drm_device *dev)
13262{
e7b903d2 13263 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13264
b6283055
VS		 13265 intel_update_cdclk(dev);
13266
9cd86933
DV		 13267 if (HAS_DDI(dev))
13268 intel_ddi_pll_init(dev);
13269 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13270 ibx_pch_dpll_init(dev);
13271 else
13272 dev_priv->num_shared_dpll = 0;
13273
13274 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13275}
13276
6beb8c23
MR		 13277/**
13278 * intel_prepare_plane_fb - Prepare fb for usage on plane
13279 * @plane: drm plane to prepare for
13280 * @fb: framebuffer to prepare for presentation
13281 *
13282 * Prepares a framebuffer for usage on a display plane. Generally this
13283 * involves pinning the underlying object and updating the frontbuffer tracking
13284 * bits. Some older platforms need special physical address handling for
13285 * cursor planes.
13286 *
13287 * Returns 0 on success, negative error code on failure.
13288 */
13289int
13290intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13291 struct drm_framebuffer *fb,
13292 const struct drm_plane_state *new_state)
465c120c
MR		 13293{
13294 struct drm_device *dev = plane->dev;
6beb8c23 13295 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13296 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13297 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13298 int ret = 0;
465c120c 13299
ea2c67bb 13300 if (!obj)
465c120c
MR		 13301 return 0;
13302
6beb8c23 13303 mutex_lock(&dev->struct_mutex);
465c120c 13304
6beb8c23
MR		 13305 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13306 INTEL_INFO(dev)->cursor_needs_physical) {
13307 int align = IS_I830(dev) ? 16 * 1024 : 256;
13308 ret = i915_gem_object_attach_phys(obj, align);
13309 if (ret)
13310 DRM_DEBUG_KMS("failed to attach phys object\n");
13311 } else {
91af127f 13312 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13313 }
465c120c 13314
6beb8c23 13315 if (ret == 0)
a9ff8714 13316 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13317
4c34574f 13318 mutex_unlock(&dev->struct_mutex);
465c120c 13319
6beb8c23
MR		 13320 return ret;
13321}
13322
38f3ce3a
MR		 13323/**
13324 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13325 * @plane: drm plane to clean up for
13326 * @fb: old framebuffer that was on plane
13327 *
13328 * Cleans up a framebuffer that has just been removed from a plane.
13329 */
13330void
13331intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13332 struct drm_framebuffer *fb,
13333 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13334{
13335 struct drm_device *dev = plane->dev;
13336 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13337
13338 if (WARN_ON(!obj))
13339 return;
13340
13341 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13342 !INTEL_INFO(dev)->cursor_needs_physical) {
13343 mutex_lock(&dev->struct_mutex);
82bc3b2d 13344 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13345 mutex_unlock(&dev->struct_mutex);
13346 }
465c120c
MR		 13347}
13348
6156a456
CK		 13349int
13350skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13351{
13352 int max_scale;
13353 struct drm_device *dev;
13354 struct drm_i915_private *dev_priv;
13355 int crtc_clock, cdclk;
13356
13357 if (!intel_crtc || !crtc_state)
13358 return DRM_PLANE_HELPER_NO_SCALING;
13359
13360 dev = intel_crtc->base.dev;
13361 dev_priv = dev->dev_private;
13362 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13363 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13364
13365 if (!crtc_clock || !cdclk)
13366 return DRM_PLANE_HELPER_NO_SCALING;
13367
13368 /*
13369 * skl max scale is lower of:
13370 * close to 3 but not 3, -1 is for that purpose
13371 * or
13372 * cdclk/crtc_clock
13373 */
13374 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13375
13376 return max_scale;
13377}
13378
465c120c 13379static int
3c692a41 13380intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13381 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13382 struct intel_plane_state *state)
13383{
2b875c22
MR		 13384 struct drm_crtc *crtc = state->base.crtc;
13385 struct drm_framebuffer *fb = state->base.fb;
6156a456 13386 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13387 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13388 bool can_position = false;
465c120c 13389
061e4b8d
ML		 13390 /* use scaler when colorkey is not required */
13391 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13392 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13393 min_scale = 1;
13394 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13395 can_position = true;
6156a456 13396 }
d8106366 13397
061e4b8d
ML		 13398 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13399 &state->dst, &state->clip,
da20eabd
ML		 13400 min_scale, max_scale,
13401 can_position, true,
13402 &state->visible);
14af293f
GP		 13403}
13404
13405static void
13406intel_commit_primary_plane(struct drm_plane *plane,
13407 struct intel_plane_state *state)
13408{
2b875c22
MR		 13409 struct drm_crtc *crtc = state->base.crtc;
13410 struct drm_framebuffer *fb = state->base.fb;
13411 struct drm_device *dev = plane->dev;
14af293f 13412 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13413 struct intel_crtc *intel_crtc;
14af293f
GP		 13414 struct drm_rect *src = &state->src;
13415
ea2c67bb
MR		 13416 crtc = crtc ? crtc : plane->crtc;
13417 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13418
13419 plane->fb = fb;
9dc806fc
MR		 13420 crtc->x = src->x1 >> 16;
13421 crtc->y = src->y1 >> 16;
ccc759dc 13422
a539205a 13423 if (!crtc->state->active)
302d19ac 13424 return;
465c120c 13425
302d19ac
ML		 13426 if (state->visible)
13427 /* FIXME: kill this fastboot hack */
13428 intel_update_pipe_size(intel_crtc);
13429
d4b08630
ML		 13430 dev_priv->display.update_primary_plane(crtc, fb,
13431 state->src.x1 >> 16,
13432 state->src.y1 >> 16);
465c120c
MR		 13433}
13434
a8ad0d8e
ML		 13435static void
13436intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13437 struct drm_crtc *crtc)
a8ad0d8e
ML		 13438{
13439 struct drm_device *dev = plane->dev;
13440 struct drm_i915_private *dev_priv = dev->dev_private;
13441
a8ad0d8e
ML		 13442 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13443}
13444
613d2b27
ML		 13445static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13446 struct drm_crtc_state *old_crtc_state)
3c692a41 13447{
32b7eeec 13448 struct drm_device *dev = crtc->dev;
3c692a41 13449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13450
f015c551 13451 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13452 intel_update_watermarks(crtc);
3c692a41 13453
c34c9ee4 13454 /* Perform vblank evasion around commit operation */
a539205a 13455 if (crtc->state->active)
34e0adbb 13456 intel_pipe_update_start(intel_crtc);
0583236e
ML		 13457
13458 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13459 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13460}
13461
613d2b27
ML		 13462static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13463 struct drm_crtc_state *old_crtc_state)
32b7eeec 13464{
32b7eeec 13465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13466
8f539a83 13467 if (crtc->state->active)
34e0adbb 13468 intel_pipe_update_end(intel_crtc);
3c692a41
GP		 13469}
13470
cf4c7c12 13471/**
4a3b8769
MR		 13472 * intel_plane_destroy - destroy a plane
13473 * @plane: plane to destroy
cf4c7c12 13474 *
4a3b8769
MR		 13475 * Common destruction function for all types of planes (primary, cursor,
13476 * sprite).
cf4c7c12 13477 */
4a3b8769 13478void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13479{
13480 struct intel_plane *intel_plane = to_intel_plane(plane);
13481 drm_plane_cleanup(plane);
13482 kfree(intel_plane);
13483}
13484
65a3fea0 13485const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13486 .update_plane = drm_atomic_helper_update_plane,
13487 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13488 .destroy = intel_plane_destroy,
c196e1d6 13489 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13490 .atomic_get_property = intel_plane_atomic_get_property,
13491 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13492 .atomic_duplicate_state = intel_plane_duplicate_state,
13493 .atomic_destroy_state = intel_plane_destroy_state,
13494
465c120c
MR		 13495};
13496
13497static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13498 int pipe)
13499{
13500 struct intel_plane *primary;
8e7d688b 13501 struct intel_plane_state *state;
465c120c 13502 const uint32_t *intel_primary_formats;
45e3743a 13503 unsigned int num_formats;
465c120c
MR		 13504
13505 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13506 if (primary == NULL)
13507 return NULL;
13508
8e7d688b
MR		 13509 state = intel_create_plane_state(&primary->base);
13510 if (!state) {
ea2c67bb
MR		 13511 kfree(primary);
13512 return NULL;
13513 }
8e7d688b 13514 primary->base.state = &state->base;
ea2c67bb 13515
465c120c
MR		 13516 primary->can_scale = false;
13517 primary->max_downscale = 1;
6156a456
CK		 13518 if (INTEL_INFO(dev)->gen >= 9) {
13519 primary->can_scale = true;
af99ceda 13520 state->scaler_id = -1;
6156a456 13521 }
465c120c
MR		 13522 primary->pipe = pipe;
13523 primary->plane = pipe;
a9ff8714 13524 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13525 primary->check_plane = intel_check_primary_plane;
13526 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13527 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13528 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13529 primary->plane = !pipe;
13530
6c0fd451
DL		 13531 if (INTEL_INFO(dev)->gen >= 9) {
13532 intel_primary_formats = skl_primary_formats;
13533 num_formats = ARRAY_SIZE(skl_primary_formats);
13534 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13535 intel_primary_formats = i965_primary_formats;
13536 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13537 } else {
13538 intel_primary_formats = i8xx_primary_formats;
13539 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13540 }
13541
13542 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13543 &intel_plane_funcs,
465c120c
MR		 13544 intel_primary_formats, num_formats,
13545 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13546
3b7a5119
SJ		 13547 if (INTEL_INFO(dev)->gen >= 4)
13548 intel_create_rotation_property(dev, primary);
48404c1e 13549
ea2c67bb
MR		 13550 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13551
465c120c
MR		 13552 return &primary->base;
13553}
13554
3b7a5119
SJ		 13555void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13556{
13557 if (!dev->mode_config.rotation_property) {
13558 unsigned long flags = BIT(DRM_ROTATE_0) |
13559 BIT(DRM_ROTATE_180);
13560
13561 if (INTEL_INFO(dev)->gen >= 9)
13562 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13563
13564 dev->mode_config.rotation_property =
13565 drm_mode_create_rotation_property(dev, flags);
13566 }
13567 if (dev->mode_config.rotation_property)
13568 drm_object_attach_property(&plane->base.base,
13569 dev->mode_config.rotation_property,
13570 plane->base.state->rotation);
13571}
13572
3d7d6510 13573static int
852e787c 13574intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13575 struct intel_crtc_state *crtc_state,
852e787c 13576 struct intel_plane_state *state)
3d7d6510 13577{
061e4b8d 13578 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13579 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13580 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13581 unsigned stride;
13582 int ret;
3d7d6510 13583
061e4b8d
ML		 13584 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13585 &state->dst, &state->clip,
3d7d6510
MR		 13586 DRM_PLANE_HELPER_NO_SCALING,
13587 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13588 true, true, &state->visible);
757f9a3e
GP		 13589 if (ret)
13590 return ret;
13591
757f9a3e
GP		 13592 /* if we want to turn off the cursor ignore width and height */
13593 if (!obj)
da20eabd 13594 return 0;
757f9a3e 13595
757f9a3e 13596 /* Check for which cursor types we support */
061e4b8d 13597 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13598 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13599 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13600 return -EINVAL;
13601 }
13602
ea2c67bb
MR		 13603 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13604 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13605 DRM_DEBUG_KMS("buffer is too small\n");
13606 return -ENOMEM;
13607 }
13608
3a656b54 13609 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13610 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13611 return -EINVAL;
32b7eeec
MR		 13612 }
13613
da20eabd 13614 return 0;
852e787c 13615}
3d7d6510 13616
a8ad0d8e
ML		 13617static void
13618intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13619 struct drm_crtc *crtc)
a8ad0d8e 13620{
a8ad0d8e
ML		 13621 intel_crtc_update_cursor(crtc, false);
13622}
13623
f4a2cf29 13624static void
852e787c
GP		 13625intel_commit_cursor_plane(struct drm_plane *plane,
13626 struct intel_plane_state *state)
13627{
2b875c22 13628 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13629 struct drm_device *dev = plane->dev;
13630 struct intel_crtc *intel_crtc;
2b875c22 13631 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13632 uint32_t addr;
852e787c 13633
ea2c67bb
MR		 13634 crtc = crtc ? crtc : plane->crtc;
13635 intel_crtc = to_intel_crtc(crtc);
13636
a912f12f
GP		 13637 if (intel_crtc->cursor_bo == obj)
13638 goto update;
4ed91096 13639
f4a2cf29 13640 if (!obj)
a912f12f 13641 addr = 0;
f4a2cf29 13642 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13643 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13644 else
a912f12f 13645 addr = obj->phys_handle->busaddr;
852e787c 13646
a912f12f
GP		 13647 intel_crtc->cursor_addr = addr;
13648 intel_crtc->cursor_bo = obj;
852e787c 13649
302d19ac 13650update:
a539205a 13651 if (crtc->state->active)
a912f12f 13652 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13653}
13654
3d7d6510
MR		 13655static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13656 int pipe)
13657{
13658 struct intel_plane *cursor;
8e7d688b 13659 struct intel_plane_state *state;
3d7d6510
MR		 13660
13661 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13662 if (cursor == NULL)
13663 return NULL;
13664
8e7d688b
MR		 13665 state = intel_create_plane_state(&cursor->base);
13666 if (!state) {
ea2c67bb
MR		 13667 kfree(cursor);
13668 return NULL;
13669 }
8e7d688b 13670 cursor->base.state = &state->base;
ea2c67bb 13671
3d7d6510
MR		 13672 cursor->can_scale = false;
13673 cursor->max_downscale = 1;
13674 cursor->pipe = pipe;
13675 cursor->plane = pipe;
a9ff8714 13676 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13677 cursor->check_plane = intel_check_cursor_plane;
13678 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13679 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13680
13681 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13682 &intel_plane_funcs,
3d7d6510
MR		 13683 intel_cursor_formats,
13684 ARRAY_SIZE(intel_cursor_formats),
13685 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13686
13687 if (INTEL_INFO(dev)->gen >= 4) {
13688 if (!dev->mode_config.rotation_property)
13689 dev->mode_config.rotation_property =
13690 drm_mode_create_rotation_property(dev,
13691 BIT(DRM_ROTATE_0) |
13692 BIT(DRM_ROTATE_180));
13693 if (dev->mode_config.rotation_property)
13694 drm_object_attach_property(&cursor->base.base,
13695 dev->mode_config.rotation_property,
8e7d688b 13696 state->base.rotation);
4398ad45
VS		 13697 }
13698
af99ceda
CK		 13699 if (INTEL_INFO(dev)->gen >=9)
13700 state->scaler_id = -1;
13701
ea2c67bb
MR		 13702 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13703
3d7d6510
MR		 13704 return &cursor->base;
13705}
13706
549e2bfb
CK		 13707static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13708 struct intel_crtc_state *crtc_state)
13709{
13710 int i;
13711 struct intel_scaler *intel_scaler;
13712 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13713
13714 for (i = 0; i < intel_crtc->num_scalers; i++) {
13715 intel_scaler = &scaler_state->scalers[i];
13716 intel_scaler->in_use = 0;
549e2bfb
CK		 13717 intel_scaler->mode = PS_SCALER_MODE_DYN;
13718 }
13719
13720 scaler_state->scaler_id = -1;
13721}
13722
b358d0a6 13723static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13724{
fbee40df 13725 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13726 struct intel_crtc *intel_crtc;
f5de6e07 13727 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13728 struct drm_plane *primary = NULL;
13729 struct drm_plane *cursor = NULL;
465c120c 13730 int i, ret;
79e53945 13731
955382f3 13732 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13733 if (intel_crtc == NULL)
13734 return;
13735
f5de6e07
ACO		 13736 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13737 if (!crtc_state)
13738 goto fail;
550acefd
ACO		 13739 intel_crtc->config = crtc_state;
13740 intel_crtc->base.state = &crtc_state->base;
07878248 13741 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13742
549e2bfb
CK		 13743 /* initialize shared scalers */
13744 if (INTEL_INFO(dev)->gen >= 9) {
13745 if (pipe == PIPE_C)
13746 intel_crtc->num_scalers = 1;
13747 else
13748 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13749
13750 skl_init_scalers(dev, intel_crtc, crtc_state);
13751 }
13752
465c120c 13753 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13754 if (!primary)
13755 goto fail;
13756
13757 cursor = intel_cursor_plane_create(dev, pipe);
13758 if (!cursor)
13759 goto fail;
13760
465c120c 13761 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13762 cursor, &intel_crtc_funcs);
13763 if (ret)
13764 goto fail;
79e53945
JB		 13765
13766 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13767 for (i = 0; i < 256; i++) {
13768 intel_crtc->lut_r[i] = i;
13769 intel_crtc->lut_g[i] = i;
13770 intel_crtc->lut_b[i] = i;
13771 }
13772
1f1c2e24
VS		 13773 /*
13774 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13775 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13776 */
80824003
JB		 13777 intel_crtc->pipe = pipe;
13778 intel_crtc->plane = pipe;
3a77c4c4 13779 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13780 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13781 intel_crtc->plane = !pipe;
80824003
JB		 13782 }
13783
4b0e333e
CW		 13784 intel_crtc->cursor_base = ~0;
13785 intel_crtc->cursor_cntl = ~0;
dc41c154 13786 intel_crtc->cursor_size = ~0;
8d7849db 13787
852eb00d
VS		 13788 intel_crtc->wm.cxsr_allowed = true;
13789
22fd0fab
JB		 13790 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13791 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13792 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13793 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13794
79e53945 13795 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13796
13797 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13798 return;
13799
13800fail:
13801 if (primary)
13802 drm_plane_cleanup(primary);
13803 if (cursor)
13804 drm_plane_cleanup(cursor);
f5de6e07 13805 kfree(crtc_state);
3d7d6510 13806 kfree(intel_crtc);
79e53945
JB		 13807}
13808
752aa88a
JB		 13809enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13810{
13811 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13812 struct drm_device *dev = connector->base.dev;
752aa88a 13813
51fd371b 13814 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13815
d3babd3f 13816 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13817 return INVALID_PIPE;
13818
13819 return to_intel_crtc(encoder->crtc)->pipe;
13820}
13821
08d7b3d1 13822int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13823 struct drm_file *file)
08d7b3d1 13824{
08d7b3d1 13825 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13826 struct drm_crtc *drmmode_crtc;
c05422d5 13827 struct intel_crtc *crtc;
08d7b3d1 13828
7707e653 13829 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13830
7707e653 13831 if (!drmmode_crtc) {
08d7b3d1 13832 DRM_ERROR("no such CRTC id\n");
3f2c2057 13833 return -ENOENT;
08d7b3d1
CW		 13834 }
13835
7707e653 13836 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13837 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13838
c05422d5 13839 return 0;
08d7b3d1
CW		 13840}
13841
66a9278e 13842static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13843{
66a9278e
DV		 13844 struct drm_device *dev = encoder->base.dev;
13845 struct intel_encoder *source_encoder;
79e53945 13846 int index_mask = 0;
79e53945
JB		 13847 int entry = 0;
13848
b2784e15 13849 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13850 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13851 index_mask |= (1 << entry);
13852
79e53945
JB		 13853 entry++;
13854 }
4ef69c7a 13855
79e53945
JB		 13856 return index_mask;
13857}
13858
4d302442
CW		 13859static bool has_edp_a(struct drm_device *dev)
13860{
13861 struct drm_i915_private *dev_priv = dev->dev_private;
13862
13863 if (!IS_MOBILE(dev))
13864 return false;
13865
13866 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13867 return false;
13868
e3589908 13869 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13870 return false;
13871
13872 return true;
13873}
13874
84b4e042
JB		 13875static bool intel_crt_present(struct drm_device *dev)
13876{
13877 struct drm_i915_private *dev_priv = dev->dev_private;
13878
884497ed
DL		 13879 if (INTEL_INFO(dev)->gen >= 9)
13880 return false;
13881
cf404ce4 13882 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13883 return false;
13884
13885 if (IS_CHERRYVIEW(dev))
13886 return false;
13887
13888 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13889 return false;
13890
13891 return true;
13892}
13893
79e53945
JB		 13894static void intel_setup_outputs(struct drm_device *dev)
13895{
725e30ad 13896 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13897 struct intel_encoder *encoder;
cb0953d7 13898 bool dpd_is_edp = false;
79e53945 13899
c9093354 13900 intel_lvds_init(dev);
79e53945 13901
84b4e042 13902 if (intel_crt_present(dev))
79935fca 13903 intel_crt_init(dev);
cb0953d7 13904
c776eb2e
VK		 13905 if (IS_BROXTON(dev)) {
13906 /*
13907 * FIXME: Broxton doesn't support port detection via the
13908 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13909 * detect the ports.
13910 */
13911 intel_ddi_init(dev, PORT_A);
13912 intel_ddi_init(dev, PORT_B);
13913 intel_ddi_init(dev, PORT_C);
13914 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13915 int found;
13916
de31facd
JB		 13917 /*
13918 * Haswell uses DDI functions to detect digital outputs.
13919 * On SKL pre-D0 the strap isn't connected, so we assume
13920 * it's there.
13921 */
0e72a5b5 13922 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd 13923 /* WaIgnoreDDIAStrap: skl */
5a2376d1 13924 if (found || IS_SKYLAKE(dev))
0e72a5b5
ED		 13925 intel_ddi_init(dev, PORT_A);
13926
13927 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13928 * register */
13929 found = I915_READ(SFUSE_STRAP);
13930
13931 if (found & SFUSE_STRAP_DDIB_DETECTED)
13932 intel_ddi_init(dev, PORT_B);
13933 if (found & SFUSE_STRAP_DDIC_DETECTED)
13934 intel_ddi_init(dev, PORT_C);
13935 if (found & SFUSE_STRAP_DDID_DETECTED)
13936 intel_ddi_init(dev, PORT_D);
2800e4c2
RV		 13937 /*
13938 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
13939 */
13940 if (IS_SKYLAKE(dev) &&
13941 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
13942 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
13943 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
13944 intel_ddi_init(dev, PORT_E);
13945
0e72a5b5 13946 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13947 int found;
5d8a7752 13948 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13949
13950 if (has_edp_a(dev))
13951 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13952
dc0fa718 13953 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13954 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13955 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13956 if (!found)
e2debe91 13957 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13958 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13959 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13960 }
13961
dc0fa718 13962 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13963 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13964
dc0fa718 13965 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13966 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13967
5eb08b69 13968 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13969 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13970
270b3042 13971 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13972 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13973 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13974 /*
13975 * The DP_DETECTED bit is the latched state of the DDC
13976 * SDA pin at boot. However since eDP doesn't require DDC
13977 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13978 * eDP ports may have been muxed to an alternate function.
13979 * Thus we can't rely on the DP_DETECTED bit alone to detect
13980 * eDP ports. Consult the VBT as well as DP_DETECTED to
13981 * detect eDP ports.
13982 */
d2182a66
VS		 13983 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13984 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13985 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13986 PORT_B);
e17ac6db
VS		 13987 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13988 intel_dp_is_edp(dev, PORT_B))
13989 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13990
d2182a66
VS		 13991 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13992 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13993 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13994 PORT_C);
e17ac6db
VS		 13995 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13996 intel_dp_is_edp(dev, PORT_C))
13997 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13998
9418c1f1 13999 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14000 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14001 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14002 PORT_D);
e17ac6db
VS		 14003 /* eDP not supported on port D, so don't check VBT */
14004 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14005 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14006 }
14007
3cfca973 14008 intel_dsi_init(dev);
09da55dc 14009 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14010 bool found = false;
7d57382e 14011
e2debe91 14012 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14013 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14014 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14015 if (!found && IS_G4X(dev)) {
b01f2c3a 14016 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14017 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14018 }
27185ae1 14019
3fec3d2f 14020 if (!found && IS_G4X(dev))
ab9d7c30 14021 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14022 }
13520b05
KH		 14023
14024 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14025
e2debe91 14026 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14027 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14028 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14029 }
27185ae1 14030
e2debe91 14031 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14032
3fec3d2f 14033 if (IS_G4X(dev)) {
b01f2c3a 14034 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14035 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14036 }
3fec3d2f 14037 if (IS_G4X(dev))
ab9d7c30 14038 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14039 }
27185ae1 14040
3fec3d2f 14041 if (IS_G4X(dev) &&
e7281eab 14042 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14043 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14044 } else if (IS_GEN2(dev))
79e53945
JB		 14045 intel_dvo_init(dev);
14046
103a196f 14047 if (SUPPORTS_TV(dev))
79e53945
JB		 14048 intel_tv_init(dev);
14049
0bc12bcb 14050 intel_psr_init(dev);
7c8f8a70 14051
b2784e15 14052 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14053 encoder->base.possible_crtcs = encoder->crtc_mask;
14054 encoder->base.possible_clones =
66a9278e 14055 intel_encoder_clones(encoder);
79e53945 14056 }
47356eb6 14057
dde86e2d 14058 intel_init_pch_refclk(dev);
270b3042
DV		 14059
14060 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14061}
14062
14063static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14064{
60a5ca01 14065 struct drm_device *dev = fb->dev;
79e53945 14066 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14067
ef2d633e 14068 drm_framebuffer_cleanup(fb);
60a5ca01 14069 mutex_lock(&dev->struct_mutex);
ef2d633e 14070 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14071 drm_gem_object_unreference(&intel_fb->obj->base);
14072 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14073 kfree(intel_fb);
14074}
14075
14076static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14077 struct drm_file *file,
79e53945
JB		 14078 unsigned int *handle)
14079{
14080 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14081 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14082
05394f39 14083 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14084}
14085
86c98588
RV		 14086static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14087 struct drm_file *file,
14088 unsigned flags, unsigned color,
14089 struct drm_clip_rect *clips,
14090 unsigned num_clips)
14091{
14092 struct drm_device *dev = fb->dev;
14093 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14094 struct drm_i915_gem_object *obj = intel_fb->obj;
14095
14096 mutex_lock(&dev->struct_mutex);
74b4ea1e 14097 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
86c98588
RV		 14098 mutex_unlock(&dev->struct_mutex);
14099
14100 return 0;
14101}
14102
79e53945
JB		 14103static const struct drm_framebuffer_funcs intel_fb_funcs = {
14104 .destroy = intel_user_framebuffer_destroy,
14105 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14106 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14107};
14108
b321803d
DL		 14109static
14110u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14111 uint32_t pixel_format)
14112{
14113 u32 gen = INTEL_INFO(dev)->gen;
14114
14115 if (gen >= 9) {
14116 /* "The stride in bytes must not exceed the of the size of 8K
14117 * pixels and 32K bytes."
14118 */
14119 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14120 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14121 return 32*1024;
14122 } else if (gen >= 4) {
14123 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14124 return 16*1024;
14125 else
14126 return 32*1024;
14127 } else if (gen >= 3) {
14128 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14129 return 8*1024;
14130 else
14131 return 16*1024;
14132 } else {
14133 /* XXX DSPC is limited to 4k tiled */
14134 return 8*1024;
14135 }
14136}
14137
b5ea642a
DV		 14138static int intel_framebuffer_init(struct drm_device *dev,
14139 struct intel_framebuffer *intel_fb,
14140 struct drm_mode_fb_cmd2 *mode_cmd,
14141 struct drm_i915_gem_object *obj)
79e53945 14142{
6761dd31 14143 unsigned int aligned_height;
79e53945 14144 int ret;
b321803d 14145 u32 pitch_limit, stride_alignment;
79e53945 14146
dd4916c5
DV		 14147 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14148
2a80eada
DV		 14149 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14150 /* Enforce that fb modifier and tiling mode match, but only for
14151 * X-tiled. This is needed for FBC. */
14152 if (!!(obj->tiling_mode == I915_TILING_X) !=
14153 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14154 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14155 return -EINVAL;
14156 }
14157 } else {
14158 if (obj->tiling_mode == I915_TILING_X)
14159 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14160 else if (obj->tiling_mode == I915_TILING_Y) {
14161 DRM_DEBUG("No Y tiling for legacy addfb\n");
14162 return -EINVAL;
14163 }
14164 }
14165
9a8f0a12
TU		 14166 /* Passed in modifier sanity checking. */
14167 switch (mode_cmd->modifier[0]) {
14168 case I915_FORMAT_MOD_Y_TILED:
14169 case I915_FORMAT_MOD_Yf_TILED:
14170 if (INTEL_INFO(dev)->gen < 9) {
14171 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14172 mode_cmd->modifier[0]);
14173 return -EINVAL;
14174 }
14175 case DRM_FORMAT_MOD_NONE:
14176 case I915_FORMAT_MOD_X_TILED:
14177 break;
14178 default:
c0f40428
JB		 14179 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14180 mode_cmd->modifier[0]);
57cd6508 14181 return -EINVAL;
c16ed4be 14182 }
57cd6508 14183
b321803d
DL		 14184 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14185 mode_cmd->pixel_format);
14186 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14187 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14188 mode_cmd->pitches[0], stride_alignment);
57cd6508 14189 return -EINVAL;
c16ed4be 14190 }
57cd6508 14191
b321803d
DL		 14192 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14193 mode_cmd->pixel_format);
a35cdaa0 14194 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14195 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14196 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14197 "tiled" : "linear",
a35cdaa0 14198 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14199 return -EINVAL;
c16ed4be 14200 }
5d7bd705 14201
2a80eada 14202 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14203 mode_cmd->pitches[0] != obj->stride) {
14204 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14205 mode_cmd->pitches[0], obj->stride);
5d7bd705 14206 return -EINVAL;
c16ed4be 14207 }
5d7bd705 14208
57779d06 14209 /* Reject formats not supported by any plane early. */
308e5bcb 14210 switch (mode_cmd->pixel_format) {
57779d06 14211 case DRM_FORMAT_C8:
04b3924d
VS		 14212 case DRM_FORMAT_RGB565:
14213 case DRM_FORMAT_XRGB8888:
14214 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14215 break;
14216 case DRM_FORMAT_XRGB1555:
c16ed4be 14217 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14218 DRM_DEBUG("unsupported pixel format: %s\n",
14219 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14220 return -EINVAL;
c16ed4be 14221 }
57779d06 14222 break;
57779d06 14223 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14224 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14225 DRM_DEBUG("unsupported pixel format: %s\n",
14226 drm_get_format_name(mode_cmd->pixel_format));
14227 return -EINVAL;
14228 }
14229 break;
14230 case DRM_FORMAT_XBGR8888:
04b3924d 14231 case DRM_FORMAT_XRGB2101010:
57779d06 14232 case DRM_FORMAT_XBGR2101010:
c16ed4be 14233 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14234 DRM_DEBUG("unsupported pixel format: %s\n",
14235 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14236 return -EINVAL;
c16ed4be 14237 }
b5626747 14238 break;
7531208b
DL		 14239 case DRM_FORMAT_ABGR2101010:
14240 if (!IS_VALLEYVIEW(dev)) {
14241 DRM_DEBUG("unsupported pixel format: %s\n",
14242 drm_get_format_name(mode_cmd->pixel_format));
14243 return -EINVAL;
14244 }
14245 break;
04b3924d
VS		 14246 case DRM_FORMAT_YUYV:
14247 case DRM_FORMAT_UYVY:
14248 case DRM_FORMAT_YVYU:
14249 case DRM_FORMAT_VYUY:
c16ed4be 14250 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14251 DRM_DEBUG("unsupported pixel format: %s\n",
14252 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14253 return -EINVAL;
c16ed4be 14254 }
57cd6508
CW		 14255 break;
14256 default:
4ee62c76
VS		 14257 DRM_DEBUG("unsupported pixel format: %s\n",
14258 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14259 return -EINVAL;
14260 }
14261
90f9a336
VS		 14262 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14263 if (mode_cmd->offsets[0] != 0)
14264 return -EINVAL;
14265
ec2c981e 14266 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14267 mode_cmd->pixel_format,
14268 mode_cmd->modifier[0]);
53155c0a
DV		 14269 /* FIXME drm helper for size checks (especially planar formats)? */
14270 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14271 return -EINVAL;
14272
c7d73f6a
DV		 14273 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14274 intel_fb->obj = obj;
80075d49 14275 intel_fb->obj->framebuffer_references++;
c7d73f6a 14276
79e53945
JB		 14277 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14278 if (ret) {
14279 DRM_ERROR("framebuffer init failed %d\n", ret);
14280 return ret;
14281 }
14282
79e53945
JB		 14283 return 0;
14284}
14285
79e53945
JB		 14286static struct drm_framebuffer *
14287intel_user_framebuffer_create(struct drm_device *dev,
14288 struct drm_file *filp,
308e5bcb 14289 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14290{
05394f39 14291 struct drm_i915_gem_object *obj;
79e53945 14292
308e5bcb
JB		 14293 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14294 mode_cmd->handles[0]));
c8725226 14295 if (&obj->base == NULL)
cce13ff7 14296 return ERR_PTR(-ENOENT);
79e53945 14297
d2dff872 14298 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14299}
14300
0695726e 14301#ifndef CONFIG_DRM_FBDEV_EMULATION
0632fef6 14302static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14303{
14304}
14305#endif
14306
79e53945 14307static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14308 .fb_create = intel_user_framebuffer_create,
0632fef6 14309 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14310 .atomic_check = intel_atomic_check,
14311 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14312 .atomic_state_alloc = intel_atomic_state_alloc,
14313 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14314};
14315
e70236a8
JB		 14316/* Set up chip specific display functions */
14317static void intel_init_display(struct drm_device *dev)
14318{
14319 struct drm_i915_private *dev_priv = dev->dev_private;
14320
ee9300bb
DV		 14321 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14322 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14323 else if (IS_CHERRYVIEW(dev))
14324 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14325 else if (IS_VALLEYVIEW(dev))
14326 dev_priv->display.find_dpll = vlv_find_best_dpll;
14327 else if (IS_PINEVIEW(dev))
14328 dev_priv->display.find_dpll = pnv_find_best_dpll;
14329 else
14330 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14331
bc8d7dff
DL		 14332 if (INTEL_INFO(dev)->gen >= 9) {
14333 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14334 dev_priv->display.get_initial_plane_config =
14335 skylake_get_initial_plane_config;
bc8d7dff
DL		 14336 dev_priv->display.crtc_compute_clock =
14337 haswell_crtc_compute_clock;
14338 dev_priv->display.crtc_enable = haswell_crtc_enable;
14339 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14340 dev_priv->display.update_primary_plane =
14341 skylake_update_primary_plane;
14342 } else if (HAS_DDI(dev)) {
0e8ffe1b 14343 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14344 dev_priv->display.get_initial_plane_config =
14345 ironlake_get_initial_plane_config;
797d0259
ACO		 14346 dev_priv->display.crtc_compute_clock =
14347 haswell_crtc_compute_clock;
4f771f10
PZ		 14348 dev_priv->display.crtc_enable = haswell_crtc_enable;
14349 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14350 dev_priv->display.update_primary_plane =
14351 ironlake_update_primary_plane;
09b4ddf9 14352 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14353 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14354 dev_priv->display.get_initial_plane_config =
14355 ironlake_get_initial_plane_config;
3fb37703
ACO		 14356 dev_priv->display.crtc_compute_clock =
14357 ironlake_crtc_compute_clock;
76e5a89c
DV		 14358 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14359 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14360 dev_priv->display.update_primary_plane =
14361 ironlake_update_primary_plane;
89b667f8
JB		 14362 } else if (IS_VALLEYVIEW(dev)) {
14363 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14364 dev_priv->display.get_initial_plane_config =
14365 i9xx_get_initial_plane_config;
d6dfee7a 14366 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14367 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14368 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14369 dev_priv->display.update_primary_plane =
14370 i9xx_update_primary_plane;
f564048e 14371 } else {
0e8ffe1b 14372 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14373 dev_priv->display.get_initial_plane_config =
14374 i9xx_get_initial_plane_config;
d6dfee7a 14375 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14376 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14377 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14378 dev_priv->display.update_primary_plane =
14379 i9xx_update_primary_plane;
f564048e 14380 }
e70236a8 14381
e70236a8 14382 /* Returns the core display clock speed */
1652d19e
VS		 14383 if (IS_SKYLAKE(dev))
14384 dev_priv->display.get_display_clock_speed =
14385 skylake_get_display_clock_speed;
acd3f3d3
BP		 14386 else if (IS_BROXTON(dev))
14387 dev_priv->display.get_display_clock_speed =
14388 broxton_get_display_clock_speed;
1652d19e
VS		 14389 else if (IS_BROADWELL(dev))
14390 dev_priv->display.get_display_clock_speed =
14391 broadwell_get_display_clock_speed;
14392 else if (IS_HASWELL(dev))
14393 dev_priv->display.get_display_clock_speed =
14394 haswell_get_display_clock_speed;
14395 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14396 dev_priv->display.get_display_clock_speed =
14397 valleyview_get_display_clock_speed;
b37a6434
VS		 14398 else if (IS_GEN5(dev))
14399 dev_priv->display.get_display_clock_speed =
14400 ilk_get_display_clock_speed;
a7c66cd8 14401 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14402 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14403 dev_priv->display.get_display_clock_speed =
14404 i945_get_display_clock_speed;
34edce2f
VS		 14405 else if (IS_GM45(dev))
14406 dev_priv->display.get_display_clock_speed =
14407 gm45_get_display_clock_speed;
14408 else if (IS_CRESTLINE(dev))
14409 dev_priv->display.get_display_clock_speed =
14410 i965gm_get_display_clock_speed;
14411 else if (IS_PINEVIEW(dev))
14412 dev_priv->display.get_display_clock_speed =
14413 pnv_get_display_clock_speed;
14414 else if (IS_G33(dev) || IS_G4X(dev))
14415 dev_priv->display.get_display_clock_speed =
14416 g33_get_display_clock_speed;
e70236a8
JB		 14417 else if (IS_I915G(dev))
14418 dev_priv->display.get_display_clock_speed =
14419 i915_get_display_clock_speed;
257a7ffc 14420 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14421 dev_priv->display.get_display_clock_speed =
14422 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14423 else if (IS_PINEVIEW(dev))
14424 dev_priv->display.get_display_clock_speed =
14425 pnv_get_display_clock_speed;
e70236a8
JB		 14426 else if (IS_I915GM(dev))
14427 dev_priv->display.get_display_clock_speed =
14428 i915gm_get_display_clock_speed;
14429 else if (IS_I865G(dev))
14430 dev_priv->display.get_display_clock_speed =
14431 i865_get_display_clock_speed;
f0f8a9ce 14432 else if (IS_I85X(dev))
e70236a8 14433 dev_priv->display.get_display_clock_speed =
1b1d2716 14434 i85x_get_display_clock_speed;
623e01e5
VS		 14435 else { /* 830 */
14436 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14437 dev_priv->display.get_display_clock_speed =
14438 i830_get_display_clock_speed;
623e01e5 14439 }
e70236a8 14440
7c10a2b5 14441 if (IS_GEN5(dev)) {
3bb11b53 14442 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14443 } else if (IS_GEN6(dev)) {
14444 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14445 } else if (IS_IVYBRIDGE(dev)) {
14446 /* FIXME: detect B0+ stepping and use auto training */
14447 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14448 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14449 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14450 if (IS_BROADWELL(dev)) {
14451 dev_priv->display.modeset_commit_cdclk =
14452 broadwell_modeset_commit_cdclk;
14453 dev_priv->display.modeset_calc_cdclk =
14454 broadwell_modeset_calc_cdclk;
14455 }
30a970c6 14456 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14457 dev_priv->display.modeset_commit_cdclk =
14458 valleyview_modeset_commit_cdclk;
14459 dev_priv->display.modeset_calc_cdclk =
14460 valleyview_modeset_calc_cdclk;
f8437dd1 14461 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14462 dev_priv->display.modeset_commit_cdclk =
14463 broxton_modeset_commit_cdclk;
14464 dev_priv->display.modeset_calc_cdclk =
14465 broxton_modeset_calc_cdclk;
e70236a8 14466 }
8c9f3aaf 14467
8c9f3aaf
JB		 14468 switch (INTEL_INFO(dev)->gen) {
14469 case 2:
14470 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14471 break;
14472
14473 case 3:
14474 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14475 break;
14476
14477 case 4:
14478 case 5:
14479 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14480 break;
14481
14482 case 6:
14483 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14484 break;
7c9017e5 14485 case 7:
4e0bbc31 14486 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14487 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14488 break;
830c81db 14489 case 9:
ba343e02
TU		 14490 /* Drop through - unsupported since execlist only. */
14491 default:
14492 /* Default just returns -ENODEV to indicate unsupported */
14493 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14494 }
7bd688cd
JN		 14495
14496 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14497
14498 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14499}
14500
b690e96c
JB		 14501/*
14502 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14503 * resume, or other times. This quirk makes sure that's the case for
14504 * affected systems.
14505 */
0206e353 14506static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14507{
14508 struct drm_i915_private *dev_priv = dev->dev_private;
14509
14510 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14511 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14512}
14513
b6b5d049
VS		 14514static void quirk_pipeb_force(struct drm_device *dev)
14515{
14516 struct drm_i915_private *dev_priv = dev->dev_private;
14517
14518 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14519 DRM_INFO("applying pipe b force quirk\n");
14520}
14521
435793df
KP		 14522/*
14523 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14524 */
14525static void quirk_ssc_force_disable(struct drm_device *dev)
14526{
14527 struct drm_i915_private *dev_priv = dev->dev_private;
14528 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14529 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14530}
14531
4dca20ef 14532/*
5a15ab5b
CE		 14533 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14534 * brightness value
4dca20ef
CE		 14535 */
14536static void quirk_invert_brightness(struct drm_device *dev)
14537{
14538 struct drm_i915_private *dev_priv = dev->dev_private;
14539 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14540 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14541}
14542
9c72cc6f
SD		 14543/* Some VBT's incorrectly indicate no backlight is present */
14544static void quirk_backlight_present(struct drm_device *dev)
14545{
14546 struct drm_i915_private *dev_priv = dev->dev_private;
14547 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14548 DRM_INFO("applying backlight present quirk\n");
14549}
14550
b690e96c
JB		 14551struct intel_quirk {
14552 int device;
14553 int subsystem_vendor;
14554 int subsystem_device;
14555 void (*hook)(struct drm_device *dev);
14556};
14557
5f85f176
EE		 14558/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14559struct intel_dmi_quirk {
14560 void (*hook)(struct drm_device *dev);
14561 const struct dmi_system_id (*dmi_id_list)[];
14562};
14563
14564static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14565{
14566 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14567 return 1;
14568}
14569
14570static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14571 {
14572 .dmi_id_list = &(const struct dmi_system_id[]) {
14573 {
14574 .callback = intel_dmi_reverse_brightness,
14575 .ident = "NCR Corporation",
14576 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14577 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14578 },
14579 },
14580 { } /* terminating entry */
14581 },
14582 .hook = quirk_invert_brightness,
14583 },
14584};
14585
c43b5634 14586static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14587 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14588 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14589
b690e96c
JB		 14590 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14591 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14592
5f080c0f
VS		 14593 /* 830 needs to leave pipe A & dpll A up */
14594 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14595
b6b5d049
VS		 14596 /* 830 needs to leave pipe B & dpll B up */
14597 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14598
435793df
KP		 14599 /* Lenovo U160 cannot use SSC on LVDS */
14600 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14601
14602 /* Sony Vaio Y cannot use SSC on LVDS */
14603 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14604
be505f64
AH		 14605 /* Acer Aspire 5734Z must invert backlight brightness */
14606 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14607
14608 /* Acer/eMachines G725 */
14609 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14610
14611 /* Acer/eMachines e725 */
14612 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14613
14614 /* Acer/Packard Bell NCL20 */
14615 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14616
14617 /* Acer Aspire 4736Z */
14618 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14619
14620 /* Acer Aspire 5336 */
14621 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14622
14623 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14624 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14625
dfb3d47b
SD		 14626 /* Acer C720 Chromebook (Core i3 4005U) */
14627 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14628
b2a9601c 14629 /* Apple Macbook 2,1 (Core 2 T7400) */
14630 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14631
d4967d8c
SD		 14632 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14633 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14634
14635 /* HP Chromebook 14 (Celeron 2955U) */
14636 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14637
14638 /* Dell Chromebook 11 */
14639 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14640};
14641
14642static void intel_init_quirks(struct drm_device *dev)
14643{
14644 struct pci_dev *d = dev->pdev;
14645 int i;
14646
14647 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14648 struct intel_quirk *q = &intel_quirks[i];
14649
14650 if (d->device == q->device &&
14651 (d->subsystem_vendor == q->subsystem_vendor ||
14652 q->subsystem_vendor == PCI_ANY_ID) &&
14653 (d->subsystem_device == q->subsystem_device ||
14654 q->subsystem_device == PCI_ANY_ID))
14655 q->hook(dev);
14656 }
5f85f176
EE		 14657 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14658 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14659 intel_dmi_quirks[i].hook(dev);
14660 }
b690e96c
JB		 14661}
14662
9cce37f4
JB		 14663/* Disable the VGA plane that we never use */
14664static void i915_disable_vga(struct drm_device *dev)
14665{
14666 struct drm_i915_private *dev_priv = dev->dev_private;
14667 u8 sr1;
766aa1c4 14668 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14669
2b37c616 14670 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14671 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14672 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14673 sr1 = inb(VGA_SR_DATA);
14674 outb(sr1 | 1<<5, VGA_SR_DATA);
14675 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14676 udelay(300);
14677
01f5a626 14678 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14679 POSTING_READ(vga_reg);
14680}
14681
f817586c
DV		 14682void intel_modeset_init_hw(struct drm_device *dev)
14683{
b6283055 14684 intel_update_cdclk(dev);
a8f78b58 14685 intel_prepare_ddi(dev);
f817586c 14686 intel_init_clock_gating(dev);
8090c6b9 14687 intel_enable_gt_powersave(dev);
f817586c
DV		 14688}
14689
79e53945
JB		 14690void intel_modeset_init(struct drm_device *dev)
14691{
652c393a 14692 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14693 int sprite, ret;
8cc87b75 14694 enum pipe pipe;
46f297fb 14695 struct intel_crtc *crtc;
79e53945
JB		 14696
14697 drm_mode_config_init(dev);
14698
14699 dev->mode_config.min_width = 0;
14700 dev->mode_config.min_height = 0;
14701
019d96cb
DA		 14702 dev->mode_config.preferred_depth = 24;
14703 dev->mode_config.prefer_shadow = 1;
14704
25bab385
TU		 14705 dev->mode_config.allow_fb_modifiers = true;
14706
e6ecefaa 14707 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14708
b690e96c
JB		 14709 intel_init_quirks(dev);
14710
1fa61106
ED		 14711 intel_init_pm(dev);
14712
e3c74757
BW		 14713 if (INTEL_INFO(dev)->num_pipes == 0)
14714 return;
14715
69f92f67
LW		 14716 /*
14717 * There may be no VBT; and if the BIOS enabled SSC we can
14718 * just keep using it to avoid unnecessary flicker. Whereas if the
14719 * BIOS isn't using it, don't assume it will work even if the VBT
14720 * indicates as much.
14721 */
14722 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
14723 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14724 DREF_SSC1_ENABLE);
14725
14726 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14727 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14728 bios_lvds_use_ssc ? "en" : "dis",
14729 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14730 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14731 }
14732 }
14733
e70236a8 14734 intel_init_display(dev);
7c10a2b5 14735 intel_init_audio(dev);
e70236a8 14736
a6c45cf0
CW		 14737 if (IS_GEN2(dev)) {
14738 dev->mode_config.max_width = 2048;
14739 dev->mode_config.max_height = 2048;
14740 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14741 dev->mode_config.max_width = 4096;
14742 dev->mode_config.max_height = 4096;
79e53945 14743 } else {
a6c45cf0
CW		 14744 dev->mode_config.max_width = 8192;
14745 dev->mode_config.max_height = 8192;
79e53945 14746 }
068be561 14747
dc41c154
VS		 14748 if (IS_845G(dev) || IS_I865G(dev)) {
14749 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14750 dev->mode_config.cursor_height = 1023;
14751 } else if (IS_GEN2(dev)) {
068be561
DL		 14752 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14753 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14754 } else {
14755 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14756 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14757 }
14758
5d4545ae 14759 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14760
28c97730 14761 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14762 INTEL_INFO(dev)->num_pipes,
14763 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14764
055e393f 14765 for_each_pipe(dev_priv, pipe) {
8cc87b75 14766 intel_crtc_init(dev, pipe);
3bdcfc0c 14767 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14768 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14769 if (ret)
06da8da2 14770 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14771 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14772 }
79e53945
JB		 14773 }
14774
e72f9fbf 14775 intel_shared_dpll_init(dev);
ee7b9f93 14776
9cce37f4
JB		 14777 /* Just disable it once at startup */
14778 i915_disable_vga(dev);
79e53945 14779 intel_setup_outputs(dev);
11be49eb
CW		 14780
14781 /* Just in case the BIOS is doing something questionable. */
7733b49b 14782 intel_fbc_disable(dev_priv);
fa9fa083 14783
6e9f798d 14784 drm_modeset_lock_all(dev);
043e9bda 14785 intel_modeset_setup_hw_state(dev);
6e9f798d 14786 drm_modeset_unlock_all(dev);
46f297fb 14787
d3fcc808 14788 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14789 struct intel_initial_plane_config plane_config = {};
14790
46f297fb
JB		 14791 if (!crtc->active)
14792 continue;
14793
46f297fb 14794 /*
46f297fb
JB		 14795 * Note that reserving the BIOS fb up front prevents us
14796 * from stuffing other stolen allocations like the ring
14797 * on top. This prevents some ugliness at boot time, and
14798 * can even allow for smooth boot transitions if the BIOS
14799 * fb is large enough for the active pipe configuration.
14800 */
eeebeac5
ML		 14801 dev_priv->display.get_initial_plane_config(crtc,
14802 &plane_config);
14803
14804 /*
14805 * If the fb is shared between multiple heads, we'll
14806 * just get the first one.
14807 */
14808 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14809 }
2c7111db
CW		 14810}
14811
7fad798e
DV		 14812static void intel_enable_pipe_a(struct drm_device *dev)
14813{
14814 struct intel_connector *connector;
14815 struct drm_connector *crt = NULL;
14816 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14817 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14818
14819 /* We can't just switch on the pipe A, we need to set things up with a
14820 * proper mode and output configuration. As a gross hack, enable pipe A
14821 * by enabling the load detect pipe once. */
3a3371ff 14822 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14823 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14824 crt = &connector->base;
14825 break;
14826 }
14827 }
14828
14829 if (!crt)
14830 return;
14831
208bf9fd 14832 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14833 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14834}
14835
fa555837
DV		 14836static bool
14837intel_check_plane_mapping(struct intel_crtc *crtc)
14838{
7eb552ae
BW		 14839 struct drm_device *dev = crtc->base.dev;
14840 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14841 u32 reg, val;
14842
7eb552ae 14843 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14844 return true;
14845
14846 reg = DSPCNTR(!crtc->plane);
14847 val = I915_READ(reg);
14848
14849 if ((val & DISPLAY_PLANE_ENABLE) &&
14850 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14851 return false;
14852
14853 return true;
14854}
14855
02e93c35
VS		 14856static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
14857{
14858 struct drm_device *dev = crtc->base.dev;
14859 struct intel_encoder *encoder;
14860
14861 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
14862 return true;
14863
14864 return false;
14865}
14866
24929352
DV		 14867static void intel_sanitize_crtc(struct intel_crtc *crtc)
14868{
14869 struct drm_device *dev = crtc->base.dev;
14870 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14871 u32 reg;
24929352 14872
24929352 14873 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14874 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14875 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14876
d3eaf884 14877 /* restore vblank interrupts to correct state */
9625604c 14878 drm_crtc_vblank_reset(&crtc->base);
d297e103 14879 if (crtc->active) {
3a03dfb0 14880 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 14881 update_scanline_offset(crtc);
9625604c
DV		 14882 drm_crtc_vblank_on(&crtc->base);
14883 }
d3eaf884 14884
24929352 14885 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14886 * disable the crtc (and hence change the state) if it is wrong. Note
14887 * that gen4+ has a fixed plane -> pipe mapping. */
14888 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14889 bool plane;
14890
24929352
DV		 14891 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14892 crtc->base.base.id);
14893
14894 /* Pipe has the wrong plane attached and the plane is active.
14895 * Temporarily change the plane mapping and disable everything
14896 * ... */
14897 plane = crtc->plane;
b70709a6 14898 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14899 crtc->plane = !plane;
b17d48e2 14900 intel_crtc_disable_noatomic(&crtc->base);
24929352 14901 crtc->plane = plane;
24929352 14902 }
24929352 14903
7fad798e
DV		 14904 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14905 crtc->pipe == PIPE_A && !crtc->active) {
14906 /* BIOS forgot to enable pipe A, this mostly happens after
14907 * resume. Force-enable the pipe to fix this, the update_dpms
14908 * call below we restore the pipe to the right state, but leave
14909 * the required bits on. */
14910 intel_enable_pipe_a(dev);
14911 }
14912
24929352
DV		 14913 /* Adjust the state of the output pipe according to whether we
14914 * have active connectors/encoders. */
02e93c35 14915 if (!intel_crtc_has_encoders(crtc))
b17d48e2 14916 intel_crtc_disable_noatomic(&crtc->base);
24929352 14917
53d9f4e9 14918 if (crtc->active != crtc->base.state->active) {
02e93c35 14919 struct intel_encoder *encoder;
24929352
DV		 14920
14921 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 14922 * functions or because of calls to intel_crtc_disable_noatomic,
14923 * or because the pipe is force-enabled due to the
24929352
DV		 14924 * pipe A quirk. */
14925 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14926 crtc->base.base.id,
83d65738 14927 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14928 crtc->active ? "enabled" : "disabled");
14929
4be40c98 14930 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 14931 crtc->base.state->active = crtc->active;
24929352
DV		 14932 crtc->base.enabled = crtc->active;
14933
14934 /* Because we only establish the connector -> encoder ->
14935 * crtc links if something is active, this means the
14936 * crtc is now deactivated. Break the links. connector
14937 * -> encoder links are only establish when things are
14938 * actually up, hence no need to break them. */
14939 WARN_ON(crtc->active);
14940
2d406bb0 14941 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
24929352 14942 encoder->base.crtc = NULL;
24929352 14943 }
c5ab3bc0 14944
a3ed6aad 14945 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14946 /*
14947 * We start out with underrun reporting disabled to avoid races.
14948 * For correct bookkeeping mark this on active crtcs.
14949 *
c5ab3bc0
DV		 14950 * Also on gmch platforms we dont have any hardware bits to
14951 * disable the underrun reporting. Which means we need to start
14952 * out with underrun reporting disabled also on inactive pipes,
14953 * since otherwise we'll complain about the garbage we read when
14954 * e.g. coming up after runtime pm.
14955 *
4cc31489
DV		 14956 * No protection against concurrent access is required - at
14957 * worst a fifo underrun happens which also sets this to false.
14958 */
14959 crtc->cpu_fifo_underrun_disabled = true;
14960 crtc->pch_fifo_underrun_disabled = true;
14961 }
24929352
DV		 14962}
14963
14964static void intel_sanitize_encoder(struct intel_encoder *encoder)
14965{
14966 struct intel_connector *connector;
14967 struct drm_device *dev = encoder->base.dev;
873ffe69 14968 bool active = false;
24929352
DV		 14969
14970 /* We need to check both for a crtc link (meaning that the
14971 * encoder is active and trying to read from a pipe) and the
14972 * pipe itself being active. */
14973 bool has_active_crtc = encoder->base.crtc &&
14974 to_intel_crtc(encoder->base.crtc)->active;
14975
873ffe69
ML		 14976 for_each_intel_connector(dev, connector) {
14977 if (connector->base.encoder != &encoder->base)
14978 continue;
14979
14980 active = true;
14981 break;
14982 }
14983
14984 if (active && !has_active_crtc) {
24929352
DV		 14985 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14986 encoder->base.base.id,
8e329a03 14987 encoder->base.name);
24929352
DV		 14988
14989 /* Connector is active, but has no active pipe. This is
14990 * fallout from our resume register restoring. Disable
14991 * the encoder manually again. */
14992 if (encoder->base.crtc) {
14993 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14994 encoder->base.base.id,
8e329a03 14995 encoder->base.name);
24929352 14996 encoder->disable(encoder);
a62d1497
VS		 14997 if (encoder->post_disable)
14998 encoder->post_disable(encoder);
24929352 14999 }
7f1950fb 15000 encoder->base.crtc = NULL;
24929352
DV		 15001
15002 /* Inconsistent output/port/pipe state happens presumably due to
15003 * a bug in one of the get_hw_state functions. Or someplace else
15004 * in our code, like the register restore mess on resume. Clamp
15005 * things to off as a safer default. */
3a3371ff 15006 for_each_intel_connector(dev, connector) {
24929352
DV		 15007 if (connector->encoder != encoder)
15008 continue;
7f1950fb
EE		 15009 connector->base.dpms = DRM_MODE_DPMS_OFF;
15010 connector->base.encoder = NULL;
24929352
DV		 15011 }
15012 }
15013 /* Enabled encoders without active connectors will be fixed in
15014 * the crtc fixup. */
15015}
15016
04098753 15017void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15018{
15019 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15020 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15021
04098753
ID		 15022 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15023 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15024 i915_disable_vga(dev);
15025 }
15026}
15027
15028void i915_redisable_vga(struct drm_device *dev)
15029{
15030 struct drm_i915_private *dev_priv = dev->dev_private;
15031
8dc8a27c
PZ		 15032 /* This function can be called both from intel_modeset_setup_hw_state or
15033 * at a very early point in our resume sequence, where the power well
15034 * structures are not yet restored. Since this function is at a very
15035 * paranoid "someone might have enabled VGA while we were not looking"
15036 * level, just check if the power well is enabled instead of trying to
15037 * follow the "don't touch the power well if we don't need it" policy
15038 * the rest of the driver uses. */
f458ebbc 15039 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15040 return;
15041
04098753 15042 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15043}
15044
98ec7739
VS		 15045static bool primary_get_hw_state(struct intel_crtc *crtc)
15046{
15047 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15048
d032ffa0
ML		 15049 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15050}
15051
15052static void readout_plane_state(struct intel_crtc *crtc,
15053 struct intel_crtc_state *crtc_state)
15054{
15055 struct intel_plane *p;
4cf0ebbd 15056 struct intel_plane_state *plane_state;
d032ffa0
ML		 15057 bool active = crtc_state->base.active;
15058
d032ffa0 15059 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15060 if (crtc->pipe != p->pipe)
15061 continue;
15062
4cf0ebbd 15063 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15064
4cf0ebbd
ML		 15065 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15066 plane_state->visible = primary_get_hw_state(crtc);
15067 else {
15068 if (active)
15069 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15070
4cf0ebbd 15071 plane_state->visible = false;
d032ffa0
ML		 15072 }
15073 }
98ec7739
VS		 15074}
15075
30e984df 15076static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15077{
15078 struct drm_i915_private *dev_priv = dev->dev_private;
15079 enum pipe pipe;
24929352
DV		 15080 struct intel_crtc *crtc;
15081 struct intel_encoder *encoder;
15082 struct intel_connector *connector;
5358901f 15083 int i;
24929352 15084
d3fcc808 15085 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15086 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15087 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15088 crtc->config->base.crtc = &crtc->base;
3b117c8f 15089
0e8ffe1b 15090 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15091 crtc->config);
24929352 15092
49d6fa21 15093 crtc->base.state->active = crtc->active;
24929352 15094 crtc->base.enabled = crtc->active;
b70709a6 15095
5c1e3426
ML		 15096 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15097 if (crtc->base.state->active) {
15098 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15099 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15100 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15101
15102 /*
15103 * The initial mode needs to be set in order to keep
15104 * the atomic core happy. It wants a valid mode if the
15105 * crtc's enabled, so we do the above call.
15106 *
15107 * At this point some state updated by the connectors
15108 * in their ->detect() callback has not run yet, so
15109 * no recalculation can be done yet.
15110 *
15111 * Even if we could do a recalculation and modeset
15112 * right now it would cause a double modeset if
15113 * fbdev or userspace chooses a different initial mode.
15114 *
5c1e3426
ML		 15115 * If that happens, someone indicated they wanted a
15116 * mode change, which means it's safe to do a full
15117 * recalculation.
15118 */
1ed51de9 15119 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
5c1e3426
ML		 15120 }
15121
15122 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15123 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15124
15125 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15126 crtc->base.base.id,
15127 crtc->active ? "enabled" : "disabled");
15128 }
15129
5358901f
DV		 15130 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15131 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15132
3e369b76
ACO		 15133 pll->on = pll->get_hw_state(dev_priv, pll,
15134 &pll->config.hw_state);
5358901f 15135 pll->active = 0;
3e369b76 15136 pll->config.crtc_mask = 0;
d3fcc808 15137 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15138 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15139 pll->active++;
3e369b76 15140 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15141 }
5358901f 15142 }
5358901f 15143
1e6f2ddc 15144 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15145 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15146
3e369b76 15147 if (pll->config.crtc_mask)
bd2bb1b9 15148 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15149 }
15150
b2784e15 15151 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15152 pipe = 0;
15153
15154 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15155 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15156 encoder->base.crtc = &crtc->base;
6e3c9717 15157 encoder->get_config(encoder, crtc->config);
24929352
DV		 15158 } else {
15159 encoder->base.crtc = NULL;
15160 }
15161
6f2bcceb 15162 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15163 encoder->base.base.id,
8e329a03 15164 encoder->base.name,
24929352 15165 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15166 pipe_name(pipe));
24929352
DV		 15167 }
15168
3a3371ff 15169 for_each_intel_connector(dev, connector) {
24929352
DV		 15170 if (connector->get_hw_state(connector)) {
15171 connector->base.dpms = DRM_MODE_DPMS_ON;
24929352
DV		 15172 connector->base.encoder = &connector->encoder->base;
15173 } else {
15174 connector->base.dpms = DRM_MODE_DPMS_OFF;
15175 connector->base.encoder = NULL;
15176 }
15177 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15178 connector->base.base.id,
c23cc417 15179 connector->base.name,
24929352
DV		 15180 connector->base.encoder ? "enabled" : "disabled");
15181 }
30e984df
DV		 15182}
15183
043e9bda
ML		 15184/* Scan out the current hw modeset state,
15185 * and sanitizes it to the current state
15186 */
15187static void
15188intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15189{
15190 struct drm_i915_private *dev_priv = dev->dev_private;
15191 enum pipe pipe;
30e984df
DV		 15192 struct intel_crtc *crtc;
15193 struct intel_encoder *encoder;
35c95375 15194 int i;
30e984df
DV		 15195
15196 intel_modeset_readout_hw_state(dev);
24929352
DV		 15197
15198 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15199 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15200 intel_sanitize_encoder(encoder);
15201 }
15202
055e393f 15203 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15204 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15205 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15206 intel_dump_pipe_config(crtc, crtc->config,
15207 "[setup_hw_state]");
24929352 15208 }
9a935856 15209
d29b2f9d
ACO		 15210 intel_modeset_update_connector_atomic_state(dev);
15211
35c95375
DV		 15212 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15213 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15214
15215 if (!pll->on || pll->active)
15216 continue;
15217
15218 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15219
15220 pll->disable(dev_priv, pll);
15221 pll->on = false;
15222 }
15223
26e1fe4f 15224 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15225 vlv_wm_get_hw_state(dev);
15226 else if (IS_GEN9(dev))
3078999f
PB		 15227 skl_wm_get_hw_state(dev);
15228 else if (HAS_PCH_SPLIT(dev))
243e6a44 15229 ilk_wm_get_hw_state(dev);
292b990e
ML		 15230
15231 for_each_intel_crtc(dev, crtc) {
15232 unsigned long put_domains;
15233
15234 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15235 if (WARN_ON(put_domains))
15236 modeset_put_power_domains(dev_priv, put_domains);
15237 }
15238 intel_display_set_init_power(dev_priv, false);
043e9bda 15239}
7d0bc1ea 15240
043e9bda
ML		 15241void intel_display_resume(struct drm_device *dev)
15242{
15243 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15244 struct intel_connector *conn;
15245 struct intel_plane *plane;
15246 struct drm_crtc *crtc;
15247 int ret;
f30da187 15248
043e9bda
ML		 15249 if (!state)
15250 return;
15251
15252 state->acquire_ctx = dev->mode_config.acquire_ctx;
15253
15254 /* preserve complete old state, including dpll */
15255 intel_atomic_get_shared_dpll_state(state);
15256
15257 for_each_crtc(dev, crtc) {
15258 struct drm_crtc_state *crtc_state =
15259 drm_atomic_get_crtc_state(state, crtc);
15260
15261 ret = PTR_ERR_OR_ZERO(crtc_state);
15262 if (ret)
15263 goto err;
15264
15265 /* force a restore */
15266 crtc_state->mode_changed = true;
45e2b5f6 15267 }
8af6cf88 15268
043e9bda
ML		 15269 for_each_intel_plane(dev, plane) {
15270 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15271 if (ret)
15272 goto err;
15273 }
15274
15275 for_each_intel_connector(dev, conn) {
15276 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15277 if (ret)
15278 goto err;
15279 }
15280
15281 intel_modeset_setup_hw_state(dev);
15282
15283 i915_redisable_vga(dev);
74c090b1 15284 ret = drm_atomic_commit(state);
043e9bda
ML		 15285 if (!ret)
15286 return;
15287
15288err:
15289 DRM_ERROR("Restoring old state failed with %i\n", ret);
15290 drm_atomic_state_free(state);
2c7111db
CW		 15291}
15292
15293void intel_modeset_gem_init(struct drm_device *dev)
15294{
484b41dd 15295 struct drm_crtc *c;
2ff8fde1 15296 struct drm_i915_gem_object *obj;
e0d6149b 15297 int ret;
484b41dd 15298
ae48434c
ID		 15299 mutex_lock(&dev->struct_mutex);
15300 intel_init_gt_powersave(dev);
15301 mutex_unlock(&dev->struct_mutex);
15302
1833b134 15303 intel_modeset_init_hw(dev);
02e792fb
DV		 15304
15305 intel_setup_overlay(dev);
484b41dd
JB		 15306
15307 /*
15308 * Make sure any fbs we allocated at startup are properly
15309 * pinned & fenced. When we do the allocation it's too early
15310 * for this.
15311 */
70e1e0ec 15312 for_each_crtc(dev, c) {
2ff8fde1
MR		 15313 obj = intel_fb_obj(c->primary->fb);
15314 if (obj == NULL)
484b41dd
JB		 15315 continue;
15316
e0d6149b
TU		 15317 mutex_lock(&dev->struct_mutex);
15318 ret = intel_pin_and_fence_fb_obj(c->primary,
15319 c->primary->fb,
15320 c->primary->state,
91af127f 15321 NULL, NULL);
e0d6149b
TU		 15322 mutex_unlock(&dev->struct_mutex);
15323 if (ret) {
484b41dd
JB		 15324 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15325 to_intel_crtc(c)->pipe);
66e514c1
DA		 15326 drm_framebuffer_unreference(c->primary->fb);
15327 c->primary->fb = NULL;
36750f28 15328 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15329 update_state_fb(c->primary);
36750f28 15330 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15331 }
15332 }
0962c3c9
VS		 15333
15334 intel_backlight_register(dev);
79e53945
JB		 15335}
15336
4932e2c3
ID		 15337void intel_connector_unregister(struct intel_connector *intel_connector)
15338{
15339 struct drm_connector *connector = &intel_connector->base;
15340
15341 intel_panel_destroy_backlight(connector);
34ea3d38 15342 drm_connector_unregister(connector);
4932e2c3
ID		 15343}
15344
79e53945
JB		 15345void intel_modeset_cleanup(struct drm_device *dev)
15346{
652c393a 15347 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15348 struct drm_connector *connector;
652c393a 15349
2eb5252e
ID		 15350 intel_disable_gt_powersave(dev);
15351
0962c3c9
VS		 15352 intel_backlight_unregister(dev);
15353
fd0c0642
DV		 15354 /*
15355 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15356 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15357 * experience fancy races otherwise.
15358 */
2aeb7d3a 15359 intel_irq_uninstall(dev_priv);
eb21b92b 15360
fd0c0642
DV		 15361 /*
15362 * Due to the hpd irq storm handling the hotplug work can re-arm the
15363 * poll handlers. Hence disable polling after hpd handling is shut down.
15364 */
f87ea761 15365 drm_kms_helper_poll_fini(dev);
fd0c0642 15366
723bfd70
JB		 15367 intel_unregister_dsm_handler();
15368
7733b49b 15369 intel_fbc_disable(dev_priv);
69341a5e 15370
1630fe75
CW		 15371 /* flush any delayed tasks or pending work */
15372 flush_scheduled_work();
15373
db31af1d
JN		 15374 /* destroy the backlight and sysfs files before encoders/connectors */
15375 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15376 struct intel_connector *intel_connector;
15377
15378 intel_connector = to_intel_connector(connector);
15379 intel_connector->unregister(intel_connector);
db31af1d 15380 }
d9255d57 15381
79e53945 15382 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15383
15384 intel_cleanup_overlay(dev);
ae48434c
ID		 15385
15386 mutex_lock(&dev->struct_mutex);
15387 intel_cleanup_gt_powersave(dev);
15388 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15389}
15390
f1c79df3
ZW		 15391/*
15392 * Return which encoder is currently attached for connector.
15393 */
df0e9248 15394struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15395{
df0e9248
CW		 15396 return &intel_attached_encoder(connector)->base;
15397}
f1c79df3 15398
df0e9248
CW		 15399void intel_connector_attach_encoder(struct intel_connector *connector,
15400 struct intel_encoder *encoder)
15401{
15402 connector->encoder = encoder;
15403 drm_mode_connector_attach_encoder(&connector->base,
15404 &encoder->base);
79e53945 15405}
28d52043
DA		 15406
15407/*
15408 * set vga decode state - true == enable VGA decode
15409 */
15410int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15411{
15412 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15413 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15414 u16 gmch_ctrl;
15415
75fa041d
CW		 15416 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15417 DRM_ERROR("failed to read control word\n");
15418 return -EIO;
15419 }
15420
c0cc8a55
CW		 15421 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15422 return 0;
15423
28d52043
DA		 15424 if (state)
15425 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15426 else
15427 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15428
15429 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15430 DRM_ERROR("failed to write control word\n");
15431 return -EIO;
15432 }
15433
28d52043
DA		 15434 return 0;
15435}
c4a1d9e4 15436
c4a1d9e4 15437struct intel_display_error_state {
ff57f1b0
PZ		 15438
15439 u32 power_well_driver;
15440
63b66e5b
CW		 15441 int num_transcoders;
15442
c4a1d9e4
CW		 15443 struct intel_cursor_error_state {
15444 u32 control;
15445 u32 position;
15446 u32 base;
15447 u32 size;
52331309 15448 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15449
15450 struct intel_pipe_error_state {
ddf9c536 15451 bool power_domain_on;
c4a1d9e4 15452 u32 source;
f301b1e1 15453 u32 stat;
52331309 15454 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15455
15456 struct intel_plane_error_state {
15457 u32 control;
15458 u32 stride;
15459 u32 size;
15460 u32 pos;
15461 u32 addr;
15462 u32 surface;
15463 u32 tile_offset;
52331309 15464 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15465
15466 struct intel_transcoder_error_state {
ddf9c536 15467 bool power_domain_on;
63b66e5b
CW		 15468 enum transcoder cpu_transcoder;
15469
15470 u32 conf;
15471
15472 u32 htotal;
15473 u32 hblank;
15474 u32 hsync;
15475 u32 vtotal;
15476 u32 vblank;
15477 u32 vsync;
15478 } transcoder[4];
c4a1d9e4
CW		 15479};
15480
15481struct intel_display_error_state *
15482intel_display_capture_error_state(struct drm_device *dev)
15483{
fbee40df 15484 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15485 struct intel_display_error_state *error;
63b66e5b
CW		 15486 int transcoders[] = {
15487 TRANSCODER_A,
15488 TRANSCODER_B,
15489 TRANSCODER_C,
15490 TRANSCODER_EDP,
15491 };
c4a1d9e4
CW		 15492 int i;
15493
63b66e5b
CW		 15494 if (INTEL_INFO(dev)->num_pipes == 0)
15495 return NULL;
15496
9d1cb914 15497 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15498 if (error == NULL)
15499 return NULL;
15500
190be112 15501 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15502 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15503
055e393f 15504 for_each_pipe(dev_priv, i) {
ddf9c536 15505 error->pipe[i].power_domain_on =
f458ebbc
DV		 15506 __intel_display_power_is_enabled(dev_priv,
15507 POWER_DOMAIN_PIPE(i));
ddf9c536 15508 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15509 continue;
15510
5efb3e28
VS		 15511 error->cursor[i].control = I915_READ(CURCNTR(i));
15512 error->cursor[i].position = I915_READ(CURPOS(i));
15513 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15514
15515 error->plane[i].control = I915_READ(DSPCNTR(i));
15516 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15517 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15518 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15519 error->plane[i].pos = I915_READ(DSPPOS(i));
15520 }
ca291363
PZ		 15521 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15522 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15523 if (INTEL_INFO(dev)->gen >= 4) {
15524 error->plane[i].surface = I915_READ(DSPSURF(i));
15525 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15526 }
15527
c4a1d9e4 15528 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15529
3abfce77 15530 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15531 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15532 }
15533
15534 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15535 if (HAS_DDI(dev_priv->dev))
15536 error->num_transcoders++; /* Account for eDP. */
15537
15538 for (i = 0; i < error->num_transcoders; i++) {
15539 enum transcoder cpu_transcoder = transcoders[i];
15540
ddf9c536 15541 error->transcoder[i].power_domain_on =
f458ebbc 15542 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15543 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15544 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15545 continue;
15546
63b66e5b
CW		 15547 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15548
15549 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15550 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15551 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15552 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15553 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15554 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15555 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15556 }
15557
15558 return error;
15559}
15560
edc3d884
MK		 15561#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15562
c4a1d9e4 15563void
edc3d884 15564intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15565 struct drm_device *dev,
15566 struct intel_display_error_state *error)
15567{
055e393f 15568 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15569 int i;
15570
63b66e5b
CW		 15571 if (!error)
15572 return;
15573
edc3d884 15574 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15575 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15576 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15577 error->power_well_driver);
055e393f 15578 for_each_pipe(dev_priv, i) {
edc3d884 15579 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15580 err_printf(m, " Power: %s\n",
15581 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15582 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15583 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15584
15585 err_printf(m, "Plane [%d]:\n", i);
15586 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15587 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15588 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15589 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15590 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15591 }
4b71a570 15592 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15593 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15594 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15595 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15596 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15597 }
15598
edc3d884
MK		 15599 err_printf(m, "Cursor [%d]:\n", i);
15600 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15601 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15602 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15603 }
63b66e5b
CW		 15604
15605 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15606 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15607 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15608 err_printf(m, " Power: %s\n",
15609 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15610 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15611 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15612 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15613 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15614 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15615 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15616 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15617 }
c4a1d9e4 15618}
e2fcdaa9
VS		 15619
15620void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15621{
15622 struct intel_crtc *crtc;
15623
15624 for_each_intel_crtc(dev, crtc) {
15625 struct intel_unpin_work *work;
e2fcdaa9 15626
5e2d7afc 15627 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15628
15629 work = crtc->unpin_work;
15630
15631 if (work && work->event &&
15632 work->event->base.file_priv == file) {
15633 kfree(work->event);
15634 work->event = NULL;
15635 }
15636
5e2d7afc 15637 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15638 }
15639}
Linux kernel - Deliverables
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