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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP) |
46 | #define IS_PCH_eDP(i) ((i)->is_pch_edp) | |
32f9d658 | 47 | |
ea5b213a CW |
48 | struct intel_dp { |
49 | struct intel_encoder base; | |
a4fc5ed6 KP |
50 | uint32_t output_reg; |
51 | uint32_t DP; | |
52 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 53 | bool has_audio; |
c8110e52 | 54 | int dpms_mode; |
a4fc5ed6 KP |
55 | uint8_t link_bw; |
56 | uint8_t lane_count; | |
57 | uint8_t dpcd[4]; | |
a4fc5ed6 KP |
58 | struct i2c_adapter adapter; |
59 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 60 | bool is_pch_edp; |
33a34e4e JB |
61 | uint8_t train_set[4]; |
62 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
a4fc5ed6 KP |
63 | }; |
64 | ||
ea5b213a CW |
65 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
66 | { | |
67 | return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base); | |
68 | } | |
a4fc5ed6 | 69 | |
33a34e4e JB |
70 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
71 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 72 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 73 | |
32f9d658 | 74 | void |
21d40d37 | 75 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 76 | int *lane_num, int *link_bw) |
32f9d658 | 77 | { |
ea5b213a | 78 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 79 | |
ea5b213a CW |
80 | *lane_num = intel_dp->lane_count; |
81 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 82 | *link_bw = 162000; |
ea5b213a | 83 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
84 | *link_bw = 270000; |
85 | } | |
86 | ||
a4fc5ed6 | 87 | static int |
ea5b213a | 88 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 89 | { |
a4fc5ed6 KP |
90 | int max_lane_count = 4; |
91 | ||
ea5b213a CW |
92 | if (intel_dp->dpcd[0] >= 0x11) { |
93 | max_lane_count = intel_dp->dpcd[2] & 0x1f; | |
a4fc5ed6 KP |
94 | switch (max_lane_count) { |
95 | case 1: case 2: case 4: | |
96 | break; | |
97 | default: | |
98 | max_lane_count = 4; | |
99 | } | |
100 | } | |
101 | return max_lane_count; | |
102 | } | |
103 | ||
104 | static int | |
ea5b213a | 105 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 106 | { |
ea5b213a | 107 | int max_link_bw = intel_dp->dpcd[1]; |
a4fc5ed6 KP |
108 | |
109 | switch (max_link_bw) { | |
110 | case DP_LINK_BW_1_62: | |
111 | case DP_LINK_BW_2_7: | |
112 | break; | |
113 | default: | |
114 | max_link_bw = DP_LINK_BW_1_62; | |
115 | break; | |
116 | } | |
117 | return max_link_bw; | |
118 | } | |
119 | ||
120 | static int | |
121 | intel_dp_link_clock(uint8_t link_bw) | |
122 | { | |
123 | if (link_bw == DP_LINK_BW_2_7) | |
124 | return 270000; | |
125 | else | |
126 | return 162000; | |
127 | } | |
128 | ||
129 | /* I think this is a fiction */ | |
130 | static int | |
ea5b213a | 131 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 132 | { |
885a5fb5 ZW |
133 | struct drm_i915_private *dev_priv = dev->dev_private; |
134 | ||
ea5b213a | 135 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
885a5fb5 ZW |
136 | return (pixel_clock * dev_priv->edp_bpp) / 8; |
137 | else | |
138 | return pixel_clock * 3; | |
a4fc5ed6 KP |
139 | } |
140 | ||
fe27d53e DA |
141 | static int |
142 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
143 | { | |
144 | return (max_link_clock * max_lanes * 8) / 10; | |
145 | } | |
146 | ||
a4fc5ed6 KP |
147 | static int |
148 | intel_dp_mode_valid(struct drm_connector *connector, | |
149 | struct drm_display_mode *mode) | |
150 | { | |
55f78c43 | 151 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a | 152 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
7de56f43 ZY |
153 | struct drm_device *dev = connector->dev; |
154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a CW |
155 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
156 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 157 | |
ea5b213a | 158 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
7de56f43 ZY |
159 | dev_priv->panel_fixed_mode) { |
160 | if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay) | |
161 | return MODE_PANEL; | |
162 | ||
163 | if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay) | |
164 | return MODE_PANEL; | |
165 | } | |
166 | ||
fe27d53e DA |
167 | /* only refuse the mode on non eDP since we have seen some wierd eDP panels |
168 | which are outside spec tolerances but somehow work by magic */ | |
ea5b213a CW |
169 | if (!IS_eDP(intel_dp) && |
170 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) | |
fe27d53e | 171 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
172 | return MODE_CLOCK_HIGH; |
173 | ||
174 | if (mode->clock < 10000) | |
175 | return MODE_CLOCK_LOW; | |
176 | ||
177 | return MODE_OK; | |
178 | } | |
179 | ||
180 | static uint32_t | |
181 | pack_aux(uint8_t *src, int src_bytes) | |
182 | { | |
183 | int i; | |
184 | uint32_t v = 0; | |
185 | ||
186 | if (src_bytes > 4) | |
187 | src_bytes = 4; | |
188 | for (i = 0; i < src_bytes; i++) | |
189 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
190 | return v; | |
191 | } | |
192 | ||
193 | static void | |
194 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
195 | { | |
196 | int i; | |
197 | if (dst_bytes > 4) | |
198 | dst_bytes = 4; | |
199 | for (i = 0; i < dst_bytes; i++) | |
200 | dst[i] = src >> ((3-i) * 8); | |
201 | } | |
202 | ||
fb0f8fbf KP |
203 | /* hrawclock is 1/4 the FSB frequency */ |
204 | static int | |
205 | intel_hrawclk(struct drm_device *dev) | |
206 | { | |
207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
208 | uint32_t clkcfg; | |
209 | ||
210 | clkcfg = I915_READ(CLKCFG); | |
211 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
212 | case CLKCFG_FSB_400: | |
213 | return 100; | |
214 | case CLKCFG_FSB_533: | |
215 | return 133; | |
216 | case CLKCFG_FSB_667: | |
217 | return 166; | |
218 | case CLKCFG_FSB_800: | |
219 | return 200; | |
220 | case CLKCFG_FSB_1067: | |
221 | return 266; | |
222 | case CLKCFG_FSB_1333: | |
223 | return 333; | |
224 | /* these two are just a guess; one of them might be right */ | |
225 | case CLKCFG_FSB_1600: | |
226 | case CLKCFG_FSB_1600_ALT: | |
227 | return 400; | |
228 | default: | |
229 | return 133; | |
230 | } | |
231 | } | |
232 | ||
a4fc5ed6 | 233 | static int |
ea5b213a | 234 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
235 | uint8_t *send, int send_bytes, |
236 | uint8_t *recv, int recv_size) | |
237 | { | |
ea5b213a CW |
238 | uint32_t output_reg = intel_dp->output_reg; |
239 | struct drm_device *dev = intel_dp->base.enc.dev; | |
a4fc5ed6 KP |
240 | struct drm_i915_private *dev_priv = dev->dev_private; |
241 | uint32_t ch_ctl = output_reg + 0x10; | |
242 | uint32_t ch_data = ch_ctl + 4; | |
243 | int i; | |
244 | int recv_bytes; | |
a4fc5ed6 | 245 | uint32_t status; |
fb0f8fbf | 246 | uint32_t aux_clock_divider; |
e3421a18 | 247 | int try, precharge; |
a4fc5ed6 KP |
248 | |
249 | /* The clock divider is based off the hrawclk, | |
fb0f8fbf KP |
250 | * and would like to run at 2MHz. So, take the |
251 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
252 | * |
253 | * Note that PCH attached eDP panels should use a 125MHz input | |
254 | * clock divider. | |
a4fc5ed6 | 255 | */ |
6176b8f9 | 256 | if (IS_eDP(intel_dp) && !IS_PCH_eDP(intel_dp)) { |
e3421a18 ZW |
257 | if (IS_GEN6(dev)) |
258 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
259 | else | |
260 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
261 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 262 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
263 | else |
264 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
265 | ||
e3421a18 ZW |
266 | if (IS_GEN6(dev)) |
267 | precharge = 3; | |
268 | else | |
269 | precharge = 5; | |
270 | ||
4f7f7b7e CW |
271 | if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { |
272 | DRM_ERROR("dp_aux_ch not started status 0x%08x\n", | |
273 | I915_READ(ch_ctl)); | |
274 | return -EBUSY; | |
275 | } | |
276 | ||
fb0f8fbf KP |
277 | /* Must try at least 3 times according to DP spec */ |
278 | for (try = 0; try < 5; try++) { | |
279 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
280 | for (i = 0; i < send_bytes; i += 4) |
281 | I915_WRITE(ch_data + i, | |
282 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
283 | |
284 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
285 | I915_WRITE(ch_ctl, |
286 | DP_AUX_CH_CTL_SEND_BUSY | | |
287 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
288 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
289 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
290 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
291 | DP_AUX_CH_CTL_DONE | | |
292 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
293 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 294 | for (;;) { |
fb0f8fbf KP |
295 | status = I915_READ(ch_ctl); |
296 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
297 | break; | |
4f7f7b7e | 298 | udelay(100); |
fb0f8fbf KP |
299 | } |
300 | ||
301 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
302 | I915_WRITE(ch_ctl, |
303 | status | | |
304 | DP_AUX_CH_CTL_DONE | | |
305 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
306 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
307 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
308 | break; |
309 | } | |
310 | ||
a4fc5ed6 | 311 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 312 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 313 | return -EBUSY; |
a4fc5ed6 KP |
314 | } |
315 | ||
316 | /* Check for timeout or receive error. | |
317 | * Timeouts occur when the sink is not connected | |
318 | */ | |
a5b3da54 | 319 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 320 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
321 | return -EIO; |
322 | } | |
1ae8c0a5 KP |
323 | |
324 | /* Timeouts occur when the device isn't connected, so they're | |
325 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 326 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 327 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 328 | return -ETIMEDOUT; |
a4fc5ed6 KP |
329 | } |
330 | ||
331 | /* Unload any bytes sent back from the other side */ | |
332 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
333 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
334 | if (recv_bytes > recv_size) |
335 | recv_bytes = recv_size; | |
336 | ||
4f7f7b7e CW |
337 | for (i = 0; i < recv_bytes; i += 4) |
338 | unpack_aux(I915_READ(ch_data + i), | |
339 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
340 | |
341 | return recv_bytes; | |
342 | } | |
343 | ||
344 | /* Write data to the aux channel in native mode */ | |
345 | static int | |
ea5b213a | 346 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
347 | uint16_t address, uint8_t *send, int send_bytes) |
348 | { | |
349 | int ret; | |
350 | uint8_t msg[20]; | |
351 | int msg_bytes; | |
352 | uint8_t ack; | |
353 | ||
354 | if (send_bytes > 16) | |
355 | return -1; | |
356 | msg[0] = AUX_NATIVE_WRITE << 4; | |
357 | msg[1] = address >> 8; | |
eebc863e | 358 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
359 | msg[3] = send_bytes - 1; |
360 | memcpy(&msg[4], send, send_bytes); | |
361 | msg_bytes = send_bytes + 4; | |
362 | for (;;) { | |
ea5b213a | 363 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
364 | if (ret < 0) |
365 | return ret; | |
366 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
367 | break; | |
368 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
369 | udelay(100); | |
370 | else | |
a5b3da54 | 371 | return -EIO; |
a4fc5ed6 KP |
372 | } |
373 | return send_bytes; | |
374 | } | |
375 | ||
376 | /* Write a single byte to the aux channel in native mode */ | |
377 | static int | |
ea5b213a | 378 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
379 | uint16_t address, uint8_t byte) |
380 | { | |
ea5b213a | 381 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
382 | } |
383 | ||
384 | /* read bytes from a native aux channel */ | |
385 | static int | |
ea5b213a | 386 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
387 | uint16_t address, uint8_t *recv, int recv_bytes) |
388 | { | |
389 | uint8_t msg[4]; | |
390 | int msg_bytes; | |
391 | uint8_t reply[20]; | |
392 | int reply_bytes; | |
393 | uint8_t ack; | |
394 | int ret; | |
395 | ||
396 | msg[0] = AUX_NATIVE_READ << 4; | |
397 | msg[1] = address >> 8; | |
398 | msg[2] = address & 0xff; | |
399 | msg[3] = recv_bytes - 1; | |
400 | ||
401 | msg_bytes = 4; | |
402 | reply_bytes = recv_bytes + 1; | |
403 | ||
404 | for (;;) { | |
ea5b213a | 405 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 406 | reply, reply_bytes); |
a5b3da54 KP |
407 | if (ret == 0) |
408 | return -EPROTO; | |
409 | if (ret < 0) | |
a4fc5ed6 KP |
410 | return ret; |
411 | ack = reply[0]; | |
412 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
413 | memcpy(recv, reply + 1, ret - 1); | |
414 | return ret - 1; | |
415 | } | |
416 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
417 | udelay(100); | |
418 | else | |
a5b3da54 | 419 | return -EIO; |
a4fc5ed6 KP |
420 | } |
421 | } | |
422 | ||
423 | static int | |
ab2c0672 DA |
424 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
425 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 426 | { |
ab2c0672 | 427 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
428 | struct intel_dp *intel_dp = container_of(adapter, |
429 | struct intel_dp, | |
430 | adapter); | |
ab2c0672 DA |
431 | uint16_t address = algo_data->address; |
432 | uint8_t msg[5]; | |
433 | uint8_t reply[2]; | |
434 | int msg_bytes; | |
435 | int reply_bytes; | |
436 | int ret; | |
437 | ||
438 | /* Set up the command byte */ | |
439 | if (mode & MODE_I2C_READ) | |
440 | msg[0] = AUX_I2C_READ << 4; | |
441 | else | |
442 | msg[0] = AUX_I2C_WRITE << 4; | |
443 | ||
444 | if (!(mode & MODE_I2C_STOP)) | |
445 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 446 | |
ab2c0672 DA |
447 | msg[1] = address >> 8; |
448 | msg[2] = address; | |
449 | ||
450 | switch (mode) { | |
451 | case MODE_I2C_WRITE: | |
452 | msg[3] = 0; | |
453 | msg[4] = write_byte; | |
454 | msg_bytes = 5; | |
455 | reply_bytes = 1; | |
456 | break; | |
457 | case MODE_I2C_READ: | |
458 | msg[3] = 0; | |
459 | msg_bytes = 4; | |
460 | reply_bytes = 2; | |
461 | break; | |
462 | default: | |
463 | msg_bytes = 3; | |
464 | reply_bytes = 1; | |
465 | break; | |
466 | } | |
467 | ||
468 | for (;;) { | |
ea5b213a | 469 | ret = intel_dp_aux_ch(intel_dp, |
ab2c0672 DA |
470 | msg, msg_bytes, |
471 | reply, reply_bytes); | |
472 | if (ret < 0) { | |
3ff99164 | 473 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
474 | return ret; |
475 | } | |
476 | switch (reply[0] & AUX_I2C_REPLY_MASK) { | |
477 | case AUX_I2C_REPLY_ACK: | |
478 | if (mode == MODE_I2C_READ) { | |
479 | *read_byte = reply[1]; | |
480 | } | |
481 | return reply_bytes - 1; | |
482 | case AUX_I2C_REPLY_NACK: | |
3ff99164 | 483 | DRM_DEBUG_KMS("aux_ch nack\n"); |
ab2c0672 DA |
484 | return -EREMOTEIO; |
485 | case AUX_I2C_REPLY_DEFER: | |
3ff99164 | 486 | DRM_DEBUG_KMS("aux_ch defer\n"); |
ab2c0672 DA |
487 | udelay(100); |
488 | break; | |
489 | default: | |
490 | DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]); | |
491 | return -EREMOTEIO; | |
492 | } | |
493 | } | |
a4fc5ed6 KP |
494 | } |
495 | ||
496 | static int | |
ea5b213a | 497 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 498 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 499 | { |
d54e9d28 | 500 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
501 | intel_dp->algo.running = false; |
502 | intel_dp->algo.address = 0; | |
503 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
504 | ||
505 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
506 | intel_dp->adapter.owner = THIS_MODULE; | |
507 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
508 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
509 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
510 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
511 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
512 | ||
513 | return i2c_dp_aux_add_bus(&intel_dp->adapter); | |
a4fc5ed6 KP |
514 | } |
515 | ||
516 | static bool | |
517 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
518 | struct drm_display_mode *adjusted_mode) | |
519 | { | |
0d3a1bee ZY |
520 | struct drm_device *dev = encoder->dev; |
521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 522 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 523 | int lane_count, clock; |
ea5b213a CW |
524 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
525 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
526 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
527 | ||
ea5b213a | 528 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
0d3a1bee | 529 | dev_priv->panel_fixed_mode) { |
1d8e1c75 CW |
530 | intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode); |
531 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, | |
532 | mode, adjusted_mode); | |
0d3a1bee ZY |
533 | /* |
534 | * the mode->clock is used to calculate the Data&Link M/N | |
535 | * of the pipe. For the eDP the fixed clock should be used. | |
536 | */ | |
537 | mode->clock = dev_priv->panel_fixed_mode->clock; | |
538 | } | |
539 | ||
a4fc5ed6 KP |
540 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
541 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 542 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 543 | |
ea5b213a | 544 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 545 | <= link_avail) { |
ea5b213a CW |
546 | intel_dp->link_bw = bws[clock]; |
547 | intel_dp->lane_count = lane_count; | |
548 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
549 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
550 | "count %d clock %d\n", | |
ea5b213a | 551 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
552 | adjusted_mode->clock); |
553 | return true; | |
554 | } | |
555 | } | |
556 | } | |
fe27d53e | 557 | |
ea5b213a | 558 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
fe27d53e | 559 | /* okay we failed just pick the highest */ |
ea5b213a CW |
560 | intel_dp->lane_count = max_lane_count; |
561 | intel_dp->link_bw = bws[max_clock]; | |
562 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
fe27d53e DA |
563 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " |
564 | "count %d clock %d\n", | |
ea5b213a | 565 | intel_dp->link_bw, intel_dp->lane_count, |
fe27d53e | 566 | adjusted_mode->clock); |
1d8e1c75 | 567 | |
fe27d53e DA |
568 | return true; |
569 | } | |
1d8e1c75 | 570 | |
a4fc5ed6 KP |
571 | return false; |
572 | } | |
573 | ||
574 | struct intel_dp_m_n { | |
575 | uint32_t tu; | |
576 | uint32_t gmch_m; | |
577 | uint32_t gmch_n; | |
578 | uint32_t link_m; | |
579 | uint32_t link_n; | |
580 | }; | |
581 | ||
582 | static void | |
583 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
584 | { | |
585 | while (*num > 0xffffff || *den > 0xffffff) { | |
586 | *num >>= 1; | |
587 | *den >>= 1; | |
588 | } | |
589 | } | |
590 | ||
591 | static void | |
36e83a18 | 592 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
593 | int nlanes, |
594 | int pixel_clock, | |
595 | int link_clock, | |
596 | struct intel_dp_m_n *m_n) | |
597 | { | |
598 | m_n->tu = 64; | |
36e83a18 | 599 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
600 | m_n->gmch_n = link_clock * nlanes; |
601 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
602 | m_n->link_m = pixel_clock; | |
603 | m_n->link_n = link_clock; | |
604 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
605 | } | |
606 | ||
36e83a18 ZY |
607 | bool intel_pch_has_edp(struct drm_crtc *crtc) |
608 | { | |
609 | struct drm_device *dev = crtc->dev; | |
610 | struct drm_mode_config *mode_config = &dev->mode_config; | |
611 | struct drm_encoder *encoder; | |
612 | ||
613 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a | 614 | struct intel_dp *intel_dp; |
36e83a18 | 615 | |
ea5b213a | 616 | if (encoder->crtc != crtc) |
36e83a18 ZY |
617 | continue; |
618 | ||
ea5b213a CW |
619 | intel_dp = enc_to_intel_dp(encoder); |
620 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
621 | return intel_dp->is_pch_edp; | |
36e83a18 ZY |
622 | } |
623 | return false; | |
624 | } | |
625 | ||
a4fc5ed6 KP |
626 | void |
627 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
628 | struct drm_display_mode *adjusted_mode) | |
629 | { | |
630 | struct drm_device *dev = crtc->dev; | |
631 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 632 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
633 | struct drm_i915_private *dev_priv = dev->dev_private; |
634 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
36e83a18 | 635 | int lane_count = 4, bpp = 24; |
a4fc5ed6 KP |
636 | struct intel_dp_m_n m_n; |
637 | ||
638 | /* | |
21d40d37 | 639 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 640 | */ |
55f78c43 | 641 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 642 | struct intel_dp *intel_dp; |
a4fc5ed6 | 643 | |
d8201ab6 | 644 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
645 | continue; |
646 | ||
ea5b213a CW |
647 | intel_dp = enc_to_intel_dp(encoder); |
648 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
649 | lane_count = intel_dp->lane_count; | |
650 | if (IS_PCH_eDP(intel_dp)) | |
36e83a18 | 651 | bpp = dev_priv->edp_bpp; |
a4fc5ed6 KP |
652 | break; |
653 | } | |
654 | } | |
655 | ||
656 | /* | |
657 | * Compute the GMCH and Link ratios. The '3' here is | |
658 | * the number of bytes_per_pixel post-LUT, which we always | |
659 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
660 | */ | |
36e83a18 | 661 | intel_dp_compute_m_n(bpp, lane_count, |
a4fc5ed6 KP |
662 | mode->clock, adjusted_mode->clock, &m_n); |
663 | ||
c619eed4 | 664 | if (HAS_PCH_SPLIT(dev)) { |
5eb08b69 ZW |
665 | if (intel_crtc->pipe == 0) { |
666 | I915_WRITE(TRANSA_DATA_M1, | |
667 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
668 | m_n.gmch_m); | |
669 | I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n); | |
670 | I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m); | |
671 | I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n); | |
672 | } else { | |
673 | I915_WRITE(TRANSB_DATA_M1, | |
674 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
675 | m_n.gmch_m); | |
676 | I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n); | |
677 | I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m); | |
678 | I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n); | |
679 | } | |
a4fc5ed6 | 680 | } else { |
5eb08b69 ZW |
681 | if (intel_crtc->pipe == 0) { |
682 | I915_WRITE(PIPEA_GMCH_DATA_M, | |
683 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
684 | m_n.gmch_m); | |
685 | I915_WRITE(PIPEA_GMCH_DATA_N, | |
686 | m_n.gmch_n); | |
687 | I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m); | |
688 | I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n); | |
689 | } else { | |
690 | I915_WRITE(PIPEB_GMCH_DATA_M, | |
691 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
692 | m_n.gmch_m); | |
693 | I915_WRITE(PIPEB_GMCH_DATA_N, | |
694 | m_n.gmch_n); | |
695 | I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m); | |
696 | I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n); | |
697 | } | |
a4fc5ed6 KP |
698 | } |
699 | } | |
700 | ||
701 | static void | |
702 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
703 | struct drm_display_mode *adjusted_mode) | |
704 | { | |
e3421a18 | 705 | struct drm_device *dev = encoder->dev; |
ea5b213a CW |
706 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
707 | struct drm_crtc *crtc = intel_dp->base.enc.crtc; | |
a4fc5ed6 KP |
708 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
709 | ||
ea5b213a | 710 | intel_dp->DP = (DP_VOLTAGE_0_4 | |
9c9e7927 AJ |
711 | DP_PRE_EMPHASIS_0); |
712 | ||
713 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 714 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 715 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 716 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 717 | |
ea5b213a CW |
718 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
719 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
e3421a18 | 720 | else |
ea5b213a | 721 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 722 | |
ea5b213a | 723 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 724 | case 1: |
ea5b213a | 725 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
726 | break; |
727 | case 2: | |
ea5b213a | 728 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
729 | break; |
730 | case 4: | |
ea5b213a | 731 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
732 | break; |
733 | } | |
ea5b213a CW |
734 | if (intel_dp->has_audio) |
735 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 736 | |
ea5b213a CW |
737 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
738 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
739 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a4fc5ed6 KP |
740 | |
741 | /* | |
9962c925 | 742 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 743 | */ |
ea5b213a CW |
744 | if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) { |
745 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
746 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
747 | } |
748 | ||
e3421a18 ZW |
749 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
750 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 751 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 752 | |
ea5b213a | 753 | if (IS_eDP(intel_dp)) { |
32f9d658 | 754 | /* don't miss out required setting for eDP */ |
ea5b213a | 755 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 756 | if (adjusted_mode->clock < 200000) |
ea5b213a | 757 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 758 | else |
ea5b213a | 759 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 760 | } |
a4fc5ed6 KP |
761 | } |
762 | ||
7eaf5547 JB |
763 | /* Returns true if the panel was already on when called */ |
764 | static bool ironlake_edp_panel_on (struct drm_device *dev) | |
9934c132 JB |
765 | { |
766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 767 | u32 pp; |
9934c132 | 768 | |
913d8d11 | 769 | if (I915_READ(PCH_PP_STATUS) & PP_ON) |
7eaf5547 | 770 | return true; |
9934c132 JB |
771 | |
772 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
773 | |
774 | /* ILK workaround: disable reset around power sequence */ | |
775 | pp &= ~PANEL_POWER_RESET; | |
776 | I915_WRITE(PCH_PP_CONTROL, pp); | |
777 | POSTING_READ(PCH_PP_CONTROL); | |
778 | ||
9934c132 JB |
779 | pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON; |
780 | I915_WRITE(PCH_PP_CONTROL, pp); | |
9934c132 | 781 | |
481b6af3 | 782 | if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000)) |
913d8d11 CW |
783 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
784 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 785 | |
3969c9c9 | 786 | pp &= ~(PANEL_UNLOCK_REGS); |
37c6c9b0 | 787 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 788 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 789 | POSTING_READ(PCH_PP_CONTROL); |
7eaf5547 JB |
790 | |
791 | return false; | |
9934c132 JB |
792 | } |
793 | ||
794 | static void ironlake_edp_panel_off (struct drm_device *dev) | |
795 | { | |
796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913d8d11 | 797 | u32 pp; |
9934c132 JB |
798 | |
799 | pp = I915_READ(PCH_PP_CONTROL); | |
37c6c9b0 JB |
800 | |
801 | /* ILK workaround: disable reset around power sequence */ | |
802 | pp &= ~PANEL_POWER_RESET; | |
803 | I915_WRITE(PCH_PP_CONTROL, pp); | |
804 | POSTING_READ(PCH_PP_CONTROL); | |
805 | ||
9934c132 JB |
806 | pp &= ~POWER_TARGET_ON; |
807 | I915_WRITE(PCH_PP_CONTROL, pp); | |
9934c132 | 808 | |
481b6af3 | 809 | if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000)) |
913d8d11 CW |
810 | DRM_ERROR("panel off wait timed out: 0x%08x\n", |
811 | I915_READ(PCH_PP_STATUS)); | |
9934c132 JB |
812 | |
813 | /* Make sure VDD is enabled so DP AUX will work */ | |
3969c9c9 | 814 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
9934c132 | 815 | I915_WRITE(PCH_PP_CONTROL, pp); |
37c6c9b0 | 816 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 JB |
817 | } |
818 | ||
b2094bba JB |
819 | static void ironlake_edp_panel_vdd_on(struct drm_device *dev) |
820 | { | |
821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
822 | u32 pp; | |
823 | ||
824 | pp = I915_READ(PCH_PP_CONTROL); | |
825 | pp |= EDP_FORCE_VDD; | |
826 | I915_WRITE(PCH_PP_CONTROL, pp); | |
827 | POSTING_READ(PCH_PP_CONTROL); | |
3ba5c569 | 828 | msleep(300); |
b2094bba JB |
829 | } |
830 | ||
831 | static void ironlake_edp_panel_vdd_off(struct drm_device *dev) | |
832 | { | |
833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
834 | u32 pp; | |
835 | ||
836 | pp = I915_READ(PCH_PP_CONTROL); | |
837 | pp &= ~EDP_FORCE_VDD; | |
838 | I915_WRITE(PCH_PP_CONTROL, pp); | |
839 | POSTING_READ(PCH_PP_CONTROL); | |
3ba5c569 | 840 | msleep(300); |
b2094bba JB |
841 | } |
842 | ||
f2b115e6 | 843 | static void ironlake_edp_backlight_on (struct drm_device *dev) |
32f9d658 ZW |
844 | { |
845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
846 | u32 pp; | |
847 | ||
28c97730 | 848 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
849 | pp = I915_READ(PCH_PP_CONTROL); |
850 | pp |= EDP_BLC_ENABLE; | |
851 | I915_WRITE(PCH_PP_CONTROL, pp); | |
852 | } | |
853 | ||
f2b115e6 | 854 | static void ironlake_edp_backlight_off (struct drm_device *dev) |
32f9d658 ZW |
855 | { |
856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
857 | u32 pp; | |
858 | ||
28c97730 | 859 | DRM_DEBUG_KMS("\n"); |
32f9d658 ZW |
860 | pp = I915_READ(PCH_PP_CONTROL); |
861 | pp &= ~EDP_BLC_ENABLE; | |
862 | I915_WRITE(PCH_PP_CONTROL, pp); | |
863 | } | |
a4fc5ed6 | 864 | |
d240f20f JB |
865 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
866 | { | |
867 | struct drm_device *dev = encoder->dev; | |
868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
869 | u32 dpa_ctl; | |
870 | ||
871 | DRM_DEBUG_KMS("\n"); | |
872 | dpa_ctl = I915_READ(DP_A); | |
873 | dpa_ctl &= ~DP_PLL_ENABLE; | |
874 | I915_WRITE(DP_A, dpa_ctl); | |
875 | } | |
876 | ||
877 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
878 | { | |
879 | struct drm_device *dev = encoder->dev; | |
880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
881 | u32 dpa_ctl; | |
882 | ||
883 | dpa_ctl = I915_READ(DP_A); | |
884 | dpa_ctl |= DP_PLL_ENABLE; | |
885 | I915_WRITE(DP_A, dpa_ctl); | |
886 | udelay(200); | |
887 | } | |
888 | ||
889 | static void intel_dp_prepare(struct drm_encoder *encoder) | |
890 | { | |
891 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
892 | struct drm_device *dev = encoder->dev; | |
893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
894 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
895 | ||
7eaf5547 | 896 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
2c9d9754 | 897 | ironlake_edp_panel_off(dev); |
d240f20f | 898 | ironlake_edp_backlight_off(dev); |
b2094bba | 899 | ironlake_edp_panel_vdd_on(dev); |
d240f20f JB |
900 | ironlake_edp_pll_on(encoder); |
901 | } | |
902 | if (dp_reg & DP_PORT_EN) | |
903 | intel_dp_link_down(intel_dp); | |
904 | } | |
905 | ||
906 | static void intel_dp_commit(struct drm_encoder *encoder) | |
907 | { | |
908 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
909 | struct drm_device *dev = encoder->dev; | |
d240f20f | 910 | |
33a34e4e JB |
911 | intel_dp_start_link_train(intel_dp); |
912 | ||
913 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
b2094bba | 914 | ironlake_edp_panel_on(dev); |
33a34e4e JB |
915 | |
916 | intel_dp_complete_link_train(intel_dp); | |
917 | ||
918 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
d240f20f JB |
919 | ironlake_edp_backlight_on(dev); |
920 | } | |
921 | ||
a4fc5ed6 KP |
922 | static void |
923 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
924 | { | |
ea5b213a | 925 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 926 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 927 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 928 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
929 | |
930 | if (mode != DRM_MODE_DPMS_ON) { | |
7643a7fa JB |
931 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
932 | ironlake_edp_backlight_off(dev); | |
933 | ironlake_edp_panel_off(dev); | |
32f9d658 | 934 | } |
7643a7fa JB |
935 | if (dp_reg & DP_PORT_EN) |
936 | intel_dp_link_down(intel_dp); | |
d240f20f JB |
937 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
938 | ironlake_edp_pll_off(encoder); | |
a4fc5ed6 | 939 | } else { |
32f9d658 | 940 | if (!(dp_reg & DP_PORT_EN)) { |
33a34e4e | 941 | intel_dp_start_link_train(intel_dp); |
7643a7fa | 942 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
9934c132 | 943 | ironlake_edp_panel_on(dev); |
33a34e4e | 944 | intel_dp_complete_link_train(intel_dp); |
7643a7fa | 945 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
f2b115e6 | 946 | ironlake_edp_backlight_on(dev); |
32f9d658 | 947 | } |
a4fc5ed6 | 948 | } |
ea5b213a | 949 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
950 | } |
951 | ||
952 | /* | |
953 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
954 | * link status information | |
955 | */ | |
956 | static bool | |
33a34e4e | 957 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
958 | { |
959 | int ret; | |
960 | ||
ea5b213a | 961 | ret = intel_dp_aux_native_read(intel_dp, |
a4fc5ed6 | 962 | DP_LANE0_1_STATUS, |
33a34e4e | 963 | intel_dp->link_status, DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
964 | if (ret != DP_LINK_STATUS_SIZE) |
965 | return false; | |
966 | return true; | |
967 | } | |
968 | ||
969 | static uint8_t | |
970 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
971 | int r) | |
972 | { | |
973 | return link_status[r - DP_LANE0_1_STATUS]; | |
974 | } | |
975 | ||
a4fc5ed6 KP |
976 | static uint8_t |
977 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
978 | int lane) | |
979 | { | |
980 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
981 | int s = ((lane & 1) ? | |
982 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
983 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
984 | uint8_t l = intel_dp_link_status(link_status, i); | |
985 | ||
986 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
987 | } | |
988 | ||
989 | static uint8_t | |
990 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
991 | int lane) | |
992 | { | |
993 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
994 | int s = ((lane & 1) ? | |
995 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
996 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
997 | uint8_t l = intel_dp_link_status(link_status, i); | |
998 | ||
999 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1000 | } | |
1001 | ||
1002 | ||
1003 | #if 0 | |
1004 | static char *voltage_names[] = { | |
1005 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1006 | }; | |
1007 | static char *pre_emph_names[] = { | |
1008 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1009 | }; | |
1010 | static char *link_train_names[] = { | |
1011 | "pattern 1", "pattern 2", "idle", "off" | |
1012 | }; | |
1013 | #endif | |
1014 | ||
1015 | /* | |
1016 | * These are source-specific values; current Intel hardware supports | |
1017 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1018 | */ | |
1019 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1020 | ||
1021 | static uint8_t | |
1022 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1023 | { | |
1024 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1025 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1026 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1027 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1028 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1029 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1030 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1031 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1032 | default: | |
1033 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | static void | |
33a34e4e | 1038 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1039 | { |
1040 | uint8_t v = 0; | |
1041 | uint8_t p = 0; | |
1042 | int lane; | |
1043 | ||
33a34e4e JB |
1044 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1045 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1046 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1047 | |
1048 | if (this_v > v) | |
1049 | v = this_v; | |
1050 | if (this_p > p) | |
1051 | p = this_p; | |
1052 | } | |
1053 | ||
1054 | if (v >= I830_DP_VOLTAGE_MAX) | |
1055 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1056 | ||
1057 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1058 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1059 | ||
1060 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1061 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1062 | } |
1063 | ||
1064 | static uint32_t | |
1065 | intel_dp_signal_levels(uint8_t train_set, int lane_count) | |
1066 | { | |
1067 | uint32_t signal_levels = 0; | |
1068 | ||
1069 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1070 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1071 | default: | |
1072 | signal_levels |= DP_VOLTAGE_0_4; | |
1073 | break; | |
1074 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1075 | signal_levels |= DP_VOLTAGE_0_6; | |
1076 | break; | |
1077 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1078 | signal_levels |= DP_VOLTAGE_0_8; | |
1079 | break; | |
1080 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1081 | signal_levels |= DP_VOLTAGE_1_2; | |
1082 | break; | |
1083 | } | |
1084 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
1085 | case DP_TRAIN_PRE_EMPHASIS_0: | |
1086 | default: | |
1087 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1088 | break; | |
1089 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1090 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1091 | break; | |
1092 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1093 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1094 | break; | |
1095 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1096 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1097 | break; | |
1098 | } | |
1099 | return signal_levels; | |
1100 | } | |
1101 | ||
e3421a18 ZW |
1102 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1103 | static uint32_t | |
1104 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1105 | { | |
1106 | switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) { | |
1107 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
1108 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1109 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
1110 | return EDP_LINK_TRAIN_400MV_6DB_SNB_B; | |
1111 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1112 | return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B; | |
1113 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
1114 | return EDP_LINK_TRAIN_800MV_0DB_SNB_B; | |
1115 | default: | |
1116 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n"); | |
1117 | return EDP_LINK_TRAIN_400MV_0DB_SNB_B; | |
1118 | } | |
1119 | } | |
1120 | ||
a4fc5ed6 KP |
1121 | static uint8_t |
1122 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1123 | int lane) | |
1124 | { | |
1125 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1126 | int s = (lane & 1) * 4; | |
1127 | uint8_t l = intel_dp_link_status(link_status, i); | |
1128 | ||
1129 | return (l >> s) & 0xf; | |
1130 | } | |
1131 | ||
1132 | /* Check for clock recovery is done on all channels */ | |
1133 | static bool | |
1134 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1135 | { | |
1136 | int lane; | |
1137 | uint8_t lane_status; | |
1138 | ||
1139 | for (lane = 0; lane < lane_count; lane++) { | |
1140 | lane_status = intel_get_lane_status(link_status, lane); | |
1141 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1142 | return false; | |
1143 | } | |
1144 | return true; | |
1145 | } | |
1146 | ||
1147 | /* Check to see if channel eq is done on all channels */ | |
1148 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1149 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1150 | DP_LANE_SYMBOL_LOCKED) | |
1151 | static bool | |
33a34e4e | 1152 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1153 | { |
1154 | uint8_t lane_align; | |
1155 | uint8_t lane_status; | |
1156 | int lane; | |
1157 | ||
33a34e4e | 1158 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1159 | DP_LANE_ALIGN_STATUS_UPDATED); |
1160 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1161 | return false; | |
33a34e4e JB |
1162 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1163 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1164 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1165 | return false; | |
1166 | } | |
1167 | return true; | |
1168 | } | |
1169 | ||
1170 | static bool | |
ea5b213a | 1171 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
1172 | uint32_t dp_reg_value, |
1173 | uint8_t dp_train_pat, | |
a4fc5ed6 KP |
1174 | bool first) |
1175 | { | |
ea5b213a | 1176 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1177 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d0498a2 | 1178 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc); |
a4fc5ed6 KP |
1179 | int ret; |
1180 | ||
ea5b213a CW |
1181 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1182 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1183 | if (first) |
9d0498a2 | 1184 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
a4fc5ed6 | 1185 | |
ea5b213a | 1186 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1187 | DP_TRAINING_PATTERN_SET, |
1188 | dp_train_pat); | |
1189 | ||
ea5b213a | 1190 | ret = intel_dp_aux_native_write(intel_dp, |
33a34e4e | 1191 | DP_TRAINING_LANE0_SET, intel_dp->train_set, 4); |
a4fc5ed6 KP |
1192 | if (ret != 4) |
1193 | return false; | |
1194 | ||
1195 | return true; | |
1196 | } | |
1197 | ||
33a34e4e | 1198 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1199 | static void |
33a34e4e | 1200 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1201 | { |
ea5b213a | 1202 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 KP |
1203 | int i; |
1204 | uint8_t voltage; | |
1205 | bool clock_recovery = false; | |
a4fc5ed6 KP |
1206 | bool first = true; |
1207 | int tries; | |
e3421a18 | 1208 | u32 reg; |
ea5b213a | 1209 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 KP |
1210 | |
1211 | /* Write the link configuration data */ | |
ea5b213a CW |
1212 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
1213 | intel_dp->link_configuration, | |
1214 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1215 | |
1216 | DP |= DP_PORT_EN; | |
ea5b213a | 1217 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1218 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1219 | else | |
1220 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1221 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1222 | voltage = 0xff; |
1223 | tries = 0; | |
1224 | clock_recovery = false; | |
1225 | for (;;) { | |
33a34e4e | 1226 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1227 | uint32_t signal_levels; |
ea5b213a | 1228 | if (IS_GEN6(dev) && IS_eDP(intel_dp)) { |
33a34e4e | 1229 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1230 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1231 | } else { | |
33a34e4e | 1232 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1233 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1234 | } | |
a4fc5ed6 | 1235 | |
ea5b213a | 1236 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1237 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1238 | else | |
1239 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1240 | ||
ea5b213a | 1241 | if (!intel_dp_set_link_train(intel_dp, reg, |
33a34e4e | 1242 | DP_TRAINING_PATTERN_1, first)) |
a4fc5ed6 KP |
1243 | break; |
1244 | first = false; | |
1245 | /* Set training pattern 1 */ | |
1246 | ||
1247 | udelay(100); | |
33a34e4e | 1248 | if (!intel_dp_get_link_status(intel_dp)) |
a4fc5ed6 KP |
1249 | break; |
1250 | ||
33a34e4e | 1251 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
a4fc5ed6 KP |
1252 | clock_recovery = true; |
1253 | break; | |
1254 | } | |
1255 | ||
1256 | /* Check to see if we've tried the max voltage */ | |
ea5b213a | 1257 | for (i = 0; i < intel_dp->lane_count; i++) |
33a34e4e | 1258 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
a4fc5ed6 | 1259 | break; |
ea5b213a | 1260 | if (i == intel_dp->lane_count) |
a4fc5ed6 KP |
1261 | break; |
1262 | ||
1263 | /* Check to see if we've tried the same voltage 5 times */ | |
33a34e4e | 1264 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
a4fc5ed6 KP |
1265 | ++tries; |
1266 | if (tries == 5) | |
1267 | break; | |
1268 | } else | |
1269 | tries = 0; | |
33a34e4e | 1270 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
a4fc5ed6 | 1271 | |
33a34e4e JB |
1272 | /* Compute new intel_dp->train_set as requested by target */ |
1273 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1274 | } |
1275 | ||
33a34e4e JB |
1276 | intel_dp->DP = DP; |
1277 | } | |
1278 | ||
1279 | static void | |
1280 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1281 | { | |
1282 | struct drm_device *dev = intel_dp->base.enc.dev; | |
1283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1284 | bool channel_eq = false; | |
1285 | int tries; | |
1286 | u32 reg; | |
1287 | uint32_t DP = intel_dp->DP; | |
1288 | ||
a4fc5ed6 KP |
1289 | /* channel equalization */ |
1290 | tries = 0; | |
1291 | channel_eq = false; | |
1292 | for (;;) { | |
33a34e4e | 1293 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1294 | uint32_t signal_levels; |
1295 | ||
ea5b213a | 1296 | if (IS_GEN6(dev) && IS_eDP(intel_dp)) { |
33a34e4e | 1297 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1298 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1299 | } else { | |
33a34e4e | 1300 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1301 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1302 | } | |
1303 | ||
ea5b213a | 1304 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1305 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1306 | else | |
1307 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1308 | |
1309 | /* channel eq pattern */ | |
ea5b213a | 1310 | if (!intel_dp_set_link_train(intel_dp, reg, |
33a34e4e | 1311 | DP_TRAINING_PATTERN_2, |
a4fc5ed6 KP |
1312 | false)) |
1313 | break; | |
1314 | ||
1315 | udelay(400); | |
33a34e4e | 1316 | if (!intel_dp_get_link_status(intel_dp)) |
a4fc5ed6 KP |
1317 | break; |
1318 | ||
33a34e4e | 1319 | if (intel_channel_eq_ok(intel_dp)) { |
a4fc5ed6 KP |
1320 | channel_eq = true; |
1321 | break; | |
1322 | } | |
1323 | ||
1324 | /* Try 5 times */ | |
1325 | if (tries > 5) | |
1326 | break; | |
1327 | ||
33a34e4e JB |
1328 | /* Compute new intel_dp->train_set as requested by target */ |
1329 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1330 | ++tries; |
1331 | } | |
1332 | ||
ea5b213a | 1333 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) |
e3421a18 ZW |
1334 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1335 | else | |
1336 | reg = DP | DP_LINK_TRAIN_OFF; | |
1337 | ||
ea5b213a CW |
1338 | I915_WRITE(intel_dp->output_reg, reg); |
1339 | POSTING_READ(intel_dp->output_reg); | |
1340 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1341 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1342 | } | |
1343 | ||
1344 | static void | |
ea5b213a | 1345 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1346 | { |
ea5b213a | 1347 | struct drm_device *dev = intel_dp->base.enc.dev; |
a4fc5ed6 | 1348 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1349 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1350 | |
28c97730 | 1351 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1352 | |
ea5b213a | 1353 | if (IS_eDP(intel_dp)) { |
32f9d658 | 1354 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1355 | I915_WRITE(intel_dp->output_reg, DP); |
1356 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1357 | udelay(100); |
1358 | } | |
1359 | ||
ea5b213a | 1360 | if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) { |
e3421a18 | 1361 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a CW |
1362 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
1363 | POSTING_READ(intel_dp->output_reg); | |
e3421a18 ZW |
1364 | } else { |
1365 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a CW |
1366 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
1367 | POSTING_READ(intel_dp->output_reg); | |
e3421a18 | 1368 | } |
5eb08b69 ZW |
1369 | |
1370 | udelay(17000); | |
1371 | ||
ea5b213a | 1372 | if (IS_eDP(intel_dp)) |
32f9d658 | 1373 | DP |= DP_LINK_TRAIN_OFF; |
ea5b213a CW |
1374 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1375 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 KP |
1376 | } |
1377 | ||
a4fc5ed6 KP |
1378 | /* |
1379 | * According to DP spec | |
1380 | * 5.1.2: | |
1381 | * 1. Read DPCD | |
1382 | * 2. Configure link according to Receiver Capabilities | |
1383 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1384 | * 4. Check link status on receipt of hot-plug interrupt | |
1385 | */ | |
1386 | ||
1387 | static void | |
ea5b213a | 1388 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1389 | { |
ea5b213a | 1390 | if (!intel_dp->base.enc.crtc) |
a4fc5ed6 KP |
1391 | return; |
1392 | ||
33a34e4e | 1393 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1394 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1395 | return; |
1396 | } | |
1397 | ||
33a34e4e JB |
1398 | if (!intel_channel_eq_ok(intel_dp)) { |
1399 | intel_dp_start_link_train(intel_dp); | |
1400 | intel_dp_complete_link_train(intel_dp); | |
1401 | } | |
a4fc5ed6 | 1402 | } |
a4fc5ed6 | 1403 | |
5eb08b69 | 1404 | static enum drm_connector_status |
f2b115e6 | 1405 | ironlake_dp_detect(struct drm_connector *connector) |
5eb08b69 | 1406 | { |
55f78c43 | 1407 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a | 1408 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5eb08b69 ZW |
1409 | enum drm_connector_status status; |
1410 | ||
7eaf5547 JB |
1411 | /* Panel needs power for AUX to work */ |
1412 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) | |
b2094bba | 1413 | ironlake_edp_panel_vdd_on(connector->dev); |
5eb08b69 | 1414 | status = connector_status_disconnected; |
ea5b213a CW |
1415 | if (intel_dp_aux_native_read(intel_dp, |
1416 | 0x000, intel_dp->dpcd, | |
1417 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
5eb08b69 | 1418 | { |
ea5b213a | 1419 | if (intel_dp->dpcd[0] != 0) |
5eb08b69 ZW |
1420 | status = connector_status_connected; |
1421 | } | |
ea5b213a CW |
1422 | DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0], |
1423 | intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]); | |
b2094bba JB |
1424 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) |
1425 | ironlake_edp_panel_vdd_off(connector->dev); | |
5eb08b69 ZW |
1426 | return status; |
1427 | } | |
1428 | ||
a4fc5ed6 KP |
1429 | /** |
1430 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1431 | * | |
1432 | * \return true if DP port is connected. | |
1433 | * \return false if DP port is disconnected. | |
1434 | */ | |
1435 | static enum drm_connector_status | |
1436 | intel_dp_detect(struct drm_connector *connector) | |
1437 | { | |
55f78c43 | 1438 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a CW |
1439 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1440 | struct drm_device *dev = intel_dp->base.enc.dev; | |
a4fc5ed6 | 1441 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1442 | uint32_t temp, bit; |
1443 | enum drm_connector_status status; | |
1444 | ||
ea5b213a | 1445 | intel_dp->has_audio = false; |
a4fc5ed6 | 1446 | |
c619eed4 | 1447 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1448 | return ironlake_dp_detect(connector); |
5eb08b69 | 1449 | |
ea5b213a | 1450 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1451 | case DP_B: |
1452 | bit = DPB_HOTPLUG_INT_STATUS; | |
1453 | break; | |
1454 | case DP_C: | |
1455 | bit = DPC_HOTPLUG_INT_STATUS; | |
1456 | break; | |
1457 | case DP_D: | |
1458 | bit = DPD_HOTPLUG_INT_STATUS; | |
1459 | break; | |
1460 | default: | |
1461 | return connector_status_unknown; | |
1462 | } | |
1463 | ||
1464 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1465 | ||
1466 | if ((temp & bit) == 0) | |
1467 | return connector_status_disconnected; | |
1468 | ||
1469 | status = connector_status_disconnected; | |
ea5b213a CW |
1470 | if (intel_dp_aux_native_read(intel_dp, |
1471 | 0x000, intel_dp->dpcd, | |
1472 | sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) | |
a4fc5ed6 | 1473 | { |
ea5b213a | 1474 | if (intel_dp->dpcd[0] != 0) |
a4fc5ed6 KP |
1475 | status = connector_status_connected; |
1476 | } | |
1477 | return status; | |
1478 | } | |
1479 | ||
1480 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1481 | { | |
55f78c43 | 1482 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
ea5b213a CW |
1483 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1484 | struct drm_device *dev = intel_dp->base.enc.dev; | |
32f9d658 ZW |
1485 | struct drm_i915_private *dev_priv = dev->dev_private; |
1486 | int ret; | |
a4fc5ed6 KP |
1487 | |
1488 | /* We should parse the EDID data and find out if it has an audio sink | |
1489 | */ | |
1490 | ||
ea5b213a | 1491 | ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus); |
b9efc480 | 1492 | if (ret) { |
ea5b213a | 1493 | if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) && |
b9efc480 ZY |
1494 | !dev_priv->panel_fixed_mode) { |
1495 | struct drm_display_mode *newmode; | |
1496 | list_for_each_entry(newmode, &connector->probed_modes, | |
1497 | head) { | |
1498 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
1499 | dev_priv->panel_fixed_mode = | |
1500 | drm_mode_duplicate(dev, newmode); | |
1501 | break; | |
1502 | } | |
1503 | } | |
1504 | } | |
1505 | ||
32f9d658 | 1506 | return ret; |
b9efc480 | 1507 | } |
32f9d658 ZW |
1508 | |
1509 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
ea5b213a | 1510 | if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) { |
32f9d658 ZW |
1511 | if (dev_priv->panel_fixed_mode != NULL) { |
1512 | struct drm_display_mode *mode; | |
1513 | mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode); | |
1514 | drm_mode_probed_add(connector, mode); | |
1515 | return 1; | |
1516 | } | |
1517 | } | |
1518 | return 0; | |
a4fc5ed6 KP |
1519 | } |
1520 | ||
1521 | static void | |
1522 | intel_dp_destroy (struct drm_connector *connector) | |
1523 | { | |
a4fc5ed6 KP |
1524 | drm_sysfs_connector_remove(connector); |
1525 | drm_connector_cleanup(connector); | |
55f78c43 | 1526 | kfree(connector); |
a4fc5ed6 KP |
1527 | } |
1528 | ||
24d05927 DV |
1529 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
1530 | { | |
1531 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1532 | ||
1533 | i2c_del_adapter(&intel_dp->adapter); | |
1534 | drm_encoder_cleanup(encoder); | |
1535 | kfree(intel_dp); | |
1536 | } | |
1537 | ||
a4fc5ed6 KP |
1538 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
1539 | .dpms = intel_dp_dpms, | |
1540 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 1541 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 1542 | .mode_set = intel_dp_mode_set, |
d240f20f | 1543 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
1544 | }; |
1545 | ||
1546 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
1547 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
1548 | .detect = intel_dp_detect, |
1549 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1550 | .destroy = intel_dp_destroy, | |
1551 | }; | |
1552 | ||
1553 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
1554 | .get_modes = intel_dp_get_modes, | |
1555 | .mode_valid = intel_dp_mode_valid, | |
55f78c43 | 1556 | .best_encoder = intel_attached_encoder, |
a4fc5ed6 KP |
1557 | }; |
1558 | ||
a4fc5ed6 | 1559 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 1560 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
1561 | }; |
1562 | ||
995b6762 | 1563 | static void |
21d40d37 | 1564 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 1565 | { |
ea5b213a | 1566 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 1567 | |
ea5b213a CW |
1568 | if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON) |
1569 | intel_dp_check_link_status(intel_dp); | |
c8110e52 | 1570 | } |
6207937d | 1571 | |
e3421a18 ZW |
1572 | /* Return which DP Port should be selected for Transcoder DP control */ |
1573 | int | |
1574 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
1575 | { | |
1576 | struct drm_device *dev = crtc->dev; | |
1577 | struct drm_mode_config *mode_config = &dev->mode_config; | |
1578 | struct drm_encoder *encoder; | |
e3421a18 ZW |
1579 | |
1580 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
1581 | struct intel_dp *intel_dp; |
1582 | ||
d8201ab6 | 1583 | if (encoder->crtc != crtc) |
e3421a18 ZW |
1584 | continue; |
1585 | ||
ea5b213a CW |
1586 | intel_dp = enc_to_intel_dp(encoder); |
1587 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
1588 | return intel_dp->output_reg; | |
e3421a18 | 1589 | } |
ea5b213a | 1590 | |
e3421a18 ZW |
1591 | return -1; |
1592 | } | |
1593 | ||
36e83a18 | 1594 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 1595 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
1596 | { |
1597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1598 | struct child_device_config *p_child; | |
1599 | int i; | |
1600 | ||
1601 | if (!dev_priv->child_dev_num) | |
1602 | return false; | |
1603 | ||
1604 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
1605 | p_child = dev_priv->child_dev + i; | |
1606 | ||
1607 | if (p_child->dvo_port == PORT_IDPD && | |
1608 | p_child->device_type == DEVICE_TYPE_eDP) | |
1609 | return true; | |
1610 | } | |
1611 | return false; | |
1612 | } | |
1613 | ||
a4fc5ed6 KP |
1614 | void |
1615 | intel_dp_init(struct drm_device *dev, int output_reg) | |
1616 | { | |
1617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1618 | struct drm_connector *connector; | |
ea5b213a | 1619 | struct intel_dp *intel_dp; |
21d40d37 | 1620 | struct intel_encoder *intel_encoder; |
55f78c43 | 1621 | struct intel_connector *intel_connector; |
5eb08b69 | 1622 | const char *name = NULL; |
b329530c | 1623 | int type; |
a4fc5ed6 | 1624 | |
ea5b213a CW |
1625 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
1626 | if (!intel_dp) | |
a4fc5ed6 KP |
1627 | return; |
1628 | ||
55f78c43 ZW |
1629 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
1630 | if (!intel_connector) { | |
ea5b213a | 1631 | kfree(intel_dp); |
55f78c43 ZW |
1632 | return; |
1633 | } | |
ea5b213a | 1634 | intel_encoder = &intel_dp->base; |
55f78c43 | 1635 | |
ea5b213a | 1636 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 1637 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 1638 | intel_dp->is_pch_edp = true; |
b329530c | 1639 | |
ea5b213a | 1640 | if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { |
b329530c AJ |
1641 | type = DRM_MODE_CONNECTOR_eDP; |
1642 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
1643 | } else { | |
1644 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
1645 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
1646 | } | |
1647 | ||
55f78c43 | 1648 | connector = &intel_connector->base; |
b329530c | 1649 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
1650 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
1651 | ||
eb1f8e4f DA |
1652 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
1653 | ||
652af9d7 | 1654 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 1655 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 1656 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 1657 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 1658 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 1659 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 1660 | |
ea5b213a | 1661 | if (IS_eDP(intel_dp)) |
21d40d37 | 1662 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
6251ec0a | 1663 | |
21d40d37 | 1664 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
1665 | connector->interlace_allowed = true; |
1666 | connector->doublescan_allowed = 0; | |
1667 | ||
ea5b213a CW |
1668 | intel_dp->output_reg = output_reg; |
1669 | intel_dp->has_audio = false; | |
1670 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
a4fc5ed6 | 1671 | |
21d40d37 | 1672 | drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs, |
a4fc5ed6 | 1673 | DRM_MODE_ENCODER_TMDS); |
21d40d37 | 1674 | drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs); |
a4fc5ed6 | 1675 | |
55f78c43 | 1676 | drm_mode_connector_attach_encoder(&intel_connector->base, |
21d40d37 | 1677 | &intel_encoder->enc); |
a4fc5ed6 KP |
1678 | drm_sysfs_connector_add(connector); |
1679 | ||
1680 | /* Set up the DDC bus. */ | |
5eb08b69 | 1681 | switch (output_reg) { |
32f9d658 ZW |
1682 | case DP_A: |
1683 | name = "DPDDC-A"; | |
1684 | break; | |
5eb08b69 ZW |
1685 | case DP_B: |
1686 | case PCH_DP_B: | |
b01f2c3a JB |
1687 | dev_priv->hotplug_supported_mask |= |
1688 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1689 | name = "DPDDC-B"; |
1690 | break; | |
1691 | case DP_C: | |
1692 | case PCH_DP_C: | |
b01f2c3a JB |
1693 | dev_priv->hotplug_supported_mask |= |
1694 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1695 | name = "DPDDC-C"; |
1696 | break; | |
1697 | case DP_D: | |
1698 | case PCH_DP_D: | |
b01f2c3a JB |
1699 | dev_priv->hotplug_supported_mask |= |
1700 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
1701 | name = "DPDDC-D"; |
1702 | break; | |
1703 | } | |
1704 | ||
ea5b213a | 1705 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
32f9d658 | 1706 | |
ea5b213a | 1707 | intel_encoder->ddc_bus = &intel_dp->adapter; |
21d40d37 | 1708 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 1709 | |
ea5b213a | 1710 | if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) { |
32f9d658 ZW |
1711 | /* initialize panel mode from VBT if available for eDP */ |
1712 | if (dev_priv->lfp_lvds_vbt_mode) { | |
1713 | dev_priv->panel_fixed_mode = | |
1714 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); | |
1715 | if (dev_priv->panel_fixed_mode) { | |
1716 | dev_priv->panel_fixed_mode->type |= | |
1717 | DRM_MODE_TYPE_PREFERRED; | |
1718 | } | |
1719 | } | |
1720 | } | |
1721 | ||
a4fc5ed6 KP |
1722 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
1723 | * 0xd. Failure to do so will result in spurious interrupts being | |
1724 | * generated on the port when a cable is not attached. | |
1725 | */ | |
1726 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1727 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1728 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1729 | } | |
1730 | } |