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drm/i915: refactor ilk display interrupt handling
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 94
a4fc5ed6 95static int
ea5b213a 96intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 97{
7183dc29 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
d4eead50
ID		 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
a4fc5ed6 107 default:
d4eead50
ID		 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
a4fc5ed6
KP		 110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
cd9dde44
AJ		 116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
a4fc5ed6 133static int
c898261c 134intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 135{
cd9dde44 136 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 137}
138
fe27d53e
DA		 139static int
140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
a4fc5ed6
KP		 145static int
146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
df0e9248 149 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 154
dd06f90e
JN		 155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 157 return MODE_PANEL;
158
dd06f90e 159 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 160 return MODE_PANEL;
03afc4a2
DV		 161
162 target_clock = fixed_mode->clock;
7de56f43
ZY		 163 }
164
36008365
DV		 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
c4867936 172 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
0af78a2b
DV		 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
a4fc5ed6
KP		 180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
fb0f8fbf
KP		 206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
9473c8f4
VP		 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
fb0f8fbf
KP		 217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
bf13e81b
JN		 240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
ebf33b18
KP		 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
30add22d 299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 300 struct drm_i915_private *dev_priv = dev->dev_private;
301
bf13e81b 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 311}
312
9b984dae
KP		 313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
30add22d 316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 317 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 318
9b984dae
KP		 319 if (!is_edp(intel_dp))
320 return;
453c5420 321
ebf33b18 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 327 }
328}
329
9ee32fea
DV		 330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 337 uint32_t status;
338 bool done;
339
ef04f00d 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 341 if (has_aux_irq)
b18ac466 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 343 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
bc86625a
CW		 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
a4fc5ed6 356{
174edf1f
PZ		 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 359 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 360
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
a62d0834 368 if (IS_VALLEYVIEW(dev)) {
bc86625a 369 return index ? 0 : 100;
a62d0834 370 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 371 if (index)
372 return 0;
affa9354 373 if (HAS_DDI(dev))
bc86625a 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 375 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 377 else
b84a1cf8 378 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
bc86625a
CW		 381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
2c55c336 386 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 388 } else {
bc86625a 389 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 390 }
b84a1cf8
RV		 391}
392
393static int
394intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
bc86625a 403 uint32_t aux_clock_divider;
b84a1cf8
RV		 404 int i, ret, recv_bytes;
405 uint32_t status;
bc86625a 406 int try, precharge, clock = 0;
b84a1cf8
RV		 407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
408
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
411 * deep sleep states.
412 */
413 pm_qos_update_request(&dev_priv->pm_qos, 0);
414
415 intel_dp_check_edp(intel_dp);
5eb08b69 416
6b4e0a93
DV		 417 if (IS_GEN6(dev))
418 precharge = 3;
419 else
420 precharge = 5;
421
c67a470b
PZ		 422 intel_aux_display_runtime_get(dev_priv);
423
11bee43e
JB		 424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
ef04f00d 426 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
428 break;
429 msleep(1);
430 }
431
432 if (try == 3) {
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
434 I915_READ(ch_ctl));
9ee32fea
DV		 435 ret = -EBUSY;
436 goto out;
4f7f7b7e
CW		 437 }
438
46a5ae9f
PZ		 439 /* Only 5 data registers! */
440 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
441 ret = -E2BIG;
442 goto out;
443 }
444
bc86625a
CW		 445 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
446 /* Must try at least 3 times according to DP spec */
447 for (try = 0; try < 5; try++) {
448 /* Load the send data into the aux channel data registers */
449 for (i = 0; i < send_bytes; i += 4)
450 I915_WRITE(ch_data + i,
451 pack_aux(send + i, send_bytes - i));
452
453 /* Send the command and wait for it to complete */
454 I915_WRITE(ch_ctl,
455 DP_AUX_CH_CTL_SEND_BUSY |
456 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
457 DP_AUX_CH_CTL_TIME_OUT_400us |
458 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
459 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
460 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
461 DP_AUX_CH_CTL_DONE |
462 DP_AUX_CH_CTL_TIME_OUT_ERROR |
463 DP_AUX_CH_CTL_RECEIVE_ERROR);
464
465 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
466
467 /* Clear done status and any errors */
468 I915_WRITE(ch_ctl,
469 status |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
473
474 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
475 DP_AUX_CH_CTL_RECEIVE_ERROR))
476 continue;
477 if (status & DP_AUX_CH_CTL_DONE)
478 break;
479 }
4f7f7b7e 480 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 481 break;
482 }
483
a4fc5ed6 484 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 485 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 486 ret = -EBUSY;
487 goto out;
a4fc5ed6
KP		 488 }
489
490 /* Check for timeout or receive error.
491 * Timeouts occur when the sink is not connected
492 */
a5b3da54 493 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 494 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 495 ret = -EIO;
496 goto out;
a5b3da54 497 }
1ae8c0a5
KP		 498
499 /* Timeouts occur when the device isn't connected, so they're
500 * "normal" -- don't fill the kernel log with these */
a5b3da54 501 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 502 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 503 ret = -ETIMEDOUT;
504 goto out;
a4fc5ed6
KP		 505 }
506
507 /* Unload any bytes sent back from the other side */
508 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
509 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 510 if (recv_bytes > recv_size)
511 recv_bytes = recv_size;
0206e353 512
4f7f7b7e
CW		 513 for (i = 0; i < recv_bytes; i += 4)
514 unpack_aux(I915_READ(ch_data + i),
515 recv + i, recv_bytes - i);
a4fc5ed6 516
9ee32fea
DV		 517 ret = recv_bytes;
518out:
519 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 520 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 521
522 return ret;
a4fc5ed6
KP		 523}
524
525/* Write data to the aux channel in native mode */
526static int
ea5b213a 527intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 528 uint16_t address, uint8_t *send, int send_bytes)
529{
530 int ret;
531 uint8_t msg[20];
532 int msg_bytes;
533 uint8_t ack;
534
46a5ae9f
PZ		 535 if (WARN_ON(send_bytes > 16))
536 return -E2BIG;
537
9b984dae 538 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 539 msg[0] = AUX_NATIVE_WRITE << 4;
540 msg[1] = address >> 8;
eebc863e 541 msg[2] = address & 0xff;
a4fc5ed6
KP		 542 msg[3] = send_bytes - 1;
543 memcpy(&msg[4], send, send_bytes);
544 msg_bytes = send_bytes + 4;
545 for (;;) {
ea5b213a 546 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 547 if (ret < 0)
548 return ret;
549 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
550 break;
551 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
552 udelay(100);
553 else
a5b3da54 554 return -EIO;
a4fc5ed6
KP		 555 }
556 return send_bytes;
557}
558
559/* Write a single byte to the aux channel in native mode */
560static int
ea5b213a 561intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 562 uint16_t address, uint8_t byte)
563{
ea5b213a 564 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 565}
566
567/* read bytes from a native aux channel */
568static int
ea5b213a 569intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 570 uint16_t address, uint8_t *recv, int recv_bytes)
571{
572 uint8_t msg[4];
573 int msg_bytes;
574 uint8_t reply[20];
575 int reply_bytes;
576 uint8_t ack;
577 int ret;
578
46a5ae9f
PZ		 579 if (WARN_ON(recv_bytes > 19))
580 return -E2BIG;
581
9b984dae 582 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 583 msg[0] = AUX_NATIVE_READ << 4;
584 msg[1] = address >> 8;
585 msg[2] = address & 0xff;
586 msg[3] = recv_bytes - 1;
587
588 msg_bytes = 4;
589 reply_bytes = recv_bytes + 1;
590
591 for (;;) {
ea5b213a 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 593 reply, reply_bytes);
a5b3da54
KP		 594 if (ret == 0)
595 return -EPROTO;
596 if (ret < 0)
a4fc5ed6
KP		 597 return ret;
598 ack = reply[0];
599 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
600 memcpy(recv, reply + 1, ret - 1);
601 return ret - 1;
602 }
603 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
604 udelay(100);
605 else
a5b3da54 606 return -EIO;
a4fc5ed6
KP		 607 }
608}
609
610static int
ab2c0672
DA		 611intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
612 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 613{
ab2c0672 614 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 615 struct intel_dp *intel_dp = container_of(adapter,
616 struct intel_dp,
617 adapter);
ab2c0672
DA		 618 uint16_t address = algo_data->address;
619 uint8_t msg[5];
620 uint8_t reply[2];
8316f337 621 unsigned retry;
ab2c0672
DA		 622 int msg_bytes;
623 int reply_bytes;
624 int ret;
625
9b984dae 626 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 627 /* Set up the command byte */
628 if (mode & MODE_I2C_READ)
629 msg[0] = AUX_I2C_READ << 4;
630 else
631 msg[0] = AUX_I2C_WRITE << 4;
632
633 if (!(mode & MODE_I2C_STOP))
634 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 635
ab2c0672
DA		 636 msg[1] = address >> 8;
637 msg[2] = address;
638
639 switch (mode) {
640 case MODE_I2C_WRITE:
641 msg[3] = 0;
642 msg[4] = write_byte;
643 msg_bytes = 5;
644 reply_bytes = 1;
645 break;
646 case MODE_I2C_READ:
647 msg[3] = 0;
648 msg_bytes = 4;
649 reply_bytes = 2;
650 break;
651 default:
652 msg_bytes = 3;
653 reply_bytes = 1;
654 break;
655 }
656
58c67ce9
JN		 657 /*
658 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
659 * required to retry at least seven times upon receiving AUX_DEFER
660 * before giving up the AUX transaction.
661 */
662 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 663 ret = intel_dp_aux_ch(intel_dp,
664 msg, msg_bytes,
665 reply, reply_bytes);
ab2c0672 666 if (ret < 0) {
3ff99164 667 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 668 return ret;
669 }
8316f337
DF		 670
671 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
672 case AUX_NATIVE_REPLY_ACK:
673 /* I2C-over-AUX Reply field is only valid
674 * when paired with AUX ACK.
675 */
676 break;
677 case AUX_NATIVE_REPLY_NACK:
678 DRM_DEBUG_KMS("aux_ch native nack\n");
679 return -EREMOTEIO;
680 case AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 681 /*
682 * For now, just give more slack to branch devices. We
683 * could check the DPCD for I2C bit rate capabilities,
684 * and if available, adjust the interval. We could also
685 * be more careful with DP-to-Legacy adapters where a
686 * long legacy cable may force very low I2C bit rates.
687 */
688 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
689 DP_DWN_STRM_PORT_PRESENT)
690 usleep_range(500, 600);
691 else
692 usleep_range(300, 400);
8316f337
DF		 693 continue;
694 default:
695 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
696 reply[0]);
697 return -EREMOTEIO;
698 }
699
ab2c0672
DA		 700 switch (reply[0] & AUX_I2C_REPLY_MASK) {
701 case AUX_I2C_REPLY_ACK:
702 if (mode == MODE_I2C_READ) {
703 *read_byte = reply[1];
704 }
705 return reply_bytes - 1;
706 case AUX_I2C_REPLY_NACK:
8316f337 707 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 708 return -EREMOTEIO;
709 case AUX_I2C_REPLY_DEFER:
8316f337 710 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 711 udelay(100);
712 break;
713 default:
8316f337 714 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 715 return -EREMOTEIO;
716 }
717 }
8316f337
DF		 718
719 DRM_ERROR("too many retries, giving up\n");
720 return -EREMOTEIO;
a4fc5ed6
KP		 721}
722
723static int
ea5b213a 724intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 725 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 726{
0b5c541b
KP		 727 int ret;
728
d54e9d28 729 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 730 intel_dp->algo.running = false;
731 intel_dp->algo.address = 0;
732 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
733
0206e353 734 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 735 intel_dp->adapter.owner = THIS_MODULE;
736 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 737 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 738 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
739 intel_dp->adapter.algo_data = &intel_dp->algo;
740 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
741
0b5c541b
KP		 742 ironlake_edp_panel_vdd_on(intel_dp);
743 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 744 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 745 return ret;
a4fc5ed6
KP		 746}
747
c6bb3538
DV		 748static void
749intel_dp_set_clock(struct intel_encoder *encoder,
750 struct intel_crtc_config *pipe_config, int link_bw)
751{
752 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 753 const struct dp_link_dpll *divisor = NULL;
754 int i, count = 0;
c6bb3538
DV		 755
756 if (IS_G4X(dev)) {
9dd4ffdf
CML		 757 divisor = gen4_dpll;
758 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 759 } else if (IS_HASWELL(dev)) {
760 /* Haswell has special-purpose DP DDI clocks. */
761 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 762 divisor = pch_dpll;
763 count = ARRAY_SIZE(pch_dpll);
c6bb3538 764 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 765 divisor = vlv_dpll;
766 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 767 }
9dd4ffdf
CML		 768
769 if (divisor && count) {
770 for (i = 0; i < count; i++) {
771 if (link_bw == divisor[i].link_bw) {
772 pipe_config->dpll = divisor[i].dpll;
773 pipe_config->clock_set = true;
774 break;
775 }
776 }
c6bb3538
DV		 777 }
778}
779
00c09d70 780bool
5bfe2ac0
DV		 781intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
a4fc5ed6 783{
5bfe2ac0 784 struct drm_device *dev = encoder->base.dev;
36008365 785 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 788 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 789 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 790 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 791 int lane_count, clock;
397fe157 792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 793 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 794 int bpp, mode_rate;
a4fc5ed6 795 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 796 int link_avail, link_clock;
a4fc5ed6 797
bc7d38a4 798 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 799 pipe_config->has_pch_encoder = true;
800
03afc4a2 801 pipe_config->has_dp_encoder = true;
a4fc5ed6 802
dd06f90e
JN		 803 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
804 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
805 adjusted_mode);
2dd24552
JB		 806 if (!HAS_PCH_SPLIT(dev))
807 intel_gmch_panel_fitting(intel_crtc, pipe_config,
808 intel_connector->panel.fitting_mode);
809 else
b074cec8
JB		 810 intel_pch_panel_fitting(intel_crtc, pipe_config,
811 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 812 }
813
cb1793ce 814 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 815 return false;
816
083f9560
DV		 817 DRM_DEBUG_KMS("DP link computation with max lane count %i "
818 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 819 max_lane_count, bws[max_clock],
820 adjusted_mode->crtc_clock);
083f9560 821
36008365
DV		 822 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
823 * bpc in between. */
3e7ca985 824 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 825 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
826 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 827 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
828 dev_priv->vbt.edp_bpp);
6da7f10d 829 bpp = dev_priv->vbt.edp_bpp;
7984211e 830 }
657445fe 831
36008365 832 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 833 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
834 bpp);
36008365
DV		 835
836 for (clock = 0; clock <= max_clock; clock++) {
837 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
838 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
839 link_avail = intel_dp_max_data_rate(link_clock,
840 lane_count);
841
842 if (mode_rate <= link_avail) {
843 goto found;
844 }
845 }
846 }
847 }
c4867936 848
36008365 849 return false;
3685a8f3 850
36008365 851found:
55bc60db
VS		 852 if (intel_dp->color_range_auto) {
853 /*
854 * See:
855 * CEA-861-E - 5.1 Default Encoding Parameters
856 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
857 */
18316c8c 858 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 859 intel_dp->color_range = DP_COLOR_RANGE_16_235;
860 else
861 intel_dp->color_range = 0;
862 }
863
3685a8f3 864 if (intel_dp->color_range)
50f3b016 865 pipe_config->limited_color_range = true;
a4fc5ed6 866
36008365
DV		 867 intel_dp->link_bw = bws[clock];
868 intel_dp->lane_count = lane_count;
657445fe 869 pipe_config->pipe_bpp = bpp;
ff9a6750 870 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 871
36008365
DV		 872 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
873 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 874 pipe_config->port_clock, bpp);
36008365
DV		 875 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
876 mode_rate, link_avail);
a4fc5ed6 877
03afc4a2 878 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 879 adjusted_mode->crtc_clock,
880 pipe_config->port_clock,
03afc4a2 881 &pipe_config->dp_m_n);
9d1a455b 882
c6bb3538
DV		 883 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
884
03afc4a2 885 return true;
a4fc5ed6
KP		 886}
887
7c62a164 888static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 889{
7c62a164
DV		 890 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
891 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
892 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 893 struct drm_i915_private *dev_priv = dev->dev_private;
894 u32 dpa_ctl;
895
ff9a6750 896 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 897 dpa_ctl = I915_READ(DP_A);
898 dpa_ctl &= ~DP_PLL_FREQ_MASK;
899
ff9a6750 900 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 901 /* For a long time we've carried around a ILK-DevA w/a for the
902 * 160MHz clock. If we're really unlucky, it's still required.
903 */
904 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 905 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 906 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 907 } else {
908 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 909 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 910 }
1ce17038 911
ea9b6006
DV		 912 I915_WRITE(DP_A, dpa_ctl);
913
914 POSTING_READ(DP_A);
915 udelay(500);
916}
917
b934223d 918static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 919{
b934223d 920 struct drm_device *dev = encoder->base.dev;
417e822d 921 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 922 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 923 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 924 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
925 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 926
417e822d 927 /*
1a2eb460 928 * There are four kinds of DP registers:
417e822d
KP		 929 *
930 * IBX PCH
1a2eb460
KP		 931 * SNB CPU
932 * IVB CPU
417e822d
KP		 933 * CPT PCH
934 *
935 * IBX PCH and CPU are the same for almost everything,
936 * except that the CPU DP PLL is configured in this
937 * register
938 *
939 * CPT PCH is quite different, having many bits moved
940 * to the TRANS_DP_CTL register instead. That
941 * configuration happens (oddly) in ironlake_pch_enable
942 */
9c9e7927 943
417e822d
KP		 944 /* Preserve the BIOS-computed detected bit. This is
945 * supposed to be read-only.
946 */
947 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 948
417e822d 949 /* Handle DP bits in common between all three register formats */
417e822d 950 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 951 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 952
e0dac65e
WF		 953 if (intel_dp->has_audio) {
954 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 955 pipe_name(crtc->pipe));
ea5b213a 956 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 957 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 958 }
247d89f6 959
417e822d 960 /* Split out the IBX/CPU vs CPT settings */
32f9d658 961
bc7d38a4 962 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 963 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
964 intel_dp->DP |= DP_SYNC_HS_HIGH;
965 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
966 intel_dp->DP |= DP_SYNC_VS_HIGH;
967 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
968
6aba5b6c 969 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 970 intel_dp->DP |= DP_ENHANCED_FRAMING;
971
7c62a164 972 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 973 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 974 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 975 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 976
977 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
978 intel_dp->DP |= DP_SYNC_HS_HIGH;
979 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
980 intel_dp->DP |= DP_SYNC_VS_HIGH;
981 intel_dp->DP |= DP_LINK_TRAIN_OFF;
982
6aba5b6c 983 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 984 intel_dp->DP |= DP_ENHANCED_FRAMING;
985
7c62a164 986 if (crtc->pipe == 1)
417e822d 987 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 988 } else {
989 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 990 }
ea9b6006 991
bc7d38a4 992 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 993 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 994}
995
99ea7127
KP		 996#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
997#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
998
999#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1000#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1001
1002#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1003#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1004
1005static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1006 u32 mask,
1007 u32 value)
bd943159 1008{
30add22d 1009 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1010 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1011 u32 pp_stat_reg, pp_ctrl_reg;
1012
bf13e81b
JN		 1013 pp_stat_reg = _pp_stat_reg(intel_dp);
1014 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1015
99ea7127 1016 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1017 mask, value,
1018 I915_READ(pp_stat_reg),
1019 I915_READ(pp_ctrl_reg));
32ce697c 1020
453c5420 1021 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1022 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1023 I915_READ(pp_stat_reg),
1024 I915_READ(pp_ctrl_reg));
32ce697c 1025 }
99ea7127 1026}
32ce697c 1027
99ea7127
KP		 1028static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1029{
1030 DRM_DEBUG_KMS("Wait for panel power on\n");
1031 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1032}
1033
99ea7127
KP		 1034static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1035{
1036 DRM_DEBUG_KMS("Wait for panel power off time\n");
1037 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1038}
1039
1040static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1041{
1042 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1043 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1044}
1045
1046
832dd3c1
KP		 1047/* Read the current pp_control value, unlocking the register if it
1048 * is locked
1049 */
1050
453c5420 1051static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1052{
453c5420
JB		 1053 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1054 struct drm_i915_private *dev_priv = dev->dev_private;
1055 u32 control;
832dd3c1 1056
bf13e81b 1057 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1058 control &= ~PANEL_UNLOCK_MASK;
1059 control |= PANEL_UNLOCK_REGS;
1060 return control;
bd943159
KP		 1061}
1062
82a4d9c0 1063void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1064{
30add22d 1065 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1066 struct drm_i915_private *dev_priv = dev->dev_private;
1067 u32 pp;
453c5420 1068 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1069
97af61f5
KP		 1070 if (!is_edp(intel_dp))
1071 return;
f01eca2e 1072 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1073
bd943159
KP		 1074 WARN(intel_dp->want_panel_vdd,
1075 "eDP VDD already requested on\n");
1076
1077 intel_dp->want_panel_vdd = true;
99ea7127 1078
bd943159
KP		 1079 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1080 DRM_DEBUG_KMS("eDP VDD already on\n");
1081 return;
1082 }
1083
99ea7127
KP		 1084 if (!ironlake_edp_have_panel_power(intel_dp))
1085 ironlake_wait_panel_power_cycle(intel_dp);
1086
453c5420 1087 pp = ironlake_get_pp_control(intel_dp);
5d613501 1088 pp |= EDP_FORCE_VDD;
ebf33b18 1089
bf13e81b
JN		 1090 pp_stat_reg = _pp_stat_reg(intel_dp);
1091 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1092
1093 I915_WRITE(pp_ctrl_reg, pp);
1094 POSTING_READ(pp_ctrl_reg);
1095 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1096 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1097 /*
1098 * If the panel wasn't on, delay before accessing aux channel
1099 */
1100 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1101 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1102 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1103 }
5d613501
JB		 1104}
1105
bd943159 1106static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1107{
30add22d 1108 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1109 struct drm_i915_private *dev_priv = dev->dev_private;
1110 u32 pp;
453c5420 1111 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1112
a0e99e68
DV		 1113 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1114
bd943159 1115 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1116 pp = ironlake_get_pp_control(intel_dp);
bd943159 1117 pp &= ~EDP_FORCE_VDD;
bd943159 1118
bf13e81b
JN		 1119 pp_stat_reg = _pp_ctrl_reg(intel_dp);
1120 pp_ctrl_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1121
1122 I915_WRITE(pp_ctrl_reg, pp);
1123 POSTING_READ(pp_ctrl_reg);
99ea7127 1124
453c5420
JB		 1125 /* Make sure sequencer is idle before allowing subsequent activity */
1126 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1127 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1128 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1129 }
1130}
5d613501 1131
bd943159
KP		 1132static void ironlake_panel_vdd_work(struct work_struct *__work)
1133{
1134 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1135 struct intel_dp, panel_vdd_work);
30add22d 1136 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1137
627f7675 1138 mutex_lock(&dev->mode_config.mutex);
bd943159 1139 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1140 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1141}
1142
82a4d9c0 1143void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1144{
97af61f5
KP		 1145 if (!is_edp(intel_dp))
1146 return;
5d613501 1147
bd943159
KP		 1148 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1149 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1150
bd943159
KP		 1151 intel_dp->want_panel_vdd = false;
1152
1153 if (sync) {
1154 ironlake_panel_vdd_off_sync(intel_dp);
1155 } else {
1156 /*
1157 * Queue the timer to fire a long
1158 * time from now (relative to the power down delay)
1159 * to keep the panel power up across a sequence of operations
1160 */
1161 schedule_delayed_work(&intel_dp->panel_vdd_work,
1162 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1163 }
5d613501
JB		 1164}
1165
82a4d9c0 1166void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1167{
30add22d 1168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1169 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1170 u32 pp;
453c5420 1171 u32 pp_ctrl_reg;
9934c132 1172
97af61f5 1173 if (!is_edp(intel_dp))
bd943159 1174 return;
99ea7127
KP		 1175
1176 DRM_DEBUG_KMS("Turn eDP power on\n");
1177
1178 if (ironlake_edp_have_panel_power(intel_dp)) {
1179 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1180 return;
99ea7127 1181 }
9934c132 1182
99ea7127 1183 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1184
bf13e81b 1185 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1186 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1187 if (IS_GEN5(dev)) {
1188 /* ILK workaround: disable reset around power sequence */
1189 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1190 I915_WRITE(pp_ctrl_reg, pp);
1191 POSTING_READ(pp_ctrl_reg);
05ce1a49 1192 }
37c6c9b0 1193
1c0ae80a 1194 pp |= POWER_TARGET_ON;
99ea7127
KP		 1195 if (!IS_GEN5(dev))
1196 pp |= PANEL_POWER_RESET;
1197
453c5420
JB		 1198 I915_WRITE(pp_ctrl_reg, pp);
1199 POSTING_READ(pp_ctrl_reg);
9934c132 1200
99ea7127 1201 ironlake_wait_panel_on(intel_dp);
9934c132 1202
05ce1a49
KP		 1203 if (IS_GEN5(dev)) {
1204 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1205 I915_WRITE(pp_ctrl_reg, pp);
1206 POSTING_READ(pp_ctrl_reg);
05ce1a49 1207 }
9934c132
JB		 1208}
1209
82a4d9c0 1210void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1211{
30add22d 1212 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1213 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1214 u32 pp;
453c5420 1215 u32 pp_ctrl_reg;
9934c132 1216
97af61f5
KP		 1217 if (!is_edp(intel_dp))
1218 return;
37c6c9b0 1219
99ea7127 1220 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1221
6cb49835 1222 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1223
453c5420 1224 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1225 /* We need to switch off panel power _and_ force vdd, for otherwise some
1226 * panels get very unhappy and cease to work. */
1227 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1228
bf13e81b 1229 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1230
1231 I915_WRITE(pp_ctrl_reg, pp);
1232 POSTING_READ(pp_ctrl_reg);
9934c132 1233
35a38556
DV		 1234 intel_dp->want_panel_vdd = false;
1235
99ea7127 1236 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1237}
1238
d6c50ff8 1239void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1240{
da63a9f2
PZ		 1241 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1242 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1243 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1244 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1245 u32 pp;
453c5420 1246 u32 pp_ctrl_reg;
32f9d658 1247
f01eca2e
KP		 1248 if (!is_edp(intel_dp))
1249 return;
1250
28c97730 1251 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1252 /*
1253 * If we enable the backlight right away following a panel power
1254 * on, we may see slight flicker as the panel syncs with the eDP
1255 * link. So delay a bit to make sure the image is solid before
1256 * allowing it to appear.
1257 */
f01eca2e 1258 msleep(intel_dp->backlight_on_delay);
453c5420 1259 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1260 pp |= EDP_BLC_ENABLE;
453c5420 1261
bf13e81b 1262 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1263
1264 I915_WRITE(pp_ctrl_reg, pp);
1265 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1266
1267 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1268}
1269
d6c50ff8 1270void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1271{
30add22d 1272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1273 struct drm_i915_private *dev_priv = dev->dev_private;
1274 u32 pp;
453c5420 1275 u32 pp_ctrl_reg;
32f9d658 1276
f01eca2e
KP		 1277 if (!is_edp(intel_dp))
1278 return;
1279
035aa3de
DV		 1280 intel_panel_disable_backlight(dev);
1281
28c97730 1282 DRM_DEBUG_KMS("\n");
453c5420 1283 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1284 pp &= ~EDP_BLC_ENABLE;
453c5420 1285
bf13e81b 1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1287
1288 I915_WRITE(pp_ctrl_reg, pp);
1289 POSTING_READ(pp_ctrl_reg);
f01eca2e 1290 msleep(intel_dp->backlight_off_delay);
32f9d658 1291}
a4fc5ed6 1292
2bd2ad64 1293static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1294{
da63a9f2
PZ		 1295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1296 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1297 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1298 struct drm_i915_private *dev_priv = dev->dev_private;
1299 u32 dpa_ctl;
1300
2bd2ad64
DV		 1301 assert_pipe_disabled(dev_priv,
1302 to_intel_crtc(crtc)->pipe);
1303
d240f20f
JB		 1304 DRM_DEBUG_KMS("\n");
1305 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1306 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1307 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1308
1309 /* We don't adjust intel_dp->DP while tearing down the link, to
1310 * facilitate link retraining (e.g. after hotplug). Hence clear all
1311 * enable bits here to ensure that we don't enable too much. */
1312 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1313 intel_dp->DP |= DP_PLL_ENABLE;
1314 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1315 POSTING_READ(DP_A);
1316 udelay(200);
d240f20f
JB		 1317}
1318
2bd2ad64 1319static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1320{
da63a9f2
PZ		 1321 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1322 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1323 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 u32 dpa_ctl;
1326
2bd2ad64
DV		 1327 assert_pipe_disabled(dev_priv,
1328 to_intel_crtc(crtc)->pipe);
1329
d240f20f 1330 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1331 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1332 "dp pll off, should be on\n");
1333 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1334
1335 /* We can't rely on the value tracked for the DP register in
1336 * intel_dp->DP because link_down must not change that (otherwise link
1337 * re-training will fail. */
298b0b39 1338 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1339 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1340 POSTING_READ(DP_A);
d240f20f
JB		 1341 udelay(200);
1342}
1343
c7ad3810 1344/* If the sink supports it, try to set the power state appropriately */
c19b0669 1345void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1346{
1347 int ret, i;
1348
1349 /* Should have a valid DPCD by this point */
1350 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1351 return;
1352
1353 if (mode != DRM_MODE_DPMS_ON) {
1354 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1355 DP_SET_POWER_D3);
1356 if (ret != 1)
1357 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1358 } else {
1359 /*
1360 * When turning on, we need to retry for 1ms to give the sink
1361 * time to wake up.
1362 */
1363 for (i = 0; i < 3; i++) {
1364 ret = intel_dp_aux_native_write_1(intel_dp,
1365 DP_SET_POWER,
1366 DP_SET_POWER_D0);
1367 if (ret == 1)
1368 break;
1369 msleep(1);
1370 }
1371 }
1372}
1373
19d8fe15
DV		 1374static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1375 enum pipe *pipe)
d240f20f 1376{
19d8fe15 1377 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1378 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1379 struct drm_device *dev = encoder->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 u32 tmp = I915_READ(intel_dp->output_reg);
1382
1383 if (!(tmp & DP_PORT_EN))
1384 return false;
1385
bc7d38a4 1386 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1387 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1388 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1389 *pipe = PORT_TO_PIPE(tmp);
1390 } else {
1391 u32 trans_sel;
1392 u32 trans_dp;
1393 int i;
1394
1395 switch (intel_dp->output_reg) {
1396 case PCH_DP_B:
1397 trans_sel = TRANS_DP_PORT_SEL_B;
1398 break;
1399 case PCH_DP_C:
1400 trans_sel = TRANS_DP_PORT_SEL_C;
1401 break;
1402 case PCH_DP_D:
1403 trans_sel = TRANS_DP_PORT_SEL_D;
1404 break;
1405 default:
1406 return true;
1407 }
1408
1409 for_each_pipe(i) {
1410 trans_dp = I915_READ(TRANS_DP_CTL(i));
1411 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1412 *pipe = i;
1413 return true;
1414 }
1415 }
19d8fe15 1416
4a0833ec
DV		 1417 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1418 intel_dp->output_reg);
1419 }
d240f20f 1420
19d8fe15
DV		 1421 return true;
1422}
d240f20f 1423
045ac3b5
JB		 1424static void intel_dp_get_config(struct intel_encoder *encoder,
1425 struct intel_crtc_config *pipe_config)
1426{
1427 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1428 u32 tmp, flags = 0;
63000ef6
XZ		 1429 struct drm_device *dev = encoder->base.dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 enum port port = dp_to_dig_port(intel_dp)->port;
1432 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1433 int dotclock;
045ac3b5 1434
63000ef6
XZ		 1435 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1436 tmp = I915_READ(intel_dp->output_reg);
1437 if (tmp & DP_SYNC_HS_HIGH)
1438 flags |= DRM_MODE_FLAG_PHSYNC;
1439 else
1440 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1441
63000ef6
XZ		 1442 if (tmp & DP_SYNC_VS_HIGH)
1443 flags |= DRM_MODE_FLAG_PVSYNC;
1444 else
1445 flags |= DRM_MODE_FLAG_NVSYNC;
1446 } else {
1447 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1448 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1449 flags |= DRM_MODE_FLAG_PHSYNC;
1450 else
1451 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1452
63000ef6
XZ		 1453 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1454 flags |= DRM_MODE_FLAG_PVSYNC;
1455 else
1456 flags |= DRM_MODE_FLAG_NVSYNC;
1457 }
045ac3b5
JB		 1458
1459 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1460
eb14cb74
VS		 1461 pipe_config->has_dp_encoder = true;
1462
1463 intel_dp_get_m_n(crtc, pipe_config);
1464
18442d08 1465 if (port == PORT_A) {
f1f644dc
JB		 1466 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1467 pipe_config->port_clock = 162000;
1468 else
1469 pipe_config->port_clock = 270000;
1470 }
18442d08
VS		 1471
1472 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1473 &pipe_config->dp_m_n);
1474
1475 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1476 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1477
241bfc38 1478 pipe_config->adjusted_mode.crtc_clock = dotclock;
045ac3b5
JB		 1479}
1480
a031d709 1481static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1482{
a031d709
RV		 1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484
1485 return dev_priv->psr.sink_support;
2293bb5c
SK		 1486}
1487
2b28bb1b
RV		 1488static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1489{
1490 struct drm_i915_private *dev_priv = dev->dev_private;
1491
18b5992c 1492 if (!HAS_PSR(dev))
2b28bb1b
RV		 1493 return false;
1494
18b5992c 1495 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1496}
1497
1498static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1499 struct edp_vsc_psr *vsc_psr)
1500{
1501 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1502 struct drm_device *dev = dig_port->base.base.dev;
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1505 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1506 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1507 uint32_t *data = (uint32_t *) vsc_psr;
1508 unsigned int i;
1509
1510 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1511 the video DIP being updated before program video DIP data buffer
1512 registers for DIP being updated. */
1513 I915_WRITE(ctl_reg, 0);
1514 POSTING_READ(ctl_reg);
1515
1516 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1517 if (i < sizeof(struct edp_vsc_psr))
1518 I915_WRITE(data_reg + i, *data++);
1519 else
1520 I915_WRITE(data_reg + i, 0);
1521 }
1522
1523 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1524 POSTING_READ(ctl_reg);
1525}
1526
1527static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1528{
1529 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1530 struct drm_i915_private *dev_priv = dev->dev_private;
1531 struct edp_vsc_psr psr_vsc;
1532
1533 if (intel_dp->psr_setup_done)
1534 return;
1535
1536 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1537 memset(&psr_vsc, 0, sizeof(psr_vsc));
1538 psr_vsc.sdp_header.HB0 = 0;
1539 psr_vsc.sdp_header.HB1 = 0x7;
1540 psr_vsc.sdp_header.HB2 = 0x2;
1541 psr_vsc.sdp_header.HB3 = 0x8;
1542 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1543
1544 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1545 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2b28bb1b
RV		 1546 EDP_PSR_DEBUG_MASK_HPD);
1547
1548 intel_dp->psr_setup_done = true;
1549}
1550
1551static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1552{
1553 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1554 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1555 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1556 int precharge = 0x3;
1557 int msg_size = 5; /* Header(4) + Message(1) */
1558
1559 /* Enable PSR in sink */
1560 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1561 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1562 DP_PSR_ENABLE &
1563 ~DP_PSR_MAIN_LINK_ACTIVE);
1564 else
1565 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1566 DP_PSR_ENABLE |
1567 DP_PSR_MAIN_LINK_ACTIVE);
1568
1569 /* Setup AUX registers */
18b5992c
BW		 1570 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1571 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1572 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1573 DP_AUX_CH_CTL_TIME_OUT_400us |
1574 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1575 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1576 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1577}
1578
1579static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1580{
1581 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1582 struct drm_i915_private *dev_priv = dev->dev_private;
1583 uint32_t max_sleep_time = 0x1f;
1584 uint32_t idle_frames = 1;
1585 uint32_t val = 0x0;
1586
1587 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1588 val |= EDP_PSR_LINK_STANDBY;
1589 val |= EDP_PSR_TP2_TP3_TIME_0us;
1590 val |= EDP_PSR_TP1_TIME_0us;
1591 val |= EDP_PSR_SKIP_AUX_EXIT;
1592 } else
1593 val |= EDP_PSR_LINK_DISABLE;
1594
18b5992c 1595 I915_WRITE(EDP_PSR_CTL(dev), val |
2b28bb1b
RV		 1596 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1597 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1598 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1599 EDP_PSR_ENABLE);
1600}
1601
3f51e471
RV		 1602static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1603{
1604 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1605 struct drm_device *dev = dig_port->base.base.dev;
1606 struct drm_i915_private *dev_priv = dev->dev_private;
1607 struct drm_crtc *crtc = dig_port->base.base.crtc;
1608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1609 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1610 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1611
a031d709
RV		 1612 dev_priv->psr.source_ok = false;
1613
18b5992c 1614 if (!HAS_PSR(dev)) {
3f51e471 1615 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1616 return false;
1617 }
1618
1619 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1620 (dig_port->port != PORT_A)) {
1621 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1622 return false;
1623 }
1624
105b7c11
RV		 1625 if (!i915_enable_psr) {
1626 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1627 return false;
1628 }
1629
cd234b0b
CW		 1630 crtc = dig_port->base.base.crtc;
1631 if (crtc == NULL) {
1632 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1633 return false;
1634 }
1635
1636 intel_crtc = to_intel_crtc(crtc);
20ddf665 1637 if (!intel_crtc_active(crtc)) {
3f51e471 1638 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1639 return false;
1640 }
1641
cd234b0b 1642 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1643 if (obj->tiling_mode != I915_TILING_X ||
1644 obj->fence_reg == I915_FENCE_REG_NONE) {
1645 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1646 return false;
1647 }
1648
1649 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1650 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1651 return false;
1652 }
1653
1654 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1655 S3D_ENABLE) {
1656 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1657 return false;
1658 }
1659
ca73b4f0 1660 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1661 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1662 return false;
1663 }
1664
a031d709 1665 dev_priv->psr.source_ok = true;
3f51e471
RV		 1666 return true;
1667}
1668
3d739d92 1669static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1670{
1671 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1672
3f51e471
RV		 1673 if (!intel_edp_psr_match_conditions(intel_dp) ||
1674 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1675 return;
1676
1677 /* Setup PSR once */
1678 intel_edp_psr_setup(intel_dp);
1679
1680 /* Enable PSR on the panel */
1681 intel_edp_psr_enable_sink(intel_dp);
1682
1683 /* Enable PSR on the host */
1684 intel_edp_psr_enable_source(intel_dp);
1685}
1686
3d739d92
RV		 1687void intel_edp_psr_enable(struct intel_dp *intel_dp)
1688{
1689 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1690
1691 if (intel_edp_psr_match_conditions(intel_dp) &&
1692 !intel_edp_is_psr_enabled(dev))
1693 intel_edp_psr_do_enable(intel_dp);
1694}
1695
2b28bb1b
RV		 1696void intel_edp_psr_disable(struct intel_dp *intel_dp)
1697{
1698 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700
1701 if (!intel_edp_is_psr_enabled(dev))
1702 return;
1703
18b5992c
BW		 1704 I915_WRITE(EDP_PSR_CTL(dev),
1705 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1706
1707 /* Wait till PSR is idle */
18b5992c 1708 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1709 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1710 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1711}
1712
3d739d92
RV		 1713void intel_edp_psr_update(struct drm_device *dev)
1714{
1715 struct intel_encoder *encoder;
1716 struct intel_dp *intel_dp = NULL;
1717
1718 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1719 if (encoder->type == INTEL_OUTPUT_EDP) {
1720 intel_dp = enc_to_intel_dp(&encoder->base);
1721
a031d709 1722 if (!is_edp_psr(dev))
3d739d92
RV		 1723 return;
1724
1725 if (!intel_edp_psr_match_conditions(intel_dp))
1726 intel_edp_psr_disable(intel_dp);
1727 else
1728 if (!intel_edp_is_psr_enabled(dev))
1729 intel_edp_psr_do_enable(intel_dp);
1730 }
1731}
1732
e8cb4558 1733static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1734{
e8cb4558 1735 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1736 enum port port = dp_to_dig_port(intel_dp)->port;
1737 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1738
1739 /* Make sure the panel is off before trying to change the mode. But also
1740 * ensure that we have vdd while we switch off the panel. */
1741 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1742 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1743 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1744 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1745
1746 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1747 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1748 intel_dp_link_down(intel_dp);
d240f20f
JB		 1749}
1750
2bd2ad64 1751static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1752{
2bd2ad64 1753 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1754 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1755 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1756
982a3866 1757 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1758 intel_dp_link_down(intel_dp);
b2634017
JB		 1759 if (!IS_VALLEYVIEW(dev))
1760 ironlake_edp_pll_off(intel_dp);
3739850b 1761 }
2bd2ad64
DV		 1762}
1763
e8cb4558 1764static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1765{
e8cb4558
DV		 1766 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1767 struct drm_device *dev = encoder->base.dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1770
0c33d8d7
DV		 1771 if (WARN_ON(dp_reg & DP_PORT_EN))
1772 return;
5d613501 1773
97af61f5 1774 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1775 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1776 intel_dp_start_link_train(intel_dp);
97af61f5 1777 ironlake_edp_panel_on(intel_dp);
bd943159 1778 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1779 intel_dp_complete_link_train(intel_dp);
3ab9c637 1780 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1781}
89b667f8 1782
ecff4f3b
JN		 1783static void g4x_enable_dp(struct intel_encoder *encoder)
1784{
828f5c6e
JN		 1785 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1786
ecff4f3b 1787 intel_enable_dp(encoder);
f01eca2e 1788 ironlake_edp_backlight_on(intel_dp);
ab1f90f9 1789}
89b667f8 1790
ab1f90f9
JN		 1791static void vlv_enable_dp(struct intel_encoder *encoder)
1792{
828f5c6e
JN		 1793 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1794
1795 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1796}
1797
ecff4f3b 1798static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1799{
1800 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1801 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1802
1803 if (dport->port == PORT_A)
1804 ironlake_edp_pll_on(intel_dp);
1805}
1806
1807static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1808{
2bd2ad64 1809 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1810 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1811 struct drm_device *dev = encoder->base.dev;
89b667f8 1812 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1813 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1814 int port = vlv_dport_to_channel(dport);
1815 int pipe = intel_crtc->pipe;
bf13e81b 1816 struct edp_power_seq power_seq;
ab1f90f9 1817 u32 val;
a4fc5ed6 1818
ab1f90f9 1819 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1820
5e69f97f 1821 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
ab1f90f9
JN		 1822 val = 0;
1823 if (pipe)
1824 val |= (1<<21);
1825 else
1826 val &= ~(1<<21);
1827 val |= 0x001000c4;
5e69f97f
CML		 1828 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1829 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1830 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1831
ab1f90f9
JN		 1832 mutex_unlock(&dev_priv->dpio_lock);
1833
bf13e81b
JN		 1834 /* init power sequencer on this pipe and port */
1835 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1836 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1837 &power_seq);
1838
ab1f90f9
JN		 1839 intel_enable_dp(encoder);
1840
1841 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1842}
1843
ecff4f3b 1844static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1845{
1846 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1847 struct drm_device *dev = encoder->base.dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1849 struct intel_crtc *intel_crtc =
1850 to_intel_crtc(encoder->base.crtc);
89b667f8 1851 int port = vlv_dport_to_channel(dport);
5e69f97f 1852 int pipe = intel_crtc->pipe;
89b667f8 1853
89b667f8 1854 /* Program Tx lane resets to default */
0980a60f 1855 mutex_lock(&dev_priv->dpio_lock);
5e69f97f 1856 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
89b667f8
JB		 1857 DPIO_PCS_TX_LANE2_RESET |
1858 DPIO_PCS_TX_LANE1_RESET);
5e69f97f 1859 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
89b667f8
JB		 1860 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1861 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1862 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1863 DPIO_PCS_CLK_SOFT_RESET);
1864
1865 /* Fix up inter-pair skew failure */
5e69f97f
CML		 1866 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1867 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1868 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1869 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1870}
1871
1872/*
df0c237d
JB		 1873 * Native read with retry for link status and receiver capability reads for
1874 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1875 */
1876static bool
df0c237d
JB		 1877intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1878 uint8_t *recv, int recv_bytes)
a4fc5ed6 1879{
61da5fab
JB		 1880 int ret, i;
1881
df0c237d
JB		 1882 /*
1883 * Sinks are *supposed* to come up within 1ms from an off state,
1884 * but we're also supposed to retry 3 times per the spec.
1885 */
61da5fab 1886 for (i = 0; i < 3; i++) {
df0c237d
JB		 1887 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1888 recv_bytes);
1889 if (ret == recv_bytes)
61da5fab
JB		 1890 return true;
1891 msleep(1);
1892 }
a4fc5ed6 1893
61da5fab 1894 return false;
a4fc5ed6
KP		 1895}
1896
1897/*
1898 * Fetch AUX CH registers 0x202 - 0x207 which contain
1899 * link status information
1900 */
1901static bool
93f62dad 1902intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1903{
df0c237d
JB		 1904 return intel_dp_aux_native_read_retry(intel_dp,
1905 DP_LANE0_1_STATUS,
93f62dad 1906 link_status,
df0c237d 1907 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1908}
1909
a4fc5ed6
KP		 1910#if 0
1911static char *voltage_names[] = {
1912 "0.4V", "0.6V", "0.8V", "1.2V"
1913};
1914static char *pre_emph_names[] = {
1915 "0dB", "3.5dB", "6dB", "9.5dB"
1916};
1917static char *link_train_names[] = {
1918 "pattern 1", "pattern 2", "idle", "off"
1919};
1920#endif
1921
1922/*
1923 * These are source-specific values; current Intel hardware supports
1924 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1925 */
a4fc5ed6
KP		 1926
1927static uint8_t
1a2eb460 1928intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1929{
30add22d 1930 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1931 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1932
e2fa6fba
P		 1933 if (IS_VALLEYVIEW(dev))
1934 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1935 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1936 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1937 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1938 return DP_TRAIN_VOLTAGE_SWING_1200;
1939 else
1940 return DP_TRAIN_VOLTAGE_SWING_800;
1941}
1942
1943static uint8_t
1944intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1945{
30add22d 1946 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1947 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1948
22b8bf17 1949 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1950 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1951 case DP_TRAIN_VOLTAGE_SWING_400:
1952 return DP_TRAIN_PRE_EMPHASIS_9_5;
1953 case DP_TRAIN_VOLTAGE_SWING_600:
1954 return DP_TRAIN_PRE_EMPHASIS_6;
1955 case DP_TRAIN_VOLTAGE_SWING_800:
1956 return DP_TRAIN_PRE_EMPHASIS_3_5;
1957 case DP_TRAIN_VOLTAGE_SWING_1200:
1958 default:
1959 return DP_TRAIN_PRE_EMPHASIS_0;
1960 }
e2fa6fba
P		 1961 } else if (IS_VALLEYVIEW(dev)) {
1962 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1963 case DP_TRAIN_VOLTAGE_SWING_400:
1964 return DP_TRAIN_PRE_EMPHASIS_9_5;
1965 case DP_TRAIN_VOLTAGE_SWING_600:
1966 return DP_TRAIN_PRE_EMPHASIS_6;
1967 case DP_TRAIN_VOLTAGE_SWING_800:
1968 return DP_TRAIN_PRE_EMPHASIS_3_5;
1969 case DP_TRAIN_VOLTAGE_SWING_1200:
1970 default:
1971 return DP_TRAIN_PRE_EMPHASIS_0;
1972 }
bc7d38a4 1973 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1974 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1975 case DP_TRAIN_VOLTAGE_SWING_400:
1976 return DP_TRAIN_PRE_EMPHASIS_6;
1977 case DP_TRAIN_VOLTAGE_SWING_600:
1978 case DP_TRAIN_VOLTAGE_SWING_800:
1979 return DP_TRAIN_PRE_EMPHASIS_3_5;
1980 default:
1981 return DP_TRAIN_PRE_EMPHASIS_0;
1982 }
1983 } else {
1984 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1985 case DP_TRAIN_VOLTAGE_SWING_400:
1986 return DP_TRAIN_PRE_EMPHASIS_6;
1987 case DP_TRAIN_VOLTAGE_SWING_600:
1988 return DP_TRAIN_PRE_EMPHASIS_6;
1989 case DP_TRAIN_VOLTAGE_SWING_800:
1990 return DP_TRAIN_PRE_EMPHASIS_3_5;
1991 case DP_TRAIN_VOLTAGE_SWING_1200:
1992 default:
1993 return DP_TRAIN_PRE_EMPHASIS_0;
1994 }
a4fc5ed6
KP		 1995 }
1996}
1997
e2fa6fba
P		 1998static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1999{
2000 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2003 struct intel_crtc *intel_crtc =
2004 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2005 unsigned long demph_reg_value, preemph_reg_value,
2006 uniqtranscale_reg_value;
2007 uint8_t train_set = intel_dp->train_set[0];
cece5d58 2008 int port = vlv_dport_to_channel(dport);
5e69f97f 2009 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2010
2011 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2012 case DP_TRAIN_PRE_EMPHASIS_0:
2013 preemph_reg_value = 0x0004000;
2014 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2015 case DP_TRAIN_VOLTAGE_SWING_400:
2016 demph_reg_value = 0x2B405555;
2017 uniqtranscale_reg_value = 0x552AB83A;
2018 break;
2019 case DP_TRAIN_VOLTAGE_SWING_600:
2020 demph_reg_value = 0x2B404040;
2021 uniqtranscale_reg_value = 0x5548B83A;
2022 break;
2023 case DP_TRAIN_VOLTAGE_SWING_800:
2024 demph_reg_value = 0x2B245555;
2025 uniqtranscale_reg_value = 0x5560B83A;
2026 break;
2027 case DP_TRAIN_VOLTAGE_SWING_1200:
2028 demph_reg_value = 0x2B405555;
2029 uniqtranscale_reg_value = 0x5598DA3A;
2030 break;
2031 default:
2032 return 0;
2033 }
2034 break;
2035 case DP_TRAIN_PRE_EMPHASIS_3_5:
2036 preemph_reg_value = 0x0002000;
2037 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2038 case DP_TRAIN_VOLTAGE_SWING_400:
2039 demph_reg_value = 0x2B404040;
2040 uniqtranscale_reg_value = 0x5552B83A;
2041 break;
2042 case DP_TRAIN_VOLTAGE_SWING_600:
2043 demph_reg_value = 0x2B404848;
2044 uniqtranscale_reg_value = 0x5580B83A;
2045 break;
2046 case DP_TRAIN_VOLTAGE_SWING_800:
2047 demph_reg_value = 0x2B404040;
2048 uniqtranscale_reg_value = 0x55ADDA3A;
2049 break;
2050 default:
2051 return 0;
2052 }
2053 break;
2054 case DP_TRAIN_PRE_EMPHASIS_6:
2055 preemph_reg_value = 0x0000000;
2056 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2057 case DP_TRAIN_VOLTAGE_SWING_400:
2058 demph_reg_value = 0x2B305555;
2059 uniqtranscale_reg_value = 0x5570B83A;
2060 break;
2061 case DP_TRAIN_VOLTAGE_SWING_600:
2062 demph_reg_value = 0x2B2B4040;
2063 uniqtranscale_reg_value = 0x55ADDA3A;
2064 break;
2065 default:
2066 return 0;
2067 }
2068 break;
2069 case DP_TRAIN_PRE_EMPHASIS_9_5:
2070 preemph_reg_value = 0x0006000;
2071 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2072 case DP_TRAIN_VOLTAGE_SWING_400:
2073 demph_reg_value = 0x1B405555;
2074 uniqtranscale_reg_value = 0x55ADDA3A;
2075 break;
2076 default:
2077 return 0;
2078 }
2079 break;
2080 default:
2081 return 0;
2082 }
2083
0980a60f 2084 mutex_lock(&dev_priv->dpio_lock);
5e69f97f
CML		 2085 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2086 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2087 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
e2fa6fba 2088 uniqtranscale_reg_value);
5e69f97f
CML		 2089 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2090 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2091 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2092 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 2093 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2094
2095 return 0;
2096}
2097
a4fc5ed6 2098static void
0301b3ac
JN		 2099intel_get_adjust_train(struct intel_dp *intel_dp,
2100 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2101{
2102 uint8_t v = 0;
2103 uint8_t p = 0;
2104 int lane;
1a2eb460
KP		 2105 uint8_t voltage_max;
2106 uint8_t preemph_max;
a4fc5ed6 2107
33a34e4e 2108 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2109 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2110 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2111
2112 if (this_v > v)
2113 v = this_v;
2114 if (this_p > p)
2115 p = this_p;
2116 }
2117
1a2eb460 2118 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2119 if (v >= voltage_max)
2120 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2121
1a2eb460
KP		 2122 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2123 if (p >= preemph_max)
2124 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2125
2126 for (lane = 0; lane < 4; lane++)
33a34e4e 2127 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2128}
2129
2130static uint32_t
f0a3424e 2131intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2132{
3cf2efb1 2133 uint32_t signal_levels = 0;
a4fc5ed6 2134
3cf2efb1 2135 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2136 case DP_TRAIN_VOLTAGE_SWING_400:
2137 default:
2138 signal_levels |= DP_VOLTAGE_0_4;
2139 break;
2140 case DP_TRAIN_VOLTAGE_SWING_600:
2141 signal_levels |= DP_VOLTAGE_0_6;
2142 break;
2143 case DP_TRAIN_VOLTAGE_SWING_800:
2144 signal_levels |= DP_VOLTAGE_0_8;
2145 break;
2146 case DP_TRAIN_VOLTAGE_SWING_1200:
2147 signal_levels |= DP_VOLTAGE_1_2;
2148 break;
2149 }
3cf2efb1 2150 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2151 case DP_TRAIN_PRE_EMPHASIS_0:
2152 default:
2153 signal_levels |= DP_PRE_EMPHASIS_0;
2154 break;
2155 case DP_TRAIN_PRE_EMPHASIS_3_5:
2156 signal_levels |= DP_PRE_EMPHASIS_3_5;
2157 break;
2158 case DP_TRAIN_PRE_EMPHASIS_6:
2159 signal_levels |= DP_PRE_EMPHASIS_6;
2160 break;
2161 case DP_TRAIN_PRE_EMPHASIS_9_5:
2162 signal_levels |= DP_PRE_EMPHASIS_9_5;
2163 break;
2164 }
2165 return signal_levels;
2166}
2167
e3421a18
ZW		 2168/* Gen6's DP voltage swing and pre-emphasis control */
2169static uint32_t
2170intel_gen6_edp_signal_levels(uint8_t train_set)
2171{
3c5a62b5
YL		 2172 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2173 DP_TRAIN_PRE_EMPHASIS_MASK);
2174 switch (signal_levels) {
e3421a18 2175 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2176 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2177 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2178 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2179 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2180 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2181 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2182 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2183 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2184 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2185 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2186 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2187 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2188 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2189 default:
3c5a62b5
YL		 2190 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2191 "0x%x\n", signal_levels);
2192 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2193 }
2194}
2195
1a2eb460
KP		 2196/* Gen7's DP voltage swing and pre-emphasis control */
2197static uint32_t
2198intel_gen7_edp_signal_levels(uint8_t train_set)
2199{
2200 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2201 DP_TRAIN_PRE_EMPHASIS_MASK);
2202 switch (signal_levels) {
2203 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2204 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2205 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2206 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2207 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2208 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2209
2210 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2211 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2212 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2213 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2214
2215 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2216 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2217 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2218 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2219
2220 default:
2221 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2222 "0x%x\n", signal_levels);
2223 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2224 }
2225}
2226
d6c0d722
PZ		 2227/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2228static uint32_t
f0a3424e 2229intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2230{
d6c0d722
PZ		 2231 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2232 DP_TRAIN_PRE_EMPHASIS_MASK);
2233 switch (signal_levels) {
2234 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2235 return DDI_BUF_EMP_400MV_0DB_HSW;
2236 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2237 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2238 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2239 return DDI_BUF_EMP_400MV_6DB_HSW;
2240 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2241 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2242
d6c0d722
PZ		 2243 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2244 return DDI_BUF_EMP_600MV_0DB_HSW;
2245 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2246 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2247 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2248 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2249
d6c0d722
PZ		 2250 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2251 return DDI_BUF_EMP_800MV_0DB_HSW;
2252 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2253 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2254 default:
2255 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2256 "0x%x\n", signal_levels);
2257 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2258 }
a4fc5ed6
KP		 2259}
2260
f0a3424e
PZ		 2261/* Properly updates "DP" with the correct signal levels. */
2262static void
2263intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2264{
2265 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2266 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2267 struct drm_device *dev = intel_dig_port->base.base.dev;
2268 uint32_t signal_levels, mask;
2269 uint8_t train_set = intel_dp->train_set[0];
2270
22b8bf17 2271 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2272 signal_levels = intel_hsw_signal_levels(train_set);
2273 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2274 } else if (IS_VALLEYVIEW(dev)) {
2275 signal_levels = intel_vlv_signal_levels(intel_dp);
2276 mask = 0;
bc7d38a4 2277 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2278 signal_levels = intel_gen7_edp_signal_levels(train_set);
2279 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2280 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2281 signal_levels = intel_gen6_edp_signal_levels(train_set);
2282 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2283 } else {
2284 signal_levels = intel_gen4_signal_levels(train_set);
2285 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2286 }
2287
2288 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2289
2290 *DP = (*DP & ~mask) | signal_levels;
2291}
2292
a4fc5ed6 2293static bool
ea5b213a 2294intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2295 uint32_t *DP,
58e10eb9 2296 uint8_t dp_train_pat)
a4fc5ed6 2297{
174edf1f
PZ		 2298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2299 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2300 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2301 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2302 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2303 int ret, len;
a4fc5ed6 2304
22b8bf17 2305 if (HAS_DDI(dev)) {
3ab9c637 2306 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2307
2308 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2309 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2310 else
2311 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2312
2313 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2314 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2315 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2316 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2317
2318 break;
2319 case DP_TRAINING_PATTERN_1:
2320 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2321 break;
2322 case DP_TRAINING_PATTERN_2:
2323 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2324 break;
2325 case DP_TRAINING_PATTERN_3:
2326 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2327 break;
2328 }
174edf1f 2329 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2330
bc7d38a4 2331 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2332 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2333
2334 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2335 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2336 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2337 break;
2338 case DP_TRAINING_PATTERN_1:
70aff66c 2339 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2340 break;
2341 case DP_TRAINING_PATTERN_2:
70aff66c 2342 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2343 break;
2344 case DP_TRAINING_PATTERN_3:
2345 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2346 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2347 break;
2348 }
2349
2350 } else {
70aff66c 2351 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2352
2353 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2354 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2355 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2356 break;
2357 case DP_TRAINING_PATTERN_1:
70aff66c 2358 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2359 break;
2360 case DP_TRAINING_PATTERN_2:
70aff66c 2361 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2362 break;
2363 case DP_TRAINING_PATTERN_3:
2364 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2365 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2366 break;
2367 }
2368 }
2369
70aff66c 2370 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2371 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2372
2cdfe6c8
JN		 2373 buf[0] = dp_train_pat;
2374 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2375 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2376 /* don't write DP_TRAINING_LANEx_SET on disable */
2377 len = 1;
2378 } else {
2379 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2380 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2381 len = intel_dp->lane_count + 1;
47ea7542 2382 }
a4fc5ed6 2383
2cdfe6c8
JN		 2384 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2385 buf, len);
2386
2387 return ret == len;
a4fc5ed6
KP		 2388}
2389
70aff66c
JN		 2390static bool
2391intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2392 uint8_t dp_train_pat)
2393{
953d22e8 2394 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2395 intel_dp_set_signal_levels(intel_dp, DP);
2396 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2397}
2398
2399static bool
2400intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2401 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2402{
2403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2404 struct drm_device *dev = intel_dig_port->base.base.dev;
2405 struct drm_i915_private *dev_priv = dev->dev_private;
2406 int ret;
2407
2408 intel_get_adjust_train(intel_dp, link_status);
2409 intel_dp_set_signal_levels(intel_dp, DP);
2410
2411 I915_WRITE(intel_dp->output_reg, *DP);
2412 POSTING_READ(intel_dp->output_reg);
2413
2414 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2415 intel_dp->train_set,
2416 intel_dp->lane_count);
2417
2418 return ret == intel_dp->lane_count;
2419}
2420
3ab9c637
ID		 2421static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2422{
2423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2424 struct drm_device *dev = intel_dig_port->base.base.dev;
2425 struct drm_i915_private *dev_priv = dev->dev_private;
2426 enum port port = intel_dig_port->port;
2427 uint32_t val;
2428
2429 if (!HAS_DDI(dev))
2430 return;
2431
2432 val = I915_READ(DP_TP_CTL(port));
2433 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2434 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2435 I915_WRITE(DP_TP_CTL(port), val);
2436
2437 /*
2438 * On PORT_A we can have only eDP in SST mode. There the only reason
2439 * we need to set idle transmission mode is to work around a HW issue
2440 * where we enable the pipe while not in idle link-training mode.
2441 * In this case there is requirement to wait for a minimum number of
2442 * idle patterns to be sent.
2443 */
2444 if (port == PORT_A)
2445 return;
2446
2447 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2448 1))
2449 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2450}
2451
33a34e4e 2452/* Enable corresponding port and start training pattern 1 */
c19b0669 2453void
33a34e4e 2454intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2455{
da63a9f2 2456 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2457 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2458 int i;
2459 uint8_t voltage;
cdb0e95b 2460 int voltage_tries, loop_tries;
ea5b213a 2461 uint32_t DP = intel_dp->DP;
6aba5b6c 2462 uint8_t link_config[2];
a4fc5ed6 2463
affa9354 2464 if (HAS_DDI(dev))
c19b0669
PZ		 2465 intel_ddi_prepare_link_retrain(encoder);
2466
3cf2efb1 2467 /* Write the link configuration data */
6aba5b6c
JN		 2468 link_config[0] = intel_dp->link_bw;
2469 link_config[1] = intel_dp->lane_count;
2470 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2471 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2472 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2473
2474 link_config[0] = 0;
2475 link_config[1] = DP_SET_ANSI_8B10B;
2476 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2477
2478 DP |= DP_PORT_EN;
1a2eb460 2479
70aff66c
JN		 2480 /* clock recovery */
2481 if (!intel_dp_reset_link_train(intel_dp, &DP,
2482 DP_TRAINING_PATTERN_1 |
2483 DP_LINK_SCRAMBLING_DISABLE)) {
2484 DRM_ERROR("failed to enable link training\n");
2485 return;
2486 }
2487
a4fc5ed6 2488 voltage = 0xff;
cdb0e95b
KP		 2489 voltage_tries = 0;
2490 loop_tries = 0;
a4fc5ed6 2491 for (;;) {
70aff66c 2492 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2493
a7c9655f 2494 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2495 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2496 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2497 break;
93f62dad 2498 }
a4fc5ed6 2499
01916270 2500 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2501 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2502 break;
2503 }
2504
2505 /* Check to see if we've tried the max voltage */
2506 for (i = 0; i < intel_dp->lane_count; i++)
2507 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2508 break;
3b4f819d 2509 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2510 ++loop_tries;
2511 if (loop_tries == 5) {
3def84b3 2512 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2513 break;
2514 }
70aff66c
JN		 2515 intel_dp_reset_link_train(intel_dp, &DP,
2516 DP_TRAINING_PATTERN_1 |
2517 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2518 voltage_tries = 0;
2519 continue;
2520 }
a4fc5ed6 2521
3cf2efb1 2522 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2523 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2524 ++voltage_tries;
b06fbda3 2525 if (voltage_tries == 5) {
3def84b3 2526 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2527 break;
2528 }
2529 } else
2530 voltage_tries = 0;
2531 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2532
70aff66c
JN		 2533 /* Update training set as requested by target */
2534 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2535 DRM_ERROR("failed to update link training\n");
2536 break;
2537 }
a4fc5ed6
KP		 2538 }
2539
33a34e4e
JB		 2540 intel_dp->DP = DP;
2541}
2542
c19b0669 2543void
33a34e4e
JB		 2544intel_dp_complete_link_train(struct intel_dp *intel_dp)
2545{
33a34e4e 2546 bool channel_eq = false;
37f80975 2547 int tries, cr_tries;
33a34e4e
JB		 2548 uint32_t DP = intel_dp->DP;
2549
a4fc5ed6 2550 /* channel equalization */
70aff66c
JN		 2551 if (!intel_dp_set_link_train(intel_dp, &DP,
2552 DP_TRAINING_PATTERN_2 |
2553 DP_LINK_SCRAMBLING_DISABLE)) {
2554 DRM_ERROR("failed to start channel equalization\n");
2555 return;
2556 }
2557
a4fc5ed6 2558 tries = 0;
37f80975 2559 cr_tries = 0;
a4fc5ed6
KP		 2560 channel_eq = false;
2561 for (;;) {
70aff66c 2562 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2563
37f80975
JB		 2564 if (cr_tries > 5) {
2565 DRM_ERROR("failed to train DP, aborting\n");
2566 intel_dp_link_down(intel_dp);
2567 break;
2568 }
2569
a7c9655f 2570 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2571 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2572 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2573 break;
70aff66c 2574 }
a4fc5ed6 2575
37f80975 2576 /* Make sure clock is still ok */
01916270 2577 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2578 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2579 intel_dp_set_link_train(intel_dp, &DP,
2580 DP_TRAINING_PATTERN_2 |
2581 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2582 cr_tries++;
2583 continue;
2584 }
2585
1ffdff13 2586 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2587 channel_eq = true;
2588 break;
2589 }
a4fc5ed6 2590
37f80975
JB		 2591 /* Try 5 times, then try clock recovery if that fails */
2592 if (tries > 5) {
2593 intel_dp_link_down(intel_dp);
2594 intel_dp_start_link_train(intel_dp);
70aff66c
JN		 2595 intel_dp_set_link_train(intel_dp, &DP,
2596 DP_TRAINING_PATTERN_2 |
2597 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2598 tries = 0;
2599 cr_tries++;
2600 continue;
2601 }
a4fc5ed6 2602
70aff66c
JN		 2603 /* Update training set as requested by target */
2604 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2605 DRM_ERROR("failed to update link training\n");
2606 break;
2607 }
3cf2efb1 2608 ++tries;
869184a6 2609 }
3cf2efb1 2610
3ab9c637
ID		 2611 intel_dp_set_idle_link_train(intel_dp);
2612
2613 intel_dp->DP = DP;
2614
d6c0d722 2615 if (channel_eq)
07f42258 2616 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2617
3ab9c637
ID		 2618}
2619
2620void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2621{
70aff66c 2622 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2623 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2624}
2625
2626static void
ea5b213a 2627intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2628{
da63a9f2 2629 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2630 enum port port = intel_dig_port->port;
da63a9f2 2631 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2632 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2633 struct intel_crtc *intel_crtc =
2634 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2635 uint32_t DP = intel_dp->DP;
a4fc5ed6 2636
c19b0669
PZ		 2637 /*
2638 * DDI code has a strict mode set sequence and we should try to respect
2639 * it, otherwise we might hang the machine in many different ways. So we
2640 * really should be disabling the port only on a complete crtc_disable
2641 * sequence. This function is just called under two conditions on DDI
2642 * code:
2643 * - Link train failed while doing crtc_enable, and on this case we
2644 * really should respect the mode set sequence and wait for a
2645 * crtc_disable.
2646 * - Someone turned the monitor off and intel_dp_check_link_status
2647 * called us. We don't need to disable the whole port on this case, so
2648 * when someone turns the monitor on again,
2649 * intel_ddi_prepare_link_retrain will take care of redoing the link
2650 * train.
2651 */
affa9354 2652 if (HAS_DDI(dev))
c19b0669
PZ		 2653 return;
2654
0c33d8d7 2655 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2656 return;
2657
28c97730 2658 DRM_DEBUG_KMS("\n");
32f9d658 2659
bc7d38a4 2660 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2661 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2662 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2663 } else {
2664 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2665 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2666 }
fe255d00 2667 POSTING_READ(intel_dp->output_reg);
5eb08b69 2668
ab527efc
DV		 2669 /* We don't really know why we're doing this */
2670 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2671
493a7081 2672 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2673 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2674 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2675
5bddd17f
EA		 2676 /* Hardware workaround: leaving our transcoder select
2677 * set to transcoder B while it's off will prevent the
2678 * corresponding HDMI output on transcoder A.
2679 *
2680 * Combine this with another hardware workaround:
2681 * transcoder select bit can only be cleared while the
2682 * port is enabled.
2683 */
2684 DP &= ~DP_PIPEB_SELECT;
2685 I915_WRITE(intel_dp->output_reg, DP);
2686
2687 /* Changes to enable or select take place the vblank
2688 * after being written.
2689 */
ff50afe9
DV		 2690 if (WARN_ON(crtc == NULL)) {
2691 /* We should never try to disable a port without a crtc
2692 * attached. For paranoia keep the code around for a
2693 * bit. */
31acbcc4
CW		 2694 POSTING_READ(intel_dp->output_reg);
2695 msleep(50);
2696 } else
ab527efc 2697 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2698 }
2699
832afda6 2700 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2701 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2702 POSTING_READ(intel_dp->output_reg);
f01eca2e 2703 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2704}
2705
26d61aad
KP		 2706static bool
2707intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2708{
a031d709
RV		 2709 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2710 struct drm_device *dev = dig_port->base.base.dev;
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712
577c7a50
DL		 2713 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2714
92fd8fd1 2715 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2716 sizeof(intel_dp->dpcd)) == 0)
2717 return false; /* aux transfer failed */
92fd8fd1 2718
577c7a50
DL		 2719 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2720 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2721 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2722
edb39244
AJ		 2723 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2724 return false; /* DPCD not present */
2725
2293bb5c
SK		 2726 /* Check if the panel supports PSR */
2727 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2728 if (is_edp(intel_dp)) {
2729 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2730 intel_dp->psr_dpcd,
2731 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2732 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2733 dev_priv->psr.sink_support = true;
50003939 2734 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2735 }
50003939
JN		 2736 }
2737
edb39244
AJ		 2738 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2739 DP_DWN_STRM_PORT_PRESENT))
2740 return true; /* native DP sink */
2741
2742 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2743 return true; /* no per-port downstream info */
2744
2745 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2746 intel_dp->downstream_ports,
2747 DP_MAX_DOWNSTREAM_PORTS) == 0)
2748 return false; /* downstream port status fetch failed */
2749
2750 return true;
92fd8fd1
KP		 2751}
2752
0d198328
AJ		 2753static void
2754intel_dp_probe_oui(struct intel_dp *intel_dp)
2755{
2756 u8 buf[3];
2757
2758 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2759 return;
2760
351cfc34
DV		 2761 ironlake_edp_panel_vdd_on(intel_dp);
2762
0d198328
AJ		 2763 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2764 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2765 buf[0], buf[1], buf[2]);
2766
2767 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2768 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2769 buf[0], buf[1], buf[2]);
351cfc34
DV		 2770
2771 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2772}
2773
a60f0e38
JB		 2774static bool
2775intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2776{
2777 int ret;
2778
2779 ret = intel_dp_aux_native_read_retry(intel_dp,
2780 DP_DEVICE_SERVICE_IRQ_VECTOR,
2781 sink_irq_vector, 1);
2782 if (!ret)
2783 return false;
2784
2785 return true;
2786}
2787
2788static void
2789intel_dp_handle_test_request(struct intel_dp *intel_dp)
2790{
2791 /* NAK by default */
9324cf7f 2792 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2793}
2794
a4fc5ed6
KP		 2795/*
2796 * According to DP spec
2797 * 5.1.2:
2798 * 1. Read DPCD
2799 * 2. Configure link according to Receiver Capabilities
2800 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2801 * 4. Check link status on receipt of hot-plug interrupt
2802 */
2803
00c09d70 2804void
ea5b213a 2805intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2806{
da63a9f2 2807 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2808 u8 sink_irq_vector;
93f62dad 2809 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2810
da63a9f2 2811 if (!intel_encoder->connectors_active)
d2b996ac 2812 return;
59cd09e1 2813
da63a9f2 2814 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2815 return;
2816
92fd8fd1 2817 /* Try to read receiver status if the link appears to be up */
93f62dad 2818 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2819 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2820 return;
2821 }
2822
92fd8fd1 2823 /* Now read the DPCD to see if it's actually running */
26d61aad 2824 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2825 intel_dp_link_down(intel_dp);
2826 return;
2827 }
2828
a60f0e38
JB		 2829 /* Try to read the source of the interrupt */
2830 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2831 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2832 /* Clear interrupt source */
2833 intel_dp_aux_native_write_1(intel_dp,
2834 DP_DEVICE_SERVICE_IRQ_VECTOR,
2835 sink_irq_vector);
2836
2837 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2838 intel_dp_handle_test_request(intel_dp);
2839 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2840 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2841 }
2842
1ffdff13 2843 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2844 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2845 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2846 intel_dp_start_link_train(intel_dp);
2847 intel_dp_complete_link_train(intel_dp);
3ab9c637 2848 intel_dp_stop_link_train(intel_dp);
33a34e4e 2849 }
a4fc5ed6 2850}
a4fc5ed6 2851
caf9ab24 2852/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2853static enum drm_connector_status
26d61aad 2854intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2855{
caf9ab24 2856 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2857 uint8_t type;
2858
2859 if (!intel_dp_get_dpcd(intel_dp))
2860 return connector_status_disconnected;
2861
2862 /* if there's no downstream port, we're done */
2863 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2864 return connector_status_connected;
caf9ab24
AJ		 2865
2866 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 2867 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2868 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 2869 uint8_t reg;
caf9ab24 2870 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2871 &reg, 1))
caf9ab24 2872 return connector_status_unknown;
23235177
AJ		 2873 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2874 : connector_status_disconnected;
caf9ab24
AJ		 2875 }
2876
2877 /* If no HPD, poke DDC gently */
2878 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2879 return connector_status_connected;
caf9ab24
AJ		 2880
2881 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 2882 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2883 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2884 if (type == DP_DS_PORT_TYPE_VGA ||
2885 type == DP_DS_PORT_TYPE_NON_EDID)
2886 return connector_status_unknown;
2887 } else {
2888 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2889 DP_DWN_STRM_PORT_TYPE_MASK;
2890 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2891 type == DP_DWN_STRM_PORT_TYPE_OTHER)
2892 return connector_status_unknown;
2893 }
caf9ab24
AJ		 2894
2895 /* Anything else is out of spec, warn and ignore */
2896 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2897 return connector_status_disconnected;
71ba9000
AJ		 2898}
2899
5eb08b69 2900static enum drm_connector_status
a9756bb5 2901ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2902{
30add22d 2903 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2904 struct drm_i915_private *dev_priv = dev->dev_private;
2905 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2906 enum drm_connector_status status;
2907
fe16d949
CW		 2908 /* Can't disconnect eDP, but you can close the lid... */
2909 if (is_edp(intel_dp)) {
30add22d 2910 status = intel_panel_detect(dev);
fe16d949
CW		 2911 if (status == connector_status_unknown)
2912 status = connector_status_connected;
2913 return status;
2914 }
01cb9ea6 2915
1b469639
DL		 2916 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2917 return connector_status_disconnected;
2918
26d61aad 2919 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2920}
2921
a4fc5ed6 2922static enum drm_connector_status
a9756bb5 2923g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2924{
30add22d 2925 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2926 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2928 uint32_t bit;
5eb08b69 2929
35aad75f
JB		 2930 /* Can't disconnect eDP, but you can close the lid... */
2931 if (is_edp(intel_dp)) {
2932 enum drm_connector_status status;
2933
2934 status = intel_panel_detect(dev);
2935 if (status == connector_status_unknown)
2936 status = connector_status_connected;
2937 return status;
2938 }
2939
34f2be46
VS		 2940 switch (intel_dig_port->port) {
2941 case PORT_B:
26739f12 2942 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2943 break;
34f2be46 2944 case PORT_C:
26739f12 2945 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2946 break;
34f2be46 2947 case PORT_D:
26739f12 2948 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2949 break;
2950 default:
2951 return connector_status_unknown;
2952 }
2953
10f76a38 2954 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2955 return connector_status_disconnected;
2956
26d61aad 2957 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2958}
2959
8c241fef
KP		 2960static struct edid *
2961intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2962{
9cd300e0 2963 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2964
9cd300e0
JN		 2965 /* use cached edid if we have one */
2966 if (intel_connector->edid) {
9cd300e0
JN		 2967 /* invalid edid */
2968 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2969 return NULL;
2970
55e9edeb 2971 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 2972 }
8c241fef 2973
9cd300e0 2974 return drm_get_edid(connector, adapter);
8c241fef
KP		 2975}
2976
2977static int
2978intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2979{
9cd300e0 2980 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2981
9cd300e0
JN		 2982 /* use cached edid if we have one */
2983 if (intel_connector->edid) {
2984 /* invalid edid */
2985 if (IS_ERR(intel_connector->edid))
2986 return 0;
2987
2988 return intel_connector_update_modes(connector,
2989 intel_connector->edid);
d6f24d0f
JB		 2990 }
2991
9cd300e0 2992 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2993}
2994
a9756bb5
ZW		 2995static enum drm_connector_status
2996intel_dp_detect(struct drm_connector *connector, bool force)
2997{
2998 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2999 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3000 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3001 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 3002 enum drm_connector_status status;
3003 struct edid *edid = NULL;
3004
164c8598
CW		 3005 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3006 connector->base.id, drm_get_connector_name(connector));
3007
a9756bb5
ZW		 3008 intel_dp->has_audio = false;
3009
3010 if (HAS_PCH_SPLIT(dev))
3011 status = ironlake_dp_detect(intel_dp);
3012 else
3013 status = g4x_dp_detect(intel_dp);
1b9be9d0 3014
a9756bb5
ZW		 3015 if (status != connector_status_connected)
3016 return status;
3017
0d198328
AJ		 3018 intel_dp_probe_oui(intel_dp);
3019
c3e5f67b
DV		 3020 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3021 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3022 } else {
8c241fef 3023 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3024 if (edid) {
3025 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3026 kfree(edid);
3027 }
a9756bb5
ZW		 3028 }
3029
d63885da
PZ		 3030 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3031 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 3032 return connector_status_connected;
a4fc5ed6
KP		 3033}
3034
3035static int intel_dp_get_modes(struct drm_connector *connector)
3036{
df0e9248 3037 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 3038 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3039 struct drm_device *dev = connector->dev;
32f9d658 3040 int ret;
a4fc5ed6
KP		 3041
3042 /* We should parse the EDID data and find out if it has an audio sink
3043 */
3044
8c241fef 3045 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 3046 if (ret)
32f9d658
ZW		 3047 return ret;
3048
f8779fda 3049 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3050 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3051 struct drm_display_mode *mode;
dd06f90e
JN		 3052 mode = drm_mode_duplicate(dev,
3053 intel_connector->panel.fixed_mode);
f8779fda 3054 if (mode) {
32f9d658
ZW		 3055 drm_mode_probed_add(connector, mode);
3056 return 1;
3057 }
3058 }
3059 return 0;
a4fc5ed6
KP		 3060}
3061
1aad7ac0
CW		 3062static bool
3063intel_dp_detect_audio(struct drm_connector *connector)
3064{
3065 struct intel_dp *intel_dp = intel_attached_dp(connector);
3066 struct edid *edid;
3067 bool has_audio = false;
3068
8c241fef 3069 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3070 if (edid) {
3071 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3072 kfree(edid);
3073 }
3074
3075 return has_audio;
3076}
3077
f684960e
CW		 3078static int
3079intel_dp_set_property(struct drm_connector *connector,
3080 struct drm_property *property,
3081 uint64_t val)
3082{
e953fd7b 3083 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3084 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3085 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3086 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3087 int ret;
3088
662595df 3089 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3090 if (ret)
3091 return ret;
3092
3f43c48d 3093 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3094 int i = val;
3095 bool has_audio;
3096
3097 if (i == intel_dp->force_audio)
f684960e
CW		 3098 return 0;
3099
1aad7ac0 3100 intel_dp->force_audio = i;
f684960e 3101
c3e5f67b 3102 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3103 has_audio = intel_dp_detect_audio(connector);
3104 else
c3e5f67b 3105 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3106
3107 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3108 return 0;
3109
1aad7ac0 3110 intel_dp->has_audio = has_audio;
f684960e
CW		 3111 goto done;
3112 }
3113
e953fd7b 3114 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3115 bool old_auto = intel_dp->color_range_auto;
3116 uint32_t old_range = intel_dp->color_range;
3117
55bc60db
VS		 3118 switch (val) {
3119 case INTEL_BROADCAST_RGB_AUTO:
3120 intel_dp->color_range_auto = true;
3121 break;
3122 case INTEL_BROADCAST_RGB_FULL:
3123 intel_dp->color_range_auto = false;
3124 intel_dp->color_range = 0;
3125 break;
3126 case INTEL_BROADCAST_RGB_LIMITED:
3127 intel_dp->color_range_auto = false;
3128 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3129 break;
3130 default:
3131 return -EINVAL;
3132 }
ae4edb80
DV		 3133
3134 if (old_auto == intel_dp->color_range_auto &&
3135 old_range == intel_dp->color_range)
3136 return 0;
3137
e953fd7b
CW		 3138 goto done;
3139 }
3140
53b41837
YN		 3141 if (is_edp(intel_dp) &&
3142 property == connector->dev->mode_config.scaling_mode_property) {
3143 if (val == DRM_MODE_SCALE_NONE) {
3144 DRM_DEBUG_KMS("no scaling not supported\n");
3145 return -EINVAL;
3146 }
3147
3148 if (intel_connector->panel.fitting_mode == val) {
3149 /* the eDP scaling property is not changed */
3150 return 0;
3151 }
3152 intel_connector->panel.fitting_mode = val;
3153
3154 goto done;
3155 }
3156
f684960e
CW		 3157 return -EINVAL;
3158
3159done:
c0c36b94
CW		 3160 if (intel_encoder->base.crtc)
3161 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3162
3163 return 0;
3164}
3165
a4fc5ed6 3166static void
73845adf 3167intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3168{
1d508706 3169 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3170
9cd300e0
JN		 3171 if (!IS_ERR_OR_NULL(intel_connector->edid))
3172 kfree(intel_connector->edid);
3173
acd8db10
PZ		 3174 /* Can't call is_edp() since the encoder may have been destroyed
3175 * already. */
3176 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3177 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3178
a4fc5ed6 3179 drm_connector_cleanup(connector);
55f78c43 3180 kfree(connector);
a4fc5ed6
KP		 3181}
3182
00c09d70 3183void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3184{
da63a9f2
PZ		 3185 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3186 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3187 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3188
3189 i2c_del_adapter(&intel_dp->adapter);
3190 drm_encoder_cleanup(encoder);
bd943159
KP		 3191 if (is_edp(intel_dp)) {
3192 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3193 mutex_lock(&dev->mode_config.mutex);
bd943159 3194 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3195 mutex_unlock(&dev->mode_config.mutex);
bd943159 3196 }
da63a9f2 3197 kfree(intel_dig_port);
24d05927
DV		 3198}
3199
a4fc5ed6 3200static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3201 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3202 .detect = intel_dp_detect,
3203 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3204 .set_property = intel_dp_set_property,
73845adf 3205 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3206};
3207
3208static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3209 .get_modes = intel_dp_get_modes,
3210 .mode_valid = intel_dp_mode_valid,
df0e9248 3211 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3212};
3213
a4fc5ed6 3214static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3215 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3216};
3217
995b6762 3218static void
21d40d37 3219intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3220{
fa90ecef 3221 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3222
885a5014 3223 intel_dp_check_link_status(intel_dp);
c8110e52 3224}
6207937d 3225
e3421a18
ZW		 3226/* Return which DP Port should be selected for Transcoder DP control */
3227int
0206e353 3228intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3229{
3230 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3231 struct intel_encoder *intel_encoder;
3232 struct intel_dp *intel_dp;
e3421a18 3233
fa90ecef
PZ		 3234 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3235 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3236
fa90ecef
PZ		 3237 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3238 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3239 return intel_dp->output_reg;
e3421a18 3240 }
ea5b213a 3241
e3421a18
ZW		 3242 return -1;
3243}
3244
36e83a18 3245/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3246bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3247{
3248 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3249 union child_device_config *p_child;
36e83a18
ZY		 3250 int i;
3251
41aa3448 3252 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3253 return false;
3254
41aa3448
RV		 3255 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3256 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3257
768f69c9
PZ		 3258 if (p_child->common.dvo_port == PORT_IDPD &&
3259 p_child->common.device_type == DEVICE_TYPE_eDP)
36e83a18
ZY		 3260 return true;
3261 }
3262 return false;
3263}
3264
f684960e
CW		 3265static void
3266intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3267{
53b41837
YN		 3268 struct intel_connector *intel_connector = to_intel_connector(connector);
3269
3f43c48d 3270 intel_attach_force_audio_property(connector);
e953fd7b 3271 intel_attach_broadcast_rgb_property(connector);
55bc60db 3272 intel_dp->color_range_auto = true;
53b41837
YN		 3273
3274 if (is_edp(intel_dp)) {
3275 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3276 drm_object_attach_property(
3277 &connector->base,
53b41837 3278 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3279 DRM_MODE_SCALE_ASPECT);
3280 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3281 }
f684960e
CW		 3282}
3283
67a54566
DV		 3284static void
3285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3286 struct intel_dp *intel_dp,
3287 struct edp_power_seq *out)
67a54566
DV		 3288{
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct edp_power_seq cur, vbt, spec, final;
3291 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3292 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3293
3294 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3295 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3296 pp_on_reg = PCH_PP_ON_DELAYS;
3297 pp_off_reg = PCH_PP_OFF_DELAYS;
3298 pp_div_reg = PCH_PP_DIVISOR;
3299 } else {
bf13e81b
JN		 3300 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3301
3302 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3303 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3304 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3305 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3306 }
67a54566
DV		 3307
3308 /* Workaround: Need to write PP_CONTROL with the unlock key as
3309 * the very first thing. */
453c5420 3310 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3311 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3312
453c5420
JB		 3313 pp_on = I915_READ(pp_on_reg);
3314 pp_off = I915_READ(pp_off_reg);
3315 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3316
3317 /* Pull timing values out of registers */
3318 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3319 PANEL_POWER_UP_DELAY_SHIFT;
3320
3321 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3322 PANEL_LIGHT_ON_DELAY_SHIFT;
3323
3324 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3325 PANEL_LIGHT_OFF_DELAY_SHIFT;
3326
3327 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3328 PANEL_POWER_DOWN_DELAY_SHIFT;
3329
3330 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3331 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3332
3333 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3334 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3335
41aa3448 3336 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3337
3338 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3339 * our hw here, which are all in 100usec. */
3340 spec.t1_t3 = 210 * 10;
3341 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3342 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3343 spec.t10 = 500 * 10;
3344 /* This one is special and actually in units of 100ms, but zero
3345 * based in the hw (so we need to add 100 ms). But the sw vbt
3346 * table multiplies it with 1000 to make it in units of 100usec,
3347 * too. */
3348 spec.t11_t12 = (510 + 100) * 10;
3349
3350 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3351 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3352
3353 /* Use the max of the register settings and vbt. If both are
3354 * unset, fall back to the spec limits. */
3355#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3356 spec.field : \
3357 max(cur.field, vbt.field))
3358 assign_final(t1_t3);
3359 assign_final(t8);
3360 assign_final(t9);
3361 assign_final(t10);
3362 assign_final(t11_t12);
3363#undef assign_final
3364
3365#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3366 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3367 intel_dp->backlight_on_delay = get_delay(t8);
3368 intel_dp->backlight_off_delay = get_delay(t9);
3369 intel_dp->panel_power_down_delay = get_delay(t10);
3370 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3371#undef get_delay
3372
f30d26e4
JN		 3373 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3374 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3375 intel_dp->panel_power_cycle_delay);
3376
3377 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3378 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3379
3380 if (out)
3381 *out = final;
3382}
3383
3384static void
3385intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3386 struct intel_dp *intel_dp,
3387 struct edp_power_seq *seq)
3388{
3389 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3390 u32 pp_on, pp_off, pp_div, port_sel = 0;
3391 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3392 int pp_on_reg, pp_off_reg, pp_div_reg;
3393
3394 if (HAS_PCH_SPLIT(dev)) {
3395 pp_on_reg = PCH_PP_ON_DELAYS;
3396 pp_off_reg = PCH_PP_OFF_DELAYS;
3397 pp_div_reg = PCH_PP_DIVISOR;
3398 } else {
bf13e81b
JN		 3399 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3400
3401 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3402 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3403 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3404 }
3405
67a54566 3406 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3407 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3408 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3409 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3410 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3411 /* Compute the divisor for the pp clock, simply match the Bspec
3412 * formula. */
453c5420 3413 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3414 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3415 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3416
3417 /* Haswell doesn't have any port selection bits for the panel
3418 * power sequencer any more. */
bc7d38a4 3419 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3420 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3421 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3422 else
3423 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3424 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3425 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3426 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3427 else
a24c144c 3428 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3429 }
3430
453c5420
JB		 3431 pp_on |= port_sel;
3432
3433 I915_WRITE(pp_on_reg, pp_on);
3434 I915_WRITE(pp_off_reg, pp_off);
3435 I915_WRITE(pp_div_reg, pp_div);
67a54566 3436
67a54566 3437 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3438 I915_READ(pp_on_reg),
3439 I915_READ(pp_off_reg),
3440 I915_READ(pp_div_reg));
f684960e
CW		 3441}
3442
ed92f0b2
PZ		 3443static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3444 struct intel_connector *intel_connector)
3445{
3446 struct drm_connector *connector = &intel_connector->base;
3447 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3448 struct drm_device *dev = intel_dig_port->base.base.dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 struct drm_display_mode *fixed_mode = NULL;
3451 struct edp_power_seq power_seq = { 0 };
3452 bool has_dpcd;
3453 struct drm_display_mode *scan;
3454 struct edid *edid;
3455
3456 if (!is_edp(intel_dp))
3457 return true;
3458
3459 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3460
3461 /* Cache DPCD and EDID for edp. */
3462 ironlake_edp_panel_vdd_on(intel_dp);
3463 has_dpcd = intel_dp_get_dpcd(intel_dp);
3464 ironlake_edp_panel_vdd_off(intel_dp, false);
3465
3466 if (has_dpcd) {
3467 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3468 dev_priv->no_aux_handshake =
3469 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3470 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3471 } else {
3472 /* if this fails, presume the device is a ghost */
3473 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3474 return false;
3475 }
3476
3477 /* We now know it's not a ghost, init power sequence regs. */
3478 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3479 &power_seq);
3480
3481 ironlake_edp_panel_vdd_on(intel_dp);
3482 edid = drm_get_edid(connector, &intel_dp->adapter);
3483 if (edid) {
3484 if (drm_add_edid_modes(connector, edid)) {
3485 drm_mode_connector_update_edid_property(connector,
3486 edid);
3487 drm_edid_to_eld(connector, edid);
3488 } else {
3489 kfree(edid);
3490 edid = ERR_PTR(-EINVAL);
3491 }
3492 } else {
3493 edid = ERR_PTR(-ENOENT);
3494 }
3495 intel_connector->edid = edid;
3496
3497 /* prefer fixed mode from EDID if available */
3498 list_for_each_entry(scan, &connector->probed_modes, head) {
3499 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3500 fixed_mode = drm_mode_duplicate(dev, scan);
3501 break;
3502 }
3503 }
3504
3505 /* fallback to VBT if available for eDP */
3506 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3507 fixed_mode = drm_mode_duplicate(dev,
3508 dev_priv->vbt.lfp_lvds_vbt_mode);
3509 if (fixed_mode)
3510 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3511 }
3512
3513 ironlake_edp_panel_vdd_off(intel_dp, false);
3514
3515 intel_panel_init(&intel_connector->panel, fixed_mode);
3516 intel_panel_setup_backlight(connector);
3517
3518 return true;
3519}
3520
16c25533 3521bool
f0fec3f2
PZ		 3522intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3523 struct intel_connector *intel_connector)
a4fc5ed6 3524{
f0fec3f2
PZ		 3525 struct drm_connector *connector = &intel_connector->base;
3526 struct intel_dp *intel_dp = &intel_dig_port->dp;
3527 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3528 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3529 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3530 enum port port = intel_dig_port->port;
5eb08b69 3531 const char *name = NULL;
b2a14755 3532 int type, error;
a4fc5ed6 3533
0767935e
DV		 3534 /* Preserve the current hw state. */
3535 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3536 intel_dp->attached_connector = intel_connector;
3d3dc149 3537
f7d24902 3538 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3539 /*
3540 * FIXME : We need to initialize built-in panels before external panels.
3541 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3542 */
f7d24902
ID		 3543 switch (port) {
3544 case PORT_A:
b329530c 3545 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3546 break;
3547 case PORT_C:
3548 if (IS_VALLEYVIEW(dev))
3549 type = DRM_MODE_CONNECTOR_eDP;
3550 break;
3551 case PORT_D:
3552 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3553 type = DRM_MODE_CONNECTOR_eDP;
3554 break;
3555 default: /* silence GCC warning */
3556 break;
b329530c
AJ		 3557 }
3558
f7d24902
ID		 3559 /*
3560 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3561 * for DP the encoder type can be set by the caller to
3562 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3563 */
3564 if (type == DRM_MODE_CONNECTOR_eDP)
3565 intel_encoder->type = INTEL_OUTPUT_EDP;
3566
e7281eab
ID		 3567 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3568 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3569 port_name(port));
3570
b329530c 3571 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3572 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3573
a4fc5ed6
KP		 3574 connector->interlace_allowed = true;
3575 connector->doublescan_allowed = 0;
3576
f0fec3f2
PZ		 3577 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3578 ironlake_panel_vdd_work);
a4fc5ed6 3579
df0e9248 3580 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3581 drm_sysfs_connector_add(connector);
3582
affa9354 3583 if (HAS_DDI(dev))
bcbc889b
PZ		 3584 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3585 else
3586 intel_connector->get_hw_state = intel_connector_get_hw_state;
3587
9ed35ab1
PZ		 3588 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3589 if (HAS_DDI(dev)) {
3590 switch (intel_dig_port->port) {
3591 case PORT_A:
3592 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3593 break;
3594 case PORT_B:
3595 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3596 break;
3597 case PORT_C:
3598 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3599 break;
3600 case PORT_D:
3601 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3602 break;
3603 default:
3604 BUG();
3605 }
3606 }
e8cb4558 3607
a4fc5ed6 3608 /* Set up the DDC bus. */
ab9d7c30
PZ		 3609 switch (port) {
3610 case PORT_A:
1d843f9d 3611 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3612 name = "DPDDC-A";
3613 break;
3614 case PORT_B:
1d843f9d 3615 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3616 name = "DPDDC-B";
3617 break;
3618 case PORT_C:
1d843f9d 3619 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3620 name = "DPDDC-C";
3621 break;
3622 case PORT_D:
1d843f9d 3623 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3624 name = "DPDDC-D";
3625 break;
3626 default:
ad1c0b19 3627 BUG();
5eb08b69
ZW		 3628 }
3629
b2a14755
PZ		 3630 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3631 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3632 error, port_name(port));
c1f05264 3633
2b28bb1b
RV		 3634 intel_dp->psr_setup_done = false;
3635
b2f246a8 3636 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3637 i2c_del_adapter(&intel_dp->adapter);
3638 if (is_edp(intel_dp)) {
3639 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3640 mutex_lock(&dev->mode_config.mutex);
3641 ironlake_panel_vdd_off_sync(intel_dp);
3642 mutex_unlock(&dev->mode_config.mutex);
3643 }
b2f246a8
PZ		 3644 drm_sysfs_connector_remove(connector);
3645 drm_connector_cleanup(connector);
16c25533 3646 return false;
b2f246a8 3647 }
32f9d658 3648
f684960e
CW		 3649 intel_dp_add_properties(intel_dp, connector);
3650
a4fc5ed6
KP		 3651 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3652 * 0xd. Failure to do so will result in spurious interrupts being
3653 * generated on the port when a cable is not attached.
3654 */
3655 if (IS_G4X(dev) && !IS_GM45(dev)) {
3656 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3657 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3658 }
16c25533
PZ		 3659
3660 return true;
a4fc5ed6 3661}
f0fec3f2
PZ		 3662
3663void
3664intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3665{
3666 struct intel_digital_port *intel_dig_port;
3667 struct intel_encoder *intel_encoder;
3668 struct drm_encoder *encoder;
3669 struct intel_connector *intel_connector;
3670
b14c5679 3671 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3672 if (!intel_dig_port)
3673 return;
3674
b14c5679 3675 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3676 if (!intel_connector) {
3677 kfree(intel_dig_port);
3678 return;
3679 }
3680
3681 intel_encoder = &intel_dig_port->base;
3682 encoder = &intel_encoder->base;
3683
3684 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3685 DRM_MODE_ENCODER_TMDS);
3686
5bfe2ac0 3687 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3688 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3689 intel_encoder->disable = intel_disable_dp;
3690 intel_encoder->post_disable = intel_post_disable_dp;
3691 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3692 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3693 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3694 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3695 intel_encoder->pre_enable = vlv_pre_enable_dp;
3696 intel_encoder->enable = vlv_enable_dp;
3697 } else {
ecff4f3b
JN		 3698 intel_encoder->pre_enable = g4x_pre_enable_dp;
3699 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3700 }
f0fec3f2 3701
174edf1f 3702 intel_dig_port->port = port;
f0fec3f2
PZ		 3703 intel_dig_port->dp.output_reg = output_reg;
3704
00c09d70 3705 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3706 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3707 intel_encoder->cloneable = false;
3708 intel_encoder->hot_plug = intel_dp_hot_plug;
3709
15b1d171
PZ		 3710 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3711 drm_encoder_cleanup(encoder);
3712 kfree(intel_dig_port);
b2f246a8 3713 kfree(intel_connector);
15b1d171 3714 }
f0fec3f2 3715}
Linux kernel - Deliverables
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