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drm/i915: Add support for pipe_bpp readout
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } },
63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 94
a4fc5ed6 95static int
ea5b213a 96intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 97{
7183dc29 98 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 99
100 switch (max_link_bw) {
101 case DP_LINK_BW_1_62:
102 case DP_LINK_BW_2_7:
103 break;
d4eead50
ID		 104 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
105 max_link_bw = DP_LINK_BW_2_7;
106 break;
a4fc5ed6 107 default:
d4eead50
ID		 108 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
109 max_link_bw);
a4fc5ed6
KP		 110 max_link_bw = DP_LINK_BW_1_62;
111 break;
112 }
113 return max_link_bw;
114}
115
cd9dde44
AJ		 116/*
117 * The units on the numbers in the next two are... bizarre. Examples will
118 * make it clearer; this one parallels an example in the eDP spec.
119 *
120 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
121 *
122 * 270000 * 1 * 8 / 10 == 216000
123 *
124 * The actual data capacity of that configuration is 2.16Gbit/s, so the
125 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
126 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
127 * 119000. At 18bpp that's 2142000 kilobits per second.
128 *
129 * Thus the strange-looking division by 10 in intel_dp_link_required, to
130 * get the result in decakilobits instead of kilobits.
131 */
132
a4fc5ed6 133static int
c898261c 134intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 135{
cd9dde44 136 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 137}
138
fe27d53e
DA		 139static int
140intel_dp_max_data_rate(int max_link_clock, int max_lanes)
141{
142 return (max_link_clock * max_lanes * 8) / 10;
143}
144
a4fc5ed6
KP		 145static int
146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode)
148{
df0e9248 149 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 150 struct intel_connector *intel_connector = to_intel_connector(connector);
151 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 152 int target_clock = mode->clock;
153 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 154
dd06f90e
JN		 155 if (is_edp(intel_dp) && fixed_mode) {
156 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 157 return MODE_PANEL;
158
dd06f90e 159 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 160 return MODE_PANEL;
03afc4a2
DV		 161
162 target_clock = fixed_mode->clock;
7de56f43
ZY		 163 }
164
36008365
DV		 165 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
166 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
169 mode_rate = intel_dp_link_required(target_clock, 18);
170
171 if (mode_rate > max_rate)
c4867936 172 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 173
174 if (mode->clock < 10000)
175 return MODE_CLOCK_LOW;
176
0af78a2b
DV		 177 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
178 return MODE_H_ILLEGAL;
179
a4fc5ed6
KP		 180 return MODE_OK;
181}
182
183static uint32_t
184pack_aux(uint8_t *src, int src_bytes)
185{
186 int i;
187 uint32_t v = 0;
188
189 if (src_bytes > 4)
190 src_bytes = 4;
191 for (i = 0; i < src_bytes; i++)
192 v |= ((uint32_t) src[i]) << ((3-i) * 8);
193 return v;
194}
195
196static void
197unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
198{
199 int i;
200 if (dst_bytes > 4)
201 dst_bytes = 4;
202 for (i = 0; i < dst_bytes; i++)
203 dst[i] = src >> ((3-i) * 8);
204}
205
fb0f8fbf
KP		 206/* hrawclock is 1/4 the FSB frequency */
207static int
208intel_hrawclk(struct drm_device *dev)
209{
210 struct drm_i915_private *dev_priv = dev->dev_private;
211 uint32_t clkcfg;
212
9473c8f4
VP		 213 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
214 if (IS_VALLEYVIEW(dev))
215 return 200;
216
fb0f8fbf
KP		 217 clkcfg = I915_READ(CLKCFG);
218 switch (clkcfg & CLKCFG_FSB_MASK) {
219 case CLKCFG_FSB_400:
220 return 100;
221 case CLKCFG_FSB_533:
222 return 133;
223 case CLKCFG_FSB_667:
224 return 166;
225 case CLKCFG_FSB_800:
226 return 200;
227 case CLKCFG_FSB_1067:
228 return 266;
229 case CLKCFG_FSB_1333:
230 return 333;
231 /* these two are just a guess; one of them might be right */
232 case CLKCFG_FSB_1600:
233 case CLKCFG_FSB_1600_ALT:
234 return 400;
235 default:
236 return 133;
237 }
238}
239
bf13e81b
JN		 240static void
241intel_dp_init_panel_power_sequencer(struct drm_device *dev,
242 struct intel_dp *intel_dp,
243 struct edp_power_seq *out);
244static void
245intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
246 struct intel_dp *intel_dp,
247 struct edp_power_seq *out);
248
249static enum pipe
250vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
251{
252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
253 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 enum port port = intel_dig_port->port;
257 enum pipe pipe;
258
259 /* modeset should have pipe */
260 if (crtc)
261 return to_intel_crtc(crtc)->pipe;
262
263 /* init time, try to find a pipe with this port selected */
264 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
265 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
266 PANEL_PORT_SELECT_MASK;
267 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
268 return pipe;
269 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
270 return pipe;
271 }
272
273 /* shrug */
274 return PIPE_A;
275}
276
277static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
278{
279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
280
281 if (HAS_PCH_SPLIT(dev))
282 return PCH_PP_CONTROL;
283 else
284 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
285}
286
287static u32 _pp_stat_reg(struct intel_dp *intel_dp)
288{
289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
290
291 if (HAS_PCH_SPLIT(dev))
292 return PCH_PP_STATUS;
293 else
294 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
295}
296
ebf33b18
KP		 297static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
298{
30add22d 299 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 300 struct drm_i915_private *dev_priv = dev->dev_private;
301
bf13e81b 302 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 303}
304
305static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 311}
312
9b984dae
KP		 313static void
314intel_dp_check_edp(struct intel_dp *intel_dp)
315{
30add22d 316 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 317 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 318
9b984dae
KP		 319 if (!is_edp(intel_dp))
320 return;
453c5420 321
ebf33b18 322 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 323 WARN(1, "eDP powered off while attempting aux channel communication.\n");
324 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 325 I915_READ(_pp_stat_reg(intel_dp)),
326 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 327 }
328}
329
9ee32fea
DV		 330static uint32_t
331intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 336 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 337 uint32_t status;
338 bool done;
339
ef04f00d 340#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 341 if (has_aux_irq)
b18ac466 342 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 343 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 344 else
345 done = wait_for_atomic(C, 10) == 0;
346 if (!done)
347 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
348 has_aux_irq);
349#undef C
350
351 return status;
352}
353
bc86625a
CW		 354static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
355 int index)
a4fc5ed6 356{
174edf1f
PZ		 357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
358 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 359 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 360
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
a62d0834 368 if (IS_VALLEYVIEW(dev)) {
bc86625a 369 return index ? 0 : 100;
a62d0834 370 } else if (intel_dig_port->port == PORT_A) {
bc86625a
CW		 371 if (index)
372 return 0;
affa9354 373 if (HAS_DDI(dev))
bc86625a 374 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 375 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 376 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 377 else
b84a1cf8 378 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 379 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
380 /* Workaround for non-ULT HSW */
bc86625a
CW		 381 switch (index) {
382 case 0: return 63;
383 case 1: return 72;
384 default: return 0;
385 }
2c55c336 386 } else if (HAS_PCH_SPLIT(dev)) {
bc86625a 387 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 388 } else {
bc86625a 389 return index ? 0 :intel_hrawclk(dev) / 2;
2c55c336 390 }
b84a1cf8
RV		 391}
392
393static int
394intel_dp_aux_ch(struct intel_dp *intel_dp,
395 uint8_t *send, int send_bytes,
396 uint8_t *recv, int recv_size)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
402 uint32_t ch_data = ch_ctl + 4;
bc86625a 403 uint32_t aux_clock_divider;
b84a1cf8
RV		 404 int i, ret, recv_bytes;
405 uint32_t status;
bc86625a 406 int try, precharge, clock = 0;
b84a1cf8
RV		 407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
408
409 /* dp aux is extremely sensitive to irq latency, hence request the
410 * lowest possible wakeup latency and so prevent the cpu from going into
411 * deep sleep states.
412 */
413 pm_qos_update_request(&dev_priv->pm_qos, 0);
414
415 intel_dp_check_edp(intel_dp);
5eb08b69 416
6b4e0a93
DV		 417 if (IS_GEN6(dev))
418 precharge = 3;
419 else
420 precharge = 5;
421
c67a470b
PZ		 422 intel_aux_display_runtime_get(dev_priv);
423
11bee43e
JB		 424 /* Try to wait for any previous AUX channel activity */
425 for (try = 0; try < 3; try++) {
ef04f00d 426 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 427 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
428 break;
429 msleep(1);
430 }
431
432 if (try == 3) {
433 WARN(1, "dp_aux_ch not started status 0x%08x\n",
434 I915_READ(ch_ctl));
9ee32fea
DV		 435 ret = -EBUSY;
436 goto out;
4f7f7b7e
CW		 437 }
438
bc86625a
CW		 439 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
440 /* Must try at least 3 times according to DP spec */
441 for (try = 0; try < 5; try++) {
442 /* Load the send data into the aux channel data registers */
443 for (i = 0; i < send_bytes; i += 4)
444 I915_WRITE(ch_data + i,
445 pack_aux(send + i, send_bytes - i));
446
447 /* Send the command and wait for it to complete */
448 I915_WRITE(ch_ctl,
449 DP_AUX_CH_CTL_SEND_BUSY |
450 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
451 DP_AUX_CH_CTL_TIME_OUT_400us |
452 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
453 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
454 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
455 DP_AUX_CH_CTL_DONE |
456 DP_AUX_CH_CTL_TIME_OUT_ERROR |
457 DP_AUX_CH_CTL_RECEIVE_ERROR);
458
459 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
460
461 /* Clear done status and any errors */
462 I915_WRITE(ch_ctl,
463 status |
464 DP_AUX_CH_CTL_DONE |
465 DP_AUX_CH_CTL_TIME_OUT_ERROR |
466 DP_AUX_CH_CTL_RECEIVE_ERROR);
467
468 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
469 DP_AUX_CH_CTL_RECEIVE_ERROR))
470 continue;
471 if (status & DP_AUX_CH_CTL_DONE)
472 break;
473 }
4f7f7b7e 474 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 475 break;
476 }
477
a4fc5ed6 478 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 479 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 480 ret = -EBUSY;
481 goto out;
a4fc5ed6
KP		 482 }
483
484 /* Check for timeout or receive error.
485 * Timeouts occur when the sink is not connected
486 */
a5b3da54 487 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 488 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 489 ret = -EIO;
490 goto out;
a5b3da54 491 }
1ae8c0a5
KP		 492
493 /* Timeouts occur when the device isn't connected, so they're
494 * "normal" -- don't fill the kernel log with these */
a5b3da54 495 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 496 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 497 ret = -ETIMEDOUT;
498 goto out;
a4fc5ed6
KP		 499 }
500
501 /* Unload any bytes sent back from the other side */
502 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
503 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 504 if (recv_bytes > recv_size)
505 recv_bytes = recv_size;
0206e353 506
4f7f7b7e
CW		 507 for (i = 0; i < recv_bytes; i += 4)
508 unpack_aux(I915_READ(ch_data + i),
509 recv + i, recv_bytes - i);
a4fc5ed6 510
9ee32fea
DV		 511 ret = recv_bytes;
512out:
513 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 514 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 515
516 return ret;
a4fc5ed6
KP		 517}
518
519/* Write data to the aux channel in native mode */
520static int
ea5b213a 521intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 522 uint16_t address, uint8_t *send, int send_bytes)
523{
524 int ret;
525 uint8_t msg[20];
526 int msg_bytes;
527 uint8_t ack;
528
9b984dae 529 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 530 if (send_bytes > 16)
531 return -1;
532 msg[0] = AUX_NATIVE_WRITE << 4;
533 msg[1] = address >> 8;
eebc863e 534 msg[2] = address & 0xff;
a4fc5ed6
KP		 535 msg[3] = send_bytes - 1;
536 memcpy(&msg[4], send, send_bytes);
537 msg_bytes = send_bytes + 4;
538 for (;;) {
ea5b213a 539 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 540 if (ret < 0)
541 return ret;
542 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
543 break;
544 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
545 udelay(100);
546 else
a5b3da54 547 return -EIO;
a4fc5ed6
KP		 548 }
549 return send_bytes;
550}
551
552/* Write a single byte to the aux channel in native mode */
553static int
ea5b213a 554intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 555 uint16_t address, uint8_t byte)
556{
ea5b213a 557 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 558}
559
560/* read bytes from a native aux channel */
561static int
ea5b213a 562intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 563 uint16_t address, uint8_t *recv, int recv_bytes)
564{
565 uint8_t msg[4];
566 int msg_bytes;
567 uint8_t reply[20];
568 int reply_bytes;
569 uint8_t ack;
570 int ret;
571
9b984dae 572 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 573 msg[0] = AUX_NATIVE_READ << 4;
574 msg[1] = address >> 8;
575 msg[2] = address & 0xff;
576 msg[3] = recv_bytes - 1;
577
578 msg_bytes = 4;
579 reply_bytes = recv_bytes + 1;
580
581 for (;;) {
ea5b213a 582 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 583 reply, reply_bytes);
a5b3da54
KP		 584 if (ret == 0)
585 return -EPROTO;
586 if (ret < 0)
a4fc5ed6
KP		 587 return ret;
588 ack = reply[0];
589 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
590 memcpy(recv, reply + 1, ret - 1);
591 return ret - 1;
592 }
593 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
594 udelay(100);
595 else
a5b3da54 596 return -EIO;
a4fc5ed6
KP		 597 }
598}
599
600static int
ab2c0672
DA		 601intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
602 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 603{
ab2c0672 604 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 605 struct intel_dp *intel_dp = container_of(adapter,
606 struct intel_dp,
607 adapter);
ab2c0672
DA		 608 uint16_t address = algo_data->address;
609 uint8_t msg[5];
610 uint8_t reply[2];
8316f337 611 unsigned retry;
ab2c0672
DA		 612 int msg_bytes;
613 int reply_bytes;
614 int ret;
615
9b984dae 616 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 617 /* Set up the command byte */
618 if (mode & MODE_I2C_READ)
619 msg[0] = AUX_I2C_READ << 4;
620 else
621 msg[0] = AUX_I2C_WRITE << 4;
622
623 if (!(mode & MODE_I2C_STOP))
624 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 625
ab2c0672
DA		 626 msg[1] = address >> 8;
627 msg[2] = address;
628
629 switch (mode) {
630 case MODE_I2C_WRITE:
631 msg[3] = 0;
632 msg[4] = write_byte;
633 msg_bytes = 5;
634 reply_bytes = 1;
635 break;
636 case MODE_I2C_READ:
637 msg[3] = 0;
638 msg_bytes = 4;
639 reply_bytes = 2;
640 break;
641 default:
642 msg_bytes = 3;
643 reply_bytes = 1;
644 break;
645 }
646
8316f337
DF		 647 for (retry = 0; retry < 5; retry++) {
648 ret = intel_dp_aux_ch(intel_dp,
649 msg, msg_bytes,
650 reply, reply_bytes);
ab2c0672 651 if (ret < 0) {
3ff99164 652 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 653 return ret;
654 }
8316f337
DF		 655
656 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
657 case AUX_NATIVE_REPLY_ACK:
658 /* I2C-over-AUX Reply field is only valid
659 * when paired with AUX ACK.
660 */
661 break;
662 case AUX_NATIVE_REPLY_NACK:
663 DRM_DEBUG_KMS("aux_ch native nack\n");
664 return -EREMOTEIO;
665 case AUX_NATIVE_REPLY_DEFER:
666 udelay(100);
667 continue;
668 default:
669 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
670 reply[0]);
671 return -EREMOTEIO;
672 }
673
ab2c0672
DA		 674 switch (reply[0] & AUX_I2C_REPLY_MASK) {
675 case AUX_I2C_REPLY_ACK:
676 if (mode == MODE_I2C_READ) {
677 *read_byte = reply[1];
678 }
679 return reply_bytes - 1;
680 case AUX_I2C_REPLY_NACK:
8316f337 681 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 682 return -EREMOTEIO;
683 case AUX_I2C_REPLY_DEFER:
8316f337 684 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 685 udelay(100);
686 break;
687 default:
8316f337 688 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 689 return -EREMOTEIO;
690 }
691 }
8316f337
DF		 692
693 DRM_ERROR("too many retries, giving up\n");
694 return -EREMOTEIO;
a4fc5ed6
KP		 695}
696
697static int
ea5b213a 698intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 699 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 700{
0b5c541b
KP		 701 int ret;
702
d54e9d28 703 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 704 intel_dp->algo.running = false;
705 intel_dp->algo.address = 0;
706 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
707
0206e353 708 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 709 intel_dp->adapter.owner = THIS_MODULE;
710 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 711 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 712 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
713 intel_dp->adapter.algo_data = &intel_dp->algo;
714 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
715
0b5c541b
KP		 716 ironlake_edp_panel_vdd_on(intel_dp);
717 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 718 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 719 return ret;
a4fc5ed6
KP		 720}
721
c6bb3538
DV		 722static void
723intel_dp_set_clock(struct intel_encoder *encoder,
724 struct intel_crtc_config *pipe_config, int link_bw)
725{
726 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 727 const struct dp_link_dpll *divisor = NULL;
728 int i, count = 0;
c6bb3538
DV		 729
730 if (IS_G4X(dev)) {
9dd4ffdf
CML		 731 divisor = gen4_dpll;
732 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 733 } else if (IS_HASWELL(dev)) {
734 /* Haswell has special-purpose DP DDI clocks. */
735 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 736 divisor = pch_dpll;
737 count = ARRAY_SIZE(pch_dpll);
c6bb3538 738 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 739 divisor = vlv_dpll;
740 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 741 }
9dd4ffdf
CML		 742
743 if (divisor && count) {
744 for (i = 0; i < count; i++) {
745 if (link_bw == divisor[i].link_bw) {
746 pipe_config->dpll = divisor[i].dpll;
747 pipe_config->clock_set = true;
748 break;
749 }
750 }
751 }
c6bb3538
DV		 752}
753
00c09d70 754bool
5bfe2ac0
DV		 755intel_dp_compute_config(struct intel_encoder *encoder,
756 struct intel_crtc_config *pipe_config)
a4fc5ed6 757{
5bfe2ac0 758 struct drm_device *dev = encoder->base.dev;
36008365 759 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 760 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 761 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 762 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 763 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 764 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 765 int lane_count, clock;
397fe157 766 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 767 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 768 int bpp, mode_rate;
a4fc5ed6 769 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 770 int link_avail, link_clock;
a4fc5ed6 771
bc7d38a4 772 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 773 pipe_config->has_pch_encoder = true;
774
03afc4a2 775 pipe_config->has_dp_encoder = true;
a4fc5ed6 776
dd06f90e
JN		 777 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
778 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
779 adjusted_mode);
2dd24552
JB		 780 if (!HAS_PCH_SPLIT(dev))
781 intel_gmch_panel_fitting(intel_crtc, pipe_config,
782 intel_connector->panel.fitting_mode);
783 else
b074cec8
JB		 784 intel_pch_panel_fitting(intel_crtc, pipe_config,
785 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 786 }
787
cb1793ce 788 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 789 return false;
790
083f9560
DV		 791 DRM_DEBUG_KMS("DP link computation with max lane count %i "
792 "max bw %02x pixel clock %iKHz\n",
71244653 793 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 794
36008365
DV		 795 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
796 * bpc in between. */
3e7ca985 797 bpp = pipe_config->pipe_bpp;
7984211e
ID		 798 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
799 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
800 dev_priv->vbt.edp_bpp);
e1b73cba 801 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
7984211e 802 }
657445fe 803
36008365 804 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 805 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 806
807 for (clock = 0; clock <= max_clock; clock++) {
808 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
809 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
810 link_avail = intel_dp_max_data_rate(link_clock,
811 lane_count);
812
813 if (mode_rate <= link_avail) {
814 goto found;
815 }
816 }
817 }
818 }
c4867936 819
36008365 820 return false;
3685a8f3 821
36008365 822found:
55bc60db
VS		 823 if (intel_dp->color_range_auto) {
824 /*
825 * See:
826 * CEA-861-E - 5.1 Default Encoding Parameters
827 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
828 */
18316c8c 829 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 830 intel_dp->color_range = DP_COLOR_RANGE_16_235;
831 else
832 intel_dp->color_range = 0;
833 }
834
3685a8f3 835 if (intel_dp->color_range)
50f3b016 836 pipe_config->limited_color_range = true;
a4fc5ed6 837
36008365
DV		 838 intel_dp->link_bw = bws[clock];
839 intel_dp->lane_count = lane_count;
657445fe 840 pipe_config->pipe_bpp = bpp;
ff9a6750 841 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 842
36008365
DV		 843 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
844 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 845 pipe_config->port_clock, bpp);
36008365
DV		 846 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
847 mode_rate, link_avail);
a4fc5ed6 848
03afc4a2 849 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 850 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 851 &pipe_config->dp_m_n);
9d1a455b 852
c6bb3538
DV		 853 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
854
03afc4a2 855 return true;
a4fc5ed6
KP		 856}
857
247d89f6
PZ		 858void intel_dp_init_link_config(struct intel_dp *intel_dp)
859{
860 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
861 intel_dp->link_configuration[0] = intel_dp->link_bw;
862 intel_dp->link_configuration[1] = intel_dp->lane_count;
863 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
864 /*
865 * Check for DPCD version > 1.1 and enhanced framing support
866 */
867 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
868 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
869 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
870 }
871}
872
7c62a164 873static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 874{
7c62a164
DV		 875 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
876 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
877 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 878 struct drm_i915_private *dev_priv = dev->dev_private;
879 u32 dpa_ctl;
880
ff9a6750 881 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 882 dpa_ctl = I915_READ(DP_A);
883 dpa_ctl &= ~DP_PLL_FREQ_MASK;
884
ff9a6750 885 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 886 /* For a long time we've carried around a ILK-DevA w/a for the
887 * 160MHz clock. If we're really unlucky, it's still required.
888 */
889 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 890 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 891 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 892 } else {
893 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 894 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 895 }
1ce17038 896
ea9b6006
DV		 897 I915_WRITE(DP_A, dpa_ctl);
898
899 POSTING_READ(DP_A);
900 udelay(500);
901}
902
b934223d 903static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 904{
b934223d 905 struct drm_device *dev = encoder->base.dev;
417e822d 906 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 907 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 908 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 909 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
910 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 911
417e822d 912 /*
1a2eb460 913 * There are four kinds of DP registers:
417e822d
KP		 914 *
915 * IBX PCH
1a2eb460
KP		 916 * SNB CPU
917 * IVB CPU
417e822d
KP		 918 * CPT PCH
919 *
920 * IBX PCH and CPU are the same for almost everything,
921 * except that the CPU DP PLL is configured in this
922 * register
923 *
924 * CPT PCH is quite different, having many bits moved
925 * to the TRANS_DP_CTL register instead. That
926 * configuration happens (oddly) in ironlake_pch_enable
927 */
9c9e7927 928
417e822d
KP		 929 /* Preserve the BIOS-computed detected bit. This is
930 * supposed to be read-only.
931 */
932 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 933
417e822d 934 /* Handle DP bits in common between all three register formats */
417e822d 935 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 936 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 937
e0dac65e
WF		 938 if (intel_dp->has_audio) {
939 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 940 pipe_name(crtc->pipe));
ea5b213a 941 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 942 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 943 }
247d89f6
PZ		 944
945 intel_dp_init_link_config(intel_dp);
a4fc5ed6 946
417e822d 947 /* Split out the IBX/CPU vs CPT settings */
32f9d658 948
bc7d38a4 949 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 950 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
951 intel_dp->DP |= DP_SYNC_HS_HIGH;
952 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
953 intel_dp->DP |= DP_SYNC_VS_HIGH;
954 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
955
956 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
957 intel_dp->DP |= DP_ENHANCED_FRAMING;
958
7c62a164 959 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 960 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 961 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 962 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 963
964 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
965 intel_dp->DP |= DP_SYNC_HS_HIGH;
966 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
967 intel_dp->DP |= DP_SYNC_VS_HIGH;
968 intel_dp->DP |= DP_LINK_TRAIN_OFF;
969
970 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
971 intel_dp->DP |= DP_ENHANCED_FRAMING;
972
7c62a164 973 if (crtc->pipe == 1)
417e822d 974 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 975 } else {
976 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 977 }
ea9b6006 978
bc7d38a4 979 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 980 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 981}
982
99ea7127
KP		 983#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
984#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
985
986#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
987#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
988
989#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
990#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
991
992static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
993 u32 mask,
994 u32 value)
bd943159 995{
30add22d 996 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 997 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 998 u32 pp_stat_reg, pp_ctrl_reg;
999
bf13e81b
JN		 1000 pp_stat_reg = _pp_stat_reg(intel_dp);
1001 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1002
99ea7127 1003 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1004 mask, value,
1005 I915_READ(pp_stat_reg),
1006 I915_READ(pp_ctrl_reg));
32ce697c 1007
453c5420 1008 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1009 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1010 I915_READ(pp_stat_reg),
1011 I915_READ(pp_ctrl_reg));
32ce697c 1012 }
99ea7127 1013}
32ce697c 1014
99ea7127
KP		 1015static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1016{
1017 DRM_DEBUG_KMS("Wait for panel power on\n");
1018 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1019}
1020
99ea7127
KP		 1021static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1022{
1023 DRM_DEBUG_KMS("Wait for panel power off time\n");
1024 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1025}
1026
1027static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1028{
1029 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1030 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1031}
1032
1033
832dd3c1
KP		 1034/* Read the current pp_control value, unlocking the register if it
1035 * is locked
1036 */
1037
453c5420 1038static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1039{
453c5420
JB		 1040 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 u32 control;
832dd3c1 1043
bf13e81b 1044 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1045 control &= ~PANEL_UNLOCK_MASK;
1046 control |= PANEL_UNLOCK_REGS;
1047 return control;
bd943159
KP		 1048}
1049
82a4d9c0 1050void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1051{
30add22d 1052 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1053 struct drm_i915_private *dev_priv = dev->dev_private;
1054 u32 pp;
453c5420 1055 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1056
97af61f5
KP		 1057 if (!is_edp(intel_dp))
1058 return;
f01eca2e 1059 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1060
bd943159
KP		 1061 WARN(intel_dp->want_panel_vdd,
1062 "eDP VDD already requested on\n");
1063
1064 intel_dp->want_panel_vdd = true;
99ea7127 1065
bd943159
KP		 1066 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1067 DRM_DEBUG_KMS("eDP VDD already on\n");
1068 return;
1069 }
1070
99ea7127
KP		 1071 if (!ironlake_edp_have_panel_power(intel_dp))
1072 ironlake_wait_panel_power_cycle(intel_dp);
1073
453c5420 1074 pp = ironlake_get_pp_control(intel_dp);
5d613501 1075 pp |= EDP_FORCE_VDD;
ebf33b18 1076
bf13e81b
JN		 1077 pp_stat_reg = _pp_stat_reg(intel_dp);
1078 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1079
1080 I915_WRITE(pp_ctrl_reg, pp);
1081 POSTING_READ(pp_ctrl_reg);
1082 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1083 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1084 /*
1085 * If the panel wasn't on, delay before accessing aux channel
1086 */
1087 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1088 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1089 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1090 }
5d613501
JB		 1091}
1092
bd943159 1093static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1094{
30add22d 1095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1096 struct drm_i915_private *dev_priv = dev->dev_private;
1097 u32 pp;
453c5420 1098 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1099
a0e99e68
DV		 1100 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1101
bd943159 1102 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1103 pp = ironlake_get_pp_control(intel_dp);
bd943159 1104 pp &= ~EDP_FORCE_VDD;
bd943159 1105
bf13e81b
JN		 1106 pp_stat_reg = _pp_ctrl_reg(intel_dp);
1107 pp_ctrl_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1108
1109 I915_WRITE(pp_ctrl_reg, pp);
1110 POSTING_READ(pp_ctrl_reg);
99ea7127 1111
453c5420
JB		 1112 /* Make sure sequencer is idle before allowing subsequent activity */
1113 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1114 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1115 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1116 }
1117}
5d613501 1118
bd943159
KP		 1119static void ironlake_panel_vdd_work(struct work_struct *__work)
1120{
1121 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1122 struct intel_dp, panel_vdd_work);
30add22d 1123 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1124
627f7675 1125 mutex_lock(&dev->mode_config.mutex);
bd943159 1126 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1127 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1128}
1129
82a4d9c0 1130void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1131{
97af61f5
KP		 1132 if (!is_edp(intel_dp))
1133 return;
5d613501 1134
bd943159
KP		 1135 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1136 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1137
bd943159
KP		 1138 intel_dp->want_panel_vdd = false;
1139
1140 if (sync) {
1141 ironlake_panel_vdd_off_sync(intel_dp);
1142 } else {
1143 /*
1144 * Queue the timer to fire a long
1145 * time from now (relative to the power down delay)
1146 * to keep the panel power up across a sequence of operations
1147 */
1148 schedule_delayed_work(&intel_dp->panel_vdd_work,
1149 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1150 }
5d613501
JB		 1151}
1152
82a4d9c0 1153void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1154{
30add22d 1155 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1156 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1157 u32 pp;
453c5420 1158 u32 pp_ctrl_reg;
9934c132 1159
97af61f5 1160 if (!is_edp(intel_dp))
bd943159 1161 return;
99ea7127
KP		 1162
1163 DRM_DEBUG_KMS("Turn eDP power on\n");
1164
1165 if (ironlake_edp_have_panel_power(intel_dp)) {
1166 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1167 return;
99ea7127 1168 }
9934c132 1169
99ea7127 1170 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1171
bf13e81b 1172 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1173 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1174 if (IS_GEN5(dev)) {
1175 /* ILK workaround: disable reset around power sequence */
1176 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1177 I915_WRITE(pp_ctrl_reg, pp);
1178 POSTING_READ(pp_ctrl_reg);
05ce1a49 1179 }
37c6c9b0 1180
1c0ae80a 1181 pp |= POWER_TARGET_ON;
99ea7127
KP		 1182 if (!IS_GEN5(dev))
1183 pp |= PANEL_POWER_RESET;
1184
453c5420
JB		 1185 I915_WRITE(pp_ctrl_reg, pp);
1186 POSTING_READ(pp_ctrl_reg);
9934c132 1187
99ea7127 1188 ironlake_wait_panel_on(intel_dp);
9934c132 1189
05ce1a49
KP		 1190 if (IS_GEN5(dev)) {
1191 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1192 I915_WRITE(pp_ctrl_reg, pp);
1193 POSTING_READ(pp_ctrl_reg);
05ce1a49 1194 }
9934c132
JB		 1195}
1196
82a4d9c0 1197void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1198{
30add22d 1199 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1200 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1201 u32 pp;
453c5420 1202 u32 pp_ctrl_reg;
9934c132 1203
97af61f5
KP		 1204 if (!is_edp(intel_dp))
1205 return;
37c6c9b0 1206
99ea7127 1207 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1208
6cb49835 1209 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1210
453c5420 1211 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1212 /* We need to switch off panel power _and_ force vdd, for otherwise some
1213 * panels get very unhappy and cease to work. */
1214 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1215
bf13e81b 1216 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1217
1218 I915_WRITE(pp_ctrl_reg, pp);
1219 POSTING_READ(pp_ctrl_reg);
9934c132 1220
35a38556
DV		 1221 intel_dp->want_panel_vdd = false;
1222
99ea7127 1223 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1224}
1225
d6c50ff8 1226void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1227{
da63a9f2
PZ		 1228 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1229 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1230 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1231 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1232 u32 pp;
453c5420 1233 u32 pp_ctrl_reg;
32f9d658 1234
f01eca2e
KP		 1235 if (!is_edp(intel_dp))
1236 return;
1237
28c97730 1238 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1239 /*
1240 * If we enable the backlight right away following a panel power
1241 * on, we may see slight flicker as the panel syncs with the eDP
1242 * link. So delay a bit to make sure the image is solid before
1243 * allowing it to appear.
1244 */
f01eca2e 1245 msleep(intel_dp->backlight_on_delay);
453c5420 1246 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1247 pp |= EDP_BLC_ENABLE;
453c5420 1248
bf13e81b 1249 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1250
1251 I915_WRITE(pp_ctrl_reg, pp);
1252 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1253
1254 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1255}
1256
d6c50ff8 1257void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1258{
30add22d 1259 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 u32 pp;
453c5420 1262 u32 pp_ctrl_reg;
32f9d658 1263
f01eca2e
KP		 1264 if (!is_edp(intel_dp))
1265 return;
1266
035aa3de
DV		 1267 intel_panel_disable_backlight(dev);
1268
28c97730 1269 DRM_DEBUG_KMS("\n");
453c5420 1270 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1271 pp &= ~EDP_BLC_ENABLE;
453c5420 1272
bf13e81b 1273 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1274
1275 I915_WRITE(pp_ctrl_reg, pp);
1276 POSTING_READ(pp_ctrl_reg);
f01eca2e 1277 msleep(intel_dp->backlight_off_delay);
32f9d658 1278}
a4fc5ed6 1279
2bd2ad64 1280static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1281{
da63a9f2
PZ		 1282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1283 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1284 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1285 struct drm_i915_private *dev_priv = dev->dev_private;
1286 u32 dpa_ctl;
1287
2bd2ad64
DV		 1288 assert_pipe_disabled(dev_priv,
1289 to_intel_crtc(crtc)->pipe);
1290
d240f20f
JB		 1291 DRM_DEBUG_KMS("\n");
1292 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1293 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1294 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1295
1296 /* We don't adjust intel_dp->DP while tearing down the link, to
1297 * facilitate link retraining (e.g. after hotplug). Hence clear all
1298 * enable bits here to ensure that we don't enable too much. */
1299 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1300 intel_dp->DP |= DP_PLL_ENABLE;
1301 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1302 POSTING_READ(DP_A);
1303 udelay(200);
d240f20f
JB		 1304}
1305
2bd2ad64 1306static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1307{
da63a9f2
PZ		 1308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1310 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1311 struct drm_i915_private *dev_priv = dev->dev_private;
1312 u32 dpa_ctl;
1313
2bd2ad64
DV		 1314 assert_pipe_disabled(dev_priv,
1315 to_intel_crtc(crtc)->pipe);
1316
d240f20f 1317 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1318 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1319 "dp pll off, should be on\n");
1320 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1321
1322 /* We can't rely on the value tracked for the DP register in
1323 * intel_dp->DP because link_down must not change that (otherwise link
1324 * re-training will fail. */
298b0b39 1325 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1326 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1327 POSTING_READ(DP_A);
d240f20f
JB		 1328 udelay(200);
1329}
1330
c7ad3810 1331/* If the sink supports it, try to set the power state appropriately */
c19b0669 1332void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1333{
1334 int ret, i;
1335
1336 /* Should have a valid DPCD by this point */
1337 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1338 return;
1339
1340 if (mode != DRM_MODE_DPMS_ON) {
1341 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1342 DP_SET_POWER_D3);
1343 if (ret != 1)
1344 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1345 } else {
1346 /*
1347 * When turning on, we need to retry for 1ms to give the sink
1348 * time to wake up.
1349 */
1350 for (i = 0; i < 3; i++) {
1351 ret = intel_dp_aux_native_write_1(intel_dp,
1352 DP_SET_POWER,
1353 DP_SET_POWER_D0);
1354 if (ret == 1)
1355 break;
1356 msleep(1);
1357 }
1358 }
1359}
1360
19d8fe15
DV		 1361static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1362 enum pipe *pipe)
d240f20f 1363{
19d8fe15 1364 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1365 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1366 struct drm_device *dev = encoder->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 u32 tmp = I915_READ(intel_dp->output_reg);
1369
1370 if (!(tmp & DP_PORT_EN))
1371 return false;
1372
bc7d38a4 1373 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1374 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1375 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1376 *pipe = PORT_TO_PIPE(tmp);
1377 } else {
1378 u32 trans_sel;
1379 u32 trans_dp;
1380 int i;
1381
1382 switch (intel_dp->output_reg) {
1383 case PCH_DP_B:
1384 trans_sel = TRANS_DP_PORT_SEL_B;
1385 break;
1386 case PCH_DP_C:
1387 trans_sel = TRANS_DP_PORT_SEL_C;
1388 break;
1389 case PCH_DP_D:
1390 trans_sel = TRANS_DP_PORT_SEL_D;
1391 break;
1392 default:
1393 return true;
1394 }
1395
1396 for_each_pipe(i) {
1397 trans_dp = I915_READ(TRANS_DP_CTL(i));
1398 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1399 *pipe = i;
1400 return true;
1401 }
1402 }
19d8fe15 1403
4a0833ec
DV		 1404 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1405 intel_dp->output_reg);
1406 }
d240f20f 1407
19d8fe15
DV		 1408 return true;
1409}
d240f20f 1410
045ac3b5
JB		 1411static void intel_dp_get_config(struct intel_encoder *encoder,
1412 struct intel_crtc_config *pipe_config)
1413{
1414 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1415 u32 tmp, flags = 0;
63000ef6
XZ		 1416 struct drm_device *dev = encoder->base.dev;
1417 struct drm_i915_private *dev_priv = dev->dev_private;
1418 enum port port = dp_to_dig_port(intel_dp)->port;
1419 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 1420
63000ef6
XZ		 1421 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1422 tmp = I915_READ(intel_dp->output_reg);
1423 if (tmp & DP_SYNC_HS_HIGH)
1424 flags |= DRM_MODE_FLAG_PHSYNC;
1425 else
1426 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1427
63000ef6
XZ		 1428 if (tmp & DP_SYNC_VS_HIGH)
1429 flags |= DRM_MODE_FLAG_PVSYNC;
1430 else
1431 flags |= DRM_MODE_FLAG_NVSYNC;
1432 } else {
1433 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1434 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1435 flags |= DRM_MODE_FLAG_PHSYNC;
1436 else
1437 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1438
63000ef6
XZ		 1439 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1440 flags |= DRM_MODE_FLAG_PVSYNC;
1441 else
1442 flags |= DRM_MODE_FLAG_NVSYNC;
1443 }
045ac3b5
JB		 1444
1445 pipe_config->adjusted_mode.flags |= flags;
f1f644dc
JB		 1446
1447 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1448 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1449 pipe_config->port_clock = 162000;
1450 else
1451 pipe_config->port_clock = 270000;
1452 }
045ac3b5
JB		 1453}
1454
2293bb5c
SK		 1455static bool is_edp_psr(struct intel_dp *intel_dp)
1456{
1457 return is_edp(intel_dp) &&
1458 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1459}
1460
2b28bb1b
RV		 1461static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1462{
1463 struct drm_i915_private *dev_priv = dev->dev_private;
1464
1465 if (!IS_HASWELL(dev))
1466 return false;
1467
1468 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1469}
1470
1471static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1472 struct edp_vsc_psr *vsc_psr)
1473{
1474 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1475 struct drm_device *dev = dig_port->base.base.dev;
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1477 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1478 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1479 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1480 uint32_t *data = (uint32_t *) vsc_psr;
1481 unsigned int i;
1482
1483 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1484 the video DIP being updated before program video DIP data buffer
1485 registers for DIP being updated. */
1486 I915_WRITE(ctl_reg, 0);
1487 POSTING_READ(ctl_reg);
1488
1489 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1490 if (i < sizeof(struct edp_vsc_psr))
1491 I915_WRITE(data_reg + i, *data++);
1492 else
1493 I915_WRITE(data_reg + i, 0);
1494 }
1495
1496 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1497 POSTING_READ(ctl_reg);
1498}
1499
1500static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1501{
1502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 struct edp_vsc_psr psr_vsc;
1505
1506 if (intel_dp->psr_setup_done)
1507 return;
1508
1509 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1510 memset(&psr_vsc, 0, sizeof(psr_vsc));
1511 psr_vsc.sdp_header.HB0 = 0;
1512 psr_vsc.sdp_header.HB1 = 0x7;
1513 psr_vsc.sdp_header.HB2 = 0x2;
1514 psr_vsc.sdp_header.HB3 = 0x8;
1515 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1516
1517 /* Avoid continuous PSR exit by masking memup and hpd */
1518 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1519 EDP_PSR_DEBUG_MASK_HPD);
1520
1521 intel_dp->psr_setup_done = true;
1522}
1523
1524static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1525{
1526 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1527 struct drm_i915_private *dev_priv = dev->dev_private;
bc86625a 1528 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
2b28bb1b
RV		 1529 int precharge = 0x3;
1530 int msg_size = 5; /* Header(4) + Message(1) */
1531
1532 /* Enable PSR in sink */
1533 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1534 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1535 DP_PSR_ENABLE &
1536 ~DP_PSR_MAIN_LINK_ACTIVE);
1537 else
1538 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1539 DP_PSR_ENABLE |
1540 DP_PSR_MAIN_LINK_ACTIVE);
1541
1542 /* Setup AUX registers */
1543 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1544 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1545 I915_WRITE(EDP_PSR_AUX_CTL,
1546 DP_AUX_CH_CTL_TIME_OUT_400us |
1547 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1548 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1549 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1550}
1551
1552static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1553{
1554 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 uint32_t max_sleep_time = 0x1f;
1557 uint32_t idle_frames = 1;
1558 uint32_t val = 0x0;
1559
1560 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1561 val |= EDP_PSR_LINK_STANDBY;
1562 val |= EDP_PSR_TP2_TP3_TIME_0us;
1563 val |= EDP_PSR_TP1_TIME_0us;
1564 val |= EDP_PSR_SKIP_AUX_EXIT;
1565 } else
1566 val |= EDP_PSR_LINK_DISABLE;
1567
1568 I915_WRITE(EDP_PSR_CTL, val |
1569 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1570 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1571 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1572 EDP_PSR_ENABLE);
1573}
1574
3f51e471
RV		 1575static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1576{
1577 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1578 struct drm_device *dev = dig_port->base.base.dev;
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580 struct drm_crtc *crtc = dig_port->base.base.crtc;
1581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1583 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1584
1585 if (!IS_HASWELL(dev)) {
1586 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1587 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1588 return false;
1589 }
1590
1591 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1592 (dig_port->port != PORT_A)) {
1593 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1594 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1595 return false;
1596 }
1597
1598 if (!is_edp_psr(intel_dp)) {
1599 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1600 dev_priv->no_psr_reason = PSR_NO_SINK;
1601 return false;
1602 }
1603
105b7c11
RV		 1604 if (!i915_enable_psr) {
1605 DRM_DEBUG_KMS("PSR disable by flag\n");
1606 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1607 return false;
1608 }
1609
cd234b0b
CW		 1610 crtc = dig_port->base.base.crtc;
1611 if (crtc == NULL) {
1612 DRM_DEBUG_KMS("crtc not active for PSR\n");
1613 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1614 return false;
1615 }
1616
1617 intel_crtc = to_intel_crtc(crtc);
3f51e471
RV		 1618 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1619 DRM_DEBUG_KMS("crtc not active for PSR\n");
1620 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1621 return false;
1622 }
1623
cd234b0b 1624 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1625 if (obj->tiling_mode != I915_TILING_X ||
1626 obj->fence_reg == I915_FENCE_REG_NONE) {
1627 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1628 dev_priv->no_psr_reason = PSR_NOT_TILED;
1629 return false;
1630 }
1631
1632 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1633 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1634 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1635 return false;
1636 }
1637
1638 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1639 S3D_ENABLE) {
1640 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1641 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1642 return false;
1643 }
1644
1645 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1646 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1647 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1648 return false;
1649 }
1650
1651 return true;
1652}
1653
3d739d92 1654static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1655{
1656 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1657
3f51e471
RV		 1658 if (!intel_edp_psr_match_conditions(intel_dp) ||
1659 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1660 return;
1661
1662 /* Setup PSR once */
1663 intel_edp_psr_setup(intel_dp);
1664
1665 /* Enable PSR on the panel */
1666 intel_edp_psr_enable_sink(intel_dp);
1667
1668 /* Enable PSR on the host */
1669 intel_edp_psr_enable_source(intel_dp);
1670}
1671
3d739d92
RV		 1672void intel_edp_psr_enable(struct intel_dp *intel_dp)
1673{
1674 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1675
1676 if (intel_edp_psr_match_conditions(intel_dp) &&
1677 !intel_edp_is_psr_enabled(dev))
1678 intel_edp_psr_do_enable(intel_dp);
1679}
1680
2b28bb1b
RV		 1681void intel_edp_psr_disable(struct intel_dp *intel_dp)
1682{
1683 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685
1686 if (!intel_edp_is_psr_enabled(dev))
1687 return;
1688
1689 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1690
1691 /* Wait till PSR is idle */
1692 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1693 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1694 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1695}
1696
3d739d92
RV		 1697void intel_edp_psr_update(struct drm_device *dev)
1698{
1699 struct intel_encoder *encoder;
1700 struct intel_dp *intel_dp = NULL;
1701
1702 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1703 if (encoder->type == INTEL_OUTPUT_EDP) {
1704 intel_dp = enc_to_intel_dp(&encoder->base);
1705
1706 if (!is_edp_psr(intel_dp))
1707 return;
1708
1709 if (!intel_edp_psr_match_conditions(intel_dp))
1710 intel_edp_psr_disable(intel_dp);
1711 else
1712 if (!intel_edp_is_psr_enabled(dev))
1713 intel_edp_psr_do_enable(intel_dp);
1714 }
1715}
1716
e8cb4558 1717static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1718{
e8cb4558 1719 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1720 enum port port = dp_to_dig_port(intel_dp)->port;
1721 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1722
1723 /* Make sure the panel is off before trying to change the mode. But also
1724 * ensure that we have vdd while we switch off the panel. */
1725 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1726 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1727 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1728 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1729
1730 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1731 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1732 intel_dp_link_down(intel_dp);
d240f20f
JB		 1733}
1734
2bd2ad64 1735static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1736{
2bd2ad64 1737 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1738 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1739 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1740
982a3866 1741 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1742 intel_dp_link_down(intel_dp);
b2634017
JB		 1743 if (!IS_VALLEYVIEW(dev))
1744 ironlake_edp_pll_off(intel_dp);
3739850b 1745 }
2bd2ad64
DV		 1746}
1747
e8cb4558 1748static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1749{
e8cb4558
DV		 1750 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1751 struct drm_device *dev = encoder->base.dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1754
0c33d8d7
DV		 1755 if (WARN_ON(dp_reg & DP_PORT_EN))
1756 return;
5d613501 1757
97af61f5 1758 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1759 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1760 intel_dp_start_link_train(intel_dp);
97af61f5 1761 ironlake_edp_panel_on(intel_dp);
bd943159 1762 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1763 intel_dp_complete_link_train(intel_dp);
3ab9c637 1764 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1765}
89b667f8 1766
ecff4f3b
JN		 1767static void g4x_enable_dp(struct intel_encoder *encoder)
1768{
828f5c6e
JN		 1769 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1770
ecff4f3b 1771 intel_enable_dp(encoder);
828f5c6e 1772 ironlake_edp_backlight_on(intel_dp);
ecff4f3b
JN		 1773}
1774
ab1f90f9
JN		 1775static void vlv_enable_dp(struct intel_encoder *encoder)
1776{
828f5c6e
JN		 1777 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1778
1779 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1780}
1781
ecff4f3b 1782static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1783{
1784 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1785 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1786
1787 if (dport->port == PORT_A)
1788 ironlake_edp_pll_on(intel_dp);
1789}
1790
1791static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1792{
2bd2ad64 1793 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1794 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1795 struct drm_device *dev = encoder->base.dev;
89b667f8 1796 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9
JN		 1797 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1798 int port = vlv_dport_to_channel(dport);
1799 int pipe = intel_crtc->pipe;
bf13e81b 1800 struct edp_power_seq power_seq;
ab1f90f9 1801 u32 val;
a4fc5ed6 1802
ab1f90f9 1803 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1804
5e69f97f 1805 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port));
ab1f90f9
JN		 1806 val = 0;
1807 if (pipe)
1808 val |= (1<<21);
1809 else
1810 val &= ~(1<<21);
1811 val |= 0x001000c4;
5e69f97f
CML		 1812 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val);
1813 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1814 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
89b667f8 1815
ab1f90f9
JN		 1816 mutex_unlock(&dev_priv->dpio_lock);
1817
bf13e81b
JN		 1818 /* init power sequencer on this pipe and port */
1819 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1820 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1821 &power_seq);
1822
ab1f90f9
JN		 1823 intel_enable_dp(encoder);
1824
1825 vlv_wait_port_ready(dev_priv, port);
89b667f8
JB		 1826}
1827
ecff4f3b 1828static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1829{
1830 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1831 struct drm_device *dev = encoder->base.dev;
1832 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1833 struct intel_crtc *intel_crtc =
1834 to_intel_crtc(encoder->base.crtc);
89b667f8 1835 int port = vlv_dport_to_channel(dport);
5e69f97f 1836 int pipe = intel_crtc->pipe;
89b667f8 1837
89b667f8 1838 /* Program Tx lane resets to default */
0980a60f 1839 mutex_lock(&dev_priv->dpio_lock);
5e69f97f 1840 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port),
89b667f8
JB		 1841 DPIO_PCS_TX_LANE2_RESET |
1842 DPIO_PCS_TX_LANE1_RESET);
5e69f97f 1843 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port),
89b667f8
JB		 1844 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1845 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1846 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1847 DPIO_PCS_CLK_SOFT_RESET);
1848
1849 /* Fix up inter-pair skew failure */
5e69f97f
CML		 1850 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00);
1851 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500);
1852 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000);
0980a60f 1853 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1854}
1855
1856/*
df0c237d
JB		 1857 * Native read with retry for link status and receiver capability reads for
1858 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1859 */
1860static bool
df0c237d
JB		 1861intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1862 uint8_t *recv, int recv_bytes)
a4fc5ed6 1863{
61da5fab
JB		 1864 int ret, i;
1865
df0c237d
JB		 1866 /*
1867 * Sinks are *supposed* to come up within 1ms from an off state,
1868 * but we're also supposed to retry 3 times per the spec.
1869 */
61da5fab 1870 for (i = 0; i < 3; i++) {
df0c237d
JB		 1871 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1872 recv_bytes);
1873 if (ret == recv_bytes)
61da5fab
JB		 1874 return true;
1875 msleep(1);
1876 }
a4fc5ed6 1877
61da5fab 1878 return false;
a4fc5ed6
KP		 1879}
1880
1881/*
1882 * Fetch AUX CH registers 0x202 - 0x207 which contain
1883 * link status information
1884 */
1885static bool
93f62dad 1886intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1887{
df0c237d
JB		 1888 return intel_dp_aux_native_read_retry(intel_dp,
1889 DP_LANE0_1_STATUS,
93f62dad 1890 link_status,
df0c237d 1891 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1892}
1893
a4fc5ed6
KP		 1894#if 0
1895static char *voltage_names[] = {
1896 "0.4V", "0.6V", "0.8V", "1.2V"
1897};
1898static char *pre_emph_names[] = {
1899 "0dB", "3.5dB", "6dB", "9.5dB"
1900};
1901static char *link_train_names[] = {
1902 "pattern 1", "pattern 2", "idle", "off"
1903};
1904#endif
1905
1906/*
1907 * These are source-specific values; current Intel hardware supports
1908 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1909 */
a4fc5ed6
KP		 1910
1911static uint8_t
1a2eb460 1912intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1913{
30add22d 1914 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1915 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1916
e2fa6fba
P		 1917 if (IS_VALLEYVIEW(dev))
1918 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1919 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1920 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1921 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1922 return DP_TRAIN_VOLTAGE_SWING_1200;
1923 else
1924 return DP_TRAIN_VOLTAGE_SWING_800;
1925}
1926
1927static uint8_t
1928intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1929{
30add22d 1930 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1931 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1932
22b8bf17 1933 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1934 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1935 case DP_TRAIN_VOLTAGE_SWING_400:
1936 return DP_TRAIN_PRE_EMPHASIS_9_5;
1937 case DP_TRAIN_VOLTAGE_SWING_600:
1938 return DP_TRAIN_PRE_EMPHASIS_6;
1939 case DP_TRAIN_VOLTAGE_SWING_800:
1940 return DP_TRAIN_PRE_EMPHASIS_3_5;
1941 case DP_TRAIN_VOLTAGE_SWING_1200:
1942 default:
1943 return DP_TRAIN_PRE_EMPHASIS_0;
1944 }
e2fa6fba
P		 1945 } else if (IS_VALLEYVIEW(dev)) {
1946 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1947 case DP_TRAIN_VOLTAGE_SWING_400:
1948 return DP_TRAIN_PRE_EMPHASIS_9_5;
1949 case DP_TRAIN_VOLTAGE_SWING_600:
1950 return DP_TRAIN_PRE_EMPHASIS_6;
1951 case DP_TRAIN_VOLTAGE_SWING_800:
1952 return DP_TRAIN_PRE_EMPHASIS_3_5;
1953 case DP_TRAIN_VOLTAGE_SWING_1200:
1954 default:
1955 return DP_TRAIN_PRE_EMPHASIS_0;
1956 }
bc7d38a4 1957 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1958 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1959 case DP_TRAIN_VOLTAGE_SWING_400:
1960 return DP_TRAIN_PRE_EMPHASIS_6;
1961 case DP_TRAIN_VOLTAGE_SWING_600:
1962 case DP_TRAIN_VOLTAGE_SWING_800:
1963 return DP_TRAIN_PRE_EMPHASIS_3_5;
1964 default:
1965 return DP_TRAIN_PRE_EMPHASIS_0;
1966 }
1967 } else {
1968 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1969 case DP_TRAIN_VOLTAGE_SWING_400:
1970 return DP_TRAIN_PRE_EMPHASIS_6;
1971 case DP_TRAIN_VOLTAGE_SWING_600:
1972 return DP_TRAIN_PRE_EMPHASIS_6;
1973 case DP_TRAIN_VOLTAGE_SWING_800:
1974 return DP_TRAIN_PRE_EMPHASIS_3_5;
1975 case DP_TRAIN_VOLTAGE_SWING_1200:
1976 default:
1977 return DP_TRAIN_PRE_EMPHASIS_0;
1978 }
a4fc5ed6
KP		 1979 }
1980}
1981
e2fa6fba
P		 1982static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1983{
1984 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1985 struct drm_i915_private *dev_priv = dev->dev_private;
1986 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 1987 struct intel_crtc *intel_crtc =
1988 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 1989 unsigned long demph_reg_value, preemph_reg_value,
1990 uniqtranscale_reg_value;
1991 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1992 int port = vlv_dport_to_channel(dport);
5e69f97f 1993 int pipe = intel_crtc->pipe;
e2fa6fba
P		 1994
1995 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1996 case DP_TRAIN_PRE_EMPHASIS_0:
1997 preemph_reg_value = 0x0004000;
1998 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1999 case DP_TRAIN_VOLTAGE_SWING_400:
2000 demph_reg_value = 0x2B405555;
2001 uniqtranscale_reg_value = 0x552AB83A;
2002 break;
2003 case DP_TRAIN_VOLTAGE_SWING_600:
2004 demph_reg_value = 0x2B404040;
2005 uniqtranscale_reg_value = 0x5548B83A;
2006 break;
2007 case DP_TRAIN_VOLTAGE_SWING_800:
2008 demph_reg_value = 0x2B245555;
2009 uniqtranscale_reg_value = 0x5560B83A;
2010 break;
2011 case DP_TRAIN_VOLTAGE_SWING_1200:
2012 demph_reg_value = 0x2B405555;
2013 uniqtranscale_reg_value = 0x5598DA3A;
2014 break;
2015 default:
2016 return 0;
2017 }
2018 break;
2019 case DP_TRAIN_PRE_EMPHASIS_3_5:
2020 preemph_reg_value = 0x0002000;
2021 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2022 case DP_TRAIN_VOLTAGE_SWING_400:
2023 demph_reg_value = 0x2B404040;
2024 uniqtranscale_reg_value = 0x5552B83A;
2025 break;
2026 case DP_TRAIN_VOLTAGE_SWING_600:
2027 demph_reg_value = 0x2B404848;
2028 uniqtranscale_reg_value = 0x5580B83A;
2029 break;
2030 case DP_TRAIN_VOLTAGE_SWING_800:
2031 demph_reg_value = 0x2B404040;
2032 uniqtranscale_reg_value = 0x55ADDA3A;
2033 break;
2034 default:
2035 return 0;
2036 }
2037 break;
2038 case DP_TRAIN_PRE_EMPHASIS_6:
2039 preemph_reg_value = 0x0000000;
2040 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2041 case DP_TRAIN_VOLTAGE_SWING_400:
2042 demph_reg_value = 0x2B305555;
2043 uniqtranscale_reg_value = 0x5570B83A;
2044 break;
2045 case DP_TRAIN_VOLTAGE_SWING_600:
2046 demph_reg_value = 0x2B2B4040;
2047 uniqtranscale_reg_value = 0x55ADDA3A;
2048 break;
2049 default:
2050 return 0;
2051 }
2052 break;
2053 case DP_TRAIN_PRE_EMPHASIS_9_5:
2054 preemph_reg_value = 0x0006000;
2055 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2056 case DP_TRAIN_VOLTAGE_SWING_400:
2057 demph_reg_value = 0x1B405555;
2058 uniqtranscale_reg_value = 0x55ADDA3A;
2059 break;
2060 default:
2061 return 0;
2062 }
2063 break;
2064 default:
2065 return 0;
2066 }
2067
0980a60f 2068 mutex_lock(&dev_priv->dpio_lock);
5e69f97f
CML		 2069 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000);
2070 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value);
2071 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port),
e2fa6fba 2072 uniqtranscale_reg_value);
5e69f97f
CML		 2073 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040);
2074 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
2075 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
2076 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000);
0980a60f 2077 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2078
2079 return 0;
2080}
2081
a4fc5ed6 2082static void
93f62dad 2083intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2084{
2085 uint8_t v = 0;
2086 uint8_t p = 0;
2087 int lane;
1a2eb460
KP		 2088 uint8_t voltage_max;
2089 uint8_t preemph_max;
a4fc5ed6 2090
33a34e4e 2091 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2092 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2093 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2094
2095 if (this_v > v)
2096 v = this_v;
2097 if (this_p > p)
2098 p = this_p;
2099 }
2100
1a2eb460 2101 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2102 if (v >= voltage_max)
2103 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2104
1a2eb460
KP		 2105 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2106 if (p >= preemph_max)
2107 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2108
2109 for (lane = 0; lane < 4; lane++)
33a34e4e 2110 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2111}
2112
2113static uint32_t
f0a3424e 2114intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2115{
3cf2efb1 2116 uint32_t signal_levels = 0;
a4fc5ed6 2117
3cf2efb1 2118 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2119 case DP_TRAIN_VOLTAGE_SWING_400:
2120 default:
2121 signal_levels |= DP_VOLTAGE_0_4;
2122 break;
2123 case DP_TRAIN_VOLTAGE_SWING_600:
2124 signal_levels |= DP_VOLTAGE_0_6;
2125 break;
2126 case DP_TRAIN_VOLTAGE_SWING_800:
2127 signal_levels |= DP_VOLTAGE_0_8;
2128 break;
2129 case DP_TRAIN_VOLTAGE_SWING_1200:
2130 signal_levels |= DP_VOLTAGE_1_2;
2131 break;
2132 }
3cf2efb1 2133 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2134 case DP_TRAIN_PRE_EMPHASIS_0:
2135 default:
2136 signal_levels |= DP_PRE_EMPHASIS_0;
2137 break;
2138 case DP_TRAIN_PRE_EMPHASIS_3_5:
2139 signal_levels |= DP_PRE_EMPHASIS_3_5;
2140 break;
2141 case DP_TRAIN_PRE_EMPHASIS_6:
2142 signal_levels |= DP_PRE_EMPHASIS_6;
2143 break;
2144 case DP_TRAIN_PRE_EMPHASIS_9_5:
2145 signal_levels |= DP_PRE_EMPHASIS_9_5;
2146 break;
2147 }
2148 return signal_levels;
2149}
2150
e3421a18
ZW		 2151/* Gen6's DP voltage swing and pre-emphasis control */
2152static uint32_t
2153intel_gen6_edp_signal_levels(uint8_t train_set)
2154{
3c5a62b5
YL		 2155 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2156 DP_TRAIN_PRE_EMPHASIS_MASK);
2157 switch (signal_levels) {
e3421a18 2158 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2159 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2160 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2161 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2162 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2163 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2164 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2165 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2166 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2167 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2168 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2169 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2170 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2171 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2172 default:
3c5a62b5
YL		 2173 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2174 "0x%x\n", signal_levels);
2175 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2176 }
2177}
2178
1a2eb460
KP		 2179/* Gen7's DP voltage swing and pre-emphasis control */
2180static uint32_t
2181intel_gen7_edp_signal_levels(uint8_t train_set)
2182{
2183 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2184 DP_TRAIN_PRE_EMPHASIS_MASK);
2185 switch (signal_levels) {
2186 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2187 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2188 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2189 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2190 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2191 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2192
2193 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2194 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2195 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2196 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2197
2198 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2199 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2200 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2201 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2202
2203 default:
2204 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2205 "0x%x\n", signal_levels);
2206 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2207 }
2208}
2209
d6c0d722
PZ		 2210/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2211static uint32_t
f0a3424e 2212intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2213{
d6c0d722
PZ		 2214 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2215 DP_TRAIN_PRE_EMPHASIS_MASK);
2216 switch (signal_levels) {
2217 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2218 return DDI_BUF_EMP_400MV_0DB_HSW;
2219 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2220 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2221 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2222 return DDI_BUF_EMP_400MV_6DB_HSW;
2223 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2224 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2225
d6c0d722
PZ		 2226 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2227 return DDI_BUF_EMP_600MV_0DB_HSW;
2228 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2229 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2230 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2231 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2232
d6c0d722
PZ		 2233 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2234 return DDI_BUF_EMP_800MV_0DB_HSW;
2235 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2236 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2237 default:
2238 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2239 "0x%x\n", signal_levels);
2240 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2241 }
a4fc5ed6
KP		 2242}
2243
f0a3424e
PZ		 2244/* Properly updates "DP" with the correct signal levels. */
2245static void
2246intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2247{
2248 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2249 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2250 struct drm_device *dev = intel_dig_port->base.base.dev;
2251 uint32_t signal_levels, mask;
2252 uint8_t train_set = intel_dp->train_set[0];
2253
22b8bf17 2254 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2255 signal_levels = intel_hsw_signal_levels(train_set);
2256 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2257 } else if (IS_VALLEYVIEW(dev)) {
2258 signal_levels = intel_vlv_signal_levels(intel_dp);
2259 mask = 0;
bc7d38a4 2260 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2261 signal_levels = intel_gen7_edp_signal_levels(train_set);
2262 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2263 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2264 signal_levels = intel_gen6_edp_signal_levels(train_set);
2265 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2266 } else {
2267 signal_levels = intel_gen4_signal_levels(train_set);
2268 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2269 }
2270
2271 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2272
2273 *DP = (*DP & ~mask) | signal_levels;
2274}
2275
a4fc5ed6 2276static bool
ea5b213a 2277intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 2278 uint32_t dp_reg_value,
58e10eb9 2279 uint8_t dp_train_pat)
a4fc5ed6 2280{
174edf1f
PZ		 2281 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2282 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2283 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2284 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 2285 int ret;
2286
22b8bf17 2287 if (HAS_DDI(dev)) {
3ab9c637 2288 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2289
2290 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2291 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2292 else
2293 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2294
2295 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2296 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2297 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2298 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2299
2300 break;
2301 case DP_TRAINING_PATTERN_1:
2302 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2303 break;
2304 case DP_TRAINING_PATTERN_2:
2305 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2306 break;
2307 case DP_TRAINING_PATTERN_3:
2308 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2309 break;
2310 }
174edf1f 2311 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2312
bc7d38a4 2313 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 2314 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2315
2316 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2317 case DP_TRAINING_PATTERN_DISABLE:
2318 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2319 break;
2320 case DP_TRAINING_PATTERN_1:
2321 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2322 break;
2323 case DP_TRAINING_PATTERN_2:
2324 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2325 break;
2326 case DP_TRAINING_PATTERN_3:
2327 DRM_ERROR("DP training pattern 3 not supported\n");
2328 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2329 break;
2330 }
2331
2332 } else {
2333 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2334
2335 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2336 case DP_TRAINING_PATTERN_DISABLE:
2337 dp_reg_value |= DP_LINK_TRAIN_OFF;
2338 break;
2339 case DP_TRAINING_PATTERN_1:
2340 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2341 break;
2342 case DP_TRAINING_PATTERN_2:
2343 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2344 break;
2345 case DP_TRAINING_PATTERN_3:
2346 DRM_ERROR("DP training pattern 3 not supported\n");
2347 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2348 break;
2349 }
2350 }
2351
ea5b213a
CW		 2352 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2353 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2354
ea5b213a 2355 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2356 DP_TRAINING_PATTERN_SET,
2357 dp_train_pat);
2358
47ea7542
PZ		 2359 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2360 DP_TRAINING_PATTERN_DISABLE) {
2361 ret = intel_dp_aux_native_write(intel_dp,
2362 DP_TRAINING_LANE0_SET,
2363 intel_dp->train_set,
2364 intel_dp->lane_count);
2365 if (ret != intel_dp->lane_count)
2366 return false;
2367 }
a4fc5ed6
KP		 2368
2369 return true;
2370}
2371
3ab9c637
ID		 2372static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2373{
2374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2375 struct drm_device *dev = intel_dig_port->base.base.dev;
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 enum port port = intel_dig_port->port;
2378 uint32_t val;
2379
2380 if (!HAS_DDI(dev))
2381 return;
2382
2383 val = I915_READ(DP_TP_CTL(port));
2384 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2385 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2386 I915_WRITE(DP_TP_CTL(port), val);
2387
2388 /*
2389 * On PORT_A we can have only eDP in SST mode. There the only reason
2390 * we need to set idle transmission mode is to work around a HW issue
2391 * where we enable the pipe while not in idle link-training mode.
2392 * In this case there is requirement to wait for a minimum number of
2393 * idle patterns to be sent.
2394 */
2395 if (port == PORT_A)
2396 return;
2397
2398 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2399 1))
2400 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2401}
2402
33a34e4e 2403/* Enable corresponding port and start training pattern 1 */
c19b0669 2404void
33a34e4e 2405intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2406{
da63a9f2 2407 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2408 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2409 int i;
2410 uint8_t voltage;
cdb0e95b 2411 int voltage_tries, loop_tries;
ea5b213a 2412 uint32_t DP = intel_dp->DP;
a4fc5ed6 2413
affa9354 2414 if (HAS_DDI(dev))
c19b0669
PZ		 2415 intel_ddi_prepare_link_retrain(encoder);
2416
3cf2efb1
CW		 2417 /* Write the link configuration data */
2418 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2419 intel_dp->link_configuration,
2420 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2421
2422 DP |= DP_PORT_EN;
1a2eb460 2423
33a34e4e 2424 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2425 voltage = 0xff;
cdb0e95b
KP		 2426 voltage_tries = 0;
2427 loop_tries = 0;
a4fc5ed6 2428 for (;;) {
33a34e4e 2429 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2430 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2431
2432 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2433
a7c9655f 2434 /* Set training pattern 1 */
47ea7542 2435 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2436 DP_TRAINING_PATTERN_1 |
2437 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2438 break;
a4fc5ed6 2439
a7c9655f 2440 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2441 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2442 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2443 break;
93f62dad 2444 }
a4fc5ed6 2445
01916270 2446 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2447 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2448 break;
2449 }
2450
2451 /* Check to see if we've tried the max voltage */
2452 for (i = 0; i < intel_dp->lane_count; i++)
2453 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2454 break;
3b4f819d 2455 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2456 ++loop_tries;
2457 if (loop_tries == 5) {
cdb0e95b
KP		 2458 DRM_DEBUG_KMS("too many full retries, give up\n");
2459 break;
2460 }
2461 memset(intel_dp->train_set, 0, 4);
2462 voltage_tries = 0;
2463 continue;
2464 }
a4fc5ed6 2465
3cf2efb1 2466 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2467 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2468 ++voltage_tries;
b06fbda3
DV		 2469 if (voltage_tries == 5) {
2470 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2471 break;
2472 }
2473 } else
2474 voltage_tries = 0;
2475 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2476
3cf2efb1 2477 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2478 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2479 }
2480
33a34e4e
JB		 2481 intel_dp->DP = DP;
2482}
2483
c19b0669 2484void
33a34e4e
JB		 2485intel_dp_complete_link_train(struct intel_dp *intel_dp)
2486{
33a34e4e 2487 bool channel_eq = false;
37f80975 2488 int tries, cr_tries;
33a34e4e
JB		 2489 uint32_t DP = intel_dp->DP;
2490
a4fc5ed6
KP		 2491 /* channel equalization */
2492 tries = 0;
37f80975 2493 cr_tries = 0;
a4fc5ed6
KP		 2494 channel_eq = false;
2495 for (;;) {
93f62dad 2496 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2497
37f80975
JB		 2498 if (cr_tries > 5) {
2499 DRM_ERROR("failed to train DP, aborting\n");
2500 intel_dp_link_down(intel_dp);
2501 break;
2502 }
2503
f0a3424e 2504 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2505
a4fc5ed6 2506 /* channel eq pattern */
47ea7542 2507 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2508 DP_TRAINING_PATTERN_2 |
2509 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2510 break;
2511
a7c9655f 2512 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2513 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2514 break;
a4fc5ed6 2515
37f80975 2516 /* Make sure clock is still ok */
01916270 2517 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2518 intel_dp_start_link_train(intel_dp);
2519 cr_tries++;
2520 continue;
2521 }
2522
1ffdff13 2523 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2524 channel_eq = true;
2525 break;
2526 }
a4fc5ed6 2527
37f80975
JB		 2528 /* Try 5 times, then try clock recovery if that fails */
2529 if (tries > 5) {
2530 intel_dp_link_down(intel_dp);
2531 intel_dp_start_link_train(intel_dp);
2532 tries = 0;
2533 cr_tries++;
2534 continue;
2535 }
a4fc5ed6 2536
3cf2efb1 2537 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2538 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2539 ++tries;
869184a6 2540 }
3cf2efb1 2541
3ab9c637
ID		 2542 intel_dp_set_idle_link_train(intel_dp);
2543
2544 intel_dp->DP = DP;
2545
d6c0d722 2546 if (channel_eq)
07f42258 2547 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2548
3ab9c637
ID		 2549}
2550
2551void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2552{
2553 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2554 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2555}
2556
2557static void
ea5b213a 2558intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2559{
da63a9f2 2560 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2561 enum port port = intel_dig_port->port;
da63a9f2 2562 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2563 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2564 struct intel_crtc *intel_crtc =
2565 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2566 uint32_t DP = intel_dp->DP;
a4fc5ed6 2567
c19b0669
PZ		 2568 /*
2569 * DDI code has a strict mode set sequence and we should try to respect
2570 * it, otherwise we might hang the machine in many different ways. So we
2571 * really should be disabling the port only on a complete crtc_disable
2572 * sequence. This function is just called under two conditions on DDI
2573 * code:
2574 * - Link train failed while doing crtc_enable, and on this case we
2575 * really should respect the mode set sequence and wait for a
2576 * crtc_disable.
2577 * - Someone turned the monitor off and intel_dp_check_link_status
2578 * called us. We don't need to disable the whole port on this case, so
2579 * when someone turns the monitor on again,
2580 * intel_ddi_prepare_link_retrain will take care of redoing the link
2581 * train.
2582 */
affa9354 2583 if (HAS_DDI(dev))
c19b0669
PZ		 2584 return;
2585
0c33d8d7 2586 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2587 return;
2588
28c97730 2589 DRM_DEBUG_KMS("\n");
32f9d658 2590
bc7d38a4 2591 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2592 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2593 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2594 } else {
2595 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2596 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2597 }
fe255d00 2598 POSTING_READ(intel_dp->output_reg);
5eb08b69 2599
ab527efc
DV		 2600 /* We don't really know why we're doing this */
2601 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2602
493a7081 2603 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2604 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2605 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2606
5bddd17f
EA		 2607 /* Hardware workaround: leaving our transcoder select
2608 * set to transcoder B while it's off will prevent the
2609 * corresponding HDMI output on transcoder A.
2610 *
2611 * Combine this with another hardware workaround:
2612 * transcoder select bit can only be cleared while the
2613 * port is enabled.
2614 */
2615 DP &= ~DP_PIPEB_SELECT;
2616 I915_WRITE(intel_dp->output_reg, DP);
2617
2618 /* Changes to enable or select take place the vblank
2619 * after being written.
2620 */
ff50afe9
DV		 2621 if (WARN_ON(crtc == NULL)) {
2622 /* We should never try to disable a port without a crtc
2623 * attached. For paranoia keep the code around for a
2624 * bit. */
31acbcc4
CW		 2625 POSTING_READ(intel_dp->output_reg);
2626 msleep(50);
2627 } else
ab527efc 2628 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2629 }
2630
832afda6 2631 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2632 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2633 POSTING_READ(intel_dp->output_reg);
f01eca2e 2634 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2635}
2636
26d61aad
KP		 2637static bool
2638intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2639{
577c7a50
DL		 2640 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2641
92fd8fd1 2642 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2643 sizeof(intel_dp->dpcd)) == 0)
2644 return false; /* aux transfer failed */
92fd8fd1 2645
577c7a50
DL		 2646 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2647 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2648 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2649
edb39244
AJ		 2650 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2651 return false; /* DPCD not present */
2652
2293bb5c
SK		 2653 /* Check if the panel supports PSR */
2654 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2655 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2656 intel_dp->psr_dpcd,
2657 sizeof(intel_dp->psr_dpcd));
2658 if (is_edp_psr(intel_dp))
2659 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
edb39244
AJ		 2660 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2661 DP_DWN_STRM_PORT_PRESENT))
2662 return true; /* native DP sink */
2663
2664 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2665 return true; /* no per-port downstream info */
2666
2667 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2668 intel_dp->downstream_ports,
2669 DP_MAX_DOWNSTREAM_PORTS) == 0)
2670 return false; /* downstream port status fetch failed */
2671
2672 return true;
92fd8fd1
KP		 2673}
2674
0d198328
AJ		 2675static void
2676intel_dp_probe_oui(struct intel_dp *intel_dp)
2677{
2678 u8 buf[3];
2679
2680 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2681 return;
2682
351cfc34
DV		 2683 ironlake_edp_panel_vdd_on(intel_dp);
2684
0d198328
AJ		 2685 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2686 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2687 buf[0], buf[1], buf[2]);
2688
2689 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2690 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2691 buf[0], buf[1], buf[2]);
351cfc34
DV		 2692
2693 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2694}
2695
a60f0e38
JB		 2696static bool
2697intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2698{
2699 int ret;
2700
2701 ret = intel_dp_aux_native_read_retry(intel_dp,
2702 DP_DEVICE_SERVICE_IRQ_VECTOR,
2703 sink_irq_vector, 1);
2704 if (!ret)
2705 return false;
2706
2707 return true;
2708}
2709
2710static void
2711intel_dp_handle_test_request(struct intel_dp *intel_dp)
2712{
2713 /* NAK by default */
9324cf7f 2714 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2715}
2716
a4fc5ed6
KP		 2717/*
2718 * According to DP spec
2719 * 5.1.2:
2720 * 1. Read DPCD
2721 * 2. Configure link according to Receiver Capabilities
2722 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2723 * 4. Check link status on receipt of hot-plug interrupt
2724 */
2725
00c09d70 2726void
ea5b213a 2727intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2728{
da63a9f2 2729 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2730 u8 sink_irq_vector;
93f62dad 2731 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2732
da63a9f2 2733 if (!intel_encoder->connectors_active)
d2b996ac 2734 return;
59cd09e1 2735
da63a9f2 2736 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2737 return;
2738
92fd8fd1 2739 /* Try to read receiver status if the link appears to be up */
93f62dad 2740 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2741 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2742 return;
2743 }
2744
92fd8fd1 2745 /* Now read the DPCD to see if it's actually running */
26d61aad 2746 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2747 intel_dp_link_down(intel_dp);
2748 return;
2749 }
2750
a60f0e38
JB		 2751 /* Try to read the source of the interrupt */
2752 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2753 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2754 /* Clear interrupt source */
2755 intel_dp_aux_native_write_1(intel_dp,
2756 DP_DEVICE_SERVICE_IRQ_VECTOR,
2757 sink_irq_vector);
2758
2759 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2760 intel_dp_handle_test_request(intel_dp);
2761 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2762 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2763 }
2764
1ffdff13 2765 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2766 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2767 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2768 intel_dp_start_link_train(intel_dp);
2769 intel_dp_complete_link_train(intel_dp);
3ab9c637 2770 intel_dp_stop_link_train(intel_dp);
33a34e4e 2771 }
a4fc5ed6 2772}
a4fc5ed6 2773
caf9ab24 2774/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2775static enum drm_connector_status
26d61aad 2776intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2777{
caf9ab24
AJ		 2778 uint8_t *dpcd = intel_dp->dpcd;
2779 bool hpd;
2780 uint8_t type;
2781
2782 if (!intel_dp_get_dpcd(intel_dp))
2783 return connector_status_disconnected;
2784
2785 /* if there's no downstream port, we're done */
2786 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2787 return connector_status_connected;
caf9ab24
AJ		 2788
2789 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2790 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2791 if (hpd) {
23235177 2792 uint8_t reg;
caf9ab24 2793 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2794 &reg, 1))
caf9ab24 2795 return connector_status_unknown;
23235177
AJ		 2796 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2797 : connector_status_disconnected;
caf9ab24
AJ		 2798 }
2799
2800 /* If no HPD, poke DDC gently */
2801 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2802 return connector_status_connected;
caf9ab24
AJ		 2803
2804 /* Well we tried, say unknown for unreliable port types */
2805 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2806 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2807 return connector_status_unknown;
2808
2809 /* Anything else is out of spec, warn and ignore */
2810 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2811 return connector_status_disconnected;
71ba9000
AJ		 2812}
2813
5eb08b69 2814static enum drm_connector_status
a9756bb5 2815ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2816{
30add22d 2817 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2818 struct drm_i915_private *dev_priv = dev->dev_private;
2819 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2820 enum drm_connector_status status;
2821
fe16d949
CW		 2822 /* Can't disconnect eDP, but you can close the lid... */
2823 if (is_edp(intel_dp)) {
30add22d 2824 status = intel_panel_detect(dev);
fe16d949
CW		 2825 if (status == connector_status_unknown)
2826 status = connector_status_connected;
2827 return status;
2828 }
01cb9ea6 2829
1b469639
DL		 2830 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2831 return connector_status_disconnected;
2832
26d61aad 2833 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2834}
2835
a4fc5ed6 2836static enum drm_connector_status
a9756bb5 2837g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2838{
30add22d 2839 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2840 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2841 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2842 uint32_t bit;
5eb08b69 2843
35aad75f
JB		 2844 /* Can't disconnect eDP, but you can close the lid... */
2845 if (is_edp(intel_dp)) {
2846 enum drm_connector_status status;
2847
2848 status = intel_panel_detect(dev);
2849 if (status == connector_status_unknown)
2850 status = connector_status_connected;
2851 return status;
2852 }
2853
34f2be46
VS		 2854 switch (intel_dig_port->port) {
2855 case PORT_B:
26739f12 2856 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2857 break;
34f2be46 2858 case PORT_C:
26739f12 2859 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2860 break;
34f2be46 2861 case PORT_D:
26739f12 2862 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2863 break;
2864 default:
2865 return connector_status_unknown;
2866 }
2867
10f76a38 2868 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2869 return connector_status_disconnected;
2870
26d61aad 2871 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2872}
2873
8c241fef
KP		 2874static struct edid *
2875intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2876{
9cd300e0 2877 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2878
9cd300e0
JN		 2879 /* use cached edid if we have one */
2880 if (intel_connector->edid) {
2881 struct edid *edid;
2882 int size;
2883
2884 /* invalid edid */
2885 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2886 return NULL;
2887
9cd300e0 2888 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2889 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2890 if (!edid)
2891 return NULL;
2892
d6f24d0f
JB		 2893 return edid;
2894 }
8c241fef 2895
9cd300e0 2896 return drm_get_edid(connector, adapter);
8c241fef
KP		 2897}
2898
2899static int
2900intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2901{
9cd300e0 2902 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2903
9cd300e0
JN		 2904 /* use cached edid if we have one */
2905 if (intel_connector->edid) {
2906 /* invalid edid */
2907 if (IS_ERR(intel_connector->edid))
2908 return 0;
2909
2910 return intel_connector_update_modes(connector,
2911 intel_connector->edid);
d6f24d0f
JB		 2912 }
2913
9cd300e0 2914 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2915}
2916
a9756bb5
ZW		 2917static enum drm_connector_status
2918intel_dp_detect(struct drm_connector *connector, bool force)
2919{
2920 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2921 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2922 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2923 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2924 enum drm_connector_status status;
2925 struct edid *edid = NULL;
2926
164c8598
CW		 2927 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2928 connector->base.id, drm_get_connector_name(connector));
2929
a9756bb5
ZW		 2930 intel_dp->has_audio = false;
2931
2932 if (HAS_PCH_SPLIT(dev))
2933 status = ironlake_dp_detect(intel_dp);
2934 else
2935 status = g4x_dp_detect(intel_dp);
1b9be9d0 2936
a9756bb5
ZW		 2937 if (status != connector_status_connected)
2938 return status;
2939
0d198328
AJ		 2940 intel_dp_probe_oui(intel_dp);
2941
c3e5f67b
DV		 2942 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2943 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2944 } else {
8c241fef 2945 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2946 if (edid) {
2947 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2948 kfree(edid);
2949 }
a9756bb5
ZW		 2950 }
2951
d63885da
PZ		 2952 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2953 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2954 return connector_status_connected;
a4fc5ed6
KP		 2955}
2956
2957static int intel_dp_get_modes(struct drm_connector *connector)
2958{
df0e9248 2959 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2960 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2961 struct drm_device *dev = connector->dev;
32f9d658 2962 int ret;
a4fc5ed6
KP		 2963
2964 /* We should parse the EDID data and find out if it has an audio sink
2965 */
2966
8c241fef 2967 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2968 if (ret)
32f9d658
ZW		 2969 return ret;
2970
f8779fda 2971 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2972 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2973 struct drm_display_mode *mode;
dd06f90e
JN		 2974 mode = drm_mode_duplicate(dev,
2975 intel_connector->panel.fixed_mode);
f8779fda 2976 if (mode) {
32f9d658
ZW		 2977 drm_mode_probed_add(connector, mode);
2978 return 1;
2979 }
2980 }
2981 return 0;
a4fc5ed6
KP		 2982}
2983
1aad7ac0
CW		 2984static bool
2985intel_dp_detect_audio(struct drm_connector *connector)
2986{
2987 struct intel_dp *intel_dp = intel_attached_dp(connector);
2988 struct edid *edid;
2989 bool has_audio = false;
2990
8c241fef 2991 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2992 if (edid) {
2993 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2994 kfree(edid);
2995 }
2996
2997 return has_audio;
2998}
2999
f684960e
CW		 3000static int
3001intel_dp_set_property(struct drm_connector *connector,
3002 struct drm_property *property,
3003 uint64_t val)
3004{
e953fd7b 3005 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3006 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3007 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3008 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3009 int ret;
3010
662595df 3011 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3012 if (ret)
3013 return ret;
3014
3f43c48d 3015 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3016 int i = val;
3017 bool has_audio;
3018
3019 if (i == intel_dp->force_audio)
f684960e
CW		 3020 return 0;
3021
1aad7ac0 3022 intel_dp->force_audio = i;
f684960e 3023
c3e5f67b 3024 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3025 has_audio = intel_dp_detect_audio(connector);
3026 else
c3e5f67b 3027 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3028
3029 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3030 return 0;
3031
1aad7ac0 3032 intel_dp->has_audio = has_audio;
f684960e
CW		 3033 goto done;
3034 }
3035
e953fd7b 3036 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3037 bool old_auto = intel_dp->color_range_auto;
3038 uint32_t old_range = intel_dp->color_range;
3039
55bc60db
VS		 3040 switch (val) {
3041 case INTEL_BROADCAST_RGB_AUTO:
3042 intel_dp->color_range_auto = true;
3043 break;
3044 case INTEL_BROADCAST_RGB_FULL:
3045 intel_dp->color_range_auto = false;
3046 intel_dp->color_range = 0;
3047 break;
3048 case INTEL_BROADCAST_RGB_LIMITED:
3049 intel_dp->color_range_auto = false;
3050 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3051 break;
3052 default:
3053 return -EINVAL;
3054 }
ae4edb80
DV		 3055
3056 if (old_auto == intel_dp->color_range_auto &&
3057 old_range == intel_dp->color_range)
3058 return 0;
3059
e953fd7b
CW		 3060 goto done;
3061 }
3062
53b41837
YN		 3063 if (is_edp(intel_dp) &&
3064 property == connector->dev->mode_config.scaling_mode_property) {
3065 if (val == DRM_MODE_SCALE_NONE) {
3066 DRM_DEBUG_KMS("no scaling not supported\n");
3067 return -EINVAL;
3068 }
3069
3070 if (intel_connector->panel.fitting_mode == val) {
3071 /* the eDP scaling property is not changed */
3072 return 0;
3073 }
3074 intel_connector->panel.fitting_mode = val;
3075
3076 goto done;
3077 }
3078
f684960e
CW		 3079 return -EINVAL;
3080
3081done:
c0c36b94
CW		 3082 if (intel_encoder->base.crtc)
3083 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3084
3085 return 0;
3086}
3087
a4fc5ed6 3088static void
73845adf 3089intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3090{
1d508706 3091 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3092
9cd300e0
JN		 3093 if (!IS_ERR_OR_NULL(intel_connector->edid))
3094 kfree(intel_connector->edid);
3095
acd8db10
PZ		 3096 /* Can't call is_edp() since the encoder may have been destroyed
3097 * already. */
3098 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3099 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3100
a4fc5ed6
KP		 3101 drm_sysfs_connector_remove(connector);
3102 drm_connector_cleanup(connector);
55f78c43 3103 kfree(connector);
a4fc5ed6
KP		 3104}
3105
00c09d70 3106void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3107{
da63a9f2
PZ		 3108 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3109 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3110 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3111
3112 i2c_del_adapter(&intel_dp->adapter);
3113 drm_encoder_cleanup(encoder);
bd943159
KP		 3114 if (is_edp(intel_dp)) {
3115 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3116 mutex_lock(&dev->mode_config.mutex);
bd943159 3117 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3118 mutex_unlock(&dev->mode_config.mutex);
bd943159 3119 }
da63a9f2 3120 kfree(intel_dig_port);
24d05927
DV		 3121}
3122
a4fc5ed6 3123static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3124 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3125 .detect = intel_dp_detect,
3126 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3127 .set_property = intel_dp_set_property,
73845adf 3128 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3129};
3130
3131static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3132 .get_modes = intel_dp_get_modes,
3133 .mode_valid = intel_dp_mode_valid,
df0e9248 3134 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3135};
3136
a4fc5ed6 3137static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3138 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3139};
3140
995b6762 3141static void
21d40d37 3142intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3143{
fa90ecef 3144 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3145
885a5014 3146 intel_dp_check_link_status(intel_dp);
c8110e52 3147}
6207937d 3148
e3421a18
ZW		 3149/* Return which DP Port should be selected for Transcoder DP control */
3150int
0206e353 3151intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3152{
3153 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3154 struct intel_encoder *intel_encoder;
3155 struct intel_dp *intel_dp;
e3421a18 3156
fa90ecef
PZ		 3157 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3158 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3159
fa90ecef
PZ		 3160 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3161 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3162 return intel_dp->output_reg;
e3421a18 3163 }
ea5b213a 3164
e3421a18
ZW		 3165 return -1;
3166}
3167
36e83a18 3168/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3169bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3170{
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 struct child_device_config *p_child;
3173 int i;
3174
41aa3448 3175 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3176 return false;
3177
41aa3448
RV		 3178 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3179 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 3180
3181 if (p_child->dvo_port == PORT_IDPD &&
3182 p_child->device_type == DEVICE_TYPE_eDP)
3183 return true;
3184 }
3185 return false;
3186}
3187
f684960e
CW		 3188static void
3189intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3190{
53b41837
YN		 3191 struct intel_connector *intel_connector = to_intel_connector(connector);
3192
3f43c48d 3193 intel_attach_force_audio_property(connector);
e953fd7b 3194 intel_attach_broadcast_rgb_property(connector);
55bc60db 3195 intel_dp->color_range_auto = true;
53b41837
YN		 3196
3197 if (is_edp(intel_dp)) {
3198 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3199 drm_object_attach_property(
3200 &connector->base,
53b41837 3201 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3202 DRM_MODE_SCALE_ASPECT);
3203 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3204 }
f684960e
CW		 3205}
3206
67a54566
DV		 3207static void
3208intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3209 struct intel_dp *intel_dp,
3210 struct edp_power_seq *out)
67a54566
DV		 3211{
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3213 struct edp_power_seq cur, vbt, spec, final;
3214 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3215 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3216
3217 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3218 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3219 pp_on_reg = PCH_PP_ON_DELAYS;
3220 pp_off_reg = PCH_PP_OFF_DELAYS;
3221 pp_div_reg = PCH_PP_DIVISOR;
3222 } else {
bf13e81b
JN		 3223 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3224
3225 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3226 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3227 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3228 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3229 }
67a54566
DV		 3230
3231 /* Workaround: Need to write PP_CONTROL with the unlock key as
3232 * the very first thing. */
453c5420 3233 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3234 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3235
453c5420
JB		 3236 pp_on = I915_READ(pp_on_reg);
3237 pp_off = I915_READ(pp_off_reg);
3238 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3239
3240 /* Pull timing values out of registers */
3241 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3242 PANEL_POWER_UP_DELAY_SHIFT;
3243
3244 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3245 PANEL_LIGHT_ON_DELAY_SHIFT;
3246
3247 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3248 PANEL_LIGHT_OFF_DELAY_SHIFT;
3249
3250 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3251 PANEL_POWER_DOWN_DELAY_SHIFT;
3252
3253 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3254 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3255
3256 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3257 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3258
41aa3448 3259 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3260
3261 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3262 * our hw here, which are all in 100usec. */
3263 spec.t1_t3 = 210 * 10;
3264 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3265 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3266 spec.t10 = 500 * 10;
3267 /* This one is special and actually in units of 100ms, but zero
3268 * based in the hw (so we need to add 100 ms). But the sw vbt
3269 * table multiplies it with 1000 to make it in units of 100usec,
3270 * too. */
3271 spec.t11_t12 = (510 + 100) * 10;
3272
3273 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3274 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3275
3276 /* Use the max of the register settings and vbt. If both are
3277 * unset, fall back to the spec limits. */
3278#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3279 spec.field : \
3280 max(cur.field, vbt.field))
3281 assign_final(t1_t3);
3282 assign_final(t8);
3283 assign_final(t9);
3284 assign_final(t10);
3285 assign_final(t11_t12);
3286#undef assign_final
3287
3288#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3289 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3290 intel_dp->backlight_on_delay = get_delay(t8);
3291 intel_dp->backlight_off_delay = get_delay(t9);
3292 intel_dp->panel_power_down_delay = get_delay(t10);
3293 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3294#undef get_delay
3295
f30d26e4
JN		 3296 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3297 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3298 intel_dp->panel_power_cycle_delay);
3299
3300 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3301 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3302
3303 if (out)
3304 *out = final;
3305}
3306
3307static void
3308intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3309 struct intel_dp *intel_dp,
3310 struct edp_power_seq *seq)
3311{
3312 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3313 u32 pp_on, pp_off, pp_div, port_sel = 0;
3314 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3315 int pp_on_reg, pp_off_reg, pp_div_reg;
3316
3317 if (HAS_PCH_SPLIT(dev)) {
3318 pp_on_reg = PCH_PP_ON_DELAYS;
3319 pp_off_reg = PCH_PP_OFF_DELAYS;
3320 pp_div_reg = PCH_PP_DIVISOR;
3321 } else {
bf13e81b
JN		 3322 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3323
3324 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3325 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3326 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3327 }
3328
67a54566 3329 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3330 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3331 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3332 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3333 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3334 /* Compute the divisor for the pp clock, simply match the Bspec
3335 * formula. */
453c5420 3336 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3337 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3338 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3339
3340 /* Haswell doesn't have any port selection bits for the panel
3341 * power sequencer any more. */
bc7d38a4 3342 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3343 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3344 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3345 else
3346 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3347 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3348 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3349 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3350 else
a24c144c 3351 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3352 }
3353
453c5420
JB		 3354 pp_on |= port_sel;
3355
3356 I915_WRITE(pp_on_reg, pp_on);
3357 I915_WRITE(pp_off_reg, pp_off);
3358 I915_WRITE(pp_div_reg, pp_div);
67a54566 3359
67a54566 3360 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3361 I915_READ(pp_on_reg),
3362 I915_READ(pp_off_reg),
3363 I915_READ(pp_div_reg));
f684960e
CW		 3364}
3365
ed92f0b2
PZ		 3366static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3367 struct intel_connector *intel_connector)
3368{
3369 struct drm_connector *connector = &intel_connector->base;
3370 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3371 struct drm_device *dev = intel_dig_port->base.base.dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct drm_display_mode *fixed_mode = NULL;
3374 struct edp_power_seq power_seq = { 0 };
3375 bool has_dpcd;
3376 struct drm_display_mode *scan;
3377 struct edid *edid;
3378
3379 if (!is_edp(intel_dp))
3380 return true;
3381
3382 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3383
3384 /* Cache DPCD and EDID for edp. */
3385 ironlake_edp_panel_vdd_on(intel_dp);
3386 has_dpcd = intel_dp_get_dpcd(intel_dp);
3387 ironlake_edp_panel_vdd_off(intel_dp, false);
3388
3389 if (has_dpcd) {
3390 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3391 dev_priv->no_aux_handshake =
3392 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3393 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3394 } else {
3395 /* if this fails, presume the device is a ghost */
3396 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3397 return false;
3398 }
3399
3400 /* We now know it's not a ghost, init power sequence regs. */
3401 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3402 &power_seq);
3403
3404 ironlake_edp_panel_vdd_on(intel_dp);
3405 edid = drm_get_edid(connector, &intel_dp->adapter);
3406 if (edid) {
3407 if (drm_add_edid_modes(connector, edid)) {
3408 drm_mode_connector_update_edid_property(connector,
3409 edid);
3410 drm_edid_to_eld(connector, edid);
3411 } else {
3412 kfree(edid);
3413 edid = ERR_PTR(-EINVAL);
3414 }
3415 } else {
3416 edid = ERR_PTR(-ENOENT);
3417 }
3418 intel_connector->edid = edid;
3419
3420 /* prefer fixed mode from EDID if available */
3421 list_for_each_entry(scan, &connector->probed_modes, head) {
3422 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3423 fixed_mode = drm_mode_duplicate(dev, scan);
3424 break;
3425 }
3426 }
3427
3428 /* fallback to VBT if available for eDP */
3429 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3430 fixed_mode = drm_mode_duplicate(dev,
3431 dev_priv->vbt.lfp_lvds_vbt_mode);
3432 if (fixed_mode)
3433 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3434 }
3435
3436 ironlake_edp_panel_vdd_off(intel_dp, false);
3437
3438 intel_panel_init(&intel_connector->panel, fixed_mode);
3439 intel_panel_setup_backlight(connector);
3440
3441 return true;
3442}
3443
16c25533 3444bool
f0fec3f2
PZ		 3445intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3446 struct intel_connector *intel_connector)
a4fc5ed6 3447{
f0fec3f2
PZ		 3448 struct drm_connector *connector = &intel_connector->base;
3449 struct intel_dp *intel_dp = &intel_dig_port->dp;
3450 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3451 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3452 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3453 enum port port = intel_dig_port->port;
5eb08b69 3454 const char *name = NULL;
b2a14755 3455 int type, error;
a4fc5ed6 3456
0767935e
DV		 3457 /* Preserve the current hw state. */
3458 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3459 intel_dp->attached_connector = intel_connector;
3d3dc149 3460
f7d24902 3461 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3462 /*
3463 * FIXME : We need to initialize built-in panels before external panels.
3464 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3465 */
f7d24902
ID		 3466 switch (port) {
3467 case PORT_A:
b329530c 3468 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3469 break;
3470 case PORT_C:
3471 if (IS_VALLEYVIEW(dev))
3472 type = DRM_MODE_CONNECTOR_eDP;
3473 break;
3474 case PORT_D:
3475 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3476 type = DRM_MODE_CONNECTOR_eDP;
3477 break;
3478 default: /* silence GCC warning */
3479 break;
b329530c
AJ		 3480 }
3481
f7d24902
ID		 3482 /*
3483 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3484 * for DP the encoder type can be set by the caller to
3485 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3486 */
3487 if (type == DRM_MODE_CONNECTOR_eDP)
3488 intel_encoder->type = INTEL_OUTPUT_EDP;
3489
e7281eab
ID		 3490 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3491 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3492 port_name(port));
3493
b329530c 3494 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3495 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3496
a4fc5ed6
KP		 3497 connector->interlace_allowed = true;
3498 connector->doublescan_allowed = 0;
3499
f0fec3f2
PZ		 3500 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3501 ironlake_panel_vdd_work);
a4fc5ed6 3502
df0e9248 3503 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3504 drm_sysfs_connector_add(connector);
3505
affa9354 3506 if (HAS_DDI(dev))
bcbc889b
PZ		 3507 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3508 else
3509 intel_connector->get_hw_state = intel_connector_get_hw_state;
3510
9ed35ab1
PZ		 3511 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3512 if (HAS_DDI(dev)) {
3513 switch (intel_dig_port->port) {
3514 case PORT_A:
3515 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3516 break;
3517 case PORT_B:
3518 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3519 break;
3520 case PORT_C:
3521 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3522 break;
3523 case PORT_D:
3524 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3525 break;
3526 default:
3527 BUG();
3528 }
3529 }
e8cb4558 3530
a4fc5ed6 3531 /* Set up the DDC bus. */
ab9d7c30
PZ		 3532 switch (port) {
3533 case PORT_A:
1d843f9d 3534 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3535 name = "DPDDC-A";
3536 break;
3537 case PORT_B:
1d843f9d 3538 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3539 name = "DPDDC-B";
3540 break;
3541 case PORT_C:
1d843f9d 3542 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3543 name = "DPDDC-C";
3544 break;
3545 case PORT_D:
1d843f9d 3546 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3547 name = "DPDDC-D";
3548 break;
3549 default:
ad1c0b19 3550 BUG();
5eb08b69
ZW		 3551 }
3552
b2a14755
PZ		 3553 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3554 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3555 error, port_name(port));
c1f05264 3556
2b28bb1b
RV		 3557 intel_dp->psr_setup_done = false;
3558
b2f246a8 3559 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3560 i2c_del_adapter(&intel_dp->adapter);
3561 if (is_edp(intel_dp)) {
3562 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3563 mutex_lock(&dev->mode_config.mutex);
3564 ironlake_panel_vdd_off_sync(intel_dp);
3565 mutex_unlock(&dev->mode_config.mutex);
3566 }
b2f246a8
PZ		 3567 drm_sysfs_connector_remove(connector);
3568 drm_connector_cleanup(connector);
16c25533 3569 return false;
b2f246a8 3570 }
32f9d658 3571
f684960e
CW		 3572 intel_dp_add_properties(intel_dp, connector);
3573
a4fc5ed6
KP		 3574 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3575 * 0xd. Failure to do so will result in spurious interrupts being
3576 * generated on the port when a cable is not attached.
3577 */
3578 if (IS_G4X(dev) && !IS_GM45(dev)) {
3579 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3580 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3581 }
16c25533
PZ		 3582
3583 return true;
a4fc5ed6 3584}
f0fec3f2
PZ		 3585
3586void
3587intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3588{
3589 struct intel_digital_port *intel_dig_port;
3590 struct intel_encoder *intel_encoder;
3591 struct drm_encoder *encoder;
3592 struct intel_connector *intel_connector;
3593
3594 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3595 if (!intel_dig_port)
3596 return;
3597
3598 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3599 if (!intel_connector) {
3600 kfree(intel_dig_port);
3601 return;
3602 }
3603
3604 intel_encoder = &intel_dig_port->base;
3605 encoder = &intel_encoder->base;
3606
3607 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3608 DRM_MODE_ENCODER_TMDS);
3609
5bfe2ac0 3610 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3611 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3612 intel_encoder->disable = intel_disable_dp;
3613 intel_encoder->post_disable = intel_post_disable_dp;
3614 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3615 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3616 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3617 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3618 intel_encoder->pre_enable = vlv_pre_enable_dp;
3619 intel_encoder->enable = vlv_enable_dp;
3620 } else {
ecff4f3b
JN		 3621 intel_encoder->pre_enable = g4x_pre_enable_dp;
3622 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3623 }
f0fec3f2 3624
174edf1f 3625 intel_dig_port->port = port;
f0fec3f2
PZ		 3626 intel_dig_port->dp.output_reg = output_reg;
3627
00c09d70 3628 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3629 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3630 intel_encoder->cloneable = false;
3631 intel_encoder->hot_plug = intel_dp_hot_plug;
3632
15b1d171
PZ		 3633 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3634 drm_encoder_cleanup(encoder);
3635 kfree(intel_dig_port);
b2f246a8 3636 kfree(intel_connector);
15b1d171 3637 }
f0fec3f2 3638}
Linux kernel - Deliverables
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