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drm/i915: Make crtc checking use the atomic state, v2.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf
CML		 50struct dp_link_dpll {
51 int link_bw;
52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
63 { DP_LINK_BW_1_62,
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
65 { DP_LINK_BW_2_7,
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5
CML		 69static const struct dp_link_dpll vlv_dpll[] = {
70 { DP_LINK_BW_1_62,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 72 { DP_LINK_BW_2_7,
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
86 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15 97 324000, 432000, 540000 };
fe51bfb9
VS		 98static const int chv_rates[] = { 162000, 202500, 210000, 216000,
99 243000, 270000, 324000, 405000,
100 420000, 432000, 540000 };
f4896f15 101static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 102
cfcb0fc9
JB		 103/**
104 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
105 * @intel_dp: DP struct
106 *
107 * If a CPU or PCH DP output is attached to an eDP panel, this function
108 * will return true, and false otherwise.
109 */
110static bool is_edp(struct intel_dp *intel_dp)
111{
da63a9f2
PZ		 112 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
113
114 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 115}
116
68b4d824 117static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 118{
68b4d824
ID		 119 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
120
121 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 122}
123
df0e9248
CW		 124static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
125{
fa90ecef 126 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 127}
128
ea5b213a 129static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 130static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 131static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 132static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 133static void vlv_steal_power_sequencer(struct drm_device *dev,
134 enum pipe pipe);
a4fc5ed6 135
ed4e9c1d
VS		 136static int
137intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 138{
7183dc29 139 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 140
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
143 case DP_LINK_BW_2_7:
1db10e28 144 case DP_LINK_BW_5_4:
d4eead50 145 break;
a4fc5ed6 146 default:
d4eead50
ID		 147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
148 max_link_bw);
a4fc5ed6
KP		 149 max_link_bw = DP_LINK_BW_1_62;
150 break;
151 }
152 return max_link_bw;
153}
154
eeb6324d
PZ		 155static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
156{
157 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
158 struct drm_device *dev = intel_dig_port->base.base.dev;
159 u8 source_max, sink_max;
160
161 source_max = 4;
162 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
163 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
164 source_max = 2;
165
166 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 return min(source_max, sink_max);
169}
170
cd9dde44
AJ		 171/*
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
174 *
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
176 *
177 * 270000 * 1 * 8 / 10 == 216000
178 *
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
183 *
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
186 */
187
a4fc5ed6 188static int
c898261c 189intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 190{
cd9dde44 191 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 192}
193
fe27d53e
DA		 194static int
195intel_dp_max_data_rate(int max_link_clock, int max_lanes)
196{
197 return (max_link_clock * max_lanes * 8) / 10;
198}
199
c19de8eb 200static enum drm_mode_status
a4fc5ed6
KP		 201intel_dp_mode_valid(struct drm_connector *connector,
202 struct drm_display_mode *mode)
203{
df0e9248 204 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 205 struct intel_connector *intel_connector = to_intel_connector(connector);
206 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 207 int target_clock = mode->clock;
208 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 209
dd06f90e
JN		 210 if (is_edp(intel_dp) && fixed_mode) {
211 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 212 return MODE_PANEL;
213
dd06f90e 214 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 215 return MODE_PANEL;
03afc4a2
DV		 216
217 target_clock = fixed_mode->clock;
7de56f43
ZY		 218 }
219
50fec21a 220 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 221 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 222
223 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
224 mode_rate = intel_dp_link_required(target_clock, 18);
225
226 if (mode_rate > max_rate)
c4867936 227 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 228
229 if (mode->clock < 10000)
230 return MODE_CLOCK_LOW;
231
0af78a2b
DV		 232 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
233 return MODE_H_ILLEGAL;
234
a4fc5ed6
KP		 235 return MODE_OK;
236}
237
a4f1289e 238uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 239{
240 int i;
241 uint32_t v = 0;
242
243 if (src_bytes > 4)
244 src_bytes = 4;
245 for (i = 0; i < src_bytes; i++)
246 v |= ((uint32_t) src[i]) << ((3-i) * 8);
247 return v;
248}
249
c2af70e2 250static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
bf13e81b
JN		 293static void
294intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 295 struct intel_dp *intel_dp);
bf13e81b
JN		 296static void
297intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 298 struct intel_dp *intel_dp);
bf13e81b 299
773538e8
VS		 300static void pps_lock(struct intel_dp *intel_dp)
301{
302 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
303 struct intel_encoder *encoder = &intel_dig_port->base;
304 struct drm_device *dev = encoder->base.dev;
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 enum intel_display_power_domain power_domain;
307
308 /*
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
311 */
312 power_domain = intel_display_port_power_domain(encoder);
313 intel_display_power_get(dev_priv, power_domain);
314
315 mutex_lock(&dev_priv->pps_mutex);
316}
317
318static void pps_unlock(struct intel_dp *intel_dp)
319{
320 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
321 struct intel_encoder *encoder = &intel_dig_port->base;
322 struct drm_device *dev = encoder->base.dev;
323 struct drm_i915_private *dev_priv = dev->dev_private;
324 enum intel_display_power_domain power_domain;
325
326 mutex_unlock(&dev_priv->pps_mutex);
327
328 power_domain = intel_display_port_power_domain(encoder);
329 intel_display_power_put(dev_priv, power_domain);
330}
331
961a0db0
VS		 332static void
333vlv_power_sequencer_kick(struct intel_dp *intel_dp)
334{
335 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
336 struct drm_device *dev = intel_dig_port->base.base.dev;
337 struct drm_i915_private *dev_priv = dev->dev_private;
338 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 339 bool pll_enabled;
961a0db0
VS		 340 uint32_t DP;
341
342 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe), port_name(intel_dig_port->port)))
345 return;
346
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe), port_name(intel_dig_port->port));
349
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
352 */
353 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
354 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
355 DP |= DP_PORT_WIDTH(1);
356 DP |= DP_LINK_TRAIN_PAT_1;
357
358 if (IS_CHERRYVIEW(dev))
359 DP |= DP_PIPE_SELECT_CHV(pipe);
360 else if (pipe == PIPE_B)
361 DP |= DP_PIPEB_SELECT;
362
d288f65f
VS		 363 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
364
365 /*
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
368 */
369 if (!pll_enabled)
370 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
371 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
372
961a0db0
VS		 373 /*
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
378 */
379 I915_WRITE(intel_dp->output_reg, DP);
380 POSTING_READ(intel_dp->output_reg);
381
382 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
383 POSTING_READ(intel_dp->output_reg);
384
385 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
386 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 387
388 if (!pll_enabled)
389 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 390}
391
bf13e81b
JN		 392static enum pipe
393vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
394{
395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 396 struct drm_device *dev = intel_dig_port->base.base.dev;
397 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 398 struct intel_encoder *encoder;
399 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 400 enum pipe pipe;
bf13e81b 401
e39b999a 402 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 403
a8c3344e
VS		 404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp));
406
a4a5d2f8
VS		 407 if (intel_dp->pps_pipe != INVALID_PIPE)
408 return intel_dp->pps_pipe;
409
410 /*
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
413 */
414 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
415 base.head) {
416 struct intel_dp *tmp;
417
418 if (encoder->type != INTEL_OUTPUT_EDP)
419 continue;
420
421 tmp = enc_to_intel_dp(&encoder->base);
422
423 if (tmp->pps_pipe != INVALID_PIPE)
424 pipes &= ~(1 << tmp->pps_pipe);
425 }
426
427 /*
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
430 */
431 if (WARN_ON(pipes == 0))
a8c3344e
VS		 432 pipe = PIPE_A;
433 else
434 pipe = ffs(pipes) - 1;
a4a5d2f8 435
a8c3344e
VS		 436 vlv_steal_power_sequencer(dev, pipe);
437 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 438
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp->pps_pipe),
441 port_name(intel_dig_port->port));
442
443 /* init power sequencer on this pipe and port */
36b5f425
VS		 444 intel_dp_init_panel_power_sequencer(dev, intel_dp);
445 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 446
961a0db0
VS		 447 /*
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
450 */
451 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 452
453 return intel_dp->pps_pipe;
454}
455
6491ab27
VS		 456typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
457 enum pipe pipe);
458
459static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
460 enum pipe pipe)
461{
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
463}
464
465static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
466 enum pipe pipe)
467{
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
469}
470
471static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
472 enum pipe pipe)
473{
474 return true;
475}
bf13e81b 476
a4a5d2f8 477static enum pipe
6491ab27
VS		 478vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
479 enum port port,
480 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 481{
482 enum pipe pipe;
bf13e81b 483
bf13e81b
JN		 484 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
485 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
486 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 487
488 if (port_sel != PANEL_PORT_SELECT_VLV(port))
489 continue;
490
6491ab27
VS		 491 if (!pipe_check(dev_priv, pipe))
492 continue;
493
a4a5d2f8 494 return pipe;
bf13e81b
JN		 495 }
496
a4a5d2f8
VS		 497 return INVALID_PIPE;
498}
499
500static void
501vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
502{
503 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
504 struct drm_device *dev = intel_dig_port->base.base.dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 506 enum port port = intel_dig_port->port;
507
508 lockdep_assert_held(&dev_priv->pps_mutex);
509
510 /* try to find a pipe with this port selected */
6491ab27
VS		 511 /* first pick one where the panel is on */
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_has_pp_on);
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp->pps_pipe == INVALID_PIPE)
516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
517 vlv_pipe_has_vdd_on);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp->pps_pipe == INVALID_PIPE)
520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
521 vlv_pipe_any);
a4a5d2f8
VS		 522
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp->pps_pipe == INVALID_PIPE) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
526 port_name(port));
527 return;
bf13e81b
JN		 528 }
529
a4a5d2f8
VS		 530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port), pipe_name(intel_dp->pps_pipe));
532
36b5f425
VS		 533 intel_dp_init_panel_power_sequencer(dev, intel_dp);
534 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 535}
536
773538e8
VS		 537void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
538{
539 struct drm_device *dev = dev_priv->dev;
540 struct intel_encoder *encoder;
541
542 if (WARN_ON(!IS_VALLEYVIEW(dev)))
543 return;
544
545 /*
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
553 */
554
555 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
556 struct intel_dp *intel_dp;
557
558 if (encoder->type != INTEL_OUTPUT_EDP)
559 continue;
560
561 intel_dp = enc_to_intel_dp(&encoder->base);
562 intel_dp->pps_pipe = INVALID_PIPE;
563 }
bf13e81b
JN		 564}
565
566static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
567{
568 struct drm_device *dev = intel_dp_to_dev(intel_dp);
569
b0a08bec
VK		 570 if (IS_BROXTON(dev))
571 return BXT_PP_CONTROL(0);
572 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 573 return PCH_PP_CONTROL;
574 else
575 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
576}
577
578static u32 _pp_stat_reg(struct intel_dp *intel_dp)
579{
580 struct drm_device *dev = intel_dp_to_dev(intel_dp);
581
b0a08bec
VK		 582 if (IS_BROXTON(dev))
583 return BXT_PP_STATUS(0);
584 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 585 return PCH_PP_STATUS;
586 else
587 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
588}
589
01527b31
CT		 590/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
591 This function only applicable when panel PM state is not to be tracked */
592static int edp_notify_handler(struct notifier_block *this, unsigned long code,
593 void *unused)
594{
595 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
596 edp_notifier);
597 struct drm_device *dev = intel_dp_to_dev(intel_dp);
598 struct drm_i915_private *dev_priv = dev->dev_private;
599 u32 pp_div;
600 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 601
602 if (!is_edp(intel_dp) || code != SYS_RESTART)
603 return 0;
604
773538e8 605 pps_lock(intel_dp);
e39b999a 606
01527b31 607 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 608 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
609
01527b31
CT		 610 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
611 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
612 pp_div = I915_READ(pp_div_reg);
613 pp_div &= PP_REFERENCE_DIVIDER_MASK;
614
615 /* 0x1F write to PP_DIV_REG sets max cycle delay */
616 I915_WRITE(pp_div_reg, pp_div | 0x1F);
617 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
618 msleep(intel_dp->panel_power_cycle_delay);
619 }
620
773538e8 621 pps_unlock(intel_dp);
e39b999a 622
01527b31
CT		 623 return 0;
624}
625
4be73780 626static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 627{
30add22d 628 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 629 struct drm_i915_private *dev_priv = dev->dev_private;
630
e39b999a
VS		 631 lockdep_assert_held(&dev_priv->pps_mutex);
632
9a42356b
VS		 633 if (IS_VALLEYVIEW(dev) &&
634 intel_dp->pps_pipe == INVALID_PIPE)
635 return false;
636
bf13e81b 637 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 638}
639
4be73780 640static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 641{
30add22d 642 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 643 struct drm_i915_private *dev_priv = dev->dev_private;
644
e39b999a
VS		 645 lockdep_assert_held(&dev_priv->pps_mutex);
646
9a42356b
VS		 647 if (IS_VALLEYVIEW(dev) &&
648 intel_dp->pps_pipe == INVALID_PIPE)
649 return false;
650
773538e8 651 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 652}
653
9b984dae
KP		 654static void
655intel_dp_check_edp(struct intel_dp *intel_dp)
656{
30add22d 657 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 658 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 659
9b984dae
KP		 660 if (!is_edp(intel_dp))
661 return;
453c5420 662
4be73780 663 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 664 WARN(1, "eDP powered off while attempting aux channel communication.\n");
665 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 666 I915_READ(_pp_stat_reg(intel_dp)),
667 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 668 }
669}
670
9ee32fea
DV		 671static uint32_t
672intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
673{
674 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
675 struct drm_device *dev = intel_dig_port->base.base.dev;
676 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 677 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 678 uint32_t status;
679 bool done;
680
ef04f00d 681#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 682 if (has_aux_irq)
b18ac466 683 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 684 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 685 else
686 done = wait_for_atomic(C, 10) == 0;
687 if (!done)
688 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
689 has_aux_irq);
690#undef C
691
692 return status;
693}
694
ec5b01dd 695static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 696{
174edf1f
PZ		 697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 699
ec5b01dd
DL		 700 /*
701 * The clock divider is based off the hrawclk, and would like to run at
702 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 703 */
ec5b01dd
DL		 704 return index ? 0 : intel_hrawclk(dev) / 2;
705}
706
707static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
708{
709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
710 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 711 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 712
713 if (index)
714 return 0;
715
716 if (intel_dig_port->port == PORT_A) {
05024da3
VS		 717 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
718
ec5b01dd
DL		 719 } else {
720 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
721 }
722}
723
724static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
725{
726 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
727 struct drm_device *dev = intel_dig_port->base.base.dev;
728 struct drm_i915_private *dev_priv = dev->dev_private;
729
730 if (intel_dig_port->port == PORT_A) {
731 if (index)
732 return 0;
05024da3 733 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
2c55c336
JN		 734 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
735 /* Workaround for non-ULT HSW */
bc86625a
CW		 736 switch (index) {
737 case 0: return 63;
738 case 1: return 72;
739 default: return 0;
740 }
ec5b01dd 741 } else {
bc86625a 742 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 743 }
b84a1cf8
RV		 744}
745
ec5b01dd
DL		 746static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
747{
748 return index ? 0 : 100;
749}
750
b6b5e383
DL		 751static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
752{
753 /*
754 * SKL doesn't need us to program the AUX clock divider (Hardware will
755 * derive the clock from CDCLK automatically). We still implement the
756 * get_aux_clock_divider vfunc to plug-in into the existing code.
757 */
758 return index ? 0 : 1;
759}
760
5ed12a19
DL		 761static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
762 bool has_aux_irq,
763 int send_bytes,
764 uint32_t aux_clock_divider)
765{
766 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
767 struct drm_device *dev = intel_dig_port->base.base.dev;
768 uint32_t precharge, timeout;
769
770 if (IS_GEN6(dev))
771 precharge = 3;
772 else
773 precharge = 5;
774
775 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
776 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
777 else
778 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
779
780 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 781 DP_AUX_CH_CTL_DONE |
5ed12a19 782 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 783 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 784 timeout |
788d4433 785 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 786 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
787 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 788 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 789}
790
b9ca5fad
DL		 791static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
792 bool has_aux_irq,
793 int send_bytes,
794 uint32_t unused)
795{
796 return DP_AUX_CH_CTL_SEND_BUSY |
797 DP_AUX_CH_CTL_DONE |
798 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR |
800 DP_AUX_CH_CTL_TIME_OUT_1600us |
801 DP_AUX_CH_CTL_RECEIVE_ERROR |
802 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
803 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
804}
805
b84a1cf8
RV		 806static int
807intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 808 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 809 uint8_t *recv, int recv_size)
810{
811 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
812 struct drm_device *dev = intel_dig_port->base.base.dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
815 uint32_t ch_data = ch_ctl + 4;
bc86625a 816 uint32_t aux_clock_divider;
b84a1cf8
RV		 817 int i, ret, recv_bytes;
818 uint32_t status;
5ed12a19 819 int try, clock = 0;
4e6b788c 820 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 821 bool vdd;
822
773538e8 823 pps_lock(intel_dp);
e39b999a 824
72c3500a
VS		 825 /*
826 * We will be called with VDD already enabled for dpcd/edid/oui reads.
827 * In such cases we want to leave VDD enabled and it's up to upper layers
828 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
829 * ourselves.
830 */
1e0560e0 831 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 832
833 /* dp aux is extremely sensitive to irq latency, hence request the
834 * lowest possible wakeup latency and so prevent the cpu from going into
835 * deep sleep states.
836 */
837 pm_qos_update_request(&dev_priv->pm_qos, 0);
838
839 intel_dp_check_edp(intel_dp);
5eb08b69 840
c67a470b
PZ		 841 intel_aux_display_runtime_get(dev_priv);
842
11bee43e
JB		 843 /* Try to wait for any previous AUX channel activity */
844 for (try = 0; try < 3; try++) {
ef04f00d 845 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 846 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
847 break;
848 msleep(1);
849 }
850
851 if (try == 3) {
852 WARN(1, "dp_aux_ch not started status 0x%08x\n",
853 I915_READ(ch_ctl));
9ee32fea
DV		 854 ret = -EBUSY;
855 goto out;
4f7f7b7e
CW		 856 }
857
46a5ae9f
PZ		 858 /* Only 5 data registers! */
859 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
860 ret = -E2BIG;
861 goto out;
862 }
863
ec5b01dd 864 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 865 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
866 has_aux_irq,
867 send_bytes,
868 aux_clock_divider);
5ed12a19 869
bc86625a
CW		 870 /* Must try at least 3 times according to DP spec */
871 for (try = 0; try < 5; try++) {
872 /* Load the send data into the aux channel data registers */
873 for (i = 0; i < send_bytes; i += 4)
874 I915_WRITE(ch_data + i,
a4f1289e
RV		 875 intel_dp_pack_aux(send + i,
876 send_bytes - i));
bc86625a
CW		 877
878 /* Send the command and wait for it to complete */
5ed12a19 879 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 880
881 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
882
883 /* Clear done status and any errors */
884 I915_WRITE(ch_ctl,
885 status |
886 DP_AUX_CH_CTL_DONE |
887 DP_AUX_CH_CTL_TIME_OUT_ERROR |
888 DP_AUX_CH_CTL_RECEIVE_ERROR);
889
74ebf294 890 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 891 continue;
74ebf294
TP		 892
893 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
894 * 400us delay required for errors and timeouts
895 * Timeout errors from the HW already meet this
896 * requirement so skip to next iteration
897 */
898 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
899 usleep_range(400, 500);
bc86625a 900 continue;
74ebf294 901 }
bc86625a 902 if (status & DP_AUX_CH_CTL_DONE)
e058c945 903 goto done;
bc86625a 904 }
a4fc5ed6
KP		 905 }
906
a4fc5ed6 907 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 908 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 909 ret = -EBUSY;
910 goto out;
a4fc5ed6
KP		 911 }
912
e058c945 913done:
a4fc5ed6
KP		 914 /* Check for timeout or receive error.
915 * Timeouts occur when the sink is not connected
916 */
a5b3da54 917 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 918 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 919 ret = -EIO;
920 goto out;
a5b3da54 921 }
1ae8c0a5
KP		 922
923 /* Timeouts occur when the device isn't connected, so they're
924 * "normal" -- don't fill the kernel log with these */
a5b3da54 925 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 926 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 927 ret = -ETIMEDOUT;
928 goto out;
a4fc5ed6
KP		 929 }
930
931 /* Unload any bytes sent back from the other side */
932 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
933 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 934 if (recv_bytes > recv_size)
935 recv_bytes = recv_size;
0206e353 936
4f7f7b7e 937 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 938 intel_dp_unpack_aux(I915_READ(ch_data + i),
939 recv + i, recv_bytes - i);
a4fc5ed6 940
9ee32fea
DV		 941 ret = recv_bytes;
942out:
943 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 944 intel_aux_display_runtime_put(dev_priv);
9ee32fea 945
884f19e9
JN		 946 if (vdd)
947 edp_panel_vdd_off(intel_dp, false);
948
773538e8 949 pps_unlock(intel_dp);
e39b999a 950
9ee32fea 951 return ret;
a4fc5ed6
KP		 952}
953
a6c8aff0
JN		 954#define BARE_ADDRESS_SIZE 3
955#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 956static ssize_t
957intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 958{
9d1a1031
JN		 959 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
960 uint8_t txbuf[20], rxbuf[20];
961 size_t txsize, rxsize;
a4fc5ed6 962 int ret;
a4fc5ed6 963
d2d9cbbd
VS		 964 txbuf[0] = (msg->request << 4) |
965 ((msg->address >> 16) & 0xf);
966 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 967 txbuf[2] = msg->address & 0xff;
968 txbuf[3] = msg->size - 1;
46a5ae9f 969
9d1a1031
JN		 970 switch (msg->request & ~DP_AUX_I2C_MOT) {
971 case DP_AUX_NATIVE_WRITE:
972 case DP_AUX_I2C_WRITE:
a6c8aff0 973 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 974 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 975
9d1a1031
JN		 976 if (WARN_ON(txsize > 20))
977 return -E2BIG;
a4fc5ed6 978
9d1a1031 979 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 980
9d1a1031
JN		 981 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
982 if (ret > 0) {
983 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 984
a1ddefd8
JN		 985 if (ret > 1) {
986 /* Number of bytes written in a short write. */
987 ret = clamp_t(int, rxbuf[1], 0, msg->size);
988 } else {
989 /* Return payload size. */
990 ret = msg->size;
991 }
9d1a1031
JN		 992 }
993 break;
46a5ae9f 994
9d1a1031
JN		 995 case DP_AUX_NATIVE_READ:
996 case DP_AUX_I2C_READ:
a6c8aff0 997 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 998 rxsize = msg->size + 1;
a4fc5ed6 999
9d1a1031
JN		 1000 if (WARN_ON(rxsize > 20))
1001 return -E2BIG;
a4fc5ed6 1002
9d1a1031
JN		 1003 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1004 if (ret > 0) {
1005 msg->reply = rxbuf[0] >> 4;
1006 /*
1007 * Assume happy day, and copy the data. The caller is
1008 * expected to check msg->reply before touching it.
1009 *
1010 * Return payload size.
1011 */
1012 ret--;
1013 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1014 }
9d1a1031
JN		 1015 break;
1016
1017 default:
1018 ret = -EINVAL;
1019 break;
a4fc5ed6 1020 }
f51a44b9 1021
9d1a1031 1022 return ret;
a4fc5ed6
KP		 1023}
1024
9d1a1031
JN		 1025static void
1026intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1027{
1028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1029 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1030 enum port port = intel_dig_port->port;
0b99836f 1031 const char *name = NULL;
ab2c0672
DA		 1032 int ret;
1033
33ad6626
JN		 1034 switch (port) {
1035 case PORT_A:
1036 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1037 name = "DPDDC-A";
ab2c0672 1038 break;
33ad6626
JN		 1039 case PORT_B:
1040 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1041 name = "DPDDC-B";
ab2c0672 1042 break;
33ad6626
JN		 1043 case PORT_C:
1044 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1045 name = "DPDDC-C";
ab2c0672 1046 break;
33ad6626
JN		 1047 case PORT_D:
1048 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1049 name = "DPDDC-D";
33ad6626
JN		 1050 break;
1051 default:
1052 BUG();
ab2c0672
DA		 1053 }
1054
1b1aad75
DL		 1055 /*
1056 * The AUX_CTL register is usually DP_CTL + 0x10.
1057 *
1058 * On Haswell and Broadwell though:
1059 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1060 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1061 *
1062 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1063 */
1064 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1065 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1066
0b99836f 1067 intel_dp->aux.name = name;
9d1a1031
JN		 1068 intel_dp->aux.dev = dev->dev;
1069 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1070
0b99836f
JN		 1071 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1072 connector->base.kdev->kobj.name);
8316f337 1073
4f71d0cb 1074 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1075 if (ret < 0) {
4f71d0cb 1076 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1077 name, ret);
1078 return;
ab2c0672 1079 }
8a5e6aeb 1080
0b99836f
JN		 1081 ret = sysfs_create_link(&connector->base.kdev->kobj,
1082 &intel_dp->aux.ddc.dev.kobj,
1083 intel_dp->aux.ddc.dev.kobj.name);
1084 if (ret < 0) {
1085 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1086 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1087 }
a4fc5ed6
KP		 1088}
1089
80f65de3
ID		 1090static void
1091intel_dp_connector_unregister(struct intel_connector *intel_connector)
1092{
1093 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1094
0e32b39c
DA		 1095 if (!intel_connector->mst_port)
1096 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1097 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1098 intel_connector_unregister(intel_connector);
1099}
1100
5416d871 1101static void
c3346ef6 1102skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
5416d871
DL		 1103{
1104 u32 ctrl1;
1105
dd3cd74a
ACO		 1106 memset(&pipe_config->dpll_hw_state, 0,
1107 sizeof(pipe_config->dpll_hw_state));
1108
5416d871
DL		 1109 pipe_config->ddi_pll_sel = SKL_DPLL0;
1110 pipe_config->dpll_hw_state.cfgcr1 = 0;
1111 pipe_config->dpll_hw_state.cfgcr2 = 0;
1112
1113 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
c3346ef6
SJ		 1114 switch (link_clock / 2) {
1115 case 81000:
71cd8423 1116 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5416d871
DL		 1117 SKL_DPLL0);
1118 break;
c3346ef6 1119 case 135000:
71cd8423 1120 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
5416d871
DL		 1121 SKL_DPLL0);
1122 break;
c3346ef6 1123 case 270000:
71cd8423 1124 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
5416d871
DL		 1125 SKL_DPLL0);
1126 break;
c3346ef6 1127 case 162000:
71cd8423 1128 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
c3346ef6
SJ		 1129 SKL_DPLL0);
1130 break;
1131 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1132 results in CDCLK change. Need to handle the change of CDCLK by
1133 disabling pipes and re-enabling them */
1134 case 108000:
71cd8423 1135 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
c3346ef6
SJ		 1136 SKL_DPLL0);
1137 break;
1138 case 216000:
71cd8423 1139 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
c3346ef6
SJ		 1140 SKL_DPLL0);
1141 break;
1142
5416d871
DL		 1143 }
1144 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1145}
1146
0e50338c 1147static void
5cec258b 1148hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c 1149{
ee46f3c7
ACO		 1150 memset(&pipe_config->dpll_hw_state, 0,
1151 sizeof(pipe_config->dpll_hw_state));
1152
0e50338c
DV		 1153 switch (link_bw) {
1154 case DP_LINK_BW_1_62:
1155 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1156 break;
1157 case DP_LINK_BW_2_7:
1158 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1159 break;
1160 case DP_LINK_BW_5_4:
1161 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1162 break;
1163 }
1164}
1165
fc0f8e25 1166static int
12f6a2e2 1167intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1168{
94ca719e
VS		 1169 if (intel_dp->num_sink_rates) {
1170 *sink_rates = intel_dp->sink_rates;
1171 return intel_dp->num_sink_rates;
fc0f8e25 1172 }
12f6a2e2
VS		 1173
1174 *sink_rates = default_rates;
1175
1176 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1177}
1178
a8f3ef61 1179static int
1db10e28 1180intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
a8f3ef61 1181{
64987fc5
SJ		 1182 if (IS_BROXTON(dev)) {
1183 *source_rates = bxt_rates;
1184 return ARRAY_SIZE(bxt_rates);
1185 } else if (IS_SKYLAKE(dev)) {
637a9c63
SJ		 1186 *source_rates = skl_rates;
1187 return ARRAY_SIZE(skl_rates);
fe51bfb9
VS		 1188 } else if (IS_CHERRYVIEW(dev)) {
1189 *source_rates = chv_rates;
1190 return ARRAY_SIZE(chv_rates);
a8f3ef61 1191 }
636280ba
VS		 1192
1193 *source_rates = default_rates;
1194
1db10e28
VS		 1195 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1196 /* WaDisableHBR2:skl */
1197 return (DP_LINK_BW_2_7 >> 3) + 1;
1198 else if (INTEL_INFO(dev)->gen >= 8 ||
1199 (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1200 return (DP_LINK_BW_5_4 >> 3) + 1;
1201 else
1202 return (DP_LINK_BW_2_7 >> 3) + 1;
a8f3ef61
SJ		 1203}
1204
c6bb3538
DV		 1205static void
1206intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1207 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1208{
1209 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1210 const struct dp_link_dpll *divisor = NULL;
1211 int i, count = 0;
c6bb3538
DV		 1212
1213 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1214 divisor = gen4_dpll;
1215 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1216 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1217 divisor = pch_dpll;
1218 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1219 } else if (IS_CHERRYVIEW(dev)) {
1220 divisor = chv_dpll;
1221 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1222 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1223 divisor = vlv_dpll;
1224 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1225 }
9dd4ffdf
CML		 1226
1227 if (divisor && count) {
1228 for (i = 0; i < count; i++) {
1229 if (link_bw == divisor[i].link_bw) {
1230 pipe_config->dpll = divisor[i].dpll;
1231 pipe_config->clock_set = true;
1232 break;
1233 }
1234 }
c6bb3538
DV		 1235 }
1236}
1237
2ecae76a
VS		 1238static int intersect_rates(const int *source_rates, int source_len,
1239 const int *sink_rates, int sink_len,
94ca719e 1240 int *common_rates)
a8f3ef61
SJ		 1241{
1242 int i = 0, j = 0, k = 0;
1243
a8f3ef61
SJ		 1244 while (i < source_len && j < sink_len) {
1245 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1246 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1247 return k;
94ca719e 1248 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1249 ++k;
1250 ++i;
1251 ++j;
1252 } else if (source_rates[i] < sink_rates[j]) {
1253 ++i;
1254 } else {
1255 ++j;
1256 }
1257 }
1258 return k;
1259}
1260
94ca719e
VS		 1261static int intel_dp_common_rates(struct intel_dp *intel_dp,
1262 int *common_rates)
2ecae76a
VS		 1263{
1264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1265 const int *source_rates, *sink_rates;
1266 int source_len, sink_len;
1267
1268 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1269 source_len = intel_dp_source_rates(dev, &source_rates);
1270
1271 return intersect_rates(source_rates, source_len,
1272 sink_rates, sink_len,
94ca719e 1273 common_rates);
2ecae76a
VS		 1274}
1275
0336400e
VS		 1276static void snprintf_int_array(char *str, size_t len,
1277 const int *array, int nelem)
1278{
1279 int i;
1280
1281 str[0] = '\0';
1282
1283 for (i = 0; i < nelem; i++) {
b2f505be 1284 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1285 if (r >= len)
1286 return;
1287 str += r;
1288 len -= r;
1289 }
1290}
1291
1292static void intel_dp_print_rates(struct intel_dp *intel_dp)
1293{
1294 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1295 const int *source_rates, *sink_rates;
94ca719e
VS		 1296 int source_len, sink_len, common_len;
1297 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1298 char str[128]; /* FIXME: too big for stack? */
1299
1300 if ((drm_debug & DRM_UT_KMS) == 0)
1301 return;
1302
1303 source_len = intel_dp_source_rates(dev, &source_rates);
1304 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1305 DRM_DEBUG_KMS("source rates: %s\n", str);
1306
1307 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1308 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1309 DRM_DEBUG_KMS("sink rates: %s\n", str);
1310
94ca719e
VS		 1311 common_len = intel_dp_common_rates(intel_dp, common_rates);
1312 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1313 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1314}
1315
f4896f15 1316static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1317{
1318 int i = 0;
1319
1320 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1321 if (find == rates[i])
1322 break;
1323
1324 return i;
1325}
1326
50fec21a
VS		 1327int
1328intel_dp_max_link_rate(struct intel_dp *intel_dp)
1329{
1330 int rates[DP_MAX_SUPPORTED_RATES] = {};
1331 int len;
1332
94ca719e 1333 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1334 if (WARN_ON(len <= 0))
1335 return 162000;
1336
1337 return rates[rate_to_index(0, rates) - 1];
1338}
1339
ed4e9c1d
VS		 1340int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1341{
94ca719e 1342 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1343}
1344
00c09d70 1345bool
5bfe2ac0 1346intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1347 struct intel_crtc_state *pipe_config)
a4fc5ed6 1348{
5bfe2ac0 1349 struct drm_device *dev = encoder->base.dev;
36008365 1350 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1351 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1352 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1353 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1354 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1355 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1356 int lane_count, clock;
56071a20 1357 int min_lane_count = 1;
eeb6324d 1358 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1359 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1360 int min_clock = 0;
a8f3ef61 1361 int max_clock;
083f9560 1362 int bpp, mode_rate;
ff9a6750 1363 int link_avail, link_clock;
94ca719e
VS		 1364 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1365 int common_len;
a8f3ef61 1366
94ca719e 1367 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1368
1369 /* No common link rates between source and sink */
94ca719e 1370 WARN_ON(common_len <= 0);
a8f3ef61 1371
94ca719e 1372 max_clock = common_len - 1;
a4fc5ed6 1373
bc7d38a4 1374 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1375 pipe_config->has_pch_encoder = true;
1376
03afc4a2 1377 pipe_config->has_dp_encoder = true;
f769cd24 1378 pipe_config->has_drrs = false;
9fcb1704 1379 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1380
dd06f90e
JN		 1381 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1382 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1383 adjusted_mode);
a1b2278e
CK		 1384
1385 if (INTEL_INFO(dev)->gen >= 9) {
1386 int ret;
e435d6e5 1387 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1388 if (ret)
1389 return ret;
1390 }
1391
2dd24552
JB		 1392 if (!HAS_PCH_SPLIT(dev))
1393 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1394 intel_connector->panel.fitting_mode);
1395 else
b074cec8
JB		 1396 intel_pch_panel_fitting(intel_crtc, pipe_config,
1397 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1398 }
1399
cb1793ce 1400 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1401 return false;
1402
083f9560 1403 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1404 "max bw %d pixel clock %iKHz\n",
94ca719e 1405 max_lane_count, common_rates[max_clock],
241bfc38 1406 adjusted_mode->crtc_clock);
083f9560 1407
36008365
DV		 1408 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1409 * bpc in between. */
3e7ca985 1410 bpp = pipe_config->pipe_bpp;
56071a20 1411 if (is_edp(intel_dp)) {
22ce5628
TS		 1412
1413 /* Get bpp from vbt only for panels that dont have bpp in edid */
1414 if (intel_connector->base.display_info.bpc == 0 &&
1415 (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
56071a20
JN		 1416 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1417 dev_priv->vbt.edp_bpp);
1418 bpp = dev_priv->vbt.edp_bpp;
1419 }
1420
344c5bbc
JN		 1421 /*
1422 * Use the maximum clock and number of lanes the eDP panel
1423 * advertizes being capable of. The panels are generally
1424 * designed to support only a single clock and lane
1425 * configuration, and typically these values correspond to the
1426 * native resolution of the panel.
1427 */
1428 min_lane_count = max_lane_count;
1429 min_clock = max_clock;
7984211e 1430 }
657445fe 1431
36008365 1432 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1433 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1434 bpp);
36008365 1435
c6930992 1436 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1437 for (lane_count = min_lane_count;
1438 lane_count <= max_lane_count;
1439 lane_count <<= 1) {
1440
94ca719e 1441 link_clock = common_rates[clock];
36008365
DV		 1442 link_avail = intel_dp_max_data_rate(link_clock,
1443 lane_count);
1444
1445 if (mode_rate <= link_avail) {
1446 goto found;
1447 }
1448 }
1449 }
1450 }
c4867936 1451
36008365 1452 return false;
3685a8f3 1453
36008365 1454found:
55bc60db
VS		 1455 if (intel_dp->color_range_auto) {
1456 /*
1457 * See:
1458 * CEA-861-E - 5.1 Default Encoding Parameters
1459 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1460 */
18316c8c 1461 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1462 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1463 else
1464 intel_dp->color_range = 0;
1465 }
1466
3685a8f3 1467 if (intel_dp->color_range)
50f3b016 1468 pipe_config->limited_color_range = true;
a4fc5ed6 1469
36008365 1470 intel_dp->lane_count = lane_count;
a8f3ef61 1471
94ca719e 1472 if (intel_dp->num_sink_rates) {
bc27b7d3 1473 intel_dp->link_bw = 0;
a8f3ef61 1474 intel_dp->rate_select =
94ca719e 1475 intel_dp_rate_select(intel_dp, common_rates[clock]);
bc27b7d3
VS		 1476 } else {
1477 intel_dp->link_bw =
94ca719e 1478 drm_dp_link_rate_to_bw_code(common_rates[clock]);
bc27b7d3 1479 intel_dp->rate_select = 0;
a8f3ef61
SJ		 1480 }
1481
657445fe 1482 pipe_config->pipe_bpp = bpp;
94ca719e 1483 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1484
36008365
DV		 1485 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1486 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1487 pipe_config->port_clock, bpp);
36008365
DV		 1488 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1489 mode_rate, link_avail);
a4fc5ed6 1490
03afc4a2 1491 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1492 adjusted_mode->crtc_clock,
1493 pipe_config->port_clock,
03afc4a2 1494 &pipe_config->dp_m_n);
9d1a455b 1495
439d7ac0 1496 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1497 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1498 pipe_config->has_drrs = true;
439d7ac0
PB		 1499 intel_link_compute_m_n(bpp, lane_count,
1500 intel_connector->panel.downclock_mode->clock,
1501 pipe_config->port_clock,
1502 &pipe_config->dp_m2_n2);
1503 }
1504
5416d871 1505 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
94ca719e 1506 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
977bb38d
S		 1507 else if (IS_BROXTON(dev))
1508 /* handled in ddi */;
5416d871 1509 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1510 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1511 else
1512 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1513
03afc4a2 1514 return true;
a4fc5ed6
KP		 1515}
1516
7c62a164 1517static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1518{
7c62a164
DV		 1519 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1520 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1521 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1522 struct drm_i915_private *dev_priv = dev->dev_private;
1523 u32 dpa_ctl;
1524
6e3c9717
ACO		 1525 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1526 crtc->config->port_clock);
ea9b6006
DV		 1527 dpa_ctl = I915_READ(DP_A);
1528 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1529
6e3c9717 1530 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1531 /* For a long time we've carried around a ILK-DevA w/a for the
1532 * 160MHz clock. If we're really unlucky, it's still required.
1533 */
1534 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1535 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1536 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1537 } else {
1538 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1539 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1540 }
1ce17038 1541
ea9b6006
DV		 1542 I915_WRITE(DP_A, dpa_ctl);
1543
1544 POSTING_READ(DP_A);
1545 udelay(500);
1546}
1547
8ac33ed3 1548static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1549{
b934223d 1550 struct drm_device *dev = encoder->base.dev;
417e822d 1551 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1552 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1553 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1554 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1555 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1556
417e822d 1557 /*
1a2eb460 1558 * There are four kinds of DP registers:
417e822d
KP		 1559 *
1560 * IBX PCH
1a2eb460
KP		 1561 * SNB CPU
1562 * IVB CPU
417e822d
KP		 1563 * CPT PCH
1564 *
1565 * IBX PCH and CPU are the same for almost everything,
1566 * except that the CPU DP PLL is configured in this
1567 * register
1568 *
1569 * CPT PCH is quite different, having many bits moved
1570 * to the TRANS_DP_CTL register instead. That
1571 * configuration happens (oddly) in ironlake_pch_enable
1572 */
9c9e7927 1573
417e822d
KP		 1574 /* Preserve the BIOS-computed detected bit. This is
1575 * supposed to be read-only.
1576 */
1577 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1578
417e822d 1579 /* Handle DP bits in common between all three register formats */
417e822d 1580 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1581 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1582
6e3c9717 1583 if (crtc->config->has_audio)
ea5b213a 1584 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1585
417e822d 1586 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1587
39e5fa88 1588 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1589 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1590 intel_dp->DP |= DP_SYNC_HS_HIGH;
1591 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1592 intel_dp->DP |= DP_SYNC_VS_HIGH;
1593 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1594
6aba5b6c 1595 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1596 intel_dp->DP |= DP_ENHANCED_FRAMING;
1597
7c62a164 1598 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1599 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1600 u32 trans_dp;
1601
39e5fa88 1602 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1603
1604 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1605 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1606 trans_dp |= TRANS_DP_ENH_FRAMING;
1607 else
1608 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1609 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1610 } else {
b2634017 1611 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1612 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1613
1614 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1615 intel_dp->DP |= DP_SYNC_HS_HIGH;
1616 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1617 intel_dp->DP |= DP_SYNC_VS_HIGH;
1618 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1619
6aba5b6c 1620 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1621 intel_dp->DP |= DP_ENHANCED_FRAMING;
1622
39e5fa88 1623 if (IS_CHERRYVIEW(dev))
44f37d1f 1624 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1625 else if (crtc->pipe == PIPE_B)
1626 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1627 }
a4fc5ed6
KP		 1628}
1629
ffd6749d
PZ		 1630#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1631#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1632
1a5ef5b7
PZ		 1633#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1634#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1635
ffd6749d
PZ		 1636#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1637#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1638
4be73780 1639static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1640 u32 mask,
1641 u32 value)
bd943159 1642{
30add22d 1643 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1644 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1645 u32 pp_stat_reg, pp_ctrl_reg;
1646
e39b999a
VS		 1647 lockdep_assert_held(&dev_priv->pps_mutex);
1648
bf13e81b
JN		 1649 pp_stat_reg = _pp_stat_reg(intel_dp);
1650 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1651
99ea7127 1652 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1653 mask, value,
1654 I915_READ(pp_stat_reg),
1655 I915_READ(pp_ctrl_reg));
32ce697c 1656
453c5420 1657 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1658 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1659 I915_READ(pp_stat_reg),
1660 I915_READ(pp_ctrl_reg));
32ce697c 1661 }
54c136d4
CW		 1662
1663 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1664}
32ce697c 1665
4be73780 1666static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1667{
1668 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1669 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1670}
1671
4be73780 1672static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1673{
1674 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1675 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1676}
1677
4be73780 1678static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1679{
1680 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1681
1682 /* When we disable the VDD override bit last we have to do the manual
1683 * wait. */
1684 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1685 intel_dp->panel_power_cycle_delay);
1686
4be73780 1687 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1688}
1689
4be73780 1690static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1691{
1692 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1693 intel_dp->backlight_on_delay);
1694}
1695
4be73780 1696static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1697{
1698 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1699 intel_dp->backlight_off_delay);
1700}
99ea7127 1701
832dd3c1
KP		 1702/* Read the current pp_control value, unlocking the register if it
1703 * is locked
1704 */
1705
453c5420 1706static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1707{
453c5420
JB		 1708 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710 u32 control;
832dd3c1 1711
e39b999a
VS		 1712 lockdep_assert_held(&dev_priv->pps_mutex);
1713
bf13e81b 1714 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1715 if (!IS_BROXTON(dev)) {
1716 control &= ~PANEL_UNLOCK_MASK;
1717 control |= PANEL_UNLOCK_REGS;
1718 }
832dd3c1 1719 return control;
bd943159
KP		 1720}
1721
951468f3
VS		 1722/*
1723 * Must be paired with edp_panel_vdd_off().
1724 * Must hold pps_mutex around the whole on/off sequence.
1725 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1726 */
1e0560e0 1727static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1728{
30add22d 1729 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1730 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1731 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1732 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1733 enum intel_display_power_domain power_domain;
5d613501 1734 u32 pp;
453c5420 1735 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1736 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1737
e39b999a
VS		 1738 lockdep_assert_held(&dev_priv->pps_mutex);
1739
97af61f5 1740 if (!is_edp(intel_dp))
adddaaf4 1741 return false;
bd943159 1742
2c623c11 1743 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1744 intel_dp->want_panel_vdd = true;
99ea7127 1745
4be73780 1746 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1747 return need_to_disable;
b0665d57 1748
4e6e1a54
ID		 1749 power_domain = intel_display_port_power_domain(intel_encoder);
1750 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1751
3936fcf4
VS		 1752 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1753 port_name(intel_dig_port->port));
bd943159 1754
4be73780
DV		 1755 if (!edp_have_panel_power(intel_dp))
1756 wait_panel_power_cycle(intel_dp);
99ea7127 1757
453c5420 1758 pp = ironlake_get_pp_control(intel_dp);
5d613501 1759 pp |= EDP_FORCE_VDD;
ebf33b18 1760
bf13e81b
JN		 1761 pp_stat_reg = _pp_stat_reg(intel_dp);
1762 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1763
1764 I915_WRITE(pp_ctrl_reg, pp);
1765 POSTING_READ(pp_ctrl_reg);
1766 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1767 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1768 /*
1769 * If the panel wasn't on, delay before accessing aux channel
1770 */
4be73780 1771 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1772 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1773 port_name(intel_dig_port->port));
f01eca2e 1774 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1775 }
adddaaf4
JN		 1776
1777 return need_to_disable;
1778}
1779
951468f3
VS		 1780/*
1781 * Must be paired with intel_edp_panel_vdd_off() or
1782 * intel_edp_panel_off().
1783 * Nested calls to these functions are not allowed since
1784 * we drop the lock. Caller must use some higher level
1785 * locking to prevent nested calls from other threads.
1786 */
b80d6c78 1787void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1788{
c695b6b6 1789 bool vdd;
adddaaf4 1790
c695b6b6
VS		 1791 if (!is_edp(intel_dp))
1792 return;
1793
773538e8 1794 pps_lock(intel_dp);
c695b6b6 1795 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1796 pps_unlock(intel_dp);
c695b6b6 1797
e2c719b7 1798 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1799 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1800}
1801
4be73780 1802static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1803{
30add22d 1804 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1805 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1806 struct intel_digital_port *intel_dig_port =
1807 dp_to_dig_port(intel_dp);
1808 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1809 enum intel_display_power_domain power_domain;
5d613501 1810 u32 pp;
453c5420 1811 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1812
e39b999a 1813 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1814
15e899a0 1815 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1816
15e899a0 1817 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1818 return;
b0665d57 1819
3936fcf4
VS		 1820 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1821 port_name(intel_dig_port->port));
bd943159 1822
be2c9196
VS		 1823 pp = ironlake_get_pp_control(intel_dp);
1824 pp &= ~EDP_FORCE_VDD;
453c5420 1825
be2c9196
VS		 1826 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1827 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1828
be2c9196
VS		 1829 I915_WRITE(pp_ctrl_reg, pp);
1830 POSTING_READ(pp_ctrl_reg);
90791a5c 1831
be2c9196
VS		 1832 /* Make sure sequencer is idle before allowing subsequent activity */
1833 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1834 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1835
be2c9196
VS		 1836 if ((pp & POWER_TARGET_ON) == 0)
1837 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1838
be2c9196
VS		 1839 power_domain = intel_display_port_power_domain(intel_encoder);
1840 intel_display_power_put(dev_priv, power_domain);
bd943159 1841}
5d613501 1842
4be73780 1843static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1844{
1845 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1846 struct intel_dp, panel_vdd_work);
bd943159 1847
773538e8 1848 pps_lock(intel_dp);
15e899a0
VS		 1849 if (!intel_dp->want_panel_vdd)
1850 edp_panel_vdd_off_sync(intel_dp);
773538e8 1851 pps_unlock(intel_dp);
bd943159
KP		 1852}
1853
aba86890
ID		 1854static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1855{
1856 unsigned long delay;
1857
1858 /*
1859 * Queue the timer to fire a long time from now (relative to the power
1860 * down delay) to keep the panel power up across a sequence of
1861 * operations.
1862 */
1863 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1864 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1865}
1866
951468f3
VS		 1867/*
1868 * Must be paired with edp_panel_vdd_on().
1869 * Must hold pps_mutex around the whole on/off sequence.
1870 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1871 */
4be73780 1872static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1873{
e39b999a
VS		 1874 struct drm_i915_private *dev_priv =
1875 intel_dp_to_dev(intel_dp)->dev_private;
1876
1877 lockdep_assert_held(&dev_priv->pps_mutex);
1878
97af61f5
KP		 1879 if (!is_edp(intel_dp))
1880 return;
5d613501 1881
e2c719b7 1882 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1883 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1884
bd943159
KP		 1885 intel_dp->want_panel_vdd = false;
1886
aba86890 1887 if (sync)
4be73780 1888 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1889 else
1890 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1891}
1892
9f0fb5be 1893static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1894{
30add22d 1895 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1896 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1897 u32 pp;
453c5420 1898 u32 pp_ctrl_reg;
9934c132 1899
9f0fb5be
VS		 1900 lockdep_assert_held(&dev_priv->pps_mutex);
1901
97af61f5 1902 if (!is_edp(intel_dp))
bd943159 1903 return;
99ea7127 1904
3936fcf4
VS		 1905 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1906 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1907
e7a89ace
VS		 1908 if (WARN(edp_have_panel_power(intel_dp),
1909 "eDP port %c panel power already on\n",
1910 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1911 return;
9934c132 1912
4be73780 1913 wait_panel_power_cycle(intel_dp);
37c6c9b0 1914
bf13e81b 1915 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1916 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1917 if (IS_GEN5(dev)) {
1918 /* ILK workaround: disable reset around power sequence */
1919 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1920 I915_WRITE(pp_ctrl_reg, pp);
1921 POSTING_READ(pp_ctrl_reg);
05ce1a49 1922 }
37c6c9b0 1923
1c0ae80a 1924 pp |= POWER_TARGET_ON;
99ea7127
KP		 1925 if (!IS_GEN5(dev))
1926 pp |= PANEL_POWER_RESET;
1927
453c5420
JB		 1928 I915_WRITE(pp_ctrl_reg, pp);
1929 POSTING_READ(pp_ctrl_reg);
9934c132 1930
4be73780 1931 wait_panel_on(intel_dp);
dce56b3c 1932 intel_dp->last_power_on = jiffies;
9934c132 1933
05ce1a49
KP		 1934 if (IS_GEN5(dev)) {
1935 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1936 I915_WRITE(pp_ctrl_reg, pp);
1937 POSTING_READ(pp_ctrl_reg);
05ce1a49 1938 }
9f0fb5be 1939}
e39b999a 1940
9f0fb5be
VS		 1941void intel_edp_panel_on(struct intel_dp *intel_dp)
1942{
1943 if (!is_edp(intel_dp))
1944 return;
1945
1946 pps_lock(intel_dp);
1947 edp_panel_on(intel_dp);
773538e8 1948 pps_unlock(intel_dp);
9934c132
JB		 1949}
1950
9f0fb5be
VS		 1951
1952static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1953{
4e6e1a54
ID		 1954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1955 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1956 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1957 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1958 enum intel_display_power_domain power_domain;
99ea7127 1959 u32 pp;
453c5420 1960 u32 pp_ctrl_reg;
9934c132 1961
9f0fb5be
VS		 1962 lockdep_assert_held(&dev_priv->pps_mutex);
1963
97af61f5
KP		 1964 if (!is_edp(intel_dp))
1965 return;
37c6c9b0 1966
3936fcf4
VS		 1967 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1968 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1969
3936fcf4
VS		 1970 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1971 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1972
453c5420 1973 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1974 /* We need to switch off panel power _and_ force vdd, for otherwise some
1975 * panels get very unhappy and cease to work. */
b3064154
PJ		 1976 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1977 EDP_BLC_ENABLE);
453c5420 1978
bf13e81b 1979 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1980
849e39f5
PZ		 1981 intel_dp->want_panel_vdd = false;
1982
453c5420
JB		 1983 I915_WRITE(pp_ctrl_reg, pp);
1984 POSTING_READ(pp_ctrl_reg);
9934c132 1985
dce56b3c 1986 intel_dp->last_power_cycle = jiffies;
4be73780 1987 wait_panel_off(intel_dp);
849e39f5
PZ		 1988
1989 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1990 power_domain = intel_display_port_power_domain(intel_encoder);
1991 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1992}
e39b999a 1993
9f0fb5be
VS		 1994void intel_edp_panel_off(struct intel_dp *intel_dp)
1995{
1996 if (!is_edp(intel_dp))
1997 return;
e39b999a 1998
9f0fb5be
VS		 1999 pps_lock(intel_dp);
2000 edp_panel_off(intel_dp);
773538e8 2001 pps_unlock(intel_dp);
9934c132
JB		 2002}
2003
1250d107
JN		 2004/* Enable backlight in the panel power control. */
2005static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2006{
da63a9f2
PZ		 2007 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2008 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 u32 pp;
453c5420 2011 u32 pp_ctrl_reg;
32f9d658 2012
01cb9ea6
JB		 2013 /*
2014 * If we enable the backlight right away following a panel power
2015 * on, we may see slight flicker as the panel syncs with the eDP
2016 * link. So delay a bit to make sure the image is solid before
2017 * allowing it to appear.
2018 */
4be73780 2019 wait_backlight_on(intel_dp);
e39b999a 2020
773538e8 2021 pps_lock(intel_dp);
e39b999a 2022
453c5420 2023 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2024 pp |= EDP_BLC_ENABLE;
453c5420 2025
bf13e81b 2026 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2027
2028 I915_WRITE(pp_ctrl_reg, pp);
2029 POSTING_READ(pp_ctrl_reg);
e39b999a 2030
773538e8 2031 pps_unlock(intel_dp);
32f9d658
ZW		 2032}
2033
1250d107
JN		 2034/* Enable backlight PWM and backlight PP control. */
2035void intel_edp_backlight_on(struct intel_dp *intel_dp)
2036{
2037 if (!is_edp(intel_dp))
2038 return;
2039
2040 DRM_DEBUG_KMS("\n");
2041
2042 intel_panel_enable_backlight(intel_dp->attached_connector);
2043 _intel_edp_backlight_on(intel_dp);
2044}
2045
2046/* Disable backlight in the panel power control. */
2047static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2048{
30add22d 2049 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2050 struct drm_i915_private *dev_priv = dev->dev_private;
2051 u32 pp;
453c5420 2052 u32 pp_ctrl_reg;
32f9d658 2053
f01eca2e
KP		 2054 if (!is_edp(intel_dp))
2055 return;
2056
773538e8 2057 pps_lock(intel_dp);
e39b999a 2058
453c5420 2059 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2060 pp &= ~EDP_BLC_ENABLE;
453c5420 2061
bf13e81b 2062 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2063
2064 I915_WRITE(pp_ctrl_reg, pp);
2065 POSTING_READ(pp_ctrl_reg);
f7d2323c 2066
773538e8 2067 pps_unlock(intel_dp);
e39b999a
VS		 2068
2069 intel_dp->last_backlight_off = jiffies;
f7d2323c 2070 edp_wait_backlight_off(intel_dp);
1250d107 2071}
f7d2323c 2072
1250d107
JN		 2073/* Disable backlight PP control and backlight PWM. */
2074void intel_edp_backlight_off(struct intel_dp *intel_dp)
2075{
2076 if (!is_edp(intel_dp))
2077 return;
2078
2079 DRM_DEBUG_KMS("\n");
f7d2323c 2080
1250d107 2081 _intel_edp_backlight_off(intel_dp);
f7d2323c 2082 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2083}
a4fc5ed6 2084
73580fb7
JN		 2085/*
2086 * Hook for controlling the panel power control backlight through the bl_power
2087 * sysfs attribute. Take care to handle multiple calls.
2088 */
2089static void intel_edp_backlight_power(struct intel_connector *connector,
2090 bool enable)
2091{
2092 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2093 bool is_enabled;
2094
773538e8 2095 pps_lock(intel_dp);
e39b999a 2096 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2097 pps_unlock(intel_dp);
73580fb7
JN		 2098
2099 if (is_enabled == enable)
2100 return;
2101
23ba9373
JN		 2102 DRM_DEBUG_KMS("panel power control backlight %s\n",
2103 enable ? "enable" : "disable");
73580fb7
JN		 2104
2105 if (enable)
2106 _intel_edp_backlight_on(intel_dp);
2107 else
2108 _intel_edp_backlight_off(intel_dp);
2109}
2110
2bd2ad64 2111static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2112{
da63a9f2
PZ		 2113 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2114 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2115 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 u32 dpa_ctl;
2118
2bd2ad64
DV		 2119 assert_pipe_disabled(dev_priv,
2120 to_intel_crtc(crtc)->pipe);
2121
d240f20f
JB		 2122 DRM_DEBUG_KMS("\n");
2123 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2124 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2125 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2126
2127 /* We don't adjust intel_dp->DP while tearing down the link, to
2128 * facilitate link retraining (e.g. after hotplug). Hence clear all
2129 * enable bits here to ensure that we don't enable too much. */
2130 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2131 intel_dp->DP |= DP_PLL_ENABLE;
2132 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2133 POSTING_READ(DP_A);
2134 udelay(200);
d240f20f
JB		 2135}
2136
2bd2ad64 2137static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2138{
da63a9f2
PZ		 2139 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2140 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2141 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2142 struct drm_i915_private *dev_priv = dev->dev_private;
2143 u32 dpa_ctl;
2144
2bd2ad64
DV		 2145 assert_pipe_disabled(dev_priv,
2146 to_intel_crtc(crtc)->pipe);
2147
d240f20f 2148 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2149 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2150 "dp pll off, should be on\n");
2151 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2152
2153 /* We can't rely on the value tracked for the DP register in
2154 * intel_dp->DP because link_down must not change that (otherwise link
2155 * re-training will fail. */
298b0b39 2156 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2157 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2158 POSTING_READ(DP_A);
d240f20f
JB		 2159 udelay(200);
2160}
2161
c7ad3810 2162/* If the sink supports it, try to set the power state appropriately */
c19b0669 2163void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2164{
2165 int ret, i;
2166
2167 /* Should have a valid DPCD by this point */
2168 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2169 return;
2170
2171 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2172 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2173 DP_SET_POWER_D3);
c7ad3810
JB		 2174 } else {
2175 /*
2176 * When turning on, we need to retry for 1ms to give the sink
2177 * time to wake up.
2178 */
2179 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2180 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2181 DP_SET_POWER_D0);
c7ad3810
JB		 2182 if (ret == 1)
2183 break;
2184 msleep(1);
2185 }
2186 }
f9cac721
JN		 2187
2188 if (ret != 1)
2189 DRM_DEBUG_KMS("failed to %s sink power state\n",
2190 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2191}
2192
19d8fe15
DV		 2193static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2194 enum pipe *pipe)
d240f20f 2195{
19d8fe15 2196 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2197 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2198 struct drm_device *dev = encoder->base.dev;
2199 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2200 enum intel_display_power_domain power_domain;
2201 u32 tmp;
2202
2203 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2204 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2205 return false;
2206
2207 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2208
2209 if (!(tmp & DP_PORT_EN))
2210 return false;
2211
39e5fa88 2212 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2213 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2214 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2215 enum pipe p;
19d8fe15 2216
adc289d7
VS		 2217 for_each_pipe(dev_priv, p) {
2218 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2219 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2220 *pipe = p;
19d8fe15
DV		 2221 return true;
2222 }
2223 }
19d8fe15 2224
4a0833ec
DV		 2225 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2226 intel_dp->output_reg);
39e5fa88
VS		 2227 } else if (IS_CHERRYVIEW(dev)) {
2228 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2229 } else {
2230 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2231 }
d240f20f 2232
19d8fe15
DV		 2233 return true;
2234}
d240f20f 2235
045ac3b5 2236static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2237 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2238{
2239 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2240 u32 tmp, flags = 0;
63000ef6
XZ		 2241 struct drm_device *dev = encoder->base.dev;
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243 enum port port = dp_to_dig_port(intel_dp)->port;
2244 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2245 int dotclock;
045ac3b5 2246
9ed109a7 2247 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2248
2249 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2250
39e5fa88
VS		 2251 if (HAS_PCH_CPT(dev) && port != PORT_A) {
2252 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2253 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2254 flags |= DRM_MODE_FLAG_PHSYNC;
2255 else
2256 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2257
39e5fa88 2258 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2259 flags |= DRM_MODE_FLAG_PVSYNC;
2260 else
2261 flags |= DRM_MODE_FLAG_NVSYNC;
2262 } else {
39e5fa88 2263 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2264 flags |= DRM_MODE_FLAG_PHSYNC;
2265 else
2266 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2267
39e5fa88 2268 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2269 flags |= DRM_MODE_FLAG_PVSYNC;
2270 else
2271 flags |= DRM_MODE_FLAG_NVSYNC;
2272 }
045ac3b5 2273
2d112de7 2274 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2275
8c875fca
VS		 2276 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2277 tmp & DP_COLOR_RANGE_16_235)
2278 pipe_config->limited_color_range = true;
2279
eb14cb74
VS		 2280 pipe_config->has_dp_encoder = true;
2281
2282 intel_dp_get_m_n(crtc, pipe_config);
2283
18442d08 2284 if (port == PORT_A) {
f1f644dc
JB		 2285 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2286 pipe_config->port_clock = 162000;
2287 else
2288 pipe_config->port_clock = 270000;
2289 }
18442d08
VS		 2290
2291 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2292 &pipe_config->dp_m_n);
2293
2294 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2295 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2296
2d112de7 2297 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2298
c6cd2ee2
JN		 2299 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2300 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2301 /*
2302 * This is a big fat ugly hack.
2303 *
2304 * Some machines in UEFI boot mode provide us a VBT that has 18
2305 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2306 * unknown we fail to light up. Yet the same BIOS boots up with
2307 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2308 * max, not what it tells us to use.
2309 *
2310 * Note: This will still be broken if the eDP panel is not lit
2311 * up by the BIOS, and thus we can't get the mode at module
2312 * load.
2313 */
2314 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2315 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2316 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2317 }
045ac3b5
JB		 2318}
2319
e8cb4558 2320static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2321{
e8cb4558 2322 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2323 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2324 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2325
6e3c9717 2326 if (crtc->config->has_audio)
495a5bb8 2327 intel_audio_codec_disable(encoder);
6cb49835 2328
b32c6f48
RV		 2329 if (HAS_PSR(dev) && !HAS_DDI(dev))
2330 intel_psr_disable(intel_dp);
2331
6cb49835
DV		 2332 /* Make sure the panel is off before trying to change the mode. But also
2333 * ensure that we have vdd while we switch off the panel. */
24f3e092 2334 intel_edp_panel_vdd_on(intel_dp);
4be73780 2335 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2336 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2337 intel_edp_panel_off(intel_dp);
3739850b 2338
08aff3fe
VS		 2339 /* disable the port before the pipe on g4x */
2340 if (INTEL_INFO(dev)->gen < 5)
3739850b 2341 intel_dp_link_down(intel_dp);
d240f20f
JB		 2342}
2343
08aff3fe 2344static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2345{
2bd2ad64 2346 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2347 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2348
49277c31 2349 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2350 if (port == PORT_A)
2351 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2352}
2353
2354static void vlv_post_disable_dp(struct intel_encoder *encoder)
2355{
2356 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2357
2358 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2359}
2360
580d3811
VS		 2361static void chv_post_disable_dp(struct intel_encoder *encoder)
2362{
2363 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2364 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2365 struct drm_device *dev = encoder->base.dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc =
2368 to_intel_crtc(encoder->base.crtc);
2369 enum dpio_channel ch = vlv_dport_to_channel(dport);
2370 enum pipe pipe = intel_crtc->pipe;
2371 u32 val;
2372
2373 intel_dp_link_down(intel_dp);
2374
a580516d 2375 mutex_lock(&dev_priv->sb_lock);
580d3811
VS		 2376
2377 /* Propagate soft reset to data lane reset */
97fd4d5c 2378 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2379 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2380 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2381
97fd4d5c
VS		 2382 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2383 val |= CHV_PCS_REQ_SOFTRESET_EN;
2384 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2385
2386 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2387 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2388 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2389
2390 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2391 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2392 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811 2393
a580516d 2394 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2395}
2396
7b13b58a
VS		 2397static void
2398_intel_dp_set_link_train(struct intel_dp *intel_dp,
2399 uint32_t *DP,
2400 uint8_t dp_train_pat)
2401{
2402 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2403 struct drm_device *dev = intel_dig_port->base.base.dev;
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2405 enum port port = intel_dig_port->port;
2406
2407 if (HAS_DDI(dev)) {
2408 uint32_t temp = I915_READ(DP_TP_CTL(port));
2409
2410 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2411 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2412 else
2413 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2414
2415 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2416 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2417 case DP_TRAINING_PATTERN_DISABLE:
2418 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2419
2420 break;
2421 case DP_TRAINING_PATTERN_1:
2422 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2423 break;
2424 case DP_TRAINING_PATTERN_2:
2425 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2426 break;
2427 case DP_TRAINING_PATTERN_3:
2428 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2429 break;
2430 }
2431 I915_WRITE(DP_TP_CTL(port), temp);
2432
39e5fa88
VS		 2433 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2434 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2435 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2436
2437 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2438 case DP_TRAINING_PATTERN_DISABLE:
2439 *DP |= DP_LINK_TRAIN_OFF_CPT;
2440 break;
2441 case DP_TRAINING_PATTERN_1:
2442 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2443 break;
2444 case DP_TRAINING_PATTERN_2:
2445 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2446 break;
2447 case DP_TRAINING_PATTERN_3:
2448 DRM_ERROR("DP training pattern 3 not supported\n");
2449 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2450 break;
2451 }
2452
2453 } else {
2454 if (IS_CHERRYVIEW(dev))
2455 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2456 else
2457 *DP &= ~DP_LINK_TRAIN_MASK;
2458
2459 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2460 case DP_TRAINING_PATTERN_DISABLE:
2461 *DP |= DP_LINK_TRAIN_OFF;
2462 break;
2463 case DP_TRAINING_PATTERN_1:
2464 *DP |= DP_LINK_TRAIN_PAT_1;
2465 break;
2466 case DP_TRAINING_PATTERN_2:
2467 *DP |= DP_LINK_TRAIN_PAT_2;
2468 break;
2469 case DP_TRAINING_PATTERN_3:
2470 if (IS_CHERRYVIEW(dev)) {
2471 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2472 } else {
2473 DRM_ERROR("DP training pattern 3 not supported\n");
2474 *DP |= DP_LINK_TRAIN_PAT_2;
2475 }
2476 break;
2477 }
2478 }
2479}
2480
2481static void intel_dp_enable_port(struct intel_dp *intel_dp)
2482{
2483 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485
7b13b58a
VS		 2486 /* enable with pattern 1 (as per spec) */
2487 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2488 DP_TRAINING_PATTERN_1);
2489
2490 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2491 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2492
2493 /*
2494 * Magic for VLV/CHV. We _must_ first set up the register
2495 * without actually enabling the port, and then do another
2496 * write to enable the port. Otherwise link training will
2497 * fail when the power sequencer is freshly used for this port.
2498 */
2499 intel_dp->DP |= DP_PORT_EN;
2500
2501 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2502 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2503}
2504
e8cb4558 2505static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2506{
e8cb4558
DV		 2507 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2508 struct drm_device *dev = encoder->base.dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2510 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2511 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
9b6de0a1 2512 unsigned int lane_mask = 0x0;
5d613501 2513
0c33d8d7
DV		 2514 if (WARN_ON(dp_reg & DP_PORT_EN))
2515 return;
5d613501 2516
093e3f13
VS		 2517 pps_lock(intel_dp);
2518
2519 if (IS_VALLEYVIEW(dev))
2520 vlv_init_panel_power_sequencer(intel_dp);
2521
7b13b58a 2522 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2523
2524 edp_panel_vdd_on(intel_dp);
2525 edp_panel_on(intel_dp);
2526 edp_panel_vdd_off(intel_dp, true);
2527
2528 pps_unlock(intel_dp);
2529
61234fa5 2530 if (IS_VALLEYVIEW(dev))
9b6de0a1
VS		 2531 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2532 lane_mask);
61234fa5 2533
f01eca2e 2534 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2535 intel_dp_start_link_train(intel_dp);
33a34e4e 2536 intel_dp_complete_link_train(intel_dp);
3ab9c637 2537 intel_dp_stop_link_train(intel_dp);
c1dec79a 2538
6e3c9717 2539 if (crtc->config->has_audio) {
c1dec79a
JN		 2540 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2541 pipe_name(crtc->pipe));
2542 intel_audio_codec_enable(encoder);
2543 }
ab1f90f9 2544}
89b667f8 2545
ecff4f3b
JN		 2546static void g4x_enable_dp(struct intel_encoder *encoder)
2547{
828f5c6e
JN		 2548 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2549
ecff4f3b 2550 intel_enable_dp(encoder);
4be73780 2551 intel_edp_backlight_on(intel_dp);
ab1f90f9 2552}
89b667f8 2553
ab1f90f9
JN		 2554static void vlv_enable_dp(struct intel_encoder *encoder)
2555{
828f5c6e
JN		 2556 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2557
4be73780 2558 intel_edp_backlight_on(intel_dp);
b32c6f48 2559 intel_psr_enable(intel_dp);
d240f20f
JB		 2560}
2561
ecff4f3b 2562static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2563{
2564 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2565 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2566
8ac33ed3
DV		 2567 intel_dp_prepare(encoder);
2568
d41f1efb
DV		 2569 /* Only ilk+ has port A */
2570 if (dport->port == PORT_A) {
2571 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2572 ironlake_edp_pll_on(intel_dp);
d41f1efb 2573 }
ab1f90f9
JN		 2574}
2575
83b84597
VS		 2576static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2577{
2578 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2579 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2580 enum pipe pipe = intel_dp->pps_pipe;
2581 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2582
2583 edp_panel_vdd_off_sync(intel_dp);
2584
2585 /*
2586 * VLV seems to get confused when multiple power seqeuencers
2587 * have the same port selected (even if only one has power/vdd
2588 * enabled). The failure manifests as vlv_wait_port_ready() failing
2589 * CHV on the other hand doesn't seem to mind having the same port
2590 * selected in multiple power seqeuencers, but let's clear the
2591 * port select always when logically disconnecting a power sequencer
2592 * from a port.
2593 */
2594 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2595 pipe_name(pipe), port_name(intel_dig_port->port));
2596 I915_WRITE(pp_on_reg, 0);
2597 POSTING_READ(pp_on_reg);
2598
2599 intel_dp->pps_pipe = INVALID_PIPE;
2600}
2601
a4a5d2f8
VS		 2602static void vlv_steal_power_sequencer(struct drm_device *dev,
2603 enum pipe pipe)
2604{
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606 struct intel_encoder *encoder;
2607
2608 lockdep_assert_held(&dev_priv->pps_mutex);
2609
ac3c12e4
VS		 2610 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2611 return;
2612
a4a5d2f8
VS		 2613 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2614 base.head) {
2615 struct intel_dp *intel_dp;
773538e8 2616 enum port port;
a4a5d2f8
VS		 2617
2618 if (encoder->type != INTEL_OUTPUT_EDP)
2619 continue;
2620
2621 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2622 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2623
2624 if (intel_dp->pps_pipe != pipe)
2625 continue;
2626
2627 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2628 pipe_name(pipe), port_name(port));
a4a5d2f8 2629
034e43c6
VS		 2630 WARN(encoder->connectors_active,
2631 "stealing pipe %c power sequencer from active eDP port %c\n",
2632 pipe_name(pipe), port_name(port));
a4a5d2f8 2633
a4a5d2f8 2634 /* make sure vdd is off before we steal it */
83b84597 2635 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2636 }
2637}
2638
2639static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2640{
2641 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2642 struct intel_encoder *encoder = &intel_dig_port->base;
2643 struct drm_device *dev = encoder->base.dev;
2644 struct drm_i915_private *dev_priv = dev->dev_private;
2645 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2646
2647 lockdep_assert_held(&dev_priv->pps_mutex);
2648
093e3f13
VS		 2649 if (!is_edp(intel_dp))
2650 return;
2651
a4a5d2f8
VS		 2652 if (intel_dp->pps_pipe == crtc->pipe)
2653 return;
2654
2655 /*
2656 * If another power sequencer was being used on this
2657 * port previously make sure to turn off vdd there while
2658 * we still have control of it.
2659 */
2660 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2661 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2662
2663 /*
2664 * We may be stealing the power
2665 * sequencer from another port.
2666 */
2667 vlv_steal_power_sequencer(dev, crtc->pipe);
2668
2669 /* now it's all ours */
2670 intel_dp->pps_pipe = crtc->pipe;
2671
2672 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2673 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2674
2675 /* init power sequencer on this pipe and port */
36b5f425
VS		 2676 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2677 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2678}
2679
ab1f90f9 2680static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2681{
2bd2ad64 2682 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2683 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2684 struct drm_device *dev = encoder->base.dev;
89b667f8 2685 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2686 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2687 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2688 int pipe = intel_crtc->pipe;
2689 u32 val;
a4fc5ed6 2690
a580516d 2691 mutex_lock(&dev_priv->sb_lock);
89b667f8 2692
ab3c759a 2693 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2694 val = 0;
2695 if (pipe)
2696 val |= (1<<21);
2697 else
2698 val &= ~(1<<21);
2699 val |= 0x001000c4;
ab3c759a
CML		 2700 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2701 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2702 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2703
a580516d 2704 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2705
2706 intel_enable_dp(encoder);
89b667f8
JB		 2707}
2708
ecff4f3b 2709static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2710{
2711 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2712 struct drm_device *dev = encoder->base.dev;
2713 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2714 struct intel_crtc *intel_crtc =
2715 to_intel_crtc(encoder->base.crtc);
e4607fcf 2716 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2717 int pipe = intel_crtc->pipe;
89b667f8 2718
8ac33ed3
DV		 2719 intel_dp_prepare(encoder);
2720
89b667f8 2721 /* Program Tx lane resets to default */
a580516d 2722 mutex_lock(&dev_priv->sb_lock);
ab3c759a 2723 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2724 DPIO_PCS_TX_LANE2_RESET |
2725 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2726 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2727 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2728 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2729 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2730 DPIO_PCS_CLK_SOFT_RESET);
2731
2732 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2733 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2734 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2735 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
a580516d 2736 mutex_unlock(&dev_priv->sb_lock);
a4fc5ed6
KP		 2737}
2738
e4a1d846
CML		 2739static void chv_pre_enable_dp(struct intel_encoder *encoder)
2740{
2741 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2742 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2743 struct drm_device *dev = encoder->base.dev;
2744 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2745 struct intel_crtc *intel_crtc =
2746 to_intel_crtc(encoder->base.crtc);
2747 enum dpio_channel ch = vlv_dport_to_channel(dport);
2748 int pipe = intel_crtc->pipe;
2e523e98 2749 int data, i, stagger;
949c1d43 2750 u32 val;
e4a1d846 2751
a580516d 2752 mutex_lock(&dev_priv->sb_lock);
949c1d43 2753
570e2a74
VS		 2754 /* allow hardware to manage TX FIFO reset source */
2755 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2756 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2757 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2758
2759 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2760 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2761 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2762
949c1d43 2763 /* Deassert soft data lane reset*/
97fd4d5c 2764 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2765 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2766 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2767
2768 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2769 val |= CHV_PCS_REQ_SOFTRESET_EN;
2770 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2771
2772 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2773 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2774 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2775
97fd4d5c 2776 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2777 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2778 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2779
2780 /* Program Tx lane latency optimal setting*/
e4a1d846 2781 for (i = 0; i < 4; i++) {
e4a1d846
CML		 2782 /* Set the upar bit */
2783 data = (i == 1) ? 0x0 : 0x1;
2784 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2785 data << DPIO_UPAR_SHIFT);
2786 }
2787
2788 /* Data lane stagger programming */
2e523e98
VS		 2789 if (intel_crtc->config->port_clock > 270000)
2790 stagger = 0x18;
2791 else if (intel_crtc->config->port_clock > 135000)
2792 stagger = 0xd;
2793 else if (intel_crtc->config->port_clock > 67500)
2794 stagger = 0x7;
2795 else if (intel_crtc->config->port_clock > 33750)
2796 stagger = 0x4;
2797 else
2798 stagger = 0x2;
2799
2800 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2801 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2802 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2803
2804 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2805 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2806 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2807
2808 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2809 DPIO_LANESTAGGER_STRAP(stagger) |
2810 DPIO_LANESTAGGER_STRAP_OVRD |
2811 DPIO_TX1_STAGGER_MASK(0x1f) |
2812 DPIO_TX1_STAGGER_MULT(6) |
2813 DPIO_TX2_STAGGER_MULT(0));
2814
2815 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2816 DPIO_LANESTAGGER_STRAP(stagger) |
2817 DPIO_LANESTAGGER_STRAP_OVRD |
2818 DPIO_TX1_STAGGER_MASK(0x1f) |
2819 DPIO_TX1_STAGGER_MULT(7) |
2820 DPIO_TX2_STAGGER_MULT(5));
e4a1d846 2821
a580516d 2822 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 2823
e4a1d846 2824 intel_enable_dp(encoder);
e4a1d846
CML		 2825}
2826
9197c88b
VS		 2827static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2828{
2829 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2830 struct drm_device *dev = encoder->base.dev;
2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832 struct intel_crtc *intel_crtc =
2833 to_intel_crtc(encoder->base.crtc);
2834 enum dpio_channel ch = vlv_dport_to_channel(dport);
2835 enum pipe pipe = intel_crtc->pipe;
2836 u32 val;
2837
625695f8
VS		 2838 intel_dp_prepare(encoder);
2839
a580516d 2840 mutex_lock(&dev_priv->sb_lock);
9197c88b 2841
b9e5ac3c
VS		 2842 /* program left/right clock distribution */
2843 if (pipe != PIPE_B) {
2844 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2845 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2846 if (ch == DPIO_CH0)
2847 val |= CHV_BUFLEFTENA1_FORCE;
2848 if (ch == DPIO_CH1)
2849 val |= CHV_BUFRIGHTENA1_FORCE;
2850 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2851 } else {
2852 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2853 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2854 if (ch == DPIO_CH0)
2855 val |= CHV_BUFLEFTENA2_FORCE;
2856 if (ch == DPIO_CH1)
2857 val |= CHV_BUFRIGHTENA2_FORCE;
2858 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2859 }
2860
9197c88b
VS		 2861 /* program clock channel usage */
2862 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2863 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2864 if (pipe != PIPE_B)
2865 val &= ~CHV_PCS_USEDCLKCHANNEL;
2866 else
2867 val |= CHV_PCS_USEDCLKCHANNEL;
2868 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2869
2870 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2871 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2872 if (pipe != PIPE_B)
2873 val &= ~CHV_PCS_USEDCLKCHANNEL;
2874 else
2875 val |= CHV_PCS_USEDCLKCHANNEL;
2876 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2877
2878 /*
2879 * This a a bit weird since generally CL
2880 * matches the pipe, but here we need to
2881 * pick the CL based on the port.
2882 */
2883 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2884 if (pipe != PIPE_B)
2885 val &= ~CHV_CMN_USEDCLKCHANNEL;
2886 else
2887 val |= CHV_CMN_USEDCLKCHANNEL;
2888 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2889
a580516d 2890 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 2891}
2892
a4fc5ed6 2893/*
df0c237d
JB		 2894 * Native read with retry for link status and receiver capability reads for
2895 * cases where the sink may still be asleep.
9d1a1031
JN		 2896 *
2897 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2898 * supposed to retry 3 times per the spec.
a4fc5ed6 2899 */
9d1a1031
JN		 2900static ssize_t
2901intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2902 void *buffer, size_t size)
a4fc5ed6 2903{
9d1a1031
JN		 2904 ssize_t ret;
2905 int i;
61da5fab 2906
f6a19066
VS		 2907 /*
2908 * Sometime we just get the same incorrect byte repeated
2909 * over the entire buffer. Doing just one throw away read
2910 * initially seems to "solve" it.
2911 */
2912 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2913
61da5fab 2914 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2915 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2916 if (ret == size)
2917 return ret;
61da5fab
JB		 2918 msleep(1);
2919 }
a4fc5ed6 2920
9d1a1031 2921 return ret;
a4fc5ed6
KP		 2922}
2923
2924/*
2925 * Fetch AUX CH registers 0x202 - 0x207 which contain
2926 * link status information
2927 */
2928static bool
93f62dad 2929intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2930{
9d1a1031
JN		 2931 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2932 DP_LANE0_1_STATUS,
2933 link_status,
2934 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2935}
2936
1100244e 2937/* These are source-specific values. */
a4fc5ed6 2938static uint8_t
1a2eb460 2939intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2940{
30add22d 2941 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2942 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2943 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2944
9314726b
VK		 2945 if (IS_BROXTON(dev))
2946 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2947 else if (INTEL_INFO(dev)->gen >= 9) {
9e458034 2948 if (dev_priv->edp_low_vswing && port == PORT_A)
7ad14a29 2949 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2950 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2951 } else if (IS_VALLEYVIEW(dev))
bd60018a 2952 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2953 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2954 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2955 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2956 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2957 else
bd60018a 2958 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2959}
2960
2961static uint8_t
2962intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2963{
30add22d 2964 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2965 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2966
5a9d1f1a
DL		 2967 if (INTEL_INFO(dev)->gen >= 9) {
2968 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2970 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2972 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2974 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2975 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2976 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2977 default:
2978 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2979 }
2980 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2981 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2983 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2987 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2988 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2989 default:
bd60018a 2990 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2991 }
e2fa6fba
P		 2992 } else if (IS_VALLEYVIEW(dev)) {
2993 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2994 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2995 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2996 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2997 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2998 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2999 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3000 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3001 default:
bd60018a 3002 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3003 }
bc7d38a4 3004 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3005 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3010 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3011 default:
bd60018a 3012 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3013 }
3014 } else {
3015 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3017 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3019 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3023 default:
bd60018a 3024 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3025 }
a4fc5ed6
KP		 3026 }
3027}
3028
5829975c 3029static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3030{
3031 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3032 struct drm_i915_private *dev_priv = dev->dev_private;
3033 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3034 struct intel_crtc *intel_crtc =
3035 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3036 unsigned long demph_reg_value, preemph_reg_value,
3037 uniqtranscale_reg_value;
3038 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3039 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3040 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3041
3042 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3043 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3044 preemph_reg_value = 0x0004000;
3045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3047 demph_reg_value = 0x2B405555;
3048 uniqtranscale_reg_value = 0x552AB83A;
3049 break;
bd60018a 3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3051 demph_reg_value = 0x2B404040;
3052 uniqtranscale_reg_value = 0x5548B83A;
3053 break;
bd60018a 3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3055 demph_reg_value = 0x2B245555;
3056 uniqtranscale_reg_value = 0x5560B83A;
3057 break;
bd60018a 3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3059 demph_reg_value = 0x2B405555;
3060 uniqtranscale_reg_value = 0x5598DA3A;
3061 break;
3062 default:
3063 return 0;
3064 }
3065 break;
bd60018a 3066 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3067 preemph_reg_value = 0x0002000;
3068 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3070 demph_reg_value = 0x2B404040;
3071 uniqtranscale_reg_value = 0x5552B83A;
3072 break;
bd60018a 3073 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3074 demph_reg_value = 0x2B404848;
3075 uniqtranscale_reg_value = 0x5580B83A;
3076 break;
bd60018a 3077 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3078 demph_reg_value = 0x2B404040;
3079 uniqtranscale_reg_value = 0x55ADDA3A;
3080 break;
3081 default:
3082 return 0;
3083 }
3084 break;
bd60018a 3085 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3086 preemph_reg_value = 0x0000000;
3087 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3089 demph_reg_value = 0x2B305555;
3090 uniqtranscale_reg_value = 0x5570B83A;
3091 break;
bd60018a 3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3093 demph_reg_value = 0x2B2B4040;
3094 uniqtranscale_reg_value = 0x55ADDA3A;
3095 break;
3096 default:
3097 return 0;
3098 }
3099 break;
bd60018a 3100 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3101 preemph_reg_value = 0x0006000;
3102 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3103 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3104 demph_reg_value = 0x1B405555;
3105 uniqtranscale_reg_value = 0x55ADDA3A;
3106 break;
3107 default:
3108 return 0;
3109 }
3110 break;
3111 default:
3112 return 0;
3113 }
3114
a580516d 3115 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 3116 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3117 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3118 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3119 uniqtranscale_reg_value);
ab3c759a
CML		 3120 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3121 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3122 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3123 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
a580516d 3124 mutex_unlock(&dev_priv->sb_lock);
e2fa6fba
P		 3125
3126 return 0;
3127}
3128
5829975c 3129static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3130{
3131 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3134 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3135 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3136 uint8_t train_set = intel_dp->train_set[0];
3137 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3138 enum pipe pipe = intel_crtc->pipe;
3139 int i;
e4a1d846
CML		 3140
3141 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3142 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3145 deemph_reg_value = 128;
3146 margin_reg_value = 52;
3147 break;
bd60018a 3148 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3149 deemph_reg_value = 128;
3150 margin_reg_value = 77;
3151 break;
bd60018a 3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3153 deemph_reg_value = 128;
3154 margin_reg_value = 102;
3155 break;
bd60018a 3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3157 deemph_reg_value = 128;
3158 margin_reg_value = 154;
3159 /* FIXME extra to set for 1200 */
3160 break;
3161 default:
3162 return 0;
3163 }
3164 break;
bd60018a 3165 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3166 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3168 deemph_reg_value = 85;
3169 margin_reg_value = 78;
3170 break;
bd60018a 3171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3172 deemph_reg_value = 85;
3173 margin_reg_value = 116;
3174 break;
bd60018a 3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3176 deemph_reg_value = 85;
3177 margin_reg_value = 154;
3178 break;
3179 default:
3180 return 0;
3181 }
3182 break;
bd60018a 3183 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3184 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3186 deemph_reg_value = 64;
3187 margin_reg_value = 104;
3188 break;
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3190 deemph_reg_value = 64;
3191 margin_reg_value = 154;
3192 break;
3193 default:
3194 return 0;
3195 }
3196 break;
bd60018a 3197 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3198 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3200 deemph_reg_value = 43;
3201 margin_reg_value = 154;
3202 break;
3203 default:
3204 return 0;
3205 }
3206 break;
3207 default:
3208 return 0;
3209 }
3210
a580516d 3211 mutex_lock(&dev_priv->sb_lock);
e4a1d846
CML		 3212
3213 /* Clear calc init */
1966e59e
VS		 3214 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3215 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3216 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3217 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3218 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3219
3220 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3221 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3222 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3223 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3224 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3225
a02ef3c7
VS		 3226 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3227 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3228 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3229 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3230
3231 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3232 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3233 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3234 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3235
e4a1d846 3236 /* Program swing deemph */
f72df8db
VS		 3237 for (i = 0; i < 4; i++) {
3238 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3239 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3240 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3241 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3242 }
e4a1d846
CML		 3243
3244 /* Program swing margin */
f72df8db
VS		 3245 for (i = 0; i < 4; i++) {
3246 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3247 val &= ~DPIO_SWING_MARGIN000_MASK;
3248 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3249 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3250 }
e4a1d846
CML		 3251
3252 /* Disable unique transition scale */
f72df8db
VS		 3253 for (i = 0; i < 4; i++) {
3254 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3255 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3256 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3257 }
e4a1d846
CML		 3258
3259 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3260 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3261 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3262 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3263
3264 /*
3265 * The document said it needs to set bit 27 for ch0 and bit 26
3266 * for ch1. Might be a typo in the doc.
3267 * For now, for this unique transition scale selection, set bit
3268 * 27 for ch0 and ch1.
3269 */
f72df8db
VS		 3270 for (i = 0; i < 4; i++) {
3271 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3272 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3273 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3274 }
e4a1d846 3275
f72df8db
VS		 3276 for (i = 0; i < 4; i++) {
3277 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3278 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3279 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3280 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3281 }
e4a1d846
CML		 3282 }
3283
3284 /* Start swing calculation */
1966e59e
VS		 3285 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3286 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3287 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3288
3289 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3290 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3291 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3292
3293 /* LRC Bypass */
3294 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3295 val |= DPIO_LRC_BYPASS;
3296 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3297
a580516d 3298 mutex_unlock(&dev_priv->sb_lock);
e4a1d846
CML		 3299
3300 return 0;
3301}
3302
a4fc5ed6 3303static void
0301b3ac
JN		 3304intel_get_adjust_train(struct intel_dp *intel_dp,
3305 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3306{
3307 uint8_t v = 0;
3308 uint8_t p = 0;
3309 int lane;
1a2eb460
KP		 3310 uint8_t voltage_max;
3311 uint8_t preemph_max;
a4fc5ed6 3312
33a34e4e 3313 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3314 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3315 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3316
3317 if (this_v > v)
3318 v = this_v;
3319 if (this_p > p)
3320 p = this_p;
3321 }
3322
1a2eb460 3323 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3324 if (v >= voltage_max)
3325 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3326
1a2eb460
KP		 3327 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3328 if (p >= preemph_max)
3329 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3330
3331 for (lane = 0; lane < 4; lane++)
33a34e4e 3332 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3333}
3334
3335static uint32_t
5829975c 3336gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3337{
3cf2efb1 3338 uint32_t signal_levels = 0;
a4fc5ed6 3339
3cf2efb1 3340 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3342 default:
3343 signal_levels |= DP_VOLTAGE_0_4;
3344 break;
bd60018a 3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3346 signal_levels |= DP_VOLTAGE_0_6;
3347 break;
bd60018a 3348 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3349 signal_levels |= DP_VOLTAGE_0_8;
3350 break;
bd60018a 3351 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3352 signal_levels |= DP_VOLTAGE_1_2;
3353 break;
3354 }
3cf2efb1 3355 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3356 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3357 default:
3358 signal_levels |= DP_PRE_EMPHASIS_0;
3359 break;
bd60018a 3360 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3361 signal_levels |= DP_PRE_EMPHASIS_3_5;
3362 break;
bd60018a 3363 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3364 signal_levels |= DP_PRE_EMPHASIS_6;
3365 break;
bd60018a 3366 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3367 signal_levels |= DP_PRE_EMPHASIS_9_5;
3368 break;
3369 }
3370 return signal_levels;
3371}
3372
e3421a18
ZW		 3373/* Gen6's DP voltage swing and pre-emphasis control */
3374static uint32_t
5829975c 3375gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3376{
3c5a62b5
YL		 3377 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3378 DP_TRAIN_PRE_EMPHASIS_MASK);
3379 switch (signal_levels) {
bd60018a
SJ		 3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3381 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3382 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3384 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3387 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3389 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3390 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3391 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3392 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3393 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3394 default:
3c5a62b5
YL		 3395 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3396 "0x%x\n", signal_levels);
3397 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3398 }
3399}
3400
1a2eb460
KP		 3401/* Gen7's DP voltage swing and pre-emphasis control */
3402static uint32_t
5829975c 3403gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3404{
3405 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3406 DP_TRAIN_PRE_EMPHASIS_MASK);
3407 switch (signal_levels) {
bd60018a 3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3409 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3411 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3412 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3413 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3414
bd60018a 3415 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3416 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3417 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3418 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3419
bd60018a 3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3421 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3423 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3424
3425 default:
3426 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3427 "0x%x\n", signal_levels);
3428 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3429 }
3430}
3431
f0a3424e
PZ		 3432/* Properly updates "DP" with the correct signal levels. */
3433static void
3434intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3435{
3436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3437 enum port port = intel_dig_port->port;
f0a3424e 3438 struct drm_device *dev = intel_dig_port->base.base.dev;
f8896f5d 3439 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3440 uint8_t train_set = intel_dp->train_set[0];
3441
f8896f5d
DW		 3442 if (HAS_DDI(dev)) {
3443 signal_levels = ddi_signal_levels(intel_dp);
3444
3445 if (IS_BROXTON(dev))
3446 signal_levels = 0;
3447 else
3448 mask = DDI_BUF_EMP_MASK;
e4a1d846 3449 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3450 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3451 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3452 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3453 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3454 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3455 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3456 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3457 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3458 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3459 } else {
5829975c 3460 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3461 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3462 }
3463
96fb9f9b
VK		 3464 if (mask)
3465 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3466
3467 DRM_DEBUG_KMS("Using vswing level %d\n",
3468 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3469 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3470 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3471 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e
PZ		 3472
3473 *DP = (*DP & ~mask) | signal_levels;
3474}
3475
a4fc5ed6 3476static bool
ea5b213a 3477intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3478 uint32_t *DP,
58e10eb9 3479 uint8_t dp_train_pat)
a4fc5ed6 3480{
174edf1f
PZ		 3481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3482 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3483 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3484 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3485 int ret, len;
a4fc5ed6 3486
7b13b58a 3487 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3488
70aff66c 3489 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3490 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3491
2cdfe6c8
JN		 3492 buf[0] = dp_train_pat;
3493 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3494 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3495 /* don't write DP_TRAINING_LANEx_SET on disable */
3496 len = 1;
3497 } else {
3498 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3499 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3500 len = intel_dp->lane_count + 1;
47ea7542 3501 }
a4fc5ed6 3502
9d1a1031
JN		 3503 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3504 buf, len);
2cdfe6c8
JN		 3505
3506 return ret == len;
a4fc5ed6
KP		 3507}
3508
70aff66c
JN		 3509static bool
3510intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3511 uint8_t dp_train_pat)
3512{
4e96c977
MK		 3513 if (!intel_dp->train_set_valid)
3514 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3515 intel_dp_set_signal_levels(intel_dp, DP);
3516 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3517}
3518
3519static bool
3520intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3521 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3522{
3523 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3524 struct drm_device *dev = intel_dig_port->base.base.dev;
3525 struct drm_i915_private *dev_priv = dev->dev_private;
3526 int ret;
3527
3528 intel_get_adjust_train(intel_dp, link_status);
3529 intel_dp_set_signal_levels(intel_dp, DP);
3530
3531 I915_WRITE(intel_dp->output_reg, *DP);
3532 POSTING_READ(intel_dp->output_reg);
3533
9d1a1031
JN		 3534 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3535 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3536
3537 return ret == intel_dp->lane_count;
3538}
3539
3ab9c637
ID		 3540static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3541{
3542 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3543 struct drm_device *dev = intel_dig_port->base.base.dev;
3544 struct drm_i915_private *dev_priv = dev->dev_private;
3545 enum port port = intel_dig_port->port;
3546 uint32_t val;
3547
3548 if (!HAS_DDI(dev))
3549 return;
3550
3551 val = I915_READ(DP_TP_CTL(port));
3552 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3553 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3554 I915_WRITE(DP_TP_CTL(port), val);
3555
3556 /*
3557 * On PORT_A we can have only eDP in SST mode. There the only reason
3558 * we need to set idle transmission mode is to work around a HW issue
3559 * where we enable the pipe while not in idle link-training mode.
3560 * In this case there is requirement to wait for a minimum number of
3561 * idle patterns to be sent.
3562 */
3563 if (port == PORT_A)
3564 return;
3565
3566 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3567 1))
3568 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3569}
3570
33a34e4e 3571/* Enable corresponding port and start training pattern 1 */
c19b0669 3572void
33a34e4e 3573intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3574{
da63a9f2 3575 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3576 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3577 int i;
3578 uint8_t voltage;
cdb0e95b 3579 int voltage_tries, loop_tries;
ea5b213a 3580 uint32_t DP = intel_dp->DP;
6aba5b6c 3581 uint8_t link_config[2];
a4fc5ed6 3582
affa9354 3583 if (HAS_DDI(dev))
c19b0669
PZ		 3584 intel_ddi_prepare_link_retrain(encoder);
3585
3cf2efb1 3586 /* Write the link configuration data */
6aba5b6c
JN		 3587 link_config[0] = intel_dp->link_bw;
3588 link_config[1] = intel_dp->lane_count;
3589 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3590 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3591 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
94ca719e 3592 if (intel_dp->num_sink_rates)
a8f3ef61
SJ		 3593 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3594 &intel_dp->rate_select, 1);
6aba5b6c
JN		 3595
3596 link_config[0] = 0;
3597 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3598 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3599
3600 DP |= DP_PORT_EN;
1a2eb460 3601
70aff66c
JN		 3602 /* clock recovery */
3603 if (!intel_dp_reset_link_train(intel_dp, &DP,
3604 DP_TRAINING_PATTERN_1 |
3605 DP_LINK_SCRAMBLING_DISABLE)) {
3606 DRM_ERROR("failed to enable link training\n");
3607 return;
3608 }
3609
a4fc5ed6 3610 voltage = 0xff;
cdb0e95b
KP		 3611 voltage_tries = 0;
3612 loop_tries = 0;
a4fc5ed6 3613 for (;;) {
70aff66c 3614 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3615
a7c9655f 3616 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3617 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3618 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3619 break;
93f62dad 3620 }
a4fc5ed6 3621
01916270 3622 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3623 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3624 break;
3625 }
3626
4e96c977
MK		 3627 /*
3628 * if we used previously trained voltage and pre-emphasis values
3629 * and we don't get clock recovery, reset link training values
3630 */
3631 if (intel_dp->train_set_valid) {
3632 DRM_DEBUG_KMS("clock recovery not ok, reset");
3633 /* clear the flag as we are not reusing train set */
3634 intel_dp->train_set_valid = false;
3635 if (!intel_dp_reset_link_train(intel_dp, &DP,
3636 DP_TRAINING_PATTERN_1 |
3637 DP_LINK_SCRAMBLING_DISABLE)) {
3638 DRM_ERROR("failed to enable link training\n");
3639 return;
3640 }
3641 continue;
3642 }
3643
3cf2efb1
CW		 3644 /* Check to see if we've tried the max voltage */
3645 for (i = 0; i < intel_dp->lane_count; i++)
3646 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3647 break;
3b4f819d 3648 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3649 ++loop_tries;
3650 if (loop_tries == 5) {
3def84b3 3651 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3652 break;
3653 }
70aff66c
JN		 3654 intel_dp_reset_link_train(intel_dp, &DP,
3655 DP_TRAINING_PATTERN_1 |
3656 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3657 voltage_tries = 0;
3658 continue;
3659 }
a4fc5ed6 3660
3cf2efb1 3661 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3662 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3663 ++voltage_tries;
b06fbda3 3664 if (voltage_tries == 5) {
3def84b3 3665 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3666 break;
3667 }
3668 } else
3669 voltage_tries = 0;
3670 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3671
70aff66c
JN		 3672 /* Update training set as requested by target */
3673 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3674 DRM_ERROR("failed to update link training\n");
3675 break;
3676 }
a4fc5ed6
KP		 3677 }
3678
33a34e4e
JB		 3679 intel_dp->DP = DP;
3680}
3681
c19b0669 3682void
33a34e4e
JB		 3683intel_dp_complete_link_train(struct intel_dp *intel_dp)
3684{
33a34e4e 3685 bool channel_eq = false;
37f80975 3686 int tries, cr_tries;
33a34e4e 3687 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3688 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3689
3690 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3691 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3692 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3693
a4fc5ed6 3694 /* channel equalization */
70aff66c 3695 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3696 training_pattern |
70aff66c
JN		 3697 DP_LINK_SCRAMBLING_DISABLE)) {
3698 DRM_ERROR("failed to start channel equalization\n");
3699 return;
3700 }
3701
a4fc5ed6 3702 tries = 0;
37f80975 3703 cr_tries = 0;
a4fc5ed6
KP		 3704 channel_eq = false;
3705 for (;;) {
70aff66c 3706 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3707
37f80975
JB		 3708 if (cr_tries > 5) {
3709 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3710 break;
3711 }
3712
a7c9655f 3713 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3714 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3715 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3716 break;
70aff66c 3717 }
a4fc5ed6 3718
37f80975 3719 /* Make sure clock is still ok */
01916270 3720 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
4e96c977 3721 intel_dp->train_set_valid = false;
37f80975 3722 intel_dp_start_link_train(intel_dp);
70aff66c 3723 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3724 training_pattern |
70aff66c 3725 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3726 cr_tries++;
3727 continue;
3728 }
3729
1ffdff13 3730 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3731 channel_eq = true;
3732 break;
3733 }
a4fc5ed6 3734
37f80975
JB		 3735 /* Try 5 times, then try clock recovery if that fails */
3736 if (tries > 5) {
4e96c977 3737 intel_dp->train_set_valid = false;
37f80975 3738 intel_dp_start_link_train(intel_dp);
70aff66c 3739 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3740 training_pattern |
70aff66c 3741 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3742 tries = 0;
3743 cr_tries++;
3744 continue;
3745 }
a4fc5ed6 3746
70aff66c
JN		 3747 /* Update training set as requested by target */
3748 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3749 DRM_ERROR("failed to update link training\n");
3750 break;
3751 }
3cf2efb1 3752 ++tries;
869184a6 3753 }
3cf2efb1 3754
3ab9c637
ID		 3755 intel_dp_set_idle_link_train(intel_dp);
3756
3757 intel_dp->DP = DP;
3758
4e96c977 3759 if (channel_eq) {
5fa836a9 3760 intel_dp->train_set_valid = true;
07f42258 3761 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
4e96c977 3762 }
3ab9c637
ID		 3763}
3764
3765void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3766{
70aff66c 3767 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3768 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3769}
3770
3771static void
ea5b213a 3772intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3773{
da63a9f2 3774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3775 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3776 enum port port = intel_dig_port->port;
da63a9f2 3777 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3778 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3779 uint32_t DP = intel_dp->DP;
a4fc5ed6 3780
bc76e320 3781 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3782 return;
3783
0c33d8d7 3784 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3785 return;
3786
28c97730 3787 DRM_DEBUG_KMS("\n");
32f9d658 3788
39e5fa88
VS		 3789 if ((IS_GEN7(dev) && port == PORT_A) ||
3790 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3791 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3792 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3793 } else {
aad3d14d
VS		 3794 if (IS_CHERRYVIEW(dev))
3795 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3796 else
3797 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3798 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3799 }
1612c8bd 3800 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3801 POSTING_READ(intel_dp->output_reg);
5eb08b69 3802
1612c8bd
VS		 3803 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3804 I915_WRITE(intel_dp->output_reg, DP);
3805 POSTING_READ(intel_dp->output_reg);
3806
3807 /*
3808 * HW workaround for IBX, we need to move the port
3809 * to transcoder A after disabling it to allow the
3810 * matching HDMI port to be enabled on transcoder A.
3811 */
3812 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3813 /* always enable with pattern 1 (as per spec) */
3814 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3815 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3816 I915_WRITE(intel_dp->output_reg, DP);
3817 POSTING_READ(intel_dp->output_reg);
3818
3819 DP &= ~DP_PORT_EN;
5bddd17f 3820 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3821 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3822 }
3823
f01eca2e 3824 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3825}
3826
26d61aad
KP		 3827static bool
3828intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3829{
a031d709
RV		 3830 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3831 struct drm_device *dev = dig_port->base.base.dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3833 uint8_t rev;
a031d709 3834
9d1a1031
JN		 3835 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3836 sizeof(intel_dp->dpcd)) < 0)
edb39244 3837 return false; /* aux transfer failed */
92fd8fd1 3838
a8e98153 3839 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3840
edb39244
AJ		 3841 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3842 return false; /* DPCD not present */
3843
2293bb5c
SK		 3844 /* Check if the panel supports PSR */
3845 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3846 if (is_edp(intel_dp)) {
9d1a1031
JN		 3847 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3848 intel_dp->psr_dpcd,
3849 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3850 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3851 dev_priv->psr.sink_support = true;
50003939 3852 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3853 }
474d1ec4
SJ		 3854
3855 if (INTEL_INFO(dev)->gen >= 9 &&
3856 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3857 uint8_t frame_sync_cap;
3858
3859 dev_priv->psr.sink_support = true;
3860 intel_dp_dpcd_read_wake(&intel_dp->aux,
3861 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3862 &frame_sync_cap, 1);
3863 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3864 /* PSR2 needs frame sync as well */
3865 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3866 DRM_DEBUG_KMS("PSR2 %s on sink",
3867 dev_priv->psr.psr2_support ? "supported" : "not supported");
3868 }
50003939
JN		 3869 }
3870
7809a611 3871 /* Training Pattern 3 support, both source and sink */
06ea66b6 3872 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3873 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3874 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3875 intel_dp->use_tps3 = true;
f8d8a672 3876 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3877 } else
3878 intel_dp->use_tps3 = false;
3879
fc0f8e25
SJ		 3880 /* Intermediate frequency support */
3881 if (is_edp(intel_dp) &&
3882 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3883 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3884 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3885 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3886 int i;
3887
fc0f8e25
SJ		 3888 intel_dp_dpcd_read_wake(&intel_dp->aux,
3889 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3890 sink_rates,
3891 sizeof(sink_rates));
ea2d8a42 3892
94ca719e
VS		 3893 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3894 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3895
3896 if (val == 0)
3897 break;
3898
af77b974
SJ		 3899 /* Value read is in kHz while drm clock is saved in deca-kHz */
3900 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3901 }
94ca719e 3902 intel_dp->num_sink_rates = i;
fc0f8e25 3903 }
0336400e
VS		 3904
3905 intel_dp_print_rates(intel_dp);
3906
edb39244
AJ		 3907 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3908 DP_DWN_STRM_PORT_PRESENT))
3909 return true; /* native DP sink */
3910
3911 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3912 return true; /* no per-port downstream info */
3913
9d1a1031
JN		 3914 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3915 intel_dp->downstream_ports,
3916 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3917 return false; /* downstream port status fetch failed */
3918
3919 return true;
92fd8fd1
KP		 3920}
3921
0d198328
AJ		 3922static void
3923intel_dp_probe_oui(struct intel_dp *intel_dp)
3924{
3925 u8 buf[3];
3926
3927 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3928 return;
3929
9d1a1031 3930 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3931 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3932 buf[0], buf[1], buf[2]);
3933
9d1a1031 3934 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3935 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3936 buf[0], buf[1], buf[2]);
3937}
3938
0e32b39c
DA		 3939static bool
3940intel_dp_probe_mst(struct intel_dp *intel_dp)
3941{
3942 u8 buf[1];
3943
3944 if (!intel_dp->can_mst)
3945 return false;
3946
3947 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3948 return false;
3949
0e32b39c
DA		 3950 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3951 if (buf[0] & DP_MST_CAP) {
3952 DRM_DEBUG_KMS("Sink is MST capable\n");
3953 intel_dp->is_mst = true;
3954 } else {
3955 DRM_DEBUG_KMS("Sink is not MST capable\n");
3956 intel_dp->is_mst = false;
3957 }
3958 }
0e32b39c
DA		 3959
3960 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3961 return intel_dp->is_mst;
3962}
3963
082dcc7c 3964static void intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3965{
082dcc7c
RV		 3966 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3967 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3968 u8 buf;
d2e216d0 3969
082dcc7c
RV		 3970 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3971 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3972 return;
4373f0f2
PZ		 3973 }
3974
082dcc7c
RV		 3975 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3976 buf & ~DP_TEST_SINK_START) < 0)
3977 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
d2e216d0 3978
082dcc7c
RV		 3979 hsw_enable_ips(intel_crtc);
3980}
3981
3982static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3983{
3984 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3985 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3986 u8 buf;
3987
3988 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3989 return -EIO;
3990
3991 if (!(buf & DP_TEST_CRC_SUPPORTED))
3992 return -ENOTTY;
3993
3994 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3995 return -EIO;
3996
3997 hsw_disable_ips(intel_crtc);
1dda5f93 3998
9d1a1031 3999 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 4000 buf | DP_TEST_SINK_START) < 0) {
4001 hsw_enable_ips(intel_crtc);
4002 return -EIO;
4373f0f2
PZ		 4003 }
4004
082dcc7c
RV		 4005 return 0;
4006}
4007
4008int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4009{
4010 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4011 struct drm_device *dev = dig_port->base.base.dev;
4012 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4013 u8 buf;
4014 int test_crc_count;
4015 int attempts = 6;
4016 int ret;
4017
4018 ret = intel_dp_sink_crc_start(intel_dp);
4019 if (ret)
4020 return ret;
4021
4373f0f2
PZ		 4022 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
4023 ret = -EIO;
afe0d67e 4024 goto stop;
4373f0f2 4025 }
d2e216d0 4026
ad9dc91b 4027 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 4028
ad9dc91b 4029 do {
1dda5f93 4030 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 4031 DP_TEST_SINK_MISC, &buf) < 0) {
4032 ret = -EIO;
afe0d67e 4033 goto stop;
4373f0f2 4034 }
ad9dc91b
RV		 4035 intel_wait_for_vblank(dev, intel_crtc->pipe);
4036 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4037
4038 if (attempts == 0) {
90bd1f46 4039 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4373f0f2 4040 ret = -ETIMEDOUT;
afe0d67e 4041 goto stop;
ad9dc91b 4042 }
d2e216d0 4043
082dcc7c 4044 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
4373f0f2 4045 ret = -EIO;
afe0d67e 4046stop:
082dcc7c 4047 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 4048 return ret;
d2e216d0
RV		 4049}
4050
a60f0e38
JB		 4051static bool
4052intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4053{
9d1a1031
JN		 4054 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4055 DP_DEVICE_SERVICE_IRQ_VECTOR,
4056 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4057}
4058
0e32b39c
DA		 4059static bool
4060intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4061{
4062 int ret;
4063
4064 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4065 DP_SINK_COUNT_ESI,
4066 sink_irq_vector, 14);
4067 if (ret != 14)
4068 return false;
4069
4070 return true;
4071}
4072
c5d5ab7a
TP		 4073static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4074{
4075 uint8_t test_result = DP_TEST_ACK;
4076 return test_result;
4077}
4078
4079static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4080{
4081 uint8_t test_result = DP_TEST_NAK;
4082 return test_result;
4083}
4084
4085static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4086{
c5d5ab7a 4087 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4088 struct intel_connector *intel_connector = intel_dp->attached_connector;
4089 struct drm_connector *connector = &intel_connector->base;
4090
4091 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4092 connector->edid_corrupt ||
559be30c
TP		 4093 intel_dp->aux.i2c_defer_count > 6) {
4094 /* Check EDID read for NACKs, DEFERs and corruption
4095 * (DP CTS 1.2 Core r1.1)
4096 * 4.2.2.4 : Failed EDID read, I2C_NAK
4097 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4098 * 4.2.2.6 : EDID corruption detected
4099 * Use failsafe mode for all cases
4100 */
4101 if (intel_dp->aux.i2c_nack_count > 0 ||
4102 intel_dp->aux.i2c_defer_count > 0)
4103 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4104 intel_dp->aux.i2c_nack_count,
4105 intel_dp->aux.i2c_defer_count);
4106 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4107 } else {
4108 if (!drm_dp_dpcd_write(&intel_dp->aux,
4109 DP_TEST_EDID_CHECKSUM,
4110 &intel_connector->detect_edid->checksum,
5a1cc655 4111 1))
559be30c
TP		 4112 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4113
4114 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4115 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4116 }
4117
4118 /* Set test active flag here so userspace doesn't interrupt things */
4119 intel_dp->compliance_test_active = 1;
4120
c5d5ab7a
TP		 4121 return test_result;
4122}
4123
4124static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4125{
c5d5ab7a
TP		 4126 uint8_t test_result = DP_TEST_NAK;
4127 return test_result;
4128}
4129
4130static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4131{
4132 uint8_t response = DP_TEST_NAK;
4133 uint8_t rxdata = 0;
4134 int status = 0;
4135
559be30c 4136 intel_dp->compliance_test_active = 0;
c5d5ab7a 4137 intel_dp->compliance_test_type = 0;
559be30c
TP		 4138 intel_dp->compliance_test_data = 0;
4139
c5d5ab7a
TP		 4140 intel_dp->aux.i2c_nack_count = 0;
4141 intel_dp->aux.i2c_defer_count = 0;
4142
4143 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4144 if (status <= 0) {
4145 DRM_DEBUG_KMS("Could not read test request from sink\n");
4146 goto update_status;
4147 }
4148
4149 switch (rxdata) {
4150 case DP_TEST_LINK_TRAINING:
4151 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4152 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4153 response = intel_dp_autotest_link_training(intel_dp);
4154 break;
4155 case DP_TEST_LINK_VIDEO_PATTERN:
4156 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4157 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4158 response = intel_dp_autotest_video_pattern(intel_dp);
4159 break;
4160 case DP_TEST_LINK_EDID_READ:
4161 DRM_DEBUG_KMS("EDID test requested\n");
4162 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4163 response = intel_dp_autotest_edid(intel_dp);
4164 break;
4165 case DP_TEST_LINK_PHY_TEST_PATTERN:
4166 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4167 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4168 response = intel_dp_autotest_phy_pattern(intel_dp);
4169 break;
4170 default:
4171 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4172 break;
4173 }
4174
4175update_status:
4176 status = drm_dp_dpcd_write(&intel_dp->aux,
4177 DP_TEST_RESPONSE,
4178 &response, 1);
4179 if (status <= 0)
4180 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4181}
4182
0e32b39c
DA		 4183static int
4184intel_dp_check_mst_status(struct intel_dp *intel_dp)
4185{
4186 bool bret;
4187
4188 if (intel_dp->is_mst) {
4189 u8 esi[16] = { 0 };
4190 int ret = 0;
4191 int retry;
4192 bool handled;
4193 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4194go_again:
4195 if (bret == true) {
4196
4197 /* check link status - esi[10] = 0x200c */
4198 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4199 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4200 intel_dp_start_link_train(intel_dp);
4201 intel_dp_complete_link_train(intel_dp);
4202 intel_dp_stop_link_train(intel_dp);
4203 }
4204
6f34cc39 4205 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4206 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4207
4208 if (handled) {
4209 for (retry = 0; retry < 3; retry++) {
4210 int wret;
4211 wret = drm_dp_dpcd_write(&intel_dp->aux,
4212 DP_SINK_COUNT_ESI+1,
4213 &esi[1], 3);
4214 if (wret == 3) {
4215 break;
4216 }
4217 }
4218
4219 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4220 if (bret == true) {
6f34cc39 4221 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4222 goto go_again;
4223 }
4224 } else
4225 ret = 0;
4226
4227 return ret;
4228 } else {
4229 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4230 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4231 intel_dp->is_mst = false;
4232 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4233 /* send a hotplug event */
4234 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4235 }
4236 }
4237 return -EINVAL;
4238}
4239
a4fc5ed6
KP		 4240/*
4241 * According to DP spec
4242 * 5.1.2:
4243 * 1. Read DPCD
4244 * 2. Configure link according to Receiver Capabilities
4245 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4246 * 4. Check link status on receipt of hot-plug interrupt
4247 */
a5146200 4248static void
ea5b213a 4249intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4250{
5b215bcf 4251 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4252 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4253 u8 sink_irq_vector;
93f62dad 4254 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4255
5b215bcf
DA		 4256 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4257
da63a9f2 4258 if (!intel_encoder->connectors_active)
d2b996ac 4259 return;
59cd09e1 4260
da63a9f2 4261 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4262 return;
4263
1a125d8a
ID		 4264 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4265 return;
4266
92fd8fd1 4267 /* Try to read receiver status if the link appears to be up */
93f62dad 4268 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4269 return;
4270 }
4271
92fd8fd1 4272 /* Now read the DPCD to see if it's actually running */
26d61aad 4273 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4274 return;
4275 }
4276
a60f0e38
JB		 4277 /* Try to read the source of the interrupt */
4278 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4279 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4280 /* Clear interrupt source */
9d1a1031
JN		 4281 drm_dp_dpcd_writeb(&intel_dp->aux,
4282 DP_DEVICE_SERVICE_IRQ_VECTOR,
4283 sink_irq_vector);
a60f0e38
JB		 4284
4285 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4286 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4287 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4288 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4289 }
4290
1ffdff13 4291 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4292 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4293 intel_encoder->base.name);
33a34e4e
JB		 4294 intel_dp_start_link_train(intel_dp);
4295 intel_dp_complete_link_train(intel_dp);
3ab9c637 4296 intel_dp_stop_link_train(intel_dp);
33a34e4e 4297 }
a4fc5ed6 4298}
a4fc5ed6 4299
caf9ab24 4300/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4301static enum drm_connector_status
26d61aad 4302intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4303{
caf9ab24 4304 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4305 uint8_t type;
4306
4307 if (!intel_dp_get_dpcd(intel_dp))
4308 return connector_status_disconnected;
4309
4310 /* if there's no downstream port, we're done */
4311 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4312 return connector_status_connected;
caf9ab24
AJ		 4313
4314 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4315 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4316 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4317 uint8_t reg;
9d1a1031
JN		 4318
4319 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4320 &reg, 1) < 0)
caf9ab24 4321 return connector_status_unknown;
9d1a1031 4322
23235177
AJ		 4323 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4324 : connector_status_disconnected;
caf9ab24
AJ		 4325 }
4326
4327 /* If no HPD, poke DDC gently */
0b99836f 4328 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4329 return connector_status_connected;
caf9ab24
AJ		 4330
4331 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4332 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4333 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4334 if (type == DP_DS_PORT_TYPE_VGA ||
4335 type == DP_DS_PORT_TYPE_NON_EDID)
4336 return connector_status_unknown;
4337 } else {
4338 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4339 DP_DWN_STRM_PORT_TYPE_MASK;
4340 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4341 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4342 return connector_status_unknown;
4343 }
caf9ab24
AJ		 4344
4345 /* Anything else is out of spec, warn and ignore */
4346 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4347 return connector_status_disconnected;
71ba9000
AJ		 4348}
4349
d410b56d
CW		 4350static enum drm_connector_status
4351edp_detect(struct intel_dp *intel_dp)
4352{
4353 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4354 enum drm_connector_status status;
4355
4356 status = intel_panel_detect(dev);
4357 if (status == connector_status_unknown)
4358 status = connector_status_connected;
4359
4360 return status;
4361}
4362
5eb08b69 4363static enum drm_connector_status
a9756bb5 4364ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4365{
30add22d 4366 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4367 struct drm_i915_private *dev_priv = dev->dev_private;
4368 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4369
1b469639
DL		 4370 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4371 return connector_status_disconnected;
4372
26d61aad 4373 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4374}
4375
2a592bec
DA		 4376static int g4x_digital_port_connected(struct drm_device *dev,
4377 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4378{
a4fc5ed6 4379 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4380 uint32_t bit;
5eb08b69 4381
232a6ee9
TP		 4382 if (IS_VALLEYVIEW(dev)) {
4383 switch (intel_dig_port->port) {
4384 case PORT_B:
4385 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4386 break;
4387 case PORT_C:
4388 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4389 break;
4390 case PORT_D:
4391 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4392 break;
4393 default:
2a592bec 4394 return -EINVAL;
232a6ee9
TP		 4395 }
4396 } else {
4397 switch (intel_dig_port->port) {
4398 case PORT_B:
4399 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4400 break;
4401 case PORT_C:
4402 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4403 break;
4404 case PORT_D:
4405 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4406 break;
4407 default:
2a592bec 4408 return -EINVAL;
232a6ee9 4409 }
a4fc5ed6
KP		 4410 }
4411
10f76a38 4412 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4413 return 0;
4414 return 1;
4415}
4416
4417static enum drm_connector_status
4418g4x_dp_detect(struct intel_dp *intel_dp)
4419{
4420 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4421 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4422 int ret;
4423
4424 /* Can't disconnect eDP, but you can close the lid... */
4425 if (is_edp(intel_dp)) {
4426 enum drm_connector_status status;
4427
4428 status = intel_panel_detect(dev);
4429 if (status == connector_status_unknown)
4430 status = connector_status_connected;
4431 return status;
4432 }
4433
4434 ret = g4x_digital_port_connected(dev, intel_dig_port);
4435 if (ret == -EINVAL)
4436 return connector_status_unknown;
4437 else if (ret == 0)
a4fc5ed6
KP		 4438 return connector_status_disconnected;
4439
26d61aad 4440 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4441}
4442
8c241fef 4443static struct edid *
beb60608 4444intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4445{
beb60608 4446 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4447
9cd300e0
JN		 4448 /* use cached edid if we have one */
4449 if (intel_connector->edid) {
9cd300e0
JN		 4450 /* invalid edid */
4451 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4452 return NULL;
4453
55e9edeb 4454 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4455 } else
4456 return drm_get_edid(&intel_connector->base,
4457 &intel_dp->aux.ddc);
4458}
8c241fef 4459
beb60608
CW		 4460static void
4461intel_dp_set_edid(struct intel_dp *intel_dp)
4462{
4463 struct intel_connector *intel_connector = intel_dp->attached_connector;
4464 struct edid *edid;
8c241fef 4465
beb60608
CW		 4466 edid = intel_dp_get_edid(intel_dp);
4467 intel_connector->detect_edid = edid;
4468
4469 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4470 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4471 else
4472 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4473}
4474
beb60608
CW		 4475static void
4476intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4477{
beb60608 4478 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4479
beb60608
CW		 4480 kfree(intel_connector->detect_edid);
4481 intel_connector->detect_edid = NULL;
9cd300e0 4482
beb60608
CW		 4483 intel_dp->has_audio = false;
4484}
d6f24d0f 4485
beb60608
CW		 4486static enum intel_display_power_domain
4487intel_dp_power_get(struct intel_dp *dp)
4488{
4489 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4490 enum intel_display_power_domain power_domain;
4491
4492 power_domain = intel_display_port_power_domain(encoder);
4493 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4494
4495 return power_domain;
4496}
d6f24d0f 4497
beb60608
CW		 4498static void
4499intel_dp_power_put(struct intel_dp *dp,
4500 enum intel_display_power_domain power_domain)
4501{
4502 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4503 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4504}
4505
a9756bb5
ZW		 4506static enum drm_connector_status
4507intel_dp_detect(struct drm_connector *connector, bool force)
4508{
4509 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4510 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4511 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4512 struct drm_device *dev = connector->dev;
a9756bb5 4513 enum drm_connector_status status;
671dedd2 4514 enum intel_display_power_domain power_domain;
0e32b39c 4515 bool ret;
09b1eb13 4516 u8 sink_irq_vector;
a9756bb5 4517
164c8598 4518 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4519 connector->base.id, connector->name);
beb60608 4520 intel_dp_unset_edid(intel_dp);
164c8598 4521
0e32b39c
DA		 4522 if (intel_dp->is_mst) {
4523 /* MST devices are disconnected from a monitor POV */
4524 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4525 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4526 return connector_status_disconnected;
0e32b39c
DA		 4527 }
4528
beb60608 4529 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4530
d410b56d
CW		 4531 /* Can't disconnect eDP, but you can close the lid... */
4532 if (is_edp(intel_dp))
4533 status = edp_detect(intel_dp);
4534 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4535 status = ironlake_dp_detect(intel_dp);
4536 else
4537 status = g4x_dp_detect(intel_dp);
4538 if (status != connector_status_connected)
c8c8fb33 4539 goto out;
a9756bb5 4540
0d198328
AJ		 4541 intel_dp_probe_oui(intel_dp);
4542
0e32b39c
DA		 4543 ret = intel_dp_probe_mst(intel_dp);
4544 if (ret) {
4545 /* if we are in MST mode then this connector
4546 won't appear connected or have anything with EDID on it */
4547 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4548 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4549 status = connector_status_disconnected;
4550 goto out;
4551 }
4552
beb60608 4553 intel_dp_set_edid(intel_dp);
a9756bb5 4554
d63885da
PZ		 4555 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4556 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4557 status = connector_status_connected;
4558
09b1eb13
TP		 4559 /* Try to read the source of the interrupt */
4560 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4561 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4562 /* Clear interrupt source */
4563 drm_dp_dpcd_writeb(&intel_dp->aux,
4564 DP_DEVICE_SERVICE_IRQ_VECTOR,
4565 sink_irq_vector);
4566
4567 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4568 intel_dp_handle_test_request(intel_dp);
4569 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4570 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4571 }
4572
c8c8fb33 4573out:
beb60608 4574 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4575 return status;
a4fc5ed6
KP		 4576}
4577
beb60608
CW		 4578static void
4579intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4580{
df0e9248 4581 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4582 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4583 enum intel_display_power_domain power_domain;
a4fc5ed6 4584
beb60608
CW		 4585 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4586 connector->base.id, connector->name);
4587 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4588
beb60608
CW		 4589 if (connector->status != connector_status_connected)
4590 return;
671dedd2 4591
beb60608
CW		 4592 power_domain = intel_dp_power_get(intel_dp);
4593
4594 intel_dp_set_edid(intel_dp);
4595
4596 intel_dp_power_put(intel_dp, power_domain);
4597
4598 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4599 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4600}
4601
4602static int intel_dp_get_modes(struct drm_connector *connector)
4603{
4604 struct intel_connector *intel_connector = to_intel_connector(connector);
4605 struct edid *edid;
4606
4607 edid = intel_connector->detect_edid;
4608 if (edid) {
4609 int ret = intel_connector_update_modes(connector, edid);
4610 if (ret)
4611 return ret;
4612 }
32f9d658 4613
f8779fda 4614 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4615 if (is_edp(intel_attached_dp(connector)) &&
4616 intel_connector->panel.fixed_mode) {
f8779fda 4617 struct drm_display_mode *mode;
beb60608
CW		 4618
4619 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4620 intel_connector->panel.fixed_mode);
f8779fda 4621 if (mode) {
32f9d658
ZW		 4622 drm_mode_probed_add(connector, mode);
4623 return 1;
4624 }
4625 }
beb60608 4626
32f9d658 4627 return 0;
a4fc5ed6
KP		 4628}
4629
1aad7ac0
CW		 4630static bool
4631intel_dp_detect_audio(struct drm_connector *connector)
4632{
1aad7ac0 4633 bool has_audio = false;
beb60608 4634 struct edid *edid;
1aad7ac0 4635
beb60608
CW		 4636 edid = to_intel_connector(connector)->detect_edid;
4637 if (edid)
1aad7ac0 4638 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4639
1aad7ac0
CW		 4640 return has_audio;
4641}
4642
f684960e
CW		 4643static int
4644intel_dp_set_property(struct drm_connector *connector,
4645 struct drm_property *property,
4646 uint64_t val)
4647{
e953fd7b 4648 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4649 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4650 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4651 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4652 int ret;
4653
662595df 4654 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4655 if (ret)
4656 return ret;
4657
3f43c48d 4658 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4659 int i = val;
4660 bool has_audio;
4661
4662 if (i == intel_dp->force_audio)
f684960e
CW		 4663 return 0;
4664
1aad7ac0 4665 intel_dp->force_audio = i;
f684960e 4666
c3e5f67b 4667 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4668 has_audio = intel_dp_detect_audio(connector);
4669 else
c3e5f67b 4670 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4671
4672 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4673 return 0;
4674
1aad7ac0 4675 intel_dp->has_audio = has_audio;
f684960e
CW		 4676 goto done;
4677 }
4678
e953fd7b 4679 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4680 bool old_auto = intel_dp->color_range_auto;
4681 uint32_t old_range = intel_dp->color_range;
4682
55bc60db
VS		 4683 switch (val) {
4684 case INTEL_BROADCAST_RGB_AUTO:
4685 intel_dp->color_range_auto = true;
4686 break;
4687 case INTEL_BROADCAST_RGB_FULL:
4688 intel_dp->color_range_auto = false;
4689 intel_dp->color_range = 0;
4690 break;
4691 case INTEL_BROADCAST_RGB_LIMITED:
4692 intel_dp->color_range_auto = false;
4693 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4694 break;
4695 default:
4696 return -EINVAL;
4697 }
ae4edb80
DV		 4698
4699 if (old_auto == intel_dp->color_range_auto &&
4700 old_range == intel_dp->color_range)
4701 return 0;
4702
e953fd7b
CW		 4703 goto done;
4704 }
4705
53b41837
YN		 4706 if (is_edp(intel_dp) &&
4707 property == connector->dev->mode_config.scaling_mode_property) {
4708 if (val == DRM_MODE_SCALE_NONE) {
4709 DRM_DEBUG_KMS("no scaling not supported\n");
4710 return -EINVAL;
4711 }
4712
4713 if (intel_connector->panel.fitting_mode == val) {
4714 /* the eDP scaling property is not changed */
4715 return 0;
4716 }
4717 intel_connector->panel.fitting_mode = val;
4718
4719 goto done;
4720 }
4721
f684960e
CW		 4722 return -EINVAL;
4723
4724done:
c0c36b94
CW		 4725 if (intel_encoder->base.crtc)
4726 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4727
4728 return 0;
4729}
4730
a4fc5ed6 4731static void
73845adf 4732intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4733{
1d508706 4734 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4735
10e972d3 4736 kfree(intel_connector->detect_edid);
beb60608 4737
9cd300e0
JN		 4738 if (!IS_ERR_OR_NULL(intel_connector->edid))
4739 kfree(intel_connector->edid);
4740
acd8db10
PZ		 4741 /* Can't call is_edp() since the encoder may have been destroyed
4742 * already. */
4743 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4744 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4745
a4fc5ed6 4746 drm_connector_cleanup(connector);
55f78c43 4747 kfree(connector);
a4fc5ed6
KP		 4748}
4749
00c09d70 4750void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4751{
da63a9f2
PZ		 4752 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4753 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4754
4f71d0cb 4755 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4756 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4757 if (is_edp(intel_dp)) {
4758 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4759 /*
4760 * vdd might still be enabled do to the delayed vdd off.
4761 * Make sure vdd is actually turned off here.
4762 */
773538e8 4763 pps_lock(intel_dp);
4be73780 4764 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4765 pps_unlock(intel_dp);
4766
01527b31
CT		 4767 if (intel_dp->edp_notifier.notifier_call) {
4768 unregister_reboot_notifier(&intel_dp->edp_notifier);
4769 intel_dp->edp_notifier.notifier_call = NULL;
4770 }
bd943159 4771 }
c8bd0e49 4772 drm_encoder_cleanup(encoder);
da63a9f2 4773 kfree(intel_dig_port);
24d05927
DV		 4774}
4775
07f9cd0b
ID		 4776static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4777{
4778 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4779
4780 if (!is_edp(intel_dp))
4781 return;
4782
951468f3
VS		 4783 /*
4784 * vdd might still be enabled do to the delayed vdd off.
4785 * Make sure vdd is actually turned off here.
4786 */
afa4e53a 4787 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4788 pps_lock(intel_dp);
07f9cd0b 4789 edp_panel_vdd_off_sync(intel_dp);
773538e8 4790 pps_unlock(intel_dp);
07f9cd0b
ID		 4791}
4792
49e6bc51
VS		 4793static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4794{
4795 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4796 struct drm_device *dev = intel_dig_port->base.base.dev;
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4798 enum intel_display_power_domain power_domain;
4799
4800 lockdep_assert_held(&dev_priv->pps_mutex);
4801
4802 if (!edp_have_panel_vdd(intel_dp))
4803 return;
4804
4805 /*
4806 * The VDD bit needs a power domain reference, so if the bit is
4807 * already enabled when we boot or resume, grab this reference and
4808 * schedule a vdd off, so we don't hold on to the reference
4809 * indefinitely.
4810 */
4811 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4812 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4813 intel_display_power_get(dev_priv, power_domain);
4814
4815 edp_panel_vdd_schedule_off(intel_dp);
4816}
4817
6d93c0c4
ID		 4818static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4819{
49e6bc51
VS		 4820 struct intel_dp *intel_dp;
4821
4822 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4823 return;
4824
4825 intel_dp = enc_to_intel_dp(encoder);
4826
4827 pps_lock(intel_dp);
4828
4829 /*
4830 * Read out the current power sequencer assignment,
4831 * in case the BIOS did something with it.
4832 */
4833 if (IS_VALLEYVIEW(encoder->dev))
4834 vlv_initial_power_sequencer_setup(intel_dp);
4835
4836 intel_edp_panel_vdd_sanitize(intel_dp);
4837
4838 pps_unlock(intel_dp);
6d93c0c4
ID		 4839}
4840
a4fc5ed6 4841static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4842 .dpms = intel_connector_dpms,
a4fc5ed6 4843 .detect = intel_dp_detect,
beb60608 4844 .force = intel_dp_force,
a4fc5ed6 4845 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4846 .set_property = intel_dp_set_property,
2545e4a6 4847 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4848 .destroy = intel_dp_connector_destroy,
c6f95f27 4849 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4850 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4851};
4852
4853static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4854 .get_modes = intel_dp_get_modes,
4855 .mode_valid = intel_dp_mode_valid,
df0e9248 4856 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4857};
4858
a4fc5ed6 4859static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4860 .reset = intel_dp_encoder_reset,
24d05927 4861 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4862};
4863
b2c5c181 4864enum irqreturn
13cf5504
DA		 4865intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4866{
4867 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4868 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4869 struct drm_device *dev = intel_dig_port->base.base.dev;
4870 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4871 enum intel_display_power_domain power_domain;
b2c5c181 4872 enum irqreturn ret = IRQ_NONE;
1c767b33 4873
0e32b39c
DA		 4874 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4875 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4876
7a7f84cc
VS		 4877 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4878 /*
4879 * vdd off can generate a long pulse on eDP which
4880 * would require vdd on to handle it, and thus we
4881 * would end up in an endless cycle of
4882 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4883 */
4884 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4885 port_name(intel_dig_port->port));
a8b3d52f 4886 return IRQ_HANDLED;
7a7f84cc
VS		 4887 }
4888
26fbb774
VS		 4889 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4890 port_name(intel_dig_port->port),
0e32b39c 4891 long_hpd ? "long" : "short");
13cf5504 4892
1c767b33
ID		 4893 power_domain = intel_display_port_power_domain(intel_encoder);
4894 intel_display_power_get(dev_priv, power_domain);
4895
0e32b39c 4896 if (long_hpd) {
5fa836a9
MK		 4897 /* indicate that we need to restart link training */
4898 intel_dp->train_set_valid = false;
2a592bec
DA		 4899
4900 if (HAS_PCH_SPLIT(dev)) {
4901 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4902 goto mst_fail;
4903 } else {
4904 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4905 goto mst_fail;
4906 }
0e32b39c
DA		 4907
4908 if (!intel_dp_get_dpcd(intel_dp)) {
4909 goto mst_fail;
4910 }
4911
4912 intel_dp_probe_oui(intel_dp);
4913
4914 if (!intel_dp_probe_mst(intel_dp))
4915 goto mst_fail;
4916
4917 } else {
4918 if (intel_dp->is_mst) {
1c767b33 4919 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4920 goto mst_fail;
4921 }
4922
4923 if (!intel_dp->is_mst) {
4924 /*
4925 * we'll check the link status via the normal hot plug path later -
4926 * but for short hpds we should check it now
4927 */
5b215bcf 4928 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4929 intel_dp_check_link_status(intel_dp);
5b215bcf 4930 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4931 }
4932 }
b2c5c181
DV		 4933
4934 ret = IRQ_HANDLED;
4935
1c767b33 4936 goto put_power;
0e32b39c
DA		 4937mst_fail:
4938 /* if we were in MST mode, and device is not there get out of MST mode */
4939 if (intel_dp->is_mst) {
4940 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4941 intel_dp->is_mst = false;
4942 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4943 }
1c767b33
ID		 4944put_power:
4945 intel_display_power_put(dev_priv, power_domain);
4946
4947 return ret;
13cf5504
DA		 4948}
4949
e3421a18
ZW		 4950/* Return which DP Port should be selected for Transcoder DP control */
4951int
0206e353 4952intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4953{
4954 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4955 struct intel_encoder *intel_encoder;
4956 struct intel_dp *intel_dp;
e3421a18 4957
fa90ecef
PZ		 4958 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4959 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4960
fa90ecef
PZ		 4961 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4962 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4963 return intel_dp->output_reg;
e3421a18 4964 }
ea5b213a 4965
e3421a18
ZW		 4966 return -1;
4967}
4968
36e83a18 4969/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4970bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4971{
4972 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4973 union child_device_config *p_child;
36e83a18 4974 int i;
5d8a7752
VS		 4975 static const short port_mapping[] = {
4976 [PORT_B] = PORT_IDPB,
4977 [PORT_C] = PORT_IDPC,
4978 [PORT_D] = PORT_IDPD,
4979 };
36e83a18 4980
3b32a35b
VS		 4981 if (port == PORT_A)
4982 return true;
4983
41aa3448 4984 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4985 return false;
4986
41aa3448
RV		 4987 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4988 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4989
5d8a7752 4990 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4991 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4992 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4993 return true;
4994 }
4995 return false;
4996}
4997
0e32b39c 4998void
f684960e
CW		 4999intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5000{
53b41837
YN		 5001 struct intel_connector *intel_connector = to_intel_connector(connector);
5002
3f43c48d 5003 intel_attach_force_audio_property(connector);
e953fd7b 5004 intel_attach_broadcast_rgb_property(connector);
55bc60db 5005 intel_dp->color_range_auto = true;
53b41837
YN		 5006
5007 if (is_edp(intel_dp)) {
5008 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 5009 drm_object_attach_property(
5010 &connector->base,
53b41837 5011 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 5012 DRM_MODE_SCALE_ASPECT);
5013 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5014 }
f684960e
CW		 5015}
5016
dada1a9f
ID		 5017static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5018{
5019 intel_dp->last_power_cycle = jiffies;
5020 intel_dp->last_power_on = jiffies;
5021 intel_dp->last_backlight_off = jiffies;
5022}
5023
67a54566
DV		 5024static void
5025intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5026 struct intel_dp *intel_dp)
67a54566
DV		 5027{
5028 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5029 struct edp_power_seq cur, vbt, spec,
5030 *final = &intel_dp->pps_delays;
b0a08bec
VK		 5031 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5032 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
453c5420 5033
e39b999a
VS		 5034 lockdep_assert_held(&dev_priv->pps_mutex);
5035
81ddbc69
VS		 5036 /* already initialized? */
5037 if (final->t11_t12 != 0)
5038 return;
5039
b0a08bec
VK		 5040 if (IS_BROXTON(dev)) {
5041 /*
5042 * TODO: BXT has 2 sets of PPS registers.
5043 * Correct Register for Broxton need to be identified
5044 * using VBT. hardcoding for now
5045 */
5046 pp_ctrl_reg = BXT_PP_CONTROL(0);
5047 pp_on_reg = BXT_PP_ON_DELAYS(0);
5048 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5049 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5050 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5051 pp_on_reg = PCH_PP_ON_DELAYS;
5052 pp_off_reg = PCH_PP_OFF_DELAYS;
5053 pp_div_reg = PCH_PP_DIVISOR;
5054 } else {
bf13e81b
JN		 5055 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5056
5057 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5058 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5059 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5060 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5061 }
67a54566
DV		 5062
5063 /* Workaround: Need to write PP_CONTROL with the unlock key as
5064 * the very first thing. */
b0a08bec 5065 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5066
453c5420
JB		 5067 pp_on = I915_READ(pp_on_reg);
5068 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 5069 if (!IS_BROXTON(dev)) {
5070 I915_WRITE(pp_ctrl_reg, pp_ctl);
5071 pp_div = I915_READ(pp_div_reg);
5072 }
67a54566
DV		 5073
5074 /* Pull timing values out of registers */
5075 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5076 PANEL_POWER_UP_DELAY_SHIFT;
5077
5078 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5079 PANEL_LIGHT_ON_DELAY_SHIFT;
5080
5081 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5082 PANEL_LIGHT_OFF_DELAY_SHIFT;
5083
5084 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5085 PANEL_POWER_DOWN_DELAY_SHIFT;
5086
b0a08bec
VK		 5087 if (IS_BROXTON(dev)) {
5088 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5089 BXT_POWER_CYCLE_DELAY_SHIFT;
5090 if (tmp > 0)
5091 cur.t11_t12 = (tmp - 1) * 1000;
5092 else
5093 cur.t11_t12 = 0;
5094 } else {
5095 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5096 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5097 }
67a54566
DV		 5098
5099 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5100 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5101
41aa3448 5102 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5103
5104 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5105 * our hw here, which are all in 100usec. */
5106 spec.t1_t3 = 210 * 10;
5107 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5108 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5109 spec.t10 = 500 * 10;
5110 /* This one is special and actually in units of 100ms, but zero
5111 * based in the hw (so we need to add 100 ms). But the sw vbt
5112 * table multiplies it with 1000 to make it in units of 100usec,
5113 * too. */
5114 spec.t11_t12 = (510 + 100) * 10;
5115
5116 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5117 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5118
5119 /* Use the max of the register settings and vbt. If both are
5120 * unset, fall back to the spec limits. */
36b5f425 5121#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5122 spec.field : \
5123 max(cur.field, vbt.field))
5124 assign_final(t1_t3);
5125 assign_final(t8);
5126 assign_final(t9);
5127 assign_final(t10);
5128 assign_final(t11_t12);
5129#undef assign_final
5130
36b5f425 5131#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5132 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5133 intel_dp->backlight_on_delay = get_delay(t8);
5134 intel_dp->backlight_off_delay = get_delay(t9);
5135 intel_dp->panel_power_down_delay = get_delay(t10);
5136 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5137#undef get_delay
5138
f30d26e4
JN		 5139 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5140 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5141 intel_dp->panel_power_cycle_delay);
5142
5143 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5144 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5145}
5146
5147static void
5148intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5149 struct intel_dp *intel_dp)
f30d26e4
JN		 5150{
5151 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5152 u32 pp_on, pp_off, pp_div, port_sel = 0;
5153 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
b0a08bec 5154 int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
ad933b56 5155 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5156 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5157
e39b999a 5158 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5159
b0a08bec
VK		 5160 if (IS_BROXTON(dev)) {
5161 /*
5162 * TODO: BXT has 2 sets of PPS registers.
5163 * Correct Register for Broxton need to be identified
5164 * using VBT. hardcoding for now
5165 */
5166 pp_ctrl_reg = BXT_PP_CONTROL(0);
5167 pp_on_reg = BXT_PP_ON_DELAYS(0);
5168 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5169
5170 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 5171 pp_on_reg = PCH_PP_ON_DELAYS;
5172 pp_off_reg = PCH_PP_OFF_DELAYS;
5173 pp_div_reg = PCH_PP_DIVISOR;
5174 } else {
bf13e81b
JN		 5175 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5176
5177 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5178 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5179 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5180 }
5181
b2f19d1a
PZ		 5182 /*
5183 * And finally store the new values in the power sequencer. The
5184 * backlight delays are set to 1 because we do manual waits on them. For
5185 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5186 * we'll end up waiting for the backlight off delay twice: once when we
5187 * do the manual sleep, and once when we disable the panel and wait for
5188 * the PP_STATUS bit to become zero.
5189 */
f30d26e4 5190 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5191 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5192 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5193 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5194 /* Compute the divisor for the pp clock, simply match the Bspec
5195 * formula. */
b0a08bec
VK		 5196 if (IS_BROXTON(dev)) {
5197 pp_div = I915_READ(pp_ctrl_reg);
5198 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5199 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5200 << BXT_POWER_CYCLE_DELAY_SHIFT);
5201 } else {
5202 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5203 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5204 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5205 }
67a54566
DV		 5206
5207 /* Haswell doesn't have any port selection bits for the panel
5208 * power sequencer any more. */
bc7d38a4 5209 if (IS_VALLEYVIEW(dev)) {
ad933b56 5210 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5211 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5212 if (port == PORT_A)
a24c144c 5213 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5214 else
a24c144c 5215 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5216 }
5217
453c5420
JB		 5218 pp_on |= port_sel;
5219
5220 I915_WRITE(pp_on_reg, pp_on);
5221 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 5222 if (IS_BROXTON(dev))
5223 I915_WRITE(pp_ctrl_reg, pp_div);
5224 else
5225 I915_WRITE(pp_div_reg, pp_div);
67a54566 5226
67a54566 5227 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5228 I915_READ(pp_on_reg),
5229 I915_READ(pp_off_reg),
b0a08bec
VK		 5230 IS_BROXTON(dev) ?
5231 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 5232 I915_READ(pp_div_reg));
f684960e
CW		 5233}
5234
b33a2815
VK		 5235/**
5236 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5237 * @dev: DRM device
5238 * @refresh_rate: RR to be programmed
5239 *
5240 * This function gets called when refresh rate (RR) has to be changed from
5241 * one frequency to another. Switches can be between high and low RR
5242 * supported by the panel or to any other RR based on media playback (in
5243 * this case, RR value needs to be passed from user space).
5244 *
5245 * The caller of this function needs to take a lock on dev_priv->drrs.
5246 */
96178eeb 5247static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5248{
5249 struct drm_i915_private *dev_priv = dev->dev_private;
5250 struct intel_encoder *encoder;
96178eeb
VK		 5251 struct intel_digital_port *dig_port = NULL;
5252 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5253 struct intel_crtc_state *config = NULL;
439d7ac0 5254 struct intel_crtc *intel_crtc = NULL;
439d7ac0 5255 u32 reg, val;
96178eeb 5256 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5257
5258 if (refresh_rate <= 0) {
5259 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5260 return;
5261 }
5262
96178eeb
VK		 5263 if (intel_dp == NULL) {
5264 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5265 return;
5266 }
5267
1fcc9d1c 5268 /*
e4d59f6b
RV		 5269 * FIXME: This needs proper synchronization with psr state for some
5270 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5271 */
439d7ac0 5272
96178eeb
VK		 5273 dig_port = dp_to_dig_port(intel_dp);
5274 encoder = &dig_port->base;
723f9aab 5275 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5276
5277 if (!intel_crtc) {
5278 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5279 return;
5280 }
5281
6e3c9717 5282 config = intel_crtc->config;
439d7ac0 5283
96178eeb 5284 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5285 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5286 return;
5287 }
5288
96178eeb
VK		 5289 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5290 refresh_rate)
439d7ac0
PB		 5291 index = DRRS_LOW_RR;
5292
96178eeb 5293 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5294 DRM_DEBUG_KMS(
5295 "DRRS requested for previously set RR...ignoring\n");
5296 return;
5297 }
5298
5299 if (!intel_crtc->active) {
5300 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5301 return;
5302 }
5303
44395bfe 5304 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5305 switch (index) {
5306 case DRRS_HIGH_RR:
5307 intel_dp_set_m_n(intel_crtc, M1_N1);
5308 break;
5309 case DRRS_LOW_RR:
5310 intel_dp_set_m_n(intel_crtc, M2_N2);
5311 break;
5312 case DRRS_MAX_RR:
5313 default:
5314 DRM_ERROR("Unsupported refreshrate type\n");
5315 }
5316 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 5317 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 5318 val = I915_READ(reg);
a4c30b1d 5319
439d7ac0 5320 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5321 if (IS_VALLEYVIEW(dev))
5322 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5323 else
5324 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5325 } else {
6fa7aec1
VK		 5326 if (IS_VALLEYVIEW(dev))
5327 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5328 else
5329 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5330 }
5331 I915_WRITE(reg, val);
5332 }
5333
4e9ac947
VK		 5334 dev_priv->drrs.refresh_rate_type = index;
5335
5336 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5337}
5338
b33a2815
VK		 5339/**
5340 * intel_edp_drrs_enable - init drrs struct if supported
5341 * @intel_dp: DP struct
5342 *
5343 * Initializes frontbuffer_bits and drrs.dp
5344 */
c395578e
VK		 5345void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5346{
5347 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5348 struct drm_i915_private *dev_priv = dev->dev_private;
5349 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5350 struct drm_crtc *crtc = dig_port->base.base.crtc;
5351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5352
5353 if (!intel_crtc->config->has_drrs) {
5354 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5355 return;
5356 }
5357
5358 mutex_lock(&dev_priv->drrs.mutex);
5359 if (WARN_ON(dev_priv->drrs.dp)) {
5360 DRM_ERROR("DRRS already enabled\n");
5361 goto unlock;
5362 }
5363
5364 dev_priv->drrs.busy_frontbuffer_bits = 0;
5365
5366 dev_priv->drrs.dp = intel_dp;
5367
5368unlock:
5369 mutex_unlock(&dev_priv->drrs.mutex);
5370}
5371
b33a2815
VK		 5372/**
5373 * intel_edp_drrs_disable - Disable DRRS
5374 * @intel_dp: DP struct
5375 *
5376 */
c395578e
VK		 5377void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5378{
5379 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5382 struct drm_crtc *crtc = dig_port->base.base.crtc;
5383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5384
5385 if (!intel_crtc->config->has_drrs)
5386 return;
5387
5388 mutex_lock(&dev_priv->drrs.mutex);
5389 if (!dev_priv->drrs.dp) {
5390 mutex_unlock(&dev_priv->drrs.mutex);
5391 return;
5392 }
5393
5394 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5395 intel_dp_set_drrs_state(dev_priv->dev,
5396 intel_dp->attached_connector->panel.
5397 fixed_mode->vrefresh);
5398
5399 dev_priv->drrs.dp = NULL;
5400 mutex_unlock(&dev_priv->drrs.mutex);
5401
5402 cancel_delayed_work_sync(&dev_priv->drrs.work);
5403}
5404
4e9ac947
VK		 5405static void intel_edp_drrs_downclock_work(struct work_struct *work)
5406{
5407 struct drm_i915_private *dev_priv =
5408 container_of(work, typeof(*dev_priv), drrs.work.work);
5409 struct intel_dp *intel_dp;
5410
5411 mutex_lock(&dev_priv->drrs.mutex);
5412
5413 intel_dp = dev_priv->drrs.dp;
5414
5415 if (!intel_dp)
5416 goto unlock;
5417
439d7ac0 5418 /*
4e9ac947
VK		 5419 * The delayed work can race with an invalidate hence we need to
5420 * recheck.
439d7ac0
PB		 5421 */
5422
4e9ac947
VK		 5423 if (dev_priv->drrs.busy_frontbuffer_bits)
5424 goto unlock;
439d7ac0 5425
4e9ac947
VK		 5426 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5427 intel_dp_set_drrs_state(dev_priv->dev,
5428 intel_dp->attached_connector->panel.
5429 downclock_mode->vrefresh);
439d7ac0 5430
4e9ac947 5431unlock:
4e9ac947 5432 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5433}
5434
b33a2815 5435/**
0ddfd203 5436 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5437 * @dev: DRM device
5438 * @frontbuffer_bits: frontbuffer plane tracking bits
5439 *
0ddfd203
R		 5440 * This function gets called everytime rendering on the given planes start.
5441 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5442 *
5443 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5444 */
a93fad0f
VK		 5445void intel_edp_drrs_invalidate(struct drm_device *dev,
5446 unsigned frontbuffer_bits)
5447{
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 struct drm_crtc *crtc;
5450 enum pipe pipe;
5451
9da7d693 5452 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5453 return;
5454
88f933a8 5455 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5456
a93fad0f 5457 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5458 if (!dev_priv->drrs.dp) {
5459 mutex_unlock(&dev_priv->drrs.mutex);
5460 return;
5461 }
5462
a93fad0f
VK		 5463 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5464 pipe = to_intel_crtc(crtc)->pipe;
5465
c1d038c6
DV		 5466 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5467 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5468
0ddfd203 5469 /* invalidate means busy screen hence upclock */
c1d038c6 5470 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5471 intel_dp_set_drrs_state(dev_priv->dev,
5472 dev_priv->drrs.dp->attached_connector->panel.
5473 fixed_mode->vrefresh);
a93fad0f 5474
a93fad0f
VK		 5475 mutex_unlock(&dev_priv->drrs.mutex);
5476}
5477
b33a2815 5478/**
0ddfd203 5479 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5480 * @dev: DRM device
5481 * @frontbuffer_bits: frontbuffer plane tracking bits
5482 *
0ddfd203
R		 5483 * This function gets called every time rendering on the given planes has
5484 * completed or flip on a crtc is completed. So DRRS should be upclocked
5485 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5486 * if no other planes are dirty.
b33a2815
VK		 5487 *
5488 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5489 */
a93fad0f
VK		 5490void intel_edp_drrs_flush(struct drm_device *dev,
5491 unsigned frontbuffer_bits)
5492{
5493 struct drm_i915_private *dev_priv = dev->dev_private;
5494 struct drm_crtc *crtc;
5495 enum pipe pipe;
5496
9da7d693 5497 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5498 return;
5499
88f933a8 5500 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5501
a93fad0f 5502 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5503 if (!dev_priv->drrs.dp) {
5504 mutex_unlock(&dev_priv->drrs.mutex);
5505 return;
5506 }
5507
a93fad0f
VK		 5508 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5509 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5510
5511 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5512 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5513
0ddfd203 5514 /* flush means busy screen hence upclock */
c1d038c6 5515 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5516 intel_dp_set_drrs_state(dev_priv->dev,
5517 dev_priv->drrs.dp->attached_connector->panel.
5518 fixed_mode->vrefresh);
5519
5520 /*
5521 * flush also means no more activity hence schedule downclock, if all
5522 * other fbs are quiescent too
5523 */
5524 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5525 schedule_delayed_work(&dev_priv->drrs.work,
5526 msecs_to_jiffies(1000));
5527 mutex_unlock(&dev_priv->drrs.mutex);
5528}
5529
b33a2815
VK		 5530/**
5531 * DOC: Display Refresh Rate Switching (DRRS)
5532 *
5533 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5534 * which enables swtching between low and high refresh rates,
5535 * dynamically, based on the usage scenario. This feature is applicable
5536 * for internal panels.
5537 *
5538 * Indication that the panel supports DRRS is given by the panel EDID, which
5539 * would list multiple refresh rates for one resolution.
5540 *
5541 * DRRS is of 2 types - static and seamless.
5542 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5543 * (may appear as a blink on screen) and is used in dock-undock scenario.
5544 * Seamless DRRS involves changing RR without any visual effect to the user
5545 * and can be used during normal system usage. This is done by programming
5546 * certain registers.
5547 *
5548 * Support for static/seamless DRRS may be indicated in the VBT based on
5549 * inputs from the panel spec.
5550 *
5551 * DRRS saves power by switching to low RR based on usage scenarios.
5552 *
5553 * eDP DRRS:-
5554 * The implementation is based on frontbuffer tracking implementation.
5555 * When there is a disturbance on the screen triggered by user activity or a
5556 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5557 * When there is no movement on screen, after a timeout of 1 second, a switch
5558 * to low RR is made.
5559 * For integration with frontbuffer tracking code,
5560 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5561 *
5562 * DRRS can be further extended to support other internal panels and also
5563 * the scenario of video playback wherein RR is set based on the rate
5564 * requested by userspace.
5565 */
5566
5567/**
5568 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5569 * @intel_connector: eDP connector
5570 * @fixed_mode: preferred mode of panel
5571 *
5572 * This function is called only once at driver load to initialize basic
5573 * DRRS stuff.
5574 *
5575 * Returns:
5576 * Downclock mode if panel supports it, else return NULL.
5577 * DRRS support is determined by the presence of downclock mode (apart
5578 * from VBT setting).
5579 */
4f9db5b5 5580static struct drm_display_mode *
96178eeb
VK		 5581intel_dp_drrs_init(struct intel_connector *intel_connector,
5582 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5583{
5584 struct drm_connector *connector = &intel_connector->base;
96178eeb 5585 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5586 struct drm_i915_private *dev_priv = dev->dev_private;
5587 struct drm_display_mode *downclock_mode = NULL;
5588
9da7d693
DV		 5589 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5590 mutex_init(&dev_priv->drrs.mutex);
5591
4f9db5b5
PB		 5592 if (INTEL_INFO(dev)->gen <= 6) {
5593 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5594 return NULL;
5595 }
5596
5597 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5598 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5599 return NULL;
5600 }
5601
5602 downclock_mode = intel_find_panel_downclock
5603 (dev, fixed_mode, connector);
5604
5605 if (!downclock_mode) {
a1d26342 5606 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5607 return NULL;
5608 }
5609
96178eeb 5610 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5611
96178eeb 5612 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5613 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5614 return downclock_mode;
5615}
5616
ed92f0b2 5617static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5618 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5619{
5620 struct drm_connector *connector = &intel_connector->base;
5621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5622 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5623 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5624 struct drm_i915_private *dev_priv = dev->dev_private;
5625 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5626 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5627 bool has_dpcd;
5628 struct drm_display_mode *scan;
5629 struct edid *edid;
6517d273 5630 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5631
5632 if (!is_edp(intel_dp))
5633 return true;
5634
49e6bc51
VS		 5635 pps_lock(intel_dp);
5636 intel_edp_panel_vdd_sanitize(intel_dp);
5637 pps_unlock(intel_dp);
63635217 5638
ed92f0b2 5639 /* Cache DPCD and EDID for edp. */
ed92f0b2 5640 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5641
5642 if (has_dpcd) {
5643 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5644 dev_priv->no_aux_handshake =
5645 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5646 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5647 } else {
5648 /* if this fails, presume the device is a ghost */
5649 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5650 return false;
5651 }
5652
5653 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5654 pps_lock(intel_dp);
36b5f425 5655 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5656 pps_unlock(intel_dp);
ed92f0b2 5657
060c8778 5658 mutex_lock(&dev->mode_config.mutex);
0b99836f 5659 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5660 if (edid) {
5661 if (drm_add_edid_modes(connector, edid)) {
5662 drm_mode_connector_update_edid_property(connector,
5663 edid);
5664 drm_edid_to_eld(connector, edid);
5665 } else {
5666 kfree(edid);
5667 edid = ERR_PTR(-EINVAL);
5668 }
5669 } else {
5670 edid = ERR_PTR(-ENOENT);
5671 }
5672 intel_connector->edid = edid;
5673
5674 /* prefer fixed mode from EDID if available */
5675 list_for_each_entry(scan, &connector->probed_modes, head) {
5676 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5677 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5678 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5679 intel_connector, fixed_mode);
ed92f0b2
PZ		 5680 break;
5681 }
5682 }
5683
5684 /* fallback to VBT if available for eDP */
5685 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5686 fixed_mode = drm_mode_duplicate(dev,
5687 dev_priv->vbt.lfp_lvds_vbt_mode);
5688 if (fixed_mode)
5689 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5690 }
060c8778 5691 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5692
01527b31
CT		 5693 if (IS_VALLEYVIEW(dev)) {
5694 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5695 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5696
5697 /*
5698 * Figure out the current pipe for the initial backlight setup.
5699 * If the current pipe isn't valid, try the PPS pipe, and if that
5700 * fails just assume pipe A.
5701 */
5702 if (IS_CHERRYVIEW(dev))
5703 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5704 else
5705 pipe = PORT_TO_PIPE(intel_dp->DP);
5706
5707 if (pipe != PIPE_A && pipe != PIPE_B)
5708 pipe = intel_dp->pps_pipe;
5709
5710 if (pipe != PIPE_A && pipe != PIPE_B)
5711 pipe = PIPE_A;
5712
5713 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5714 pipe_name(pipe));
01527b31
CT		 5715 }
5716
4f9db5b5 5717 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5718 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5719 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5720
5721 return true;
5722}
5723
16c25533 5724bool
f0fec3f2
PZ		 5725intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5726 struct intel_connector *intel_connector)
a4fc5ed6 5727{
f0fec3f2
PZ		 5728 struct drm_connector *connector = &intel_connector->base;
5729 struct intel_dp *intel_dp = &intel_dig_port->dp;
5730 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5731 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5732 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5733 enum port port = intel_dig_port->port;
0b99836f 5734 int type;
a4fc5ed6 5735
a4a5d2f8
VS		 5736 intel_dp->pps_pipe = INVALID_PIPE;
5737
ec5b01dd 5738 /* intel_dp vfuncs */
b6b5e383
DL		 5739 if (INTEL_INFO(dev)->gen >= 9)
5740 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5741 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5742 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5743 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5744 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5745 else if (HAS_PCH_SPLIT(dev))
5746 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5747 else
5748 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5749
b9ca5fad
DL		 5750 if (INTEL_INFO(dev)->gen >= 9)
5751 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5752 else
5753 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5754
0767935e
DV		 5755 /* Preserve the current hw state. */
5756 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5757 intel_dp->attached_connector = intel_connector;
3d3dc149 5758
3b32a35b 5759 if (intel_dp_is_edp(dev, port))
b329530c 5760 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5761 else
5762 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5763
f7d24902
ID		 5764 /*
5765 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5766 * for DP the encoder type can be set by the caller to
5767 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5768 */
5769 if (type == DRM_MODE_CONNECTOR_eDP)
5770 intel_encoder->type = INTEL_OUTPUT_EDP;
5771
c17ed5b5
VS		 5772 /* eDP only on port B and/or C on vlv/chv */
5773 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5774 port != PORT_B && port != PORT_C))
5775 return false;
5776
e7281eab
ID		 5777 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5778 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5779 port_name(port));
5780
b329530c 5781 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5782 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5783
a4fc5ed6
KP		 5784 connector->interlace_allowed = true;
5785 connector->doublescan_allowed = 0;
5786
f0fec3f2 5787 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5788 edp_panel_vdd_work);
a4fc5ed6 5789
df0e9248 5790 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5791 drm_connector_register(connector);
a4fc5ed6 5792
affa9354 5793 if (HAS_DDI(dev))
bcbc889b
PZ		 5794 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5795 else
5796 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5797 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5798
0b99836f 5799 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5800 switch (port) {
5801 case PORT_A:
1d843f9d 5802 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5803 break;
5804 case PORT_B:
1d843f9d 5805 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5806 break;
5807 case PORT_C:
1d843f9d 5808 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5809 break;
5810 case PORT_D:
1d843f9d 5811 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5812 break;
5813 default:
ad1c0b19 5814 BUG();
5eb08b69
ZW		 5815 }
5816
dada1a9f 5817 if (is_edp(intel_dp)) {
773538e8 5818 pps_lock(intel_dp);
1e74a324
VS		 5819 intel_dp_init_panel_power_timestamps(intel_dp);
5820 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5821 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5822 else
36b5f425 5823 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5824 pps_unlock(intel_dp);
dada1a9f 5825 }
0095e6dc 5826
9d1a1031 5827 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5828
0e32b39c 5829 /* init MST on ports that can support it */
0c9b3715
JN		 5830 if (HAS_DP_MST(dev) &&
5831 (port == PORT_B || port == PORT_C || port == PORT_D))
5832 intel_dp_mst_encoder_init(intel_dig_port,
5833 intel_connector->base.base.id);
0e32b39c 5834
36b5f425 5835 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5836 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5837 if (is_edp(intel_dp)) {
5838 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5839 /*
5840 * vdd might still be enabled do to the delayed vdd off.
5841 * Make sure vdd is actually turned off here.
5842 */
773538e8 5843 pps_lock(intel_dp);
4be73780 5844 edp_panel_vdd_off_sync(intel_dp);
773538e8 5845 pps_unlock(intel_dp);
15b1d171 5846 }
34ea3d38 5847 drm_connector_unregister(connector);
b2f246a8 5848 drm_connector_cleanup(connector);
16c25533 5849 return false;
b2f246a8 5850 }
32f9d658 5851
f684960e
CW		 5852 intel_dp_add_properties(intel_dp, connector);
5853
a4fc5ed6
KP		 5854 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5855 * 0xd. Failure to do so will result in spurious interrupts being
5856 * generated on the port when a cable is not attached.
5857 */
5858 if (IS_G4X(dev) && !IS_GM45(dev)) {
5859 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5860 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5861 }
16c25533 5862
aa7471d2
JN		 5863 i915_debugfs_connector_add(connector);
5864
16c25533 5865 return true;
a4fc5ed6 5866}
f0fec3f2
PZ		 5867
5868void
5869intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5870{
13cf5504 5871 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5872 struct intel_digital_port *intel_dig_port;
5873 struct intel_encoder *intel_encoder;
5874 struct drm_encoder *encoder;
5875 struct intel_connector *intel_connector;
5876
b14c5679 5877 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5878 if (!intel_dig_port)
5879 return;
5880
08d9bc92 5881 intel_connector = intel_connector_alloc();
f0fec3f2
PZ		 5882 if (!intel_connector) {
5883 kfree(intel_dig_port);
5884 return;
5885 }
5886
5887 intel_encoder = &intel_dig_port->base;
5888 encoder = &intel_encoder->base;
5889
5890 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5891 DRM_MODE_ENCODER_TMDS);
5892
5bfe2ac0 5893 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5894 intel_encoder->disable = intel_disable_dp;
00c09d70 5895 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5896 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5897 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5898 if (IS_CHERRYVIEW(dev)) {
9197c88b 5899 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5900 intel_encoder->pre_enable = chv_pre_enable_dp;
5901 intel_encoder->enable = vlv_enable_dp;
580d3811 5902 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5903 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5904 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5905 intel_encoder->pre_enable = vlv_pre_enable_dp;
5906 intel_encoder->enable = vlv_enable_dp;
49277c31 5907 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5908 } else {
ecff4f3b
JN		 5909 intel_encoder->pre_enable = g4x_pre_enable_dp;
5910 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5911 if (INTEL_INFO(dev)->gen >= 5)
5912 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5913 }
f0fec3f2 5914
174edf1f 5915 intel_dig_port->port = port;
f0fec3f2
PZ		 5916 intel_dig_port->dp.output_reg = output_reg;
5917
00c09d70 5918 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5919 if (IS_CHERRYVIEW(dev)) {
5920 if (port == PORT_D)
5921 intel_encoder->crtc_mask = 1 << 2;
5922 else
5923 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5924 } else {
5925 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5926 }
bc079e8b 5927 intel_encoder->cloneable = 0;
f0fec3f2 5928
13cf5504 5929 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5930 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5931
15b1d171
PZ		 5932 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5933 drm_encoder_cleanup(encoder);
5934 kfree(intel_dig_port);
b2f246a8 5935 kfree(intel_connector);
15b1d171 5936 }
f0fec3f2 5937}
0e32b39c
DA		 5938
5939void intel_dp_mst_suspend(struct drm_device *dev)
5940{
5941 struct drm_i915_private *dev_priv = dev->dev_private;
5942 int i;
5943
5944 /* disable MST */
5945 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5946 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5947 if (!intel_dig_port)
5948 continue;
5949
5950 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5951 if (!intel_dig_port->dp.can_mst)
5952 continue;
5953 if (intel_dig_port->dp.is_mst)
5954 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5955 }
5956 }
5957}
5958
5959void intel_dp_mst_resume(struct drm_device *dev)
5960{
5961 struct drm_i915_private *dev_priv = dev->dev_private;
5962 int i;
5963
5964 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5965 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 5966 if (!intel_dig_port)
5967 continue;
5968 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5969 int ret;
5970
5971 if (!intel_dig_port->dp.can_mst)
5972 continue;
5973
5974 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5975 if (ret != 0) {
5976 intel_dp_check_mst_status(&intel_dig_port->dp);
5977 }
5978 }
5979 }
5980}
Linux kernel - Deliverables
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