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Merge remote-tracking branch 'spi/for-next'
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
c19de8eb 193static enum drm_mode_status
a4fc5ed6
KP		 194intel_dp_mode_valid(struct drm_connector *connector,
195 struct drm_display_mode *mode)
196{
df0e9248 197 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 198 struct intel_connector *intel_connector = to_intel_connector(connector);
199 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 200 int target_clock = mode->clock;
201 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 202 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 203
dd06f90e
JN		 204 if (is_edp(intel_dp) && fixed_mode) {
205 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 206 return MODE_PANEL;
207
dd06f90e 208 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 209 return MODE_PANEL;
03afc4a2
DV		 210
211 target_clock = fixed_mode->clock;
7de56f43
ZY		 212 }
213
50fec21a 214 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 215 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 216
217 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
218 mode_rate = intel_dp_link_required(target_clock, 18);
219
799487f5 220 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 221 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 222
223 if (mode->clock < 10000)
224 return MODE_CLOCK_LOW;
225
0af78a2b
DV		 226 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
227 return MODE_H_ILLEGAL;
228
a4fc5ed6
KP		 229 return MODE_OK;
230}
231
a4f1289e 232uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 233{
234 int i;
235 uint32_t v = 0;
236
237 if (src_bytes > 4)
238 src_bytes = 4;
239 for (i = 0; i < src_bytes; i++)
240 v |= ((uint32_t) src[i]) << ((3-i) * 8);
241 return v;
242}
243
c2af70e2 244static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 245{
246 int i;
247 if (dst_bytes > 4)
248 dst_bytes = 4;
249 for (i = 0; i < dst_bytes; i++)
250 dst[i] = src >> ((3-i) * 8);
251}
252
bf13e81b
JN		 253static void
254intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 255 struct intel_dp *intel_dp);
bf13e81b
JN		 256static void
257intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 258 struct intel_dp *intel_dp);
335f752b
ID		 259static void
260intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
bf13e81b 261
773538e8
VS		 262static void pps_lock(struct intel_dp *intel_dp)
263{
264 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
265 struct intel_encoder *encoder = &intel_dig_port->base;
266 struct drm_device *dev = encoder->base.dev;
fac5e23e 267 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 268 enum intel_display_power_domain power_domain;
269
270 /*
271 * See vlv_power_sequencer_reset() why we need
272 * a power domain reference here.
273 */
25f78f58 274 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 275 intel_display_power_get(dev_priv, power_domain);
276
277 mutex_lock(&dev_priv->pps_mutex);
278}
279
280static void pps_unlock(struct intel_dp *intel_dp)
281{
282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct intel_encoder *encoder = &intel_dig_port->base;
284 struct drm_device *dev = encoder->base.dev;
fac5e23e 285 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 286 enum intel_display_power_domain power_domain;
287
288 mutex_unlock(&dev_priv->pps_mutex);
289
25f78f58 290 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 291 intel_display_power_put(dev_priv, power_domain);
292}
293
961a0db0
VS		 294static void
295vlv_power_sequencer_kick(struct intel_dp *intel_dp)
296{
297 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
298 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 299 struct drm_i915_private *dev_priv = to_i915(dev);
961a0db0 300 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 301 bool pll_enabled, release_cl_override = false;
302 enum dpio_phy phy = DPIO_PHY(pipe);
303 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 304 uint32_t DP;
305
306 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
307 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
308 pipe_name(pipe), port_name(intel_dig_port->port)))
309 return;
310
311 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
312 pipe_name(pipe), port_name(intel_dig_port->port));
313
314 /* Preserve the BIOS-computed detected bit. This is
315 * supposed to be read-only.
316 */
317 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
318 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
319 DP |= DP_PORT_WIDTH(1);
320 DP |= DP_LINK_TRAIN_PAT_1;
321
322 if (IS_CHERRYVIEW(dev))
323 DP |= DP_PIPE_SELECT_CHV(pipe);
324 else if (pipe == PIPE_B)
325 DP |= DP_PIPEB_SELECT;
326
d288f65f
VS		 327 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
328
329 /*
330 * The DPLL for the pipe must be enabled for this to work.
331 * So enable temporarily it if it's not already enabled.
332 */
0047eedc
VS		 333 if (!pll_enabled) {
334 release_cl_override = IS_CHERRYVIEW(dev) &&
335 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
336
3f36b937
TU		 337 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
338 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
339 DRM_ERROR("Failed to force on pll for pipe %c!\n",
340 pipe_name(pipe));
341 return;
342 }
0047eedc 343 }
d288f65f 344
961a0db0
VS		 345 /*
346 * Similar magic as in intel_dp_enable_port().
347 * We _must_ do this port enable + disable trick
348 * to make this power seqeuencer lock onto the port.
349 * Otherwise even VDD force bit won't work.
350 */
351 I915_WRITE(intel_dp->output_reg, DP);
352 POSTING_READ(intel_dp->output_reg);
353
354 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
355 POSTING_READ(intel_dp->output_reg);
356
357 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
358 POSTING_READ(intel_dp->output_reg);
d288f65f 359
0047eedc 360 if (!pll_enabled) {
d288f65f 361 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 362
363 if (release_cl_override)
364 chv_phy_powergate_ch(dev_priv, phy, ch, false);
365 }
961a0db0
VS		 366}
367
bf13e81b
JN		 368static enum pipe
369vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
370{
371 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b 372 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 373 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 374 struct intel_encoder *encoder;
375 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 376 enum pipe pipe;
bf13e81b 377
e39b999a 378 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 379
a8c3344e
VS		 380 /* We should never land here with regular DP ports */
381 WARN_ON(!is_edp(intel_dp));
382
a4a5d2f8
VS		 383 if (intel_dp->pps_pipe != INVALID_PIPE)
384 return intel_dp->pps_pipe;
385
386 /*
387 * We don't have power sequencer currently.
388 * Pick one that's not used by other ports.
389 */
19c8054c 390 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 391 struct intel_dp *tmp;
392
393 if (encoder->type != INTEL_OUTPUT_EDP)
394 continue;
395
396 tmp = enc_to_intel_dp(&encoder->base);
397
398 if (tmp->pps_pipe != INVALID_PIPE)
399 pipes &= ~(1 << tmp->pps_pipe);
400 }
401
402 /*
403 * Didn't find one. This should not happen since there
404 * are two power sequencers and up to two eDP ports.
405 */
406 if (WARN_ON(pipes == 0))
a8c3344e
VS		 407 pipe = PIPE_A;
408 else
409 pipe = ffs(pipes) - 1;
a4a5d2f8 410
a8c3344e
VS		 411 vlv_steal_power_sequencer(dev, pipe);
412 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 413
414 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
415 pipe_name(intel_dp->pps_pipe),
416 port_name(intel_dig_port->port));
417
418 /* init power sequencer on this pipe and port */
36b5f425
VS		 419 intel_dp_init_panel_power_sequencer(dev, intel_dp);
420 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 421
961a0db0
VS		 422 /*
423 * Even vdd force doesn't work until we've made
424 * the power sequencer lock in on the port.
425 */
426 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 427
428 return intel_dp->pps_pipe;
429}
430
78597996
ID		 431static int
432bxt_power_sequencer_idx(struct intel_dp *intel_dp)
433{
434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 436 struct drm_i915_private *dev_priv = to_i915(dev);
78597996
ID		 437
438 lockdep_assert_held(&dev_priv->pps_mutex);
439
440 /* We should never land here with regular DP ports */
441 WARN_ON(!is_edp(intel_dp));
442
443 /*
444 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
445 * mapping needs to be retrieved from VBT, for now just hard-code to
446 * use instance #0 always.
447 */
448 if (!intel_dp->pps_reset)
449 return 0;
450
451 intel_dp->pps_reset = false;
452
453 /*
454 * Only the HW needs to be reprogrammed, the SW state is fixed and
455 * has been setup during connector init.
456 */
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
458
459 return 0;
460}
461
6491ab27
VS		 462typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
463 enum pipe pipe);
464
465static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
466 enum pipe pipe)
467{
44cb734c 468 return I915_READ(PP_STATUS(pipe)) & PP_ON;
6491ab27
VS		 469}
470
471static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
472 enum pipe pipe)
473{
44cb734c 474 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
6491ab27
VS		 475}
476
477static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
478 enum pipe pipe)
479{
480 return true;
481}
bf13e81b 482
a4a5d2f8 483static enum pipe
6491ab27
VS		 484vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
485 enum port port,
486 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 487{
488 enum pipe pipe;
bf13e81b 489
bf13e81b 490 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
44cb734c 491 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
bf13e81b 492 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 493
494 if (port_sel != PANEL_PORT_SELECT_VLV(port))
495 continue;
496
6491ab27
VS		 497 if (!pipe_check(dev_priv, pipe))
498 continue;
499
a4a5d2f8 500 return pipe;
bf13e81b
JN		 501 }
502
a4a5d2f8
VS		 503 return INVALID_PIPE;
504}
505
506static void
507vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
508{
509 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
510 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 511 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 512 enum port port = intel_dig_port->port;
513
514 lockdep_assert_held(&dev_priv->pps_mutex);
515
516 /* try to find a pipe with this port selected */
6491ab27
VS		 517 /* first pick one where the panel is on */
518 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
519 vlv_pipe_has_pp_on);
520 /* didn't find one? pick one where vdd is on */
521 if (intel_dp->pps_pipe == INVALID_PIPE)
522 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
523 vlv_pipe_has_vdd_on);
524 /* didn't find one? pick one with just the correct port */
525 if (intel_dp->pps_pipe == INVALID_PIPE)
526 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
527 vlv_pipe_any);
a4a5d2f8
VS		 528
529 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
530 if (intel_dp->pps_pipe == INVALID_PIPE) {
531 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
532 port_name(port));
533 return;
bf13e81b
JN		 534 }
535
a4a5d2f8
VS		 536 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
537 port_name(port), pipe_name(intel_dp->pps_pipe));
538
36b5f425
VS		 539 intel_dp_init_panel_power_sequencer(dev, intel_dp);
540 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 541}
542
78597996 543void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8 544{
91c8a326 545 struct drm_device *dev = &dev_priv->drm;
773538e8
VS		 546 struct intel_encoder *encoder;
547
78597996
ID		 548 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
549 !IS_BROXTON(dev)))
773538e8
VS		 550 return;
551
552 /*
553 * We can't grab pps_mutex here due to deadlock with power_domain
554 * mutex when power_domain functions are called while holding pps_mutex.
555 * That also means that in order to use pps_pipe the code needs to
556 * hold both a power domain reference and pps_mutex, and the power domain
557 * reference get/put must be done while _not_ holding pps_mutex.
558 * pps_{lock,unlock}() do these steps in the correct order, so one
559 * should use them always.
560 */
561
19c8054c 562 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 563 struct intel_dp *intel_dp;
564
565 if (encoder->type != INTEL_OUTPUT_EDP)
566 continue;
567
568 intel_dp = enc_to_intel_dp(&encoder->base);
78597996
ID		 569 if (IS_BROXTON(dev))
570 intel_dp->pps_reset = true;
571 else
572 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 573 }
bf13e81b
JN		 574}
575
8e8232d5
ID		 576struct pps_registers {
577 i915_reg_t pp_ctrl;
578 i915_reg_t pp_stat;
579 i915_reg_t pp_on;
580 i915_reg_t pp_off;
581 i915_reg_t pp_div;
582};
583
584static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
585 struct intel_dp *intel_dp,
586 struct pps_registers *regs)
587{
44cb734c
ID		 588 int pps_idx = 0;
589
8e8232d5
ID		 590 memset(regs, 0, sizeof(*regs));
591
44cb734c
ID		 592 if (IS_BROXTON(dev_priv))
593 pps_idx = bxt_power_sequencer_idx(intel_dp);
594 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
595 pps_idx = vlv_power_sequencer_pipe(intel_dp);
8e8232d5 596
44cb734c
ID		 597 regs->pp_ctrl = PP_CONTROL(pps_idx);
598 regs->pp_stat = PP_STATUS(pps_idx);
599 regs->pp_on = PP_ON_DELAYS(pps_idx);
600 regs->pp_off = PP_OFF_DELAYS(pps_idx);
601 if (!IS_BROXTON(dev_priv))
602 regs->pp_div = PP_DIVISOR(pps_idx);
8e8232d5
ID		 603}
604
f0f59a00
VS		 605static i915_reg_t
606_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 607{
8e8232d5 608 struct pps_registers regs;
bf13e81b 609
8e8232d5
ID		 610 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
611 &regs);
612
613 return regs.pp_ctrl;
bf13e81b
JN		 614}
615
f0f59a00
VS		 616static i915_reg_t
617_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 618{
8e8232d5 619 struct pps_registers regs;
bf13e81b 620
8e8232d5
ID		 621 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
622 &regs);
623
624 return regs.pp_stat;
bf13e81b
JN		 625}
626
01527b31
CT		 627/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
628 This function only applicable when panel PM state is not to be tracked */
629static int edp_notify_handler(struct notifier_block *this, unsigned long code,
630 void *unused)
631{
632 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
633 edp_notifier);
634 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 635 struct drm_i915_private *dev_priv = to_i915(dev);
01527b31
CT		 636
637 if (!is_edp(intel_dp) || code != SYS_RESTART)
638 return 0;
639
773538e8 640 pps_lock(intel_dp);
e39b999a 641
666a4537 642 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 643 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 644 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 645 u32 pp_div;
e39b999a 646
44cb734c
ID		 647 pp_ctrl_reg = PP_CONTROL(pipe);
648 pp_div_reg = PP_DIVISOR(pipe);
01527b31
CT		 649 pp_div = I915_READ(pp_div_reg);
650 pp_div &= PP_REFERENCE_DIVIDER_MASK;
651
652 /* 0x1F write to PP_DIV_REG sets max cycle delay */
653 I915_WRITE(pp_div_reg, pp_div | 0x1F);
654 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
655 msleep(intel_dp->panel_power_cycle_delay);
656 }
657
773538e8 658 pps_unlock(intel_dp);
e39b999a 659
01527b31
CT		 660 return 0;
661}
662
4be73780 663static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 664{
30add22d 665 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 666 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 667
e39b999a
VS		 668 lockdep_assert_held(&dev_priv->pps_mutex);
669
666a4537 670 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 671 intel_dp->pps_pipe == INVALID_PIPE)
672 return false;
673
bf13e81b 674 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 675}
676
4be73780 677static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 678{
30add22d 679 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 680 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 681
e39b999a
VS		 682 lockdep_assert_held(&dev_priv->pps_mutex);
683
666a4537 684 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 685 intel_dp->pps_pipe == INVALID_PIPE)
686 return false;
687
773538e8 688 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 689}
690
9b984dae
KP		 691static void
692intel_dp_check_edp(struct intel_dp *intel_dp)
693{
30add22d 694 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 695 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 696
9b984dae
KP		 697 if (!is_edp(intel_dp))
698 return;
453c5420 699
4be73780 700 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 701 WARN(1, "eDP powered off while attempting aux channel communication.\n");
702 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 703 I915_READ(_pp_stat_reg(intel_dp)),
704 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 705 }
706}
707
9ee32fea
DV		 708static uint32_t
709intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
710{
711 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
712 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 713 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 714 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 715 uint32_t status;
716 bool done;
717
ef04f00d 718#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 719 if (has_aux_irq)
b18ac466 720 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 721 msecs_to_jiffies_timeout(10));
9ee32fea 722 else
713a6b66 723 done = wait_for(C, 10) == 0;
9ee32fea
DV		 724 if (!done)
725 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
726 has_aux_irq);
727#undef C
728
729 return status;
730}
731
6ffb1be7 732static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 733{
174edf1f 734 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 735 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 736
a457f54b
VS		 737 if (index)
738 return 0;
739
ec5b01dd
DL		 740 /*
741 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 742 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 743 */
a457f54b 744 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 745}
746
747static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
748{
749 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 750 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 751
752 if (index)
753 return 0;
754
a457f54b
VS		 755 /*
756 * The clock divider is based off the cdclk or PCH rawclk, and would
757 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
758 * divide by 2000 and use that
759 */
e7dc33f3 760 if (intel_dig_port->port == PORT_A)
fce18c4c 761 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 762 else
763 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 764}
765
766static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
767{
768 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 769 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 770
a457f54b 771 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 772 /* Workaround for non-ULT HSW */
bc86625a
CW		 773 switch (index) {
774 case 0: return 63;
775 case 1: return 72;
776 default: return 0;
777 }
2c55c336 778 }
a457f54b
VS		 779
780 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 781}
782
b6b5e383
DL		 783static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
784{
785 /*
786 * SKL doesn't need us to program the AUX clock divider (Hardware will
787 * derive the clock from CDCLK automatically). We still implement the
788 * get_aux_clock_divider vfunc to plug-in into the existing code.
789 */
790 return index ? 0 : 1;
791}
792
6ffb1be7
VS		 793static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
794 bool has_aux_irq,
795 int send_bytes,
796 uint32_t aux_clock_divider)
5ed12a19
DL		 797{
798 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
799 struct drm_device *dev = intel_dig_port->base.base.dev;
800 uint32_t precharge, timeout;
801
802 if (IS_GEN6(dev))
803 precharge = 3;
804 else
805 precharge = 5;
806
f3c6a3a7 807 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 808 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
809 else
810 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
811
812 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 813 DP_AUX_CH_CTL_DONE |
5ed12a19 814 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 815 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 816 timeout |
788d4433 817 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 818 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
819 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 820 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 821}
822
b9ca5fad
DL		 823static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
824 bool has_aux_irq,
825 int send_bytes,
826 uint32_t unused)
827{
828 return DP_AUX_CH_CTL_SEND_BUSY |
829 DP_AUX_CH_CTL_DONE |
830 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
831 DP_AUX_CH_CTL_TIME_OUT_ERROR |
832 DP_AUX_CH_CTL_TIME_OUT_1600us |
833 DP_AUX_CH_CTL_RECEIVE_ERROR |
834 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
d4dcbdce 835 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
b9ca5fad
DL		 836 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
837}
838
b84a1cf8
RV		 839static int
840intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 841 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 842 uint8_t *recv, int recv_size)
843{
844 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
845 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 846 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 847 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 848 uint32_t aux_clock_divider;
b84a1cf8
RV		 849 int i, ret, recv_bytes;
850 uint32_t status;
5ed12a19 851 int try, clock = 0;
4e6b788c 852 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 853 bool vdd;
854
773538e8 855 pps_lock(intel_dp);
e39b999a 856
72c3500a
VS		 857 /*
858 * We will be called with VDD already enabled for dpcd/edid/oui reads.
859 * In such cases we want to leave VDD enabled and it's up to upper layers
860 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
861 * ourselves.
862 */
1e0560e0 863 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 864
865 /* dp aux is extremely sensitive to irq latency, hence request the
866 * lowest possible wakeup latency and so prevent the cpu from going into
867 * deep sleep states.
868 */
869 pm_qos_update_request(&dev_priv->pm_qos, 0);
870
871 intel_dp_check_edp(intel_dp);
5eb08b69 872
11bee43e
JB		 873 /* Try to wait for any previous AUX channel activity */
874 for (try = 0; try < 3; try++) {
ef04f00d 875 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 876 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
877 break;
878 msleep(1);
879 }
880
881 if (try == 3) {
02196c77
MK		 882 static u32 last_status = -1;
883 const u32 status = I915_READ(ch_ctl);
884
885 if (status != last_status) {
886 WARN(1, "dp_aux_ch not started status 0x%08x\n",
887 status);
888 last_status = status;
889 }
890
9ee32fea
DV		 891 ret = -EBUSY;
892 goto out;
4f7f7b7e
CW		 893 }
894
46a5ae9f
PZ		 895 /* Only 5 data registers! */
896 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
897 ret = -E2BIG;
898 goto out;
899 }
900
ec5b01dd 901 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 902 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
903 has_aux_irq,
904 send_bytes,
905 aux_clock_divider);
5ed12a19 906
bc86625a
CW		 907 /* Must try at least 3 times according to DP spec */
908 for (try = 0; try < 5; try++) {
909 /* Load the send data into the aux channel data registers */
910 for (i = 0; i < send_bytes; i += 4)
330e20ec 911 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 912 intel_dp_pack_aux(send + i,
913 send_bytes - i));
bc86625a
CW		 914
915 /* Send the command and wait for it to complete */
5ed12a19 916 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 917
918 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
919
920 /* Clear done status and any errors */
921 I915_WRITE(ch_ctl,
922 status |
923 DP_AUX_CH_CTL_DONE |
924 DP_AUX_CH_CTL_TIME_OUT_ERROR |
925 DP_AUX_CH_CTL_RECEIVE_ERROR);
926
74ebf294 927 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 928 continue;
74ebf294
TP		 929
930 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
931 * 400us delay required for errors and timeouts
932 * Timeout errors from the HW already meet this
933 * requirement so skip to next iteration
934 */
935 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
936 usleep_range(400, 500);
bc86625a 937 continue;
74ebf294 938 }
bc86625a 939 if (status & DP_AUX_CH_CTL_DONE)
e058c945 940 goto done;
bc86625a 941 }
a4fc5ed6
KP		 942 }
943
a4fc5ed6 944 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 945 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 946 ret = -EBUSY;
947 goto out;
a4fc5ed6
KP		 948 }
949
e058c945 950done:
a4fc5ed6
KP		 951 /* Check for timeout or receive error.
952 * Timeouts occur when the sink is not connected
953 */
a5b3da54 954 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 955 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 956 ret = -EIO;
957 goto out;
a5b3da54 958 }
1ae8c0a5
KP		 959
960 /* Timeouts occur when the device isn't connected, so they're
961 * "normal" -- don't fill the kernel log with these */
a5b3da54 962 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 963 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 964 ret = -ETIMEDOUT;
965 goto out;
a4fc5ed6
KP		 966 }
967
968 /* Unload any bytes sent back from the other side */
969 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
970 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 971
972 /*
973 * By BSpec: "Message sizes of 0 or >20 are not allowed."
974 * We have no idea of what happened so we return -EBUSY so
975 * drm layer takes care for the necessary retries.
976 */
977 if (recv_bytes == 0 || recv_bytes > 20) {
978 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
979 recv_bytes);
980 /*
981 * FIXME: This patch was created on top of a series that
982 * organize the retries at drm level. There EBUSY should
983 * also take care for 1ms wait before retrying.
984 * That aux retries re-org is still needed and after that is
985 * merged we remove this sleep from here.
986 */
987 usleep_range(1000, 1500);
988 ret = -EBUSY;
989 goto out;
990 }
991
a4fc5ed6
KP		 992 if (recv_bytes > recv_size)
993 recv_bytes = recv_size;
0206e353 994
4f7f7b7e 995 for (i = 0; i < recv_bytes; i += 4)
330e20ec 996 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 997 recv + i, recv_bytes - i);
a4fc5ed6 998
9ee32fea
DV		 999 ret = recv_bytes;
1000out:
1001 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1002
884f19e9
JN		 1003 if (vdd)
1004 edp_panel_vdd_off(intel_dp, false);
1005
773538e8 1006 pps_unlock(intel_dp);
e39b999a 1007
9ee32fea 1008 return ret;
a4fc5ed6
KP		 1009}
1010
a6c8aff0
JN		 1011#define BARE_ADDRESS_SIZE 3
1012#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 1013static ssize_t
1014intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1015{
9d1a1031
JN		 1016 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1017 uint8_t txbuf[20], rxbuf[20];
1018 size_t txsize, rxsize;
a4fc5ed6 1019 int ret;
a4fc5ed6 1020
d2d9cbbd
VS		 1021 txbuf[0] = (msg->request << 4) |
1022 ((msg->address >> 16) & 0xf);
1023 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 1024 txbuf[2] = msg->address & 0xff;
1025 txbuf[3] = msg->size - 1;
46a5ae9f 1026
9d1a1031
JN		 1027 switch (msg->request & ~DP_AUX_I2C_MOT) {
1028 case DP_AUX_NATIVE_WRITE:
1029 case DP_AUX_I2C_WRITE:
c1e74122 1030 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1031 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1032 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1033
9d1a1031
JN		 1034 if (WARN_ON(txsize > 20))
1035 return -E2BIG;
a4fc5ed6 1036
dd788090
VS		 1037 WARN_ON(!msg->buffer != !msg->size);
1038
d81a67cc
ID		 1039 if (msg->buffer)
1040 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 1041
9d1a1031
JN		 1042 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1043 if (ret > 0) {
1044 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1045
a1ddefd8
JN		 1046 if (ret > 1) {
1047 /* Number of bytes written in a short write. */
1048 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1049 } else {
1050 /* Return payload size. */
1051 ret = msg->size;
1052 }
9d1a1031
JN		 1053 }
1054 break;
46a5ae9f 1055
9d1a1031
JN		 1056 case DP_AUX_NATIVE_READ:
1057 case DP_AUX_I2C_READ:
a6c8aff0 1058 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1059 rxsize = msg->size + 1;
a4fc5ed6 1060
9d1a1031
JN		 1061 if (WARN_ON(rxsize > 20))
1062 return -E2BIG;
a4fc5ed6 1063
9d1a1031
JN		 1064 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1065 if (ret > 0) {
1066 msg->reply = rxbuf[0] >> 4;
1067 /*
1068 * Assume happy day, and copy the data. The caller is
1069 * expected to check msg->reply before touching it.
1070 *
1071 * Return payload size.
1072 */
1073 ret--;
1074 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1075 }
9d1a1031
JN		 1076 break;
1077
1078 default:
1079 ret = -EINVAL;
1080 break;
a4fc5ed6 1081 }
f51a44b9 1082
9d1a1031 1083 return ret;
a4fc5ed6
KP		 1084}
1085
f0f59a00
VS		 1086static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1087 enum port port)
da00bdcf
VS		 1088{
1089 switch (port) {
1090 case PORT_B:
1091 case PORT_C:
1092 case PORT_D:
1093 return DP_AUX_CH_CTL(port);
1094 default:
1095 MISSING_CASE(port);
1096 return DP_AUX_CH_CTL(PORT_B);
1097 }
1098}
1099
f0f59a00
VS		 1100static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1101 enum port port, int index)
330e20ec
VS		 1102{
1103 switch (port) {
1104 case PORT_B:
1105 case PORT_C:
1106 case PORT_D:
1107 return DP_AUX_CH_DATA(port, index);
1108 default:
1109 MISSING_CASE(port);
1110 return DP_AUX_CH_DATA(PORT_B, index);
1111 }
1112}
1113
f0f59a00
VS		 1114static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1115 enum port port)
da00bdcf
VS		 1116{
1117 switch (port) {
1118 case PORT_A:
1119 return DP_AUX_CH_CTL(port);
1120 case PORT_B:
1121 case PORT_C:
1122 case PORT_D:
1123 return PCH_DP_AUX_CH_CTL(port);
1124 default:
1125 MISSING_CASE(port);
1126 return DP_AUX_CH_CTL(PORT_A);
1127 }
1128}
1129
f0f59a00
VS		 1130static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1131 enum port port, int index)
330e20ec
VS		 1132{
1133 switch (port) {
1134 case PORT_A:
1135 return DP_AUX_CH_DATA(port, index);
1136 case PORT_B:
1137 case PORT_C:
1138 case PORT_D:
1139 return PCH_DP_AUX_CH_DATA(port, index);
1140 default:
1141 MISSING_CASE(port);
1142 return DP_AUX_CH_DATA(PORT_A, index);
1143 }
1144}
1145
da00bdcf
VS		 1146/*
1147 * On SKL we don't have Aux for port E so we rely
1148 * on VBT to set a proper alternate aux channel.
1149 */
1150static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1151{
1152 const struct ddi_vbt_port_info *info =
1153 &dev_priv->vbt.ddi_port_info[PORT_E];
1154
1155 switch (info->alternate_aux_channel) {
1156 case DP_AUX_A:
1157 return PORT_A;
1158 case DP_AUX_B:
1159 return PORT_B;
1160 case DP_AUX_C:
1161 return PORT_C;
1162 case DP_AUX_D:
1163 return PORT_D;
1164 default:
1165 MISSING_CASE(info->alternate_aux_channel);
1166 return PORT_A;
1167 }
1168}
1169
f0f59a00
VS		 1170static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1171 enum port port)
da00bdcf
VS		 1172{
1173 if (port == PORT_E)
1174 port = skl_porte_aux_port(dev_priv);
1175
1176 switch (port) {
1177 case PORT_A:
1178 case PORT_B:
1179 case PORT_C:
1180 case PORT_D:
1181 return DP_AUX_CH_CTL(port);
1182 default:
1183 MISSING_CASE(port);
1184 return DP_AUX_CH_CTL(PORT_A);
1185 }
1186}
1187
f0f59a00
VS		 1188static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1189 enum port port, int index)
330e20ec
VS		 1190{
1191 if (port == PORT_E)
1192 port = skl_porte_aux_port(dev_priv);
1193
1194 switch (port) {
1195 case PORT_A:
1196 case PORT_B:
1197 case PORT_C:
1198 case PORT_D:
1199 return DP_AUX_CH_DATA(port, index);
1200 default:
1201 MISSING_CASE(port);
1202 return DP_AUX_CH_DATA(PORT_A, index);
1203 }
1204}
1205
f0f59a00
VS		 1206static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1207 enum port port)
330e20ec
VS		 1208{
1209 if (INTEL_INFO(dev_priv)->gen >= 9)
1210 return skl_aux_ctl_reg(dev_priv, port);
1211 else if (HAS_PCH_SPLIT(dev_priv))
1212 return ilk_aux_ctl_reg(dev_priv, port);
1213 else
1214 return g4x_aux_ctl_reg(dev_priv, port);
1215}
1216
f0f59a00
VS		 1217static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1218 enum port port, int index)
330e20ec
VS		 1219{
1220 if (INTEL_INFO(dev_priv)->gen >= 9)
1221 return skl_aux_data_reg(dev_priv, port, index);
1222 else if (HAS_PCH_SPLIT(dev_priv))
1223 return ilk_aux_data_reg(dev_priv, port, index);
1224 else
1225 return g4x_aux_data_reg(dev_priv, port, index);
1226}
1227
1228static void intel_aux_reg_init(struct intel_dp *intel_dp)
1229{
1230 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1231 enum port port = dp_to_dig_port(intel_dp)->port;
1232 int i;
1233
1234 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1235 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1236 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1237}
1238
9d1a1031 1239static void
a121f4e5
VS		 1240intel_dp_aux_fini(struct intel_dp *intel_dp)
1241{
a121f4e5
VS		 1242 kfree(intel_dp->aux.name);
1243}
1244
7a418e34 1245static void
9d1a1031
JN		 1246intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1247{
33ad6626
JN		 1248 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1249 enum port port = intel_dig_port->port;
ab2c0672 1250
330e20ec 1251 intel_aux_reg_init(intel_dp);
7a418e34 1252 drm_dp_aux_init(&intel_dp->aux);
8316f337 1253
7a418e34 1254 /* Failure to allocate our preferred name is not critical */
a121f4e5 1255 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
9d1a1031 1256 intel_dp->aux.transfer = intel_dp_aux_transfer;
a4fc5ed6
KP		 1257}
1258
fc0f8e25 1259static int
12f6a2e2 1260intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1261{
94ca719e
VS		 1262 if (intel_dp->num_sink_rates) {
1263 *sink_rates = intel_dp->sink_rates;
1264 return intel_dp->num_sink_rates;
fc0f8e25 1265 }
12f6a2e2
VS		 1266
1267 *sink_rates = default_rates;
1268
1269 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1270}
1271
e588fa18 1272bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1273{
e588fa18
ACO		 1274 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1275 struct drm_device *dev = dig_port->base.base.dev;
1276
ed63baaf 1277 /* WaDisableHBR2:skl */
e87a005d 1278 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1279 return false;
1280
1281 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1282 (INTEL_INFO(dev)->gen >= 9))
1283 return true;
1284 else
1285 return false;
1286}
1287
a8f3ef61 1288static int
e588fa18 1289intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1290{
e588fa18
ACO		 1291 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1292 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1293 int size;
1294
64987fc5
SJ		 1295 if (IS_BROXTON(dev)) {
1296 *source_rates = bxt_rates;
af7080f5 1297 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1298 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1299 *source_rates = skl_rates;
af7080f5
TS		 1300 size = ARRAY_SIZE(skl_rates);
1301 } else {
1302 *source_rates = default_rates;
1303 size = ARRAY_SIZE(default_rates);
a8f3ef61 1304 }
636280ba 1305
ed63baaf 1306 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1307 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1308 size--;
636280ba 1309
af7080f5 1310 return size;
a8f3ef61
SJ		 1311}
1312
c6bb3538
DV		 1313static void
1314intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1315 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1316{
1317 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1318 const struct dp_link_dpll *divisor = NULL;
1319 int i, count = 0;
c6bb3538
DV		 1320
1321 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1322 divisor = gen4_dpll;
1323 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1324 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1325 divisor = pch_dpll;
1326 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1327 } else if (IS_CHERRYVIEW(dev)) {
1328 divisor = chv_dpll;
1329 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1330 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1331 divisor = vlv_dpll;
1332 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1333 }
9dd4ffdf
CML		 1334
1335 if (divisor && count) {
1336 for (i = 0; i < count; i++) {
840b32b7 1337 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1338 pipe_config->dpll = divisor[i].dpll;
1339 pipe_config->clock_set = true;
1340 break;
1341 }
1342 }
c6bb3538
DV		 1343 }
1344}
1345
2ecae76a
VS		 1346static int intersect_rates(const int *source_rates, int source_len,
1347 const int *sink_rates, int sink_len,
94ca719e 1348 int *common_rates)
a8f3ef61
SJ		 1349{
1350 int i = 0, j = 0, k = 0;
1351
a8f3ef61
SJ		 1352 while (i < source_len && j < sink_len) {
1353 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1354 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1355 return k;
94ca719e 1356 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1357 ++k;
1358 ++i;
1359 ++j;
1360 } else if (source_rates[i] < sink_rates[j]) {
1361 ++i;
1362 } else {
1363 ++j;
1364 }
1365 }
1366 return k;
1367}
1368
94ca719e
VS		 1369static int intel_dp_common_rates(struct intel_dp *intel_dp,
1370 int *common_rates)
2ecae76a 1371{
2ecae76a
VS		 1372 const int *source_rates, *sink_rates;
1373 int source_len, sink_len;
1374
1375 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1376 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1377
1378 return intersect_rates(source_rates, source_len,
1379 sink_rates, sink_len,
94ca719e 1380 common_rates);
2ecae76a
VS		 1381}
1382
0336400e
VS		 1383static void snprintf_int_array(char *str, size_t len,
1384 const int *array, int nelem)
1385{
1386 int i;
1387
1388 str[0] = '\0';
1389
1390 for (i = 0; i < nelem; i++) {
b2f505be 1391 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1392 if (r >= len)
1393 return;
1394 str += r;
1395 len -= r;
1396 }
1397}
1398
1399static void intel_dp_print_rates(struct intel_dp *intel_dp)
1400{
0336400e 1401 const int *source_rates, *sink_rates;
94ca719e
VS		 1402 int source_len, sink_len, common_len;
1403 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1404 char str[128]; /* FIXME: too big for stack? */
1405
1406 if ((drm_debug & DRM_UT_KMS) == 0)
1407 return;
1408
e588fa18 1409 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1410 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1411 DRM_DEBUG_KMS("source rates: %s\n", str);
1412
1413 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1414 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1415 DRM_DEBUG_KMS("sink rates: %s\n", str);
1416
94ca719e
VS		 1417 common_len = intel_dp_common_rates(intel_dp, common_rates);
1418 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1419 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1420}
1421
f4896f15 1422static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1423{
1424 int i = 0;
1425
1426 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1427 if (find == rates[i])
1428 break;
1429
1430 return i;
1431}
1432
50fec21a
VS		 1433int
1434intel_dp_max_link_rate(struct intel_dp *intel_dp)
1435{
1436 int rates[DP_MAX_SUPPORTED_RATES] = {};
1437 int len;
1438
94ca719e 1439 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1440 if (WARN_ON(len <= 0))
1441 return 162000;
1442
1354f734 1443 return rates[len - 1];
50fec21a
VS		 1444}
1445
ed4e9c1d
VS		 1446int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1447{
94ca719e 1448 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1449}
1450
94223d04
ACO		 1451void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1452 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1453{
1454 if (intel_dp->num_sink_rates) {
1455 *link_bw = 0;
1456 *rate_select =
1457 intel_dp_rate_select(intel_dp, port_clock);
1458 } else {
1459 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1460 *rate_select = 0;
1461 }
1462}
1463
00c09d70 1464bool
5bfe2ac0 1465intel_dp_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1466 struct intel_crtc_state *pipe_config,
1467 struct drm_connector_state *conn_state)
a4fc5ed6 1468{
5bfe2ac0 1469 struct drm_device *dev = encoder->base.dev;
fac5e23e 1470 struct drm_i915_private *dev_priv = to_i915(dev);
2d112de7 1471 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1472 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1473 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1474 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1475 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1476 int lane_count, clock;
56071a20 1477 int min_lane_count = 1;
eeb6324d 1478 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1479 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1480 int min_clock = 0;
a8f3ef61 1481 int max_clock;
083f9560 1482 int bpp, mode_rate;
ff9a6750 1483 int link_avail, link_clock;
94ca719e
VS		 1484 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1485 int common_len;
04a60f9f 1486 uint8_t link_bw, rate_select;
a8f3ef61 1487
94ca719e 1488 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1489
1490 /* No common link rates between source and sink */
94ca719e 1491 WARN_ON(common_len <= 0);
a8f3ef61 1492
94ca719e 1493 max_clock = common_len - 1;
a4fc5ed6 1494
bc7d38a4 1495 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1496 pipe_config->has_pch_encoder = true;
1497
f769cd24 1498 pipe_config->has_drrs = false;
9fcb1704 1499 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1500
dd06f90e
JN		 1501 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1502 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1503 adjusted_mode);
a1b2278e
CK		 1504
1505 if (INTEL_INFO(dev)->gen >= 9) {
1506 int ret;
e435d6e5 1507 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1508 if (ret)
1509 return ret;
1510 }
1511
b5667627 1512 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1513 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1514 intel_connector->panel.fitting_mode);
1515 else
b074cec8
JB		 1516 intel_pch_panel_fitting(intel_crtc, pipe_config,
1517 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1518 }
1519
cb1793ce 1520 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1521 return false;
1522
083f9560 1523 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1524 "max bw %d pixel clock %iKHz\n",
94ca719e 1525 max_lane_count, common_rates[max_clock],
241bfc38 1526 adjusted_mode->crtc_clock);
083f9560 1527
36008365
DV		 1528 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1529 * bpc in between. */
3e7ca985 1530 bpp = pipe_config->pipe_bpp;
56071a20 1531 if (is_edp(intel_dp)) {
22ce5628
TS		 1532
1533 /* Get bpp from vbt only for panels that dont have bpp in edid */
1534 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1535 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1536 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1537 dev_priv->vbt.edp.bpp);
1538 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1539 }
1540
344c5bbc
JN		 1541 /*
1542 * Use the maximum clock and number of lanes the eDP panel
1543 * advertizes being capable of. The panels are generally
1544 * designed to support only a single clock and lane
1545 * configuration, and typically these values correspond to the
1546 * native resolution of the panel.
1547 */
1548 min_lane_count = max_lane_count;
1549 min_clock = max_clock;
7984211e 1550 }
657445fe 1551
36008365 1552 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1553 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1554 bpp);
36008365 1555
c6930992 1556 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1557 for (lane_count = min_lane_count;
1558 lane_count <= max_lane_count;
1559 lane_count <<= 1) {
1560
94ca719e 1561 link_clock = common_rates[clock];
36008365
DV		 1562 link_avail = intel_dp_max_data_rate(link_clock,
1563 lane_count);
1564
1565 if (mode_rate <= link_avail) {
1566 goto found;
1567 }
1568 }
1569 }
1570 }
c4867936 1571
36008365 1572 return false;
3685a8f3 1573
36008365 1574found:
55bc60db
VS		 1575 if (intel_dp->color_range_auto) {
1576 /*
1577 * See:
1578 * CEA-861-E - 5.1 Default Encoding Parameters
1579 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1580 */
0f2a2a75
VS		 1581 pipe_config->limited_color_range =
1582 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1583 } else {
1584 pipe_config->limited_color_range =
1585 intel_dp->limited_color_range;
55bc60db
VS		 1586 }
1587
90a6b7b0 1588 pipe_config->lane_count = lane_count;
a8f3ef61 1589
657445fe 1590 pipe_config->pipe_bpp = bpp;
94ca719e 1591 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1592
04a60f9f
VS		 1593 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1594 &link_bw, &rate_select);
1595
1596 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1597 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1598 pipe_config->port_clock, bpp);
36008365
DV		 1599 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1600 mode_rate, link_avail);
a4fc5ed6 1601
03afc4a2 1602 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1603 adjusted_mode->crtc_clock,
1604 pipe_config->port_clock,
03afc4a2 1605 &pipe_config->dp_m_n);
9d1a455b 1606
439d7ac0 1607 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1608 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1609 pipe_config->has_drrs = true;
439d7ac0
PB		 1610 intel_link_compute_m_n(bpp, lane_count,
1611 intel_connector->panel.downclock_mode->clock,
1612 pipe_config->port_clock,
1613 &pipe_config->dp_m2_n2);
1614 }
1615
14d41b3b
VS		 1616 /*
1617 * DPLL0 VCO may need to be adjusted to get the correct
1618 * clock for eDP. This will affect cdclk as well.
1619 */
1620 if (is_edp(intel_dp) &&
1621 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1622 int vco;
1623
1624 switch (pipe_config->port_clock / 2) {
1625 case 108000:
1626 case 216000:
63911d72 1627 vco = 8640000;
14d41b3b
VS		 1628 break;
1629 default:
63911d72 1630 vco = 8100000;
14d41b3b
VS		 1631 break;
1632 }
1633
1634 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1635 }
1636
a3c988ea 1637 if (!HAS_DDI(dev))
840b32b7 1638 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1639
03afc4a2 1640 return true;
a4fc5ed6
KP		 1641}
1642
901c2daf 1643void intel_dp_set_link_params(struct intel_dp *intel_dp,
dfa10480
ACO		 1644 int link_rate, uint8_t lane_count,
1645 bool link_mst)
901c2daf 1646{
dfa10480
ACO		 1647 intel_dp->link_rate = link_rate;
1648 intel_dp->lane_count = lane_count;
1649 intel_dp->link_mst = link_mst;
901c2daf
VS		 1650}
1651
85cb48a1
ML		 1652static void intel_dp_prepare(struct intel_encoder *encoder,
1653 struct intel_crtc_state *pipe_config)
a4fc5ed6 1654{
b934223d 1655 struct drm_device *dev = encoder->base.dev;
fac5e23e 1656 struct drm_i915_private *dev_priv = to_i915(dev);
b934223d 1657 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1658 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1659 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
85cb48a1 1660 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
a4fc5ed6 1661
dfa10480
ACO		 1662 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1663 pipe_config->lane_count,
1664 intel_crtc_has_type(pipe_config,
1665 INTEL_OUTPUT_DP_MST));
901c2daf 1666
417e822d 1667 /*
1a2eb460 1668 * There are four kinds of DP registers:
417e822d
KP		 1669 *
1670 * IBX PCH
1a2eb460
KP		 1671 * SNB CPU
1672 * IVB CPU
417e822d
KP		 1673 * CPT PCH
1674 *
1675 * IBX PCH and CPU are the same for almost everything,
1676 * except that the CPU DP PLL is configured in this
1677 * register
1678 *
1679 * CPT PCH is quite different, having many bits moved
1680 * to the TRANS_DP_CTL register instead. That
1681 * configuration happens (oddly) in ironlake_pch_enable
1682 */
9c9e7927 1683
417e822d
KP		 1684 /* Preserve the BIOS-computed detected bit. This is
1685 * supposed to be read-only.
1686 */
1687 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1688
417e822d 1689 /* Handle DP bits in common between all three register formats */
417e822d 1690 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
85cb48a1 1691 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
a4fc5ed6 1692
417e822d 1693 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1694
39e5fa88 1695 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1696 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1697 intel_dp->DP |= DP_SYNC_HS_HIGH;
1698 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1699 intel_dp->DP |= DP_SYNC_VS_HIGH;
1700 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1701
6aba5b6c 1702 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1703 intel_dp->DP |= DP_ENHANCED_FRAMING;
1704
7c62a164 1705 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1706 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1707 u32 trans_dp;
1708
39e5fa88 1709 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1710
1711 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1712 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1713 trans_dp |= TRANS_DP_ENH_FRAMING;
1714 else
1715 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1716 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1717 } else {
0f2a2a75 1718 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
85cb48a1 1719 !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
0f2a2a75 1720 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1721
1722 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1723 intel_dp->DP |= DP_SYNC_HS_HIGH;
1724 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1725 intel_dp->DP |= DP_SYNC_VS_HIGH;
1726 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1727
6aba5b6c 1728 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1729 intel_dp->DP |= DP_ENHANCED_FRAMING;
1730
39e5fa88 1731 if (IS_CHERRYVIEW(dev))
44f37d1f 1732 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1733 else if (crtc->pipe == PIPE_B)
1734 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1735 }
a4fc5ed6
KP		 1736}
1737
ffd6749d
PZ		 1738#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1739#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1740
1a5ef5b7
PZ		 1741#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1742#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1743
ffd6749d
PZ		 1744#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1745#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1746
de9c1b6b
ID		 1747static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1748 struct intel_dp *intel_dp);
1749
4be73780 1750static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1751 u32 mask,
1752 u32 value)
bd943159 1753{
30add22d 1754 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1755 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 1756 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1757
e39b999a
VS		 1758 lockdep_assert_held(&dev_priv->pps_mutex);
1759
de9c1b6b
ID		 1760 intel_pps_verify_state(dev_priv, intel_dp);
1761
bf13e81b
JN		 1762 pp_stat_reg = _pp_stat_reg(intel_dp);
1763 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1764
99ea7127 1765 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1766 mask, value,
1767 I915_READ(pp_stat_reg),
1768 I915_READ(pp_ctrl_reg));
32ce697c 1769
9036ff06
CW		 1770 if (intel_wait_for_register(dev_priv,
1771 pp_stat_reg, mask, value,
1772 5000))
99ea7127 1773 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1774 I915_READ(pp_stat_reg),
1775 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1776
1777 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1778}
32ce697c 1779
4be73780 1780static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1781{
1782 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1783 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1784}
1785
4be73780 1786static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1787{
1788 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1789 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1790}
1791
4be73780 1792static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1793{
d28d4731
AK		 1794 ktime_t panel_power_on_time;
1795 s64 panel_power_off_duration;
1796
99ea7127 1797 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1798
d28d4731
AK		 1799 /* take the difference of currrent time and panel power off time
1800 * and then make panel wait for t11_t12 if needed. */
1801 panel_power_on_time = ktime_get_boottime();
1802 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1803
dce56b3c
PZ		 1804 /* When we disable the VDD override bit last we have to do the manual
1805 * wait. */
d28d4731
AK		 1806 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1807 wait_remaining_ms_from_jiffies(jiffies,
1808 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1809
4be73780 1810 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1811}
1812
4be73780 1813static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1814{
1815 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1816 intel_dp->backlight_on_delay);
1817}
1818
4be73780 1819static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1820{
1821 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1822 intel_dp->backlight_off_delay);
1823}
99ea7127 1824
832dd3c1
KP		 1825/* Read the current pp_control value, unlocking the register if it
1826 * is locked
1827 */
1828
453c5420 1829static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1830{
453c5420 1831 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1832 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 1833 u32 control;
832dd3c1 1834
e39b999a
VS		 1835 lockdep_assert_held(&dev_priv->pps_mutex);
1836
bf13e81b 1837 control = I915_READ(_pp_ctrl_reg(intel_dp));
8090ba8c
ID		 1838 if (WARN_ON(!HAS_DDI(dev_priv) &&
1839 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
b0a08bec
VK		 1840 control &= ~PANEL_UNLOCK_MASK;
1841 control |= PANEL_UNLOCK_REGS;
1842 }
832dd3c1 1843 return control;
bd943159
KP		 1844}
1845
951468f3
VS		 1846/*
1847 * Must be paired with edp_panel_vdd_off().
1848 * Must hold pps_mutex around the whole on/off sequence.
1849 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1850 */
1e0560e0 1851static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1852{
30add22d 1853 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1854 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1855 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fac5e23e 1856 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 1857 enum intel_display_power_domain power_domain;
5d613501 1858 u32 pp;
f0f59a00 1859 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1860 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1861
e39b999a
VS		 1862 lockdep_assert_held(&dev_priv->pps_mutex);
1863
97af61f5 1864 if (!is_edp(intel_dp))
adddaaf4 1865 return false;
bd943159 1866
2c623c11 1867 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1868 intel_dp->want_panel_vdd = true;
99ea7127 1869
4be73780 1870 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1871 return need_to_disable;
b0665d57 1872
25f78f58 1873 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1874 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1875
3936fcf4
VS		 1876 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1877 port_name(intel_dig_port->port));
bd943159 1878
4be73780
DV		 1879 if (!edp_have_panel_power(intel_dp))
1880 wait_panel_power_cycle(intel_dp);
99ea7127 1881
453c5420 1882 pp = ironlake_get_pp_control(intel_dp);
5d613501 1883 pp |= EDP_FORCE_VDD;
ebf33b18 1884
bf13e81b
JN		 1885 pp_stat_reg = _pp_stat_reg(intel_dp);
1886 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1887
1888 I915_WRITE(pp_ctrl_reg, pp);
1889 POSTING_READ(pp_ctrl_reg);
1890 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1891 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1892 /*
1893 * If the panel wasn't on, delay before accessing aux channel
1894 */
4be73780 1895 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1896 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1897 port_name(intel_dig_port->port));
f01eca2e 1898 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1899 }
adddaaf4
JN		 1900
1901 return need_to_disable;
1902}
1903
951468f3
VS		 1904/*
1905 * Must be paired with intel_edp_panel_vdd_off() or
1906 * intel_edp_panel_off().
1907 * Nested calls to these functions are not allowed since
1908 * we drop the lock. Caller must use some higher level
1909 * locking to prevent nested calls from other threads.
1910 */
b80d6c78 1911void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1912{
c695b6b6 1913 bool vdd;
adddaaf4 1914
c695b6b6
VS		 1915 if (!is_edp(intel_dp))
1916 return;
1917
773538e8 1918 pps_lock(intel_dp);
c695b6b6 1919 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1920 pps_unlock(intel_dp);
c695b6b6 1921
e2c719b7 1922 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1923 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1924}
1925
4be73780 1926static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1927{
30add22d 1928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1929 struct drm_i915_private *dev_priv = to_i915(dev);
be2c9196
VS		 1930 struct intel_digital_port *intel_dig_port =
1931 dp_to_dig_port(intel_dp);
1932 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1933 enum intel_display_power_domain power_domain;
5d613501 1934 u32 pp;
f0f59a00 1935 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1936
e39b999a 1937 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1938
15e899a0 1939 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1940
15e899a0 1941 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1942 return;
b0665d57 1943
3936fcf4
VS		 1944 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1945 port_name(intel_dig_port->port));
bd943159 1946
be2c9196
VS		 1947 pp = ironlake_get_pp_control(intel_dp);
1948 pp &= ~EDP_FORCE_VDD;
453c5420 1949
be2c9196
VS		 1950 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1951 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1952
be2c9196
VS		 1953 I915_WRITE(pp_ctrl_reg, pp);
1954 POSTING_READ(pp_ctrl_reg);
90791a5c 1955
be2c9196
VS		 1956 /* Make sure sequencer is idle before allowing subsequent activity */
1957 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1958 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1959
5a162e22 1960 if ((pp & PANEL_POWER_ON) == 0)
d28d4731 1961 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1962
25f78f58 1963 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1964 intel_display_power_put(dev_priv, power_domain);
bd943159 1965}
5d613501 1966
4be73780 1967static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1968{
1969 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1970 struct intel_dp, panel_vdd_work);
bd943159 1971
773538e8 1972 pps_lock(intel_dp);
15e899a0
VS		 1973 if (!intel_dp->want_panel_vdd)
1974 edp_panel_vdd_off_sync(intel_dp);
773538e8 1975 pps_unlock(intel_dp);
bd943159
KP		 1976}
1977
aba86890
ID		 1978static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1979{
1980 unsigned long delay;
1981
1982 /*
1983 * Queue the timer to fire a long time from now (relative to the power
1984 * down delay) to keep the panel power up across a sequence of
1985 * operations.
1986 */
1987 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1988 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1989}
1990
951468f3
VS		 1991/*
1992 * Must be paired with edp_panel_vdd_on().
1993 * Must hold pps_mutex around the whole on/off sequence.
1994 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1995 */
4be73780 1996static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1997{
fac5e23e 1998 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
e39b999a
VS		 1999
2000 lockdep_assert_held(&dev_priv->pps_mutex);
2001
97af61f5
KP		 2002 if (!is_edp(intel_dp))
2003 return;
5d613501 2004
e2c719b7 2005 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 2006 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 2007
bd943159
KP		 2008 intel_dp->want_panel_vdd = false;
2009
aba86890 2010 if (sync)
4be73780 2011 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2012 else
2013 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2014}
2015
9f0fb5be 2016static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2017{
30add22d 2018 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2019 struct drm_i915_private *dev_priv = to_i915(dev);
99ea7127 2020 u32 pp;
f0f59a00 2021 i915_reg_t pp_ctrl_reg;
9934c132 2022
9f0fb5be
VS		 2023 lockdep_assert_held(&dev_priv->pps_mutex);
2024
97af61f5 2025 if (!is_edp(intel_dp))
bd943159 2026 return;
99ea7127 2027
3936fcf4
VS		 2028 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2029 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2030
e7a89ace
VS		 2031 if (WARN(edp_have_panel_power(intel_dp),
2032 "eDP port %c panel power already on\n",
2033 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2034 return;
9934c132 2035
4be73780 2036 wait_panel_power_cycle(intel_dp);
37c6c9b0 2037
bf13e81b 2038 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2039 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 2040 if (IS_GEN5(dev)) {
2041 /* ILK workaround: disable reset around power sequence */
2042 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2043 I915_WRITE(pp_ctrl_reg, pp);
2044 POSTING_READ(pp_ctrl_reg);
05ce1a49 2045 }
37c6c9b0 2046
5a162e22 2047 pp |= PANEL_POWER_ON;
99ea7127
KP		 2048 if (!IS_GEN5(dev))
2049 pp |= PANEL_POWER_RESET;
2050
453c5420
JB		 2051 I915_WRITE(pp_ctrl_reg, pp);
2052 POSTING_READ(pp_ctrl_reg);
9934c132 2053
4be73780 2054 wait_panel_on(intel_dp);
dce56b3c 2055 intel_dp->last_power_on = jiffies;
9934c132 2056
05ce1a49
KP		 2057 if (IS_GEN5(dev)) {
2058 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2059 I915_WRITE(pp_ctrl_reg, pp);
2060 POSTING_READ(pp_ctrl_reg);
05ce1a49 2061 }
9f0fb5be 2062}
e39b999a 2063
9f0fb5be
VS		 2064void intel_edp_panel_on(struct intel_dp *intel_dp)
2065{
2066 if (!is_edp(intel_dp))
2067 return;
2068
2069 pps_lock(intel_dp);
2070 edp_panel_on(intel_dp);
773538e8 2071 pps_unlock(intel_dp);
9934c132
JB		 2072}
2073
9f0fb5be
VS		 2074
2075static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2076{
4e6e1a54
ID		 2077 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2078 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2080 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 2081 enum intel_display_power_domain power_domain;
99ea7127 2082 u32 pp;
f0f59a00 2083 i915_reg_t pp_ctrl_reg;
9934c132 2084
9f0fb5be
VS		 2085 lockdep_assert_held(&dev_priv->pps_mutex);
2086
97af61f5
KP		 2087 if (!is_edp(intel_dp))
2088 return;
37c6c9b0 2089
3936fcf4
VS		 2090 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2091 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2092
3936fcf4
VS		 2093 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2094 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2095
453c5420 2096 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2097 /* We need to switch off panel power _and_ force vdd, for otherwise some
2098 * panels get very unhappy and cease to work. */
5a162e22 2099 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
b3064154 2100 EDP_BLC_ENABLE);
453c5420 2101
bf13e81b 2102 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2103
849e39f5
PZ		 2104 intel_dp->want_panel_vdd = false;
2105
453c5420
JB		 2106 I915_WRITE(pp_ctrl_reg, pp);
2107 POSTING_READ(pp_ctrl_reg);
9934c132 2108
d28d4731 2109 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2110 wait_panel_off(intel_dp);
849e39f5
PZ		 2111
2112 /* We got a reference when we enabled the VDD. */
25f78f58 2113 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2114 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2115}
e39b999a 2116
9f0fb5be
VS		 2117void intel_edp_panel_off(struct intel_dp *intel_dp)
2118{
2119 if (!is_edp(intel_dp))
2120 return;
e39b999a 2121
9f0fb5be
VS		 2122 pps_lock(intel_dp);
2123 edp_panel_off(intel_dp);
773538e8 2124 pps_unlock(intel_dp);
9934c132
JB		 2125}
2126
1250d107
JN		 2127/* Enable backlight in the panel power control. */
2128static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2129{
da63a9f2
PZ		 2130 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2131 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2132 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2133 u32 pp;
f0f59a00 2134 i915_reg_t pp_ctrl_reg;
32f9d658 2135
01cb9ea6
JB		 2136 /*
2137 * If we enable the backlight right away following a panel power
2138 * on, we may see slight flicker as the panel syncs with the eDP
2139 * link. So delay a bit to make sure the image is solid before
2140 * allowing it to appear.
2141 */
4be73780 2142 wait_backlight_on(intel_dp);
e39b999a 2143
773538e8 2144 pps_lock(intel_dp);
e39b999a 2145
453c5420 2146 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2147 pp |= EDP_BLC_ENABLE;
453c5420 2148
bf13e81b 2149 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2150
2151 I915_WRITE(pp_ctrl_reg, pp);
2152 POSTING_READ(pp_ctrl_reg);
e39b999a 2153
773538e8 2154 pps_unlock(intel_dp);
32f9d658
ZW		 2155}
2156
1250d107
JN		 2157/* Enable backlight PWM and backlight PP control. */
2158void intel_edp_backlight_on(struct intel_dp *intel_dp)
2159{
2160 if (!is_edp(intel_dp))
2161 return;
2162
2163 DRM_DEBUG_KMS("\n");
2164
2165 intel_panel_enable_backlight(intel_dp->attached_connector);
2166 _intel_edp_backlight_on(intel_dp);
2167}
2168
2169/* Disable backlight in the panel power control. */
2170static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2171{
30add22d 2172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2173 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2174 u32 pp;
f0f59a00 2175 i915_reg_t pp_ctrl_reg;
32f9d658 2176
f01eca2e
KP		 2177 if (!is_edp(intel_dp))
2178 return;
2179
773538e8 2180 pps_lock(intel_dp);
e39b999a 2181
453c5420 2182 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2183 pp &= ~EDP_BLC_ENABLE;
453c5420 2184
bf13e81b 2185 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2186
2187 I915_WRITE(pp_ctrl_reg, pp);
2188 POSTING_READ(pp_ctrl_reg);
f7d2323c 2189
773538e8 2190 pps_unlock(intel_dp);
e39b999a
VS		 2191
2192 intel_dp->last_backlight_off = jiffies;
f7d2323c 2193 edp_wait_backlight_off(intel_dp);
1250d107 2194}
f7d2323c 2195
1250d107
JN		 2196/* Disable backlight PP control and backlight PWM. */
2197void intel_edp_backlight_off(struct intel_dp *intel_dp)
2198{
2199 if (!is_edp(intel_dp))
2200 return;
2201
2202 DRM_DEBUG_KMS("\n");
f7d2323c 2203
1250d107 2204 _intel_edp_backlight_off(intel_dp);
f7d2323c 2205 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2206}
a4fc5ed6 2207
73580fb7
JN		 2208/*
2209 * Hook for controlling the panel power control backlight through the bl_power
2210 * sysfs attribute. Take care to handle multiple calls.
2211 */
2212static void intel_edp_backlight_power(struct intel_connector *connector,
2213 bool enable)
2214{
2215 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2216 bool is_enabled;
2217
773538e8 2218 pps_lock(intel_dp);
e39b999a 2219 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2220 pps_unlock(intel_dp);
73580fb7
JN		 2221
2222 if (is_enabled == enable)
2223 return;
2224
23ba9373
JN		 2225 DRM_DEBUG_KMS("panel power control backlight %s\n",
2226 enable ? "enable" : "disable");
73580fb7
JN		 2227
2228 if (enable)
2229 _intel_edp_backlight_on(intel_dp);
2230 else
2231 _intel_edp_backlight_off(intel_dp);
2232}
2233
64e1077a
VS		 2234static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2235{
2236 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2237 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2238 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2239
2240 I915_STATE_WARN(cur_state != state,
2241 "DP port %c state assertion failure (expected %s, current %s)\n",
2242 port_name(dig_port->port),
87ad3212 2243 onoff(state), onoff(cur_state));
64e1077a
VS		 2244}
2245#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2246
2247static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2248{
2249 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2250
2251 I915_STATE_WARN(cur_state != state,
2252 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2253 onoff(state), onoff(cur_state));
64e1077a
VS		 2254}
2255#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2256#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2257
85cb48a1
ML		 2258static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2259 struct intel_crtc_state *pipe_config)
d240f20f 2260{
85cb48a1 2261 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
64e1077a 2262 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2263
64e1077a
VS		 2264 assert_pipe_disabled(dev_priv, crtc->pipe);
2265 assert_dp_port_disabled(intel_dp);
2266 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2267
abfce949 2268 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
85cb48a1 2269 pipe_config->port_clock);
abfce949
VS		 2270
2271 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2272
85cb48a1 2273 if (pipe_config->port_clock == 162000)
abfce949
VS		 2274 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2275 else
2276 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2277
2278 I915_WRITE(DP_A, intel_dp->DP);
2279 POSTING_READ(DP_A);
2280 udelay(500);
2281
6b23f3e8
VS		 2282 /*
2283 * [DevILK] Work around required when enabling DP PLL
2284 * while a pipe is enabled going to FDI:
2285 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2286 * 2. Program DP PLL enable
2287 */
2288 if (IS_GEN5(dev_priv))
91c8a326 2289 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
6b23f3e8 2290
0767935e 2291 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2292
0767935e 2293 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2294 POSTING_READ(DP_A);
2295 udelay(200);
d240f20f
JB		 2296}
2297
2bd2ad64 2298static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2299{
da63a9f2 2300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2301 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2302 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2303
64e1077a
VS		 2304 assert_pipe_disabled(dev_priv, crtc->pipe);
2305 assert_dp_port_disabled(intel_dp);
2306 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2307
abfce949
VS		 2308 DRM_DEBUG_KMS("disabling eDP PLL\n");
2309
6fec7662 2310 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2311
6fec7662 2312 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2313 POSTING_READ(DP_A);
d240f20f
JB		 2314 udelay(200);
2315}
2316
c7ad3810 2317/* If the sink supports it, try to set the power state appropriately */
c19b0669 2318void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2319{
2320 int ret, i;
2321
2322 /* Should have a valid DPCD by this point */
2323 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2324 return;
2325
2326 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2327 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2328 DP_SET_POWER_D3);
c7ad3810
JB		 2329 } else {
2330 /*
2331 * When turning on, we need to retry for 1ms to give the sink
2332 * time to wake up.
2333 */
2334 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2335 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2336 DP_SET_POWER_D0);
c7ad3810
JB		 2337 if (ret == 1)
2338 break;
2339 msleep(1);
2340 }
2341 }
f9cac721
JN		 2342
2343 if (ret != 1)
2344 DRM_DEBUG_KMS("failed to %s sink power state\n",
2345 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2346}
2347
19d8fe15
DV		 2348static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2349 enum pipe *pipe)
d240f20f 2350{
19d8fe15 2351 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2352 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15 2353 struct drm_device *dev = encoder->base.dev;
fac5e23e 2354 struct drm_i915_private *dev_priv = to_i915(dev);
6d129bea
ID		 2355 enum intel_display_power_domain power_domain;
2356 u32 tmp;
6fa9a5ec 2357 bool ret;
6d129bea
ID		 2358
2359 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2360 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2361 return false;
2362
6fa9a5ec
ID		 2363 ret = false;
2364
6d129bea 2365 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2366
2367 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2368 goto out;
19d8fe15 2369
39e5fa88 2370 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2371 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2372 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2373 enum pipe p;
19d8fe15 2374
adc289d7
VS		 2375 for_each_pipe(dev_priv, p) {
2376 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2377 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2378 *pipe = p;
6fa9a5ec
ID		 2379 ret = true;
2380
2381 goto out;
19d8fe15
DV		 2382 }
2383 }
19d8fe15 2384
4a0833ec 2385 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2386 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2387 } else if (IS_CHERRYVIEW(dev)) {
2388 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2389 } else {
2390 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2391 }
d240f20f 2392
6fa9a5ec
ID		 2393 ret = true;
2394
2395out:
2396 intel_display_power_put(dev_priv, power_domain);
2397
2398 return ret;
19d8fe15 2399}
d240f20f 2400
045ac3b5 2401static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2402 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2403{
2404 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2405 u32 tmp, flags = 0;
63000ef6 2406 struct drm_device *dev = encoder->base.dev;
fac5e23e 2407 struct drm_i915_private *dev_priv = to_i915(dev);
63000ef6
XZ		 2408 enum port port = dp_to_dig_port(intel_dp)->port;
2409 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2410
9ed109a7 2411 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2412
2413 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2414
39e5fa88 2415 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2416 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2417
2418 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2419 flags |= DRM_MODE_FLAG_PHSYNC;
2420 else
2421 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2422
b81e34c2 2423 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2424 flags |= DRM_MODE_FLAG_PVSYNC;
2425 else
2426 flags |= DRM_MODE_FLAG_NVSYNC;
2427 } else {
39e5fa88 2428 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2429 flags |= DRM_MODE_FLAG_PHSYNC;
2430 else
2431 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2432
39e5fa88 2433 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2434 flags |= DRM_MODE_FLAG_PVSYNC;
2435 else
2436 flags |= DRM_MODE_FLAG_NVSYNC;
2437 }
045ac3b5 2438
2d112de7 2439 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2440
8c875fca 2441 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2442 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2443 pipe_config->limited_color_range = true;
2444
90a6b7b0
VS		 2445 pipe_config->lane_count =
2446 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2447
eb14cb74
VS		 2448 intel_dp_get_m_n(crtc, pipe_config);
2449
18442d08 2450 if (port == PORT_A) {
b377e0df 2451 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2452 pipe_config->port_clock = 162000;
2453 else
2454 pipe_config->port_clock = 270000;
2455 }
18442d08 2456
e3b247da
VS		 2457 pipe_config->base.adjusted_mode.crtc_clock =
2458 intel_dotclock_calculate(pipe_config->port_clock,
2459 &pipe_config->dp_m_n);
7f16e5c1 2460
6aa23e65
JN		 2461 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2462 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2463 /*
2464 * This is a big fat ugly hack.
2465 *
2466 * Some machines in UEFI boot mode provide us a VBT that has 18
2467 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2468 * unknown we fail to light up. Yet the same BIOS boots up with
2469 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2470 * max, not what it tells us to use.
2471 *
2472 * Note: This will still be broken if the eDP panel is not lit
2473 * up by the BIOS, and thus we can't get the mode at module
2474 * load.
2475 */
2476 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2477 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2478 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2479 }
045ac3b5
JB		 2480}
2481
fd6bbda9
ML		 2482static void intel_disable_dp(struct intel_encoder *encoder,
2483 struct intel_crtc_state *old_crtc_state,
2484 struct drm_connector_state *old_conn_state)
d240f20f 2485{
e8cb4558 2486 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
85cb48a1 2487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
495a5bb8 2488
85cb48a1 2489 if (old_crtc_state->has_audio)
495a5bb8 2490 intel_audio_codec_disable(encoder);
6cb49835 2491
85cb48a1 2492 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
b32c6f48
RV		 2493 intel_psr_disable(intel_dp);
2494
6cb49835
DV		 2495 /* Make sure the panel is off before trying to change the mode. But also
2496 * ensure that we have vdd while we switch off the panel. */
24f3e092 2497 intel_edp_panel_vdd_on(intel_dp);
4be73780 2498 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2499 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2500 intel_edp_panel_off(intel_dp);
3739850b 2501
08aff3fe 2502 /* disable the port before the pipe on g4x */
85cb48a1 2503 if (INTEL_GEN(dev_priv) < 5)
3739850b 2504 intel_dp_link_down(intel_dp);
d240f20f
JB		 2505}
2506
fd6bbda9
ML		 2507static void ilk_post_disable_dp(struct intel_encoder *encoder,
2508 struct intel_crtc_state *old_crtc_state,
2509 struct drm_connector_state *old_conn_state)
d240f20f 2510{
2bd2ad64 2511 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2512 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2513
49277c31 2514 intel_dp_link_down(intel_dp);
abfce949
VS		 2515
2516 /* Only ilk+ has port A */
08aff3fe
VS		 2517 if (port == PORT_A)
2518 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2519}
2520
fd6bbda9
ML		 2521static void vlv_post_disable_dp(struct intel_encoder *encoder,
2522 struct intel_crtc_state *old_crtc_state,
2523 struct drm_connector_state *old_conn_state)
49277c31
VS		 2524{
2525 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2526
2527 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2528}
2529
fd6bbda9
ML		 2530static void chv_post_disable_dp(struct intel_encoder *encoder,
2531 struct intel_crtc_state *old_crtc_state,
2532 struct drm_connector_state *old_conn_state)
a8f327fb
VS		 2533{
2534 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2535 struct drm_device *dev = encoder->base.dev;
fac5e23e 2536 struct drm_i915_private *dev_priv = to_i915(dev);
97fd4d5c 2537
a8f327fb
VS		 2538 intel_dp_link_down(intel_dp);
2539
2540 mutex_lock(&dev_priv->sb_lock);
2541
2542 /* Assert data lane reset */
2543 chv_data_lane_soft_reset(encoder, true);
580d3811 2544
a580516d 2545 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2546}
2547
7b13b58a
VS		 2548static void
2549_intel_dp_set_link_train(struct intel_dp *intel_dp,
2550 uint32_t *DP,
2551 uint8_t dp_train_pat)
2552{
2553 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2554 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2555 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a
VS		 2556 enum port port = intel_dig_port->port;
2557
8b0878a0
PD		 2558 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2559 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2560 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2561
7b13b58a
VS		 2562 if (HAS_DDI(dev)) {
2563 uint32_t temp = I915_READ(DP_TP_CTL(port));
2564
2565 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2566 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2567 else
2568 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2569
2570 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2571 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2572 case DP_TRAINING_PATTERN_DISABLE:
2573 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2574
2575 break;
2576 case DP_TRAINING_PATTERN_1:
2577 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2578 break;
2579 case DP_TRAINING_PATTERN_2:
2580 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2581 break;
2582 case DP_TRAINING_PATTERN_3:
2583 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2584 break;
2585 }
2586 I915_WRITE(DP_TP_CTL(port), temp);
2587
39e5fa88
VS		 2588 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2589 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2590 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2591
2592 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2593 case DP_TRAINING_PATTERN_DISABLE:
2594 *DP |= DP_LINK_TRAIN_OFF_CPT;
2595 break;
2596 case DP_TRAINING_PATTERN_1:
2597 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2598 break;
2599 case DP_TRAINING_PATTERN_2:
2600 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2601 break;
2602 case DP_TRAINING_PATTERN_3:
8b0878a0 2603 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 2604 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2605 break;
2606 }
2607
2608 } else {
2609 if (IS_CHERRYVIEW(dev))
2610 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2611 else
2612 *DP &= ~DP_LINK_TRAIN_MASK;
2613
2614 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2615 case DP_TRAINING_PATTERN_DISABLE:
2616 *DP |= DP_LINK_TRAIN_OFF;
2617 break;
2618 case DP_TRAINING_PATTERN_1:
2619 *DP |= DP_LINK_TRAIN_PAT_1;
2620 break;
2621 case DP_TRAINING_PATTERN_2:
2622 *DP |= DP_LINK_TRAIN_PAT_2;
2623 break;
2624 case DP_TRAINING_PATTERN_3:
2625 if (IS_CHERRYVIEW(dev)) {
2626 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2627 } else {
8b0878a0 2628 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 2629 *DP |= DP_LINK_TRAIN_PAT_2;
2630 }
2631 break;
2632 }
2633 }
2634}
2635
85cb48a1
ML		 2636static void intel_dp_enable_port(struct intel_dp *intel_dp,
2637 struct intel_crtc_state *old_crtc_state)
7b13b58a
VS		 2638{
2639 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2640 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a 2641
7b13b58a 2642 /* enable with pattern 1 (as per spec) */
7b13b58a 2643
8b0878a0 2644 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
7b713f50
VS		 2645
2646 /*
2647 * Magic for VLV/CHV. We _must_ first set up the register
2648 * without actually enabling the port, and then do another
2649 * write to enable the port. Otherwise link training will
2650 * fail when the power sequencer is freshly used for this port.
2651 */
2652 intel_dp->DP |= DP_PORT_EN;
85cb48a1 2653 if (old_crtc_state->has_audio)
6fec7662 2654 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2655
2656 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2657 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2658}
2659
85cb48a1
ML		 2660static void intel_enable_dp(struct intel_encoder *encoder,
2661 struct intel_crtc_state *pipe_config)
d240f20f 2662{
e8cb4558
DV		 2663 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2664 struct drm_device *dev = encoder->base.dev;
fac5e23e 2665 struct drm_i915_private *dev_priv = to_i915(dev);
c1dec79a 2666 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2667 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2668 enum pipe pipe = crtc->pipe;
5d613501 2669
0c33d8d7
DV		 2670 if (WARN_ON(dp_reg & DP_PORT_EN))
2671 return;
5d613501 2672
093e3f13
VS		 2673 pps_lock(intel_dp);
2674
666a4537 2675 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2676 vlv_init_panel_power_sequencer(intel_dp);
2677
85cb48a1 2678 intel_dp_enable_port(intel_dp, pipe_config);
093e3f13
VS		 2679
2680 edp_panel_vdd_on(intel_dp);
2681 edp_panel_on(intel_dp);
2682 edp_panel_vdd_off(intel_dp, true);
2683
2684 pps_unlock(intel_dp);
2685
666a4537 2686 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2687 unsigned int lane_mask = 0x0;
2688
2689 if (IS_CHERRYVIEW(dev))
85cb48a1 2690 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
e0fce78f 2691
9b6de0a1
VS		 2692 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2693 lane_mask);
e0fce78f 2694 }
61234fa5 2695
f01eca2e 2696 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2697 intel_dp_start_link_train(intel_dp);
3ab9c637 2698 intel_dp_stop_link_train(intel_dp);
c1dec79a 2699
85cb48a1 2700 if (pipe_config->has_audio) {
c1dec79a 2701 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2702 pipe_name(pipe));
c1dec79a
JN		 2703 intel_audio_codec_enable(encoder);
2704 }
ab1f90f9 2705}
89b667f8 2706
fd6bbda9
ML		 2707static void g4x_enable_dp(struct intel_encoder *encoder,
2708 struct intel_crtc_state *pipe_config,
2709 struct drm_connector_state *conn_state)
ecff4f3b 2710{
828f5c6e
JN		 2711 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2712
85cb48a1 2713 intel_enable_dp(encoder, pipe_config);
4be73780 2714 intel_edp_backlight_on(intel_dp);
ab1f90f9 2715}
89b667f8 2716
fd6bbda9
ML		 2717static void vlv_enable_dp(struct intel_encoder *encoder,
2718 struct intel_crtc_state *pipe_config,
2719 struct drm_connector_state *conn_state)
ab1f90f9 2720{
828f5c6e
JN		 2721 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2722
4be73780 2723 intel_edp_backlight_on(intel_dp);
b32c6f48 2724 intel_psr_enable(intel_dp);
d240f20f
JB		 2725}
2726
fd6bbda9
ML		 2727static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2728 struct intel_crtc_state *pipe_config,
2729 struct drm_connector_state *conn_state)
ab1f90f9
JN		 2730{
2731 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2732 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2733
85cb48a1 2734 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 2735
d41f1efb 2736 /* Only ilk+ has port A */
abfce949 2737 if (port == PORT_A)
85cb48a1 2738 ironlake_edp_pll_on(intel_dp, pipe_config);
ab1f90f9
JN		 2739}
2740
83b84597
VS		 2741static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2742{
2743 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
fac5e23e 2744 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
83b84597 2745 enum pipe pipe = intel_dp->pps_pipe;
44cb734c 2746 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
83b84597
VS		 2747
2748 edp_panel_vdd_off_sync(intel_dp);
2749
2750 /*
2751 * VLV seems to get confused when multiple power seqeuencers
2752 * have the same port selected (even if only one has power/vdd
2753 * enabled). The failure manifests as vlv_wait_port_ready() failing
2754 * CHV on the other hand doesn't seem to mind having the same port
2755 * selected in multiple power seqeuencers, but let's clear the
2756 * port select always when logically disconnecting a power sequencer
2757 * from a port.
2758 */
2759 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2760 pipe_name(pipe), port_name(intel_dig_port->port));
2761 I915_WRITE(pp_on_reg, 0);
2762 POSTING_READ(pp_on_reg);
2763
2764 intel_dp->pps_pipe = INVALID_PIPE;
2765}
2766
a4a5d2f8
VS		 2767static void vlv_steal_power_sequencer(struct drm_device *dev,
2768 enum pipe pipe)
2769{
fac5e23e 2770 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 2771 struct intel_encoder *encoder;
2772
2773 lockdep_assert_held(&dev_priv->pps_mutex);
2774
ac3c12e4
VS		 2775 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2776 return;
2777
19c8054c 2778 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2779 struct intel_dp *intel_dp;
773538e8 2780 enum port port;
a4a5d2f8
VS		 2781
2782 if (encoder->type != INTEL_OUTPUT_EDP)
2783 continue;
2784
2785 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2786 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2787
2788 if (intel_dp->pps_pipe != pipe)
2789 continue;
2790
2791 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2792 pipe_name(pipe), port_name(port));
a4a5d2f8 2793
e02f9a06 2794 WARN(encoder->base.crtc,
034e43c6
VS		 2795 "stealing pipe %c power sequencer from active eDP port %c\n",
2796 pipe_name(pipe), port_name(port));
a4a5d2f8 2797
a4a5d2f8 2798 /* make sure vdd is off before we steal it */
83b84597 2799 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2800 }
2801}
2802
2803static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2804{
2805 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2806 struct intel_encoder *encoder = &intel_dig_port->base;
2807 struct drm_device *dev = encoder->base.dev;
fac5e23e 2808 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8 2809 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2810
2811 lockdep_assert_held(&dev_priv->pps_mutex);
2812
093e3f13
VS		 2813 if (!is_edp(intel_dp))
2814 return;
2815
a4a5d2f8
VS		 2816 if (intel_dp->pps_pipe == crtc->pipe)
2817 return;
2818
2819 /*
2820 * If another power sequencer was being used on this
2821 * port previously make sure to turn off vdd there while
2822 * we still have control of it.
2823 */
2824 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2825 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2826
2827 /*
2828 * We may be stealing the power
2829 * sequencer from another port.
2830 */
2831 vlv_steal_power_sequencer(dev, crtc->pipe);
2832
2833 /* now it's all ours */
2834 intel_dp->pps_pipe = crtc->pipe;
2835
2836 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2837 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2838
2839 /* init power sequencer on this pipe and port */
36b5f425
VS		 2840 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2841 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2842}
2843
fd6bbda9
ML		 2844static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2845 struct intel_crtc_state *pipe_config,
2846 struct drm_connector_state *conn_state)
a4fc5ed6 2847{
5f68c275 2848 vlv_phy_pre_encoder_enable(encoder);
ab1f90f9 2849
85cb48a1 2850 intel_enable_dp(encoder, pipe_config);
89b667f8
JB		 2851}
2852
fd6bbda9
ML		 2853static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2854 struct intel_crtc_state *pipe_config,
2855 struct drm_connector_state *conn_state)
89b667f8 2856{
85cb48a1 2857 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 2858
6da2e616 2859 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2860}
2861
fd6bbda9
ML		 2862static void chv_pre_enable_dp(struct intel_encoder *encoder,
2863 struct intel_crtc_state *pipe_config,
2864 struct drm_connector_state *conn_state)
e4a1d846 2865{
e7d2a717 2866 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2867
85cb48a1 2868 intel_enable_dp(encoder, pipe_config);
b0b33846
VS		 2869
2870 /* Second common lane will stay alive on its own now */
e7d2a717 2871 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2872}
2873
fd6bbda9
ML		 2874static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2875 struct intel_crtc_state *pipe_config,
2876 struct drm_connector_state *conn_state)
9197c88b 2877{
85cb48a1 2878 intel_dp_prepare(encoder, pipe_config);
625695f8 2879
419b1b7a 2880 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2881}
2882
fd6bbda9
ML		 2883static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2884 struct intel_crtc_state *pipe_config,
2885 struct drm_connector_state *conn_state)
d6db995f 2886{
204970b5 2887 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2888}
2889
a4fc5ed6
KP		 2890/*
2891 * Fetch AUX CH registers 0x202 - 0x207 which contain
2892 * link status information
2893 */
94223d04 2894bool
93f62dad 2895intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2896{
9f085ebb
L		 2897 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2898 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2899}
2900
1100244e 2901/* These are source-specific values. */
94223d04 2902uint8_t
1a2eb460 2903intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2904{
30add22d 2905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2906 struct drm_i915_private *dev_priv = to_i915(dev);
bc7d38a4 2907 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2908
9314726b
VK		 2909 if (IS_BROXTON(dev))
2910 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2911 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2912 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2913 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2914 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 2915 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 2916 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2917 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2918 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2919 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2920 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2921 else
bd60018a 2922 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2923}
2924
94223d04 2925uint8_t
1a2eb460
KP		 2926intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2927{
30add22d 2928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2929 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2930
5a9d1f1a
DL		 2931 if (INTEL_INFO(dev)->gen >= 9) {
2932 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2934 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2935 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2936 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2940 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2941 default:
2942 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2943 }
2944 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2945 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2947 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2949 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2953 default:
bd60018a 2954 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2955 }
666a4537 2956 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 2957 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2959 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2965 default:
bd60018a 2966 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2967 }
bc7d38a4 2968 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2969 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2974 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2975 default:
bd60018a 2976 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2977 }
2978 } else {
2979 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2980 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2981 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2983 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2987 default:
bd60018a 2988 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2989 }
a4fc5ed6
KP		 2990 }
2991}
2992
5829975c 2993static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 2994{
53d98725 2995 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 2996 unsigned long demph_reg_value, preemph_reg_value,
2997 uniqtranscale_reg_value;
2998 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 2999
3000 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3001 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3002 preemph_reg_value = 0x0004000;
3003 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3005 demph_reg_value = 0x2B405555;
3006 uniqtranscale_reg_value = 0x552AB83A;
3007 break;
bd60018a 3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3009 demph_reg_value = 0x2B404040;
3010 uniqtranscale_reg_value = 0x5548B83A;
3011 break;
bd60018a 3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3013 demph_reg_value = 0x2B245555;
3014 uniqtranscale_reg_value = 0x5560B83A;
3015 break;
bd60018a 3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3017 demph_reg_value = 0x2B405555;
3018 uniqtranscale_reg_value = 0x5598DA3A;
3019 break;
3020 default:
3021 return 0;
3022 }
3023 break;
bd60018a 3024 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3025 preemph_reg_value = 0x0002000;
3026 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3027 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3028 demph_reg_value = 0x2B404040;
3029 uniqtranscale_reg_value = 0x5552B83A;
3030 break;
bd60018a 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3032 demph_reg_value = 0x2B404848;
3033 uniqtranscale_reg_value = 0x5580B83A;
3034 break;
bd60018a 3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3036 demph_reg_value = 0x2B404040;
3037 uniqtranscale_reg_value = 0x55ADDA3A;
3038 break;
3039 default:
3040 return 0;
3041 }
3042 break;
bd60018a 3043 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3044 preemph_reg_value = 0x0000000;
3045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3047 demph_reg_value = 0x2B305555;
3048 uniqtranscale_reg_value = 0x5570B83A;
3049 break;
bd60018a 3050 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3051 demph_reg_value = 0x2B2B4040;
3052 uniqtranscale_reg_value = 0x55ADDA3A;
3053 break;
3054 default:
3055 return 0;
3056 }
3057 break;
bd60018a 3058 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3059 preemph_reg_value = 0x0006000;
3060 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3062 demph_reg_value = 0x1B405555;
3063 uniqtranscale_reg_value = 0x55ADDA3A;
3064 break;
3065 default:
3066 return 0;
3067 }
3068 break;
3069 default:
3070 return 0;
3071 }
3072
53d98725
ACO		 3073 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3074 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3075
3076 return 0;
3077}
3078
5829975c 3079static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3080{
b7fa22d8
ACO		 3081 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3082 u32 deemph_reg_value, margin_reg_value;
3083 bool uniq_trans_scale = false;
e4a1d846 3084 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3085
3086 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3087 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3088 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3090 deemph_reg_value = 128;
3091 margin_reg_value = 52;
3092 break;
bd60018a 3093 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3094 deemph_reg_value = 128;
3095 margin_reg_value = 77;
3096 break;
bd60018a 3097 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3098 deemph_reg_value = 128;
3099 margin_reg_value = 102;
3100 break;
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3102 deemph_reg_value = 128;
3103 margin_reg_value = 154;
b7fa22d8 3104 uniq_trans_scale = true;
e4a1d846
CML		 3105 break;
3106 default:
3107 return 0;
3108 }
3109 break;
bd60018a 3110 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3111 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3112 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3113 deemph_reg_value = 85;
3114 margin_reg_value = 78;
3115 break;
bd60018a 3116 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3117 deemph_reg_value = 85;
3118 margin_reg_value = 116;
3119 break;
bd60018a 3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3121 deemph_reg_value = 85;
3122 margin_reg_value = 154;
3123 break;
3124 default:
3125 return 0;
3126 }
3127 break;
bd60018a 3128 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3129 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3131 deemph_reg_value = 64;
3132 margin_reg_value = 104;
3133 break;
bd60018a 3134 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3135 deemph_reg_value = 64;
3136 margin_reg_value = 154;
3137 break;
3138 default:
3139 return 0;
3140 }
3141 break;
bd60018a 3142 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3145 deemph_reg_value = 43;
3146 margin_reg_value = 154;
3147 break;
3148 default:
3149 return 0;
3150 }
3151 break;
3152 default:
3153 return 0;
3154 }
3155
b7fa22d8
ACO		 3156 chv_set_phy_signal_level(encoder, deemph_reg_value,
3157 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3158
3159 return 0;
3160}
3161
a4fc5ed6 3162static uint32_t
5829975c 3163gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3164{
3cf2efb1 3165 uint32_t signal_levels = 0;
a4fc5ed6 3166
3cf2efb1 3167 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3168 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3169 default:
3170 signal_levels |= DP_VOLTAGE_0_4;
3171 break;
bd60018a 3172 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3173 signal_levels |= DP_VOLTAGE_0_6;
3174 break;
bd60018a 3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3176 signal_levels |= DP_VOLTAGE_0_8;
3177 break;
bd60018a 3178 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3179 signal_levels |= DP_VOLTAGE_1_2;
3180 break;
3181 }
3cf2efb1 3182 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3183 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3184 default:
3185 signal_levels |= DP_PRE_EMPHASIS_0;
3186 break;
bd60018a 3187 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3188 signal_levels |= DP_PRE_EMPHASIS_3_5;
3189 break;
bd60018a 3190 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3191 signal_levels |= DP_PRE_EMPHASIS_6;
3192 break;
bd60018a 3193 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3194 signal_levels |= DP_PRE_EMPHASIS_9_5;
3195 break;
3196 }
3197 return signal_levels;
3198}
3199
e3421a18
ZW		 3200/* Gen6's DP voltage swing and pre-emphasis control */
3201static uint32_t
5829975c 3202gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3203{
3c5a62b5
YL		 3204 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3205 DP_TRAIN_PRE_EMPHASIS_MASK);
3206 switch (signal_levels) {
bd60018a
SJ		 3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3209 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3210 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3211 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3213 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3214 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3215 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3216 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3217 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3219 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3220 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3221 default:
3c5a62b5
YL		 3222 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3223 "0x%x\n", signal_levels);
3224 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3225 }
3226}
3227
1a2eb460
KP		 3228/* Gen7's DP voltage swing and pre-emphasis control */
3229static uint32_t
5829975c 3230gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3231{
3232 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3233 DP_TRAIN_PRE_EMPHASIS_MASK);
3234 switch (signal_levels) {
bd60018a 3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3236 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3238 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3240 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3241
bd60018a 3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3243 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3245 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3246
bd60018a 3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3248 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3250 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3251
3252 default:
3253 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3254 "0x%x\n", signal_levels);
3255 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3256 }
3257}
3258
94223d04 3259void
f4eb692e 3260intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3261{
3262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3263 enum port port = intel_dig_port->port;
f0a3424e 3264 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3265 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3266 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3267 uint8_t train_set = intel_dp->train_set[0];
3268
f8896f5d
DW		 3269 if (HAS_DDI(dev)) {
3270 signal_levels = ddi_signal_levels(intel_dp);
3271
3272 if (IS_BROXTON(dev))
3273 signal_levels = 0;
3274 else
3275 mask = DDI_BUF_EMP_MASK;
e4a1d846 3276 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3277 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3278 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3279 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3280 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3281 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3282 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3283 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3284 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3285 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3286 } else {
5829975c 3287 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3288 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3289 }
3290
96fb9f9b
VK		 3291 if (mask)
3292 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3293
3294 DRM_DEBUG_KMS("Using vswing level %d\n",
3295 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3296 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3297 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3298 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3299
f4eb692e 3300 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3301
3302 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3303 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3304}
3305
94223d04 3306void
e9c176d5
ACO		 3307intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3308 uint8_t dp_train_pat)
a4fc5ed6 3309{
174edf1f 3310 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3311 struct drm_i915_private *dev_priv =
3312 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3313
f4eb692e 3314 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3315
f4eb692e 3316 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3317 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3318}
3319
94223d04 3320void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3321{
3322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3323 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3324 struct drm_i915_private *dev_priv = to_i915(dev);
3ab9c637
ID		 3325 enum port port = intel_dig_port->port;
3326 uint32_t val;
3327
3328 if (!HAS_DDI(dev))
3329 return;
3330
3331 val = I915_READ(DP_TP_CTL(port));
3332 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3333 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3334 I915_WRITE(DP_TP_CTL(port), val);
3335
3336 /*
3337 * On PORT_A we can have only eDP in SST mode. There the only reason
3338 * we need to set idle transmission mode is to work around a HW issue
3339 * where we enable the pipe while not in idle link-training mode.
3340 * In this case there is requirement to wait for a minimum number of
3341 * idle patterns to be sent.
3342 */
3343 if (port == PORT_A)
3344 return;
3345
a767017f
CW		 3346 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3347 DP_TP_STATUS_IDLE_DONE,
3348 DP_TP_STATUS_IDLE_DONE,
3349 1))
3ab9c637
ID		 3350 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3351}
3352
a4fc5ed6 3353static void
ea5b213a 3354intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3355{
da63a9f2 3356 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3357 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3358 enum port port = intel_dig_port->port;
da63a9f2 3359 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3360 struct drm_i915_private *dev_priv = to_i915(dev);
ea5b213a 3361 uint32_t DP = intel_dp->DP;
a4fc5ed6 3362
bc76e320 3363 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3364 return;
3365
0c33d8d7 3366 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3367 return;
3368
28c97730 3369 DRM_DEBUG_KMS("\n");
32f9d658 3370
39e5fa88
VS		 3371 if ((IS_GEN7(dev) && port == PORT_A) ||
3372 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3373 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3374 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3375 } else {
aad3d14d
VS		 3376 if (IS_CHERRYVIEW(dev))
3377 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3378 else
3379 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3380 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3381 }
1612c8bd 3382 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3383 POSTING_READ(intel_dp->output_reg);
5eb08b69 3384
1612c8bd
VS		 3385 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3386 I915_WRITE(intel_dp->output_reg, DP);
3387 POSTING_READ(intel_dp->output_reg);
3388
3389 /*
3390 * HW workaround for IBX, we need to move the port
3391 * to transcoder A after disabling it to allow the
3392 * matching HDMI port to be enabled on transcoder A.
3393 */
3394 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3395 /*
3396 * We get CPU/PCH FIFO underruns on the other pipe when
3397 * doing the workaround. Sweep them under the rug.
3398 */
3399 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3400 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3401
1612c8bd
VS		 3402 /* always enable with pattern 1 (as per spec) */
3403 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3404 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3405 I915_WRITE(intel_dp->output_reg, DP);
3406 POSTING_READ(intel_dp->output_reg);
3407
3408 DP &= ~DP_PORT_EN;
5bddd17f 3409 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3410 POSTING_READ(intel_dp->output_reg);
0c241d5b 3411
91c8a326 3412 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
0c241d5b
VS		 3413 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3414 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3415 }
3416
f01eca2e 3417 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3418
3419 intel_dp->DP = DP;
a4fc5ed6
KP		 3420}
3421
26d61aad 3422static bool
fe5a66f9 3423intel_dp_read_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3424{
9f085ebb
L		 3425 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3426 sizeof(intel_dp->dpcd)) < 0)
edb39244 3427 return false; /* aux transfer failed */
92fd8fd1 3428
a8e98153 3429 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3430
fe5a66f9
VS		 3431 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3432}
edb39244 3433
fe5a66f9
VS		 3434static bool
3435intel_edp_init_dpcd(struct intel_dp *intel_dp)
3436{
3437 struct drm_i915_private *dev_priv =
3438 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
30d9aa42 3439
fe5a66f9
VS		 3440 /* this function is meant to be called only once */
3441 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
30d9aa42 3442
fe5a66f9 3443 if (!intel_dp_read_dpcd(intel_dp))
30d9aa42
SS		 3444 return false;
3445
fe5a66f9
VS		 3446 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3447 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3448 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
474d1ec4 3449
fe5a66f9
VS		 3450 /* Check if the panel supports PSR */
3451 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3452 intel_dp->psr_dpcd,
3453 sizeof(intel_dp->psr_dpcd));
3454 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3455 dev_priv->psr.sink_support = true;
3456 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3457 }
86ee27b5 3458
fe5a66f9
VS		 3459 if (INTEL_GEN(dev_priv) >= 9 &&
3460 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3461 uint8_t frame_sync_cap;
3462
3463 dev_priv->psr.sink_support = true;
3464 drm_dp_dpcd_read(&intel_dp->aux,
3465 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3466 &frame_sync_cap, 1);
3467 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3468 /* PSR2 needs frame sync as well */
3469 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3470 DRM_DEBUG_KMS("PSR2 %s on sink",
3471 dev_priv->psr.psr2_support ? "supported" : "not supported");
50003939
JN		 3472 }
3473
fe5a66f9
VS		 3474 /* Read the eDP Display control capabilities registers */
3475 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3476 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3477 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) ==
3478 sizeof(intel_dp->edp_dpcd)))
3479 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3480 intel_dp->edp_dpcd);
06ea66b6 3481
fc0f8e25 3482 /* Intermediate frequency support */
fe5a66f9 3483 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
94ca719e 3484 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3485 int i;
3486
9f085ebb
L		 3487 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3488 sink_rates, sizeof(sink_rates));
ea2d8a42 3489
94ca719e
VS		 3490 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3491 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3492
3493 if (val == 0)
3494 break;
3495
af77b974
SJ		 3496 /* Value read is in kHz while drm clock is saved in deca-kHz */
3497 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3498 }
94ca719e 3499 intel_dp->num_sink_rates = i;
fc0f8e25 3500 }
0336400e 3501
fe5a66f9
VS		 3502 return true;
3503}
3504
3505
3506static bool
3507intel_dp_get_dpcd(struct intel_dp *intel_dp)
3508{
3509 if (!intel_dp_read_dpcd(intel_dp))
3510 return false;
3511
3512 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3513 &intel_dp->sink_count, 1) < 0)
3514 return false;
3515
3516 /*
3517 * Sink count can change between short pulse hpd hence
3518 * a member variable in intel_dp will track any changes
3519 * between short pulse interrupts.
3520 */
3521 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3522
3523 /*
3524 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3525 * a dongle is present but no display. Unless we require to know
3526 * if a dongle is present or not, we don't need to update
3527 * downstream port information. So, an early return here saves
3528 * time from performing other operations which are not required.
3529 */
3530 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3531 return false;
0336400e 3532
edb39244
AJ		 3533 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3534 DP_DWN_STRM_PORT_PRESENT))
3535 return true; /* native DP sink */
3536
3537 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3538 return true; /* no per-port downstream info */
3539
9f085ebb
L		 3540 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3541 intel_dp->downstream_ports,
3542 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3543 return false; /* downstream port status fetch failed */
3544
3545 return true;
92fd8fd1
KP		 3546}
3547
0d198328
AJ		 3548static void
3549intel_dp_probe_oui(struct intel_dp *intel_dp)
3550{
3551 u8 buf[3];
3552
3553 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3554 return;
3555
9f085ebb 3556 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3557 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3558 buf[0], buf[1], buf[2]);
3559
9f085ebb 3560 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3561 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3562 buf[0], buf[1], buf[2]);
3563}
3564
0e32b39c 3565static bool
c4e3170a 3566intel_dp_can_mst(struct intel_dp *intel_dp)
0e32b39c
DA		 3567{
3568 u8 buf[1];
3569
7cc96139
NS		 3570 if (!i915.enable_dp_mst)
3571 return false;
3572
0e32b39c
DA		 3573 if (!intel_dp->can_mst)
3574 return false;
3575
3576 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3577 return false;
3578
c4e3170a
VS		 3579 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3580 return false;
0e32b39c 3581
c4e3170a
VS		 3582 return buf[0] & DP_MST_CAP;
3583}
3584
3585static void
3586intel_dp_configure_mst(struct intel_dp *intel_dp)
3587{
3588 if (!i915.enable_dp_mst)
3589 return;
3590
3591 if (!intel_dp->can_mst)
3592 return;
3593
3594 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3595
3596 if (intel_dp->is_mst)
3597 DRM_DEBUG_KMS("Sink is MST capable\n");
3598 else
3599 DRM_DEBUG_KMS("Sink is not MST capable\n");
3600
3601 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3602 intel_dp->is_mst);
0e32b39c
DA		 3603}
3604
e5a1cab5 3605static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3606{
082dcc7c 3607 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3608 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3609 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3610 u8 buf;
e5a1cab5 3611 int ret = 0;
c6297843
RV		 3612 int count = 0;
3613 int attempts = 10;
d2e216d0 3614
082dcc7c
RV		 3615 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3616 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3617 ret = -EIO;
3618 goto out;
4373f0f2
PZ		 3619 }
3620
082dcc7c 3621 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3622 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3623 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3624 ret = -EIO;
3625 goto out;
3626 }
d2e216d0 3627
c6297843
RV		 3628 do {
3629 intel_wait_for_vblank(dev, intel_crtc->pipe);
3630
3631 if (drm_dp_dpcd_readb(&intel_dp->aux,
3632 DP_TEST_SINK_MISC, &buf) < 0) {
3633 ret = -EIO;
3634 goto out;
3635 }
3636 count = buf & DP_TEST_COUNT_MASK;
3637 } while (--attempts && count);
3638
3639 if (attempts == 0) {
dc5a9037 3640 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3641 ret = -ETIMEDOUT;
3642 }
3643
e5a1cab5 3644 out:
082dcc7c 3645 hsw_enable_ips(intel_crtc);
e5a1cab5 3646 return ret;
082dcc7c
RV		 3647}
3648
3649static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3650{
3651 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3652 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3653 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3654 u8 buf;
e5a1cab5
RV		 3655 int ret;
3656
082dcc7c
RV		 3657 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3658 return -EIO;
3659
3660 if (!(buf & DP_TEST_CRC_SUPPORTED))
3661 return -ENOTTY;
3662
3663 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3664 return -EIO;
3665
6d8175da
RV		 3666 if (buf & DP_TEST_SINK_START) {
3667 ret = intel_dp_sink_crc_stop(intel_dp);
3668 if (ret)
3669 return ret;
3670 }
3671
082dcc7c 3672 hsw_disable_ips(intel_crtc);
1dda5f93 3673
9d1a1031 3674 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3675 buf | DP_TEST_SINK_START) < 0) {
3676 hsw_enable_ips(intel_crtc);
3677 return -EIO;
4373f0f2
PZ		 3678 }
3679
d72f9d91 3680 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3681 return 0;
3682}
3683
3684int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3685{
3686 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3687 struct drm_device *dev = dig_port->base.base.dev;
3688 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3689 u8 buf;
621d4c76 3690 int count, ret;
082dcc7c 3691 int attempts = 6;
082dcc7c
RV		 3692
3693 ret = intel_dp_sink_crc_start(intel_dp);
3694 if (ret)
3695 return ret;
3696
ad9dc91b 3697 do {
621d4c76
RV		 3698 intel_wait_for_vblank(dev, intel_crtc->pipe);
3699
1dda5f93 3700 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3701 DP_TEST_SINK_MISC, &buf) < 0) {
3702 ret = -EIO;
afe0d67e 3703 goto stop;
4373f0f2 3704 }
621d4c76 3705 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3706
7e38eeff 3707 } while (--attempts && count == 0);
ad9dc91b
RV		 3708
3709 if (attempts == 0) {
7e38eeff
RV		 3710 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3711 ret = -ETIMEDOUT;
3712 goto stop;
3713 }
3714
3715 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3716 ret = -EIO;
3717 goto stop;
ad9dc91b 3718 }
d2e216d0 3719
afe0d67e 3720stop:
082dcc7c 3721 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3722 return ret;
d2e216d0
RV		 3723}
3724
a60f0e38
JB		 3725static bool
3726intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3727{
9f085ebb 3728 return drm_dp_dpcd_read(&intel_dp->aux,
9d1a1031
JN		 3729 DP_DEVICE_SERVICE_IRQ_VECTOR,
3730 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3731}
3732
0e32b39c
DA		 3733static bool
3734intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3735{
3736 int ret;
3737
9f085ebb 3738 ret = drm_dp_dpcd_read(&intel_dp->aux,
0e32b39c
DA		 3739 DP_SINK_COUNT_ESI,
3740 sink_irq_vector, 14);
3741 if (ret != 14)
3742 return false;
3743
3744 return true;
3745}
3746
c5d5ab7a
TP		 3747static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3748{
3749 uint8_t test_result = DP_TEST_ACK;
3750 return test_result;
3751}
3752
3753static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3754{
3755 uint8_t test_result = DP_TEST_NAK;
3756 return test_result;
3757}
3758
3759static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3760{
c5d5ab7a 3761 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3762 struct intel_connector *intel_connector = intel_dp->attached_connector;
3763 struct drm_connector *connector = &intel_connector->base;
3764
3765 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3766 connector->edid_corrupt ||
559be30c
TP		 3767 intel_dp->aux.i2c_defer_count > 6) {
3768 /* Check EDID read for NACKs, DEFERs and corruption
3769 * (DP CTS 1.2 Core r1.1)
3770 * 4.2.2.4 : Failed EDID read, I2C_NAK
3771 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3772 * 4.2.2.6 : EDID corruption detected
3773 * Use failsafe mode for all cases
3774 */
3775 if (intel_dp->aux.i2c_nack_count > 0 ||
3776 intel_dp->aux.i2c_defer_count > 0)
3777 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3778 intel_dp->aux.i2c_nack_count,
3779 intel_dp->aux.i2c_defer_count);
3780 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3781 } else {
f79b468e
TS		 3782 struct edid *block = intel_connector->detect_edid;
3783
3784 /* We have to write the checksum
3785 * of the last block read
3786 */
3787 block += intel_connector->detect_edid->extensions;
3788
559be30c
TP		 3789 if (!drm_dp_dpcd_write(&intel_dp->aux,
3790 DP_TEST_EDID_CHECKSUM,
f79b468e 3791 &block->checksum,
5a1cc655 3792 1))
559be30c
TP		 3793 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3794
3795 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3796 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3797 }
3798
3799 /* Set test active flag here so userspace doesn't interrupt things */
3800 intel_dp->compliance_test_active = 1;
3801
c5d5ab7a
TP		 3802 return test_result;
3803}
3804
3805static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3806{
c5d5ab7a
TP		 3807 uint8_t test_result = DP_TEST_NAK;
3808 return test_result;
3809}
3810
3811static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3812{
3813 uint8_t response = DP_TEST_NAK;
3814 uint8_t rxdata = 0;
3815 int status = 0;
3816
c5d5ab7a
TP		 3817 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3818 if (status <= 0) {
3819 DRM_DEBUG_KMS("Could not read test request from sink\n");
3820 goto update_status;
3821 }
3822
3823 switch (rxdata) {
3824 case DP_TEST_LINK_TRAINING:
3825 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3826 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3827 response = intel_dp_autotest_link_training(intel_dp);
3828 break;
3829 case DP_TEST_LINK_VIDEO_PATTERN:
3830 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3831 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3832 response = intel_dp_autotest_video_pattern(intel_dp);
3833 break;
3834 case DP_TEST_LINK_EDID_READ:
3835 DRM_DEBUG_KMS("EDID test requested\n");
3836 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3837 response = intel_dp_autotest_edid(intel_dp);
3838 break;
3839 case DP_TEST_LINK_PHY_TEST_PATTERN:
3840 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3841 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3842 response = intel_dp_autotest_phy_pattern(intel_dp);
3843 break;
3844 default:
3845 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3846 break;
3847 }
3848
3849update_status:
3850 status = drm_dp_dpcd_write(&intel_dp->aux,
3851 DP_TEST_RESPONSE,
3852 &response, 1);
3853 if (status <= 0)
3854 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3855}
3856
0e32b39c
DA		 3857static int
3858intel_dp_check_mst_status(struct intel_dp *intel_dp)
3859{
3860 bool bret;
3861
3862 if (intel_dp->is_mst) {
3863 u8 esi[16] = { 0 };
3864 int ret = 0;
3865 int retry;
3866 bool handled;
3867 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3868go_again:
3869 if (bret == true) {
3870
3871 /* check link status - esi[10] = 0x200c */
19e0b4ca 3872 if (intel_dp->active_mst_links &&
901c2daf 3873 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3874 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3875 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3876 intel_dp_stop_link_train(intel_dp);
3877 }
3878
6f34cc39 3879 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3880 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3881
3882 if (handled) {
3883 for (retry = 0; retry < 3; retry++) {
3884 int wret;
3885 wret = drm_dp_dpcd_write(&intel_dp->aux,
3886 DP_SINK_COUNT_ESI+1,
3887 &esi[1], 3);
3888 if (wret == 3) {
3889 break;
3890 }
3891 }
3892
3893 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3894 if (bret == true) {
6f34cc39 3895 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3896 goto go_again;
3897 }
3898 } else
3899 ret = 0;
3900
3901 return ret;
3902 } else {
3903 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3904 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3905 intel_dp->is_mst = false;
3906 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3907 /* send a hotplug event */
3908 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3909 }
3910 }
3911 return -EINVAL;
3912}
3913
5c9114d0
SS		 3914static void
3915intel_dp_check_link_status(struct intel_dp *intel_dp)
3916{
3917 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3918 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3919 u8 link_status[DP_LINK_STATUS_SIZE];
3920
3921 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3922
3923 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3924 DRM_ERROR("Failed to get link status\n");
3925 return;
3926 }
3927
3928 if (!intel_encoder->base.crtc)
3929 return;
3930
3931 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3932 return;
3933
3934 /* if link training is requested we should perform it always */
3935 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
3936 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
3937 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3938 intel_encoder->base.name);
3939 intel_dp_start_link_train(intel_dp);
3940 intel_dp_stop_link_train(intel_dp);
3941 }
3942}
3943
a4fc5ed6
KP		 3944/*
3945 * According to DP spec
3946 * 5.1.2:
3947 * 1. Read DPCD
3948 * 2. Configure link according to Receiver Capabilities
3949 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3950 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 3951 *
3952 * intel_dp_short_pulse - handles short pulse interrupts
3953 * when full detection is not required.
3954 * Returns %true if short pulse is handled and full detection
3955 * is NOT required and %false otherwise.
a4fc5ed6 3956 */
39ff747b 3957static bool
5c9114d0 3958intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 3959{
5b215bcf 3960 struct drm_device *dev = intel_dp_to_dev(intel_dp);
65fbb4e7 3961 u8 sink_irq_vector = 0;
39ff747b
SS		 3962 u8 old_sink_count = intel_dp->sink_count;
3963 bool ret;
5b215bcf 3964
4df6960e
SS		 3965 /*
3966 * Clearing compliance test variables to allow capturing
3967 * of values for next automated test request.
3968 */
3969 intel_dp->compliance_test_active = 0;
3970 intel_dp->compliance_test_type = 0;
3971 intel_dp->compliance_test_data = 0;
3972
39ff747b
SS		 3973 /*
3974 * Now read the DPCD to see if it's actually running
3975 * If the current value of sink count doesn't match with
3976 * the value that was stored earlier or dpcd read failed
3977 * we need to do full detection
3978 */
3979 ret = intel_dp_get_dpcd(intel_dp);
3980
3981 if ((old_sink_count != intel_dp->sink_count) || !ret) {
3982 /* No need to proceed if we are going to do full detect */
3983 return false;
59cd09e1
JB		 3984 }
3985
a60f0e38
JB		 3986 /* Try to read the source of the interrupt */
3987 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 3988 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
3989 sink_irq_vector != 0) {
a60f0e38 3990 /* Clear interrupt source */
9d1a1031
JN		 3991 drm_dp_dpcd_writeb(&intel_dp->aux,
3992 DP_DEVICE_SERVICE_IRQ_VECTOR,
3993 sink_irq_vector);
a60f0e38
JB		 3994
3995 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 3996 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 3997 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3998 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3999 }
4000
5c9114d0
SS		 4001 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4002 intel_dp_check_link_status(intel_dp);
4003 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 4004
4005 return true;
a4fc5ed6 4006}
a4fc5ed6 4007
caf9ab24 4008/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4009static enum drm_connector_status
26d61aad 4010intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4011{
caf9ab24 4012 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4013 uint8_t type;
4014
4015 if (!intel_dp_get_dpcd(intel_dp))
4016 return connector_status_disconnected;
4017
1034ce70
SS		 4018 if (is_edp(intel_dp))
4019 return connector_status_connected;
4020
caf9ab24
AJ		 4021 /* if there's no downstream port, we're done */
4022 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4023 return connector_status_connected;
caf9ab24
AJ		 4024
4025 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4026 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4027 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 4028
30d9aa42
SS		 4029 return intel_dp->sink_count ?
4030 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 4031 }
4032
c4e3170a
VS		 4033 if (intel_dp_can_mst(intel_dp))
4034 return connector_status_connected;
4035
caf9ab24 4036 /* If no HPD, poke DDC gently */
0b99836f 4037 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4038 return connector_status_connected;
caf9ab24
AJ		 4039
4040 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4041 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4042 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4043 if (type == DP_DS_PORT_TYPE_VGA ||
4044 type == DP_DS_PORT_TYPE_NON_EDID)
4045 return connector_status_unknown;
4046 } else {
4047 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4048 DP_DWN_STRM_PORT_TYPE_MASK;
4049 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4050 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4051 return connector_status_unknown;
4052 }
caf9ab24
AJ		 4053
4054 /* Anything else is out of spec, warn and ignore */
4055 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4056 return connector_status_disconnected;
71ba9000
AJ		 4057}
4058
d410b56d
CW		 4059static enum drm_connector_status
4060edp_detect(struct intel_dp *intel_dp)
4061{
4062 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4063 enum drm_connector_status status;
4064
4065 status = intel_panel_detect(dev);
4066 if (status == connector_status_unknown)
4067 status = connector_status_connected;
4068
4069 return status;
4070}
4071
b93433cc
JN		 4072static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4073 struct intel_digital_port *port)
5eb08b69 4074{
b93433cc 4075 u32 bit;
01cb9ea6 4076
0df53b77
JN		 4077 switch (port->port) {
4078 case PORT_A:
4079 return true;
4080 case PORT_B:
4081 bit = SDE_PORTB_HOTPLUG;
4082 break;
4083 case PORT_C:
4084 bit = SDE_PORTC_HOTPLUG;
4085 break;
4086 case PORT_D:
4087 bit = SDE_PORTD_HOTPLUG;
4088 break;
4089 default:
4090 MISSING_CASE(port->port);
4091 return false;
4092 }
4093
4094 return I915_READ(SDEISR) & bit;
4095}
4096
4097static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4098 struct intel_digital_port *port)
4099{
4100 u32 bit;
4101
4102 switch (port->port) {
4103 case PORT_A:
4104 return true;
4105 case PORT_B:
4106 bit = SDE_PORTB_HOTPLUG_CPT;
4107 break;
4108 case PORT_C:
4109 bit = SDE_PORTC_HOTPLUG_CPT;
4110 break;
4111 case PORT_D:
4112 bit = SDE_PORTD_HOTPLUG_CPT;
4113 break;
a78695d3
JN		 4114 case PORT_E:
4115 bit = SDE_PORTE_HOTPLUG_SPT;
4116 break;
0df53b77
JN		 4117 default:
4118 MISSING_CASE(port->port);
4119 return false;
b93433cc 4120 }
1b469639 4121
b93433cc 4122 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4123}
4124
7e66bcf2 4125static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4126 struct intel_digital_port *port)
a4fc5ed6 4127{
9642c81c 4128 u32 bit;
5eb08b69 4129
9642c81c
JN		 4130 switch (port->port) {
4131 case PORT_B:
4132 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4133 break;
4134 case PORT_C:
4135 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4136 break;
4137 case PORT_D:
4138 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4139 break;
4140 default:
4141 MISSING_CASE(port->port);
4142 return false;
4143 }
4144
4145 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4146}
4147
0780cd36
VS		 4148static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4149 struct intel_digital_port *port)
9642c81c
JN		 4150{
4151 u32 bit;
4152
4153 switch (port->port) {
4154 case PORT_B:
0780cd36 4155 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4156 break;
4157 case PORT_C:
0780cd36 4158 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4159 break;
4160 case PORT_D:
0780cd36 4161 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4162 break;
4163 default:
4164 MISSING_CASE(port->port);
4165 return false;
a4fc5ed6
KP		 4166 }
4167
1d245987 4168 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4169}
4170
e464bfde 4171static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4172 struct intel_digital_port *intel_dig_port)
e464bfde 4173{
e2ec35a5
SJ		 4174 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4175 enum port port;
e464bfde
JN		 4176 u32 bit;
4177
e2ec35a5
SJ		 4178 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4179 switch (port) {
e464bfde
JN		 4180 case PORT_A:
4181 bit = BXT_DE_PORT_HP_DDIA;
4182 break;
4183 case PORT_B:
4184 bit = BXT_DE_PORT_HP_DDIB;
4185 break;
4186 case PORT_C:
4187 bit = BXT_DE_PORT_HP_DDIC;
4188 break;
4189 default:
e2ec35a5 4190 MISSING_CASE(port);
e464bfde
JN		 4191 return false;
4192 }
4193
4194 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4195}
4196
7e66bcf2
JN		 4197/*
4198 * intel_digital_port_connected - is the specified port connected?
4199 * @dev_priv: i915 private structure
4200 * @port: the port to test
4201 *
4202 * Return %true if @port is connected, %false otherwise.
4203 */
23f889bd 4204static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4205 struct intel_digital_port *port)
4206{
0df53b77 4207 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4208 return ibx_digital_port_connected(dev_priv, port);
22824fac 4209 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4210 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4211 else if (IS_BROXTON(dev_priv))
4212 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4213 else if (IS_GM45(dev_priv))
4214 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4215 else
4216 return g4x_digital_port_connected(dev_priv, port);
4217}
4218
8c241fef 4219static struct edid *
beb60608 4220intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4221{
beb60608 4222 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4223
9cd300e0
JN		 4224 /* use cached edid if we have one */
4225 if (intel_connector->edid) {
9cd300e0
JN		 4226 /* invalid edid */
4227 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4228 return NULL;
4229
55e9edeb 4230 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4231 } else
4232 return drm_get_edid(&intel_connector->base,
4233 &intel_dp->aux.ddc);
4234}
8c241fef 4235
beb60608
CW		 4236static void
4237intel_dp_set_edid(struct intel_dp *intel_dp)
4238{
4239 struct intel_connector *intel_connector = intel_dp->attached_connector;
4240 struct edid *edid;
8c241fef 4241
f21a2198 4242 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4243 edid = intel_dp_get_edid(intel_dp);
4244 intel_connector->detect_edid = edid;
4245
4246 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4247 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4248 else
4249 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4250}
4251
beb60608
CW		 4252static void
4253intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4254{
beb60608 4255 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4256
beb60608
CW		 4257 kfree(intel_connector->detect_edid);
4258 intel_connector->detect_edid = NULL;
9cd300e0 4259
beb60608
CW		 4260 intel_dp->has_audio = false;
4261}
d6f24d0f 4262
f21a2198
SS		 4263static void
4264intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4265{
f21a2198 4266 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4267 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4269 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4270 struct drm_device *dev = connector->dev;
a9756bb5 4271 enum drm_connector_status status;
671dedd2 4272 enum intel_display_power_domain power_domain;
65fbb4e7 4273 u8 sink_irq_vector = 0;
a9756bb5 4274
25f78f58
VS		 4275 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4276 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4277
d410b56d
CW		 4278 /* Can't disconnect eDP, but you can close the lid... */
4279 if (is_edp(intel_dp))
4280 status = edp_detect(intel_dp);
c555a81d
ACO		 4281 else if (intel_digital_port_connected(to_i915(dev),
4282 dp_to_dig_port(intel_dp)))
4283 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4284 else
c555a81d
ACO		 4285 status = connector_status_disconnected;
4286
4df6960e
SS		 4287 if (status != connector_status_connected) {
4288 intel_dp->compliance_test_active = 0;
4289 intel_dp->compliance_test_type = 0;
4290 intel_dp->compliance_test_data = 0;
4291
0e505a08 4292 if (intel_dp->is_mst) {
4293 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4294 intel_dp->is_mst,
4295 intel_dp->mst_mgr.mst_state);
4296 intel_dp->is_mst = false;
4297 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4298 intel_dp->is_mst);
4299 }
4300
c8c8fb33 4301 goto out;
4df6960e 4302 }
a9756bb5 4303
f21a2198 4304 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4305 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198 4306
fe5a66f9
VS		 4307 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4308 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4309 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4310
4311 intel_dp_print_rates(intel_dp);
4312
0d198328
AJ		 4313 intel_dp_probe_oui(intel_dp);
4314
c4e3170a
VS		 4315 intel_dp_configure_mst(intel_dp);
4316
4317 if (intel_dp->is_mst) {
f21a2198
SS		 4318 /*
4319 * If we are in MST mode then this connector
4320 * won't appear connected or have anything
4321 * with EDID on it
4322 */
0e32b39c
DA		 4323 status = connector_status_disconnected;
4324 goto out;
7d23e3c3
SS		 4325 } else if (connector->status == connector_status_connected) {
4326 /*
4327 * If display was connected already and is still connected
4328 * check links status, there has been known issues of
4329 * link loss triggerring long pulse!!!!
4330 */
4331 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4332 intel_dp_check_link_status(intel_dp);
4333 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4334 goto out;
0e32b39c
DA		 4335 }
4336
4df6960e
SS		 4337 /*
4338 * Clearing NACK and defer counts to get their exact values
4339 * while reading EDID which are required by Compliance tests
4340 * 4.2.2.4 and 4.2.2.5
4341 */
4342 intel_dp->aux.i2c_nack_count = 0;
4343 intel_dp->aux.i2c_defer_count = 0;
4344
beb60608 4345 intel_dp_set_edid(intel_dp);
a9756bb5 4346
c8c8fb33 4347 status = connector_status_connected;
7d23e3c3 4348 intel_dp->detect_done = true;
c8c8fb33 4349
09b1eb13
TP		 4350 /* Try to read the source of the interrupt */
4351 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 4352 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4353 sink_irq_vector != 0) {
09b1eb13
TP		 4354 /* Clear interrupt source */
4355 drm_dp_dpcd_writeb(&intel_dp->aux,
4356 DP_DEVICE_SERVICE_IRQ_VECTOR,
4357 sink_irq_vector);
4358
4359 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4360 intel_dp_handle_test_request(intel_dp);
4361 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4362 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4363 }
4364
c8c8fb33 4365out:
0e505a08 4366 if ((status != connector_status_connected) &&
4367 (intel_dp->is_mst == false))
f21a2198 4368 intel_dp_unset_edid(intel_dp);
7d23e3c3 4369
25f78f58 4370 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4371 return;
4372}
4373
4374static enum drm_connector_status
4375intel_dp_detect(struct drm_connector *connector, bool force)
4376{
4377 struct intel_dp *intel_dp = intel_attached_dp(connector);
4378 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4379 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4380 struct intel_connector *intel_connector = to_intel_connector(connector);
4381
4382 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4383 connector->base.id, connector->name);
4384
4385 if (intel_dp->is_mst) {
4386 /* MST devices are disconnected from a monitor POV */
4387 intel_dp_unset_edid(intel_dp);
4388 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4389 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198
SS		 4390 return connector_status_disconnected;
4391 }
4392
7d23e3c3
SS		 4393 /* If full detect is not performed yet, do a full detect */
4394 if (!intel_dp->detect_done)
4395 intel_dp_long_pulse(intel_dp->attached_connector);
4396
4397 intel_dp->detect_done = false;
f21a2198 4398
1b7f2c8b 4399 if (is_edp(intel_dp) || intel_connector->detect_edid)
f21a2198
SS		 4400 return connector_status_connected;
4401 else
4402 return connector_status_disconnected;
a4fc5ed6
KP		 4403}
4404
beb60608
CW		 4405static void
4406intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4407{
df0e9248 4408 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4409 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4410 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4411 enum intel_display_power_domain power_domain;
a4fc5ed6 4412
beb60608
CW		 4413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4414 connector->base.id, connector->name);
4415 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4416
beb60608
CW		 4417 if (connector->status != connector_status_connected)
4418 return;
671dedd2 4419
25f78f58
VS		 4420 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4421 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4422
4423 intel_dp_set_edid(intel_dp);
4424
25f78f58 4425 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4426
4427 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4428 intel_encoder->type = INTEL_OUTPUT_DP;
beb60608
CW		 4429}
4430
4431static int intel_dp_get_modes(struct drm_connector *connector)
4432{
4433 struct intel_connector *intel_connector = to_intel_connector(connector);
4434 struct edid *edid;
4435
4436 edid = intel_connector->detect_edid;
4437 if (edid) {
4438 int ret = intel_connector_update_modes(connector, edid);
4439 if (ret)
4440 return ret;
4441 }
32f9d658 4442
f8779fda 4443 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4444 if (is_edp(intel_attached_dp(connector)) &&
4445 intel_connector->panel.fixed_mode) {
f8779fda 4446 struct drm_display_mode *mode;
beb60608
CW		 4447
4448 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4449 intel_connector->panel.fixed_mode);
f8779fda 4450 if (mode) {
32f9d658
ZW		 4451 drm_mode_probed_add(connector, mode);
4452 return 1;
4453 }
4454 }
beb60608 4455
32f9d658 4456 return 0;
a4fc5ed6
KP		 4457}
4458
1aad7ac0
CW		 4459static bool
4460intel_dp_detect_audio(struct drm_connector *connector)
4461{
1aad7ac0 4462 bool has_audio = false;
beb60608 4463 struct edid *edid;
1aad7ac0 4464
beb60608
CW		 4465 edid = to_intel_connector(connector)->detect_edid;
4466 if (edid)
1aad7ac0 4467 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4468
1aad7ac0
CW		 4469 return has_audio;
4470}
4471
f684960e
CW		 4472static int
4473intel_dp_set_property(struct drm_connector *connector,
4474 struct drm_property *property,
4475 uint64_t val)
4476{
fac5e23e 4477 struct drm_i915_private *dev_priv = to_i915(connector->dev);
53b41837 4478 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4479 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4480 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4481 int ret;
4482
662595df 4483 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4484 if (ret)
4485 return ret;
4486
3f43c48d 4487 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4488 int i = val;
4489 bool has_audio;
4490
4491 if (i == intel_dp->force_audio)
f684960e
CW		 4492 return 0;
4493
1aad7ac0 4494 intel_dp->force_audio = i;
f684960e 4495
c3e5f67b 4496 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4497 has_audio = intel_dp_detect_audio(connector);
4498 else
c3e5f67b 4499 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4500
4501 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4502 return 0;
4503
1aad7ac0 4504 intel_dp->has_audio = has_audio;
f684960e
CW		 4505 goto done;
4506 }
4507
e953fd7b 4508 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4509 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4510 bool old_range = intel_dp->limited_color_range;
ae4edb80 4511
55bc60db
VS		 4512 switch (val) {
4513 case INTEL_BROADCAST_RGB_AUTO:
4514 intel_dp->color_range_auto = true;
4515 break;
4516 case INTEL_BROADCAST_RGB_FULL:
4517 intel_dp->color_range_auto = false;
0f2a2a75 4518 intel_dp->limited_color_range = false;
55bc60db
VS		 4519 break;
4520 case INTEL_BROADCAST_RGB_LIMITED:
4521 intel_dp->color_range_auto = false;
0f2a2a75 4522 intel_dp->limited_color_range = true;
55bc60db
VS		 4523 break;
4524 default:
4525 return -EINVAL;
4526 }
ae4edb80
DV		 4527
4528 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4529 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4530 return 0;
4531
e953fd7b
CW		 4532 goto done;
4533 }
4534
53b41837
YN		 4535 if (is_edp(intel_dp) &&
4536 property == connector->dev->mode_config.scaling_mode_property) {
4537 if (val == DRM_MODE_SCALE_NONE) {
4538 DRM_DEBUG_KMS("no scaling not supported\n");
4539 return -EINVAL;
4540 }
234126c6
VS		 4541 if (HAS_GMCH_DISPLAY(dev_priv) &&
4542 val == DRM_MODE_SCALE_CENTER) {
4543 DRM_DEBUG_KMS("centering not supported\n");
4544 return -EINVAL;
4545 }
53b41837
YN		 4546
4547 if (intel_connector->panel.fitting_mode == val) {
4548 /* the eDP scaling property is not changed */
4549 return 0;
4550 }
4551 intel_connector->panel.fitting_mode = val;
4552
4553 goto done;
4554 }
4555
f684960e
CW		 4556 return -EINVAL;
4557
4558done:
c0c36b94
CW		 4559 if (intel_encoder->base.crtc)
4560 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4561
4562 return 0;
4563}
4564
7a418e34
CW		 4565static int
4566intel_dp_connector_register(struct drm_connector *connector)
4567{
4568 struct intel_dp *intel_dp = intel_attached_dp(connector);
1ebaa0b9
CW		 4569 int ret;
4570
4571 ret = intel_connector_register(connector);
4572 if (ret)
4573 return ret;
7a418e34
CW		 4574
4575 i915_debugfs_connector_add(connector);
4576
4577 DRM_DEBUG_KMS("registering %s bus for %s\n",
4578 intel_dp->aux.name, connector->kdev->kobj.name);
4579
4580 intel_dp->aux.dev = connector->kdev;
4581 return drm_dp_aux_register(&intel_dp->aux);
4582}
4583
c191eca1
CW		 4584static void
4585intel_dp_connector_unregister(struct drm_connector *connector)
4586{
4587 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4588 intel_connector_unregister(connector);
4589}
4590
a4fc5ed6 4591static void
73845adf 4592intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4593{
1d508706 4594 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4595
10e972d3 4596 kfree(intel_connector->detect_edid);
beb60608 4597
9cd300e0
JN		 4598 if (!IS_ERR_OR_NULL(intel_connector->edid))
4599 kfree(intel_connector->edid);
4600
acd8db10
PZ		 4601 /* Can't call is_edp() since the encoder may have been destroyed
4602 * already. */
4603 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4604 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4605
a4fc5ed6 4606 drm_connector_cleanup(connector);
55f78c43 4607 kfree(connector);
a4fc5ed6
KP		 4608}
4609
00c09d70 4610void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4611{
da63a9f2
PZ		 4612 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4613 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4614
0e32b39c 4615 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4616 if (is_edp(intel_dp)) {
4617 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4618 /*
4619 * vdd might still be enabled do to the delayed vdd off.
4620 * Make sure vdd is actually turned off here.
4621 */
773538e8 4622 pps_lock(intel_dp);
4be73780 4623 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4624 pps_unlock(intel_dp);
4625
01527b31
CT		 4626 if (intel_dp->edp_notifier.notifier_call) {
4627 unregister_reboot_notifier(&intel_dp->edp_notifier);
4628 intel_dp->edp_notifier.notifier_call = NULL;
4629 }
bd943159 4630 }
99681886
CW		 4631
4632 intel_dp_aux_fini(intel_dp);
4633
c8bd0e49 4634 drm_encoder_cleanup(encoder);
da63a9f2 4635 kfree(intel_dig_port);
24d05927
DV		 4636}
4637
bf93ba67 4638void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4639{
4640 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4641
4642 if (!is_edp(intel_dp))
4643 return;
4644
951468f3
VS		 4645 /*
4646 * vdd might still be enabled do to the delayed vdd off.
4647 * Make sure vdd is actually turned off here.
4648 */
afa4e53a 4649 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4650 pps_lock(intel_dp);
07f9cd0b 4651 edp_panel_vdd_off_sync(intel_dp);
773538e8 4652 pps_unlock(intel_dp);
07f9cd0b
ID		 4653}
4654
49e6bc51
VS		 4655static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4656{
4657 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4658 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4659 struct drm_i915_private *dev_priv = to_i915(dev);
49e6bc51
VS		 4660 enum intel_display_power_domain power_domain;
4661
4662 lockdep_assert_held(&dev_priv->pps_mutex);
4663
4664 if (!edp_have_panel_vdd(intel_dp))
4665 return;
4666
4667 /*
4668 * The VDD bit needs a power domain reference, so if the bit is
4669 * already enabled when we boot or resume, grab this reference and
4670 * schedule a vdd off, so we don't hold on to the reference
4671 * indefinitely.
4672 */
4673 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4674 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4675 intel_display_power_get(dev_priv, power_domain);
4676
4677 edp_panel_vdd_schedule_off(intel_dp);
4678}
4679
bf93ba67 4680void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4681{
64989ca4
VS		 4682 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4683 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4684
4685 if (!HAS_DDI(dev_priv))
4686 intel_dp->DP = I915_READ(intel_dp->output_reg);
49e6bc51
VS		 4687
4688 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4689 return;
4690
49e6bc51
VS		 4691 pps_lock(intel_dp);
4692
335f752b
ID		 4693 /* Reinit the power sequencer, in case BIOS did something with it. */
4694 intel_dp_pps_init(encoder->dev, intel_dp);
49e6bc51
VS		 4695 intel_edp_panel_vdd_sanitize(intel_dp);
4696
4697 pps_unlock(intel_dp);
6d93c0c4
ID		 4698}
4699
a4fc5ed6 4700static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4701 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4702 .detect = intel_dp_detect,
beb60608 4703 .force = intel_dp_force,
a4fc5ed6 4704 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4705 .set_property = intel_dp_set_property,
2545e4a6 4706 .atomic_get_property = intel_connector_atomic_get_property,
7a418e34 4707 .late_register = intel_dp_connector_register,
c191eca1 4708 .early_unregister = intel_dp_connector_unregister,
73845adf 4709 .destroy = intel_dp_connector_destroy,
c6f95f27 4710 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4711 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4712};
4713
4714static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4715 .get_modes = intel_dp_get_modes,
4716 .mode_valid = intel_dp_mode_valid,
a4fc5ed6
KP		 4717};
4718
a4fc5ed6 4719static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4720 .reset = intel_dp_encoder_reset,
24d05927 4721 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4722};
4723
b2c5c181 4724enum irqreturn
13cf5504
DA		 4725intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4726{
4727 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4728 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c 4729 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4730 struct drm_i915_private *dev_priv = to_i915(dev);
1c767b33 4731 enum intel_display_power_domain power_domain;
b2c5c181 4732 enum irqreturn ret = IRQ_NONE;
1c767b33 4733
2540058f
TI		 4734 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4735 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
cca0502b 4736 intel_dig_port->base.type = INTEL_OUTPUT_DP;
13cf5504 4737
7a7f84cc
VS		 4738 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4739 /*
4740 * vdd off can generate a long pulse on eDP which
4741 * would require vdd on to handle it, and thus we
4742 * would end up in an endless cycle of
4743 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4744 */
4745 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4746 port_name(intel_dig_port->port));
a8b3d52f 4747 return IRQ_HANDLED;
7a7f84cc
VS		 4748 }
4749
26fbb774
VS		 4750 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4751 port_name(intel_dig_port->port),
0e32b39c 4752 long_hpd ? "long" : "short");
13cf5504 4753
25f78f58 4754 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4755 intel_display_power_get(dev_priv, power_domain);
4756
0e32b39c 4757 if (long_hpd) {
7d23e3c3
SS		 4758 intel_dp_long_pulse(intel_dp->attached_connector);
4759 if (intel_dp->is_mst)
4760 ret = IRQ_HANDLED;
4761 goto put_power;
0e32b39c 4762
0e32b39c
DA		 4763 } else {
4764 if (intel_dp->is_mst) {
7d23e3c3
SS		 4765 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4766 /*
4767 * If we were in MST mode, and device is not
4768 * there, get out of MST mode
4769 */
4770 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4771 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4772 intel_dp->is_mst = false;
4773 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4774 intel_dp->is_mst);
4775 goto put_power;
4776 }
0e32b39c
DA		 4777 }
4778
39ff747b
SS		 4779 if (!intel_dp->is_mst) {
4780 if (!intel_dp_short_pulse(intel_dp)) {
4781 intel_dp_long_pulse(intel_dp->attached_connector);
4782 goto put_power;
4783 }
4784 }
0e32b39c 4785 }
b2c5c181
DV		 4786
4787 ret = IRQ_HANDLED;
4788
1c767b33
ID		 4789put_power:
4790 intel_display_power_put(dev_priv, power_domain);
4791
4792 return ret;
13cf5504
DA		 4793}
4794
477ec328 4795/* check the VBT to see whether the eDP is on another port */
5d8a7752 4796bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18 4797{
fac5e23e 4798 struct drm_i915_private *dev_priv = to_i915(dev);
36e83a18 4799
53ce81a7
VS		 4800 /*
4801 * eDP not supported on g4x. so bail out early just
4802 * for a bit extra safety in case the VBT is bonkers.
4803 */
4804 if (INTEL_INFO(dev)->gen < 5)
4805 return false;
4806
3b32a35b
VS		 4807 if (port == PORT_A)
4808 return true;
4809
951d9efe 4810 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4811}
4812
0e32b39c 4813void
f684960e
CW		 4814intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4815{
53b41837
YN		 4816 struct intel_connector *intel_connector = to_intel_connector(connector);
4817
3f43c48d 4818 intel_attach_force_audio_property(connector);
e953fd7b 4819 intel_attach_broadcast_rgb_property(connector);
55bc60db 4820 intel_dp->color_range_auto = true;
53b41837
YN		 4821
4822 if (is_edp(intel_dp)) {
4823 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4824 drm_object_attach_property(
4825 &connector->base,
53b41837 4826 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4827 DRM_MODE_SCALE_ASPECT);
4828 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4829 }
f684960e
CW		 4830}
4831
dada1a9f
ID		 4832static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4833{
d28d4731 4834 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4835 intel_dp->last_power_on = jiffies;
4836 intel_dp->last_backlight_off = jiffies;
4837}
4838
67a54566 4839static void
54648618
ID		 4840intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4841 struct intel_dp *intel_dp, struct edp_power_seq *seq)
67a54566 4842{
b0a08bec 4843 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 4844 struct pps_registers regs;
453c5420 4845
8e8232d5 4846 intel_pps_get_registers(dev_priv, intel_dp, &regs);
67a54566
DV		 4847
4848 /* Workaround: Need to write PP_CONTROL with the unlock key as
4849 * the very first thing. */
b0a08bec 4850 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4851
8e8232d5
ID		 4852 pp_on = I915_READ(regs.pp_on);
4853 pp_off = I915_READ(regs.pp_off);
54648618 4854 if (!IS_BROXTON(dev_priv)) {
8e8232d5
ID		 4855 I915_WRITE(regs.pp_ctrl, pp_ctl);
4856 pp_div = I915_READ(regs.pp_div);
b0a08bec 4857 }
67a54566
DV		 4858
4859 /* Pull timing values out of registers */
54648618
ID		 4860 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4861 PANEL_POWER_UP_DELAY_SHIFT;
67a54566 4862
54648618
ID		 4863 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4864 PANEL_LIGHT_ON_DELAY_SHIFT;
67a54566 4865
54648618
ID		 4866 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4867 PANEL_LIGHT_OFF_DELAY_SHIFT;
67a54566 4868
54648618
ID		 4869 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4870 PANEL_POWER_DOWN_DELAY_SHIFT;
67a54566 4871
54648618 4872 if (IS_BROXTON(dev_priv)) {
b0a08bec
VK		 4873 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4874 BXT_POWER_CYCLE_DELAY_SHIFT;
4875 if (tmp > 0)
54648618 4876 seq->t11_t12 = (tmp - 1) * 1000;
b0a08bec 4877 else
54648618 4878 seq->t11_t12 = 0;
b0a08bec 4879 } else {
54648618 4880 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4881 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4882 }
54648618
ID		 4883}
4884
de9c1b6b
ID		 4885static void
4886intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4887{
4888 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4889 state_name,
4890 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4891}
4892
4893static void
4894intel_pps_verify_state(struct drm_i915_private *dev_priv,
4895 struct intel_dp *intel_dp)
4896{
4897 struct edp_power_seq hw;
4898 struct edp_power_seq *sw = &intel_dp->pps_delays;
4899
4900 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4901
4902 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4903 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4904 DRM_ERROR("PPS state mismatch\n");
4905 intel_pps_dump_state("sw", sw);
4906 intel_pps_dump_state("hw", &hw);
4907 }
4908}
4909
54648618
ID		 4910static void
4911intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4912 struct intel_dp *intel_dp)
4913{
fac5e23e 4914 struct drm_i915_private *dev_priv = to_i915(dev);
54648618
ID		 4915 struct edp_power_seq cur, vbt, spec,
4916 *final = &intel_dp->pps_delays;
4917
4918 lockdep_assert_held(&dev_priv->pps_mutex);
4919
4920 /* already initialized? */
4921 if (final->t11_t12 != 0)
4922 return;
4923
4924 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
67a54566 4925
de9c1b6b 4926 intel_pps_dump_state("cur", &cur);
67a54566 4927
6aa23e65 4928 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 4929
4930 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4931 * our hw here, which are all in 100usec. */
4932 spec.t1_t3 = 210 * 10;
4933 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4934 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4935 spec.t10 = 500 * 10;
4936 /* This one is special and actually in units of 100ms, but zero
4937 * based in the hw (so we need to add 100 ms). But the sw vbt
4938 * table multiplies it with 1000 to make it in units of 100usec,
4939 * too. */
4940 spec.t11_t12 = (510 + 100) * 10;
4941
de9c1b6b 4942 intel_pps_dump_state("vbt", &vbt);
67a54566
DV		 4943
4944 /* Use the max of the register settings and vbt. If both are
4945 * unset, fall back to the spec limits. */
36b5f425 4946#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4947 spec.field : \
4948 max(cur.field, vbt.field))
4949 assign_final(t1_t3);
4950 assign_final(t8);
4951 assign_final(t9);
4952 assign_final(t10);
4953 assign_final(t11_t12);
4954#undef assign_final
4955
36b5f425 4956#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4957 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4958 intel_dp->backlight_on_delay = get_delay(t8);
4959 intel_dp->backlight_off_delay = get_delay(t9);
4960 intel_dp->panel_power_down_delay = get_delay(t10);
4961 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4962#undef get_delay
4963
f30d26e4
JN		 4964 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4965 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4966 intel_dp->panel_power_cycle_delay);
4967
4968 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4969 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
de9c1b6b
ID		 4970
4971 /*
4972 * We override the HW backlight delays to 1 because we do manual waits
4973 * on them. For T8, even BSpec recommends doing it. For T9, if we
4974 * don't do this, we'll end up waiting for the backlight off delay
4975 * twice: once when we do the manual sleep, and once when we disable
4976 * the panel and wait for the PP_STATUS bit to become zero.
4977 */
4978 final->t8 = 1;
4979 final->t9 = 1;
f30d26e4
JN		 4980}
4981
4982static void
4983intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4984 struct intel_dp *intel_dp)
f30d26e4 4985{
fac5e23e 4986 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 4987 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 4988 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 4989 struct pps_registers regs;
ad933b56 4990 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4991 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4992
e39b999a 4993 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 4994
8e8232d5 4995 intel_pps_get_registers(dev_priv, intel_dp, &regs);
453c5420 4996
f30d26e4 4997 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
de9c1b6b
ID		 4998 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
4999 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5000 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5001 /* Compute the divisor for the pp clock, simply match the Bspec
5002 * formula. */
b0a08bec 5003 if (IS_BROXTON(dev)) {
8e8232d5 5004 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec
VK		 5005 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5006 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5007 << BXT_POWER_CYCLE_DELAY_SHIFT);
5008 } else {
5009 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5010 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5011 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5012 }
67a54566
DV		 5013
5014 /* Haswell doesn't have any port selection bits for the panel
5015 * power sequencer any more. */
666a4537 5016 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 5017 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5018 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5019 if (port == PORT_A)
a24c144c 5020 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5021 else
a24c144c 5022 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5023 }
5024
453c5420
JB		 5025 pp_on |= port_sel;
5026
8e8232d5
ID		 5027 I915_WRITE(regs.pp_on, pp_on);
5028 I915_WRITE(regs.pp_off, pp_off);
b0a08bec 5029 if (IS_BROXTON(dev))
8e8232d5 5030 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 5031 else
8e8232d5 5032 I915_WRITE(regs.pp_div, pp_div);
67a54566 5033
67a54566 5034 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 5035 I915_READ(regs.pp_on),
5036 I915_READ(regs.pp_off),
b0a08bec 5037 IS_BROXTON(dev) ?
8e8232d5
ID		 5038 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5039 I915_READ(regs.pp_div));
f684960e
CW		 5040}
5041
335f752b
ID		 5042static void intel_dp_pps_init(struct drm_device *dev,
5043 struct intel_dp *intel_dp)
5044{
5045 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5046 vlv_initial_power_sequencer_setup(intel_dp);
5047 } else {
5048 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5049 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5050 }
5051}
5052
b33a2815
VK		 5053/**
5054 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5423adf1 5055 * @dev_priv: i915 device
e896402c 5056 * @crtc_state: a pointer to the active intel_crtc_state
b33a2815
VK		 5057 * @refresh_rate: RR to be programmed
5058 *
5059 * This function gets called when refresh rate (RR) has to be changed from
5060 * one frequency to another. Switches can be between high and low RR
5061 * supported by the panel or to any other RR based on media playback (in
5062 * this case, RR value needs to be passed from user space).
5063 *
5064 * The caller of this function needs to take a lock on dev_priv->drrs.
5065 */
85cb48a1
ML		 5066static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5067 struct intel_crtc_state *crtc_state,
5068 int refresh_rate)
439d7ac0 5069{
439d7ac0 5070 struct intel_encoder *encoder;
96178eeb
VK		 5071 struct intel_digital_port *dig_port = NULL;
5072 struct intel_dp *intel_dp = dev_priv->drrs.dp;
85cb48a1 5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
96178eeb 5074 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5075
5076 if (refresh_rate <= 0) {
5077 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5078 return;
5079 }
5080
96178eeb
VK		 5081 if (intel_dp == NULL) {
5082 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5083 return;
5084 }
5085
1fcc9d1c 5086 /*
e4d59f6b
RV		 5087 * FIXME: This needs proper synchronization with psr state for some
5088 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5089 */
439d7ac0 5090
96178eeb
VK		 5091 dig_port = dp_to_dig_port(intel_dp);
5092 encoder = &dig_port->base;
723f9aab 5093 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5094
5095 if (!intel_crtc) {
5096 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5097 return;
5098 }
5099
96178eeb 5100 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5101 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5102 return;
5103 }
5104
96178eeb
VK		 5105 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5106 refresh_rate)
439d7ac0
PB		 5107 index = DRRS_LOW_RR;
5108
96178eeb 5109 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5110 DRM_DEBUG_KMS(
5111 "DRRS requested for previously set RR...ignoring\n");
5112 return;
5113 }
5114
85cb48a1 5115 if (!crtc_state->base.active) {
439d7ac0
PB		 5116 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5117 return;
5118 }
5119
85cb48a1 5120 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
a4c30b1d
VK		 5121 switch (index) {
5122 case DRRS_HIGH_RR:
5123 intel_dp_set_m_n(intel_crtc, M1_N1);
5124 break;
5125 case DRRS_LOW_RR:
5126 intel_dp_set_m_n(intel_crtc, M2_N2);
5127 break;
5128 case DRRS_MAX_RR:
5129 default:
5130 DRM_ERROR("Unsupported refreshrate type\n");
5131 }
85cb48a1
ML		 5132 } else if (INTEL_GEN(dev_priv) > 6) {
5133 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
649636ef 5134 u32 val;
a4c30b1d 5135
649636ef 5136 val = I915_READ(reg);
439d7ac0 5137 if (index > DRRS_HIGH_RR) {
85cb48a1 5138 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 5139 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5140 else
5141 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5142 } else {
85cb48a1 5143 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 5144 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5145 else
5146 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5147 }
5148 I915_WRITE(reg, val);
5149 }
5150
4e9ac947
VK		 5151 dev_priv->drrs.refresh_rate_type = index;
5152
5153 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5154}
5155
b33a2815
VK		 5156/**
5157 * intel_edp_drrs_enable - init drrs struct if supported
5158 * @intel_dp: DP struct
5423adf1 5159 * @crtc_state: A pointer to the active crtc state.
b33a2815
VK		 5160 *
5161 * Initializes frontbuffer_bits and drrs.dp
5162 */
85cb48a1
ML		 5163void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5164 struct intel_crtc_state *crtc_state)
c395578e
VK		 5165{
5166 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5167 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e 5168
85cb48a1 5169 if (!crtc_state->has_drrs) {
c395578e
VK		 5170 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5171 return;
5172 }
5173
5174 mutex_lock(&dev_priv->drrs.mutex);
5175 if (WARN_ON(dev_priv->drrs.dp)) {
5176 DRM_ERROR("DRRS already enabled\n");
5177 goto unlock;
5178 }
5179
5180 dev_priv->drrs.busy_frontbuffer_bits = 0;
5181
5182 dev_priv->drrs.dp = intel_dp;
5183
5184unlock:
5185 mutex_unlock(&dev_priv->drrs.mutex);
5186}
5187
b33a2815
VK		 5188/**
5189 * intel_edp_drrs_disable - Disable DRRS
5190 * @intel_dp: DP struct
5423adf1 5191 * @old_crtc_state: Pointer to old crtc_state.
b33a2815
VK		 5192 *
5193 */
85cb48a1
ML		 5194void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5195 struct intel_crtc_state *old_crtc_state)
c395578e
VK		 5196{
5197 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5198 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e 5199
85cb48a1 5200 if (!old_crtc_state->has_drrs)
c395578e
VK		 5201 return;
5202
5203 mutex_lock(&dev_priv->drrs.mutex);
5204 if (!dev_priv->drrs.dp) {
5205 mutex_unlock(&dev_priv->drrs.mutex);
5206 return;
5207 }
5208
5209 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5210 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5211 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
c395578e
VK		 5212
5213 dev_priv->drrs.dp = NULL;
5214 mutex_unlock(&dev_priv->drrs.mutex);
5215
5216 cancel_delayed_work_sync(&dev_priv->drrs.work);
5217}
5218
4e9ac947
VK		 5219static void intel_edp_drrs_downclock_work(struct work_struct *work)
5220{
5221 struct drm_i915_private *dev_priv =
5222 container_of(work, typeof(*dev_priv), drrs.work.work);
5223 struct intel_dp *intel_dp;
5224
5225 mutex_lock(&dev_priv->drrs.mutex);
5226
5227 intel_dp = dev_priv->drrs.dp;
5228
5229 if (!intel_dp)
5230 goto unlock;
5231
439d7ac0 5232 /*
4e9ac947
VK		 5233 * The delayed work can race with an invalidate hence we need to
5234 * recheck.
439d7ac0
PB		 5235 */
5236
4e9ac947
VK		 5237 if (dev_priv->drrs.busy_frontbuffer_bits)
5238 goto unlock;
439d7ac0 5239
85cb48a1
ML		 5240 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5241 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5242
5243 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5244 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5245 }
439d7ac0 5246
4e9ac947 5247unlock:
4e9ac947 5248 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5249}
5250
b33a2815 5251/**
0ddfd203 5252 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5748b6a1 5253 * @dev_priv: i915 device
b33a2815
VK		 5254 * @frontbuffer_bits: frontbuffer plane tracking bits
5255 *
0ddfd203
R		 5256 * This function gets called everytime rendering on the given planes start.
5257 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5258 *
5259 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5260 */
5748b6a1
CW		 5261void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5262 unsigned int frontbuffer_bits)
a93fad0f 5263{
a93fad0f
VK		 5264 struct drm_crtc *crtc;
5265 enum pipe pipe;
5266
9da7d693 5267 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5268 return;
5269
88f933a8 5270 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5271
a93fad0f 5272 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5273 if (!dev_priv->drrs.dp) {
5274 mutex_unlock(&dev_priv->drrs.mutex);
5275 return;
5276 }
5277
a93fad0f
VK		 5278 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5279 pipe = to_intel_crtc(crtc)->pipe;
5280
c1d038c6
DV		 5281 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5282 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5283
0ddfd203 5284 /* invalidate means busy screen hence upclock */
c1d038c6 5285 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5286 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5287 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
a93fad0f 5288
a93fad0f
VK		 5289 mutex_unlock(&dev_priv->drrs.mutex);
5290}
5291
b33a2815 5292/**
0ddfd203 5293 * intel_edp_drrs_flush - Restart Idleness DRRS
5748b6a1 5294 * @dev_priv: i915 device
b33a2815
VK		 5295 * @frontbuffer_bits: frontbuffer plane tracking bits
5296 *
0ddfd203
R		 5297 * This function gets called every time rendering on the given planes has
5298 * completed or flip on a crtc is completed. So DRRS should be upclocked
5299 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5300 * if no other planes are dirty.
b33a2815
VK		 5301 *
5302 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5303 */
5748b6a1
CW		 5304void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5305 unsigned int frontbuffer_bits)
a93fad0f 5306{
a93fad0f
VK		 5307 struct drm_crtc *crtc;
5308 enum pipe pipe;
5309
9da7d693 5310 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5311 return;
5312
88f933a8 5313 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5314
a93fad0f 5315 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5316 if (!dev_priv->drrs.dp) {
5317 mutex_unlock(&dev_priv->drrs.mutex);
5318 return;
5319 }
5320
a93fad0f
VK		 5321 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5322 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5323
5324 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5325 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5326
0ddfd203 5327 /* flush means busy screen hence upclock */
c1d038c6 5328 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5329 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5330 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
0ddfd203
R		 5331
5332 /*
5333 * flush also means no more activity hence schedule downclock, if all
5334 * other fbs are quiescent too
5335 */
5336 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5337 schedule_delayed_work(&dev_priv->drrs.work,
5338 msecs_to_jiffies(1000));
5339 mutex_unlock(&dev_priv->drrs.mutex);
5340}
5341
b33a2815
VK		 5342/**
5343 * DOC: Display Refresh Rate Switching (DRRS)
5344 *
5345 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5346 * which enables swtching between low and high refresh rates,
5347 * dynamically, based on the usage scenario. This feature is applicable
5348 * for internal panels.
5349 *
5350 * Indication that the panel supports DRRS is given by the panel EDID, which
5351 * would list multiple refresh rates for one resolution.
5352 *
5353 * DRRS is of 2 types - static and seamless.
5354 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5355 * (may appear as a blink on screen) and is used in dock-undock scenario.
5356 * Seamless DRRS involves changing RR without any visual effect to the user
5357 * and can be used during normal system usage. This is done by programming
5358 * certain registers.
5359 *
5360 * Support for static/seamless DRRS may be indicated in the VBT based on
5361 * inputs from the panel spec.
5362 *
5363 * DRRS saves power by switching to low RR based on usage scenarios.
5364 *
2e7a5701
DV		 5365 * The implementation is based on frontbuffer tracking implementation. When
5366 * there is a disturbance on the screen triggered by user activity or a periodic
5367 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5368 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5369 * made.
5370 *
5371 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5372 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 5373 *
5374 * DRRS can be further extended to support other internal panels and also
5375 * the scenario of video playback wherein RR is set based on the rate
5376 * requested by userspace.
5377 */
5378
5379/**
5380 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5381 * @intel_connector: eDP connector
5382 * @fixed_mode: preferred mode of panel
5383 *
5384 * This function is called only once at driver load to initialize basic
5385 * DRRS stuff.
5386 *
5387 * Returns:
5388 * Downclock mode if panel supports it, else return NULL.
5389 * DRRS support is determined by the presence of downclock mode (apart
5390 * from VBT setting).
5391 */
4f9db5b5 5392static struct drm_display_mode *
96178eeb
VK		 5393intel_dp_drrs_init(struct intel_connector *intel_connector,
5394 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5395{
5396 struct drm_connector *connector = &intel_connector->base;
96178eeb 5397 struct drm_device *dev = connector->dev;
fac5e23e 5398 struct drm_i915_private *dev_priv = to_i915(dev);
4f9db5b5
PB		 5399 struct drm_display_mode *downclock_mode = NULL;
5400
9da7d693
DV		 5401 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5402 mutex_init(&dev_priv->drrs.mutex);
5403
4f9db5b5
PB		 5404 if (INTEL_INFO(dev)->gen <= 6) {
5405 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5406 return NULL;
5407 }
5408
5409 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5410 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5411 return NULL;
5412 }
5413
5414 downclock_mode = intel_find_panel_downclock
5415 (dev, fixed_mode, connector);
5416
5417 if (!downclock_mode) {
a1d26342 5418 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5419 return NULL;
5420 }
5421
96178eeb 5422 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5423
96178eeb 5424 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5425 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5426 return downclock_mode;
5427}
5428
ed92f0b2 5429static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5430 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5431{
5432 struct drm_connector *connector = &intel_connector->base;
5433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5434 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5435 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5436 struct drm_i915_private *dev_priv = to_i915(dev);
ed92f0b2 5437 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5438 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5439 bool has_dpcd;
5440 struct drm_display_mode *scan;
5441 struct edid *edid;
6517d273 5442 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5443
5444 if (!is_edp(intel_dp))
5445 return true;
5446
97a824e1
ID		 5447 /*
5448 * On IBX/CPT we may get here with LVDS already registered. Since the
5449 * driver uses the only internal power sequencer available for both
5450 * eDP and LVDS bail out early in this case to prevent interfering
5451 * with an already powered-on LVDS power sequencer.
5452 */
5453 if (intel_get_lvds_encoder(dev)) {
5454 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5455 DRM_INFO("LVDS was detected, not registering eDP\n");
5456
5457 return false;
5458 }
5459
49e6bc51 5460 pps_lock(intel_dp);
b4d06ede
ID		 5461
5462 intel_dp_init_panel_power_timestamps(intel_dp);
335f752b 5463 intel_dp_pps_init(dev, intel_dp);
49e6bc51 5464 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 5465
49e6bc51 5466 pps_unlock(intel_dp);
63635217 5467
ed92f0b2 5468 /* Cache DPCD and EDID for edp. */
fe5a66f9 5469 has_dpcd = intel_edp_init_dpcd(intel_dp);
ed92f0b2 5470
fe5a66f9 5471 if (!has_dpcd) {
ed92f0b2
PZ		 5472 /* if this fails, presume the device is a ghost */
5473 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 5474 goto out_vdd_off;
ed92f0b2
PZ		 5475 }
5476
060c8778 5477 mutex_lock(&dev->mode_config.mutex);
0b99836f 5478 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5479 if (edid) {
5480 if (drm_add_edid_modes(connector, edid)) {
5481 drm_mode_connector_update_edid_property(connector,
5482 edid);
5483 drm_edid_to_eld(connector, edid);
5484 } else {
5485 kfree(edid);
5486 edid = ERR_PTR(-EINVAL);
5487 }
5488 } else {
5489 edid = ERR_PTR(-ENOENT);
5490 }
5491 intel_connector->edid = edid;
5492
5493 /* prefer fixed mode from EDID if available */
5494 list_for_each_entry(scan, &connector->probed_modes, head) {
5495 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5496 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5497 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5498 intel_connector, fixed_mode);
ed92f0b2
PZ		 5499 break;
5500 }
5501 }
5502
5503 /* fallback to VBT if available for eDP */
5504 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5505 fixed_mode = drm_mode_duplicate(dev,
5506 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 5507 if (fixed_mode) {
ed92f0b2 5508 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 5509 connector->display_info.width_mm = fixed_mode->width_mm;
5510 connector->display_info.height_mm = fixed_mode->height_mm;
5511 }
ed92f0b2 5512 }
060c8778 5513 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5514
666a4537 5515 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5516 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5517 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5518
5519 /*
5520 * Figure out the current pipe for the initial backlight setup.
5521 * If the current pipe isn't valid, try the PPS pipe, and if that
5522 * fails just assume pipe A.
5523 */
5524 if (IS_CHERRYVIEW(dev))
5525 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5526 else
5527 pipe = PORT_TO_PIPE(intel_dp->DP);
5528
5529 if (pipe != PIPE_A && pipe != PIPE_B)
5530 pipe = intel_dp->pps_pipe;
5531
5532 if (pipe != PIPE_A && pipe != PIPE_B)
5533 pipe = PIPE_A;
5534
5535 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5536 pipe_name(pipe));
01527b31
CT		 5537 }
5538
4f9db5b5 5539 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5540 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5541 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5542
5543 return true;
b4d06ede
ID		 5544
5545out_vdd_off:
5546 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5547 /*
5548 * vdd might still be enabled do to the delayed vdd off.
5549 * Make sure vdd is actually turned off here.
5550 */
5551 pps_lock(intel_dp);
5552 edp_panel_vdd_off_sync(intel_dp);
5553 pps_unlock(intel_dp);
5554
5555 return false;
ed92f0b2
PZ		 5556}
5557
16c25533 5558bool
f0fec3f2
PZ		 5559intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5560 struct intel_connector *intel_connector)
a4fc5ed6 5561{
f0fec3f2
PZ		 5562 struct drm_connector *connector = &intel_connector->base;
5563 struct intel_dp *intel_dp = &intel_dig_port->dp;
5564 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5565 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5566 struct drm_i915_private *dev_priv = to_i915(dev);
174edf1f 5567 enum port port = intel_dig_port->port;
7a418e34 5568 int type;
a4fc5ed6 5569
ccb1a831
VS		 5570 if (WARN(intel_dig_port->max_lanes < 1,
5571 "Not enough lanes (%d) for DP on port %c\n",
5572 intel_dig_port->max_lanes, port_name(port)))
5573 return false;
5574
a4a5d2f8
VS		 5575 intel_dp->pps_pipe = INVALID_PIPE;
5576
ec5b01dd 5577 /* intel_dp vfuncs */
b6b5e383
DL		 5578 if (INTEL_INFO(dev)->gen >= 9)
5579 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5580 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5581 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5582 else if (HAS_PCH_SPLIT(dev))
5583 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5584 else
6ffb1be7 5585 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5586
b9ca5fad
DL		 5587 if (INTEL_INFO(dev)->gen >= 9)
5588 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5589 else
6ffb1be7 5590 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5591
ad64217b
ACO		 5592 if (HAS_DDI(dev))
5593 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5594
0767935e
DV		 5595 /* Preserve the current hw state. */
5596 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5597 intel_dp->attached_connector = intel_connector;
3d3dc149 5598
3b32a35b 5599 if (intel_dp_is_edp(dev, port))
b329530c 5600 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5601 else
5602 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5603
f7d24902
ID		 5604 /*
5605 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5606 * for DP the encoder type can be set by the caller to
5607 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5608 */
5609 if (type == DRM_MODE_CONNECTOR_eDP)
5610 intel_encoder->type = INTEL_OUTPUT_EDP;
5611
c17ed5b5 5612 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5613 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5614 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5615 return false;
5616
e7281eab
ID		 5617 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5618 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5619 port_name(port));
5620
b329530c 5621 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5622 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5623
a4fc5ed6
KP		 5624 connector->interlace_allowed = true;
5625 connector->doublescan_allowed = 0;
5626
7a418e34
CW		 5627 intel_dp_aux_init(intel_dp, intel_connector);
5628
f0fec3f2 5629 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5630 edp_panel_vdd_work);
a4fc5ed6 5631
df0e9248 5632 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6 5633
affa9354 5634 if (HAS_DDI(dev))
bcbc889b
PZ		 5635 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5636 else
5637 intel_connector->get_hw_state = intel_connector_get_hw_state;
5638
0b99836f 5639 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5640 switch (port) {
5641 case PORT_A:
1d843f9d 5642 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5643 break;
5644 case PORT_B:
1d843f9d 5645 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5646 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5647 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5648 break;
5649 case PORT_C:
1d843f9d 5650 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5651 break;
5652 case PORT_D:
1d843f9d 5653 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5654 break;
26951caf
XZ		 5655 case PORT_E:
5656 intel_encoder->hpd_pin = HPD_PORT_E;
5657 break;
ab9d7c30 5658 default:
ad1c0b19 5659 BUG();
5eb08b69
ZW		 5660 }
5661
0e32b39c 5662 /* init MST on ports that can support it */
f8e58ddf 5663 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
0c9b3715
JN		 5664 (port == PORT_B || port == PORT_C || port == PORT_D))
5665 intel_dp_mst_encoder_init(intel_dig_port,
5666 intel_connector->base.base.id);
0e32b39c 5667
36b5f425 5668 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5669 intel_dp_aux_fini(intel_dp);
5670 intel_dp_mst_encoder_cleanup(intel_dig_port);
5671 goto fail;
b2f246a8 5672 }
32f9d658 5673
f684960e
CW		 5674 intel_dp_add_properties(intel_dp, connector);
5675
a4fc5ed6
KP		 5676 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5677 * 0xd. Failure to do so will result in spurious interrupts being
5678 * generated on the port when a cable is not attached.
5679 */
5680 if (IS_G4X(dev) && !IS_GM45(dev)) {
5681 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5682 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5683 }
16c25533
PZ		 5684
5685 return true;
a121f4e5
VS		 5686
5687fail:
a121f4e5
VS		 5688 drm_connector_cleanup(connector);
5689
5690 return false;
a4fc5ed6 5691}
f0fec3f2 5692
457c52d8
CW		 5693bool intel_dp_init(struct drm_device *dev,
5694 i915_reg_t output_reg,
5695 enum port port)
f0fec3f2 5696{
fac5e23e 5697 struct drm_i915_private *dev_priv = to_i915(dev);
f0fec3f2
PZ		 5698 struct intel_digital_port *intel_dig_port;
5699 struct intel_encoder *intel_encoder;
5700 struct drm_encoder *encoder;
5701 struct intel_connector *intel_connector;
5702
b14c5679 5703 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 5704 if (!intel_dig_port)
457c52d8 5705 return false;
f0fec3f2 5706
08d9bc92 5707 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5708 if (!intel_connector)
5709 goto err_connector_alloc;
f0fec3f2
PZ		 5710
5711 intel_encoder = &intel_dig_port->base;
5712 encoder = &intel_encoder->base;
5713
893da0c9 5714 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
580d8ed5 5715 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
893da0c9 5716 goto err_encoder_init;
f0fec3f2 5717
5bfe2ac0 5718 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5719 intel_encoder->disable = intel_disable_dp;
00c09d70 5720 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5721 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5722 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5723 if (IS_CHERRYVIEW(dev)) {
9197c88b 5724 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5725 intel_encoder->pre_enable = chv_pre_enable_dp;
5726 intel_encoder->enable = vlv_enable_dp;
580d3811 5727 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5728 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5729 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5730 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5731 intel_encoder->pre_enable = vlv_pre_enable_dp;
5732 intel_encoder->enable = vlv_enable_dp;
49277c31 5733 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5734 } else {
ecff4f3b
JN		 5735 intel_encoder->pre_enable = g4x_pre_enable_dp;
5736 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5737 if (INTEL_INFO(dev)->gen >= 5)
5738 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5739 }
f0fec3f2 5740
174edf1f 5741 intel_dig_port->port = port;
f0fec3f2 5742 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5743 intel_dig_port->max_lanes = 4;
f0fec3f2 5744
cca0502b 5745 intel_encoder->type = INTEL_OUTPUT_DP;
882ec384
VS		 5746 if (IS_CHERRYVIEW(dev)) {
5747 if (port == PORT_D)
5748 intel_encoder->crtc_mask = 1 << 2;
5749 else
5750 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5751 } else {
5752 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5753 }
bc079e8b 5754 intel_encoder->cloneable = 0;
f0fec3f2 5755
13cf5504 5756 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5757 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5758
11aee0f6
SM		 5759 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5760 goto err_init_connector;
5761
457c52d8 5762 return true;
11aee0f6
SM		 5763
5764err_init_connector:
5765 drm_encoder_cleanup(encoder);
893da0c9 5766err_encoder_init:
11aee0f6
SM		 5767 kfree(intel_connector);
5768err_connector_alloc:
5769 kfree(intel_dig_port);
457c52d8 5770 return false;
f0fec3f2 5771}
0e32b39c
DA		 5772
5773void intel_dp_mst_suspend(struct drm_device *dev)
5774{
fac5e23e 5775 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5776 int i;
5777
5778 /* disable MST */
5779 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5780 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969
VS		 5781
5782 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
0e32b39c
DA		 5783 continue;
5784
5aa56969
VS		 5785 if (intel_dig_port->dp.is_mst)
5786 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
0e32b39c
DA		 5787 }
5788}
5789
5790void intel_dp_mst_resume(struct drm_device *dev)
5791{
fac5e23e 5792 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5793 int i;
5794
5795 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5796 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969 5797 int ret;
0e32b39c 5798
5aa56969
VS		 5799 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5800 continue;
0e32b39c 5801
5aa56969
VS		 5802 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5803 if (ret)
5804 intel_dp_check_mst_status(&intel_dig_port->dp);
0e32b39c
DA		 5805 }
5806}
Linux kernel - Deliverables
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