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drm/i915/bxt: VSwing programming sequence
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
9dd4ffdf
CML		 44struct dp_link_dpll {
45 int link_bw;
46 struct dpll dpll;
47};
48
49static const struct dp_link_dpll gen4_dpll[] = {
50 { DP_LINK_BW_1_62,
51 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
52 { DP_LINK_BW_2_7,
53 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
54};
55
56static const struct dp_link_dpll pch_dpll[] = {
57 { DP_LINK_BW_1_62,
58 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
59 { DP_LINK_BW_2_7,
60 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
61};
62
65ce4bf5
CML		 63static const struct dp_link_dpll vlv_dpll[] = {
64 { DP_LINK_BW_1_62,
58f6e632 65 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 66 { DP_LINK_BW_2_7,
67 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
68};
69
ef9348c8
CML		 70/*
71 * CHV supports eDP 1.4 that have more link rates.
72 * Below only provides the fixed rate but exclude variable rate.
73 */
74static const struct dp_link_dpll chv_dpll[] = {
75 /*
76 * CHV requires to program fractional division for m2.
77 * m2 is stored in fixed point format using formula below
78 * (m2_int << 22) | m2_fraction
79 */
80 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
81 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
82 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
83 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
84 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
85 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
86};
a8f3ef61 87/* Skylake supports following rates */
f4896f15
VS		 88static const int gen9_rates[] = { 162000, 216000, 270000,
89 324000, 432000, 540000 };
fe51bfb9
VS		 90static const int chv_rates[] = { 162000, 202500, 210000, 216000,
91 243000, 270000, 324000, 405000,
92 420000, 432000, 540000 };
f4896f15 93static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 94
cfcb0fc9
JB		 95/**
96 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
97 * @intel_dp: DP struct
98 *
99 * If a CPU or PCH DP output is attached to an eDP panel, this function
100 * will return true, and false otherwise.
101 */
102static bool is_edp(struct intel_dp *intel_dp)
103{
da63a9f2
PZ		 104 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
105
106 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 107}
108
68b4d824 109static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 110{
68b4d824
ID		 111 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
112
113 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 114}
115
df0e9248
CW		 116static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
117{
fa90ecef 118 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 119}
120
ea5b213a 121static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 122static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 123static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 124static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 125static void vlv_steal_power_sequencer(struct drm_device *dev,
126 enum pipe pipe);
a4fc5ed6 127
ed4e9c1d
VS		 128static int
129intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 130{
7183dc29 131 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 132
133 switch (max_link_bw) {
134 case DP_LINK_BW_1_62:
135 case DP_LINK_BW_2_7:
1db10e28 136 case DP_LINK_BW_5_4:
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
50fec21a 212 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
a4f1289e 230uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 231{
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240}
241
c2af70e2 242static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 331 bool pll_enabled;
961a0db0
VS		 332 uint32_t DP;
333
334 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe), port_name(intel_dig_port->port)))
337 return;
338
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe), port_name(intel_dig_port->port));
341
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
344 */
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
346 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
347 DP |= DP_PORT_WIDTH(1);
348 DP |= DP_LINK_TRAIN_PAT_1;
349
350 if (IS_CHERRYVIEW(dev))
351 DP |= DP_PIPE_SELECT_CHV(pipe);
352 else if (pipe == PIPE_B)
353 DP |= DP_PIPEB_SELECT;
354
d288f65f
VS		 355 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
356
357 /*
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
360 */
361 if (!pll_enabled)
362 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
364
961a0db0
VS		 365 /*
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
370 */
371 I915_WRITE(intel_dp->output_reg, DP);
372 POSTING_READ(intel_dp->output_reg);
373
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
375 POSTING_READ(intel_dp->output_reg);
376
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
378 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 379
380 if (!pll_enabled)
381 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 382}
383
bf13e81b
JN		 384static enum pipe
385vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
386{
387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 388 struct drm_device *dev = intel_dig_port->base.base.dev;
389 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 390 struct intel_encoder *encoder;
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 392 enum pipe pipe;
bf13e81b 393
e39b999a 394 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 395
a8c3344e
VS		 396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp));
398
a4a5d2f8
VS		 399 if (intel_dp->pps_pipe != INVALID_PIPE)
400 return intel_dp->pps_pipe;
401
402 /*
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
405 */
406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
407 base.head) {
408 struct intel_dp *tmp;
409
410 if (encoder->type != INTEL_OUTPUT_EDP)
411 continue;
412
413 tmp = enc_to_intel_dp(&encoder->base);
414
415 if (tmp->pps_pipe != INVALID_PIPE)
416 pipes &= ~(1 << tmp->pps_pipe);
417 }
418
419 /*
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
422 */
423 if (WARN_ON(pipes == 0))
a8c3344e
VS		 424 pipe = PIPE_A;
425 else
426 pipe = ffs(pipes) - 1;
a4a5d2f8 427
a8c3344e
VS		 428 vlv_steal_power_sequencer(dev, pipe);
429 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 430
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp->pps_pipe),
433 port_name(intel_dig_port->port));
434
435 /* init power sequencer on this pipe and port */
36b5f425
VS		 436 intel_dp_init_panel_power_sequencer(dev, intel_dp);
437 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 438
961a0db0
VS		 439 /*
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
442 */
443 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 444
445 return intel_dp->pps_pipe;
446}
447
6491ab27
VS		 448typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
449 enum pipe pipe);
450
451static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
452 enum pipe pipe)
453{
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
455}
456
457static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
461}
462
463static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return true;
467}
bf13e81b 468
a4a5d2f8 469static enum pipe
6491ab27
VS		 470vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
471 enum port port,
472 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 473{
474 enum pipe pipe;
bf13e81b 475
bf13e81b
JN		 476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
477 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
478 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 479
480 if (port_sel != PANEL_PORT_SELECT_VLV(port))
481 continue;
482
6491ab27
VS		 483 if (!pipe_check(dev_priv, pipe))
484 continue;
485
a4a5d2f8 486 return pipe;
bf13e81b
JN		 487 }
488
a4a5d2f8
VS		 489 return INVALID_PIPE;
490}
491
492static void
493vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
494{
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 498 enum port port = intel_dig_port->port;
499
500 lockdep_assert_held(&dev_priv->pps_mutex);
501
502 /* try to find a pipe with this port selected */
6491ab27
VS		 503 /* first pick one where the panel is on */
504 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
505 vlv_pipe_has_pp_on);
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp->pps_pipe == INVALID_PIPE)
508 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
509 vlv_pipe_has_vdd_on);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp->pps_pipe == INVALID_PIPE)
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_any);
a4a5d2f8
VS		 514
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp->pps_pipe == INVALID_PIPE) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
518 port_name(port));
519 return;
bf13e81b
JN		 520 }
521
a4a5d2f8
VS		 522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port), pipe_name(intel_dp->pps_pipe));
524
36b5f425
VS		 525 intel_dp_init_panel_power_sequencer(dev, intel_dp);
526 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 527}
528
773538e8
VS		 529void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
530{
531 struct drm_device *dev = dev_priv->dev;
532 struct intel_encoder *encoder;
533
534 if (WARN_ON(!IS_VALLEYVIEW(dev)))
535 return;
536
537 /*
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
545 */
546
547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
548 struct intel_dp *intel_dp;
549
550 if (encoder->type != INTEL_OUTPUT_EDP)
551 continue;
552
553 intel_dp = enc_to_intel_dp(&encoder->base);
554 intel_dp->pps_pipe = INVALID_PIPE;
555 }
bf13e81b
JN		 556}
557
558static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
562 if (HAS_PCH_SPLIT(dev))
563 return PCH_PP_CONTROL;
564 else
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
566}
567
568static u32 _pp_stat_reg(struct intel_dp *intel_dp)
569{
570 struct drm_device *dev = intel_dp_to_dev(intel_dp);
571
572 if (HAS_PCH_SPLIT(dev))
573 return PCH_PP_STATUS;
574 else
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
576}
577
01527b31
CT		 578/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580static int edp_notify_handler(struct notifier_block *this, unsigned long code,
581 void *unused)
582{
583 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
584 edp_notifier);
585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 u32 pp_div;
588 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 589
590 if (!is_edp(intel_dp) || code != SYS_RESTART)
591 return 0;
592
773538e8 593 pps_lock(intel_dp);
e39b999a 594
01527b31 595 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 596 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
597
01527b31
CT		 598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
599 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
600 pp_div = I915_READ(pp_div_reg);
601 pp_div &= PP_REFERENCE_DIVIDER_MASK;
602
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg, pp_div | 0x1F);
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
606 msleep(intel_dp->panel_power_cycle_delay);
607 }
608
773538e8 609 pps_unlock(intel_dp);
e39b999a 610
01527b31
CT		 611 return 0;
612}
613
4be73780 614static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 615{
30add22d 616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 617 struct drm_i915_private *dev_priv = dev->dev_private;
618
e39b999a
VS		 619 lockdep_assert_held(&dev_priv->pps_mutex);
620
9a42356b
VS		 621 if (IS_VALLEYVIEW(dev) &&
622 intel_dp->pps_pipe == INVALID_PIPE)
623 return false;
624
bf13e81b 625 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 626}
627
4be73780 628static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 629{
30add22d 630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 631 struct drm_i915_private *dev_priv = dev->dev_private;
632
e39b999a
VS		 633 lockdep_assert_held(&dev_priv->pps_mutex);
634
9a42356b
VS		 635 if (IS_VALLEYVIEW(dev) &&
636 intel_dp->pps_pipe == INVALID_PIPE)
637 return false;
638
773538e8 639 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 640}
641
9b984dae
KP		 642static void
643intel_dp_check_edp(struct intel_dp *intel_dp)
644{
30add22d 645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 646 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 647
9b984dae
KP		 648 if (!is_edp(intel_dp))
649 return;
453c5420 650
4be73780 651 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 654 I915_READ(_pp_stat_reg(intel_dp)),
655 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 656 }
657}
658
9ee32fea
DV		 659static uint32_t
660intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
661{
662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
663 struct drm_device *dev = intel_dig_port->base.base.dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 665 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 666 uint32_t status;
667 bool done;
668
ef04f00d 669#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 670 if (has_aux_irq)
b18ac466 671 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 672 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 673 else
674 done = wait_for_atomic(C, 10) == 0;
675 if (!done)
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
677 has_aux_irq);
678#undef C
679
680 return status;
681}
682
ec5b01dd 683static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 684{
174edf1f
PZ		 685 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
686 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 687
ec5b01dd
DL		 688 /*
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 691 */
ec5b01dd
DL		 692 return index ? 0 : intel_hrawclk(dev) / 2;
693}
694
695static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
696{
697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 699 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 700
701 if (index)
702 return 0;
703
704 if (intel_dig_port->port == PORT_A) {
469d4b2a 705 return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
ec5b01dd
DL		 706 } else {
707 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
708 }
709}
710
711static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
712{
713 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
714 struct drm_device *dev = intel_dig_port->base.base.dev;
715 struct drm_i915_private *dev_priv = dev->dev_private;
716
717 if (intel_dig_port->port == PORT_A) {
718 if (index)
719 return 0;
1652d19e 720 return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
2c55c336
JN		 721 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
722 /* Workaround for non-ULT HSW */
bc86625a
CW		 723 switch (index) {
724 case 0: return 63;
725 case 1: return 72;
726 default: return 0;
727 }
ec5b01dd 728 } else {
bc86625a 729 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 730 }
b84a1cf8
RV		 731}
732
ec5b01dd
DL		 733static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
734{
735 return index ? 0 : 100;
736}
737
b6b5e383
DL		 738static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
739{
740 /*
741 * SKL doesn't need us to program the AUX clock divider (Hardware will
742 * derive the clock from CDCLK automatically). We still implement the
743 * get_aux_clock_divider vfunc to plug-in into the existing code.
744 */
745 return index ? 0 : 1;
746}
747
5ed12a19
DL		 748static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
749 bool has_aux_irq,
750 int send_bytes,
751 uint32_t aux_clock_divider)
752{
753 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
754 struct drm_device *dev = intel_dig_port->base.base.dev;
755 uint32_t precharge, timeout;
756
757 if (IS_GEN6(dev))
758 precharge = 3;
759 else
760 precharge = 5;
761
762 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
763 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
764 else
765 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
766
767 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 768 DP_AUX_CH_CTL_DONE |
5ed12a19 769 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 770 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 771 timeout |
788d4433 772 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 773 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
774 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 775 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 776}
777
b9ca5fad
DL		 778static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
779 bool has_aux_irq,
780 int send_bytes,
781 uint32_t unused)
782{
783 return DP_AUX_CH_CTL_SEND_BUSY |
784 DP_AUX_CH_CTL_DONE |
785 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
786 DP_AUX_CH_CTL_TIME_OUT_ERROR |
787 DP_AUX_CH_CTL_TIME_OUT_1600us |
788 DP_AUX_CH_CTL_RECEIVE_ERROR |
789 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
790 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
791}
792
b84a1cf8
RV		 793static int
794intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 795 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 796 uint8_t *recv, int recv_size)
797{
798 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
799 struct drm_device *dev = intel_dig_port->base.base.dev;
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
802 uint32_t ch_data = ch_ctl + 4;
bc86625a 803 uint32_t aux_clock_divider;
b84a1cf8
RV		 804 int i, ret, recv_bytes;
805 uint32_t status;
5ed12a19 806 int try, clock = 0;
4e6b788c 807 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 808 bool vdd;
809
773538e8 810 pps_lock(intel_dp);
e39b999a 811
72c3500a
VS		 812 /*
813 * We will be called with VDD already enabled for dpcd/edid/oui reads.
814 * In such cases we want to leave VDD enabled and it's up to upper layers
815 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
816 * ourselves.
817 */
1e0560e0 818 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 819
820 /* dp aux is extremely sensitive to irq latency, hence request the
821 * lowest possible wakeup latency and so prevent the cpu from going into
822 * deep sleep states.
823 */
824 pm_qos_update_request(&dev_priv->pm_qos, 0);
825
826 intel_dp_check_edp(intel_dp);
5eb08b69 827
c67a470b
PZ		 828 intel_aux_display_runtime_get(dev_priv);
829
11bee43e
JB		 830 /* Try to wait for any previous AUX channel activity */
831 for (try = 0; try < 3; try++) {
ef04f00d 832 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 833 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
834 break;
835 msleep(1);
836 }
837
838 if (try == 3) {
839 WARN(1, "dp_aux_ch not started status 0x%08x\n",
840 I915_READ(ch_ctl));
9ee32fea
DV		 841 ret = -EBUSY;
842 goto out;
4f7f7b7e
CW		 843 }
844
46a5ae9f
PZ		 845 /* Only 5 data registers! */
846 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
847 ret = -E2BIG;
848 goto out;
849 }
850
ec5b01dd 851 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 852 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
853 has_aux_irq,
854 send_bytes,
855 aux_clock_divider);
5ed12a19 856
bc86625a
CW		 857 /* Must try at least 3 times according to DP spec */
858 for (try = 0; try < 5; try++) {
859 /* Load the send data into the aux channel data registers */
860 for (i = 0; i < send_bytes; i += 4)
861 I915_WRITE(ch_data + i,
a4f1289e
RV		 862 intel_dp_pack_aux(send + i,
863 send_bytes - i));
bc86625a
CW		 864
865 /* Send the command and wait for it to complete */
5ed12a19 866 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 867
868 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
869
870 /* Clear done status and any errors */
871 I915_WRITE(ch_ctl,
872 status |
873 DP_AUX_CH_CTL_DONE |
874 DP_AUX_CH_CTL_TIME_OUT_ERROR |
875 DP_AUX_CH_CTL_RECEIVE_ERROR);
876
877 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
878 DP_AUX_CH_CTL_RECEIVE_ERROR))
879 continue;
880 if (status & DP_AUX_CH_CTL_DONE)
881 break;
882 }
4f7f7b7e 883 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 884 break;
885 }
886
a4fc5ed6 887 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 888 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 889 ret = -EBUSY;
890 goto out;
a4fc5ed6
KP		 891 }
892
893 /* Check for timeout or receive error.
894 * Timeouts occur when the sink is not connected
895 */
a5b3da54 896 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 897 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 898 ret = -EIO;
899 goto out;
a5b3da54 900 }
1ae8c0a5
KP		 901
902 /* Timeouts occur when the device isn't connected, so they're
903 * "normal" -- don't fill the kernel log with these */
a5b3da54 904 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 905 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 906 ret = -ETIMEDOUT;
907 goto out;
a4fc5ed6
KP		 908 }
909
910 /* Unload any bytes sent back from the other side */
911 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
912 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 913 if (recv_bytes > recv_size)
914 recv_bytes = recv_size;
0206e353 915
4f7f7b7e 916 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 917 intel_dp_unpack_aux(I915_READ(ch_data + i),
918 recv + i, recv_bytes - i);
a4fc5ed6 919
9ee32fea
DV		 920 ret = recv_bytes;
921out:
922 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 923 intel_aux_display_runtime_put(dev_priv);
9ee32fea 924
884f19e9
JN		 925 if (vdd)
926 edp_panel_vdd_off(intel_dp, false);
927
773538e8 928 pps_unlock(intel_dp);
e39b999a 929
9ee32fea 930 return ret;
a4fc5ed6
KP		 931}
932
a6c8aff0
JN		 933#define BARE_ADDRESS_SIZE 3
934#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 935static ssize_t
936intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 937{
9d1a1031
JN		 938 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
939 uint8_t txbuf[20], rxbuf[20];
940 size_t txsize, rxsize;
a4fc5ed6 941 int ret;
a4fc5ed6 942
d2d9cbbd
VS		 943 txbuf[0] = (msg->request << 4) |
944 ((msg->address >> 16) & 0xf);
945 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 946 txbuf[2] = msg->address & 0xff;
947 txbuf[3] = msg->size - 1;
46a5ae9f 948
9d1a1031
JN		 949 switch (msg->request & ~DP_AUX_I2C_MOT) {
950 case DP_AUX_NATIVE_WRITE:
951 case DP_AUX_I2C_WRITE:
a6c8aff0 952 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 953 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 954
9d1a1031
JN		 955 if (WARN_ON(txsize > 20))
956 return -E2BIG;
a4fc5ed6 957
9d1a1031 958 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 959
9d1a1031
JN		 960 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
961 if (ret > 0) {
962 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 963
a1ddefd8
JN		 964 if (ret > 1) {
965 /* Number of bytes written in a short write. */
966 ret = clamp_t(int, rxbuf[1], 0, msg->size);
967 } else {
968 /* Return payload size. */
969 ret = msg->size;
970 }
9d1a1031
JN		 971 }
972 break;
46a5ae9f 973
9d1a1031
JN		 974 case DP_AUX_NATIVE_READ:
975 case DP_AUX_I2C_READ:
a6c8aff0 976 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 977 rxsize = msg->size + 1;
a4fc5ed6 978
9d1a1031
JN		 979 if (WARN_ON(rxsize > 20))
980 return -E2BIG;
a4fc5ed6 981
9d1a1031
JN		 982 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
983 if (ret > 0) {
984 msg->reply = rxbuf[0] >> 4;
985 /*
986 * Assume happy day, and copy the data. The caller is
987 * expected to check msg->reply before touching it.
988 *
989 * Return payload size.
990 */
991 ret--;
992 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 993 }
9d1a1031
JN		 994 break;
995
996 default:
997 ret = -EINVAL;
998 break;
a4fc5ed6 999 }
f51a44b9 1000
9d1a1031 1001 return ret;
a4fc5ed6
KP		 1002}
1003
9d1a1031
JN		 1004static void
1005intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1006{
1007 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1008 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1009 enum port port = intel_dig_port->port;
0b99836f 1010 const char *name = NULL;
ab2c0672
DA		 1011 int ret;
1012
33ad6626
JN		 1013 switch (port) {
1014 case PORT_A:
1015 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1016 name = "DPDDC-A";
ab2c0672 1017 break;
33ad6626
JN		 1018 case PORT_B:
1019 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1020 name = "DPDDC-B";
ab2c0672 1021 break;
33ad6626
JN		 1022 case PORT_C:
1023 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1024 name = "DPDDC-C";
ab2c0672 1025 break;
33ad6626
JN		 1026 case PORT_D:
1027 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1028 name = "DPDDC-D";
33ad6626
JN		 1029 break;
1030 default:
1031 BUG();
ab2c0672
DA		 1032 }
1033
1b1aad75
DL		 1034 /*
1035 * The AUX_CTL register is usually DP_CTL + 0x10.
1036 *
1037 * On Haswell and Broadwell though:
1038 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1039 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1040 *
1041 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1042 */
1043 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1044 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1045
0b99836f 1046 intel_dp->aux.name = name;
9d1a1031
JN		 1047 intel_dp->aux.dev = dev->dev;
1048 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1049
0b99836f
JN		 1050 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1051 connector->base.kdev->kobj.name);
8316f337 1052
4f71d0cb 1053 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1054 if (ret < 0) {
4f71d0cb 1055 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1056 name, ret);
1057 return;
ab2c0672 1058 }
8a5e6aeb 1059
0b99836f
JN		 1060 ret = sysfs_create_link(&connector->base.kdev->kobj,
1061 &intel_dp->aux.ddc.dev.kobj,
1062 intel_dp->aux.ddc.dev.kobj.name);
1063 if (ret < 0) {
1064 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1065 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1066 }
a4fc5ed6
KP		 1067}
1068
80f65de3
ID		 1069static void
1070intel_dp_connector_unregister(struct intel_connector *intel_connector)
1071{
1072 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1073
0e32b39c
DA		 1074 if (!intel_connector->mst_port)
1075 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1076 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1077 intel_connector_unregister(intel_connector);
1078}
1079
5416d871 1080static void
c3346ef6 1081skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
5416d871
DL		 1082{
1083 u32 ctrl1;
1084
1085 pipe_config->ddi_pll_sel = SKL_DPLL0;
1086 pipe_config->dpll_hw_state.cfgcr1 = 0;
1087 pipe_config->dpll_hw_state.cfgcr2 = 0;
1088
1089 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
c3346ef6
SJ		 1090 switch (link_clock / 2) {
1091 case 81000:
5416d871
DL		 1092 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1093 SKL_DPLL0);
1094 break;
c3346ef6 1095 case 135000:
5416d871
DL		 1096 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1097 SKL_DPLL0);
1098 break;
c3346ef6 1099 case 270000:
5416d871
DL		 1100 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1101 SKL_DPLL0);
1102 break;
c3346ef6
SJ		 1103 case 162000:
1104 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
1105 SKL_DPLL0);
1106 break;
1107 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1108 results in CDCLK change. Need to handle the change of CDCLK by
1109 disabling pipes and re-enabling them */
1110 case 108000:
1111 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
1112 SKL_DPLL0);
1113 break;
1114 case 216000:
1115 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
1116 SKL_DPLL0);
1117 break;
1118
5416d871
DL		 1119 }
1120 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1121}
1122
0e50338c 1123static void
5cec258b 1124hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c
DV		 1125{
1126 switch (link_bw) {
1127 case DP_LINK_BW_1_62:
1128 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1129 break;
1130 case DP_LINK_BW_2_7:
1131 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1132 break;
1133 case DP_LINK_BW_5_4:
1134 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1135 break;
1136 }
1137}
1138
fc0f8e25 1139static int
12f6a2e2 1140intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1141{
94ca719e
VS		 1142 if (intel_dp->num_sink_rates) {
1143 *sink_rates = intel_dp->sink_rates;
1144 return intel_dp->num_sink_rates;
fc0f8e25 1145 }
12f6a2e2
VS		 1146
1147 *sink_rates = default_rates;
1148
1149 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1150}
1151
a8f3ef61 1152static int
1db10e28 1153intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
a8f3ef61 1154{
636280ba
VS		 1155 if (INTEL_INFO(dev)->gen >= 9) {
1156 *source_rates = gen9_rates;
1157 return ARRAY_SIZE(gen9_rates);
fe51bfb9
VS		 1158 } else if (IS_CHERRYVIEW(dev)) {
1159 *source_rates = chv_rates;
1160 return ARRAY_SIZE(chv_rates);
a8f3ef61 1161 }
636280ba
VS		 1162
1163 *source_rates = default_rates;
1164
1db10e28
VS		 1165 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1166 /* WaDisableHBR2:skl */
1167 return (DP_LINK_BW_2_7 >> 3) + 1;
1168 else if (INTEL_INFO(dev)->gen >= 8 ||
1169 (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1170 return (DP_LINK_BW_5_4 >> 3) + 1;
1171 else
1172 return (DP_LINK_BW_2_7 >> 3) + 1;
a8f3ef61
SJ		 1173}
1174
c6bb3538
DV		 1175static void
1176intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1177 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1178{
1179 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1180 const struct dp_link_dpll *divisor = NULL;
1181 int i, count = 0;
c6bb3538
DV		 1182
1183 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1184 divisor = gen4_dpll;
1185 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1186 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1187 divisor = pch_dpll;
1188 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1189 } else if (IS_CHERRYVIEW(dev)) {
1190 divisor = chv_dpll;
1191 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1192 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1193 divisor = vlv_dpll;
1194 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1195 }
9dd4ffdf
CML		 1196
1197 if (divisor && count) {
1198 for (i = 0; i < count; i++) {
1199 if (link_bw == divisor[i].link_bw) {
1200 pipe_config->dpll = divisor[i].dpll;
1201 pipe_config->clock_set = true;
1202 break;
1203 }
1204 }
c6bb3538
DV		 1205 }
1206}
1207
2ecae76a
VS		 1208static int intersect_rates(const int *source_rates, int source_len,
1209 const int *sink_rates, int sink_len,
94ca719e 1210 int *common_rates)
a8f3ef61
SJ		 1211{
1212 int i = 0, j = 0, k = 0;
1213
a8f3ef61
SJ		 1214 while (i < source_len && j < sink_len) {
1215 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1216 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1217 return k;
94ca719e 1218 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1219 ++k;
1220 ++i;
1221 ++j;
1222 } else if (source_rates[i] < sink_rates[j]) {
1223 ++i;
1224 } else {
1225 ++j;
1226 }
1227 }
1228 return k;
1229}
1230
94ca719e
VS		 1231static int intel_dp_common_rates(struct intel_dp *intel_dp,
1232 int *common_rates)
2ecae76a
VS		 1233{
1234 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1235 const int *source_rates, *sink_rates;
1236 int source_len, sink_len;
1237
1238 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1239 source_len = intel_dp_source_rates(dev, &source_rates);
1240
1241 return intersect_rates(source_rates, source_len,
1242 sink_rates, sink_len,
94ca719e 1243 common_rates);
2ecae76a
VS		 1244}
1245
0336400e
VS		 1246static void snprintf_int_array(char *str, size_t len,
1247 const int *array, int nelem)
1248{
1249 int i;
1250
1251 str[0] = '\0';
1252
1253 for (i = 0; i < nelem; i++) {
1254 int r = snprintf(str, len, "%d,", array[i]);
1255 if (r >= len)
1256 return;
1257 str += r;
1258 len -= r;
1259 }
1260}
1261
1262static void intel_dp_print_rates(struct intel_dp *intel_dp)
1263{
1264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1265 const int *source_rates, *sink_rates;
94ca719e
VS		 1266 int source_len, sink_len, common_len;
1267 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1268 char str[128]; /* FIXME: too big for stack? */
1269
1270 if ((drm_debug & DRM_UT_KMS) == 0)
1271 return;
1272
1273 source_len = intel_dp_source_rates(dev, &source_rates);
1274 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1275 DRM_DEBUG_KMS("source rates: %s\n", str);
1276
1277 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1278 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1279 DRM_DEBUG_KMS("sink rates: %s\n", str);
1280
94ca719e
VS		 1281 common_len = intel_dp_common_rates(intel_dp, common_rates);
1282 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1283 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1284}
1285
f4896f15 1286static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1287{
1288 int i = 0;
1289
1290 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1291 if (find == rates[i])
1292 break;
1293
1294 return i;
1295}
1296
50fec21a
VS		 1297int
1298intel_dp_max_link_rate(struct intel_dp *intel_dp)
1299{
1300 int rates[DP_MAX_SUPPORTED_RATES] = {};
1301 int len;
1302
94ca719e 1303 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1304 if (WARN_ON(len <= 0))
1305 return 162000;
1306
1307 return rates[rate_to_index(0, rates) - 1];
1308}
1309
ed4e9c1d
VS		 1310int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1311{
94ca719e 1312 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1313}
1314
00c09d70 1315bool
5bfe2ac0 1316intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1317 struct intel_crtc_state *pipe_config)
a4fc5ed6 1318{
5bfe2ac0 1319 struct drm_device *dev = encoder->base.dev;
36008365 1320 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1321 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1322 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1323 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1324 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1325 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1326 int lane_count, clock;
56071a20 1327 int min_lane_count = 1;
eeb6324d 1328 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1329 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1330 int min_clock = 0;
a8f3ef61 1331 int max_clock;
083f9560 1332 int bpp, mode_rate;
ff9a6750 1333 int link_avail, link_clock;
94ca719e
VS		 1334 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1335 int common_len;
a8f3ef61 1336
94ca719e 1337 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1338
1339 /* No common link rates between source and sink */
94ca719e 1340 WARN_ON(common_len <= 0);
a8f3ef61 1341
94ca719e 1342 max_clock = common_len - 1;
a4fc5ed6 1343
bc7d38a4 1344 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1345 pipe_config->has_pch_encoder = true;
1346
03afc4a2 1347 pipe_config->has_dp_encoder = true;
f769cd24 1348 pipe_config->has_drrs = false;
9ed109a7 1349 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1350
dd06f90e
JN		 1351 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1352 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1353 adjusted_mode);
a1b2278e
CK		 1354
1355 if (INTEL_INFO(dev)->gen >= 9) {
1356 int ret;
1357 ret = skl_update_scaler_users(intel_crtc, pipe_config, NULL, NULL, 0);
1358 if (ret)
1359 return ret;
1360 }
1361
2dd24552
JB		 1362 if (!HAS_PCH_SPLIT(dev))
1363 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1364 intel_connector->panel.fitting_mode);
1365 else
b074cec8
JB		 1366 intel_pch_panel_fitting(intel_crtc, pipe_config,
1367 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1368 }
1369
cb1793ce 1370 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1371 return false;
1372
083f9560 1373 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1374 "max bw %d pixel clock %iKHz\n",
94ca719e 1375 max_lane_count, common_rates[max_clock],
241bfc38 1376 adjusted_mode->crtc_clock);
083f9560 1377
36008365
DV		 1378 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1379 * bpc in between. */
3e7ca985 1380 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1381 if (is_edp(intel_dp)) {
1382 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1383 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1384 dev_priv->vbt.edp_bpp);
1385 bpp = dev_priv->vbt.edp_bpp;
1386 }
1387
344c5bbc
JN		 1388 /*
1389 * Use the maximum clock and number of lanes the eDP panel
1390 * advertizes being capable of. The panels are generally
1391 * designed to support only a single clock and lane
1392 * configuration, and typically these values correspond to the
1393 * native resolution of the panel.
1394 */
1395 min_lane_count = max_lane_count;
1396 min_clock = max_clock;
7984211e 1397 }
657445fe 1398
36008365 1399 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1400 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1401 bpp);
36008365 1402
c6930992 1403 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1404 for (lane_count = min_lane_count;
1405 lane_count <= max_lane_count;
1406 lane_count <<= 1) {
1407
94ca719e 1408 link_clock = common_rates[clock];
36008365
DV		 1409 link_avail = intel_dp_max_data_rate(link_clock,
1410 lane_count);
1411
1412 if (mode_rate <= link_avail) {
1413 goto found;
1414 }
1415 }
1416 }
1417 }
c4867936 1418
36008365 1419 return false;
3685a8f3 1420
36008365 1421found:
55bc60db
VS		 1422 if (intel_dp->color_range_auto) {
1423 /*
1424 * See:
1425 * CEA-861-E - 5.1 Default Encoding Parameters
1426 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1427 */
18316c8c 1428 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1429 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1430 else
1431 intel_dp->color_range = 0;
1432 }
1433
3685a8f3 1434 if (intel_dp->color_range)
50f3b016 1435 pipe_config->limited_color_range = true;
a4fc5ed6 1436
36008365 1437 intel_dp->lane_count = lane_count;
a8f3ef61 1438
94ca719e 1439 if (intel_dp->num_sink_rates) {
bc27b7d3 1440 intel_dp->link_bw = 0;
a8f3ef61 1441 intel_dp->rate_select =
94ca719e 1442 intel_dp_rate_select(intel_dp, common_rates[clock]);
bc27b7d3
VS		 1443 } else {
1444 intel_dp->link_bw =
94ca719e 1445 drm_dp_link_rate_to_bw_code(common_rates[clock]);
bc27b7d3 1446 intel_dp->rate_select = 0;
a8f3ef61
SJ		 1447 }
1448
657445fe 1449 pipe_config->pipe_bpp = bpp;
94ca719e 1450 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1451
36008365
DV		 1452 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1453 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1454 pipe_config->port_clock, bpp);
36008365
DV		 1455 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1456 mode_rate, link_avail);
a4fc5ed6 1457
03afc4a2 1458 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1459 adjusted_mode->crtc_clock,
1460 pipe_config->port_clock,
03afc4a2 1461 &pipe_config->dp_m_n);
9d1a455b 1462
439d7ac0 1463 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1464 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1465 pipe_config->has_drrs = true;
439d7ac0
PB		 1466 intel_link_compute_m_n(bpp, lane_count,
1467 intel_connector->panel.downclock_mode->clock,
1468 pipe_config->port_clock,
1469 &pipe_config->dp_m2_n2);
1470 }
1471
5416d871 1472 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
94ca719e 1473 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
977bb38d
S		 1474 else if (IS_BROXTON(dev))
1475 /* handled in ddi */;
5416d871 1476 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1477 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1478 else
1479 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1480
03afc4a2 1481 return true;
a4fc5ed6
KP		 1482}
1483
7c62a164 1484static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1485{
7c62a164
DV		 1486 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1487 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1488 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 u32 dpa_ctl;
1491
6e3c9717
ACO		 1492 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1493 crtc->config->port_clock);
ea9b6006
DV		 1494 dpa_ctl = I915_READ(DP_A);
1495 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1496
6e3c9717 1497 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1498 /* For a long time we've carried around a ILK-DevA w/a for the
1499 * 160MHz clock. If we're really unlucky, it's still required.
1500 */
1501 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1502 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1503 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1504 } else {
1505 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1506 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1507 }
1ce17038 1508
ea9b6006
DV		 1509 I915_WRITE(DP_A, dpa_ctl);
1510
1511 POSTING_READ(DP_A);
1512 udelay(500);
1513}
1514
8ac33ed3 1515static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1516{
b934223d 1517 struct drm_device *dev = encoder->base.dev;
417e822d 1518 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1519 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1520 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1521 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1522 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1523
417e822d 1524 /*
1a2eb460 1525 * There are four kinds of DP registers:
417e822d
KP		 1526 *
1527 * IBX PCH
1a2eb460
KP		 1528 * SNB CPU
1529 * IVB CPU
417e822d
KP		 1530 * CPT PCH
1531 *
1532 * IBX PCH and CPU are the same for almost everything,
1533 * except that the CPU DP PLL is configured in this
1534 * register
1535 *
1536 * CPT PCH is quite different, having many bits moved
1537 * to the TRANS_DP_CTL register instead. That
1538 * configuration happens (oddly) in ironlake_pch_enable
1539 */
9c9e7927 1540
417e822d
KP		 1541 /* Preserve the BIOS-computed detected bit. This is
1542 * supposed to be read-only.
1543 */
1544 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1545
417e822d 1546 /* Handle DP bits in common between all three register formats */
417e822d 1547 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1548 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1549
6e3c9717 1550 if (crtc->config->has_audio)
ea5b213a 1551 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1552
417e822d 1553 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1554
bc7d38a4 1555 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1556 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1557 intel_dp->DP |= DP_SYNC_HS_HIGH;
1558 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1559 intel_dp->DP |= DP_SYNC_VS_HIGH;
1560 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1561
6aba5b6c 1562 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1563 intel_dp->DP |= DP_ENHANCED_FRAMING;
1564
7c62a164 1565 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1566 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1567 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1568 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1569
1570 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1571 intel_dp->DP |= DP_SYNC_HS_HIGH;
1572 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1573 intel_dp->DP |= DP_SYNC_VS_HIGH;
1574 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1575
6aba5b6c 1576 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1577 intel_dp->DP |= DP_ENHANCED_FRAMING;
1578
44f37d1f
CML		 1579 if (!IS_CHERRYVIEW(dev)) {
1580 if (crtc->pipe == 1)
1581 intel_dp->DP |= DP_PIPEB_SELECT;
1582 } else {
1583 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1584 }
417e822d
KP		 1585 } else {
1586 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1587 }
a4fc5ed6
KP		 1588}
1589
ffd6749d
PZ		 1590#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1591#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1592
1a5ef5b7
PZ		 1593#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1594#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1595
ffd6749d
PZ		 1596#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1597#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1598
4be73780 1599static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1600 u32 mask,
1601 u32 value)
bd943159 1602{
30add22d 1603 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1604 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1605 u32 pp_stat_reg, pp_ctrl_reg;
1606
e39b999a
VS		 1607 lockdep_assert_held(&dev_priv->pps_mutex);
1608
bf13e81b
JN		 1609 pp_stat_reg = _pp_stat_reg(intel_dp);
1610 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1611
99ea7127 1612 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1613 mask, value,
1614 I915_READ(pp_stat_reg),
1615 I915_READ(pp_ctrl_reg));
32ce697c 1616
453c5420 1617 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1618 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1619 I915_READ(pp_stat_reg),
1620 I915_READ(pp_ctrl_reg));
32ce697c 1621 }
54c136d4
CW		 1622
1623 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1624}
32ce697c 1625
4be73780 1626static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1627{
1628 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1629 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1630}
1631
4be73780 1632static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1633{
1634 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1635 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1636}
1637
4be73780 1638static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1639{
1640 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1641
1642 /* When we disable the VDD override bit last we have to do the manual
1643 * wait. */
1644 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1645 intel_dp->panel_power_cycle_delay);
1646
4be73780 1647 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1648}
1649
4be73780 1650static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1651{
1652 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1653 intel_dp->backlight_on_delay);
1654}
1655
4be73780 1656static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1657{
1658 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1659 intel_dp->backlight_off_delay);
1660}
99ea7127 1661
832dd3c1
KP		 1662/* Read the current pp_control value, unlocking the register if it
1663 * is locked
1664 */
1665
453c5420 1666static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1667{
453c5420
JB		 1668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 u32 control;
832dd3c1 1671
e39b999a
VS		 1672 lockdep_assert_held(&dev_priv->pps_mutex);
1673
bf13e81b 1674 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1675 control &= ~PANEL_UNLOCK_MASK;
1676 control |= PANEL_UNLOCK_REGS;
1677 return control;
bd943159
KP		 1678}
1679
951468f3
VS		 1680/*
1681 * Must be paired with edp_panel_vdd_off().
1682 * Must hold pps_mutex around the whole on/off sequence.
1683 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1684 */
1e0560e0 1685static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1686{
30add22d 1687 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1688 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1689 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1690 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1691 enum intel_display_power_domain power_domain;
5d613501 1692 u32 pp;
453c5420 1693 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1694 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1695
e39b999a
VS		 1696 lockdep_assert_held(&dev_priv->pps_mutex);
1697
97af61f5 1698 if (!is_edp(intel_dp))
adddaaf4 1699 return false;
bd943159 1700
2c623c11 1701 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1702 intel_dp->want_panel_vdd = true;
99ea7127 1703
4be73780 1704 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1705 return need_to_disable;
b0665d57 1706
4e6e1a54
ID		 1707 power_domain = intel_display_port_power_domain(intel_encoder);
1708 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1709
3936fcf4
VS		 1710 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1711 port_name(intel_dig_port->port));
bd943159 1712
4be73780
DV		 1713 if (!edp_have_panel_power(intel_dp))
1714 wait_panel_power_cycle(intel_dp);
99ea7127 1715
453c5420 1716 pp = ironlake_get_pp_control(intel_dp);
5d613501 1717 pp |= EDP_FORCE_VDD;
ebf33b18 1718
bf13e81b
JN		 1719 pp_stat_reg = _pp_stat_reg(intel_dp);
1720 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1721
1722 I915_WRITE(pp_ctrl_reg, pp);
1723 POSTING_READ(pp_ctrl_reg);
1724 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1725 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1726 /*
1727 * If the panel wasn't on, delay before accessing aux channel
1728 */
4be73780 1729 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1730 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1731 port_name(intel_dig_port->port));
f01eca2e 1732 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1733 }
adddaaf4
JN		 1734
1735 return need_to_disable;
1736}
1737
951468f3
VS		 1738/*
1739 * Must be paired with intel_edp_panel_vdd_off() or
1740 * intel_edp_panel_off().
1741 * Nested calls to these functions are not allowed since
1742 * we drop the lock. Caller must use some higher level
1743 * locking to prevent nested calls from other threads.
1744 */
b80d6c78 1745void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1746{
c695b6b6 1747 bool vdd;
adddaaf4 1748
c695b6b6
VS		 1749 if (!is_edp(intel_dp))
1750 return;
1751
773538e8 1752 pps_lock(intel_dp);
c695b6b6 1753 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1754 pps_unlock(intel_dp);
c695b6b6 1755
e2c719b7 1756 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1757 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1758}
1759
4be73780 1760static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1761{
30add22d 1762 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1763 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1764 struct intel_digital_port *intel_dig_port =
1765 dp_to_dig_port(intel_dp);
1766 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1767 enum intel_display_power_domain power_domain;
5d613501 1768 u32 pp;
453c5420 1769 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1770
e39b999a 1771 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1772
15e899a0 1773 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1774
15e899a0 1775 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1776 return;
b0665d57 1777
3936fcf4
VS		 1778 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1779 port_name(intel_dig_port->port));
bd943159 1780
be2c9196
VS		 1781 pp = ironlake_get_pp_control(intel_dp);
1782 pp &= ~EDP_FORCE_VDD;
453c5420 1783
be2c9196
VS		 1784 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1785 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1786
be2c9196
VS		 1787 I915_WRITE(pp_ctrl_reg, pp);
1788 POSTING_READ(pp_ctrl_reg);
90791a5c 1789
be2c9196
VS		 1790 /* Make sure sequencer is idle before allowing subsequent activity */
1791 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1792 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1793
be2c9196
VS		 1794 if ((pp & POWER_TARGET_ON) == 0)
1795 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1796
be2c9196
VS		 1797 power_domain = intel_display_port_power_domain(intel_encoder);
1798 intel_display_power_put(dev_priv, power_domain);
bd943159 1799}
5d613501 1800
4be73780 1801static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1802{
1803 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1804 struct intel_dp, panel_vdd_work);
bd943159 1805
773538e8 1806 pps_lock(intel_dp);
15e899a0
VS		 1807 if (!intel_dp->want_panel_vdd)
1808 edp_panel_vdd_off_sync(intel_dp);
773538e8 1809 pps_unlock(intel_dp);
bd943159
KP		 1810}
1811
aba86890
ID		 1812static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1813{
1814 unsigned long delay;
1815
1816 /*
1817 * Queue the timer to fire a long time from now (relative to the power
1818 * down delay) to keep the panel power up across a sequence of
1819 * operations.
1820 */
1821 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1822 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1823}
1824
951468f3
VS		 1825/*
1826 * Must be paired with edp_panel_vdd_on().
1827 * Must hold pps_mutex around the whole on/off sequence.
1828 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1829 */
4be73780 1830static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1831{
e39b999a
VS		 1832 struct drm_i915_private *dev_priv =
1833 intel_dp_to_dev(intel_dp)->dev_private;
1834
1835 lockdep_assert_held(&dev_priv->pps_mutex);
1836
97af61f5
KP		 1837 if (!is_edp(intel_dp))
1838 return;
5d613501 1839
e2c719b7 1840 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1841 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1842
bd943159
KP		 1843 intel_dp->want_panel_vdd = false;
1844
aba86890 1845 if (sync)
4be73780 1846 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1847 else
1848 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1849}
1850
9f0fb5be 1851static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1852{
30add22d 1853 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1854 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1855 u32 pp;
453c5420 1856 u32 pp_ctrl_reg;
9934c132 1857
9f0fb5be
VS		 1858 lockdep_assert_held(&dev_priv->pps_mutex);
1859
97af61f5 1860 if (!is_edp(intel_dp))
bd943159 1861 return;
99ea7127 1862
3936fcf4
VS		 1863 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1864 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1865
e7a89ace
VS		 1866 if (WARN(edp_have_panel_power(intel_dp),
1867 "eDP port %c panel power already on\n",
1868 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1869 return;
9934c132 1870
4be73780 1871 wait_panel_power_cycle(intel_dp);
37c6c9b0 1872
bf13e81b 1873 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1874 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1875 if (IS_GEN5(dev)) {
1876 /* ILK workaround: disable reset around power sequence */
1877 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1878 I915_WRITE(pp_ctrl_reg, pp);
1879 POSTING_READ(pp_ctrl_reg);
05ce1a49 1880 }
37c6c9b0 1881
1c0ae80a 1882 pp |= POWER_TARGET_ON;
99ea7127
KP		 1883 if (!IS_GEN5(dev))
1884 pp |= PANEL_POWER_RESET;
1885
453c5420
JB		 1886 I915_WRITE(pp_ctrl_reg, pp);
1887 POSTING_READ(pp_ctrl_reg);
9934c132 1888
4be73780 1889 wait_panel_on(intel_dp);
dce56b3c 1890 intel_dp->last_power_on = jiffies;
9934c132 1891
05ce1a49
KP		 1892 if (IS_GEN5(dev)) {
1893 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1894 I915_WRITE(pp_ctrl_reg, pp);
1895 POSTING_READ(pp_ctrl_reg);
05ce1a49 1896 }
9f0fb5be 1897}
e39b999a 1898
9f0fb5be
VS		 1899void intel_edp_panel_on(struct intel_dp *intel_dp)
1900{
1901 if (!is_edp(intel_dp))
1902 return;
1903
1904 pps_lock(intel_dp);
1905 edp_panel_on(intel_dp);
773538e8 1906 pps_unlock(intel_dp);
9934c132
JB		 1907}
1908
9f0fb5be
VS		 1909
1910static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1911{
4e6e1a54
ID		 1912 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1913 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1914 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1915 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1916 enum intel_display_power_domain power_domain;
99ea7127 1917 u32 pp;
453c5420 1918 u32 pp_ctrl_reg;
9934c132 1919
9f0fb5be
VS		 1920 lockdep_assert_held(&dev_priv->pps_mutex);
1921
97af61f5
KP		 1922 if (!is_edp(intel_dp))
1923 return;
37c6c9b0 1924
3936fcf4
VS		 1925 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1926 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1927
3936fcf4
VS		 1928 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1929 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1930
453c5420 1931 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1932 /* We need to switch off panel power _and_ force vdd, for otherwise some
1933 * panels get very unhappy and cease to work. */
b3064154
PJ		 1934 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1935 EDP_BLC_ENABLE);
453c5420 1936
bf13e81b 1937 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1938
849e39f5
PZ		 1939 intel_dp->want_panel_vdd = false;
1940
453c5420
JB		 1941 I915_WRITE(pp_ctrl_reg, pp);
1942 POSTING_READ(pp_ctrl_reg);
9934c132 1943
dce56b3c 1944 intel_dp->last_power_cycle = jiffies;
4be73780 1945 wait_panel_off(intel_dp);
849e39f5
PZ		 1946
1947 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1948 power_domain = intel_display_port_power_domain(intel_encoder);
1949 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1950}
e39b999a 1951
9f0fb5be
VS		 1952void intel_edp_panel_off(struct intel_dp *intel_dp)
1953{
1954 if (!is_edp(intel_dp))
1955 return;
e39b999a 1956
9f0fb5be
VS		 1957 pps_lock(intel_dp);
1958 edp_panel_off(intel_dp);
773538e8 1959 pps_unlock(intel_dp);
9934c132
JB		 1960}
1961
1250d107
JN		 1962/* Enable backlight in the panel power control. */
1963static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1964{
da63a9f2
PZ		 1965 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1966 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1967 struct drm_i915_private *dev_priv = dev->dev_private;
1968 u32 pp;
453c5420 1969 u32 pp_ctrl_reg;
32f9d658 1970
01cb9ea6
JB		 1971 /*
1972 * If we enable the backlight right away following a panel power
1973 * on, we may see slight flicker as the panel syncs with the eDP
1974 * link. So delay a bit to make sure the image is solid before
1975 * allowing it to appear.
1976 */
4be73780 1977 wait_backlight_on(intel_dp);
e39b999a 1978
773538e8 1979 pps_lock(intel_dp);
e39b999a 1980
453c5420 1981 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1982 pp |= EDP_BLC_ENABLE;
453c5420 1983
bf13e81b 1984 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1985
1986 I915_WRITE(pp_ctrl_reg, pp);
1987 POSTING_READ(pp_ctrl_reg);
e39b999a 1988
773538e8 1989 pps_unlock(intel_dp);
32f9d658
ZW		 1990}
1991
1250d107
JN		 1992/* Enable backlight PWM and backlight PP control. */
1993void intel_edp_backlight_on(struct intel_dp *intel_dp)
1994{
1995 if (!is_edp(intel_dp))
1996 return;
1997
1998 DRM_DEBUG_KMS("\n");
1999
2000 intel_panel_enable_backlight(intel_dp->attached_connector);
2001 _intel_edp_backlight_on(intel_dp);
2002}
2003
2004/* Disable backlight in the panel power control. */
2005static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2006{
30add22d 2007 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009 u32 pp;
453c5420 2010 u32 pp_ctrl_reg;
32f9d658 2011
f01eca2e
KP		 2012 if (!is_edp(intel_dp))
2013 return;
2014
773538e8 2015 pps_lock(intel_dp);
e39b999a 2016
453c5420 2017 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2018 pp &= ~EDP_BLC_ENABLE;
453c5420 2019
bf13e81b 2020 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2021
2022 I915_WRITE(pp_ctrl_reg, pp);
2023 POSTING_READ(pp_ctrl_reg);
f7d2323c 2024
773538e8 2025 pps_unlock(intel_dp);
e39b999a
VS		 2026
2027 intel_dp->last_backlight_off = jiffies;
f7d2323c 2028 edp_wait_backlight_off(intel_dp);
1250d107 2029}
f7d2323c 2030
1250d107
JN		 2031/* Disable backlight PP control and backlight PWM. */
2032void intel_edp_backlight_off(struct intel_dp *intel_dp)
2033{
2034 if (!is_edp(intel_dp))
2035 return;
2036
2037 DRM_DEBUG_KMS("\n");
f7d2323c 2038
1250d107 2039 _intel_edp_backlight_off(intel_dp);
f7d2323c 2040 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2041}
a4fc5ed6 2042
73580fb7
JN		 2043/*
2044 * Hook for controlling the panel power control backlight through the bl_power
2045 * sysfs attribute. Take care to handle multiple calls.
2046 */
2047static void intel_edp_backlight_power(struct intel_connector *connector,
2048 bool enable)
2049{
2050 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2051 bool is_enabled;
2052
773538e8 2053 pps_lock(intel_dp);
e39b999a 2054 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2055 pps_unlock(intel_dp);
73580fb7
JN		 2056
2057 if (is_enabled == enable)
2058 return;
2059
23ba9373
JN		 2060 DRM_DEBUG_KMS("panel power control backlight %s\n",
2061 enable ? "enable" : "disable");
73580fb7
JN		 2062
2063 if (enable)
2064 _intel_edp_backlight_on(intel_dp);
2065 else
2066 _intel_edp_backlight_off(intel_dp);
2067}
2068
2bd2ad64 2069static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2070{
da63a9f2
PZ		 2071 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2072 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2073 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 u32 dpa_ctl;
2076
2bd2ad64
DV		 2077 assert_pipe_disabled(dev_priv,
2078 to_intel_crtc(crtc)->pipe);
2079
d240f20f
JB		 2080 DRM_DEBUG_KMS("\n");
2081 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2082 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2083 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2084
2085 /* We don't adjust intel_dp->DP while tearing down the link, to
2086 * facilitate link retraining (e.g. after hotplug). Hence clear all
2087 * enable bits here to ensure that we don't enable too much. */
2088 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2089 intel_dp->DP |= DP_PLL_ENABLE;
2090 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2091 POSTING_READ(DP_A);
2092 udelay(200);
d240f20f
JB		 2093}
2094
2bd2ad64 2095static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2096{
da63a9f2
PZ		 2097 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2098 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2099 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 u32 dpa_ctl;
2102
2bd2ad64
DV		 2103 assert_pipe_disabled(dev_priv,
2104 to_intel_crtc(crtc)->pipe);
2105
d240f20f 2106 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2107 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2108 "dp pll off, should be on\n");
2109 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2110
2111 /* We can't rely on the value tracked for the DP register in
2112 * intel_dp->DP because link_down must not change that (otherwise link
2113 * re-training will fail. */
298b0b39 2114 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2115 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2116 POSTING_READ(DP_A);
d240f20f
JB		 2117 udelay(200);
2118}
2119
c7ad3810 2120/* If the sink supports it, try to set the power state appropriately */
c19b0669 2121void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2122{
2123 int ret, i;
2124
2125 /* Should have a valid DPCD by this point */
2126 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2127 return;
2128
2129 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2130 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2131 DP_SET_POWER_D3);
c7ad3810
JB		 2132 } else {
2133 /*
2134 * When turning on, we need to retry for 1ms to give the sink
2135 * time to wake up.
2136 */
2137 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2138 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2139 DP_SET_POWER_D0);
c7ad3810
JB		 2140 if (ret == 1)
2141 break;
2142 msleep(1);
2143 }
2144 }
f9cac721
JN		 2145
2146 if (ret != 1)
2147 DRM_DEBUG_KMS("failed to %s sink power state\n",
2148 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2149}
2150
19d8fe15
DV		 2151static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2152 enum pipe *pipe)
d240f20f 2153{
19d8fe15 2154 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2155 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2156 struct drm_device *dev = encoder->base.dev;
2157 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2158 enum intel_display_power_domain power_domain;
2159 u32 tmp;
2160
2161 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2162 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2163 return false;
2164
2165 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2166
2167 if (!(tmp & DP_PORT_EN))
2168 return false;
2169
bc7d38a4 2170 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 2171 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 2172 } else if (IS_CHERRYVIEW(dev)) {
2173 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 2174 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 2175 *pipe = PORT_TO_PIPE(tmp);
2176 } else {
2177 u32 trans_sel;
2178 u32 trans_dp;
2179 int i;
2180
2181 switch (intel_dp->output_reg) {
2182 case PCH_DP_B:
2183 trans_sel = TRANS_DP_PORT_SEL_B;
2184 break;
2185 case PCH_DP_C:
2186 trans_sel = TRANS_DP_PORT_SEL_C;
2187 break;
2188 case PCH_DP_D:
2189 trans_sel = TRANS_DP_PORT_SEL_D;
2190 break;
2191 default:
2192 return true;
2193 }
2194
055e393f 2195 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2196 trans_dp = I915_READ(TRANS_DP_CTL(i));
2197 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2198 *pipe = i;
2199 return true;
2200 }
2201 }
19d8fe15 2202
4a0833ec
DV		 2203 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2204 intel_dp->output_reg);
2205 }
d240f20f 2206
19d8fe15
DV		 2207 return true;
2208}
d240f20f 2209
045ac3b5 2210static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2211 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2212{
2213 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2214 u32 tmp, flags = 0;
63000ef6
XZ		 2215 struct drm_device *dev = encoder->base.dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 enum port port = dp_to_dig_port(intel_dp)->port;
2218 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2219 int dotclock;
045ac3b5 2220
9ed109a7
DV		 2221 tmp = I915_READ(intel_dp->output_reg);
2222 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2223 pipe_config->has_audio = true;
2224
63000ef6 2225 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2226 if (tmp & DP_SYNC_HS_HIGH)
2227 flags |= DRM_MODE_FLAG_PHSYNC;
2228 else
2229 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2230
63000ef6
XZ		 2231 if (tmp & DP_SYNC_VS_HIGH)
2232 flags |= DRM_MODE_FLAG_PVSYNC;
2233 else
2234 flags |= DRM_MODE_FLAG_NVSYNC;
2235 } else {
2236 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2237 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2238 flags |= DRM_MODE_FLAG_PHSYNC;
2239 else
2240 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2241
63000ef6
XZ		 2242 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2243 flags |= DRM_MODE_FLAG_PVSYNC;
2244 else
2245 flags |= DRM_MODE_FLAG_NVSYNC;
2246 }
045ac3b5 2247
2d112de7 2248 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2249
8c875fca
VS		 2250 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2251 tmp & DP_COLOR_RANGE_16_235)
2252 pipe_config->limited_color_range = true;
2253
eb14cb74
VS		 2254 pipe_config->has_dp_encoder = true;
2255
2256 intel_dp_get_m_n(crtc, pipe_config);
2257
18442d08 2258 if (port == PORT_A) {
f1f644dc
JB		 2259 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2260 pipe_config->port_clock = 162000;
2261 else
2262 pipe_config->port_clock = 270000;
2263 }
18442d08
VS		 2264
2265 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2266 &pipe_config->dp_m_n);
2267
2268 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2269 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2270
2d112de7 2271 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2272
c6cd2ee2
JN		 2273 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2274 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2275 /*
2276 * This is a big fat ugly hack.
2277 *
2278 * Some machines in UEFI boot mode provide us a VBT that has 18
2279 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2280 * unknown we fail to light up. Yet the same BIOS boots up with
2281 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2282 * max, not what it tells us to use.
2283 *
2284 * Note: This will still be broken if the eDP panel is not lit
2285 * up by the BIOS, and thus we can't get the mode at module
2286 * load.
2287 */
2288 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2289 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2290 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2291 }
045ac3b5
JB		 2292}
2293
e8cb4558 2294static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2295{
e8cb4558 2296 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2297 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2298 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2299
6e3c9717 2300 if (crtc->config->has_audio)
495a5bb8 2301 intel_audio_codec_disable(encoder);
6cb49835 2302
b32c6f48
RV		 2303 if (HAS_PSR(dev) && !HAS_DDI(dev))
2304 intel_psr_disable(intel_dp);
2305
6cb49835
DV		 2306 /* Make sure the panel is off before trying to change the mode. But also
2307 * ensure that we have vdd while we switch off the panel. */
24f3e092 2308 intel_edp_panel_vdd_on(intel_dp);
4be73780 2309 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2310 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2311 intel_edp_panel_off(intel_dp);
3739850b 2312
08aff3fe
VS		 2313 /* disable the port before the pipe on g4x */
2314 if (INTEL_INFO(dev)->gen < 5)
3739850b 2315 intel_dp_link_down(intel_dp);
d240f20f
JB		 2316}
2317
08aff3fe 2318static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2319{
2bd2ad64 2320 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2321 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2322
49277c31 2323 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2324 if (port == PORT_A)
2325 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2326}
2327
2328static void vlv_post_disable_dp(struct intel_encoder *encoder)
2329{
2330 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2331
2332 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2333}
2334
580d3811
VS		 2335static void chv_post_disable_dp(struct intel_encoder *encoder)
2336{
2337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2338 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2339 struct drm_device *dev = encoder->base.dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct intel_crtc *intel_crtc =
2342 to_intel_crtc(encoder->base.crtc);
2343 enum dpio_channel ch = vlv_dport_to_channel(dport);
2344 enum pipe pipe = intel_crtc->pipe;
2345 u32 val;
2346
2347 intel_dp_link_down(intel_dp);
2348
2349 mutex_lock(&dev_priv->dpio_lock);
2350
2351 /* Propagate soft reset to data lane reset */
97fd4d5c 2352 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2353 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2354 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2355
97fd4d5c
VS		 2356 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2357 val |= CHV_PCS_REQ_SOFTRESET_EN;
2358 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2359
2360 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2361 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2362 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2363
2364 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2365 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2366 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2367
2368 mutex_unlock(&dev_priv->dpio_lock);
2369}
2370
7b13b58a
VS		 2371static void
2372_intel_dp_set_link_train(struct intel_dp *intel_dp,
2373 uint32_t *DP,
2374 uint8_t dp_train_pat)
2375{
2376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2377 struct drm_device *dev = intel_dig_port->base.base.dev;
2378 struct drm_i915_private *dev_priv = dev->dev_private;
2379 enum port port = intel_dig_port->port;
2380
2381 if (HAS_DDI(dev)) {
2382 uint32_t temp = I915_READ(DP_TP_CTL(port));
2383
2384 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2385 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2386 else
2387 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2388
2389 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2390 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2391 case DP_TRAINING_PATTERN_DISABLE:
2392 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2393
2394 break;
2395 case DP_TRAINING_PATTERN_1:
2396 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2397 break;
2398 case DP_TRAINING_PATTERN_2:
2399 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2400 break;
2401 case DP_TRAINING_PATTERN_3:
2402 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2403 break;
2404 }
2405 I915_WRITE(DP_TP_CTL(port), temp);
2406
2407 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2408 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2409
2410 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2411 case DP_TRAINING_PATTERN_DISABLE:
2412 *DP |= DP_LINK_TRAIN_OFF_CPT;
2413 break;
2414 case DP_TRAINING_PATTERN_1:
2415 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2416 break;
2417 case DP_TRAINING_PATTERN_2:
2418 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2419 break;
2420 case DP_TRAINING_PATTERN_3:
2421 DRM_ERROR("DP training pattern 3 not supported\n");
2422 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2423 break;
2424 }
2425
2426 } else {
2427 if (IS_CHERRYVIEW(dev))
2428 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2429 else
2430 *DP &= ~DP_LINK_TRAIN_MASK;
2431
2432 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2433 case DP_TRAINING_PATTERN_DISABLE:
2434 *DP |= DP_LINK_TRAIN_OFF;
2435 break;
2436 case DP_TRAINING_PATTERN_1:
2437 *DP |= DP_LINK_TRAIN_PAT_1;
2438 break;
2439 case DP_TRAINING_PATTERN_2:
2440 *DP |= DP_LINK_TRAIN_PAT_2;
2441 break;
2442 case DP_TRAINING_PATTERN_3:
2443 if (IS_CHERRYVIEW(dev)) {
2444 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2445 } else {
2446 DRM_ERROR("DP training pattern 3 not supported\n");
2447 *DP |= DP_LINK_TRAIN_PAT_2;
2448 }
2449 break;
2450 }
2451 }
2452}
2453
2454static void intel_dp_enable_port(struct intel_dp *intel_dp)
2455{
2456 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2457 struct drm_i915_private *dev_priv = dev->dev_private;
2458
7b13b58a
VS		 2459 /* enable with pattern 1 (as per spec) */
2460 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2461 DP_TRAINING_PATTERN_1);
2462
2463 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2464 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2465
2466 /*
2467 * Magic for VLV/CHV. We _must_ first set up the register
2468 * without actually enabling the port, and then do another
2469 * write to enable the port. Otherwise link training will
2470 * fail when the power sequencer is freshly used for this port.
2471 */
2472 intel_dp->DP |= DP_PORT_EN;
2473
2474 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2475 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2476}
2477
e8cb4558 2478static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2479{
e8cb4558
DV		 2480 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2481 struct drm_device *dev = encoder->base.dev;
2482 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2483 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2484 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2485
0c33d8d7
DV		 2486 if (WARN_ON(dp_reg & DP_PORT_EN))
2487 return;
5d613501 2488
093e3f13
VS		 2489 pps_lock(intel_dp);
2490
2491 if (IS_VALLEYVIEW(dev))
2492 vlv_init_panel_power_sequencer(intel_dp);
2493
7b13b58a 2494 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2495
2496 edp_panel_vdd_on(intel_dp);
2497 edp_panel_on(intel_dp);
2498 edp_panel_vdd_off(intel_dp, true);
2499
2500 pps_unlock(intel_dp);
2501
61234fa5
VS		 2502 if (IS_VALLEYVIEW(dev))
2503 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2504
f01eca2e 2505 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2506 intel_dp_start_link_train(intel_dp);
33a34e4e 2507 intel_dp_complete_link_train(intel_dp);
3ab9c637 2508 intel_dp_stop_link_train(intel_dp);
c1dec79a 2509
6e3c9717 2510 if (crtc->config->has_audio) {
c1dec79a
JN		 2511 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2512 pipe_name(crtc->pipe));
2513 intel_audio_codec_enable(encoder);
2514 }
ab1f90f9 2515}
89b667f8 2516
ecff4f3b
JN		 2517static void g4x_enable_dp(struct intel_encoder *encoder)
2518{
828f5c6e
JN		 2519 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2520
ecff4f3b 2521 intel_enable_dp(encoder);
4be73780 2522 intel_edp_backlight_on(intel_dp);
ab1f90f9 2523}
89b667f8 2524
ab1f90f9
JN		 2525static void vlv_enable_dp(struct intel_encoder *encoder)
2526{
828f5c6e
JN		 2527 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2528
4be73780 2529 intel_edp_backlight_on(intel_dp);
b32c6f48 2530 intel_psr_enable(intel_dp);
d240f20f
JB		 2531}
2532
ecff4f3b 2533static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2534{
2535 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2536 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2537
8ac33ed3
DV		 2538 intel_dp_prepare(encoder);
2539
d41f1efb
DV		 2540 /* Only ilk+ has port A */
2541 if (dport->port == PORT_A) {
2542 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2543 ironlake_edp_pll_on(intel_dp);
d41f1efb 2544 }
ab1f90f9
JN		 2545}
2546
83b84597
VS		 2547static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2548{
2549 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2550 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2551 enum pipe pipe = intel_dp->pps_pipe;
2552 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2553
2554 edp_panel_vdd_off_sync(intel_dp);
2555
2556 /*
2557 * VLV seems to get confused when multiple power seqeuencers
2558 * have the same port selected (even if only one has power/vdd
2559 * enabled). The failure manifests as vlv_wait_port_ready() failing
2560 * CHV on the other hand doesn't seem to mind having the same port
2561 * selected in multiple power seqeuencers, but let's clear the
2562 * port select always when logically disconnecting a power sequencer
2563 * from a port.
2564 */
2565 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2566 pipe_name(pipe), port_name(intel_dig_port->port));
2567 I915_WRITE(pp_on_reg, 0);
2568 POSTING_READ(pp_on_reg);
2569
2570 intel_dp->pps_pipe = INVALID_PIPE;
2571}
2572
a4a5d2f8
VS		 2573static void vlv_steal_power_sequencer(struct drm_device *dev,
2574 enum pipe pipe)
2575{
2576 struct drm_i915_private *dev_priv = dev->dev_private;
2577 struct intel_encoder *encoder;
2578
2579 lockdep_assert_held(&dev_priv->pps_mutex);
2580
ac3c12e4
VS		 2581 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2582 return;
2583
a4a5d2f8
VS		 2584 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2585 base.head) {
2586 struct intel_dp *intel_dp;
773538e8 2587 enum port port;
a4a5d2f8
VS		 2588
2589 if (encoder->type != INTEL_OUTPUT_EDP)
2590 continue;
2591
2592 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2593 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2594
2595 if (intel_dp->pps_pipe != pipe)
2596 continue;
2597
2598 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2599 pipe_name(pipe), port_name(port));
a4a5d2f8 2600
034e43c6
VS		 2601 WARN(encoder->connectors_active,
2602 "stealing pipe %c power sequencer from active eDP port %c\n",
2603 pipe_name(pipe), port_name(port));
a4a5d2f8 2604
a4a5d2f8 2605 /* make sure vdd is off before we steal it */
83b84597 2606 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2607 }
2608}
2609
2610static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2611{
2612 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2613 struct intel_encoder *encoder = &intel_dig_port->base;
2614 struct drm_device *dev = encoder->base.dev;
2615 struct drm_i915_private *dev_priv = dev->dev_private;
2616 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2617
2618 lockdep_assert_held(&dev_priv->pps_mutex);
2619
093e3f13
VS		 2620 if (!is_edp(intel_dp))
2621 return;
2622
a4a5d2f8
VS		 2623 if (intel_dp->pps_pipe == crtc->pipe)
2624 return;
2625
2626 /*
2627 * If another power sequencer was being used on this
2628 * port previously make sure to turn off vdd there while
2629 * we still have control of it.
2630 */
2631 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2632 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2633
2634 /*
2635 * We may be stealing the power
2636 * sequencer from another port.
2637 */
2638 vlv_steal_power_sequencer(dev, crtc->pipe);
2639
2640 /* now it's all ours */
2641 intel_dp->pps_pipe = crtc->pipe;
2642
2643 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2644 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2645
2646 /* init power sequencer on this pipe and port */
36b5f425
VS		 2647 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2648 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2649}
2650
ab1f90f9 2651static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2652{
2bd2ad64 2653 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2654 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2655 struct drm_device *dev = encoder->base.dev;
89b667f8 2656 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2657 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2658 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2659 int pipe = intel_crtc->pipe;
2660 u32 val;
a4fc5ed6 2661
ab1f90f9 2662 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2663
ab3c759a 2664 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2665 val = 0;
2666 if (pipe)
2667 val |= (1<<21);
2668 else
2669 val &= ~(1<<21);
2670 val |= 0x001000c4;
ab3c759a
CML		 2671 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2672 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2673 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2674
ab1f90f9
JN		 2675 mutex_unlock(&dev_priv->dpio_lock);
2676
2677 intel_enable_dp(encoder);
89b667f8
JB		 2678}
2679
ecff4f3b 2680static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2681{
2682 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2683 struct drm_device *dev = encoder->base.dev;
2684 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2685 struct intel_crtc *intel_crtc =
2686 to_intel_crtc(encoder->base.crtc);
e4607fcf 2687 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2688 int pipe = intel_crtc->pipe;
89b667f8 2689
8ac33ed3
DV		 2690 intel_dp_prepare(encoder);
2691
89b667f8 2692 /* Program Tx lane resets to default */
0980a60f 2693 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2694 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2695 DPIO_PCS_TX_LANE2_RESET |
2696 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2697 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2698 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2699 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2700 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2701 DPIO_PCS_CLK_SOFT_RESET);
2702
2703 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2704 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2705 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2706 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2707 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2708}
2709
e4a1d846
CML		 2710static void chv_pre_enable_dp(struct intel_encoder *encoder)
2711{
2712 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2713 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2714 struct drm_device *dev = encoder->base.dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2716 struct intel_crtc *intel_crtc =
2717 to_intel_crtc(encoder->base.crtc);
2718 enum dpio_channel ch = vlv_dport_to_channel(dport);
2719 int pipe = intel_crtc->pipe;
2720 int data, i;
949c1d43 2721 u32 val;
e4a1d846 2722
e4a1d846 2723 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2724
570e2a74
VS		 2725 /* allow hardware to manage TX FIFO reset source */
2726 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2727 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2728 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2729
2730 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2731 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2732 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2733
949c1d43 2734 /* Deassert soft data lane reset*/
97fd4d5c 2735 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2736 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2737 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2738
2739 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2740 val |= CHV_PCS_REQ_SOFTRESET_EN;
2741 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2742
2743 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2744 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2746
97fd4d5c 2747 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2748 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2749 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2750
2751 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2752 for (i = 0; i < 4; i++) {
2753 /* Set the latency optimal bit */
2754 data = (i == 1) ? 0x0 : 0x6;
2755 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2756 data << DPIO_FRC_LATENCY_SHFIT);
2757
2758 /* Set the upar bit */
2759 data = (i == 1) ? 0x0 : 0x1;
2760 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2761 data << DPIO_UPAR_SHIFT);
2762 }
2763
2764 /* Data lane stagger programming */
2765 /* FIXME: Fix up value only after power analysis */
2766
2767 mutex_unlock(&dev_priv->dpio_lock);
2768
e4a1d846 2769 intel_enable_dp(encoder);
e4a1d846
CML		 2770}
2771
9197c88b
VS		 2772static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2773{
2774 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2775 struct drm_device *dev = encoder->base.dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc =
2778 to_intel_crtc(encoder->base.crtc);
2779 enum dpio_channel ch = vlv_dport_to_channel(dport);
2780 enum pipe pipe = intel_crtc->pipe;
2781 u32 val;
2782
625695f8
VS		 2783 intel_dp_prepare(encoder);
2784
9197c88b
VS		 2785 mutex_lock(&dev_priv->dpio_lock);
2786
b9e5ac3c
VS		 2787 /* program left/right clock distribution */
2788 if (pipe != PIPE_B) {
2789 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2790 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2791 if (ch == DPIO_CH0)
2792 val |= CHV_BUFLEFTENA1_FORCE;
2793 if (ch == DPIO_CH1)
2794 val |= CHV_BUFRIGHTENA1_FORCE;
2795 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2796 } else {
2797 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2798 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2799 if (ch == DPIO_CH0)
2800 val |= CHV_BUFLEFTENA2_FORCE;
2801 if (ch == DPIO_CH1)
2802 val |= CHV_BUFRIGHTENA2_FORCE;
2803 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2804 }
2805
9197c88b
VS		 2806 /* program clock channel usage */
2807 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2808 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2809 if (pipe != PIPE_B)
2810 val &= ~CHV_PCS_USEDCLKCHANNEL;
2811 else
2812 val |= CHV_PCS_USEDCLKCHANNEL;
2813 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2814
2815 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2816 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2817 if (pipe != PIPE_B)
2818 val &= ~CHV_PCS_USEDCLKCHANNEL;
2819 else
2820 val |= CHV_PCS_USEDCLKCHANNEL;
2821 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2822
2823 /*
2824 * This a a bit weird since generally CL
2825 * matches the pipe, but here we need to
2826 * pick the CL based on the port.
2827 */
2828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2829 if (pipe != PIPE_B)
2830 val &= ~CHV_CMN_USEDCLKCHANNEL;
2831 else
2832 val |= CHV_CMN_USEDCLKCHANNEL;
2833 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2834
2835 mutex_unlock(&dev_priv->dpio_lock);
2836}
2837
a4fc5ed6 2838/*
df0c237d
JB		 2839 * Native read with retry for link status and receiver capability reads for
2840 * cases where the sink may still be asleep.
9d1a1031
JN		 2841 *
2842 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2843 * supposed to retry 3 times per the spec.
a4fc5ed6 2844 */
9d1a1031
JN		 2845static ssize_t
2846intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2847 void *buffer, size_t size)
a4fc5ed6 2848{
9d1a1031
JN		 2849 ssize_t ret;
2850 int i;
61da5fab 2851
f6a19066
VS		 2852 /*
2853 * Sometime we just get the same incorrect byte repeated
2854 * over the entire buffer. Doing just one throw away read
2855 * initially seems to "solve" it.
2856 */
2857 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2858
61da5fab 2859 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2860 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2861 if (ret == size)
2862 return ret;
61da5fab
JB		 2863 msleep(1);
2864 }
a4fc5ed6 2865
9d1a1031 2866 return ret;
a4fc5ed6
KP		 2867}
2868
2869/*
2870 * Fetch AUX CH registers 0x202 - 0x207 which contain
2871 * link status information
2872 */
2873static bool
93f62dad 2874intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2875{
9d1a1031
JN		 2876 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2877 DP_LANE0_1_STATUS,
2878 link_status,
2879 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2880}
2881
1100244e 2882/* These are source-specific values. */
a4fc5ed6 2883static uint8_t
1a2eb460 2884intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2885{
30add22d 2886 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2887 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2888 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2889
7ad14a29
SJ		 2890 if (INTEL_INFO(dev)->gen >= 9) {
2891 if (dev_priv->vbt.edp_low_vswing && port == PORT_A)
2892 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2893 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2894 } else if (IS_VALLEYVIEW(dev))
bd60018a 2895 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2896 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2897 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2898 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2899 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2900 else
bd60018a 2901 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2902}
2903
2904static uint8_t
2905intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2906{
30add22d 2907 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2908 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2909
5a9d1f1a
DL		 2910 if (INTEL_INFO(dev)->gen >= 9) {
2911 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2913 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2915 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2917 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2919 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2920 default:
2921 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2922 }
2923 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2924 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2925 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2926 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2927 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2928 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2930 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2931 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2932 default:
bd60018a 2933 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2934 }
e2fa6fba
P		 2935 } else if (IS_VALLEYVIEW(dev)) {
2936 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2937 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2938 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2940 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2941 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2942 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2944 default:
bd60018a 2945 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2946 }
bc7d38a4 2947 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2948 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2949 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2950 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2953 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2954 default:
bd60018a 2955 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2956 }
2957 } else {
2958 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2960 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2962 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2964 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2966 default:
bd60018a 2967 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2968 }
a4fc5ed6
KP		 2969 }
2970}
2971
e2fa6fba
P		 2972static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2973{
2974 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2975 struct drm_i915_private *dev_priv = dev->dev_private;
2976 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2977 struct intel_crtc *intel_crtc =
2978 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2979 unsigned long demph_reg_value, preemph_reg_value,
2980 uniqtranscale_reg_value;
2981 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2982 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2983 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2984
2985 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2986 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2987 preemph_reg_value = 0x0004000;
2988 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2990 demph_reg_value = 0x2B405555;
2991 uniqtranscale_reg_value = 0x552AB83A;
2992 break;
bd60018a 2993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2994 demph_reg_value = 0x2B404040;
2995 uniqtranscale_reg_value = 0x5548B83A;
2996 break;
bd60018a 2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2998 demph_reg_value = 0x2B245555;
2999 uniqtranscale_reg_value = 0x5560B83A;
3000 break;
bd60018a 3001 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3002 demph_reg_value = 0x2B405555;
3003 uniqtranscale_reg_value = 0x5598DA3A;
3004 break;
3005 default:
3006 return 0;
3007 }
3008 break;
bd60018a 3009 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3010 preemph_reg_value = 0x0002000;
3011 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3013 demph_reg_value = 0x2B404040;
3014 uniqtranscale_reg_value = 0x5552B83A;
3015 break;
bd60018a 3016 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3017 demph_reg_value = 0x2B404848;
3018 uniqtranscale_reg_value = 0x5580B83A;
3019 break;
bd60018a 3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3021 demph_reg_value = 0x2B404040;
3022 uniqtranscale_reg_value = 0x55ADDA3A;
3023 break;
3024 default:
3025 return 0;
3026 }
3027 break;
bd60018a 3028 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3029 preemph_reg_value = 0x0000000;
3030 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3032 demph_reg_value = 0x2B305555;
3033 uniqtranscale_reg_value = 0x5570B83A;
3034 break;
bd60018a 3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3036 demph_reg_value = 0x2B2B4040;
3037 uniqtranscale_reg_value = 0x55ADDA3A;
3038 break;
3039 default:
3040 return 0;
3041 }
3042 break;
bd60018a 3043 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3044 preemph_reg_value = 0x0006000;
3045 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3047 demph_reg_value = 0x1B405555;
3048 uniqtranscale_reg_value = 0x55ADDA3A;
3049 break;
3050 default:
3051 return 0;
3052 }
3053 break;
3054 default:
3055 return 0;
3056 }
3057
0980a60f 3058 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3059 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3060 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3061 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3062 uniqtranscale_reg_value);
ab3c759a
CML		 3063 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3064 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3065 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3066 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3067 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3068
3069 return 0;
3070}
3071
e4a1d846
CML		 3072static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3073{
3074 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3077 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3078 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3079 uint8_t train_set = intel_dp->train_set[0];
3080 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3081 enum pipe pipe = intel_crtc->pipe;
3082 int i;
e4a1d846
CML		 3083
3084 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3085 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3086 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3088 deemph_reg_value = 128;
3089 margin_reg_value = 52;
3090 break;
bd60018a 3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3092 deemph_reg_value = 128;
3093 margin_reg_value = 77;
3094 break;
bd60018a 3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3096 deemph_reg_value = 128;
3097 margin_reg_value = 102;
3098 break;
bd60018a 3099 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3100 deemph_reg_value = 128;
3101 margin_reg_value = 154;
3102 /* FIXME extra to set for 1200 */
3103 break;
3104 default:
3105 return 0;
3106 }
3107 break;
bd60018a 3108 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3109 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3111 deemph_reg_value = 85;
3112 margin_reg_value = 78;
3113 break;
bd60018a 3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3115 deemph_reg_value = 85;
3116 margin_reg_value = 116;
3117 break;
bd60018a 3118 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3119 deemph_reg_value = 85;
3120 margin_reg_value = 154;
3121 break;
3122 default:
3123 return 0;
3124 }
3125 break;
bd60018a 3126 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3127 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3128 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3129 deemph_reg_value = 64;
3130 margin_reg_value = 104;
3131 break;
bd60018a 3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3133 deemph_reg_value = 64;
3134 margin_reg_value = 154;
3135 break;
3136 default:
3137 return 0;
3138 }
3139 break;
bd60018a 3140 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3141 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3142 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3143 deemph_reg_value = 43;
3144 margin_reg_value = 154;
3145 break;
3146 default:
3147 return 0;
3148 }
3149 break;
3150 default:
3151 return 0;
3152 }
3153
3154 mutex_lock(&dev_priv->dpio_lock);
3155
3156 /* Clear calc init */
1966e59e
VS		 3157 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3158 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3159 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3160 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3161 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3162
3163 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3164 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3165 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3166 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3167 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3168
a02ef3c7
VS		 3169 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3170 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3171 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3172 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3173
3174 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3175 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3176 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3177 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3178
e4a1d846 3179 /* Program swing deemph */
f72df8db
VS		 3180 for (i = 0; i < 4; i++) {
3181 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3182 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3183 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3184 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3185 }
e4a1d846
CML		 3186
3187 /* Program swing margin */
f72df8db
VS		 3188 for (i = 0; i < 4; i++) {
3189 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3190 val &= ~DPIO_SWING_MARGIN000_MASK;
3191 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3192 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3193 }
e4a1d846
CML		 3194
3195 /* Disable unique transition scale */
f72df8db
VS		 3196 for (i = 0; i < 4; i++) {
3197 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3198 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3199 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3200 }
e4a1d846
CML		 3201
3202 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3203 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3204 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3205 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3206
3207 /*
3208 * The document said it needs to set bit 27 for ch0 and bit 26
3209 * for ch1. Might be a typo in the doc.
3210 * For now, for this unique transition scale selection, set bit
3211 * 27 for ch0 and ch1.
3212 */
f72df8db
VS		 3213 for (i = 0; i < 4; i++) {
3214 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3215 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3216 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3217 }
e4a1d846 3218
f72df8db
VS		 3219 for (i = 0; i < 4; i++) {
3220 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3221 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3222 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3223 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3224 }
e4a1d846
CML		 3225 }
3226
3227 /* Start swing calculation */
1966e59e
VS		 3228 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3229 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3230 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3231
3232 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3233 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3234 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3235
3236 /* LRC Bypass */
3237 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3238 val |= DPIO_LRC_BYPASS;
3239 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3240
3241 mutex_unlock(&dev_priv->dpio_lock);
3242
3243 return 0;
3244}
3245
a4fc5ed6 3246static void
0301b3ac
JN		 3247intel_get_adjust_train(struct intel_dp *intel_dp,
3248 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3249{
3250 uint8_t v = 0;
3251 uint8_t p = 0;
3252 int lane;
1a2eb460
KP		 3253 uint8_t voltage_max;
3254 uint8_t preemph_max;
a4fc5ed6 3255
33a34e4e 3256 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3257 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3258 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3259
3260 if (this_v > v)
3261 v = this_v;
3262 if (this_p > p)
3263 p = this_p;
3264 }
3265
1a2eb460 3266 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3267 if (v >= voltage_max)
3268 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3269
1a2eb460
KP		 3270 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3271 if (p >= preemph_max)
3272 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3273
3274 for (lane = 0; lane < 4; lane++)
33a34e4e 3275 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3276}
3277
3278static uint32_t
f0a3424e 3279intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3280{
3cf2efb1 3281 uint32_t signal_levels = 0;
a4fc5ed6 3282
3cf2efb1 3283 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3285 default:
3286 signal_levels |= DP_VOLTAGE_0_4;
3287 break;
bd60018a 3288 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3289 signal_levels |= DP_VOLTAGE_0_6;
3290 break;
bd60018a 3291 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3292 signal_levels |= DP_VOLTAGE_0_8;
3293 break;
bd60018a 3294 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3295 signal_levels |= DP_VOLTAGE_1_2;
3296 break;
3297 }
3cf2efb1 3298 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3299 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3300 default:
3301 signal_levels |= DP_PRE_EMPHASIS_0;
3302 break;
bd60018a 3303 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3304 signal_levels |= DP_PRE_EMPHASIS_3_5;
3305 break;
bd60018a 3306 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3307 signal_levels |= DP_PRE_EMPHASIS_6;
3308 break;
bd60018a 3309 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3310 signal_levels |= DP_PRE_EMPHASIS_9_5;
3311 break;
3312 }
3313 return signal_levels;
3314}
3315
e3421a18
ZW		 3316/* Gen6's DP voltage swing and pre-emphasis control */
3317static uint32_t
3318intel_gen6_edp_signal_levels(uint8_t train_set)
3319{
3c5a62b5
YL		 3320 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3321 DP_TRAIN_PRE_EMPHASIS_MASK);
3322 switch (signal_levels) {
bd60018a
SJ		 3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3325 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3327 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3328 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3330 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3331 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3333 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3334 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3336 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3337 default:
3c5a62b5
YL		 3338 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3339 "0x%x\n", signal_levels);
3340 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3341 }
3342}
3343
1a2eb460
KP		 3344/* Gen7's DP voltage swing and pre-emphasis control */
3345static uint32_t
3346intel_gen7_edp_signal_levels(uint8_t train_set)
3347{
3348 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3349 DP_TRAIN_PRE_EMPHASIS_MASK);
3350 switch (signal_levels) {
bd60018a 3351 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3352 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3353 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3354 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3355 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3356 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3357
bd60018a 3358 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3359 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3360 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3361 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3362
bd60018a 3363 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3364 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3365 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3366 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3367
3368 default:
3369 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3370 "0x%x\n", signal_levels);
3371 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3372 }
3373}
3374
d6c0d722
PZ		 3375/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3376static uint32_t
f0a3424e 3377intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3378{
d6c0d722
PZ		 3379 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3380 DP_TRAIN_PRE_EMPHASIS_MASK);
3381 switch (signal_levels) {
bd60018a 3382 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3383 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3384 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3385 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3386 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3387 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3389 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3390
bd60018a 3391 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3392 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3393 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3394 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3395 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3396 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3397
bd60018a 3398 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3399 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3401 return DDI_BUF_TRANS_SELECT(8);
7ad14a29
SJ		 3402
3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3404 return DDI_BUF_TRANS_SELECT(9);
d6c0d722
PZ		 3405 default:
3406 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3407 "0x%x\n", signal_levels);
c5fe6a06 3408 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3409 }
a4fc5ed6
KP		 3410}
3411
96fb9f9b
VK		 3412static void intel_bxt_signal_levels(struct intel_dp *intel_dp)
3413{
3414 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3415 enum port port = dport->port;
3416 struct drm_device *dev = dport->base.base.dev;
3417 struct intel_encoder *encoder = &dport->base;
3418 uint8_t train_set = intel_dp->train_set[0];
3419 uint32_t level = 0;
3420
3421 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3422 DP_TRAIN_PRE_EMPHASIS_MASK);
3423 switch (signal_levels) {
3424 default:
3425 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3426 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3427 level = 0;
3428 break;
3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3430 level = 1;
3431 break;
3432 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3433 level = 2;
3434 break;
3435 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3436 level = 3;
3437 break;
3438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3439 level = 4;
3440 break;
3441 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3442 level = 5;
3443 break;
3444 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3445 level = 6;
3446 break;
3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3448 level = 7;
3449 break;
3450 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3451 level = 8;
3452 break;
3453 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3454 level = 9;
3455 break;
3456 }
3457
3458 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
3459}
3460
f0a3424e
PZ		 3461/* Properly updates "DP" with the correct signal levels. */
3462static void
3463intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3464{
3465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3466 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3467 struct drm_device *dev = intel_dig_port->base.base.dev;
3468 uint32_t signal_levels, mask;
3469 uint8_t train_set = intel_dp->train_set[0];
3470
96fb9f9b
VK		 3471 if (IS_BROXTON(dev)) {
3472 signal_levels = 0;
3473 intel_bxt_signal_levels(intel_dp);
3474 mask = 0;
3475 } else if (HAS_DDI(dev)) {
f0a3424e
PZ		 3476 signal_levels = intel_hsw_signal_levels(train_set);
3477 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3478 } else if (IS_CHERRYVIEW(dev)) {
3479 signal_levels = intel_chv_signal_levels(intel_dp);
3480 mask = 0;
e2fa6fba
P		 3481 } else if (IS_VALLEYVIEW(dev)) {
3482 signal_levels = intel_vlv_signal_levels(intel_dp);
3483 mask = 0;
bc7d38a4 3484 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3485 signal_levels = intel_gen7_edp_signal_levels(train_set);
3486 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3487 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3488 signal_levels = intel_gen6_edp_signal_levels(train_set);
3489 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3490 } else {
3491 signal_levels = intel_gen4_signal_levels(train_set);
3492 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3493 }
3494
96fb9f9b
VK		 3495 if (mask)
3496 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3497
3498 DRM_DEBUG_KMS("Using vswing level %d\n",
3499 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3500 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3501 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3502 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e
PZ		 3503
3504 *DP = (*DP & ~mask) | signal_levels;
3505}
3506
a4fc5ed6 3507static bool
ea5b213a 3508intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3509 uint32_t *DP,
58e10eb9 3510 uint8_t dp_train_pat)
a4fc5ed6 3511{
174edf1f
PZ		 3512 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3513 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3514 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3515 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3516 int ret, len;
a4fc5ed6 3517
7b13b58a 3518 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3519
70aff66c 3520 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3521 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3522
2cdfe6c8
JN		 3523 buf[0] = dp_train_pat;
3524 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3525 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3526 /* don't write DP_TRAINING_LANEx_SET on disable */
3527 len = 1;
3528 } else {
3529 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3530 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3531 len = intel_dp->lane_count + 1;
47ea7542 3532 }
a4fc5ed6 3533
9d1a1031
JN		 3534 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3535 buf, len);
2cdfe6c8
JN		 3536
3537 return ret == len;
a4fc5ed6
KP		 3538}
3539
70aff66c
JN		 3540static bool
3541intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3542 uint8_t dp_train_pat)
3543{
953d22e8 3544 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3545 intel_dp_set_signal_levels(intel_dp, DP);
3546 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3547}
3548
3549static bool
3550intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3551 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3552{
3553 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3554 struct drm_device *dev = intel_dig_port->base.base.dev;
3555 struct drm_i915_private *dev_priv = dev->dev_private;
3556 int ret;
3557
3558 intel_get_adjust_train(intel_dp, link_status);
3559 intel_dp_set_signal_levels(intel_dp, DP);
3560
3561 I915_WRITE(intel_dp->output_reg, *DP);
3562 POSTING_READ(intel_dp->output_reg);
3563
9d1a1031
JN		 3564 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3565 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3566
3567 return ret == intel_dp->lane_count;
3568}
3569
3ab9c637
ID		 3570static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3571{
3572 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3573 struct drm_device *dev = intel_dig_port->base.base.dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
3575 enum port port = intel_dig_port->port;
3576 uint32_t val;
3577
3578 if (!HAS_DDI(dev))
3579 return;
3580
3581 val = I915_READ(DP_TP_CTL(port));
3582 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3583 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3584 I915_WRITE(DP_TP_CTL(port), val);
3585
3586 /*
3587 * On PORT_A we can have only eDP in SST mode. There the only reason
3588 * we need to set idle transmission mode is to work around a HW issue
3589 * where we enable the pipe while not in idle link-training mode.
3590 * In this case there is requirement to wait for a minimum number of
3591 * idle patterns to be sent.
3592 */
3593 if (port == PORT_A)
3594 return;
3595
3596 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3597 1))
3598 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3599}
3600
33a34e4e 3601/* Enable corresponding port and start training pattern 1 */
c19b0669 3602void
33a34e4e 3603intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3604{
da63a9f2 3605 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3606 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3607 int i;
3608 uint8_t voltage;
cdb0e95b 3609 int voltage_tries, loop_tries;
ea5b213a 3610 uint32_t DP = intel_dp->DP;
6aba5b6c 3611 uint8_t link_config[2];
a4fc5ed6 3612
affa9354 3613 if (HAS_DDI(dev))
c19b0669
PZ		 3614 intel_ddi_prepare_link_retrain(encoder);
3615
3cf2efb1 3616 /* Write the link configuration data */
6aba5b6c
JN		 3617 link_config[0] = intel_dp->link_bw;
3618 link_config[1] = intel_dp->lane_count;
3619 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3620 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3621 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
94ca719e 3622 if (intel_dp->num_sink_rates)
a8f3ef61
SJ		 3623 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3624 &intel_dp->rate_select, 1);
6aba5b6c
JN		 3625
3626 link_config[0] = 0;
3627 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3628 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3629
3630 DP |= DP_PORT_EN;
1a2eb460 3631
70aff66c
JN		 3632 /* clock recovery */
3633 if (!intel_dp_reset_link_train(intel_dp, &DP,
3634 DP_TRAINING_PATTERN_1 |
3635 DP_LINK_SCRAMBLING_DISABLE)) {
3636 DRM_ERROR("failed to enable link training\n");
3637 return;
3638 }
3639
a4fc5ed6 3640 voltage = 0xff;
cdb0e95b
KP		 3641 voltage_tries = 0;
3642 loop_tries = 0;
a4fc5ed6 3643 for (;;) {
70aff66c 3644 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3645
a7c9655f 3646 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3647 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3648 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3649 break;
93f62dad 3650 }
a4fc5ed6 3651
01916270 3652 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3653 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3654 break;
3655 }
3656
3657 /* Check to see if we've tried the max voltage */
3658 for (i = 0; i < intel_dp->lane_count; i++)
3659 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3660 break;
3b4f819d 3661 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3662 ++loop_tries;
3663 if (loop_tries == 5) {
3def84b3 3664 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3665 break;
3666 }
70aff66c
JN		 3667 intel_dp_reset_link_train(intel_dp, &DP,
3668 DP_TRAINING_PATTERN_1 |
3669 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3670 voltage_tries = 0;
3671 continue;
3672 }
a4fc5ed6 3673
3cf2efb1 3674 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3675 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3676 ++voltage_tries;
b06fbda3 3677 if (voltage_tries == 5) {
3def84b3 3678 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3679 break;
3680 }
3681 } else
3682 voltage_tries = 0;
3683 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3684
70aff66c
JN		 3685 /* Update training set as requested by target */
3686 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3687 DRM_ERROR("failed to update link training\n");
3688 break;
3689 }
a4fc5ed6
KP		 3690 }
3691
33a34e4e
JB		 3692 intel_dp->DP = DP;
3693}
3694
c19b0669 3695void
33a34e4e
JB		 3696intel_dp_complete_link_train(struct intel_dp *intel_dp)
3697{
33a34e4e 3698 bool channel_eq = false;
37f80975 3699 int tries, cr_tries;
33a34e4e 3700 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3701 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3702
3703 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3704 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3705 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3706
a4fc5ed6 3707 /* channel equalization */
70aff66c 3708 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3709 training_pattern |
70aff66c
JN		 3710 DP_LINK_SCRAMBLING_DISABLE)) {
3711 DRM_ERROR("failed to start channel equalization\n");
3712 return;
3713 }
3714
a4fc5ed6 3715 tries = 0;
37f80975 3716 cr_tries = 0;
a4fc5ed6
KP		 3717 channel_eq = false;
3718 for (;;) {
70aff66c 3719 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3720
37f80975
JB		 3721 if (cr_tries > 5) {
3722 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3723 break;
3724 }
3725
a7c9655f 3726 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3727 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3728 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3729 break;
70aff66c 3730 }
a4fc5ed6 3731
37f80975 3732 /* Make sure clock is still ok */
01916270 3733 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3734 intel_dp_start_link_train(intel_dp);
70aff66c 3735 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3736 training_pattern |
70aff66c 3737 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3738 cr_tries++;
3739 continue;
3740 }
3741
1ffdff13 3742 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3743 channel_eq = true;
3744 break;
3745 }
a4fc5ed6 3746
37f80975
JB		 3747 /* Try 5 times, then try clock recovery if that fails */
3748 if (tries > 5) {
37f80975 3749 intel_dp_start_link_train(intel_dp);
70aff66c 3750 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3751 training_pattern |
70aff66c 3752 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3753 tries = 0;
3754 cr_tries++;
3755 continue;
3756 }
a4fc5ed6 3757
70aff66c
JN		 3758 /* Update training set as requested by target */
3759 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3760 DRM_ERROR("failed to update link training\n");
3761 break;
3762 }
3cf2efb1 3763 ++tries;
869184a6 3764 }
3cf2efb1 3765
3ab9c637
ID		 3766 intel_dp_set_idle_link_train(intel_dp);
3767
3768 intel_dp->DP = DP;
3769
d6c0d722 3770 if (channel_eq)
07f42258 3771 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3772
3ab9c637
ID		 3773}
3774
3775void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3776{
70aff66c 3777 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3778 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3779}
3780
3781static void
ea5b213a 3782intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3783{
da63a9f2 3784 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3785 enum port port = intel_dig_port->port;
da63a9f2 3786 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3787 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3788 uint32_t DP = intel_dp->DP;
a4fc5ed6 3789
bc76e320 3790 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3791 return;
3792
0c33d8d7 3793 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3794 return;
3795
28c97730 3796 DRM_DEBUG_KMS("\n");
32f9d658 3797
bc7d38a4 3798 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3799 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3800 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3801 } else {
aad3d14d
VS		 3802 if (IS_CHERRYVIEW(dev))
3803 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3804 else
3805 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3806 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3807 }
fe255d00 3808 POSTING_READ(intel_dp->output_reg);
5eb08b69 3809
493a7081 3810 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3811 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
5bddd17f
EA		 3812 /* Hardware workaround: leaving our transcoder select
3813 * set to transcoder B while it's off will prevent the
3814 * corresponding HDMI output on transcoder A.
3815 *
3816 * Combine this with another hardware workaround:
3817 * transcoder select bit can only be cleared while the
3818 * port is enabled.
3819 */
3820 DP &= ~DP_PIPEB_SELECT;
3821 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3822 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3823 }
3824
832afda6 3825 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3826 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3827 POSTING_READ(intel_dp->output_reg);
f01eca2e 3828 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3829}
3830
26d61aad
KP		 3831static bool
3832intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3833{
a031d709
RV		 3834 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3835 struct drm_device *dev = dig_port->base.base.dev;
3836 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3837 uint8_t rev;
a031d709 3838
9d1a1031
JN		 3839 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3840 sizeof(intel_dp->dpcd)) < 0)
edb39244 3841 return false; /* aux transfer failed */
92fd8fd1 3842
a8e98153 3843 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3844
edb39244
AJ		 3845 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3846 return false; /* DPCD not present */
3847
2293bb5c
SK		 3848 /* Check if the panel supports PSR */
3849 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3850 if (is_edp(intel_dp)) {
9d1a1031
JN		 3851 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3852 intel_dp->psr_dpcd,
3853 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3854 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3855 dev_priv->psr.sink_support = true;
50003939 3856 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3857 }
474d1ec4
SJ		 3858
3859 if (INTEL_INFO(dev)->gen >= 9 &&
3860 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3861 uint8_t frame_sync_cap;
3862
3863 dev_priv->psr.sink_support = true;
3864 intel_dp_dpcd_read_wake(&intel_dp->aux,
3865 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3866 &frame_sync_cap, 1);
3867 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3868 /* PSR2 needs frame sync as well */
3869 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3870 DRM_DEBUG_KMS("PSR2 %s on sink",
3871 dev_priv->psr.psr2_support ? "supported" : "not supported");
3872 }
50003939
JN		 3873 }
3874
7809a611 3875 /* Training Pattern 3 support, both source and sink */
06ea66b6 3876 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3877 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3878 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3879 intel_dp->use_tps3 = true;
f8d8a672 3880 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3881 } else
3882 intel_dp->use_tps3 = false;
3883
fc0f8e25
SJ		 3884 /* Intermediate frequency support */
3885 if (is_edp(intel_dp) &&
3886 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3887 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3888 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3889 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3890 int i;
3891
fc0f8e25
SJ		 3892 intel_dp_dpcd_read_wake(&intel_dp->aux,
3893 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3894 sink_rates,
3895 sizeof(sink_rates));
ea2d8a42 3896
94ca719e
VS		 3897 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3898 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3899
3900 if (val == 0)
3901 break;
3902
94ca719e 3903 intel_dp->sink_rates[i] = val * 200;
ea2d8a42 3904 }
94ca719e 3905 intel_dp->num_sink_rates = i;
fc0f8e25 3906 }
0336400e
VS		 3907
3908 intel_dp_print_rates(intel_dp);
3909
edb39244
AJ		 3910 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3911 DP_DWN_STRM_PORT_PRESENT))
3912 return true; /* native DP sink */
3913
3914 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3915 return true; /* no per-port downstream info */
3916
9d1a1031
JN		 3917 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3918 intel_dp->downstream_ports,
3919 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3920 return false; /* downstream port status fetch failed */
3921
3922 return true;
92fd8fd1
KP		 3923}
3924
0d198328
AJ		 3925static void
3926intel_dp_probe_oui(struct intel_dp *intel_dp)
3927{
3928 u8 buf[3];
3929
3930 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3931 return;
3932
9d1a1031 3933 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3934 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3935 buf[0], buf[1], buf[2]);
3936
9d1a1031 3937 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3938 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3939 buf[0], buf[1], buf[2]);
3940}
3941
0e32b39c
DA		 3942static bool
3943intel_dp_probe_mst(struct intel_dp *intel_dp)
3944{
3945 u8 buf[1];
3946
3947 if (!intel_dp->can_mst)
3948 return false;
3949
3950 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3951 return false;
3952
0e32b39c
DA		 3953 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3954 if (buf[0] & DP_MST_CAP) {
3955 DRM_DEBUG_KMS("Sink is MST capable\n");
3956 intel_dp->is_mst = true;
3957 } else {
3958 DRM_DEBUG_KMS("Sink is not MST capable\n");
3959 intel_dp->is_mst = false;
3960 }
3961 }
0e32b39c
DA		 3962
3963 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3964 return intel_dp->is_mst;
3965}
3966
d2e216d0
RV		 3967int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3968{
3969 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3970 struct drm_device *dev = intel_dig_port->base.base.dev;
3971 struct intel_crtc *intel_crtc =
3972 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3973 u8 buf;
3974 int test_crc_count;
3975 int attempts = 6;
d2e216d0 3976
ad9dc91b 3977 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3978 return -EIO;
d2e216d0 3979
ad9dc91b 3980 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3981 return -ENOTTY;
3982
1dda5f93
RV		 3983 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3984 return -EIO;
3985
9d1a1031 3986 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3987 buf | DP_TEST_SINK_START) < 0)
bda0381e 3988 return -EIO;
d2e216d0 3989
1dda5f93 3990 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3991 return -EIO;
ad9dc91b 3992 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3993
ad9dc91b 3994 do {
1dda5f93
RV		 3995 if (drm_dp_dpcd_readb(&intel_dp->aux,
3996 DP_TEST_SINK_MISC, &buf) < 0)
3997 return -EIO;
ad9dc91b
RV		 3998 intel_wait_for_vblank(dev, intel_crtc->pipe);
3999 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4000
4001 if (attempts == 0) {
90bd1f46
DV		 4002 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4003 return -ETIMEDOUT;
ad9dc91b 4004 }
d2e216d0 4005
9d1a1031 4006 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 4007 return -EIO;
d2e216d0 4008
1dda5f93
RV		 4009 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4010 return -EIO;
4011 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4012 buf & ~DP_TEST_SINK_START) < 0)
4013 return -EIO;
ce31d9f4 4014
d2e216d0
RV		 4015 return 0;
4016}
4017
a60f0e38
JB		 4018static bool
4019intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4020{
9d1a1031
JN		 4021 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4022 DP_DEVICE_SERVICE_IRQ_VECTOR,
4023 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4024}
4025
0e32b39c
DA		 4026static bool
4027intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4028{
4029 int ret;
4030
4031 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4032 DP_SINK_COUNT_ESI,
4033 sink_irq_vector, 14);
4034 if (ret != 14)
4035 return false;
4036
4037 return true;
4038}
4039
a60f0e38
JB		 4040static void
4041intel_dp_handle_test_request(struct intel_dp *intel_dp)
4042{
4043 /* NAK by default */
9d1a1031 4044 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 4045}
4046
0e32b39c
DA		 4047static int
4048intel_dp_check_mst_status(struct intel_dp *intel_dp)
4049{
4050 bool bret;
4051
4052 if (intel_dp->is_mst) {
4053 u8 esi[16] = { 0 };
4054 int ret = 0;
4055 int retry;
4056 bool handled;
4057 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4058go_again:
4059 if (bret == true) {
4060
4061 /* check link status - esi[10] = 0x200c */
4062 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4063 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4064 intel_dp_start_link_train(intel_dp);
4065 intel_dp_complete_link_train(intel_dp);
4066 intel_dp_stop_link_train(intel_dp);
4067 }
4068
6f34cc39 4069 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4070 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4071
4072 if (handled) {
4073 for (retry = 0; retry < 3; retry++) {
4074 int wret;
4075 wret = drm_dp_dpcd_write(&intel_dp->aux,
4076 DP_SINK_COUNT_ESI+1,
4077 &esi[1], 3);
4078 if (wret == 3) {
4079 break;
4080 }
4081 }
4082
4083 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4084 if (bret == true) {
6f34cc39 4085 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4086 goto go_again;
4087 }
4088 } else
4089 ret = 0;
4090
4091 return ret;
4092 } else {
4093 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4094 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4095 intel_dp->is_mst = false;
4096 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4097 /* send a hotplug event */
4098 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4099 }
4100 }
4101 return -EINVAL;
4102}
4103
a4fc5ed6
KP		 4104/*
4105 * According to DP spec
4106 * 5.1.2:
4107 * 1. Read DPCD
4108 * 2. Configure link according to Receiver Capabilities
4109 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4110 * 4. Check link status on receipt of hot-plug interrupt
4111 */
a5146200 4112static void
ea5b213a 4113intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4114{
5b215bcf 4115 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4116 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4117 u8 sink_irq_vector;
93f62dad 4118 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4119
5b215bcf
DA		 4120 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4121
da63a9f2 4122 if (!intel_encoder->connectors_active)
d2b996ac 4123 return;
59cd09e1 4124
da63a9f2 4125 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4126 return;
4127
1a125d8a
ID		 4128 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4129 return;
4130
92fd8fd1 4131 /* Try to read receiver status if the link appears to be up */
93f62dad 4132 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4133 return;
4134 }
4135
92fd8fd1 4136 /* Now read the DPCD to see if it's actually running */
26d61aad 4137 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4138 return;
4139 }
4140
a60f0e38
JB		 4141 /* Try to read the source of the interrupt */
4142 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4143 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4144 /* Clear interrupt source */
9d1a1031
JN		 4145 drm_dp_dpcd_writeb(&intel_dp->aux,
4146 DP_DEVICE_SERVICE_IRQ_VECTOR,
4147 sink_irq_vector);
a60f0e38
JB		 4148
4149 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4150 intel_dp_handle_test_request(intel_dp);
4151 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4152 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4153 }
4154
1ffdff13 4155 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4156 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4157 intel_encoder->base.name);
33a34e4e
JB		 4158 intel_dp_start_link_train(intel_dp);
4159 intel_dp_complete_link_train(intel_dp);
3ab9c637 4160 intel_dp_stop_link_train(intel_dp);
33a34e4e 4161 }
a4fc5ed6 4162}
a4fc5ed6 4163
caf9ab24 4164/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4165static enum drm_connector_status
26d61aad 4166intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4167{
caf9ab24 4168 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4169 uint8_t type;
4170
4171 if (!intel_dp_get_dpcd(intel_dp))
4172 return connector_status_disconnected;
4173
4174 /* if there's no downstream port, we're done */
4175 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4176 return connector_status_connected;
caf9ab24
AJ		 4177
4178 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4179 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4180 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4181 uint8_t reg;
9d1a1031
JN		 4182
4183 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4184 &reg, 1) < 0)
caf9ab24 4185 return connector_status_unknown;
9d1a1031 4186
23235177
AJ		 4187 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4188 : connector_status_disconnected;
caf9ab24
AJ		 4189 }
4190
4191 /* If no HPD, poke DDC gently */
0b99836f 4192 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4193 return connector_status_connected;
caf9ab24
AJ		 4194
4195 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4196 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4197 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4198 if (type == DP_DS_PORT_TYPE_VGA ||
4199 type == DP_DS_PORT_TYPE_NON_EDID)
4200 return connector_status_unknown;
4201 } else {
4202 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4203 DP_DWN_STRM_PORT_TYPE_MASK;
4204 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4205 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4206 return connector_status_unknown;
4207 }
caf9ab24
AJ		 4208
4209 /* Anything else is out of spec, warn and ignore */
4210 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4211 return connector_status_disconnected;
71ba9000
AJ		 4212}
4213
d410b56d
CW		 4214static enum drm_connector_status
4215edp_detect(struct intel_dp *intel_dp)
4216{
4217 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4218 enum drm_connector_status status;
4219
4220 status = intel_panel_detect(dev);
4221 if (status == connector_status_unknown)
4222 status = connector_status_connected;
4223
4224 return status;
4225}
4226
5eb08b69 4227static enum drm_connector_status
a9756bb5 4228ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4229{
30add22d 4230 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4233
1b469639
DL		 4234 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4235 return connector_status_disconnected;
4236
26d61aad 4237 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4238}
4239
2a592bec
DA		 4240static int g4x_digital_port_connected(struct drm_device *dev,
4241 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4242{
a4fc5ed6 4243 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4244 uint32_t bit;
5eb08b69 4245
232a6ee9
TP		 4246 if (IS_VALLEYVIEW(dev)) {
4247 switch (intel_dig_port->port) {
4248 case PORT_B:
4249 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4250 break;
4251 case PORT_C:
4252 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4253 break;
4254 case PORT_D:
4255 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4256 break;
4257 default:
2a592bec 4258 return -EINVAL;
232a6ee9
TP		 4259 }
4260 } else {
4261 switch (intel_dig_port->port) {
4262 case PORT_B:
4263 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4264 break;
4265 case PORT_C:
4266 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4267 break;
4268 case PORT_D:
4269 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4270 break;
4271 default:
2a592bec 4272 return -EINVAL;
232a6ee9 4273 }
a4fc5ed6
KP		 4274 }
4275
10f76a38 4276 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4277 return 0;
4278 return 1;
4279}
4280
4281static enum drm_connector_status
4282g4x_dp_detect(struct intel_dp *intel_dp)
4283{
4284 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4286 int ret;
4287
4288 /* Can't disconnect eDP, but you can close the lid... */
4289 if (is_edp(intel_dp)) {
4290 enum drm_connector_status status;
4291
4292 status = intel_panel_detect(dev);
4293 if (status == connector_status_unknown)
4294 status = connector_status_connected;
4295 return status;
4296 }
4297
4298 ret = g4x_digital_port_connected(dev, intel_dig_port);
4299 if (ret == -EINVAL)
4300 return connector_status_unknown;
4301 else if (ret == 0)
a4fc5ed6
KP		 4302 return connector_status_disconnected;
4303
26d61aad 4304 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4305}
4306
8c241fef 4307static struct edid *
beb60608 4308intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4309{
beb60608 4310 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4311
9cd300e0
JN		 4312 /* use cached edid if we have one */
4313 if (intel_connector->edid) {
9cd300e0
JN		 4314 /* invalid edid */
4315 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4316 return NULL;
4317
55e9edeb 4318 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4319 } else
4320 return drm_get_edid(&intel_connector->base,
4321 &intel_dp->aux.ddc);
4322}
8c241fef 4323
beb60608
CW		 4324static void
4325intel_dp_set_edid(struct intel_dp *intel_dp)
4326{
4327 struct intel_connector *intel_connector = intel_dp->attached_connector;
4328 struct edid *edid;
8c241fef 4329
beb60608
CW		 4330 edid = intel_dp_get_edid(intel_dp);
4331 intel_connector->detect_edid = edid;
4332
4333 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4334 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4335 else
4336 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4337}
4338
beb60608
CW		 4339static void
4340intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4341{
beb60608 4342 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4343
beb60608
CW		 4344 kfree(intel_connector->detect_edid);
4345 intel_connector->detect_edid = NULL;
9cd300e0 4346
beb60608
CW		 4347 intel_dp->has_audio = false;
4348}
d6f24d0f 4349
beb60608
CW		 4350static enum intel_display_power_domain
4351intel_dp_power_get(struct intel_dp *dp)
4352{
4353 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4354 enum intel_display_power_domain power_domain;
4355
4356 power_domain = intel_display_port_power_domain(encoder);
4357 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4358
4359 return power_domain;
4360}
d6f24d0f 4361
beb60608
CW		 4362static void
4363intel_dp_power_put(struct intel_dp *dp,
4364 enum intel_display_power_domain power_domain)
4365{
4366 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4367 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4368}
4369
a9756bb5
ZW		 4370static enum drm_connector_status
4371intel_dp_detect(struct drm_connector *connector, bool force)
4372{
4373 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4375 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4376 struct drm_device *dev = connector->dev;
a9756bb5 4377 enum drm_connector_status status;
671dedd2 4378 enum intel_display_power_domain power_domain;
0e32b39c 4379 bool ret;
a9756bb5 4380
164c8598 4381 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4382 connector->base.id, connector->name);
beb60608 4383 intel_dp_unset_edid(intel_dp);
164c8598 4384
0e32b39c
DA		 4385 if (intel_dp->is_mst) {
4386 /* MST devices are disconnected from a monitor POV */
4387 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4388 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4389 return connector_status_disconnected;
0e32b39c
DA		 4390 }
4391
beb60608 4392 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4393
d410b56d
CW		 4394 /* Can't disconnect eDP, but you can close the lid... */
4395 if (is_edp(intel_dp))
4396 status = edp_detect(intel_dp);
4397 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4398 status = ironlake_dp_detect(intel_dp);
4399 else
4400 status = g4x_dp_detect(intel_dp);
4401 if (status != connector_status_connected)
c8c8fb33 4402 goto out;
a9756bb5 4403
0d198328
AJ		 4404 intel_dp_probe_oui(intel_dp);
4405
0e32b39c
DA		 4406 ret = intel_dp_probe_mst(intel_dp);
4407 if (ret) {
4408 /* if we are in MST mode then this connector
4409 won't appear connected or have anything with EDID on it */
4410 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4411 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4412 status = connector_status_disconnected;
4413 goto out;
4414 }
4415
beb60608 4416 intel_dp_set_edid(intel_dp);
a9756bb5 4417
d63885da
PZ		 4418 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4419 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4420 status = connector_status_connected;
4421
4422out:
beb60608 4423 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4424 return status;
a4fc5ed6
KP		 4425}
4426
beb60608
CW		 4427static void
4428intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4429{
df0e9248 4430 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4431 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4432 enum intel_display_power_domain power_domain;
a4fc5ed6 4433
beb60608
CW		 4434 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4435 connector->base.id, connector->name);
4436 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4437
beb60608
CW		 4438 if (connector->status != connector_status_connected)
4439 return;
671dedd2 4440
beb60608
CW		 4441 power_domain = intel_dp_power_get(intel_dp);
4442
4443 intel_dp_set_edid(intel_dp);
4444
4445 intel_dp_power_put(intel_dp, power_domain);
4446
4447 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4448 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4449}
4450
4451static int intel_dp_get_modes(struct drm_connector *connector)
4452{
4453 struct intel_connector *intel_connector = to_intel_connector(connector);
4454 struct edid *edid;
4455
4456 edid = intel_connector->detect_edid;
4457 if (edid) {
4458 int ret = intel_connector_update_modes(connector, edid);
4459 if (ret)
4460 return ret;
4461 }
32f9d658 4462
f8779fda 4463 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4464 if (is_edp(intel_attached_dp(connector)) &&
4465 intel_connector->panel.fixed_mode) {
f8779fda 4466 struct drm_display_mode *mode;
beb60608
CW		 4467
4468 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4469 intel_connector->panel.fixed_mode);
f8779fda 4470 if (mode) {
32f9d658
ZW		 4471 drm_mode_probed_add(connector, mode);
4472 return 1;
4473 }
4474 }
beb60608 4475
32f9d658 4476 return 0;
a4fc5ed6
KP		 4477}
4478
1aad7ac0
CW		 4479static bool
4480intel_dp_detect_audio(struct drm_connector *connector)
4481{
1aad7ac0 4482 bool has_audio = false;
beb60608 4483 struct edid *edid;
1aad7ac0 4484
beb60608
CW		 4485 edid = to_intel_connector(connector)->detect_edid;
4486 if (edid)
1aad7ac0 4487 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4488
1aad7ac0
CW		 4489 return has_audio;
4490}
4491
f684960e
CW		 4492static int
4493intel_dp_set_property(struct drm_connector *connector,
4494 struct drm_property *property,
4495 uint64_t val)
4496{
e953fd7b 4497 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4498 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4499 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4500 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4501 int ret;
4502
662595df 4503 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4504 if (ret)
4505 return ret;
4506
3f43c48d 4507 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4508 int i = val;
4509 bool has_audio;
4510
4511 if (i == intel_dp->force_audio)
f684960e
CW		 4512 return 0;
4513
1aad7ac0 4514 intel_dp->force_audio = i;
f684960e 4515
c3e5f67b 4516 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4517 has_audio = intel_dp_detect_audio(connector);
4518 else
c3e5f67b 4519 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4520
4521 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4522 return 0;
4523
1aad7ac0 4524 intel_dp->has_audio = has_audio;
f684960e
CW		 4525 goto done;
4526 }
4527
e953fd7b 4528 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4529 bool old_auto = intel_dp->color_range_auto;
4530 uint32_t old_range = intel_dp->color_range;
4531
55bc60db
VS		 4532 switch (val) {
4533 case INTEL_BROADCAST_RGB_AUTO:
4534 intel_dp->color_range_auto = true;
4535 break;
4536 case INTEL_BROADCAST_RGB_FULL:
4537 intel_dp->color_range_auto = false;
4538 intel_dp->color_range = 0;
4539 break;
4540 case INTEL_BROADCAST_RGB_LIMITED:
4541 intel_dp->color_range_auto = false;
4542 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4543 break;
4544 default:
4545 return -EINVAL;
4546 }
ae4edb80
DV		 4547
4548 if (old_auto == intel_dp->color_range_auto &&
4549 old_range == intel_dp->color_range)
4550 return 0;
4551
e953fd7b
CW		 4552 goto done;
4553 }
4554
53b41837
YN		 4555 if (is_edp(intel_dp) &&
4556 property == connector->dev->mode_config.scaling_mode_property) {
4557 if (val == DRM_MODE_SCALE_NONE) {
4558 DRM_DEBUG_KMS("no scaling not supported\n");
4559 return -EINVAL;
4560 }
4561
4562 if (intel_connector->panel.fitting_mode == val) {
4563 /* the eDP scaling property is not changed */
4564 return 0;
4565 }
4566 intel_connector->panel.fitting_mode = val;
4567
4568 goto done;
4569 }
4570
f684960e
CW		 4571 return -EINVAL;
4572
4573done:
c0c36b94
CW		 4574 if (intel_encoder->base.crtc)
4575 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4576
4577 return 0;
4578}
4579
a4fc5ed6 4580static void
73845adf 4581intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4582{
1d508706 4583 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4584
10e972d3 4585 kfree(intel_connector->detect_edid);
beb60608 4586
9cd300e0
JN		 4587 if (!IS_ERR_OR_NULL(intel_connector->edid))
4588 kfree(intel_connector->edid);
4589
acd8db10
PZ		 4590 /* Can't call is_edp() since the encoder may have been destroyed
4591 * already. */
4592 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4593 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4594
a4fc5ed6 4595 drm_connector_cleanup(connector);
55f78c43 4596 kfree(connector);
a4fc5ed6
KP		 4597}
4598
00c09d70 4599void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4600{
da63a9f2
PZ		 4601 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4602 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4603
4f71d0cb 4604 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4605 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4606 if (is_edp(intel_dp)) {
4607 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4608 /*
4609 * vdd might still be enabled do to the delayed vdd off.
4610 * Make sure vdd is actually turned off here.
4611 */
773538e8 4612 pps_lock(intel_dp);
4be73780 4613 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4614 pps_unlock(intel_dp);
4615
01527b31
CT		 4616 if (intel_dp->edp_notifier.notifier_call) {
4617 unregister_reboot_notifier(&intel_dp->edp_notifier);
4618 intel_dp->edp_notifier.notifier_call = NULL;
4619 }
bd943159 4620 }
c8bd0e49 4621 drm_encoder_cleanup(encoder);
da63a9f2 4622 kfree(intel_dig_port);
24d05927
DV		 4623}
4624
07f9cd0b
ID		 4625static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4626{
4627 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4628
4629 if (!is_edp(intel_dp))
4630 return;
4631
951468f3
VS		 4632 /*
4633 * vdd might still be enabled do to the delayed vdd off.
4634 * Make sure vdd is actually turned off here.
4635 */
afa4e53a 4636 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4637 pps_lock(intel_dp);
07f9cd0b 4638 edp_panel_vdd_off_sync(intel_dp);
773538e8 4639 pps_unlock(intel_dp);
07f9cd0b
ID		 4640}
4641
49e6bc51
VS		 4642static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4643{
4644 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4645 struct drm_device *dev = intel_dig_port->base.base.dev;
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 enum intel_display_power_domain power_domain;
4648
4649 lockdep_assert_held(&dev_priv->pps_mutex);
4650
4651 if (!edp_have_panel_vdd(intel_dp))
4652 return;
4653
4654 /*
4655 * The VDD bit needs a power domain reference, so if the bit is
4656 * already enabled when we boot or resume, grab this reference and
4657 * schedule a vdd off, so we don't hold on to the reference
4658 * indefinitely.
4659 */
4660 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4661 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4662 intel_display_power_get(dev_priv, power_domain);
4663
4664 edp_panel_vdd_schedule_off(intel_dp);
4665}
4666
6d93c0c4
ID		 4667static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4668{
49e6bc51
VS		 4669 struct intel_dp *intel_dp;
4670
4671 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4672 return;
4673
4674 intel_dp = enc_to_intel_dp(encoder);
4675
4676 pps_lock(intel_dp);
4677
4678 /*
4679 * Read out the current power sequencer assignment,
4680 * in case the BIOS did something with it.
4681 */
4682 if (IS_VALLEYVIEW(encoder->dev))
4683 vlv_initial_power_sequencer_setup(intel_dp);
4684
4685 intel_edp_panel_vdd_sanitize(intel_dp);
4686
4687 pps_unlock(intel_dp);
6d93c0c4
ID		 4688}
4689
a4fc5ed6 4690static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4691 .dpms = intel_connector_dpms,
a4fc5ed6 4692 .detect = intel_dp_detect,
beb60608 4693 .force = intel_dp_force,
a4fc5ed6 4694 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4695 .set_property = intel_dp_set_property,
2545e4a6 4696 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4697 .destroy = intel_dp_connector_destroy,
c6f95f27 4698 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4699 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4700};
4701
4702static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4703 .get_modes = intel_dp_get_modes,
4704 .mode_valid = intel_dp_mode_valid,
df0e9248 4705 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4706};
4707
a4fc5ed6 4708static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4709 .reset = intel_dp_encoder_reset,
24d05927 4710 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4711};
4712
0e32b39c 4713void
21d40d37 4714intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4715{
0e32b39c 4716 return;
c8110e52 4717}
6207937d 4718
b2c5c181 4719enum irqreturn
13cf5504
DA		 4720intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4721{
4722 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4723 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4724 struct drm_device *dev = intel_dig_port->base.base.dev;
4725 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4726 enum intel_display_power_domain power_domain;
b2c5c181 4727 enum irqreturn ret = IRQ_NONE;
1c767b33 4728
0e32b39c
DA		 4729 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4730 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4731
7a7f84cc
VS		 4732 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4733 /*
4734 * vdd off can generate a long pulse on eDP which
4735 * would require vdd on to handle it, and thus we
4736 * would end up in an endless cycle of
4737 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4738 */
4739 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4740 port_name(intel_dig_port->port));
a8b3d52f 4741 return IRQ_HANDLED;
7a7f84cc
VS		 4742 }
4743
26fbb774
VS		 4744 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4745 port_name(intel_dig_port->port),
0e32b39c 4746 long_hpd ? "long" : "short");
13cf5504 4747
1c767b33
ID		 4748 power_domain = intel_display_port_power_domain(intel_encoder);
4749 intel_display_power_get(dev_priv, power_domain);
4750
0e32b39c 4751 if (long_hpd) {
2a592bec
DA		 4752
4753 if (HAS_PCH_SPLIT(dev)) {
4754 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4755 goto mst_fail;
4756 } else {
4757 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4758 goto mst_fail;
4759 }
0e32b39c
DA		 4760
4761 if (!intel_dp_get_dpcd(intel_dp)) {
4762 goto mst_fail;
4763 }
4764
4765 intel_dp_probe_oui(intel_dp);
4766
4767 if (!intel_dp_probe_mst(intel_dp))
4768 goto mst_fail;
4769
4770 } else {
4771 if (intel_dp->is_mst) {
1c767b33 4772 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4773 goto mst_fail;
4774 }
4775
4776 if (!intel_dp->is_mst) {
4777 /*
4778 * we'll check the link status via the normal hot plug path later -
4779 * but for short hpds we should check it now
4780 */
5b215bcf 4781 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4782 intel_dp_check_link_status(intel_dp);
5b215bcf 4783 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4784 }
4785 }
b2c5c181
DV		 4786
4787 ret = IRQ_HANDLED;
4788
1c767b33 4789 goto put_power;
0e32b39c
DA		 4790mst_fail:
4791 /* if we were in MST mode, and device is not there get out of MST mode */
4792 if (intel_dp->is_mst) {
4793 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4794 intel_dp->is_mst = false;
4795 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4796 }
1c767b33
ID		 4797put_power:
4798 intel_display_power_put(dev_priv, power_domain);
4799
4800 return ret;
13cf5504
DA		 4801}
4802
e3421a18
ZW		 4803/* Return which DP Port should be selected for Transcoder DP control */
4804int
0206e353 4805intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4806{
4807 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4808 struct intel_encoder *intel_encoder;
4809 struct intel_dp *intel_dp;
e3421a18 4810
fa90ecef
PZ		 4811 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4812 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4813
fa90ecef
PZ		 4814 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4815 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4816 return intel_dp->output_reg;
e3421a18 4817 }
ea5b213a 4818
e3421a18
ZW		 4819 return -1;
4820}
4821
36e83a18 4822/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4823bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4824{
4825 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4826 union child_device_config *p_child;
36e83a18 4827 int i;
5d8a7752
VS		 4828 static const short port_mapping[] = {
4829 [PORT_B] = PORT_IDPB,
4830 [PORT_C] = PORT_IDPC,
4831 [PORT_D] = PORT_IDPD,
4832 };
36e83a18 4833
3b32a35b
VS		 4834 if (port == PORT_A)
4835 return true;
4836
41aa3448 4837 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4838 return false;
4839
41aa3448
RV		 4840 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4841 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4842
5d8a7752 4843 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4844 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4845 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4846 return true;
4847 }
4848 return false;
4849}
4850
0e32b39c 4851void
f684960e
CW		 4852intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4853{
53b41837
YN		 4854 struct intel_connector *intel_connector = to_intel_connector(connector);
4855
3f43c48d 4856 intel_attach_force_audio_property(connector);
e953fd7b 4857 intel_attach_broadcast_rgb_property(connector);
55bc60db 4858 intel_dp->color_range_auto = true;
53b41837
YN		 4859
4860 if (is_edp(intel_dp)) {
4861 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4862 drm_object_attach_property(
4863 &connector->base,
53b41837 4864 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4865 DRM_MODE_SCALE_ASPECT);
4866 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4867 }
f684960e
CW		 4868}
4869
dada1a9f
ID		 4870static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4871{
4872 intel_dp->last_power_cycle = jiffies;
4873 intel_dp->last_power_on = jiffies;
4874 intel_dp->last_backlight_off = jiffies;
4875}
4876
67a54566
DV		 4877static void
4878intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4879 struct intel_dp *intel_dp)
67a54566
DV		 4880{
4881 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4882 struct edp_power_seq cur, vbt, spec,
4883 *final = &intel_dp->pps_delays;
67a54566 4884 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4885 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4886
e39b999a
VS		 4887 lockdep_assert_held(&dev_priv->pps_mutex);
4888
81ddbc69
VS		 4889 /* already initialized? */
4890 if (final->t11_t12 != 0)
4891 return;
4892
453c5420 4893 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4894 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4895 pp_on_reg = PCH_PP_ON_DELAYS;
4896 pp_off_reg = PCH_PP_OFF_DELAYS;
4897 pp_div_reg = PCH_PP_DIVISOR;
4898 } else {
bf13e81b
JN		 4899 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4900
4901 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4902 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4903 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4904 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4905 }
67a54566
DV		 4906
4907 /* Workaround: Need to write PP_CONTROL with the unlock key as
4908 * the very first thing. */
453c5420 4909 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4910 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4911
453c5420
JB		 4912 pp_on = I915_READ(pp_on_reg);
4913 pp_off = I915_READ(pp_off_reg);
4914 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4915
4916 /* Pull timing values out of registers */
4917 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4918 PANEL_POWER_UP_DELAY_SHIFT;
4919
4920 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4921 PANEL_LIGHT_ON_DELAY_SHIFT;
4922
4923 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4924 PANEL_LIGHT_OFF_DELAY_SHIFT;
4925
4926 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4927 PANEL_POWER_DOWN_DELAY_SHIFT;
4928
4929 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4930 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4931
4932 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4933 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4934
41aa3448 4935 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4936
4937 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4938 * our hw here, which are all in 100usec. */
4939 spec.t1_t3 = 210 * 10;
4940 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4941 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4942 spec.t10 = 500 * 10;
4943 /* This one is special and actually in units of 100ms, but zero
4944 * based in the hw (so we need to add 100 ms). But the sw vbt
4945 * table multiplies it with 1000 to make it in units of 100usec,
4946 * too. */
4947 spec.t11_t12 = (510 + 100) * 10;
4948
4949 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4950 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4951
4952 /* Use the max of the register settings and vbt. If both are
4953 * unset, fall back to the spec limits. */
36b5f425 4954#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4955 spec.field : \
4956 max(cur.field, vbt.field))
4957 assign_final(t1_t3);
4958 assign_final(t8);
4959 assign_final(t9);
4960 assign_final(t10);
4961 assign_final(t11_t12);
4962#undef assign_final
4963
36b5f425 4964#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4965 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4966 intel_dp->backlight_on_delay = get_delay(t8);
4967 intel_dp->backlight_off_delay = get_delay(t9);
4968 intel_dp->panel_power_down_delay = get_delay(t10);
4969 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4970#undef get_delay
4971
f30d26e4
JN		 4972 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4973 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4974 intel_dp->panel_power_cycle_delay);
4975
4976 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4977 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4978}
4979
4980static void
4981intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4982 struct intel_dp *intel_dp)
f30d26e4
JN		 4983{
4984 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4985 u32 pp_on, pp_off, pp_div, port_sel = 0;
4986 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4987 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4988 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4989 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4990
e39b999a 4991 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4992
4993 if (HAS_PCH_SPLIT(dev)) {
4994 pp_on_reg = PCH_PP_ON_DELAYS;
4995 pp_off_reg = PCH_PP_OFF_DELAYS;
4996 pp_div_reg = PCH_PP_DIVISOR;
4997 } else {
bf13e81b
JN		 4998 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4999
5000 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5001 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5002 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5003 }
5004
b2f19d1a
PZ		 5005 /*
5006 * And finally store the new values in the power sequencer. The
5007 * backlight delays are set to 1 because we do manual waits on them. For
5008 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5009 * we'll end up waiting for the backlight off delay twice: once when we
5010 * do the manual sleep, and once when we disable the panel and wait for
5011 * the PP_STATUS bit to become zero.
5012 */
f30d26e4 5013 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5014 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5015 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5016 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5017 /* Compute the divisor for the pp clock, simply match the Bspec
5018 * formula. */
453c5420 5019 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 5020 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 5021 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5022
5023 /* Haswell doesn't have any port selection bits for the panel
5024 * power sequencer any more. */
bc7d38a4 5025 if (IS_VALLEYVIEW(dev)) {
ad933b56 5026 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5027 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5028 if (port == PORT_A)
a24c144c 5029 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5030 else
a24c144c 5031 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5032 }
5033
453c5420
JB		 5034 pp_on |= port_sel;
5035
5036 I915_WRITE(pp_on_reg, pp_on);
5037 I915_WRITE(pp_off_reg, pp_off);
5038 I915_WRITE(pp_div_reg, pp_div);
67a54566 5039
67a54566 5040 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5041 I915_READ(pp_on_reg),
5042 I915_READ(pp_off_reg),
5043 I915_READ(pp_div_reg));
f684960e
CW		 5044}
5045
b33a2815
VK		 5046/**
5047 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5048 * @dev: DRM device
5049 * @refresh_rate: RR to be programmed
5050 *
5051 * This function gets called when refresh rate (RR) has to be changed from
5052 * one frequency to another. Switches can be between high and low RR
5053 * supported by the panel or to any other RR based on media playback (in
5054 * this case, RR value needs to be passed from user space).
5055 *
5056 * The caller of this function needs to take a lock on dev_priv->drrs.
5057 */
96178eeb 5058static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5059{
5060 struct drm_i915_private *dev_priv = dev->dev_private;
5061 struct intel_encoder *encoder;
96178eeb
VK		 5062 struct intel_digital_port *dig_port = NULL;
5063 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5064 struct intel_crtc_state *config = NULL;
439d7ac0 5065 struct intel_crtc *intel_crtc = NULL;
439d7ac0 5066 u32 reg, val;
96178eeb 5067 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5068
5069 if (refresh_rate <= 0) {
5070 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5071 return;
5072 }
5073
96178eeb
VK		 5074 if (intel_dp == NULL) {
5075 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5076 return;
5077 }
5078
1fcc9d1c 5079 /*
e4d59f6b
RV		 5080 * FIXME: This needs proper synchronization with psr state for some
5081 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5082 */
439d7ac0 5083
96178eeb
VK		 5084 dig_port = dp_to_dig_port(intel_dp);
5085 encoder = &dig_port->base;
723f9aab 5086 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5087
5088 if (!intel_crtc) {
5089 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5090 return;
5091 }
5092
6e3c9717 5093 config = intel_crtc->config;
439d7ac0 5094
96178eeb 5095 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5096 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5097 return;
5098 }
5099
96178eeb
VK		 5100 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5101 refresh_rate)
439d7ac0
PB		 5102 index = DRRS_LOW_RR;
5103
96178eeb 5104 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5105 DRM_DEBUG_KMS(
5106 "DRRS requested for previously set RR...ignoring\n");
5107 return;
5108 }
5109
5110 if (!intel_crtc->active) {
5111 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5112 return;
5113 }
5114
44395bfe 5115 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5116 switch (index) {
5117 case DRRS_HIGH_RR:
5118 intel_dp_set_m_n(intel_crtc, M1_N1);
5119 break;
5120 case DRRS_LOW_RR:
5121 intel_dp_set_m_n(intel_crtc, M2_N2);
5122 break;
5123 case DRRS_MAX_RR:
5124 default:
5125 DRM_ERROR("Unsupported refreshrate type\n");
5126 }
5127 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 5128 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 5129 val = I915_READ(reg);
a4c30b1d 5130
439d7ac0 5131 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5132 if (IS_VALLEYVIEW(dev))
5133 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5134 else
5135 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5136 } else {
6fa7aec1
VK		 5137 if (IS_VALLEYVIEW(dev))
5138 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5139 else
5140 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5141 }
5142 I915_WRITE(reg, val);
5143 }
5144
4e9ac947
VK		 5145 dev_priv->drrs.refresh_rate_type = index;
5146
5147 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5148}
5149
b33a2815
VK		 5150/**
5151 * intel_edp_drrs_enable - init drrs struct if supported
5152 * @intel_dp: DP struct
5153 *
5154 * Initializes frontbuffer_bits and drrs.dp
5155 */
c395578e
VK		 5156void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5157{
5158 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5159 struct drm_i915_private *dev_priv = dev->dev_private;
5160 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5161 struct drm_crtc *crtc = dig_port->base.base.crtc;
5162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5163
5164 if (!intel_crtc->config->has_drrs) {
5165 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5166 return;
5167 }
5168
5169 mutex_lock(&dev_priv->drrs.mutex);
5170 if (WARN_ON(dev_priv->drrs.dp)) {
5171 DRM_ERROR("DRRS already enabled\n");
5172 goto unlock;
5173 }
5174
5175 dev_priv->drrs.busy_frontbuffer_bits = 0;
5176
5177 dev_priv->drrs.dp = intel_dp;
5178
5179unlock:
5180 mutex_unlock(&dev_priv->drrs.mutex);
5181}
5182
b33a2815
VK		 5183/**
5184 * intel_edp_drrs_disable - Disable DRRS
5185 * @intel_dp: DP struct
5186 *
5187 */
c395578e
VK		 5188void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5189{
5190 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5191 struct drm_i915_private *dev_priv = dev->dev_private;
5192 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5193 struct drm_crtc *crtc = dig_port->base.base.crtc;
5194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5195
5196 if (!intel_crtc->config->has_drrs)
5197 return;
5198
5199 mutex_lock(&dev_priv->drrs.mutex);
5200 if (!dev_priv->drrs.dp) {
5201 mutex_unlock(&dev_priv->drrs.mutex);
5202 return;
5203 }
5204
5205 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5206 intel_dp_set_drrs_state(dev_priv->dev,
5207 intel_dp->attached_connector->panel.
5208 fixed_mode->vrefresh);
5209
5210 dev_priv->drrs.dp = NULL;
5211 mutex_unlock(&dev_priv->drrs.mutex);
5212
5213 cancel_delayed_work_sync(&dev_priv->drrs.work);
5214}
5215
4e9ac947
VK		 5216static void intel_edp_drrs_downclock_work(struct work_struct *work)
5217{
5218 struct drm_i915_private *dev_priv =
5219 container_of(work, typeof(*dev_priv), drrs.work.work);
5220 struct intel_dp *intel_dp;
5221
5222 mutex_lock(&dev_priv->drrs.mutex);
5223
5224 intel_dp = dev_priv->drrs.dp;
5225
5226 if (!intel_dp)
5227 goto unlock;
5228
439d7ac0 5229 /*
4e9ac947
VK		 5230 * The delayed work can race with an invalidate hence we need to
5231 * recheck.
439d7ac0
PB		 5232 */
5233
4e9ac947
VK		 5234 if (dev_priv->drrs.busy_frontbuffer_bits)
5235 goto unlock;
439d7ac0 5236
4e9ac947
VK		 5237 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5238 intel_dp_set_drrs_state(dev_priv->dev,
5239 intel_dp->attached_connector->panel.
5240 downclock_mode->vrefresh);
439d7ac0 5241
4e9ac947 5242unlock:
439d7ac0 5243
4e9ac947 5244 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5245}
5246
b33a2815
VK		 5247/**
5248 * intel_edp_drrs_invalidate - Invalidate DRRS
5249 * @dev: DRM device
5250 * @frontbuffer_bits: frontbuffer plane tracking bits
5251 *
5252 * When there is a disturbance on screen (due to cursor movement/time
5253 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5254 * high RR.
5255 *
5256 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5257 */
a93fad0f
VK		 5258void intel_edp_drrs_invalidate(struct drm_device *dev,
5259 unsigned frontbuffer_bits)
5260{
5261 struct drm_i915_private *dev_priv = dev->dev_private;
5262 struct drm_crtc *crtc;
5263 enum pipe pipe;
5264
5265 if (!dev_priv->drrs.dp)
5266 return;
5267
3954e733
R		 5268 cancel_delayed_work_sync(&dev_priv->drrs.work);
5269
a93fad0f
VK		 5270 mutex_lock(&dev_priv->drrs.mutex);
5271 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5272 pipe = to_intel_crtc(crtc)->pipe;
5273
5274 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
a93fad0f
VK		 5275 intel_dp_set_drrs_state(dev_priv->dev,
5276 dev_priv->drrs.dp->attached_connector->panel.
5277 fixed_mode->vrefresh);
5278 }
5279
5280 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5281
5282 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5283 mutex_unlock(&dev_priv->drrs.mutex);
5284}
5285
b33a2815
VK		 5286/**
5287 * intel_edp_drrs_flush - Flush DRRS
5288 * @dev: DRM device
5289 * @frontbuffer_bits: frontbuffer plane tracking bits
5290 *
5291 * When there is no movement on screen, DRRS work can be scheduled.
5292 * This DRRS work is responsible for setting relevant registers after a
5293 * timeout of 1 second.
5294 *
5295 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5296 */
a93fad0f
VK		 5297void intel_edp_drrs_flush(struct drm_device *dev,
5298 unsigned frontbuffer_bits)
5299{
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301 struct drm_crtc *crtc;
5302 enum pipe pipe;
5303
5304 if (!dev_priv->drrs.dp)
5305 return;
5306
3954e733
R		 5307 cancel_delayed_work_sync(&dev_priv->drrs.work);
5308
a93fad0f
VK		 5309 mutex_lock(&dev_priv->drrs.mutex);
5310 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5311 pipe = to_intel_crtc(crtc)->pipe;
5312 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5313
a93fad0f
VK		 5314 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5315 !dev_priv->drrs.busy_frontbuffer_bits)
5316 schedule_delayed_work(&dev_priv->drrs.work,
5317 msecs_to_jiffies(1000));
5318 mutex_unlock(&dev_priv->drrs.mutex);
5319}
5320
b33a2815
VK		 5321/**
5322 * DOC: Display Refresh Rate Switching (DRRS)
5323 *
5324 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5325 * which enables swtching between low and high refresh rates,
5326 * dynamically, based on the usage scenario. This feature is applicable
5327 * for internal panels.
5328 *
5329 * Indication that the panel supports DRRS is given by the panel EDID, which
5330 * would list multiple refresh rates for one resolution.
5331 *
5332 * DRRS is of 2 types - static and seamless.
5333 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5334 * (may appear as a blink on screen) and is used in dock-undock scenario.
5335 * Seamless DRRS involves changing RR without any visual effect to the user
5336 * and can be used during normal system usage. This is done by programming
5337 * certain registers.
5338 *
5339 * Support for static/seamless DRRS may be indicated in the VBT based on
5340 * inputs from the panel spec.
5341 *
5342 * DRRS saves power by switching to low RR based on usage scenarios.
5343 *
5344 * eDP DRRS:-
5345 * The implementation is based on frontbuffer tracking implementation.
5346 * When there is a disturbance on the screen triggered by user activity or a
5347 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5348 * When there is no movement on screen, after a timeout of 1 second, a switch
5349 * to low RR is made.
5350 * For integration with frontbuffer tracking code,
5351 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5352 *
5353 * DRRS can be further extended to support other internal panels and also
5354 * the scenario of video playback wherein RR is set based on the rate
5355 * requested by userspace.
5356 */
5357
5358/**
5359 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5360 * @intel_connector: eDP connector
5361 * @fixed_mode: preferred mode of panel
5362 *
5363 * This function is called only once at driver load to initialize basic
5364 * DRRS stuff.
5365 *
5366 * Returns:
5367 * Downclock mode if panel supports it, else return NULL.
5368 * DRRS support is determined by the presence of downclock mode (apart
5369 * from VBT setting).
5370 */
4f9db5b5 5371static struct drm_display_mode *
96178eeb
VK		 5372intel_dp_drrs_init(struct intel_connector *intel_connector,
5373 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5374{
5375 struct drm_connector *connector = &intel_connector->base;
96178eeb 5376 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378 struct drm_display_mode *downclock_mode = NULL;
5379
5380 if (INTEL_INFO(dev)->gen <= 6) {
5381 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5382 return NULL;
5383 }
5384
5385 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5386 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5387 return NULL;
5388 }
5389
5390 downclock_mode = intel_find_panel_downclock
5391 (dev, fixed_mode, connector);
5392
5393 if (!downclock_mode) {
a1d26342 5394 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5395 return NULL;
5396 }
5397
4e9ac947
VK		 5398 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5399
96178eeb 5400 mutex_init(&dev_priv->drrs.mutex);
439d7ac0 5401
96178eeb 5402 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5403
96178eeb 5404 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5405 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5406 return downclock_mode;
5407}
5408
ed92f0b2 5409static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5410 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5411{
5412 struct drm_connector *connector = &intel_connector->base;
5413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5414 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5415 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5416 struct drm_i915_private *dev_priv = dev->dev_private;
5417 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5418 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5419 bool has_dpcd;
5420 struct drm_display_mode *scan;
5421 struct edid *edid;
6517d273 5422 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5423
5424 if (!is_edp(intel_dp))
5425 return true;
5426
49e6bc51
VS		 5427 pps_lock(intel_dp);
5428 intel_edp_panel_vdd_sanitize(intel_dp);
5429 pps_unlock(intel_dp);
63635217 5430
ed92f0b2 5431 /* Cache DPCD and EDID for edp. */
ed92f0b2 5432 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5433
5434 if (has_dpcd) {
5435 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5436 dev_priv->no_aux_handshake =
5437 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5438 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5439 } else {
5440 /* if this fails, presume the device is a ghost */
5441 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5442 return false;
5443 }
5444
5445 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5446 pps_lock(intel_dp);
36b5f425 5447 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5448 pps_unlock(intel_dp);
ed92f0b2 5449
060c8778 5450 mutex_lock(&dev->mode_config.mutex);
0b99836f 5451 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5452 if (edid) {
5453 if (drm_add_edid_modes(connector, edid)) {
5454 drm_mode_connector_update_edid_property(connector,
5455 edid);
5456 drm_edid_to_eld(connector, edid);
5457 } else {
5458 kfree(edid);
5459 edid = ERR_PTR(-EINVAL);
5460 }
5461 } else {
5462 edid = ERR_PTR(-ENOENT);
5463 }
5464 intel_connector->edid = edid;
5465
5466 /* prefer fixed mode from EDID if available */
5467 list_for_each_entry(scan, &connector->probed_modes, head) {
5468 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5469 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5470 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5471 intel_connector, fixed_mode);
ed92f0b2
PZ		 5472 break;
5473 }
5474 }
5475
5476 /* fallback to VBT if available for eDP */
5477 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5478 fixed_mode = drm_mode_duplicate(dev,
5479 dev_priv->vbt.lfp_lvds_vbt_mode);
5480 if (fixed_mode)
5481 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5482 }
060c8778 5483 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5484
01527b31
CT		 5485 if (IS_VALLEYVIEW(dev)) {
5486 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5487 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5488
5489 /*
5490 * Figure out the current pipe for the initial backlight setup.
5491 * If the current pipe isn't valid, try the PPS pipe, and if that
5492 * fails just assume pipe A.
5493 */
5494 if (IS_CHERRYVIEW(dev))
5495 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5496 else
5497 pipe = PORT_TO_PIPE(intel_dp->DP);
5498
5499 if (pipe != PIPE_A && pipe != PIPE_B)
5500 pipe = intel_dp->pps_pipe;
5501
5502 if (pipe != PIPE_A && pipe != PIPE_B)
5503 pipe = PIPE_A;
5504
5505 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5506 pipe_name(pipe));
01527b31
CT		 5507 }
5508
4f9db5b5 5509 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5510 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5511 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5512
5513 return true;
5514}
5515
16c25533 5516bool
f0fec3f2
PZ		 5517intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5518 struct intel_connector *intel_connector)
a4fc5ed6 5519{
f0fec3f2
PZ		 5520 struct drm_connector *connector = &intel_connector->base;
5521 struct intel_dp *intel_dp = &intel_dig_port->dp;
5522 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5523 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5524 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5525 enum port port = intel_dig_port->port;
0b99836f 5526 int type;
a4fc5ed6 5527
a4a5d2f8
VS		 5528 intel_dp->pps_pipe = INVALID_PIPE;
5529
ec5b01dd 5530 /* intel_dp vfuncs */
b6b5e383
DL		 5531 if (INTEL_INFO(dev)->gen >= 9)
5532 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5533 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5534 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5535 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5536 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5537 else if (HAS_PCH_SPLIT(dev))
5538 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5539 else
5540 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5541
b9ca5fad
DL		 5542 if (INTEL_INFO(dev)->gen >= 9)
5543 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5544 else
5545 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5546
0767935e
DV		 5547 /* Preserve the current hw state. */
5548 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5549 intel_dp->attached_connector = intel_connector;
3d3dc149 5550
3b32a35b 5551 if (intel_dp_is_edp(dev, port))
b329530c 5552 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5553 else
5554 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5555
f7d24902
ID		 5556 /*
5557 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5558 * for DP the encoder type can be set by the caller to
5559 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5560 */
5561 if (type == DRM_MODE_CONNECTOR_eDP)
5562 intel_encoder->type = INTEL_OUTPUT_EDP;
5563
c17ed5b5
VS		 5564 /* eDP only on port B and/or C on vlv/chv */
5565 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5566 port != PORT_B && port != PORT_C))
5567 return false;
5568
e7281eab
ID		 5569 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5570 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5571 port_name(port));
5572
b329530c 5573 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5574 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5575
a4fc5ed6
KP		 5576 connector->interlace_allowed = true;
5577 connector->doublescan_allowed = 0;
5578
f0fec3f2 5579 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5580 edp_panel_vdd_work);
a4fc5ed6 5581
df0e9248 5582 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5583 drm_connector_register(connector);
a4fc5ed6 5584
affa9354 5585 if (HAS_DDI(dev))
bcbc889b
PZ		 5586 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5587 else
5588 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5589 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5590
0b99836f 5591 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5592 switch (port) {
5593 case PORT_A:
1d843f9d 5594 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5595 break;
5596 case PORT_B:
1d843f9d 5597 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5598 break;
5599 case PORT_C:
1d843f9d 5600 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5601 break;
5602 case PORT_D:
1d843f9d 5603 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5604 break;
5605 default:
ad1c0b19 5606 BUG();
5eb08b69
ZW		 5607 }
5608
dada1a9f 5609 if (is_edp(intel_dp)) {
773538e8 5610 pps_lock(intel_dp);
1e74a324
VS		 5611 intel_dp_init_panel_power_timestamps(intel_dp);
5612 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5613 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5614 else
36b5f425 5615 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5616 pps_unlock(intel_dp);
dada1a9f 5617 }
0095e6dc 5618
9d1a1031 5619 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5620
0e32b39c 5621 /* init MST on ports that can support it */
c86ea3d0 5622 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
0e32b39c 5623 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5624 intel_dp_mst_encoder_init(intel_dig_port,
5625 intel_connector->base.base.id);
0e32b39c
DA		 5626 }
5627 }
5628
36b5f425 5629 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5630 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5631 if (is_edp(intel_dp)) {
5632 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5633 /*
5634 * vdd might still be enabled do to the delayed vdd off.
5635 * Make sure vdd is actually turned off here.
5636 */
773538e8 5637 pps_lock(intel_dp);
4be73780 5638 edp_panel_vdd_off_sync(intel_dp);
773538e8 5639 pps_unlock(intel_dp);
15b1d171 5640 }
34ea3d38 5641 drm_connector_unregister(connector);
b2f246a8 5642 drm_connector_cleanup(connector);
16c25533 5643 return false;
b2f246a8 5644 }
32f9d658 5645
f684960e
CW		 5646 intel_dp_add_properties(intel_dp, connector);
5647
a4fc5ed6
KP		 5648 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5649 * 0xd. Failure to do so will result in spurious interrupts being
5650 * generated on the port when a cable is not attached.
5651 */
5652 if (IS_G4X(dev) && !IS_GM45(dev)) {
5653 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5654 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5655 }
16c25533 5656
aa7471d2
JN		 5657 i915_debugfs_connector_add(connector);
5658
16c25533 5659 return true;
a4fc5ed6 5660}
f0fec3f2
PZ		 5661
5662void
5663intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5664{
13cf5504 5665 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5666 struct intel_digital_port *intel_dig_port;
5667 struct intel_encoder *intel_encoder;
5668 struct drm_encoder *encoder;
5669 struct intel_connector *intel_connector;
5670
b14c5679 5671 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5672 if (!intel_dig_port)
5673 return;
5674
9bdbd0b9 5675 intel_connector = intel_connector_alloc();
f0fec3f2
PZ		 5676 if (!intel_connector) {
5677 kfree(intel_dig_port);
5678 return;
5679 }
5680
5681 intel_encoder = &intel_dig_port->base;
5682 encoder = &intel_encoder->base;
5683
5684 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5685 DRM_MODE_ENCODER_TMDS);
5686
5bfe2ac0 5687 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5688 intel_encoder->disable = intel_disable_dp;
00c09d70 5689 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5690 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5691 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5692 if (IS_CHERRYVIEW(dev)) {
9197c88b 5693 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5694 intel_encoder->pre_enable = chv_pre_enable_dp;
5695 intel_encoder->enable = vlv_enable_dp;
580d3811 5696 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5697 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5698 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5699 intel_encoder->pre_enable = vlv_pre_enable_dp;
5700 intel_encoder->enable = vlv_enable_dp;
49277c31 5701 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5702 } else {
ecff4f3b
JN		 5703 intel_encoder->pre_enable = g4x_pre_enable_dp;
5704 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5705 if (INTEL_INFO(dev)->gen >= 5)
5706 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5707 }
f0fec3f2 5708
174edf1f 5709 intel_dig_port->port = port;
f0fec3f2
PZ		 5710 intel_dig_port->dp.output_reg = output_reg;
5711
00c09d70 5712 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5713 if (IS_CHERRYVIEW(dev)) {
5714 if (port == PORT_D)
5715 intel_encoder->crtc_mask = 1 << 2;
5716 else
5717 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5718 } else {
5719 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5720 }
bc079e8b 5721 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5722 intel_encoder->hot_plug = intel_dp_hot_plug;
5723
13cf5504
DA		 5724 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5725 dev_priv->hpd_irq_port[port] = intel_dig_port;
5726
15b1d171
PZ		 5727 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5728 drm_encoder_cleanup(encoder);
5729 kfree(intel_dig_port);
b2f246a8 5730 kfree(intel_connector);
15b1d171 5731 }
f0fec3f2 5732}
0e32b39c
DA		 5733
5734void intel_dp_mst_suspend(struct drm_device *dev)
5735{
5736 struct drm_i915_private *dev_priv = dev->dev_private;
5737 int i;
5738
5739 /* disable MST */
5740 for (i = 0; i < I915_MAX_PORTS; i++) {
5741 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5742 if (!intel_dig_port)
5743 continue;
5744
5745 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5746 if (!intel_dig_port->dp.can_mst)
5747 continue;
5748 if (intel_dig_port->dp.is_mst)
5749 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5750 }
5751 }
5752}
5753
5754void intel_dp_mst_resume(struct drm_device *dev)
5755{
5756 struct drm_i915_private *dev_priv = dev->dev_private;
5757 int i;
5758
5759 for (i = 0; i < I915_MAX_PORTS; i++) {
5760 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5761 if (!intel_dig_port)
5762 continue;
5763 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5764 int ret;
5765
5766 if (!intel_dig_port->dp.can_mst)
5767 continue;
5768
5769 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5770 if (ret != 0) {
5771 intel_dp_check_mst_status(&intel_dig_port->dp);
5772 }
5773 }
5774 }
5775}
Linux kernel - Deliverables
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