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drm/i915: Add missing ')' to SKL_PS_ECC_STAT define
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
a4fc5ed6 132
e0fce78f
VS		 133static unsigned int intel_dp_unused_lane_mask(int lane_count)
134{
135 return ~((1 << lane_count) - 1) & 0xf;
136}
137
ed4e9c1d
VS		 138static int
139intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 140{
7183dc29 141 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 142
143 switch (max_link_bw) {
144 case DP_LINK_BW_1_62:
145 case DP_LINK_BW_2_7:
1db10e28 146 case DP_LINK_BW_5_4:
d4eead50 147 break;
a4fc5ed6 148 default:
d4eead50
ID		 149 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
150 max_link_bw);
a4fc5ed6
KP		 151 max_link_bw = DP_LINK_BW_1_62;
152 break;
153 }
154 return max_link_bw;
155}
156
eeb6324d
PZ		 157static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
158{
159 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
160 struct drm_device *dev = intel_dig_port->base.base.dev;
161 u8 source_max, sink_max;
162
163 source_max = 4;
164 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
165 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
166 source_max = 2;
167
168 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
169
170 return min(source_max, sink_max);
171}
172
cd9dde44
AJ		 173/*
174 * The units on the numbers in the next two are... bizarre. Examples will
175 * make it clearer; this one parallels an example in the eDP spec.
176 *
177 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
178 *
179 * 270000 * 1 * 8 / 10 == 216000
180 *
181 * The actual data capacity of that configuration is 2.16Gbit/s, so the
182 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
183 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
184 * 119000. At 18bpp that's 2142000 kilobits per second.
185 *
186 * Thus the strange-looking division by 10 in intel_dp_link_required, to
187 * get the result in decakilobits instead of kilobits.
188 */
189
a4fc5ed6 190static int
c898261c 191intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 192{
cd9dde44 193 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 194}
195
fe27d53e
DA		 196static int
197intel_dp_max_data_rate(int max_link_clock, int max_lanes)
198{
199 return (max_link_clock * max_lanes * 8) / 10;
200}
201
c19de8eb 202static enum drm_mode_status
a4fc5ed6
KP		 203intel_dp_mode_valid(struct drm_connector *connector,
204 struct drm_display_mode *mode)
205{
df0e9248 206 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 207 struct intel_connector *intel_connector = to_intel_connector(connector);
208 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 209 int target_clock = mode->clock;
210 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 211
dd06f90e
JN		 212 if (is_edp(intel_dp) && fixed_mode) {
213 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 214 return MODE_PANEL;
215
dd06f90e 216 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 217 return MODE_PANEL;
03afc4a2
DV		 218
219 target_clock = fixed_mode->clock;
7de56f43
ZY		 220 }
221
50fec21a 222 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 223 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 224
225 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
226 mode_rate = intel_dp_link_required(target_clock, 18);
227
228 if (mode_rate > max_rate)
c4867936 229 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 230
231 if (mode->clock < 10000)
232 return MODE_CLOCK_LOW;
233
0af78a2b
DV		 234 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
235 return MODE_H_ILLEGAL;
236
a4fc5ed6
KP		 237 return MODE_OK;
238}
239
a4f1289e 240uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 241{
242 int i;
243 uint32_t v = 0;
244
245 if (src_bytes > 4)
246 src_bytes = 4;
247 for (i = 0; i < src_bytes; i++)
248 v |= ((uint32_t) src[i]) << ((3-i) * 8);
249 return v;
250}
251
c2af70e2 252static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 253{
254 int i;
255 if (dst_bytes > 4)
256 dst_bytes = 4;
257 for (i = 0; i < dst_bytes; i++)
258 dst[i] = src >> ((3-i) * 8);
259}
260
bf13e81b
JN		 261static void
262intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 263 struct intel_dp *intel_dp);
bf13e81b
JN		 264static void
265intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 266 struct intel_dp *intel_dp);
bf13e81b 267
773538e8
VS		 268static void pps_lock(struct intel_dp *intel_dp)
269{
270 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
271 struct intel_encoder *encoder = &intel_dig_port->base;
272 struct drm_device *dev = encoder->base.dev;
273 struct drm_i915_private *dev_priv = dev->dev_private;
274 enum intel_display_power_domain power_domain;
275
276 /*
277 * See vlv_power_sequencer_reset() why we need
278 * a power domain reference here.
279 */
25f78f58 280 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 281 intel_display_power_get(dev_priv, power_domain);
282
283 mutex_lock(&dev_priv->pps_mutex);
284}
285
286static void pps_unlock(struct intel_dp *intel_dp)
287{
288 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
289 struct intel_encoder *encoder = &intel_dig_port->base;
290 struct drm_device *dev = encoder->base.dev;
291 struct drm_i915_private *dev_priv = dev->dev_private;
292 enum intel_display_power_domain power_domain;
293
294 mutex_unlock(&dev_priv->pps_mutex);
295
25f78f58 296 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 297 intel_display_power_put(dev_priv, power_domain);
298}
299
961a0db0
VS		 300static void
301vlv_power_sequencer_kick(struct intel_dp *intel_dp)
302{
303 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
304 struct drm_device *dev = intel_dig_port->base.base.dev;
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 307 bool pll_enabled, release_cl_override = false;
308 enum dpio_phy phy = DPIO_PHY(pipe);
309 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 310 uint32_t DP;
311
312 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
313 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
314 pipe_name(pipe), port_name(intel_dig_port->port)))
315 return;
316
317 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
318 pipe_name(pipe), port_name(intel_dig_port->port));
319
320 /* Preserve the BIOS-computed detected bit. This is
321 * supposed to be read-only.
322 */
323 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
324 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
325 DP |= DP_PORT_WIDTH(1);
326 DP |= DP_LINK_TRAIN_PAT_1;
327
328 if (IS_CHERRYVIEW(dev))
329 DP |= DP_PIPE_SELECT_CHV(pipe);
330 else if (pipe == PIPE_B)
331 DP |= DP_PIPEB_SELECT;
332
d288f65f
VS		 333 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
334
335 /*
336 * The DPLL for the pipe must be enabled for this to work.
337 * So enable temporarily it if it's not already enabled.
338 */
0047eedc
VS		 339 if (!pll_enabled) {
340 release_cl_override = IS_CHERRYVIEW(dev) &&
341 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
342
d288f65f
VS		 343 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
344 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
0047eedc 345 }
d288f65f 346
961a0db0
VS		 347 /*
348 * Similar magic as in intel_dp_enable_port().
349 * We _must_ do this port enable + disable trick
350 * to make this power seqeuencer lock onto the port.
351 * Otherwise even VDD force bit won't work.
352 */
353 I915_WRITE(intel_dp->output_reg, DP);
354 POSTING_READ(intel_dp->output_reg);
355
356 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
357 POSTING_READ(intel_dp->output_reg);
358
359 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
360 POSTING_READ(intel_dp->output_reg);
d288f65f 361
0047eedc 362 if (!pll_enabled) {
d288f65f 363 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 364
365 if (release_cl_override)
366 chv_phy_powergate_ch(dev_priv, phy, ch, false);
367 }
961a0db0
VS		 368}
369
bf13e81b
JN		 370static enum pipe
371vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
372{
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 376 struct intel_encoder *encoder;
377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 378 enum pipe pipe;
bf13e81b 379
e39b999a 380 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 381
a8c3344e
VS		 382 /* We should never land here with regular DP ports */
383 WARN_ON(!is_edp(intel_dp));
384
a4a5d2f8
VS		 385 if (intel_dp->pps_pipe != INVALID_PIPE)
386 return intel_dp->pps_pipe;
387
388 /*
389 * We don't have power sequencer currently.
390 * Pick one that's not used by other ports.
391 */
392 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
393 base.head) {
394 struct intel_dp *tmp;
395
396 if (encoder->type != INTEL_OUTPUT_EDP)
397 continue;
398
399 tmp = enc_to_intel_dp(&encoder->base);
400
401 if (tmp->pps_pipe != INVALID_PIPE)
402 pipes &= ~(1 << tmp->pps_pipe);
403 }
404
405 /*
406 * Didn't find one. This should not happen since there
407 * are two power sequencers and up to two eDP ports.
408 */
409 if (WARN_ON(pipes == 0))
a8c3344e
VS		 410 pipe = PIPE_A;
411 else
412 pipe = ffs(pipes) - 1;
a4a5d2f8 413
a8c3344e
VS		 414 vlv_steal_power_sequencer(dev, pipe);
415 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 416
417 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
418 pipe_name(intel_dp->pps_pipe),
419 port_name(intel_dig_port->port));
420
421 /* init power sequencer on this pipe and port */
36b5f425
VS		 422 intel_dp_init_panel_power_sequencer(dev, intel_dp);
423 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 424
961a0db0
VS		 425 /*
426 * Even vdd force doesn't work until we've made
427 * the power sequencer lock in on the port.
428 */
429 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 430
431 return intel_dp->pps_pipe;
432}
433
6491ab27
VS		 434typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
435 enum pipe pipe);
436
437static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
438 enum pipe pipe)
439{
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
441}
442
443static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
444 enum pipe pipe)
445{
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
447}
448
449static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
450 enum pipe pipe)
451{
452 return true;
453}
bf13e81b 454
a4a5d2f8 455static enum pipe
6491ab27
VS		 456vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
457 enum port port,
458 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 459{
460 enum pipe pipe;
bf13e81b 461
bf13e81b
JN		 462 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
463 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
464 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 465
466 if (port_sel != PANEL_PORT_SELECT_VLV(port))
467 continue;
468
6491ab27
VS		 469 if (!pipe_check(dev_priv, pipe))
470 continue;
471
a4a5d2f8 472 return pipe;
bf13e81b
JN		 473 }
474
a4a5d2f8
VS		 475 return INVALID_PIPE;
476}
477
478static void
479vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
480{
481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
482 struct drm_device *dev = intel_dig_port->base.base.dev;
483 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 484 enum port port = intel_dig_port->port;
485
486 lockdep_assert_held(&dev_priv->pps_mutex);
487
488 /* try to find a pipe with this port selected */
6491ab27
VS		 489 /* first pick one where the panel is on */
490 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
491 vlv_pipe_has_pp_on);
492 /* didn't find one? pick one where vdd is on */
493 if (intel_dp->pps_pipe == INVALID_PIPE)
494 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
495 vlv_pipe_has_vdd_on);
496 /* didn't find one? pick one with just the correct port */
497 if (intel_dp->pps_pipe == INVALID_PIPE)
498 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
499 vlv_pipe_any);
a4a5d2f8
VS		 500
501 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
502 if (intel_dp->pps_pipe == INVALID_PIPE) {
503 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
504 port_name(port));
505 return;
bf13e81b
JN		 506 }
507
a4a5d2f8
VS		 508 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
509 port_name(port), pipe_name(intel_dp->pps_pipe));
510
36b5f425
VS		 511 intel_dp_init_panel_power_sequencer(dev, intel_dp);
512 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 513}
514
773538e8
VS		 515void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
516{
517 struct drm_device *dev = dev_priv->dev;
518 struct intel_encoder *encoder;
519
520 if (WARN_ON(!IS_VALLEYVIEW(dev)))
521 return;
522
523 /*
524 * We can't grab pps_mutex here due to deadlock with power_domain
525 * mutex when power_domain functions are called while holding pps_mutex.
526 * That also means that in order to use pps_pipe the code needs to
527 * hold both a power domain reference and pps_mutex, and the power domain
528 * reference get/put must be done while _not_ holding pps_mutex.
529 * pps_{lock,unlock}() do these steps in the correct order, so one
530 * should use them always.
531 */
532
533 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
534 struct intel_dp *intel_dp;
535
536 if (encoder->type != INTEL_OUTPUT_EDP)
537 continue;
538
539 intel_dp = enc_to_intel_dp(&encoder->base);
540 intel_dp->pps_pipe = INVALID_PIPE;
541 }
bf13e81b
JN		 542}
543
544static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
545{
546 struct drm_device *dev = intel_dp_to_dev(intel_dp);
547
b0a08bec
VK		 548 if (IS_BROXTON(dev))
549 return BXT_PP_CONTROL(0);
550 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 551 return PCH_PP_CONTROL;
552 else
553 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
554}
555
556static u32 _pp_stat_reg(struct intel_dp *intel_dp)
557{
558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
559
b0a08bec
VK		 560 if (IS_BROXTON(dev))
561 return BXT_PP_STATUS(0);
562 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 563 return PCH_PP_STATUS;
564 else
565 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
566}
567
01527b31
CT		 568/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
569 This function only applicable when panel PM state is not to be tracked */
570static int edp_notify_handler(struct notifier_block *this, unsigned long code,
571 void *unused)
572{
573 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
574 edp_notifier);
575 struct drm_device *dev = intel_dp_to_dev(intel_dp);
576 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 577
578 if (!is_edp(intel_dp) || code != SYS_RESTART)
579 return 0;
580
773538e8 581 pps_lock(intel_dp);
e39b999a 582
01527b31 583 if (IS_VALLEYVIEW(dev)) {
e39b999a 584 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
649636ef
VS		 585 u32 pp_ctrl_reg, pp_div_reg;
586 u32 pp_div;
e39b999a 587
01527b31
CT		 588 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
589 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
590 pp_div = I915_READ(pp_div_reg);
591 pp_div &= PP_REFERENCE_DIVIDER_MASK;
592
593 /* 0x1F write to PP_DIV_REG sets max cycle delay */
594 I915_WRITE(pp_div_reg, pp_div | 0x1F);
595 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
596 msleep(intel_dp->panel_power_cycle_delay);
597 }
598
773538e8 599 pps_unlock(intel_dp);
e39b999a 600
01527b31
CT		 601 return 0;
602}
603
4be73780 604static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 605{
30add22d 606 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 607 struct drm_i915_private *dev_priv = dev->dev_private;
608
e39b999a
VS		 609 lockdep_assert_held(&dev_priv->pps_mutex);
610
9a42356b
VS		 611 if (IS_VALLEYVIEW(dev) &&
612 intel_dp->pps_pipe == INVALID_PIPE)
613 return false;
614
bf13e81b 615 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 616}
617
4be73780 618static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 619{
30add22d 620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 621 struct drm_i915_private *dev_priv = dev->dev_private;
622
e39b999a
VS		 623 lockdep_assert_held(&dev_priv->pps_mutex);
624
9a42356b
VS		 625 if (IS_VALLEYVIEW(dev) &&
626 intel_dp->pps_pipe == INVALID_PIPE)
627 return false;
628
773538e8 629 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 630}
631
9b984dae
KP		 632static void
633intel_dp_check_edp(struct intel_dp *intel_dp)
634{
30add22d 635 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 636 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 637
9b984dae
KP		 638 if (!is_edp(intel_dp))
639 return;
453c5420 640
4be73780 641 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 642 WARN(1, "eDP powered off while attempting aux channel communication.\n");
643 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 644 I915_READ(_pp_stat_reg(intel_dp)),
645 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 646 }
647}
648
9ee32fea
DV		 649static uint32_t
650intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
651{
652 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
653 struct drm_device *dev = intel_dig_port->base.base.dev;
654 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 655 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 656 uint32_t status;
657 bool done;
658
ef04f00d 659#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 660 if (has_aux_irq)
b18ac466 661 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 662 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 663 else
664 done = wait_for_atomic(C, 10) == 0;
665 if (!done)
666 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
667 has_aux_irq);
668#undef C
669
670 return status;
671}
672
ec5b01dd 673static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 674{
174edf1f
PZ		 675 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
676 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 677
ec5b01dd
DL		 678 /*
679 * The clock divider is based off the hrawclk, and would like to run at
680 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 681 */
ec5b01dd
DL		 682 return index ? 0 : intel_hrawclk(dev) / 2;
683}
684
685static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
686{
687 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
688 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 689 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 690
691 if (index)
692 return 0;
693
694 if (intel_dig_port->port == PORT_A) {
05024da3
VS		 695 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
696
ec5b01dd
DL		 697 } else {
698 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
699 }
700}
701
702static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
703{
704 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
705 struct drm_device *dev = intel_dig_port->base.base.dev;
706 struct drm_i915_private *dev_priv = dev->dev_private;
707
708 if (intel_dig_port->port == PORT_A) {
709 if (index)
710 return 0;
05024da3 711 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
2c55c336
JN		 712 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
713 /* Workaround for non-ULT HSW */
bc86625a
CW		 714 switch (index) {
715 case 0: return 63;
716 case 1: return 72;
717 default: return 0;
718 }
ec5b01dd 719 } else {
bc86625a 720 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 721 }
b84a1cf8
RV		 722}
723
ec5b01dd
DL		 724static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
725{
726 return index ? 0 : 100;
727}
728
b6b5e383
DL		 729static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
730{
731 /*
732 * SKL doesn't need us to program the AUX clock divider (Hardware will
733 * derive the clock from CDCLK automatically). We still implement the
734 * get_aux_clock_divider vfunc to plug-in into the existing code.
735 */
736 return index ? 0 : 1;
737}
738
5ed12a19
DL		 739static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
740 bool has_aux_irq,
741 int send_bytes,
742 uint32_t aux_clock_divider)
743{
744 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
745 struct drm_device *dev = intel_dig_port->base.base.dev;
746 uint32_t precharge, timeout;
747
748 if (IS_GEN6(dev))
749 precharge = 3;
750 else
751 precharge = 5;
752
f3c6a3a7 753 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 754 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
755 else
756 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
757
758 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 759 DP_AUX_CH_CTL_DONE |
5ed12a19 760 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 761 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 762 timeout |
788d4433 763 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 764 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
765 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 766 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 767}
768
b9ca5fad
DL		 769static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
770 bool has_aux_irq,
771 int send_bytes,
772 uint32_t unused)
773{
774 return DP_AUX_CH_CTL_SEND_BUSY |
775 DP_AUX_CH_CTL_DONE |
776 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
777 DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_TIME_OUT_1600us |
779 DP_AUX_CH_CTL_RECEIVE_ERROR |
780 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
781 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
782}
783
b84a1cf8
RV		 784static int
785intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 786 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 787 uint8_t *recv, int recv_size)
788{
789 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
790 struct drm_device *dev = intel_dig_port->base.base.dev;
791 struct drm_i915_private *dev_priv = dev->dev_private;
792 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 793 uint32_t aux_clock_divider;
b84a1cf8
RV		 794 int i, ret, recv_bytes;
795 uint32_t status;
5ed12a19 796 int try, clock = 0;
4e6b788c 797 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 798 bool vdd;
799
773538e8 800 pps_lock(intel_dp);
e39b999a 801
72c3500a
VS		 802 /*
803 * We will be called with VDD already enabled for dpcd/edid/oui reads.
804 * In such cases we want to leave VDD enabled and it's up to upper layers
805 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
806 * ourselves.
807 */
1e0560e0 808 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 809
810 /* dp aux is extremely sensitive to irq latency, hence request the
811 * lowest possible wakeup latency and so prevent the cpu from going into
812 * deep sleep states.
813 */
814 pm_qos_update_request(&dev_priv->pm_qos, 0);
815
816 intel_dp_check_edp(intel_dp);
5eb08b69 817
11bee43e
JB		 818 /* Try to wait for any previous AUX channel activity */
819 for (try = 0; try < 3; try++) {
ef04f00d 820 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 821 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
822 break;
823 msleep(1);
824 }
825
826 if (try == 3) {
02196c77
MK		 827 static u32 last_status = -1;
828 const u32 status = I915_READ(ch_ctl);
829
830 if (status != last_status) {
831 WARN(1, "dp_aux_ch not started status 0x%08x\n",
832 status);
833 last_status = status;
834 }
835
9ee32fea
DV		 836 ret = -EBUSY;
837 goto out;
4f7f7b7e
CW		 838 }
839
46a5ae9f
PZ		 840 /* Only 5 data registers! */
841 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
842 ret = -E2BIG;
843 goto out;
844 }
845
ec5b01dd 846 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 847 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
848 has_aux_irq,
849 send_bytes,
850 aux_clock_divider);
5ed12a19 851
bc86625a
CW		 852 /* Must try at least 3 times according to DP spec */
853 for (try = 0; try < 5; try++) {
854 /* Load the send data into the aux channel data registers */
855 for (i = 0; i < send_bytes; i += 4)
330e20ec 856 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 857 intel_dp_pack_aux(send + i,
858 send_bytes - i));
bc86625a
CW		 859
860 /* Send the command and wait for it to complete */
5ed12a19 861 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 862
863 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
864
865 /* Clear done status and any errors */
866 I915_WRITE(ch_ctl,
867 status |
868 DP_AUX_CH_CTL_DONE |
869 DP_AUX_CH_CTL_TIME_OUT_ERROR |
870 DP_AUX_CH_CTL_RECEIVE_ERROR);
871
74ebf294 872 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 873 continue;
74ebf294
TP		 874
875 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
876 * 400us delay required for errors and timeouts
877 * Timeout errors from the HW already meet this
878 * requirement so skip to next iteration
879 */
880 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
881 usleep_range(400, 500);
bc86625a 882 continue;
74ebf294 883 }
bc86625a 884 if (status & DP_AUX_CH_CTL_DONE)
e058c945 885 goto done;
bc86625a 886 }
a4fc5ed6
KP		 887 }
888
a4fc5ed6 889 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 890 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 891 ret = -EBUSY;
892 goto out;
a4fc5ed6
KP		 893 }
894
e058c945 895done:
a4fc5ed6
KP		 896 /* Check for timeout or receive error.
897 * Timeouts occur when the sink is not connected
898 */
a5b3da54 899 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 900 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 901 ret = -EIO;
902 goto out;
a5b3da54 903 }
1ae8c0a5
KP		 904
905 /* Timeouts occur when the device isn't connected, so they're
906 * "normal" -- don't fill the kernel log with these */
a5b3da54 907 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 908 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 909 ret = -ETIMEDOUT;
910 goto out;
a4fc5ed6
KP		 911 }
912
913 /* Unload any bytes sent back from the other side */
914 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
915 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 916 if (recv_bytes > recv_size)
917 recv_bytes = recv_size;
0206e353 918
4f7f7b7e 919 for (i = 0; i < recv_bytes; i += 4)
330e20ec 920 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 921 recv + i, recv_bytes - i);
a4fc5ed6 922
9ee32fea
DV		 923 ret = recv_bytes;
924out:
925 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
926
884f19e9
JN		 927 if (vdd)
928 edp_panel_vdd_off(intel_dp, false);
929
773538e8 930 pps_unlock(intel_dp);
e39b999a 931
9ee32fea 932 return ret;
a4fc5ed6
KP		 933}
934
a6c8aff0
JN		 935#define BARE_ADDRESS_SIZE 3
936#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 937static ssize_t
938intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 939{
9d1a1031
JN		 940 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
941 uint8_t txbuf[20], rxbuf[20];
942 size_t txsize, rxsize;
a4fc5ed6 943 int ret;
a4fc5ed6 944
d2d9cbbd
VS		 945 txbuf[0] = (msg->request << 4) |
946 ((msg->address >> 16) & 0xf);
947 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 948 txbuf[2] = msg->address & 0xff;
949 txbuf[3] = msg->size - 1;
46a5ae9f 950
9d1a1031
JN		 951 switch (msg->request & ~DP_AUX_I2C_MOT) {
952 case DP_AUX_NATIVE_WRITE:
953 case DP_AUX_I2C_WRITE:
c1e74122 954 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 955 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 956 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 957
9d1a1031
JN		 958 if (WARN_ON(txsize > 20))
959 return -E2BIG;
a4fc5ed6 960
9d1a1031 961 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 962
9d1a1031
JN		 963 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
964 if (ret > 0) {
965 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 966
a1ddefd8
JN		 967 if (ret > 1) {
968 /* Number of bytes written in a short write. */
969 ret = clamp_t(int, rxbuf[1], 0, msg->size);
970 } else {
971 /* Return payload size. */
972 ret = msg->size;
973 }
9d1a1031
JN		 974 }
975 break;
46a5ae9f 976
9d1a1031
JN		 977 case DP_AUX_NATIVE_READ:
978 case DP_AUX_I2C_READ:
a6c8aff0 979 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 980 rxsize = msg->size + 1;
a4fc5ed6 981
9d1a1031
JN		 982 if (WARN_ON(rxsize > 20))
983 return -E2BIG;
a4fc5ed6 984
9d1a1031
JN		 985 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
986 if (ret > 0) {
987 msg->reply = rxbuf[0] >> 4;
988 /*
989 * Assume happy day, and copy the data. The caller is
990 * expected to check msg->reply before touching it.
991 *
992 * Return payload size.
993 */
994 ret--;
995 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 996 }
9d1a1031
JN		 997 break;
998
999 default:
1000 ret = -EINVAL;
1001 break;
a4fc5ed6 1002 }
f51a44b9 1003
9d1a1031 1004 return ret;
a4fc5ed6
KP		 1005}
1006
da00bdcf
VS		 1007static uint32_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1008 enum port port)
1009{
1010 switch (port) {
1011 case PORT_B:
1012 case PORT_C:
1013 case PORT_D:
1014 return DP_AUX_CH_CTL(port);
1015 default:
1016 MISSING_CASE(port);
1017 return DP_AUX_CH_CTL(PORT_B);
1018 }
1019}
1020
330e20ec
VS		 1021static uint32_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1022 enum port port, int index)
1023{
1024 switch (port) {
1025 case PORT_B:
1026 case PORT_C:
1027 case PORT_D:
1028 return DP_AUX_CH_DATA(port, index);
1029 default:
1030 MISSING_CASE(port);
1031 return DP_AUX_CH_DATA(PORT_B, index);
1032 }
1033}
1034
da00bdcf
VS		 1035static uint32_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1036 enum port port)
1037{
1038 switch (port) {
1039 case PORT_A:
1040 return DP_AUX_CH_CTL(port);
1041 case PORT_B:
1042 case PORT_C:
1043 case PORT_D:
1044 return PCH_DP_AUX_CH_CTL(port);
1045 default:
1046 MISSING_CASE(port);
1047 return DP_AUX_CH_CTL(PORT_A);
1048 }
1049}
1050
330e20ec
VS		 1051static uint32_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1052 enum port port, int index)
1053{
1054 switch (port) {
1055 case PORT_A:
1056 return DP_AUX_CH_DATA(port, index);
1057 case PORT_B:
1058 case PORT_C:
1059 case PORT_D:
1060 return PCH_DP_AUX_CH_DATA(port, index);
1061 default:
1062 MISSING_CASE(port);
1063 return DP_AUX_CH_DATA(PORT_A, index);
1064 }
1065}
1066
da00bdcf
VS		 1067/*
1068 * On SKL we don't have Aux for port E so we rely
1069 * on VBT to set a proper alternate aux channel.
1070 */
1071static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1072{
1073 const struct ddi_vbt_port_info *info =
1074 &dev_priv->vbt.ddi_port_info[PORT_E];
1075
1076 switch (info->alternate_aux_channel) {
1077 case DP_AUX_A:
1078 return PORT_A;
1079 case DP_AUX_B:
1080 return PORT_B;
1081 case DP_AUX_C:
1082 return PORT_C;
1083 case DP_AUX_D:
1084 return PORT_D;
1085 default:
1086 MISSING_CASE(info->alternate_aux_channel);
1087 return PORT_A;
1088 }
1089}
1090
1091static uint32_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1092 enum port port)
1093{
1094 if (port == PORT_E)
1095 port = skl_porte_aux_port(dev_priv);
1096
1097 switch (port) {
1098 case PORT_A:
1099 case PORT_B:
1100 case PORT_C:
1101 case PORT_D:
1102 return DP_AUX_CH_CTL(port);
1103 default:
1104 MISSING_CASE(port);
1105 return DP_AUX_CH_CTL(PORT_A);
1106 }
1107}
1108
330e20ec
VS		 1109static uint32_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1110 enum port port, int index)
1111{
1112 if (port == PORT_E)
1113 port = skl_porte_aux_port(dev_priv);
1114
1115 switch (port) {
1116 case PORT_A:
1117 case PORT_B:
1118 case PORT_C:
1119 case PORT_D:
1120 return DP_AUX_CH_DATA(port, index);
1121 default:
1122 MISSING_CASE(port);
1123 return DP_AUX_CH_DATA(PORT_A, index);
1124 }
1125}
1126
1127static uint32_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1128 enum port port)
1129{
1130 if (INTEL_INFO(dev_priv)->gen >= 9)
1131 return skl_aux_ctl_reg(dev_priv, port);
1132 else if (HAS_PCH_SPLIT(dev_priv))
1133 return ilk_aux_ctl_reg(dev_priv, port);
1134 else
1135 return g4x_aux_ctl_reg(dev_priv, port);
1136}
1137
1138static uint32_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1139 enum port port, int index)
1140{
1141 if (INTEL_INFO(dev_priv)->gen >= 9)
1142 return skl_aux_data_reg(dev_priv, port, index);
1143 else if (HAS_PCH_SPLIT(dev_priv))
1144 return ilk_aux_data_reg(dev_priv, port, index);
1145 else
1146 return g4x_aux_data_reg(dev_priv, port, index);
1147}
1148
1149static void intel_aux_reg_init(struct intel_dp *intel_dp)
1150{
1151 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1152 enum port port = dp_to_dig_port(intel_dp)->port;
1153 int i;
1154
1155 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1156 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1157 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1158}
1159
9d1a1031 1160static void
a121f4e5
VS		 1161intel_dp_aux_fini(struct intel_dp *intel_dp)
1162{
1163 drm_dp_aux_unregister(&intel_dp->aux);
1164 kfree(intel_dp->aux.name);
1165}
1166
1167static int
9d1a1031
JN		 1168intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1169{
1170 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1171 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1172 enum port port = intel_dig_port->port;
ab2c0672
DA		 1173 int ret;
1174
330e20ec 1175 intel_aux_reg_init(intel_dp);
8316f337 1176
a121f4e5
VS		 1177 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1178 if (!intel_dp->aux.name)
1179 return -ENOMEM;
1180
9d1a1031
JN		 1181 intel_dp->aux.dev = dev->dev;
1182 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1183
a121f4e5
VS		 1184 DRM_DEBUG_KMS("registering %s bus for %s\n",
1185 intel_dp->aux.name,
0b99836f 1186 connector->base.kdev->kobj.name);
8316f337 1187
4f71d0cb 1188 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1189 if (ret < 0) {
4f71d0cb 1190 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
a121f4e5
VS		 1191 intel_dp->aux.name, ret);
1192 kfree(intel_dp->aux.name);
1193 return ret;
ab2c0672 1194 }
8a5e6aeb 1195
0b99836f
JN		 1196 ret = sysfs_create_link(&connector->base.kdev->kobj,
1197 &intel_dp->aux.ddc.dev.kobj,
1198 intel_dp->aux.ddc.dev.kobj.name);
1199 if (ret < 0) {
a121f4e5
VS		 1200 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
1201 intel_dp->aux.name, ret);
1202 intel_dp_aux_fini(intel_dp);
1203 return ret;
ab2c0672 1204 }
a121f4e5
VS		 1205
1206 return 0;
a4fc5ed6
KP		 1207}
1208
80f65de3
ID		 1209static void
1210intel_dp_connector_unregister(struct intel_connector *intel_connector)
1211{
1212 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1213
0e32b39c
DA		 1214 if (!intel_connector->mst_port)
1215 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1216 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1217 intel_connector_unregister(intel_connector);
1218}
1219
5416d871 1220static void
840b32b7 1221skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
5416d871
DL		 1222{
1223 u32 ctrl1;
1224
dd3cd74a
ACO		 1225 memset(&pipe_config->dpll_hw_state, 0,
1226 sizeof(pipe_config->dpll_hw_state));
1227
5416d871
DL		 1228 pipe_config->ddi_pll_sel = SKL_DPLL0;
1229 pipe_config->dpll_hw_state.cfgcr1 = 0;
1230 pipe_config->dpll_hw_state.cfgcr2 = 0;
1231
1232 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
840b32b7 1233 switch (pipe_config->port_clock / 2) {
c3346ef6 1234 case 81000:
71cd8423 1235 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5416d871
DL		 1236 SKL_DPLL0);
1237 break;
c3346ef6 1238 case 135000:
71cd8423 1239 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
5416d871
DL		 1240 SKL_DPLL0);
1241 break;
c3346ef6 1242 case 270000:
71cd8423 1243 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
5416d871
DL		 1244 SKL_DPLL0);
1245 break;
c3346ef6 1246 case 162000:
71cd8423 1247 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
c3346ef6
SJ		 1248 SKL_DPLL0);
1249 break;
1250 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1251 results in CDCLK change. Need to handle the change of CDCLK by
1252 disabling pipes and re-enabling them */
1253 case 108000:
71cd8423 1254 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
c3346ef6
SJ		 1255 SKL_DPLL0);
1256 break;
1257 case 216000:
71cd8423 1258 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
c3346ef6
SJ		 1259 SKL_DPLL0);
1260 break;
1261
5416d871
DL		 1262 }
1263 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1264}
1265
6fa2d197 1266void
840b32b7 1267hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
0e50338c 1268{
ee46f3c7
ACO		 1269 memset(&pipe_config->dpll_hw_state, 0,
1270 sizeof(pipe_config->dpll_hw_state));
1271
840b32b7
VS		 1272 switch (pipe_config->port_clock / 2) {
1273 case 81000:
0e50338c
DV		 1274 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1275 break;
840b32b7 1276 case 135000:
0e50338c
DV		 1277 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1278 break;
840b32b7 1279 case 270000:
0e50338c
DV		 1280 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1281 break;
1282 }
1283}
1284
fc0f8e25 1285static int
12f6a2e2 1286intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1287{
94ca719e
VS		 1288 if (intel_dp->num_sink_rates) {
1289 *sink_rates = intel_dp->sink_rates;
1290 return intel_dp->num_sink_rates;
fc0f8e25 1291 }
12f6a2e2
VS		 1292
1293 *sink_rates = default_rates;
1294
1295 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1296}
1297
e588fa18 1298bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1299{
e588fa18
ACO		 1300 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1301 struct drm_device *dev = dig_port->base.base.dev;
1302
ed63baaf 1303 /* WaDisableHBR2:skl */
e87a005d 1304 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1305 return false;
1306
1307 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1308 (INTEL_INFO(dev)->gen >= 9))
1309 return true;
1310 else
1311 return false;
1312}
1313
a8f3ef61 1314static int
e588fa18 1315intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1316{
e588fa18
ACO		 1317 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1318 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1319 int size;
1320
64987fc5
SJ		 1321 if (IS_BROXTON(dev)) {
1322 *source_rates = bxt_rates;
af7080f5 1323 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1324 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1325 *source_rates = skl_rates;
af7080f5
TS		 1326 size = ARRAY_SIZE(skl_rates);
1327 } else {
1328 *source_rates = default_rates;
1329 size = ARRAY_SIZE(default_rates);
a8f3ef61 1330 }
636280ba 1331
ed63baaf 1332 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1333 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1334 size--;
636280ba 1335
af7080f5 1336 return size;
a8f3ef61
SJ		 1337}
1338
c6bb3538
DV		 1339static void
1340intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1341 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1342{
1343 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1344 const struct dp_link_dpll *divisor = NULL;
1345 int i, count = 0;
c6bb3538
DV		 1346
1347 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1348 divisor = gen4_dpll;
1349 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1350 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1351 divisor = pch_dpll;
1352 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1353 } else if (IS_CHERRYVIEW(dev)) {
1354 divisor = chv_dpll;
1355 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1356 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1357 divisor = vlv_dpll;
1358 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1359 }
9dd4ffdf
CML		 1360
1361 if (divisor && count) {
1362 for (i = 0; i < count; i++) {
840b32b7 1363 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1364 pipe_config->dpll = divisor[i].dpll;
1365 pipe_config->clock_set = true;
1366 break;
1367 }
1368 }
c6bb3538
DV		 1369 }
1370}
1371
2ecae76a
VS		 1372static int intersect_rates(const int *source_rates, int source_len,
1373 const int *sink_rates, int sink_len,
94ca719e 1374 int *common_rates)
a8f3ef61
SJ		 1375{
1376 int i = 0, j = 0, k = 0;
1377
a8f3ef61
SJ		 1378 while (i < source_len && j < sink_len) {
1379 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1380 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1381 return k;
94ca719e 1382 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1383 ++k;
1384 ++i;
1385 ++j;
1386 } else if (source_rates[i] < sink_rates[j]) {
1387 ++i;
1388 } else {
1389 ++j;
1390 }
1391 }
1392 return k;
1393}
1394
94ca719e
VS		 1395static int intel_dp_common_rates(struct intel_dp *intel_dp,
1396 int *common_rates)
2ecae76a 1397{
2ecae76a
VS		 1398 const int *source_rates, *sink_rates;
1399 int source_len, sink_len;
1400
1401 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1402 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1403
1404 return intersect_rates(source_rates, source_len,
1405 sink_rates, sink_len,
94ca719e 1406 common_rates);
2ecae76a
VS		 1407}
1408
0336400e
VS		 1409static void snprintf_int_array(char *str, size_t len,
1410 const int *array, int nelem)
1411{
1412 int i;
1413
1414 str[0] = '\0';
1415
1416 for (i = 0; i < nelem; i++) {
b2f505be 1417 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1418 if (r >= len)
1419 return;
1420 str += r;
1421 len -= r;
1422 }
1423}
1424
1425static void intel_dp_print_rates(struct intel_dp *intel_dp)
1426{
0336400e 1427 const int *source_rates, *sink_rates;
94ca719e
VS		 1428 int source_len, sink_len, common_len;
1429 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1430 char str[128]; /* FIXME: too big for stack? */
1431
1432 if ((drm_debug & DRM_UT_KMS) == 0)
1433 return;
1434
e588fa18 1435 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1436 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1437 DRM_DEBUG_KMS("source rates: %s\n", str);
1438
1439 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1440 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1441 DRM_DEBUG_KMS("sink rates: %s\n", str);
1442
94ca719e
VS		 1443 common_len = intel_dp_common_rates(intel_dp, common_rates);
1444 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1445 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1446}
1447
f4896f15 1448static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1449{
1450 int i = 0;
1451
1452 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1453 if (find == rates[i])
1454 break;
1455
1456 return i;
1457}
1458
50fec21a
VS		 1459int
1460intel_dp_max_link_rate(struct intel_dp *intel_dp)
1461{
1462 int rates[DP_MAX_SUPPORTED_RATES] = {};
1463 int len;
1464
94ca719e 1465 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1466 if (WARN_ON(len <= 0))
1467 return 162000;
1468
1469 return rates[rate_to_index(0, rates) - 1];
1470}
1471
ed4e9c1d
VS		 1472int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1473{
94ca719e 1474 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1475}
1476
94223d04
ACO		 1477void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1478 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1479{
1480 if (intel_dp->num_sink_rates) {
1481 *link_bw = 0;
1482 *rate_select =
1483 intel_dp_rate_select(intel_dp, port_clock);
1484 } else {
1485 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1486 *rate_select = 0;
1487 }
1488}
1489
00c09d70 1490bool
5bfe2ac0 1491intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1492 struct intel_crtc_state *pipe_config)
a4fc5ed6 1493{
5bfe2ac0 1494 struct drm_device *dev = encoder->base.dev;
36008365 1495 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1496 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1497 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1498 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1499 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1500 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1501 int lane_count, clock;
56071a20 1502 int min_lane_count = 1;
eeb6324d 1503 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1504 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1505 int min_clock = 0;
a8f3ef61 1506 int max_clock;
083f9560 1507 int bpp, mode_rate;
ff9a6750 1508 int link_avail, link_clock;
94ca719e
VS		 1509 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1510 int common_len;
04a60f9f 1511 uint8_t link_bw, rate_select;
a8f3ef61 1512
94ca719e 1513 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1514
1515 /* No common link rates between source and sink */
94ca719e 1516 WARN_ON(common_len <= 0);
a8f3ef61 1517
94ca719e 1518 max_clock = common_len - 1;
a4fc5ed6 1519
bc7d38a4 1520 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1521 pipe_config->has_pch_encoder = true;
1522
03afc4a2 1523 pipe_config->has_dp_encoder = true;
f769cd24 1524 pipe_config->has_drrs = false;
9fcb1704 1525 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1526
dd06f90e
JN		 1527 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1528 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1529 adjusted_mode);
a1b2278e
CK		 1530
1531 if (INTEL_INFO(dev)->gen >= 9) {
1532 int ret;
e435d6e5 1533 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1534 if (ret)
1535 return ret;
1536 }
1537
b5667627 1538 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1539 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1540 intel_connector->panel.fitting_mode);
1541 else
b074cec8
JB		 1542 intel_pch_panel_fitting(intel_crtc, pipe_config,
1543 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1544 }
1545
cb1793ce 1546 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1547 return false;
1548
083f9560 1549 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1550 "max bw %d pixel clock %iKHz\n",
94ca719e 1551 max_lane_count, common_rates[max_clock],
241bfc38 1552 adjusted_mode->crtc_clock);
083f9560 1553
36008365
DV		 1554 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1555 * bpc in between. */
3e7ca985 1556 bpp = pipe_config->pipe_bpp;
56071a20 1557 if (is_edp(intel_dp)) {
22ce5628
TS		 1558
1559 /* Get bpp from vbt only for panels that dont have bpp in edid */
1560 if (intel_connector->base.display_info.bpc == 0 &&
1561 (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
56071a20
JN		 1562 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1563 dev_priv->vbt.edp_bpp);
1564 bpp = dev_priv->vbt.edp_bpp;
1565 }
1566
344c5bbc
JN		 1567 /*
1568 * Use the maximum clock and number of lanes the eDP panel
1569 * advertizes being capable of. The panels are generally
1570 * designed to support only a single clock and lane
1571 * configuration, and typically these values correspond to the
1572 * native resolution of the panel.
1573 */
1574 min_lane_count = max_lane_count;
1575 min_clock = max_clock;
7984211e 1576 }
657445fe 1577
36008365 1578 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1579 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1580 bpp);
36008365 1581
c6930992 1582 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1583 for (lane_count = min_lane_count;
1584 lane_count <= max_lane_count;
1585 lane_count <<= 1) {
1586
94ca719e 1587 link_clock = common_rates[clock];
36008365
DV		 1588 link_avail = intel_dp_max_data_rate(link_clock,
1589 lane_count);
1590
1591 if (mode_rate <= link_avail) {
1592 goto found;
1593 }
1594 }
1595 }
1596 }
c4867936 1597
36008365 1598 return false;
3685a8f3 1599
36008365 1600found:
55bc60db
VS		 1601 if (intel_dp->color_range_auto) {
1602 /*
1603 * See:
1604 * CEA-861-E - 5.1 Default Encoding Parameters
1605 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1606 */
0f2a2a75
VS		 1607 pipe_config->limited_color_range =
1608 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1609 } else {
1610 pipe_config->limited_color_range =
1611 intel_dp->limited_color_range;
55bc60db
VS		 1612 }
1613
90a6b7b0 1614 pipe_config->lane_count = lane_count;
a8f3ef61 1615
657445fe 1616 pipe_config->pipe_bpp = bpp;
94ca719e 1617 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1618
04a60f9f
VS		 1619 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1620 &link_bw, &rate_select);
1621
1622 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1623 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1624 pipe_config->port_clock, bpp);
36008365
DV		 1625 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1626 mode_rate, link_avail);
a4fc5ed6 1627
03afc4a2 1628 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1629 adjusted_mode->crtc_clock,
1630 pipe_config->port_clock,
03afc4a2 1631 &pipe_config->dp_m_n);
9d1a455b 1632
439d7ac0 1633 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1634 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1635 pipe_config->has_drrs = true;
439d7ac0
PB		 1636 intel_link_compute_m_n(bpp, lane_count,
1637 intel_connector->panel.downclock_mode->clock,
1638 pipe_config->port_clock,
1639 &pipe_config->dp_m2_n2);
1640 }
1641
ef11bdb3 1642 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && is_edp(intel_dp))
840b32b7 1643 skl_edp_set_pll_config(pipe_config);
977bb38d
S		 1644 else if (IS_BROXTON(dev))
1645 /* handled in ddi */;
5416d871 1646 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
840b32b7 1647 hsw_dp_set_ddi_pll_sel(pipe_config);
0e50338c 1648 else
840b32b7 1649 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1650
03afc4a2 1651 return true;
a4fc5ed6
KP		 1652}
1653
901c2daf
VS		 1654void intel_dp_set_link_params(struct intel_dp *intel_dp,
1655 const struct intel_crtc_state *pipe_config)
1656{
1657 intel_dp->link_rate = pipe_config->port_clock;
1658 intel_dp->lane_count = pipe_config->lane_count;
1659}
1660
8ac33ed3 1661static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1662{
b934223d 1663 struct drm_device *dev = encoder->base.dev;
417e822d 1664 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1665 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1666 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1667 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1668 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1669
901c2daf
VS		 1670 intel_dp_set_link_params(intel_dp, crtc->config);
1671
417e822d 1672 /*
1a2eb460 1673 * There are four kinds of DP registers:
417e822d
KP		 1674 *
1675 * IBX PCH
1a2eb460
KP		 1676 * SNB CPU
1677 * IVB CPU
417e822d
KP		 1678 * CPT PCH
1679 *
1680 * IBX PCH and CPU are the same for almost everything,
1681 * except that the CPU DP PLL is configured in this
1682 * register
1683 *
1684 * CPT PCH is quite different, having many bits moved
1685 * to the TRANS_DP_CTL register instead. That
1686 * configuration happens (oddly) in ironlake_pch_enable
1687 */
9c9e7927 1688
417e822d
KP		 1689 /* Preserve the BIOS-computed detected bit. This is
1690 * supposed to be read-only.
1691 */
1692 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1693
417e822d 1694 /* Handle DP bits in common between all three register formats */
417e822d 1695 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1696 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1697
417e822d 1698 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1699
39e5fa88 1700 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1701 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1702 intel_dp->DP |= DP_SYNC_HS_HIGH;
1703 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1704 intel_dp->DP |= DP_SYNC_VS_HIGH;
1705 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1706
6aba5b6c 1707 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1708 intel_dp->DP |= DP_ENHANCED_FRAMING;
1709
7c62a164 1710 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1711 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1712 u32 trans_dp;
1713
39e5fa88 1714 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1715
1716 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1717 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1718 trans_dp |= TRANS_DP_ENH_FRAMING;
1719 else
1720 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1721 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1722 } else {
0f2a2a75
VS		 1723 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1724 crtc->config->limited_color_range)
1725 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1726
1727 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1728 intel_dp->DP |= DP_SYNC_HS_HIGH;
1729 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1730 intel_dp->DP |= DP_SYNC_VS_HIGH;
1731 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1732
6aba5b6c 1733 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1734 intel_dp->DP |= DP_ENHANCED_FRAMING;
1735
39e5fa88 1736 if (IS_CHERRYVIEW(dev))
44f37d1f 1737 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1738 else if (crtc->pipe == PIPE_B)
1739 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1740 }
a4fc5ed6
KP		 1741}
1742
ffd6749d
PZ		 1743#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1744#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1745
1a5ef5b7
PZ		 1746#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1747#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1748
ffd6749d
PZ		 1749#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1750#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1751
4be73780 1752static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1753 u32 mask,
1754 u32 value)
bd943159 1755{
30add22d 1756 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1757 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1758 u32 pp_stat_reg, pp_ctrl_reg;
1759
e39b999a
VS		 1760 lockdep_assert_held(&dev_priv->pps_mutex);
1761
bf13e81b
JN		 1762 pp_stat_reg = _pp_stat_reg(intel_dp);
1763 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1764
99ea7127 1765 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1766 mask, value,
1767 I915_READ(pp_stat_reg),
1768 I915_READ(pp_ctrl_reg));
32ce697c 1769
453c5420 1770 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1771 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1772 I915_READ(pp_stat_reg),
1773 I915_READ(pp_ctrl_reg));
32ce697c 1774 }
54c136d4
CW		 1775
1776 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1777}
32ce697c 1778
4be73780 1779static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1780{
1781 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1782 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1783}
1784
4be73780 1785static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1786{
1787 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1788 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1789}
1790
4be73780 1791static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1792{
1793 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1794
1795 /* When we disable the VDD override bit last we have to do the manual
1796 * wait. */
1797 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1798 intel_dp->panel_power_cycle_delay);
1799
4be73780 1800 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1801}
1802
4be73780 1803static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1804{
1805 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1806 intel_dp->backlight_on_delay);
1807}
1808
4be73780 1809static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1810{
1811 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1812 intel_dp->backlight_off_delay);
1813}
99ea7127 1814
832dd3c1
KP		 1815/* Read the current pp_control value, unlocking the register if it
1816 * is locked
1817 */
1818
453c5420 1819static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1820{
453c5420
JB		 1821 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823 u32 control;
832dd3c1 1824
e39b999a
VS		 1825 lockdep_assert_held(&dev_priv->pps_mutex);
1826
bf13e81b 1827 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1828 if (!IS_BROXTON(dev)) {
1829 control &= ~PANEL_UNLOCK_MASK;
1830 control |= PANEL_UNLOCK_REGS;
1831 }
832dd3c1 1832 return control;
bd943159
KP		 1833}
1834
951468f3
VS		 1835/*
1836 * Must be paired with edp_panel_vdd_off().
1837 * Must hold pps_mutex around the whole on/off sequence.
1838 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1839 */
1e0560e0 1840static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1841{
30add22d 1842 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1843 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1844 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1845 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1846 enum intel_display_power_domain power_domain;
5d613501 1847 u32 pp;
453c5420 1848 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1849 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1850
e39b999a
VS		 1851 lockdep_assert_held(&dev_priv->pps_mutex);
1852
97af61f5 1853 if (!is_edp(intel_dp))
adddaaf4 1854 return false;
bd943159 1855
2c623c11 1856 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1857 intel_dp->want_panel_vdd = true;
99ea7127 1858
4be73780 1859 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1860 return need_to_disable;
b0665d57 1861
25f78f58 1862 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1863 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1864
3936fcf4
VS		 1865 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1866 port_name(intel_dig_port->port));
bd943159 1867
4be73780
DV		 1868 if (!edp_have_panel_power(intel_dp))
1869 wait_panel_power_cycle(intel_dp);
99ea7127 1870
453c5420 1871 pp = ironlake_get_pp_control(intel_dp);
5d613501 1872 pp |= EDP_FORCE_VDD;
ebf33b18 1873
bf13e81b
JN		 1874 pp_stat_reg = _pp_stat_reg(intel_dp);
1875 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1876
1877 I915_WRITE(pp_ctrl_reg, pp);
1878 POSTING_READ(pp_ctrl_reg);
1879 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1880 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1881 /*
1882 * If the panel wasn't on, delay before accessing aux channel
1883 */
4be73780 1884 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1885 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1886 port_name(intel_dig_port->port));
f01eca2e 1887 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1888 }
adddaaf4
JN		 1889
1890 return need_to_disable;
1891}
1892
951468f3
VS		 1893/*
1894 * Must be paired with intel_edp_panel_vdd_off() or
1895 * intel_edp_panel_off().
1896 * Nested calls to these functions are not allowed since
1897 * we drop the lock. Caller must use some higher level
1898 * locking to prevent nested calls from other threads.
1899 */
b80d6c78 1900void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1901{
c695b6b6 1902 bool vdd;
adddaaf4 1903
c695b6b6
VS		 1904 if (!is_edp(intel_dp))
1905 return;
1906
773538e8 1907 pps_lock(intel_dp);
c695b6b6 1908 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1909 pps_unlock(intel_dp);
c695b6b6 1910
e2c719b7 1911 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1912 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1913}
1914
4be73780 1915static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1916{
30add22d 1917 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1918 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1919 struct intel_digital_port *intel_dig_port =
1920 dp_to_dig_port(intel_dp);
1921 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1922 enum intel_display_power_domain power_domain;
5d613501 1923 u32 pp;
453c5420 1924 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1925
e39b999a 1926 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1927
15e899a0 1928 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1929
15e899a0 1930 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1931 return;
b0665d57 1932
3936fcf4
VS		 1933 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1934 port_name(intel_dig_port->port));
bd943159 1935
be2c9196
VS		 1936 pp = ironlake_get_pp_control(intel_dp);
1937 pp &= ~EDP_FORCE_VDD;
453c5420 1938
be2c9196
VS		 1939 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1940 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1941
be2c9196
VS		 1942 I915_WRITE(pp_ctrl_reg, pp);
1943 POSTING_READ(pp_ctrl_reg);
90791a5c 1944
be2c9196
VS		 1945 /* Make sure sequencer is idle before allowing subsequent activity */
1946 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1947 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1948
be2c9196
VS		 1949 if ((pp & POWER_TARGET_ON) == 0)
1950 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1951
25f78f58 1952 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1953 intel_display_power_put(dev_priv, power_domain);
bd943159 1954}
5d613501 1955
4be73780 1956static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1957{
1958 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1959 struct intel_dp, panel_vdd_work);
bd943159 1960
773538e8 1961 pps_lock(intel_dp);
15e899a0
VS		 1962 if (!intel_dp->want_panel_vdd)
1963 edp_panel_vdd_off_sync(intel_dp);
773538e8 1964 pps_unlock(intel_dp);
bd943159
KP		 1965}
1966
aba86890
ID		 1967static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1968{
1969 unsigned long delay;
1970
1971 /*
1972 * Queue the timer to fire a long time from now (relative to the power
1973 * down delay) to keep the panel power up across a sequence of
1974 * operations.
1975 */
1976 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1977 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1978}
1979
951468f3
VS		 1980/*
1981 * Must be paired with edp_panel_vdd_on().
1982 * Must hold pps_mutex around the whole on/off sequence.
1983 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1984 */
4be73780 1985static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1986{
e39b999a
VS		 1987 struct drm_i915_private *dev_priv =
1988 intel_dp_to_dev(intel_dp)->dev_private;
1989
1990 lockdep_assert_held(&dev_priv->pps_mutex);
1991
97af61f5
KP		 1992 if (!is_edp(intel_dp))
1993 return;
5d613501 1994
e2c719b7 1995 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1996 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1997
bd943159
KP		 1998 intel_dp->want_panel_vdd = false;
1999
aba86890 2000 if (sync)
4be73780 2001 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2002 else
2003 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2004}
2005
9f0fb5be 2006static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2007{
30add22d 2008 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2009 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 2010 u32 pp;
453c5420 2011 u32 pp_ctrl_reg;
9934c132 2012
9f0fb5be
VS		 2013 lockdep_assert_held(&dev_priv->pps_mutex);
2014
97af61f5 2015 if (!is_edp(intel_dp))
bd943159 2016 return;
99ea7127 2017
3936fcf4
VS		 2018 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2019 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2020
e7a89ace
VS		 2021 if (WARN(edp_have_panel_power(intel_dp),
2022 "eDP port %c panel power already on\n",
2023 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2024 return;
9934c132 2025
4be73780 2026 wait_panel_power_cycle(intel_dp);
37c6c9b0 2027
bf13e81b 2028 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2029 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 2030 if (IS_GEN5(dev)) {
2031 /* ILK workaround: disable reset around power sequence */
2032 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2033 I915_WRITE(pp_ctrl_reg, pp);
2034 POSTING_READ(pp_ctrl_reg);
05ce1a49 2035 }
37c6c9b0 2036
1c0ae80a 2037 pp |= POWER_TARGET_ON;
99ea7127
KP		 2038 if (!IS_GEN5(dev))
2039 pp |= PANEL_POWER_RESET;
2040
453c5420
JB		 2041 I915_WRITE(pp_ctrl_reg, pp);
2042 POSTING_READ(pp_ctrl_reg);
9934c132 2043
4be73780 2044 wait_panel_on(intel_dp);
dce56b3c 2045 intel_dp->last_power_on = jiffies;
9934c132 2046
05ce1a49
KP		 2047 if (IS_GEN5(dev)) {
2048 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2049 I915_WRITE(pp_ctrl_reg, pp);
2050 POSTING_READ(pp_ctrl_reg);
05ce1a49 2051 }
9f0fb5be 2052}
e39b999a 2053
9f0fb5be
VS		 2054void intel_edp_panel_on(struct intel_dp *intel_dp)
2055{
2056 if (!is_edp(intel_dp))
2057 return;
2058
2059 pps_lock(intel_dp);
2060 edp_panel_on(intel_dp);
773538e8 2061 pps_unlock(intel_dp);
9934c132
JB		 2062}
2063
9f0fb5be
VS		 2064
2065static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2066{
4e6e1a54
ID		 2067 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2068 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2069 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2070 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 2071 enum intel_display_power_domain power_domain;
99ea7127 2072 u32 pp;
453c5420 2073 u32 pp_ctrl_reg;
9934c132 2074
9f0fb5be
VS		 2075 lockdep_assert_held(&dev_priv->pps_mutex);
2076
97af61f5
KP		 2077 if (!is_edp(intel_dp))
2078 return;
37c6c9b0 2079
3936fcf4
VS		 2080 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2081 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2082
3936fcf4
VS		 2083 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2084 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2085
453c5420 2086 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2087 /* We need to switch off panel power _and_ force vdd, for otherwise some
2088 * panels get very unhappy and cease to work. */
b3064154
PJ		 2089 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2090 EDP_BLC_ENABLE);
453c5420 2091
bf13e81b 2092 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2093
849e39f5
PZ		 2094 intel_dp->want_panel_vdd = false;
2095
453c5420
JB		 2096 I915_WRITE(pp_ctrl_reg, pp);
2097 POSTING_READ(pp_ctrl_reg);
9934c132 2098
dce56b3c 2099 intel_dp->last_power_cycle = jiffies;
4be73780 2100 wait_panel_off(intel_dp);
849e39f5
PZ		 2101
2102 /* We got a reference when we enabled the VDD. */
25f78f58 2103 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2104 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2105}
e39b999a 2106
9f0fb5be
VS		 2107void intel_edp_panel_off(struct intel_dp *intel_dp)
2108{
2109 if (!is_edp(intel_dp))
2110 return;
e39b999a 2111
9f0fb5be
VS		 2112 pps_lock(intel_dp);
2113 edp_panel_off(intel_dp);
773538e8 2114 pps_unlock(intel_dp);
9934c132
JB		 2115}
2116
1250d107
JN		 2117/* Enable backlight in the panel power control. */
2118static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2119{
da63a9f2
PZ		 2120 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2121 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 u32 pp;
453c5420 2124 u32 pp_ctrl_reg;
32f9d658 2125
01cb9ea6
JB		 2126 /*
2127 * If we enable the backlight right away following a panel power
2128 * on, we may see slight flicker as the panel syncs with the eDP
2129 * link. So delay a bit to make sure the image is solid before
2130 * allowing it to appear.
2131 */
4be73780 2132 wait_backlight_on(intel_dp);
e39b999a 2133
773538e8 2134 pps_lock(intel_dp);
e39b999a 2135
453c5420 2136 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2137 pp |= EDP_BLC_ENABLE;
453c5420 2138
bf13e81b 2139 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2140
2141 I915_WRITE(pp_ctrl_reg, pp);
2142 POSTING_READ(pp_ctrl_reg);
e39b999a 2143
773538e8 2144 pps_unlock(intel_dp);
32f9d658
ZW		 2145}
2146
1250d107
JN		 2147/* Enable backlight PWM and backlight PP control. */
2148void intel_edp_backlight_on(struct intel_dp *intel_dp)
2149{
2150 if (!is_edp(intel_dp))
2151 return;
2152
2153 DRM_DEBUG_KMS("\n");
2154
2155 intel_panel_enable_backlight(intel_dp->attached_connector);
2156 _intel_edp_backlight_on(intel_dp);
2157}
2158
2159/* Disable backlight in the panel power control. */
2160static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2161{
30add22d 2162 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2163 struct drm_i915_private *dev_priv = dev->dev_private;
2164 u32 pp;
453c5420 2165 u32 pp_ctrl_reg;
32f9d658 2166
f01eca2e
KP		 2167 if (!is_edp(intel_dp))
2168 return;
2169
773538e8 2170 pps_lock(intel_dp);
e39b999a 2171
453c5420 2172 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2173 pp &= ~EDP_BLC_ENABLE;
453c5420 2174
bf13e81b 2175 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2176
2177 I915_WRITE(pp_ctrl_reg, pp);
2178 POSTING_READ(pp_ctrl_reg);
f7d2323c 2179
773538e8 2180 pps_unlock(intel_dp);
e39b999a
VS		 2181
2182 intel_dp->last_backlight_off = jiffies;
f7d2323c 2183 edp_wait_backlight_off(intel_dp);
1250d107 2184}
f7d2323c 2185
1250d107
JN		 2186/* Disable backlight PP control and backlight PWM. */
2187void intel_edp_backlight_off(struct intel_dp *intel_dp)
2188{
2189 if (!is_edp(intel_dp))
2190 return;
2191
2192 DRM_DEBUG_KMS("\n");
f7d2323c 2193
1250d107 2194 _intel_edp_backlight_off(intel_dp);
f7d2323c 2195 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2196}
a4fc5ed6 2197
73580fb7
JN		 2198/*
2199 * Hook for controlling the panel power control backlight through the bl_power
2200 * sysfs attribute. Take care to handle multiple calls.
2201 */
2202static void intel_edp_backlight_power(struct intel_connector *connector,
2203 bool enable)
2204{
2205 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2206 bool is_enabled;
2207
773538e8 2208 pps_lock(intel_dp);
e39b999a 2209 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2210 pps_unlock(intel_dp);
73580fb7
JN		 2211
2212 if (is_enabled == enable)
2213 return;
2214
23ba9373
JN		 2215 DRM_DEBUG_KMS("panel power control backlight %s\n",
2216 enable ? "enable" : "disable");
73580fb7
JN		 2217
2218 if (enable)
2219 _intel_edp_backlight_on(intel_dp);
2220 else
2221 _intel_edp_backlight_off(intel_dp);
2222}
2223
64e1077a
VS		 2224static const char *state_string(bool enabled)
2225{
2226 return enabled ? "on" : "off";
2227}
2228
2229static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2230{
2231 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2232 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2233 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2234
2235 I915_STATE_WARN(cur_state != state,
2236 "DP port %c state assertion failure (expected %s, current %s)\n",
2237 port_name(dig_port->port),
2238 state_string(state), state_string(cur_state));
2239}
2240#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2241
2242static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2243{
2244 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2245
2246 I915_STATE_WARN(cur_state != state,
2247 "eDP PLL state assertion failure (expected %s, current %s)\n",
2248 state_string(state), state_string(cur_state));
2249}
2250#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2251#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2252
2bd2ad64 2253static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2254{
da63a9f2 2255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2256 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2258
64e1077a
VS		 2259 assert_pipe_disabled(dev_priv, crtc->pipe);
2260 assert_dp_port_disabled(intel_dp);
2261 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2262
abfce949
VS		 2263 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2264 crtc->config->port_clock);
2265
2266 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2267
2268 if (crtc->config->port_clock == 162000)
2269 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2270 else
2271 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2272
2273 I915_WRITE(DP_A, intel_dp->DP);
2274 POSTING_READ(DP_A);
2275 udelay(500);
2276
0767935e 2277 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2278
0767935e 2279 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2280 POSTING_READ(DP_A);
2281 udelay(200);
d240f20f
JB		 2282}
2283
2bd2ad64 2284static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2285{
da63a9f2 2286 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2287 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2288 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2289
64e1077a
VS		 2290 assert_pipe_disabled(dev_priv, crtc->pipe);
2291 assert_dp_port_disabled(intel_dp);
2292 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2293
abfce949
VS		 2294 DRM_DEBUG_KMS("disabling eDP PLL\n");
2295
6fec7662 2296 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2297
6fec7662 2298 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2299 POSTING_READ(DP_A);
d240f20f
JB		 2300 udelay(200);
2301}
2302
c7ad3810 2303/* If the sink supports it, try to set the power state appropriately */
c19b0669 2304void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2305{
2306 int ret, i;
2307
2308 /* Should have a valid DPCD by this point */
2309 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2310 return;
2311
2312 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2313 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2314 DP_SET_POWER_D3);
c7ad3810
JB		 2315 } else {
2316 /*
2317 * When turning on, we need to retry for 1ms to give the sink
2318 * time to wake up.
2319 */
2320 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2321 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2322 DP_SET_POWER_D0);
c7ad3810
JB		 2323 if (ret == 1)
2324 break;
2325 msleep(1);
2326 }
2327 }
f9cac721
JN		 2328
2329 if (ret != 1)
2330 DRM_DEBUG_KMS("failed to %s sink power state\n",
2331 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2332}
2333
19d8fe15
DV		 2334static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2335 enum pipe *pipe)
d240f20f 2336{
19d8fe15 2337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2338 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2339 struct drm_device *dev = encoder->base.dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2341 enum intel_display_power_domain power_domain;
2342 u32 tmp;
2343
2344 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2345 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2346 return false;
2347
2348 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2349
2350 if (!(tmp & DP_PORT_EN))
2351 return false;
2352
39e5fa88 2353 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2354 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2355 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2356 enum pipe p;
19d8fe15 2357
adc289d7
VS		 2358 for_each_pipe(dev_priv, p) {
2359 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2360 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2361 *pipe = p;
19d8fe15
DV		 2362 return true;
2363 }
2364 }
19d8fe15 2365
4a0833ec
DV		 2366 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2367 intel_dp->output_reg);
39e5fa88
VS		 2368 } else if (IS_CHERRYVIEW(dev)) {
2369 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2370 } else {
2371 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2372 }
d240f20f 2373
19d8fe15
DV		 2374 return true;
2375}
d240f20f 2376
045ac3b5 2377static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2378 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2379{
2380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2381 u32 tmp, flags = 0;
63000ef6
XZ		 2382 struct drm_device *dev = encoder->base.dev;
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 enum port port = dp_to_dig_port(intel_dp)->port;
2385 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2386 int dotclock;
045ac3b5 2387
9ed109a7 2388 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2389
2390 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2391
39e5fa88 2392 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2393 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2394
2395 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2396 flags |= DRM_MODE_FLAG_PHSYNC;
2397 else
2398 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2399
b81e34c2 2400 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2401 flags |= DRM_MODE_FLAG_PVSYNC;
2402 else
2403 flags |= DRM_MODE_FLAG_NVSYNC;
2404 } else {
39e5fa88 2405 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2406 flags |= DRM_MODE_FLAG_PHSYNC;
2407 else
2408 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2409
39e5fa88 2410 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2411 flags |= DRM_MODE_FLAG_PVSYNC;
2412 else
2413 flags |= DRM_MODE_FLAG_NVSYNC;
2414 }
045ac3b5 2415
2d112de7 2416 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2417
8c875fca
VS		 2418 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2419 tmp & DP_COLOR_RANGE_16_235)
2420 pipe_config->limited_color_range = true;
2421
eb14cb74
VS		 2422 pipe_config->has_dp_encoder = true;
2423
90a6b7b0
VS		 2424 pipe_config->lane_count =
2425 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2426
eb14cb74
VS		 2427 intel_dp_get_m_n(crtc, pipe_config);
2428
18442d08 2429 if (port == PORT_A) {
b377e0df 2430 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2431 pipe_config->port_clock = 162000;
2432 else
2433 pipe_config->port_clock = 270000;
2434 }
18442d08
VS		 2435
2436 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2437 &pipe_config->dp_m_n);
2438
2439 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2440 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2441
2d112de7 2442 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2443
c6cd2ee2
JN		 2444 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2445 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2446 /*
2447 * This is a big fat ugly hack.
2448 *
2449 * Some machines in UEFI boot mode provide us a VBT that has 18
2450 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2451 * unknown we fail to light up. Yet the same BIOS boots up with
2452 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2453 * max, not what it tells us to use.
2454 *
2455 * Note: This will still be broken if the eDP panel is not lit
2456 * up by the BIOS, and thus we can't get the mode at module
2457 * load.
2458 */
2459 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2460 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2461 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2462 }
045ac3b5
JB		 2463}
2464
e8cb4558 2465static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2466{
e8cb4558 2467 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2468 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2469 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2470
6e3c9717 2471 if (crtc->config->has_audio)
495a5bb8 2472 intel_audio_codec_disable(encoder);
6cb49835 2473
b32c6f48
RV		 2474 if (HAS_PSR(dev) && !HAS_DDI(dev))
2475 intel_psr_disable(intel_dp);
2476
6cb49835
DV		 2477 /* Make sure the panel is off before trying to change the mode. But also
2478 * ensure that we have vdd while we switch off the panel. */
24f3e092 2479 intel_edp_panel_vdd_on(intel_dp);
4be73780 2480 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2481 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2482 intel_edp_panel_off(intel_dp);
3739850b 2483
08aff3fe
VS		 2484 /* disable the port before the pipe on g4x */
2485 if (INTEL_INFO(dev)->gen < 5)
3739850b 2486 intel_dp_link_down(intel_dp);
d240f20f
JB		 2487}
2488
08aff3fe 2489static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2490{
2bd2ad64 2491 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2492 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2493
49277c31 2494 intel_dp_link_down(intel_dp);
abfce949
VS		 2495
2496 /* Only ilk+ has port A */
08aff3fe
VS		 2497 if (port == PORT_A)
2498 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2499}
2500
2501static void vlv_post_disable_dp(struct intel_encoder *encoder)
2502{
2503 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2504
2505 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2506}
2507
a8f327fb
VS		 2508static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2509 bool reset)
580d3811 2510{
a8f327fb
VS		 2511 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2512 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2513 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2514 enum pipe pipe = crtc->pipe;
2515 uint32_t val;
580d3811 2516
a8f327fb
VS		 2517 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2518 if (reset)
2519 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2520 else
2521 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2522 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
580d3811 2523
a8f327fb
VS		 2524 if (crtc->config->lane_count > 2) {
2525 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2526 if (reset)
2527 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2528 else
2529 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2530 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2531 }
580d3811 2532
97fd4d5c 2533 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2534 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2535 if (reset)
2536 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2537 else
2538 val |= DPIO_PCS_CLK_SOFT_RESET;
97fd4d5c 2539 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2540
a8f327fb 2541 if (crtc->config->lane_count > 2) {
e0fce78f
VS		 2542 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2543 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2544 if (reset)
2545 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2546 else
2547 val |= DPIO_PCS_CLK_SOFT_RESET;
e0fce78f
VS		 2548 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2549 }
a8f327fb 2550}
97fd4d5c 2551
a8f327fb
VS		 2552static void chv_post_disable_dp(struct intel_encoder *encoder)
2553{
2554 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2555 struct drm_device *dev = encoder->base.dev;
2556 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2557
a8f327fb
VS		 2558 intel_dp_link_down(intel_dp);
2559
2560 mutex_lock(&dev_priv->sb_lock);
2561
2562 /* Assert data lane reset */
2563 chv_data_lane_soft_reset(encoder, true);
580d3811 2564
a580516d 2565 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2566}
2567
7b13b58a
VS		 2568static void
2569_intel_dp_set_link_train(struct intel_dp *intel_dp,
2570 uint32_t *DP,
2571 uint8_t dp_train_pat)
2572{
2573 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2574 struct drm_device *dev = intel_dig_port->base.base.dev;
2575 struct drm_i915_private *dev_priv = dev->dev_private;
2576 enum port port = intel_dig_port->port;
2577
2578 if (HAS_DDI(dev)) {
2579 uint32_t temp = I915_READ(DP_TP_CTL(port));
2580
2581 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2582 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2583 else
2584 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2585
2586 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2587 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2588 case DP_TRAINING_PATTERN_DISABLE:
2589 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2590
2591 break;
2592 case DP_TRAINING_PATTERN_1:
2593 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2594 break;
2595 case DP_TRAINING_PATTERN_2:
2596 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2597 break;
2598 case DP_TRAINING_PATTERN_3:
2599 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2600 break;
2601 }
2602 I915_WRITE(DP_TP_CTL(port), temp);
2603
39e5fa88
VS		 2604 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2605 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2606 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2607
2608 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2609 case DP_TRAINING_PATTERN_DISABLE:
2610 *DP |= DP_LINK_TRAIN_OFF_CPT;
2611 break;
2612 case DP_TRAINING_PATTERN_1:
2613 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2614 break;
2615 case DP_TRAINING_PATTERN_2:
2616 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2617 break;
2618 case DP_TRAINING_PATTERN_3:
2619 DRM_ERROR("DP training pattern 3 not supported\n");
2620 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2621 break;
2622 }
2623
2624 } else {
2625 if (IS_CHERRYVIEW(dev))
2626 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2627 else
2628 *DP &= ~DP_LINK_TRAIN_MASK;
2629
2630 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2631 case DP_TRAINING_PATTERN_DISABLE:
2632 *DP |= DP_LINK_TRAIN_OFF;
2633 break;
2634 case DP_TRAINING_PATTERN_1:
2635 *DP |= DP_LINK_TRAIN_PAT_1;
2636 break;
2637 case DP_TRAINING_PATTERN_2:
2638 *DP |= DP_LINK_TRAIN_PAT_2;
2639 break;
2640 case DP_TRAINING_PATTERN_3:
2641 if (IS_CHERRYVIEW(dev)) {
2642 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2643 } else {
2644 DRM_ERROR("DP training pattern 3 not supported\n");
2645 *DP |= DP_LINK_TRAIN_PAT_2;
2646 }
2647 break;
2648 }
2649 }
2650}
2651
2652static void intel_dp_enable_port(struct intel_dp *intel_dp)
2653{
2654 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2655 struct drm_i915_private *dev_priv = dev->dev_private;
6fec7662
VS		 2656 struct intel_crtc *crtc =
2657 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2658
7b13b58a
VS		 2659 /* enable with pattern 1 (as per spec) */
2660 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2661 DP_TRAINING_PATTERN_1);
2662
2663 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2664 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2665
2666 /*
2667 * Magic for VLV/CHV. We _must_ first set up the register
2668 * without actually enabling the port, and then do another
2669 * write to enable the port. Otherwise link training will
2670 * fail when the power sequencer is freshly used for this port.
2671 */
2672 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2673 if (crtc->config->has_audio)
2674 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2675
2676 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2677 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2678}
2679
e8cb4558 2680static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2681{
e8cb4558
DV		 2682 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2683 struct drm_device *dev = encoder->base.dev;
2684 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2685 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2686 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15
VS		 2687 enum port port = dp_to_dig_port(intel_dp)->port;
2688 enum pipe pipe = crtc->pipe;
5d613501 2689
0c33d8d7
DV		 2690 if (WARN_ON(dp_reg & DP_PORT_EN))
2691 return;
5d613501 2692
093e3f13
VS		 2693 pps_lock(intel_dp);
2694
2695 if (IS_VALLEYVIEW(dev))
2696 vlv_init_panel_power_sequencer(intel_dp);
2697
7b13b58a 2698 intel_dp_enable_port(intel_dp);
093e3f13 2699
d6fbdd15
VS		 2700 if (port == PORT_A && IS_GEN5(dev_priv)) {
2701 /*
2702 * Underrun reporting for the other pipe was disabled in
2703 * g4x_pre_enable_dp(). The eDP PLL and port have now been
2704 * enabled, so it's now safe to re-enable underrun reporting.
2705 */
2706 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2707 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2708 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2709 }
2710
093e3f13
VS		 2711 edp_panel_vdd_on(intel_dp);
2712 edp_panel_on(intel_dp);
2713 edp_panel_vdd_off(intel_dp, true);
2714
2715 pps_unlock(intel_dp);
2716
e0fce78f
VS		 2717 if (IS_VALLEYVIEW(dev)) {
2718 unsigned int lane_mask = 0x0;
2719
2720 if (IS_CHERRYVIEW(dev))
2721 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2722
9b6de0a1
VS		 2723 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2724 lane_mask);
e0fce78f 2725 }
61234fa5 2726
f01eca2e 2727 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2728 intel_dp_start_link_train(intel_dp);
3ab9c637 2729 intel_dp_stop_link_train(intel_dp);
c1dec79a 2730
6e3c9717 2731 if (crtc->config->has_audio) {
c1dec79a 2732 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2733 pipe_name(pipe));
c1dec79a
JN		 2734 intel_audio_codec_enable(encoder);
2735 }
ab1f90f9 2736}
89b667f8 2737
ecff4f3b
JN		 2738static void g4x_enable_dp(struct intel_encoder *encoder)
2739{
828f5c6e
JN		 2740 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2741
ecff4f3b 2742 intel_enable_dp(encoder);
4be73780 2743 intel_edp_backlight_on(intel_dp);
ab1f90f9 2744}
89b667f8 2745
ab1f90f9
JN		 2746static void vlv_enable_dp(struct intel_encoder *encoder)
2747{
828f5c6e
JN		 2748 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2749
4be73780 2750 intel_edp_backlight_on(intel_dp);
b32c6f48 2751 intel_psr_enable(intel_dp);
d240f20f
JB		 2752}
2753
ecff4f3b 2754static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9 2755{
d6fbdd15 2756 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ab1f90f9 2757 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15
VS		 2758 enum port port = dp_to_dig_port(intel_dp)->port;
2759 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
ab1f90f9 2760
8ac33ed3
DV		 2761 intel_dp_prepare(encoder);
2762
d6fbdd15
VS		 2763 if (port == PORT_A && IS_GEN5(dev_priv)) {
2764 /*
2765 * We get FIFO underruns on the other pipe when
2766 * enabling the CPU eDP PLL, and when enabling CPU
2767 * eDP port. We could potentially avoid the PLL
2768 * underrun with a vblank wait just prior to enabling
2769 * the PLL, but that doesn't appear to help the port
2770 * enable case. Just sweep it all under the rug.
2771 */
2772 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2773 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2774 }
2775
d41f1efb 2776 /* Only ilk+ has port A */
abfce949 2777 if (port == PORT_A)
ab1f90f9
JN		 2778 ironlake_edp_pll_on(intel_dp);
2779}
2780
83b84597
VS		 2781static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2782{
2783 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2784 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2785 enum pipe pipe = intel_dp->pps_pipe;
2786 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2787
2788 edp_panel_vdd_off_sync(intel_dp);
2789
2790 /*
2791 * VLV seems to get confused when multiple power seqeuencers
2792 * have the same port selected (even if only one has power/vdd
2793 * enabled). The failure manifests as vlv_wait_port_ready() failing
2794 * CHV on the other hand doesn't seem to mind having the same port
2795 * selected in multiple power seqeuencers, but let's clear the
2796 * port select always when logically disconnecting a power sequencer
2797 * from a port.
2798 */
2799 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2800 pipe_name(pipe), port_name(intel_dig_port->port));
2801 I915_WRITE(pp_on_reg, 0);
2802 POSTING_READ(pp_on_reg);
2803
2804 intel_dp->pps_pipe = INVALID_PIPE;
2805}
2806
a4a5d2f8
VS		 2807static void vlv_steal_power_sequencer(struct drm_device *dev,
2808 enum pipe pipe)
2809{
2810 struct drm_i915_private *dev_priv = dev->dev_private;
2811 struct intel_encoder *encoder;
2812
2813 lockdep_assert_held(&dev_priv->pps_mutex);
2814
ac3c12e4
VS		 2815 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2816 return;
2817
a4a5d2f8
VS		 2818 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2819 base.head) {
2820 struct intel_dp *intel_dp;
773538e8 2821 enum port port;
a4a5d2f8
VS		 2822
2823 if (encoder->type != INTEL_OUTPUT_EDP)
2824 continue;
2825
2826 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2827 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2828
2829 if (intel_dp->pps_pipe != pipe)
2830 continue;
2831
2832 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2833 pipe_name(pipe), port_name(port));
a4a5d2f8 2834
e02f9a06 2835 WARN(encoder->base.crtc,
034e43c6
VS		 2836 "stealing pipe %c power sequencer from active eDP port %c\n",
2837 pipe_name(pipe), port_name(port));
a4a5d2f8 2838
a4a5d2f8 2839 /* make sure vdd is off before we steal it */
83b84597 2840 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2841 }
2842}
2843
2844static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2845{
2846 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2847 struct intel_encoder *encoder = &intel_dig_port->base;
2848 struct drm_device *dev = encoder->base.dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2851
2852 lockdep_assert_held(&dev_priv->pps_mutex);
2853
093e3f13
VS		 2854 if (!is_edp(intel_dp))
2855 return;
2856
a4a5d2f8
VS		 2857 if (intel_dp->pps_pipe == crtc->pipe)
2858 return;
2859
2860 /*
2861 * If another power sequencer was being used on this
2862 * port previously make sure to turn off vdd there while
2863 * we still have control of it.
2864 */
2865 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2866 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2867
2868 /*
2869 * We may be stealing the power
2870 * sequencer from another port.
2871 */
2872 vlv_steal_power_sequencer(dev, crtc->pipe);
2873
2874 /* now it's all ours */
2875 intel_dp->pps_pipe = crtc->pipe;
2876
2877 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2878 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2879
2880 /* init power sequencer on this pipe and port */
36b5f425
VS		 2881 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2882 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2883}
2884
ab1f90f9 2885static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2886{
2bd2ad64 2887 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2888 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2889 struct drm_device *dev = encoder->base.dev;
89b667f8 2890 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2891 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2892 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2893 int pipe = intel_crtc->pipe;
2894 u32 val;
a4fc5ed6 2895
a580516d 2896 mutex_lock(&dev_priv->sb_lock);
89b667f8 2897
ab3c759a 2898 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2899 val = 0;
2900 if (pipe)
2901 val |= (1<<21);
2902 else
2903 val &= ~(1<<21);
2904 val |= 0x001000c4;
ab3c759a
CML		 2905 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2906 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2907 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2908
a580516d 2909 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2910
2911 intel_enable_dp(encoder);
89b667f8
JB		 2912}
2913
ecff4f3b 2914static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2915{
2916 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2917 struct drm_device *dev = encoder->base.dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2919 struct intel_crtc *intel_crtc =
2920 to_intel_crtc(encoder->base.crtc);
e4607fcf 2921 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2922 int pipe = intel_crtc->pipe;
89b667f8 2923
8ac33ed3
DV		 2924 intel_dp_prepare(encoder);
2925
89b667f8 2926 /* Program Tx lane resets to default */
a580516d 2927 mutex_lock(&dev_priv->sb_lock);
ab3c759a 2928 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2929 DPIO_PCS_TX_LANE2_RESET |
2930 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2931 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2932 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2933 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2934 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2935 DPIO_PCS_CLK_SOFT_RESET);
2936
2937 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2938 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2939 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2940 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
a580516d 2941 mutex_unlock(&dev_priv->sb_lock);
a4fc5ed6
KP		 2942}
2943
e4a1d846
CML		 2944static void chv_pre_enable_dp(struct intel_encoder *encoder)
2945{
2946 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2947 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2948 struct drm_device *dev = encoder->base.dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2950 struct intel_crtc *intel_crtc =
2951 to_intel_crtc(encoder->base.crtc);
2952 enum dpio_channel ch = vlv_dport_to_channel(dport);
2953 int pipe = intel_crtc->pipe;
2e523e98 2954 int data, i, stagger;
949c1d43 2955 u32 val;
e4a1d846 2956
a580516d 2957 mutex_lock(&dev_priv->sb_lock);
949c1d43 2958
570e2a74
VS		 2959 /* allow hardware to manage TX FIFO reset source */
2960 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2961 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2962 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2963
e0fce78f
VS		 2964 if (intel_crtc->config->lane_count > 2) {
2965 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2966 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2967 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2968 }
570e2a74 2969
949c1d43 2970 /* Program Tx lane latency optimal setting*/
e0fce78f 2971 for (i = 0; i < intel_crtc->config->lane_count; i++) {
e4a1d846 2972 /* Set the upar bit */
e0fce78f
VS		 2973 if (intel_crtc->config->lane_count == 1)
2974 data = 0x0;
2975 else
2976 data = (i == 1) ? 0x0 : 0x1;
e4a1d846
CML		 2977 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2978 data << DPIO_UPAR_SHIFT);
2979 }
2980
2981 /* Data lane stagger programming */
2e523e98
VS		 2982 if (intel_crtc->config->port_clock > 270000)
2983 stagger = 0x18;
2984 else if (intel_crtc->config->port_clock > 135000)
2985 stagger = 0xd;
2986 else if (intel_crtc->config->port_clock > 67500)
2987 stagger = 0x7;
2988 else if (intel_crtc->config->port_clock > 33750)
2989 stagger = 0x4;
2990 else
2991 stagger = 0x2;
2992
2993 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2994 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2995 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2996
e0fce78f
VS		 2997 if (intel_crtc->config->lane_count > 2) {
2998 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2999 val |= DPIO_TX2_STAGGER_MASK(0x1f);
3000 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
3001 }
2e523e98
VS		 3002
3003 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
3004 DPIO_LANESTAGGER_STRAP(stagger) |
3005 DPIO_LANESTAGGER_STRAP_OVRD |
3006 DPIO_TX1_STAGGER_MASK(0x1f) |
3007 DPIO_TX1_STAGGER_MULT(6) |
3008 DPIO_TX2_STAGGER_MULT(0));
3009
e0fce78f
VS		 3010 if (intel_crtc->config->lane_count > 2) {
3011 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
3012 DPIO_LANESTAGGER_STRAP(stagger) |
3013 DPIO_LANESTAGGER_STRAP_OVRD |
3014 DPIO_TX1_STAGGER_MASK(0x1f) |
3015 DPIO_TX1_STAGGER_MULT(7) |
3016 DPIO_TX2_STAGGER_MULT(5));
3017 }
e4a1d846 3018
a8f327fb
VS		 3019 /* Deassert data lane reset */
3020 chv_data_lane_soft_reset(encoder, false);
3021
a580516d 3022 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 3023
e4a1d846 3024 intel_enable_dp(encoder);
b0b33846
VS		 3025
3026 /* Second common lane will stay alive on its own now */
3027 if (dport->release_cl2_override) {
3028 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
3029 dport->release_cl2_override = false;
3030 }
e4a1d846
CML		 3031}
3032
9197c88b
VS		 3033static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
3034{
3035 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
3036 struct drm_device *dev = encoder->base.dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc =
3039 to_intel_crtc(encoder->base.crtc);
3040 enum dpio_channel ch = vlv_dport_to_channel(dport);
3041 enum pipe pipe = intel_crtc->pipe;
e0fce78f
VS		 3042 unsigned int lane_mask =
3043 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
9197c88b
VS		 3044 u32 val;
3045
625695f8
VS		 3046 intel_dp_prepare(encoder);
3047
b0b33846
VS		 3048 /*
3049 * Must trick the second common lane into life.
3050 * Otherwise we can't even access the PLL.
3051 */
3052 if (ch == DPIO_CH0 && pipe == PIPE_B)
3053 dport->release_cl2_override =
3054 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
3055
e0fce78f
VS		 3056 chv_phy_powergate_lanes(encoder, true, lane_mask);
3057
a580516d 3058 mutex_lock(&dev_priv->sb_lock);
9197c88b 3059
a8f327fb
VS		 3060 /* Assert data lane reset */
3061 chv_data_lane_soft_reset(encoder, true);
3062
b9e5ac3c
VS		 3063 /* program left/right clock distribution */
3064 if (pipe != PIPE_B) {
3065 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3066 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3067 if (ch == DPIO_CH0)
3068 val |= CHV_BUFLEFTENA1_FORCE;
3069 if (ch == DPIO_CH1)
3070 val |= CHV_BUFRIGHTENA1_FORCE;
3071 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3072 } else {
3073 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3074 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3075 if (ch == DPIO_CH0)
3076 val |= CHV_BUFLEFTENA2_FORCE;
3077 if (ch == DPIO_CH1)
3078 val |= CHV_BUFRIGHTENA2_FORCE;
3079 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3080 }
3081
9197c88b
VS		 3082 /* program clock channel usage */
3083 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3084 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3085 if (pipe != PIPE_B)
3086 val &= ~CHV_PCS_USEDCLKCHANNEL;
3087 else
3088 val |= CHV_PCS_USEDCLKCHANNEL;
3089 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3090
e0fce78f
VS		 3091 if (intel_crtc->config->lane_count > 2) {
3092 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3093 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3094 if (pipe != PIPE_B)
3095 val &= ~CHV_PCS_USEDCLKCHANNEL;
3096 else
3097 val |= CHV_PCS_USEDCLKCHANNEL;
3098 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3099 }
9197c88b
VS		 3100
3101 /*
3102 * This a a bit weird since generally CL
3103 * matches the pipe, but here we need to
3104 * pick the CL based on the port.
3105 */
3106 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3107 if (pipe != PIPE_B)
3108 val &= ~CHV_CMN_USEDCLKCHANNEL;
3109 else
3110 val |= CHV_CMN_USEDCLKCHANNEL;
3111 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3112
a580516d 3113 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 3114}
3115
d6db995f
VS		 3116static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3117{
3118 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3119 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3120 u32 val;
3121
3122 mutex_lock(&dev_priv->sb_lock);
3123
3124 /* disable left/right clock distribution */
3125 if (pipe != PIPE_B) {
3126 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3127 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3128 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3129 } else {
3130 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3131 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3132 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3133 }
3134
3135 mutex_unlock(&dev_priv->sb_lock);
e0fce78f 3136
b0b33846
VS		 3137 /*
3138 * Leave the power down bit cleared for at least one
3139 * lane so that chv_powergate_phy_ch() will power
3140 * on something when the channel is otherwise unused.
3141 * When the port is off and the override is removed
3142 * the lanes power down anyway, so otherwise it doesn't
3143 * really matter what the state of power down bits is
3144 * after this.
3145 */
e0fce78f 3146 chv_phy_powergate_lanes(encoder, false, 0x0);
d6db995f
VS		 3147}
3148
a4fc5ed6 3149/*
df0c237d
JB		 3150 * Native read with retry for link status and receiver capability reads for
3151 * cases where the sink may still be asleep.
9d1a1031
JN		 3152 *
3153 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3154 * supposed to retry 3 times per the spec.
a4fc5ed6 3155 */
9d1a1031
JN		 3156static ssize_t
3157intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3158 void *buffer, size_t size)
a4fc5ed6 3159{
9d1a1031
JN		 3160 ssize_t ret;
3161 int i;
61da5fab 3162
f6a19066
VS		 3163 /*
3164 * Sometime we just get the same incorrect byte repeated
3165 * over the entire buffer. Doing just one throw away read
3166 * initially seems to "solve" it.
3167 */
3168 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3169
61da5fab 3170 for (i = 0; i < 3; i++) {
9d1a1031
JN		 3171 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3172 if (ret == size)
3173 return ret;
61da5fab
JB		 3174 msleep(1);
3175 }
a4fc5ed6 3176
9d1a1031 3177 return ret;
a4fc5ed6
KP		 3178}
3179
3180/*
3181 * Fetch AUX CH registers 0x202 - 0x207 which contain
3182 * link status information
3183 */
94223d04 3184bool
93f62dad 3185intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 3186{
9d1a1031
JN		 3187 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3188 DP_LANE0_1_STATUS,
3189 link_status,
3190 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 3191}
3192
1100244e 3193/* These are source-specific values. */
94223d04 3194uint8_t
1a2eb460 3195intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 3196{
30add22d 3197 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 3198 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 3199 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3200
9314726b
VK		 3201 if (IS_BROXTON(dev))
3202 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3203 else if (INTEL_INFO(dev)->gen >= 9) {
9e458034 3204 if (dev_priv->edp_low_vswing && port == PORT_A)
7ad14a29 3205 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 3206 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 3207 } else if (IS_VALLEYVIEW(dev))
bd60018a 3208 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 3209 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 3210 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 3211 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 3212 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 3213 else
bd60018a 3214 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3215}
3216
94223d04 3217uint8_t
1a2eb460
KP		 3218intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3219{
30add22d 3220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3221 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3222
5a9d1f1a
DL		 3223 if (INTEL_INFO(dev)->gen >= 9) {
3224 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3225 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3226 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3227 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3228 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3230 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3231 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3232 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3233 default:
3234 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3235 }
3236 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3237 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3239 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3240 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3241 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3243 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3245 default:
bd60018a 3246 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3247 }
e2fa6fba
P		 3248 } else if (IS_VALLEYVIEW(dev)) {
3249 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3250 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3251 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3253 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3254 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3255 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3257 default:
bd60018a 3258 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3259 }
bc7d38a4 3260 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3261 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3262 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3263 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3265 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3266 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3267 default:
bd60018a 3268 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3269 }
3270 } else {
3271 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3273 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3274 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3275 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3277 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3279 default:
bd60018a 3280 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3281 }
a4fc5ed6
KP		 3282 }
3283}
3284
5829975c 3285static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3286{
3287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3290 struct intel_crtc *intel_crtc =
3291 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3292 unsigned long demph_reg_value, preemph_reg_value,
3293 uniqtranscale_reg_value;
3294 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3295 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3296 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3297
3298 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3299 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3300 preemph_reg_value = 0x0004000;
3301 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3303 demph_reg_value = 0x2B405555;
3304 uniqtranscale_reg_value = 0x552AB83A;
3305 break;
bd60018a 3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3307 demph_reg_value = 0x2B404040;
3308 uniqtranscale_reg_value = 0x5548B83A;
3309 break;
bd60018a 3310 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3311 demph_reg_value = 0x2B245555;
3312 uniqtranscale_reg_value = 0x5560B83A;
3313 break;
bd60018a 3314 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3315 demph_reg_value = 0x2B405555;
3316 uniqtranscale_reg_value = 0x5598DA3A;
3317 break;
3318 default:
3319 return 0;
3320 }
3321 break;
bd60018a 3322 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3323 preemph_reg_value = 0x0002000;
3324 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3326 demph_reg_value = 0x2B404040;
3327 uniqtranscale_reg_value = 0x5552B83A;
3328 break;
bd60018a 3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3330 demph_reg_value = 0x2B404848;
3331 uniqtranscale_reg_value = 0x5580B83A;
3332 break;
bd60018a 3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3334 demph_reg_value = 0x2B404040;
3335 uniqtranscale_reg_value = 0x55ADDA3A;
3336 break;
3337 default:
3338 return 0;
3339 }
3340 break;
bd60018a 3341 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3342 preemph_reg_value = 0x0000000;
3343 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3344 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3345 demph_reg_value = 0x2B305555;
3346 uniqtranscale_reg_value = 0x5570B83A;
3347 break;
bd60018a 3348 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3349 demph_reg_value = 0x2B2B4040;
3350 uniqtranscale_reg_value = 0x55ADDA3A;
3351 break;
3352 default:
3353 return 0;
3354 }
3355 break;
bd60018a 3356 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3357 preemph_reg_value = 0x0006000;
3358 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3360 demph_reg_value = 0x1B405555;
3361 uniqtranscale_reg_value = 0x55ADDA3A;
3362 break;
3363 default:
3364 return 0;
3365 }
3366 break;
3367 default:
3368 return 0;
3369 }
3370
a580516d 3371 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 3372 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3373 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3374 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3375 uniqtranscale_reg_value);
ab3c759a
CML		 3376 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3377 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3378 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3379 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
a580516d 3380 mutex_unlock(&dev_priv->sb_lock);
e2fa6fba
P		 3381
3382 return 0;
3383}
3384
67fa24b4
VS		 3385static bool chv_need_uniq_trans_scale(uint8_t train_set)
3386{
3387 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3388 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3389}
3390
5829975c 3391static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3392{
3393 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3396 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3397 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3398 uint8_t train_set = intel_dp->train_set[0];
3399 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3400 enum pipe pipe = intel_crtc->pipe;
3401 int i;
e4a1d846
CML		 3402
3403 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3404 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3405 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3406 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3407 deemph_reg_value = 128;
3408 margin_reg_value = 52;
3409 break;
bd60018a 3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3411 deemph_reg_value = 128;
3412 margin_reg_value = 77;
3413 break;
bd60018a 3414 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3415 deemph_reg_value = 128;
3416 margin_reg_value = 102;
3417 break;
bd60018a 3418 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3419 deemph_reg_value = 128;
3420 margin_reg_value = 154;
3421 /* FIXME extra to set for 1200 */
3422 break;
3423 default:
3424 return 0;
3425 }
3426 break;
bd60018a 3427 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3428 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3430 deemph_reg_value = 85;
3431 margin_reg_value = 78;
3432 break;
bd60018a 3433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3434 deemph_reg_value = 85;
3435 margin_reg_value = 116;
3436 break;
bd60018a 3437 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3438 deemph_reg_value = 85;
3439 margin_reg_value = 154;
3440 break;
3441 default:
3442 return 0;
3443 }
3444 break;
bd60018a 3445 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3446 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3448 deemph_reg_value = 64;
3449 margin_reg_value = 104;
3450 break;
bd60018a 3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3452 deemph_reg_value = 64;
3453 margin_reg_value = 154;
3454 break;
3455 default:
3456 return 0;
3457 }
3458 break;
bd60018a 3459 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3460 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3462 deemph_reg_value = 43;
3463 margin_reg_value = 154;
3464 break;
3465 default:
3466 return 0;
3467 }
3468 break;
3469 default:
3470 return 0;
3471 }
3472
a580516d 3473 mutex_lock(&dev_priv->sb_lock);
e4a1d846
CML		 3474
3475 /* Clear calc init */
1966e59e
VS		 3476 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3477 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3478 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3479 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3480 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3481
e0fce78f
VS		 3482 if (intel_crtc->config->lane_count > 2) {
3483 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3484 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3485 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3486 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3487 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3488 }
e4a1d846 3489
a02ef3c7
VS		 3490 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3491 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3492 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3493 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3494
e0fce78f
VS		 3495 if (intel_crtc->config->lane_count > 2) {
3496 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3497 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3498 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3499 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3500 }
a02ef3c7 3501
e4a1d846 3502 /* Program swing deemph */
e0fce78f 3503 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db
VS		 3504 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3505 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3506 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3507 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3508 }
e4a1d846
CML		 3509
3510 /* Program swing margin */
e0fce78f 3511 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3512 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
67fa24b4 3513
1fb44505
VS		 3514 val &= ~DPIO_SWING_MARGIN000_MASK;
3515 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
67fa24b4
VS		 3516
3517 /*
3518 * Supposedly this value shouldn't matter when unique transition
3519 * scale is disabled, but in fact it does matter. Let's just
3520 * always program the same value and hope it's OK.
3521 */
3522 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3523 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3524
f72df8db
VS		 3525 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3526 }
e4a1d846 3527
67fa24b4
VS		 3528 /*
3529 * The document said it needs to set bit 27 for ch0 and bit 26
3530 * for ch1. Might be a typo in the doc.
3531 * For now, for this unique transition scale selection, set bit
3532 * 27 for ch0 and ch1.
3533 */
e0fce78f 3534 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3535 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
67fa24b4 3536 if (chv_need_uniq_trans_scale(train_set))
f72df8db 3537 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
67fa24b4
VS		 3538 else
3539 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3540 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
e4a1d846
CML		 3541 }
3542
3543 /* Start swing calculation */
1966e59e
VS		 3544 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3545 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3546 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3547
e0fce78f
VS		 3548 if (intel_crtc->config->lane_count > 2) {
3549 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3550 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3551 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3552 }
e4a1d846 3553
a580516d 3554 mutex_unlock(&dev_priv->sb_lock);
e4a1d846
CML		 3555
3556 return 0;
3557}
3558
a4fc5ed6 3559static uint32_t
5829975c 3560gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3561{
3cf2efb1 3562 uint32_t signal_levels = 0;
a4fc5ed6 3563
3cf2efb1 3564 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3565 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3566 default:
3567 signal_levels |= DP_VOLTAGE_0_4;
3568 break;
bd60018a 3569 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3570 signal_levels |= DP_VOLTAGE_0_6;
3571 break;
bd60018a 3572 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3573 signal_levels |= DP_VOLTAGE_0_8;
3574 break;
bd60018a 3575 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3576 signal_levels |= DP_VOLTAGE_1_2;
3577 break;
3578 }
3cf2efb1 3579 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3580 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3581 default:
3582 signal_levels |= DP_PRE_EMPHASIS_0;
3583 break;
bd60018a 3584 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3585 signal_levels |= DP_PRE_EMPHASIS_3_5;
3586 break;
bd60018a 3587 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3588 signal_levels |= DP_PRE_EMPHASIS_6;
3589 break;
bd60018a 3590 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3591 signal_levels |= DP_PRE_EMPHASIS_9_5;
3592 break;
3593 }
3594 return signal_levels;
3595}
3596
e3421a18
ZW		 3597/* Gen6's DP voltage swing and pre-emphasis control */
3598static uint32_t
5829975c 3599gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3600{
3c5a62b5
YL		 3601 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3602 DP_TRAIN_PRE_EMPHASIS_MASK);
3603 switch (signal_levels) {
bd60018a
SJ		 3604 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3605 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3606 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3607 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3608 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3609 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3610 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3611 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3612 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3613 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3614 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3615 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3616 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3617 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3618 default:
3c5a62b5
YL		 3619 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3620 "0x%x\n", signal_levels);
3621 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3622 }
3623}
3624
1a2eb460
KP		 3625/* Gen7's DP voltage swing and pre-emphasis control */
3626static uint32_t
5829975c 3627gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3628{
3629 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3630 DP_TRAIN_PRE_EMPHASIS_MASK);
3631 switch (signal_levels) {
bd60018a 3632 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3633 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3634 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3635 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3636 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3637 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3638
bd60018a 3639 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3640 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3641 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3642 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3643
bd60018a 3644 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3645 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3646 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3647 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3648
3649 default:
3650 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3651 "0x%x\n", signal_levels);
3652 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3653 }
3654}
3655
94223d04 3656void
f4eb692e 3657intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3658{
3659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3660 enum port port = intel_dig_port->port;
f0a3424e 3661 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3662 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3663 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3664 uint8_t train_set = intel_dp->train_set[0];
3665
f8896f5d
DW		 3666 if (HAS_DDI(dev)) {
3667 signal_levels = ddi_signal_levels(intel_dp);
3668
3669 if (IS_BROXTON(dev))
3670 signal_levels = 0;
3671 else
3672 mask = DDI_BUF_EMP_MASK;
e4a1d846 3673 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3674 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3675 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3676 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3677 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3678 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3679 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3680 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3681 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3682 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3683 } else {
5829975c 3684 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3685 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3686 }
3687
96fb9f9b
VK		 3688 if (mask)
3689 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3690
3691 DRM_DEBUG_KMS("Using vswing level %d\n",
3692 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3693 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3694 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3695 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3696
f4eb692e 3697 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3698
3699 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3700 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3701}
3702
94223d04 3703void
e9c176d5
ACO		 3704intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3705 uint8_t dp_train_pat)
a4fc5ed6 3706{
174edf1f 3707 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3708 struct drm_i915_private *dev_priv =
3709 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3710
f4eb692e 3711 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3712
f4eb692e 3713 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3714 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3715}
3716
94223d04 3717void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3718{
3719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3720 struct drm_device *dev = intel_dig_port->base.base.dev;
3721 struct drm_i915_private *dev_priv = dev->dev_private;
3722 enum port port = intel_dig_port->port;
3723 uint32_t val;
3724
3725 if (!HAS_DDI(dev))
3726 return;
3727
3728 val = I915_READ(DP_TP_CTL(port));
3729 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3730 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3731 I915_WRITE(DP_TP_CTL(port), val);
3732
3733 /*
3734 * On PORT_A we can have only eDP in SST mode. There the only reason
3735 * we need to set idle transmission mode is to work around a HW issue
3736 * where we enable the pipe while not in idle link-training mode.
3737 * In this case there is requirement to wait for a minimum number of
3738 * idle patterns to be sent.
3739 */
3740 if (port == PORT_A)
3741 return;
3742
3743 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3744 1))
3745 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3746}
3747
a4fc5ed6 3748static void
ea5b213a 3749intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3750{
da63a9f2 3751 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3752 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3753 enum port port = intel_dig_port->port;
da63a9f2 3754 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3755 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3756 uint32_t DP = intel_dp->DP;
a4fc5ed6 3757
bc76e320 3758 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3759 return;
3760
0c33d8d7 3761 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3762 return;
3763
28c97730 3764 DRM_DEBUG_KMS("\n");
32f9d658 3765
39e5fa88
VS		 3766 if ((IS_GEN7(dev) && port == PORT_A) ||
3767 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3768 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3769 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3770 } else {
aad3d14d
VS		 3771 if (IS_CHERRYVIEW(dev))
3772 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3773 else
3774 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3775 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3776 }
1612c8bd 3777 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3778 POSTING_READ(intel_dp->output_reg);
5eb08b69 3779
1612c8bd
VS		 3780 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3781 I915_WRITE(intel_dp->output_reg, DP);
3782 POSTING_READ(intel_dp->output_reg);
3783
3784 /*
3785 * HW workaround for IBX, we need to move the port
3786 * to transcoder A after disabling it to allow the
3787 * matching HDMI port to be enabled on transcoder A.
3788 */
3789 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3790 /*
3791 * We get CPU/PCH FIFO underruns on the other pipe when
3792 * doing the workaround. Sweep them under the rug.
3793 */
3794 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3795 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3796
1612c8bd
VS		 3797 /* always enable with pattern 1 (as per spec) */
3798 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3799 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3800 I915_WRITE(intel_dp->output_reg, DP);
3801 POSTING_READ(intel_dp->output_reg);
3802
3803 DP &= ~DP_PORT_EN;
5bddd17f 3804 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3805 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3806
3807 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3808 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3809 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3810 }
3811
f01eca2e 3812 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3813
3814 intel_dp->DP = DP;
a4fc5ed6
KP		 3815}
3816
26d61aad
KP		 3817static bool
3818intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3819{
a031d709
RV		 3820 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3821 struct drm_device *dev = dig_port->base.base.dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3823 uint8_t rev;
a031d709 3824
9d1a1031
JN		 3825 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3826 sizeof(intel_dp->dpcd)) < 0)
edb39244 3827 return false; /* aux transfer failed */
92fd8fd1 3828
a8e98153 3829 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3830
edb39244
AJ		 3831 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3832 return false; /* DPCD not present */
3833
2293bb5c
SK		 3834 /* Check if the panel supports PSR */
3835 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3836 if (is_edp(intel_dp)) {
9d1a1031
JN		 3837 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3838 intel_dp->psr_dpcd,
3839 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3840 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3841 dev_priv->psr.sink_support = true;
50003939 3842 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3843 }
474d1ec4
SJ		 3844
3845 if (INTEL_INFO(dev)->gen >= 9 &&
3846 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3847 uint8_t frame_sync_cap;
3848
3849 dev_priv->psr.sink_support = true;
3850 intel_dp_dpcd_read_wake(&intel_dp->aux,
3851 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3852 &frame_sync_cap, 1);
3853 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3854 /* PSR2 needs frame sync as well */
3855 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3856 DRM_DEBUG_KMS("PSR2 %s on sink",
3857 dev_priv->psr.psr2_support ? "supported" : "not supported");
3858 }
50003939
JN		 3859 }
3860
bc5133d5 3861 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3862 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3863 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3864
fc0f8e25
SJ		 3865 /* Intermediate frequency support */
3866 if (is_edp(intel_dp) &&
3867 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3868 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3869 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3870 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3871 int i;
3872
fc0f8e25
SJ		 3873 intel_dp_dpcd_read_wake(&intel_dp->aux,
3874 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3875 sink_rates,
3876 sizeof(sink_rates));
ea2d8a42 3877
94ca719e
VS		 3878 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3879 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3880
3881 if (val == 0)
3882 break;
3883
af77b974
SJ		 3884 /* Value read is in kHz while drm clock is saved in deca-kHz */
3885 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3886 }
94ca719e 3887 intel_dp->num_sink_rates = i;
fc0f8e25 3888 }
0336400e
VS		 3889
3890 intel_dp_print_rates(intel_dp);
3891
edb39244
AJ		 3892 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3893 DP_DWN_STRM_PORT_PRESENT))
3894 return true; /* native DP sink */
3895
3896 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3897 return true; /* no per-port downstream info */
3898
9d1a1031
JN		 3899 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3900 intel_dp->downstream_ports,
3901 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3902 return false; /* downstream port status fetch failed */
3903
3904 return true;
92fd8fd1
KP		 3905}
3906
0d198328
AJ		 3907static void
3908intel_dp_probe_oui(struct intel_dp *intel_dp)
3909{
3910 u8 buf[3];
3911
3912 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3913 return;
3914
9d1a1031 3915 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3916 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3917 buf[0], buf[1], buf[2]);
3918
9d1a1031 3919 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3920 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3921 buf[0], buf[1], buf[2]);
3922}
3923
0e32b39c
DA		 3924static bool
3925intel_dp_probe_mst(struct intel_dp *intel_dp)
3926{
3927 u8 buf[1];
3928
3929 if (!intel_dp->can_mst)
3930 return false;
3931
3932 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3933 return false;
3934
0e32b39c
DA		 3935 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3936 if (buf[0] & DP_MST_CAP) {
3937 DRM_DEBUG_KMS("Sink is MST capable\n");
3938 intel_dp->is_mst = true;
3939 } else {
3940 DRM_DEBUG_KMS("Sink is not MST capable\n");
3941 intel_dp->is_mst = false;
3942 }
3943 }
0e32b39c
DA		 3944
3945 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3946 return intel_dp->is_mst;
3947}
3948
e5a1cab5 3949static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3950{
082dcc7c 3951 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3952 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3953 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3954 u8 buf;
e5a1cab5 3955 int ret = 0;
c6297843
RV		 3956 int count = 0;
3957 int attempts = 10;
d2e216d0 3958
082dcc7c
RV		 3959 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3960 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3961 ret = -EIO;
3962 goto out;
4373f0f2
PZ		 3963 }
3964
082dcc7c 3965 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3966 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3967 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3968 ret = -EIO;
3969 goto out;
3970 }
d2e216d0 3971
c6297843
RV		 3972 do {
3973 intel_wait_for_vblank(dev, intel_crtc->pipe);
3974
3975 if (drm_dp_dpcd_readb(&intel_dp->aux,
3976 DP_TEST_SINK_MISC, &buf) < 0) {
3977 ret = -EIO;
3978 goto out;
3979 }
3980 count = buf & DP_TEST_COUNT_MASK;
3981 } while (--attempts && count);
3982
3983 if (attempts == 0) {
3984 DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
3985 ret = -ETIMEDOUT;
3986 }
3987
e5a1cab5 3988 out:
082dcc7c 3989 hsw_enable_ips(intel_crtc);
e5a1cab5 3990 return ret;
082dcc7c
RV		 3991}
3992
3993static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3994{
3995 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3996 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3997 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3998 u8 buf;
e5a1cab5
RV		 3999 int ret;
4000
082dcc7c
RV		 4001 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4002 return -EIO;
4003
4004 if (!(buf & DP_TEST_CRC_SUPPORTED))
4005 return -ENOTTY;
4006
4007 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4008 return -EIO;
4009
6d8175da
RV		 4010 if (buf & DP_TEST_SINK_START) {
4011 ret = intel_dp_sink_crc_stop(intel_dp);
4012 if (ret)
4013 return ret;
4014 }
4015
082dcc7c 4016 hsw_disable_ips(intel_crtc);
1dda5f93 4017
9d1a1031 4018 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 4019 buf | DP_TEST_SINK_START) < 0) {
4020 hsw_enable_ips(intel_crtc);
4021 return -EIO;
4373f0f2
PZ		 4022 }
4023
d72f9d91 4024 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 4025 return 0;
4026}
4027
4028int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4029{
4030 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4031 struct drm_device *dev = dig_port->base.base.dev;
4032 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4033 u8 buf;
621d4c76 4034 int count, ret;
082dcc7c 4035 int attempts = 6;
082dcc7c
RV		 4036
4037 ret = intel_dp_sink_crc_start(intel_dp);
4038 if (ret)
4039 return ret;
4040
ad9dc91b 4041 do {
621d4c76
RV		 4042 intel_wait_for_vblank(dev, intel_crtc->pipe);
4043
1dda5f93 4044 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 4045 DP_TEST_SINK_MISC, &buf) < 0) {
4046 ret = -EIO;
afe0d67e 4047 goto stop;
4373f0f2 4048 }
621d4c76 4049 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 4050
7e38eeff 4051 } while (--attempts && count == 0);
ad9dc91b
RV		 4052
4053 if (attempts == 0) {
7e38eeff
RV		 4054 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4055 ret = -ETIMEDOUT;
4056 goto stop;
4057 }
4058
4059 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4060 ret = -EIO;
4061 goto stop;
ad9dc91b 4062 }
d2e216d0 4063
afe0d67e 4064stop:
082dcc7c 4065 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 4066 return ret;
d2e216d0
RV		 4067}
4068
a60f0e38
JB		 4069static bool
4070intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4071{
9d1a1031
JN		 4072 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4073 DP_DEVICE_SERVICE_IRQ_VECTOR,
4074 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4075}
4076
0e32b39c
DA		 4077static bool
4078intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4079{
4080 int ret;
4081
4082 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4083 DP_SINK_COUNT_ESI,
4084 sink_irq_vector, 14);
4085 if (ret != 14)
4086 return false;
4087
4088 return true;
4089}
4090
c5d5ab7a
TP		 4091static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4092{
4093 uint8_t test_result = DP_TEST_ACK;
4094 return test_result;
4095}
4096
4097static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4098{
4099 uint8_t test_result = DP_TEST_NAK;
4100 return test_result;
4101}
4102
4103static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4104{
c5d5ab7a 4105 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4106 struct intel_connector *intel_connector = intel_dp->attached_connector;
4107 struct drm_connector *connector = &intel_connector->base;
4108
4109 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4110 connector->edid_corrupt ||
559be30c
TP		 4111 intel_dp->aux.i2c_defer_count > 6) {
4112 /* Check EDID read for NACKs, DEFERs and corruption
4113 * (DP CTS 1.2 Core r1.1)
4114 * 4.2.2.4 : Failed EDID read, I2C_NAK
4115 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4116 * 4.2.2.6 : EDID corruption detected
4117 * Use failsafe mode for all cases
4118 */
4119 if (intel_dp->aux.i2c_nack_count > 0 ||
4120 intel_dp->aux.i2c_defer_count > 0)
4121 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4122 intel_dp->aux.i2c_nack_count,
4123 intel_dp->aux.i2c_defer_count);
4124 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4125 } else {
f79b468e
TS		 4126 struct edid *block = intel_connector->detect_edid;
4127
4128 /* We have to write the checksum
4129 * of the last block read
4130 */
4131 block += intel_connector->detect_edid->extensions;
4132
559be30c
TP		 4133 if (!drm_dp_dpcd_write(&intel_dp->aux,
4134 DP_TEST_EDID_CHECKSUM,
f79b468e 4135 &block->checksum,
5a1cc655 4136 1))
559be30c
TP		 4137 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4138
4139 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4140 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4141 }
4142
4143 /* Set test active flag here so userspace doesn't interrupt things */
4144 intel_dp->compliance_test_active = 1;
4145
c5d5ab7a
TP		 4146 return test_result;
4147}
4148
4149static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4150{
c5d5ab7a
TP		 4151 uint8_t test_result = DP_TEST_NAK;
4152 return test_result;
4153}
4154
4155static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4156{
4157 uint8_t response = DP_TEST_NAK;
4158 uint8_t rxdata = 0;
4159 int status = 0;
4160
c5d5ab7a
TP		 4161 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4162 if (status <= 0) {
4163 DRM_DEBUG_KMS("Could not read test request from sink\n");
4164 goto update_status;
4165 }
4166
4167 switch (rxdata) {
4168 case DP_TEST_LINK_TRAINING:
4169 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4170 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4171 response = intel_dp_autotest_link_training(intel_dp);
4172 break;
4173 case DP_TEST_LINK_VIDEO_PATTERN:
4174 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4175 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4176 response = intel_dp_autotest_video_pattern(intel_dp);
4177 break;
4178 case DP_TEST_LINK_EDID_READ:
4179 DRM_DEBUG_KMS("EDID test requested\n");
4180 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4181 response = intel_dp_autotest_edid(intel_dp);
4182 break;
4183 case DP_TEST_LINK_PHY_TEST_PATTERN:
4184 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4185 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4186 response = intel_dp_autotest_phy_pattern(intel_dp);
4187 break;
4188 default:
4189 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4190 break;
4191 }
4192
4193update_status:
4194 status = drm_dp_dpcd_write(&intel_dp->aux,
4195 DP_TEST_RESPONSE,
4196 &response, 1);
4197 if (status <= 0)
4198 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4199}
4200
0e32b39c
DA		 4201static int
4202intel_dp_check_mst_status(struct intel_dp *intel_dp)
4203{
4204 bool bret;
4205
4206 if (intel_dp->is_mst) {
4207 u8 esi[16] = { 0 };
4208 int ret = 0;
4209 int retry;
4210 bool handled;
4211 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4212go_again:
4213 if (bret == true) {
4214
4215 /* check link status - esi[10] = 0x200c */
90a6b7b0 4216 if (intel_dp->active_mst_links &&
901c2daf 4217 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 4218 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4219 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 4220 intel_dp_stop_link_train(intel_dp);
4221 }
4222
6f34cc39 4223 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4224 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4225
4226 if (handled) {
4227 for (retry = 0; retry < 3; retry++) {
4228 int wret;
4229 wret = drm_dp_dpcd_write(&intel_dp->aux,
4230 DP_SINK_COUNT_ESI+1,
4231 &esi[1], 3);
4232 if (wret == 3) {
4233 break;
4234 }
4235 }
4236
4237 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4238 if (bret == true) {
6f34cc39 4239 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4240 goto go_again;
4241 }
4242 } else
4243 ret = 0;
4244
4245 return ret;
4246 } else {
4247 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4248 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4249 intel_dp->is_mst = false;
4250 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4251 /* send a hotplug event */
4252 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4253 }
4254 }
4255 return -EINVAL;
4256}
4257
a4fc5ed6
KP		 4258/*
4259 * According to DP spec
4260 * 5.1.2:
4261 * 1. Read DPCD
4262 * 2. Configure link according to Receiver Capabilities
4263 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4264 * 4. Check link status on receipt of hot-plug interrupt
4265 */
a5146200 4266static void
ea5b213a 4267intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4268{
5b215bcf 4269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4270 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4271 u8 sink_irq_vector;
93f62dad 4272 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4273
5b215bcf
DA		 4274 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4275
4df6960e
SS		 4276 /*
4277 * Clearing compliance test variables to allow capturing
4278 * of values for next automated test request.
4279 */
4280 intel_dp->compliance_test_active = 0;
4281 intel_dp->compliance_test_type = 0;
4282 intel_dp->compliance_test_data = 0;
4283
e02f9a06 4284 if (!intel_encoder->base.crtc)
a4fc5ed6
KP		 4285 return;
4286
1a125d8a
ID		 4287 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4288 return;
4289
92fd8fd1 4290 /* Try to read receiver status if the link appears to be up */
93f62dad 4291 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4292 return;
4293 }
4294
92fd8fd1 4295 /* Now read the DPCD to see if it's actually running */
26d61aad 4296 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4297 return;
4298 }
4299
a60f0e38
JB		 4300 /* Try to read the source of the interrupt */
4301 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4302 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4303 /* Clear interrupt source */
9d1a1031
JN		 4304 drm_dp_dpcd_writeb(&intel_dp->aux,
4305 DP_DEVICE_SERVICE_IRQ_VECTOR,
4306 sink_irq_vector);
a60f0e38
JB		 4307
4308 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4309 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4310 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4311 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4312 }
4313
14631e9d
SS		 4314 /* if link training is requested we should perform it always */
4315 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4316 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
92fd8fd1 4317 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4318 intel_encoder->base.name);
33a34e4e 4319 intel_dp_start_link_train(intel_dp);
3ab9c637 4320 intel_dp_stop_link_train(intel_dp);
33a34e4e 4321 }
a4fc5ed6 4322}
a4fc5ed6 4323
caf9ab24 4324/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4325static enum drm_connector_status
26d61aad 4326intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4327{
caf9ab24 4328 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4329 uint8_t type;
4330
4331 if (!intel_dp_get_dpcd(intel_dp))
4332 return connector_status_disconnected;
4333
4334 /* if there's no downstream port, we're done */
4335 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4336 return connector_status_connected;
caf9ab24
AJ		 4337
4338 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4339 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4340 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4341 uint8_t reg;
9d1a1031
JN		 4342
4343 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4344 &reg, 1) < 0)
caf9ab24 4345 return connector_status_unknown;
9d1a1031 4346
23235177
AJ		 4347 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4348 : connector_status_disconnected;
caf9ab24
AJ		 4349 }
4350
4351 /* If no HPD, poke DDC gently */
0b99836f 4352 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4353 return connector_status_connected;
caf9ab24
AJ		 4354
4355 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4356 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4357 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4358 if (type == DP_DS_PORT_TYPE_VGA ||
4359 type == DP_DS_PORT_TYPE_NON_EDID)
4360 return connector_status_unknown;
4361 } else {
4362 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4363 DP_DWN_STRM_PORT_TYPE_MASK;
4364 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4365 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4366 return connector_status_unknown;
4367 }
caf9ab24
AJ		 4368
4369 /* Anything else is out of spec, warn and ignore */
4370 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4371 return connector_status_disconnected;
71ba9000
AJ		 4372}
4373
d410b56d
CW		 4374static enum drm_connector_status
4375edp_detect(struct intel_dp *intel_dp)
4376{
4377 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4378 enum drm_connector_status status;
4379
4380 status = intel_panel_detect(dev);
4381 if (status == connector_status_unknown)
4382 status = connector_status_connected;
4383
4384 return status;
4385}
4386
b93433cc
JN		 4387static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4388 struct intel_digital_port *port)
5eb08b69 4389{
b93433cc 4390 u32 bit;
01cb9ea6 4391
0df53b77
JN		 4392 switch (port->port) {
4393 case PORT_A:
4394 return true;
4395 case PORT_B:
4396 bit = SDE_PORTB_HOTPLUG;
4397 break;
4398 case PORT_C:
4399 bit = SDE_PORTC_HOTPLUG;
4400 break;
4401 case PORT_D:
4402 bit = SDE_PORTD_HOTPLUG;
4403 break;
4404 default:
4405 MISSING_CASE(port->port);
4406 return false;
4407 }
4408
4409 return I915_READ(SDEISR) & bit;
4410}
4411
4412static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4413 struct intel_digital_port *port)
4414{
4415 u32 bit;
4416
4417 switch (port->port) {
4418 case PORT_A:
4419 return true;
4420 case PORT_B:
4421 bit = SDE_PORTB_HOTPLUG_CPT;
4422 break;
4423 case PORT_C:
4424 bit = SDE_PORTC_HOTPLUG_CPT;
4425 break;
4426 case PORT_D:
4427 bit = SDE_PORTD_HOTPLUG_CPT;
4428 break;
a78695d3
JN		 4429 case PORT_E:
4430 bit = SDE_PORTE_HOTPLUG_SPT;
4431 break;
0df53b77
JN		 4432 default:
4433 MISSING_CASE(port->port);
4434 return false;
b93433cc 4435 }
1b469639 4436
b93433cc 4437 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4438}
4439
7e66bcf2 4440static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4441 struct intel_digital_port *port)
a4fc5ed6 4442{
9642c81c 4443 u32 bit;
5eb08b69 4444
9642c81c
JN		 4445 switch (port->port) {
4446 case PORT_B:
4447 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4448 break;
4449 case PORT_C:
4450 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4451 break;
4452 case PORT_D:
4453 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4454 break;
4455 default:
4456 MISSING_CASE(port->port);
4457 return false;
4458 }
4459
4460 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4461}
4462
4463static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
4464 struct intel_digital_port *port)
4465{
4466 u32 bit;
4467
4468 switch (port->port) {
4469 case PORT_B:
4470 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4471 break;
4472 case PORT_C:
4473 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4474 break;
4475 case PORT_D:
4476 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4477 break;
4478 default:
4479 MISSING_CASE(port->port);
4480 return false;
a4fc5ed6
KP		 4481 }
4482
1d245987 4483 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4484}
4485
e464bfde 4486static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4487 struct intel_digital_port *intel_dig_port)
e464bfde 4488{
e2ec35a5
SJ		 4489 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4490 enum port port;
e464bfde
JN		 4491 u32 bit;
4492
e2ec35a5
SJ		 4493 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4494 switch (port) {
e464bfde
JN		 4495 case PORT_A:
4496 bit = BXT_DE_PORT_HP_DDIA;
4497 break;
4498 case PORT_B:
4499 bit = BXT_DE_PORT_HP_DDIB;
4500 break;
4501 case PORT_C:
4502 bit = BXT_DE_PORT_HP_DDIC;
4503 break;
4504 default:
e2ec35a5 4505 MISSING_CASE(port);
e464bfde
JN		 4506 return false;
4507 }
4508
4509 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4510}
4511
7e66bcf2
JN		 4512/*
4513 * intel_digital_port_connected - is the specified port connected?
4514 * @dev_priv: i915 private structure
4515 * @port: the port to test
4516 *
4517 * Return %true if @port is connected, %false otherwise.
4518 */
237ed86c 4519bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4520 struct intel_digital_port *port)
4521{
0df53b77 4522 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4523 return ibx_digital_port_connected(dev_priv, port);
0df53b77
JN		 4524 if (HAS_PCH_SPLIT(dev_priv))
4525 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4526 else if (IS_BROXTON(dev_priv))
4527 return bxt_digital_port_connected(dev_priv, port);
9642c81c
JN		 4528 else if (IS_VALLEYVIEW(dev_priv))
4529 return vlv_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4530 else
4531 return g4x_digital_port_connected(dev_priv, port);
4532}
4533
b93433cc
JN		 4534static enum drm_connector_status
4535ironlake_dp_detect(struct intel_dp *intel_dp)
4536{
4537 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4538 struct drm_i915_private *dev_priv = dev->dev_private;
4539 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4540
7e66bcf2 4541 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
b93433cc
JN		 4542 return connector_status_disconnected;
4543
4544 return intel_dp_detect_dpcd(intel_dp);
4545}
4546
2a592bec
DA		 4547static enum drm_connector_status
4548g4x_dp_detect(struct intel_dp *intel_dp)
4549{
4550 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4551 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2a592bec
DA		 4552
4553 /* Can't disconnect eDP, but you can close the lid... */
4554 if (is_edp(intel_dp)) {
4555 enum drm_connector_status status;
4556
4557 status = intel_panel_detect(dev);
4558 if (status == connector_status_unknown)
4559 status = connector_status_connected;
4560 return status;
4561 }
4562
7e66bcf2 4563 if (!intel_digital_port_connected(dev->dev_private, intel_dig_port))
a4fc5ed6
KP		 4564 return connector_status_disconnected;
4565
26d61aad 4566 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4567}
4568
8c241fef 4569static struct edid *
beb60608 4570intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4571{
beb60608 4572 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4573
9cd300e0
JN		 4574 /* use cached edid if we have one */
4575 if (intel_connector->edid) {
9cd300e0
JN		 4576 /* invalid edid */
4577 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4578 return NULL;
4579
55e9edeb 4580 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4581 } else
4582 return drm_get_edid(&intel_connector->base,
4583 &intel_dp->aux.ddc);
4584}
8c241fef 4585
beb60608
CW		 4586static void
4587intel_dp_set_edid(struct intel_dp *intel_dp)
4588{
4589 struct intel_connector *intel_connector = intel_dp->attached_connector;
4590 struct edid *edid;
8c241fef 4591
beb60608
CW		 4592 edid = intel_dp_get_edid(intel_dp);
4593 intel_connector->detect_edid = edid;
4594
4595 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4596 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4597 else
4598 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4599}
4600
beb60608
CW		 4601static void
4602intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4603{
beb60608 4604 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4605
beb60608
CW		 4606 kfree(intel_connector->detect_edid);
4607 intel_connector->detect_edid = NULL;
9cd300e0 4608
beb60608
CW		 4609 intel_dp->has_audio = false;
4610}
d6f24d0f 4611
a9756bb5
ZW		 4612static enum drm_connector_status
4613intel_dp_detect(struct drm_connector *connector, bool force)
4614{
4615 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4616 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4617 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4618 struct drm_device *dev = connector->dev;
a9756bb5 4619 enum drm_connector_status status;
671dedd2 4620 enum intel_display_power_domain power_domain;
0e32b39c 4621 bool ret;
09b1eb13 4622 u8 sink_irq_vector;
a9756bb5 4623
164c8598 4624 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4625 connector->base.id, connector->name);
beb60608 4626 intel_dp_unset_edid(intel_dp);
164c8598 4627
0e32b39c
DA		 4628 if (intel_dp->is_mst) {
4629 /* MST devices are disconnected from a monitor POV */
4630 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4631 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4632 return connector_status_disconnected;
0e32b39c
DA		 4633 }
4634
25f78f58
VS		 4635 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4636 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4637
d410b56d
CW		 4638 /* Can't disconnect eDP, but you can close the lid... */
4639 if (is_edp(intel_dp))
4640 status = edp_detect(intel_dp);
4641 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4642 status = ironlake_dp_detect(intel_dp);
4643 else
4644 status = g4x_dp_detect(intel_dp);
4df6960e
SS		 4645 if (status != connector_status_connected) {
4646 intel_dp->compliance_test_active = 0;
4647 intel_dp->compliance_test_type = 0;
4648 intel_dp->compliance_test_data = 0;
4649
c8c8fb33 4650 goto out;
4df6960e 4651 }
a9756bb5 4652
0d198328
AJ		 4653 intel_dp_probe_oui(intel_dp);
4654
0e32b39c
DA		 4655 ret = intel_dp_probe_mst(intel_dp);
4656 if (ret) {
4657 /* if we are in MST mode then this connector
4658 won't appear connected or have anything with EDID on it */
4659 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4660 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4661 status = connector_status_disconnected;
4662 goto out;
4663 }
4664
4df6960e
SS		 4665 /*
4666 * Clearing NACK and defer counts to get their exact values
4667 * while reading EDID which are required by Compliance tests
4668 * 4.2.2.4 and 4.2.2.5
4669 */
4670 intel_dp->aux.i2c_nack_count = 0;
4671 intel_dp->aux.i2c_defer_count = 0;
4672
beb60608 4673 intel_dp_set_edid(intel_dp);
a9756bb5 4674
d63885da
PZ		 4675 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4676 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4677 status = connector_status_connected;
4678
09b1eb13
TP		 4679 /* Try to read the source of the interrupt */
4680 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4681 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4682 /* Clear interrupt source */
4683 drm_dp_dpcd_writeb(&intel_dp->aux,
4684 DP_DEVICE_SERVICE_IRQ_VECTOR,
4685 sink_irq_vector);
4686
4687 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4688 intel_dp_handle_test_request(intel_dp);
4689 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4690 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4691 }
4692
c8c8fb33 4693out:
25f78f58 4694 intel_display_power_put(to_i915(dev), power_domain);
c8c8fb33 4695 return status;
a4fc5ed6
KP		 4696}
4697
beb60608
CW		 4698static void
4699intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4700{
df0e9248 4701 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4702 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4703 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4704 enum intel_display_power_domain power_domain;
a4fc5ed6 4705
beb60608
CW		 4706 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4707 connector->base.id, connector->name);
4708 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4709
beb60608
CW		 4710 if (connector->status != connector_status_connected)
4711 return;
671dedd2 4712
25f78f58
VS		 4713 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4714 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4715
4716 intel_dp_set_edid(intel_dp);
4717
25f78f58 4718 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4719
4720 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4721 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4722}
4723
4724static int intel_dp_get_modes(struct drm_connector *connector)
4725{
4726 struct intel_connector *intel_connector = to_intel_connector(connector);
4727 struct edid *edid;
4728
4729 edid = intel_connector->detect_edid;
4730 if (edid) {
4731 int ret = intel_connector_update_modes(connector, edid);
4732 if (ret)
4733 return ret;
4734 }
32f9d658 4735
f8779fda 4736 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4737 if (is_edp(intel_attached_dp(connector)) &&
4738 intel_connector->panel.fixed_mode) {
f8779fda 4739 struct drm_display_mode *mode;
beb60608
CW		 4740
4741 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4742 intel_connector->panel.fixed_mode);
f8779fda 4743 if (mode) {
32f9d658
ZW		 4744 drm_mode_probed_add(connector, mode);
4745 return 1;
4746 }
4747 }
beb60608 4748
32f9d658 4749 return 0;
a4fc5ed6
KP		 4750}
4751
1aad7ac0
CW		 4752static bool
4753intel_dp_detect_audio(struct drm_connector *connector)
4754{
1aad7ac0 4755 bool has_audio = false;
beb60608 4756 struct edid *edid;
1aad7ac0 4757
beb60608
CW		 4758 edid = to_intel_connector(connector)->detect_edid;
4759 if (edid)
1aad7ac0 4760 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4761
1aad7ac0
CW		 4762 return has_audio;
4763}
4764
f684960e
CW		 4765static int
4766intel_dp_set_property(struct drm_connector *connector,
4767 struct drm_property *property,
4768 uint64_t val)
4769{
e953fd7b 4770 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4771 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4772 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4773 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4774 int ret;
4775
662595df 4776 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4777 if (ret)
4778 return ret;
4779
3f43c48d 4780 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4781 int i = val;
4782 bool has_audio;
4783
4784 if (i == intel_dp->force_audio)
f684960e
CW		 4785 return 0;
4786
1aad7ac0 4787 intel_dp->force_audio = i;
f684960e 4788
c3e5f67b 4789 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4790 has_audio = intel_dp_detect_audio(connector);
4791 else
c3e5f67b 4792 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4793
4794 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4795 return 0;
4796
1aad7ac0 4797 intel_dp->has_audio = has_audio;
f684960e
CW		 4798 goto done;
4799 }
4800
e953fd7b 4801 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4802 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4803 bool old_range = intel_dp->limited_color_range;
ae4edb80 4804
55bc60db
VS		 4805 switch (val) {
4806 case INTEL_BROADCAST_RGB_AUTO:
4807 intel_dp->color_range_auto = true;
4808 break;
4809 case INTEL_BROADCAST_RGB_FULL:
4810 intel_dp->color_range_auto = false;
0f2a2a75 4811 intel_dp->limited_color_range = false;
55bc60db
VS		 4812 break;
4813 case INTEL_BROADCAST_RGB_LIMITED:
4814 intel_dp->color_range_auto = false;
0f2a2a75 4815 intel_dp->limited_color_range = true;
55bc60db
VS		 4816 break;
4817 default:
4818 return -EINVAL;
4819 }
ae4edb80
DV		 4820
4821 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4822 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4823 return 0;
4824
e953fd7b
CW		 4825 goto done;
4826 }
4827
53b41837
YN		 4828 if (is_edp(intel_dp) &&
4829 property == connector->dev->mode_config.scaling_mode_property) {
4830 if (val == DRM_MODE_SCALE_NONE) {
4831 DRM_DEBUG_KMS("no scaling not supported\n");
4832 return -EINVAL;
4833 }
4834
4835 if (intel_connector->panel.fitting_mode == val) {
4836 /* the eDP scaling property is not changed */
4837 return 0;
4838 }
4839 intel_connector->panel.fitting_mode = val;
4840
4841 goto done;
4842 }
4843
f684960e
CW		 4844 return -EINVAL;
4845
4846done:
c0c36b94
CW		 4847 if (intel_encoder->base.crtc)
4848 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4849
4850 return 0;
4851}
4852
a4fc5ed6 4853static void
73845adf 4854intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4855{
1d508706 4856 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4857
10e972d3 4858 kfree(intel_connector->detect_edid);
beb60608 4859
9cd300e0
JN		 4860 if (!IS_ERR_OR_NULL(intel_connector->edid))
4861 kfree(intel_connector->edid);
4862
acd8db10
PZ		 4863 /* Can't call is_edp() since the encoder may have been destroyed
4864 * already. */
4865 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4866 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4867
a4fc5ed6 4868 drm_connector_cleanup(connector);
55f78c43 4869 kfree(connector);
a4fc5ed6
KP		 4870}
4871
00c09d70 4872void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4873{
da63a9f2
PZ		 4874 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4875 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4876
a121f4e5 4877 intel_dp_aux_fini(intel_dp);
0e32b39c 4878 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4879 if (is_edp(intel_dp)) {
4880 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4881 /*
4882 * vdd might still be enabled do to the delayed vdd off.
4883 * Make sure vdd is actually turned off here.
4884 */
773538e8 4885 pps_lock(intel_dp);
4be73780 4886 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4887 pps_unlock(intel_dp);
4888
01527b31
CT		 4889 if (intel_dp->edp_notifier.notifier_call) {
4890 unregister_reboot_notifier(&intel_dp->edp_notifier);
4891 intel_dp->edp_notifier.notifier_call = NULL;
4892 }
bd943159 4893 }
c8bd0e49 4894 drm_encoder_cleanup(encoder);
da63a9f2 4895 kfree(intel_dig_port);
24d05927
DV		 4896}
4897
07f9cd0b
ID		 4898static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4899{
4900 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4901
4902 if (!is_edp(intel_dp))
4903 return;
4904
951468f3
VS		 4905 /*
4906 * vdd might still be enabled do to the delayed vdd off.
4907 * Make sure vdd is actually turned off here.
4908 */
afa4e53a 4909 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4910 pps_lock(intel_dp);
07f9cd0b 4911 edp_panel_vdd_off_sync(intel_dp);
773538e8 4912 pps_unlock(intel_dp);
07f9cd0b
ID		 4913}
4914
49e6bc51
VS		 4915static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4916{
4917 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4918 struct drm_device *dev = intel_dig_port->base.base.dev;
4919 struct drm_i915_private *dev_priv = dev->dev_private;
4920 enum intel_display_power_domain power_domain;
4921
4922 lockdep_assert_held(&dev_priv->pps_mutex);
4923
4924 if (!edp_have_panel_vdd(intel_dp))
4925 return;
4926
4927 /*
4928 * The VDD bit needs a power domain reference, so if the bit is
4929 * already enabled when we boot or resume, grab this reference and
4930 * schedule a vdd off, so we don't hold on to the reference
4931 * indefinitely.
4932 */
4933 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4934 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4935 intel_display_power_get(dev_priv, power_domain);
4936
4937 edp_panel_vdd_schedule_off(intel_dp);
4938}
4939
6d93c0c4
ID		 4940static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4941{
49e6bc51
VS		 4942 struct intel_dp *intel_dp;
4943
4944 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4945 return;
4946
4947 intel_dp = enc_to_intel_dp(encoder);
4948
4949 pps_lock(intel_dp);
4950
4951 /*
4952 * Read out the current power sequencer assignment,
4953 * in case the BIOS did something with it.
4954 */
4955 if (IS_VALLEYVIEW(encoder->dev))
4956 vlv_initial_power_sequencer_setup(intel_dp);
4957
4958 intel_edp_panel_vdd_sanitize(intel_dp);
4959
4960 pps_unlock(intel_dp);
6d93c0c4
ID		 4961}
4962
a4fc5ed6 4963static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4964 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4965 .detect = intel_dp_detect,
beb60608 4966 .force = intel_dp_force,
a4fc5ed6 4967 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4968 .set_property = intel_dp_set_property,
2545e4a6 4969 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4970 .destroy = intel_dp_connector_destroy,
c6f95f27 4971 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4972 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4973};
4974
4975static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4976 .get_modes = intel_dp_get_modes,
4977 .mode_valid = intel_dp_mode_valid,
df0e9248 4978 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4979};
4980
a4fc5ed6 4981static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4982 .reset = intel_dp_encoder_reset,
24d05927 4983 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4984};
4985
b2c5c181 4986enum irqreturn
13cf5504
DA		 4987intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4988{
4989 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4990 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4991 struct drm_device *dev = intel_dig_port->base.base.dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4993 enum intel_display_power_domain power_domain;
b2c5c181 4994 enum irqreturn ret = IRQ_NONE;
1c767b33 4995
0e32b39c
DA		 4996 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4997 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4998
7a7f84cc
VS		 4999 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5000 /*
5001 * vdd off can generate a long pulse on eDP which
5002 * would require vdd on to handle it, and thus we
5003 * would end up in an endless cycle of
5004 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5005 */
5006 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5007 port_name(intel_dig_port->port));
a8b3d52f 5008 return IRQ_HANDLED;
7a7f84cc
VS		 5009 }
5010
26fbb774
VS		 5011 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5012 port_name(intel_dig_port->port),
0e32b39c 5013 long_hpd ? "long" : "short");
13cf5504 5014
25f78f58 5015 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 5016 intel_display_power_get(dev_priv, power_domain);
5017
0e32b39c 5018 if (long_hpd) {
5fa836a9
MK		 5019 /* indicate that we need to restart link training */
5020 intel_dp->train_set_valid = false;
2a592bec 5021
7e66bcf2
JN		 5022 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
5023 goto mst_fail;
0e32b39c
DA		 5024
5025 if (!intel_dp_get_dpcd(intel_dp)) {
5026 goto mst_fail;
5027 }
5028
5029 intel_dp_probe_oui(intel_dp);
5030
d14e7b6d
VS		 5031 if (!intel_dp_probe_mst(intel_dp)) {
5032 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5033 intel_dp_check_link_status(intel_dp);
5034 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c 5035 goto mst_fail;
d14e7b6d 5036 }
0e32b39c
DA		 5037 } else {
5038 if (intel_dp->is_mst) {
1c767b33 5039 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 5040 goto mst_fail;
5041 }
5042
5043 if (!intel_dp->is_mst) {
5b215bcf 5044 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 5045 intel_dp_check_link_status(intel_dp);
5b215bcf 5046 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 5047 }
5048 }
b2c5c181
DV		 5049
5050 ret = IRQ_HANDLED;
5051
1c767b33 5052 goto put_power;
0e32b39c
DA		 5053mst_fail:
5054 /* if we were in MST mode, and device is not there get out of MST mode */
5055 if (intel_dp->is_mst) {
5056 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5057 intel_dp->is_mst = false;
5058 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
5059 }
1c767b33
ID		 5060put_power:
5061 intel_display_power_put(dev_priv, power_domain);
5062
5063 return ret;
13cf5504
DA		 5064}
5065
477ec328 5066/* check the VBT to see whether the eDP is on another port */
5d8a7752 5067bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 5068{
5069 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 5070 union child_device_config *p_child;
36e83a18 5071 int i;
5d8a7752 5072 static const short port_mapping[] = {
477ec328
RV		 5073 [PORT_B] = DVO_PORT_DPB,
5074 [PORT_C] = DVO_PORT_DPC,
5075 [PORT_D] = DVO_PORT_DPD,
5076 [PORT_E] = DVO_PORT_DPE,
5d8a7752 5077 };
36e83a18 5078
53ce81a7
VS		 5079 /*
5080 * eDP not supported on g4x. so bail out early just
5081 * for a bit extra safety in case the VBT is bonkers.
5082 */
5083 if (INTEL_INFO(dev)->gen < 5)
5084 return false;
5085
3b32a35b
VS		 5086 if (port == PORT_A)
5087 return true;
5088
41aa3448 5089 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 5090 return false;
5091
41aa3448
RV		 5092 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5093 p_child = dev_priv->vbt.child_dev + i;
36e83a18 5094
5d8a7752 5095 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 5096 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5097 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 5098 return true;
5099 }
5100 return false;
5101}
5102
0e32b39c 5103void
f684960e
CW		 5104intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5105{
53b41837
YN		 5106 struct intel_connector *intel_connector = to_intel_connector(connector);
5107
3f43c48d 5108 intel_attach_force_audio_property(connector);
e953fd7b 5109 intel_attach_broadcast_rgb_property(connector);
55bc60db 5110 intel_dp->color_range_auto = true;
53b41837
YN		 5111
5112 if (is_edp(intel_dp)) {
5113 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 5114 drm_object_attach_property(
5115 &connector->base,
53b41837 5116 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 5117 DRM_MODE_SCALE_ASPECT);
5118 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5119 }
f684960e
CW		 5120}
5121
dada1a9f
ID		 5122static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5123{
5124 intel_dp->last_power_cycle = jiffies;
5125 intel_dp->last_power_on = jiffies;
5126 intel_dp->last_backlight_off = jiffies;
5127}
5128
67a54566
DV		 5129static void
5130intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5131 struct intel_dp *intel_dp)
67a54566
DV		 5132{
5133 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5134 struct edp_power_seq cur, vbt, spec,
5135 *final = &intel_dp->pps_delays;
b0a08bec
VK		 5136 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5137 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
453c5420 5138
e39b999a
VS		 5139 lockdep_assert_held(&dev_priv->pps_mutex);
5140
81ddbc69
VS		 5141 /* already initialized? */
5142 if (final->t11_t12 != 0)
5143 return;
5144
b0a08bec
VK		 5145 if (IS_BROXTON(dev)) {
5146 /*
5147 * TODO: BXT has 2 sets of PPS registers.
5148 * Correct Register for Broxton need to be identified
5149 * using VBT. hardcoding for now
5150 */
5151 pp_ctrl_reg = BXT_PP_CONTROL(0);
5152 pp_on_reg = BXT_PP_ON_DELAYS(0);
5153 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5154 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5155 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5156 pp_on_reg = PCH_PP_ON_DELAYS;
5157 pp_off_reg = PCH_PP_OFF_DELAYS;
5158 pp_div_reg = PCH_PP_DIVISOR;
5159 } else {
bf13e81b
JN		 5160 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5161
5162 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5163 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5164 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5165 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5166 }
67a54566
DV		 5167
5168 /* Workaround: Need to write PP_CONTROL with the unlock key as
5169 * the very first thing. */
b0a08bec 5170 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5171
453c5420
JB		 5172 pp_on = I915_READ(pp_on_reg);
5173 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 5174 if (!IS_BROXTON(dev)) {
5175 I915_WRITE(pp_ctrl_reg, pp_ctl);
5176 pp_div = I915_READ(pp_div_reg);
5177 }
67a54566
DV		 5178
5179 /* Pull timing values out of registers */
5180 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5181 PANEL_POWER_UP_DELAY_SHIFT;
5182
5183 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5184 PANEL_LIGHT_ON_DELAY_SHIFT;
5185
5186 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5187 PANEL_LIGHT_OFF_DELAY_SHIFT;
5188
5189 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5190 PANEL_POWER_DOWN_DELAY_SHIFT;
5191
b0a08bec
VK		 5192 if (IS_BROXTON(dev)) {
5193 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5194 BXT_POWER_CYCLE_DELAY_SHIFT;
5195 if (tmp > 0)
5196 cur.t11_t12 = (tmp - 1) * 1000;
5197 else
5198 cur.t11_t12 = 0;
5199 } else {
5200 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5201 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5202 }
67a54566
DV		 5203
5204 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5205 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5206
41aa3448 5207 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5208
5209 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5210 * our hw here, which are all in 100usec. */
5211 spec.t1_t3 = 210 * 10;
5212 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5213 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5214 spec.t10 = 500 * 10;
5215 /* This one is special and actually in units of 100ms, but zero
5216 * based in the hw (so we need to add 100 ms). But the sw vbt
5217 * table multiplies it with 1000 to make it in units of 100usec,
5218 * too. */
5219 spec.t11_t12 = (510 + 100) * 10;
5220
5221 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5222 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5223
5224 /* Use the max of the register settings and vbt. If both are
5225 * unset, fall back to the spec limits. */
36b5f425 5226#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5227 spec.field : \
5228 max(cur.field, vbt.field))
5229 assign_final(t1_t3);
5230 assign_final(t8);
5231 assign_final(t9);
5232 assign_final(t10);
5233 assign_final(t11_t12);
5234#undef assign_final
5235
36b5f425 5236#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5237 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5238 intel_dp->backlight_on_delay = get_delay(t8);
5239 intel_dp->backlight_off_delay = get_delay(t9);
5240 intel_dp->panel_power_down_delay = get_delay(t10);
5241 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5242#undef get_delay
5243
f30d26e4
JN		 5244 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5245 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5246 intel_dp->panel_power_cycle_delay);
5247
5248 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5249 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5250}
5251
5252static void
5253intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5254 struct intel_dp *intel_dp)
f30d26e4
JN		 5255{
5256 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5257 u32 pp_on, pp_off, pp_div, port_sel = 0;
5258 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
b0a08bec 5259 int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
ad933b56 5260 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5261 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5262
e39b999a 5263 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5264
b0a08bec
VK		 5265 if (IS_BROXTON(dev)) {
5266 /*
5267 * TODO: BXT has 2 sets of PPS registers.
5268 * Correct Register for Broxton need to be identified
5269 * using VBT. hardcoding for now
5270 */
5271 pp_ctrl_reg = BXT_PP_CONTROL(0);
5272 pp_on_reg = BXT_PP_ON_DELAYS(0);
5273 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5274
5275 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 5276 pp_on_reg = PCH_PP_ON_DELAYS;
5277 pp_off_reg = PCH_PP_OFF_DELAYS;
5278 pp_div_reg = PCH_PP_DIVISOR;
5279 } else {
bf13e81b
JN		 5280 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5281
5282 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5283 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5284 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5285 }
5286
b2f19d1a
PZ		 5287 /*
5288 * And finally store the new values in the power sequencer. The
5289 * backlight delays are set to 1 because we do manual waits on them. For
5290 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5291 * we'll end up waiting for the backlight off delay twice: once when we
5292 * do the manual sleep, and once when we disable the panel and wait for
5293 * the PP_STATUS bit to become zero.
5294 */
f30d26e4 5295 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5296 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5297 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5298 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5299 /* Compute the divisor for the pp clock, simply match the Bspec
5300 * formula. */
b0a08bec
VK		 5301 if (IS_BROXTON(dev)) {
5302 pp_div = I915_READ(pp_ctrl_reg);
5303 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5304 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5305 << BXT_POWER_CYCLE_DELAY_SHIFT);
5306 } else {
5307 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5308 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5309 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5310 }
67a54566
DV		 5311
5312 /* Haswell doesn't have any port selection bits for the panel
5313 * power sequencer any more. */
bc7d38a4 5314 if (IS_VALLEYVIEW(dev)) {
ad933b56 5315 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5316 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5317 if (port == PORT_A)
a24c144c 5318 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5319 else
a24c144c 5320 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5321 }
5322
453c5420
JB		 5323 pp_on |= port_sel;
5324
5325 I915_WRITE(pp_on_reg, pp_on);
5326 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 5327 if (IS_BROXTON(dev))
5328 I915_WRITE(pp_ctrl_reg, pp_div);
5329 else
5330 I915_WRITE(pp_div_reg, pp_div);
67a54566 5331
67a54566 5332 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5333 I915_READ(pp_on_reg),
5334 I915_READ(pp_off_reg),
b0a08bec
VK		 5335 IS_BROXTON(dev) ?
5336 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 5337 I915_READ(pp_div_reg));
f684960e
CW		 5338}
5339
b33a2815
VK		 5340/**
5341 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5342 * @dev: DRM device
5343 * @refresh_rate: RR to be programmed
5344 *
5345 * This function gets called when refresh rate (RR) has to be changed from
5346 * one frequency to another. Switches can be between high and low RR
5347 * supported by the panel or to any other RR based on media playback (in
5348 * this case, RR value needs to be passed from user space).
5349 *
5350 * The caller of this function needs to take a lock on dev_priv->drrs.
5351 */
96178eeb 5352static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5353{
5354 struct drm_i915_private *dev_priv = dev->dev_private;
5355 struct intel_encoder *encoder;
96178eeb
VK		 5356 struct intel_digital_port *dig_port = NULL;
5357 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5358 struct intel_crtc_state *config = NULL;
439d7ac0 5359 struct intel_crtc *intel_crtc = NULL;
96178eeb 5360 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5361
5362 if (refresh_rate <= 0) {
5363 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5364 return;
5365 }
5366
96178eeb
VK		 5367 if (intel_dp == NULL) {
5368 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5369 return;
5370 }
5371
1fcc9d1c 5372 /*
e4d59f6b
RV		 5373 * FIXME: This needs proper synchronization with psr state for some
5374 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5375 */
439d7ac0 5376
96178eeb
VK		 5377 dig_port = dp_to_dig_port(intel_dp);
5378 encoder = &dig_port->base;
723f9aab 5379 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5380
5381 if (!intel_crtc) {
5382 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5383 return;
5384 }
5385
6e3c9717 5386 config = intel_crtc->config;
439d7ac0 5387
96178eeb 5388 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5389 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5390 return;
5391 }
5392
96178eeb
VK		 5393 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5394 refresh_rate)
439d7ac0
PB		 5395 index = DRRS_LOW_RR;
5396
96178eeb 5397 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5398 DRM_DEBUG_KMS(
5399 "DRRS requested for previously set RR...ignoring\n");
5400 return;
5401 }
5402
5403 if (!intel_crtc->active) {
5404 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5405 return;
5406 }
5407
44395bfe 5408 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5409 switch (index) {
5410 case DRRS_HIGH_RR:
5411 intel_dp_set_m_n(intel_crtc, M1_N1);
5412 break;
5413 case DRRS_LOW_RR:
5414 intel_dp_set_m_n(intel_crtc, M2_N2);
5415 break;
5416 case DRRS_MAX_RR:
5417 default:
5418 DRM_ERROR("Unsupported refreshrate type\n");
5419 }
5420 } else if (INTEL_INFO(dev)->gen > 6) {
649636ef
VS		 5421 u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5422 u32 val;
a4c30b1d 5423
649636ef 5424 val = I915_READ(reg);
439d7ac0 5425 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5426 if (IS_VALLEYVIEW(dev))
5427 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5428 else
5429 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5430 } else {
6fa7aec1
VK		 5431 if (IS_VALLEYVIEW(dev))
5432 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5433 else
5434 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5435 }
5436 I915_WRITE(reg, val);
5437 }
5438
4e9ac947
VK		 5439 dev_priv->drrs.refresh_rate_type = index;
5440
5441 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5442}
5443
b33a2815
VK		 5444/**
5445 * intel_edp_drrs_enable - init drrs struct if supported
5446 * @intel_dp: DP struct
5447 *
5448 * Initializes frontbuffer_bits and drrs.dp
5449 */
c395578e
VK		 5450void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5451{
5452 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5453 struct drm_i915_private *dev_priv = dev->dev_private;
5454 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5455 struct drm_crtc *crtc = dig_port->base.base.crtc;
5456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5457
5458 if (!intel_crtc->config->has_drrs) {
5459 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5460 return;
5461 }
5462
5463 mutex_lock(&dev_priv->drrs.mutex);
5464 if (WARN_ON(dev_priv->drrs.dp)) {
5465 DRM_ERROR("DRRS already enabled\n");
5466 goto unlock;
5467 }
5468
5469 dev_priv->drrs.busy_frontbuffer_bits = 0;
5470
5471 dev_priv->drrs.dp = intel_dp;
5472
5473unlock:
5474 mutex_unlock(&dev_priv->drrs.mutex);
5475}
5476
b33a2815
VK		 5477/**
5478 * intel_edp_drrs_disable - Disable DRRS
5479 * @intel_dp: DP struct
5480 *
5481 */
c395578e
VK		 5482void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5483{
5484 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5485 struct drm_i915_private *dev_priv = dev->dev_private;
5486 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5487 struct drm_crtc *crtc = dig_port->base.base.crtc;
5488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5489
5490 if (!intel_crtc->config->has_drrs)
5491 return;
5492
5493 mutex_lock(&dev_priv->drrs.mutex);
5494 if (!dev_priv->drrs.dp) {
5495 mutex_unlock(&dev_priv->drrs.mutex);
5496 return;
5497 }
5498
5499 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5500 intel_dp_set_drrs_state(dev_priv->dev,
5501 intel_dp->attached_connector->panel.
5502 fixed_mode->vrefresh);
5503
5504 dev_priv->drrs.dp = NULL;
5505 mutex_unlock(&dev_priv->drrs.mutex);
5506
5507 cancel_delayed_work_sync(&dev_priv->drrs.work);
5508}
5509
4e9ac947
VK		 5510static void intel_edp_drrs_downclock_work(struct work_struct *work)
5511{
5512 struct drm_i915_private *dev_priv =
5513 container_of(work, typeof(*dev_priv), drrs.work.work);
5514 struct intel_dp *intel_dp;
5515
5516 mutex_lock(&dev_priv->drrs.mutex);
5517
5518 intel_dp = dev_priv->drrs.dp;
5519
5520 if (!intel_dp)
5521 goto unlock;
5522
439d7ac0 5523 /*
4e9ac947
VK		 5524 * The delayed work can race with an invalidate hence we need to
5525 * recheck.
439d7ac0
PB		 5526 */
5527
4e9ac947
VK		 5528 if (dev_priv->drrs.busy_frontbuffer_bits)
5529 goto unlock;
439d7ac0 5530
4e9ac947
VK		 5531 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5532 intel_dp_set_drrs_state(dev_priv->dev,
5533 intel_dp->attached_connector->panel.
5534 downclock_mode->vrefresh);
439d7ac0 5535
4e9ac947 5536unlock:
4e9ac947 5537 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5538}
5539
b33a2815 5540/**
0ddfd203 5541 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5542 * @dev: DRM device
5543 * @frontbuffer_bits: frontbuffer plane tracking bits
5544 *
0ddfd203
R		 5545 * This function gets called everytime rendering on the given planes start.
5546 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5547 *
5548 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5549 */
a93fad0f
VK		 5550void intel_edp_drrs_invalidate(struct drm_device *dev,
5551 unsigned frontbuffer_bits)
5552{
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 struct drm_crtc *crtc;
5555 enum pipe pipe;
5556
9da7d693 5557 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5558 return;
5559
88f933a8 5560 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5561
a93fad0f 5562 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5563 if (!dev_priv->drrs.dp) {
5564 mutex_unlock(&dev_priv->drrs.mutex);
5565 return;
5566 }
5567
a93fad0f
VK		 5568 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5569 pipe = to_intel_crtc(crtc)->pipe;
5570
c1d038c6
DV		 5571 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5572 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5573
0ddfd203 5574 /* invalidate means busy screen hence upclock */
c1d038c6 5575 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5576 intel_dp_set_drrs_state(dev_priv->dev,
5577 dev_priv->drrs.dp->attached_connector->panel.
5578 fixed_mode->vrefresh);
a93fad0f 5579
a93fad0f
VK		 5580 mutex_unlock(&dev_priv->drrs.mutex);
5581}
5582
b33a2815 5583/**
0ddfd203 5584 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5585 * @dev: DRM device
5586 * @frontbuffer_bits: frontbuffer plane tracking bits
5587 *
0ddfd203
R		 5588 * This function gets called every time rendering on the given planes has
5589 * completed or flip on a crtc is completed. So DRRS should be upclocked
5590 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5591 * if no other planes are dirty.
b33a2815
VK		 5592 *
5593 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5594 */
a93fad0f
VK		 5595void intel_edp_drrs_flush(struct drm_device *dev,
5596 unsigned frontbuffer_bits)
5597{
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 struct drm_crtc *crtc;
5600 enum pipe pipe;
5601
9da7d693 5602 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5603 return;
5604
88f933a8 5605 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5606
a93fad0f 5607 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5608 if (!dev_priv->drrs.dp) {
5609 mutex_unlock(&dev_priv->drrs.mutex);
5610 return;
5611 }
5612
a93fad0f
VK		 5613 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5614 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5615
5616 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5617 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5618
0ddfd203 5619 /* flush means busy screen hence upclock */
c1d038c6 5620 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5621 intel_dp_set_drrs_state(dev_priv->dev,
5622 dev_priv->drrs.dp->attached_connector->panel.
5623 fixed_mode->vrefresh);
5624
5625 /*
5626 * flush also means no more activity hence schedule downclock, if all
5627 * other fbs are quiescent too
5628 */
5629 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5630 schedule_delayed_work(&dev_priv->drrs.work,
5631 msecs_to_jiffies(1000));
5632 mutex_unlock(&dev_priv->drrs.mutex);
5633}
5634
b33a2815
VK		 5635/**
5636 * DOC: Display Refresh Rate Switching (DRRS)
5637 *
5638 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5639 * which enables swtching between low and high refresh rates,
5640 * dynamically, based on the usage scenario. This feature is applicable
5641 * for internal panels.
5642 *
5643 * Indication that the panel supports DRRS is given by the panel EDID, which
5644 * would list multiple refresh rates for one resolution.
5645 *
5646 * DRRS is of 2 types - static and seamless.
5647 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5648 * (may appear as a blink on screen) and is used in dock-undock scenario.
5649 * Seamless DRRS involves changing RR without any visual effect to the user
5650 * and can be used during normal system usage. This is done by programming
5651 * certain registers.
5652 *
5653 * Support for static/seamless DRRS may be indicated in the VBT based on
5654 * inputs from the panel spec.
5655 *
5656 * DRRS saves power by switching to low RR based on usage scenarios.
5657 *
5658 * eDP DRRS:-
5659 * The implementation is based on frontbuffer tracking implementation.
5660 * When there is a disturbance on the screen triggered by user activity or a
5661 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5662 * When there is no movement on screen, after a timeout of 1 second, a switch
5663 * to low RR is made.
5664 * For integration with frontbuffer tracking code,
5665 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5666 *
5667 * DRRS can be further extended to support other internal panels and also
5668 * the scenario of video playback wherein RR is set based on the rate
5669 * requested by userspace.
5670 */
5671
5672/**
5673 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5674 * @intel_connector: eDP connector
5675 * @fixed_mode: preferred mode of panel
5676 *
5677 * This function is called only once at driver load to initialize basic
5678 * DRRS stuff.
5679 *
5680 * Returns:
5681 * Downclock mode if panel supports it, else return NULL.
5682 * DRRS support is determined by the presence of downclock mode (apart
5683 * from VBT setting).
5684 */
4f9db5b5 5685static struct drm_display_mode *
96178eeb
VK		 5686intel_dp_drrs_init(struct intel_connector *intel_connector,
5687 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5688{
5689 struct drm_connector *connector = &intel_connector->base;
96178eeb 5690 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692 struct drm_display_mode *downclock_mode = NULL;
5693
9da7d693
DV		 5694 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5695 mutex_init(&dev_priv->drrs.mutex);
5696
4f9db5b5
PB		 5697 if (INTEL_INFO(dev)->gen <= 6) {
5698 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5699 return NULL;
5700 }
5701
5702 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5703 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5704 return NULL;
5705 }
5706
5707 downclock_mode = intel_find_panel_downclock
5708 (dev, fixed_mode, connector);
5709
5710 if (!downclock_mode) {
a1d26342 5711 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5712 return NULL;
5713 }
5714
96178eeb 5715 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5716
96178eeb 5717 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5718 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5719 return downclock_mode;
5720}
5721
ed92f0b2 5722static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5723 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5724{
5725 struct drm_connector *connector = &intel_connector->base;
5726 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5727 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5728 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5729 struct drm_i915_private *dev_priv = dev->dev_private;
5730 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5731 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5732 bool has_dpcd;
5733 struct drm_display_mode *scan;
5734 struct edid *edid;
6517d273 5735 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5736
5737 if (!is_edp(intel_dp))
5738 return true;
5739
49e6bc51
VS		 5740 pps_lock(intel_dp);
5741 intel_edp_panel_vdd_sanitize(intel_dp);
5742 pps_unlock(intel_dp);
63635217 5743
ed92f0b2 5744 /* Cache DPCD and EDID for edp. */
ed92f0b2 5745 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5746
5747 if (has_dpcd) {
5748 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5749 dev_priv->no_aux_handshake =
5750 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5751 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5752 } else {
5753 /* if this fails, presume the device is a ghost */
5754 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5755 return false;
5756 }
5757
5758 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5759 pps_lock(intel_dp);
36b5f425 5760 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5761 pps_unlock(intel_dp);
ed92f0b2 5762
060c8778 5763 mutex_lock(&dev->mode_config.mutex);
0b99836f 5764 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5765 if (edid) {
5766 if (drm_add_edid_modes(connector, edid)) {
5767 drm_mode_connector_update_edid_property(connector,
5768 edid);
5769 drm_edid_to_eld(connector, edid);
5770 } else {
5771 kfree(edid);
5772 edid = ERR_PTR(-EINVAL);
5773 }
5774 } else {
5775 edid = ERR_PTR(-ENOENT);
5776 }
5777 intel_connector->edid = edid;
5778
5779 /* prefer fixed mode from EDID if available */
5780 list_for_each_entry(scan, &connector->probed_modes, head) {
5781 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5782 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5783 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5784 intel_connector, fixed_mode);
ed92f0b2
PZ		 5785 break;
5786 }
5787 }
5788
5789 /* fallback to VBT if available for eDP */
5790 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5791 fixed_mode = drm_mode_duplicate(dev,
5792 dev_priv->vbt.lfp_lvds_vbt_mode);
5793 if (fixed_mode)
5794 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5795 }
060c8778 5796 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5797
01527b31
CT		 5798 if (IS_VALLEYVIEW(dev)) {
5799 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5800 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5801
5802 /*
5803 * Figure out the current pipe for the initial backlight setup.
5804 * If the current pipe isn't valid, try the PPS pipe, and if that
5805 * fails just assume pipe A.
5806 */
5807 if (IS_CHERRYVIEW(dev))
5808 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5809 else
5810 pipe = PORT_TO_PIPE(intel_dp->DP);
5811
5812 if (pipe != PIPE_A && pipe != PIPE_B)
5813 pipe = intel_dp->pps_pipe;
5814
5815 if (pipe != PIPE_A && pipe != PIPE_B)
5816 pipe = PIPE_A;
5817
5818 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5819 pipe_name(pipe));
01527b31
CT		 5820 }
5821
4f9db5b5 5822 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5823 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5824 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5825
5826 return true;
5827}
5828
16c25533 5829bool
f0fec3f2
PZ		 5830intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5831 struct intel_connector *intel_connector)
a4fc5ed6 5832{
f0fec3f2
PZ		 5833 struct drm_connector *connector = &intel_connector->base;
5834 struct intel_dp *intel_dp = &intel_dig_port->dp;
5835 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5836 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5837 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5838 enum port port = intel_dig_port->port;
a121f4e5 5839 int type, ret;
a4fc5ed6 5840
a4a5d2f8
VS		 5841 intel_dp->pps_pipe = INVALID_PIPE;
5842
ec5b01dd 5843 /* intel_dp vfuncs */
b6b5e383
DL		 5844 if (INTEL_INFO(dev)->gen >= 9)
5845 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5846 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5847 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5848 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5849 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5850 else if (HAS_PCH_SPLIT(dev))
5851 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5852 else
5853 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5854
b9ca5fad
DL		 5855 if (INTEL_INFO(dev)->gen >= 9)
5856 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5857 else
5858 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5859
ad64217b
ACO		 5860 if (HAS_DDI(dev))
5861 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5862
0767935e
DV		 5863 /* Preserve the current hw state. */
5864 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5865 intel_dp->attached_connector = intel_connector;
3d3dc149 5866
3b32a35b 5867 if (intel_dp_is_edp(dev, port))
b329530c 5868 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5869 else
5870 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5871
f7d24902
ID		 5872 /*
5873 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5874 * for DP the encoder type can be set by the caller to
5875 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5876 */
5877 if (type == DRM_MODE_CONNECTOR_eDP)
5878 intel_encoder->type = INTEL_OUTPUT_EDP;
5879
c17ed5b5
VS		 5880 /* eDP only on port B and/or C on vlv/chv */
5881 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5882 port != PORT_B && port != PORT_C))
5883 return false;
5884
e7281eab
ID		 5885 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5886 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5887 port_name(port));
5888
b329530c 5889 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5890 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5891
a4fc5ed6
KP		 5892 connector->interlace_allowed = true;
5893 connector->doublescan_allowed = 0;
5894
f0fec3f2 5895 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5896 edp_panel_vdd_work);
a4fc5ed6 5897
df0e9248 5898 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5899 drm_connector_register(connector);
a4fc5ed6 5900
affa9354 5901 if (HAS_DDI(dev))
bcbc889b
PZ		 5902 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5903 else
5904 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5905 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5906
0b99836f 5907 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5908 switch (port) {
5909 case PORT_A:
1d843f9d 5910 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5911 break;
5912 case PORT_B:
1d843f9d 5913 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5914 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5915 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5916 break;
5917 case PORT_C:
1d843f9d 5918 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5919 break;
5920 case PORT_D:
1d843f9d 5921 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5922 break;
26951caf
XZ		 5923 case PORT_E:
5924 intel_encoder->hpd_pin = HPD_PORT_E;
5925 break;
ab9d7c30 5926 default:
ad1c0b19 5927 BUG();
5eb08b69
ZW		 5928 }
5929
dada1a9f 5930 if (is_edp(intel_dp)) {
773538e8 5931 pps_lock(intel_dp);
1e74a324
VS		 5932 intel_dp_init_panel_power_timestamps(intel_dp);
5933 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5934 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5935 else
36b5f425 5936 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5937 pps_unlock(intel_dp);
dada1a9f 5938 }
0095e6dc 5939
a121f4e5
VS		 5940 ret = intel_dp_aux_init(intel_dp, intel_connector);
5941 if (ret)
5942 goto fail;
c1f05264 5943
0e32b39c 5944 /* init MST on ports that can support it */
0c9b3715
JN		 5945 if (HAS_DP_MST(dev) &&
5946 (port == PORT_B || port == PORT_C || port == PORT_D))
5947 intel_dp_mst_encoder_init(intel_dig_port,
5948 intel_connector->base.base.id);
0e32b39c 5949
36b5f425 5950 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5951 intel_dp_aux_fini(intel_dp);
5952 intel_dp_mst_encoder_cleanup(intel_dig_port);
5953 goto fail;
b2f246a8 5954 }
32f9d658 5955
f684960e
CW		 5956 intel_dp_add_properties(intel_dp, connector);
5957
a4fc5ed6
KP		 5958 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5959 * 0xd. Failure to do so will result in spurious interrupts being
5960 * generated on the port when a cable is not attached.
5961 */
5962 if (IS_G4X(dev) && !IS_GM45(dev)) {
5963 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5964 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5965 }
16c25533 5966
aa7471d2
JN		 5967 i915_debugfs_connector_add(connector);
5968
16c25533 5969 return true;
a121f4e5
VS		 5970
5971fail:
5972 if (is_edp(intel_dp)) {
5973 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5974 /*
5975 * vdd might still be enabled do to the delayed vdd off.
5976 * Make sure vdd is actually turned off here.
5977 */
5978 pps_lock(intel_dp);
5979 edp_panel_vdd_off_sync(intel_dp);
5980 pps_unlock(intel_dp);
5981 }
5982 drm_connector_unregister(connector);
5983 drm_connector_cleanup(connector);
5984
5985 return false;
a4fc5ed6 5986}
f0fec3f2
PZ		 5987
5988void
5989intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5990{
13cf5504 5991 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5992 struct intel_digital_port *intel_dig_port;
5993 struct intel_encoder *intel_encoder;
5994 struct drm_encoder *encoder;
5995 struct intel_connector *intel_connector;
5996
b14c5679 5997 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5998 if (!intel_dig_port)
5999 return;
6000
08d9bc92 6001 intel_connector = intel_connector_alloc();
11aee0f6
SM		 6002 if (!intel_connector)
6003 goto err_connector_alloc;
f0fec3f2
PZ		 6004
6005 intel_encoder = &intel_dig_port->base;
6006 encoder = &intel_encoder->base;
6007
6008 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
6009 DRM_MODE_ENCODER_TMDS);
6010
5bfe2ac0 6011 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 6012 intel_encoder->disable = intel_disable_dp;
00c09d70 6013 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 6014 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 6015 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 6016 if (IS_CHERRYVIEW(dev)) {
9197c88b 6017 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 6018 intel_encoder->pre_enable = chv_pre_enable_dp;
6019 intel_encoder->enable = vlv_enable_dp;
580d3811 6020 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 6021 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 6022 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 6023 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 6024 intel_encoder->pre_enable = vlv_pre_enable_dp;
6025 intel_encoder->enable = vlv_enable_dp;
49277c31 6026 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 6027 } else {
ecff4f3b
JN		 6028 intel_encoder->pre_enable = g4x_pre_enable_dp;
6029 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 6030 if (INTEL_INFO(dev)->gen >= 5)
6031 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 6032 }
f0fec3f2 6033
174edf1f 6034 intel_dig_port->port = port;
f0fec3f2
PZ		 6035 intel_dig_port->dp.output_reg = output_reg;
6036
00c09d70 6037 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 6038 if (IS_CHERRYVIEW(dev)) {
6039 if (port == PORT_D)
6040 intel_encoder->crtc_mask = 1 << 2;
6041 else
6042 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6043 } else {
6044 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6045 }
bc079e8b 6046 intel_encoder->cloneable = 0;
f0fec3f2 6047
13cf5504 6048 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 6049 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 6050
11aee0f6
SM		 6051 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6052 goto err_init_connector;
6053
6054 return;
6055
6056err_init_connector:
6057 drm_encoder_cleanup(encoder);
6058 kfree(intel_connector);
6059err_connector_alloc:
6060 kfree(intel_dig_port);
6061
6062 return;
f0fec3f2 6063}
0e32b39c
DA		 6064
6065void intel_dp_mst_suspend(struct drm_device *dev)
6066{
6067 struct drm_i915_private *dev_priv = dev->dev_private;
6068 int i;
6069
6070 /* disable MST */
6071 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6072 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6073 if (!intel_dig_port)
6074 continue;
6075
6076 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6077 if (!intel_dig_port->dp.can_mst)
6078 continue;
6079 if (intel_dig_port->dp.is_mst)
6080 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6081 }
6082 }
6083}
6084
6085void intel_dp_mst_resume(struct drm_device *dev)
6086{
6087 struct drm_i915_private *dev_priv = dev->dev_private;
6088 int i;
6089
6090 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6091 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6092 if (!intel_dig_port)
6093 continue;
6094 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6095 int ret;
6096
6097 if (!intel_dig_port->dp.can_mst)
6098 continue;
6099
6100 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6101 if (ret != 0) {
6102 intel_dp_check_mst_status(&intel_dig_port->dp);
6103 }
6104 }
6105 }
6106}
Linux kernel - Deliverables
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