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drm/i915/dp: use the new drm helpers for dp aux
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780
DV		 95static void edp_panel_vdd_on(struct intel_dp *intel_dp);
96static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 97
a4fc5ed6 98static int
ea5b213a 99intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 100{
7183dc29 101 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 102 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 103
104 switch (max_link_bw) {
105 case DP_LINK_BW_1_62:
106 case DP_LINK_BW_2_7:
107 break;
d4eead50 108 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 109 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
111 max_link_bw = DP_LINK_BW_5_4;
112 else
113 max_link_bw = DP_LINK_BW_2_7;
d4eead50 114 break;
a4fc5ed6 115 default:
d4eead50
ID		 116 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw);
a4fc5ed6
KP		 118 max_link_bw = DP_LINK_BW_1_62;
119 break;
120 }
121 return max_link_bw;
122}
123
cd9dde44
AJ		 124/*
125 * The units on the numbers in the next two are... bizarre. Examples will
126 * make it clearer; this one parallels an example in the eDP spec.
127 *
128 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
129 *
130 * 270000 * 1 * 8 / 10 == 216000
131 *
132 * The actual data capacity of that configuration is 2.16Gbit/s, so the
133 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
134 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
135 * 119000. At 18bpp that's 2142000 kilobits per second.
136 *
137 * Thus the strange-looking division by 10 in intel_dp_link_required, to
138 * get the result in decakilobits instead of kilobits.
139 */
140
a4fc5ed6 141static int
c898261c 142intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 143{
cd9dde44 144 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 145}
146
fe27d53e
DA		 147static int
148intel_dp_max_data_rate(int max_link_clock, int max_lanes)
149{
150 return (max_link_clock * max_lanes * 8) / 10;
151}
152
c19de8eb 153static enum drm_mode_status
a4fc5ed6
KP		 154intel_dp_mode_valid(struct drm_connector *connector,
155 struct drm_display_mode *mode)
156{
df0e9248 157 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 158 struct intel_connector *intel_connector = to_intel_connector(connector);
159 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 160 int target_clock = mode->clock;
161 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 162
dd06f90e
JN		 163 if (is_edp(intel_dp) && fixed_mode) {
164 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 165 return MODE_PANEL;
166
dd06f90e 167 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 168 return MODE_PANEL;
03afc4a2
DV		 169
170 target_clock = fixed_mode->clock;
7de56f43
ZY		 171 }
172
36008365
DV		 173 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
174 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
175
176 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
177 mode_rate = intel_dp_link_required(target_clock, 18);
178
179 if (mode_rate > max_rate)
c4867936 180 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 181
182 if (mode->clock < 10000)
183 return MODE_CLOCK_LOW;
184
0af78a2b
DV		 185 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
186 return MODE_H_ILLEGAL;
187
a4fc5ed6
KP		 188 return MODE_OK;
189}
190
191static uint32_t
192pack_aux(uint8_t *src, int src_bytes)
193{
194 int i;
195 uint32_t v = 0;
196
197 if (src_bytes > 4)
198 src_bytes = 4;
199 for (i = 0; i < src_bytes; i++)
200 v |= ((uint32_t) src[i]) << ((3-i) * 8);
201 return v;
202}
203
204static void
205unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
206{
207 int i;
208 if (dst_bytes > 4)
209 dst_bytes = 4;
210 for (i = 0; i < dst_bytes; i++)
211 dst[i] = src >> ((3-i) * 8);
212}
213
fb0f8fbf
KP		 214/* hrawclock is 1/4 the FSB frequency */
215static int
216intel_hrawclk(struct drm_device *dev)
217{
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 uint32_t clkcfg;
220
9473c8f4
VP		 221 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
222 if (IS_VALLEYVIEW(dev))
223 return 200;
224
fb0f8fbf
KP		 225 clkcfg = I915_READ(CLKCFG);
226 switch (clkcfg & CLKCFG_FSB_MASK) {
227 case CLKCFG_FSB_400:
228 return 100;
229 case CLKCFG_FSB_533:
230 return 133;
231 case CLKCFG_FSB_667:
232 return 166;
233 case CLKCFG_FSB_800:
234 return 200;
235 case CLKCFG_FSB_1067:
236 return 266;
237 case CLKCFG_FSB_1333:
238 return 333;
239 /* these two are just a guess; one of them might be right */
240 case CLKCFG_FSB_1600:
241 case CLKCFG_FSB_1600_ALT:
242 return 400;
243 default:
244 return 133;
245 }
246}
247
bf13e81b
JN		 248static void
249intel_dp_init_panel_power_sequencer(struct drm_device *dev,
250 struct intel_dp *intel_dp,
251 struct edp_power_seq *out);
252static void
253intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
254 struct intel_dp *intel_dp,
255 struct edp_power_seq *out);
256
257static enum pipe
258vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
259{
260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
261 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
262 struct drm_device *dev = intel_dig_port->base.base.dev;
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 enum port port = intel_dig_port->port;
265 enum pipe pipe;
266
267 /* modeset should have pipe */
268 if (crtc)
269 return to_intel_crtc(crtc)->pipe;
270
271 /* init time, try to find a pipe with this port selected */
272 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
273 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
274 PANEL_PORT_SELECT_MASK;
275 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
276 return pipe;
277 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
278 return pipe;
279 }
280
281 /* shrug */
282 return PIPE_A;
283}
284
285static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
286{
287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
288
289 if (HAS_PCH_SPLIT(dev))
290 return PCH_PP_CONTROL;
291 else
292 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
293}
294
295static u32 _pp_stat_reg(struct intel_dp *intel_dp)
296{
297 struct drm_device *dev = intel_dp_to_dev(intel_dp);
298
299 if (HAS_PCH_SPLIT(dev))
300 return PCH_PP_STATUS;
301 else
302 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
303}
304
4be73780 305static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 311}
312
4be73780 313static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 314{
30add22d 315 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 316 struct drm_i915_private *dev_priv = dev->dev_private;
317
bf13e81b 318 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 319}
320
9b984dae
KP		 321static void
322intel_dp_check_edp(struct intel_dp *intel_dp)
323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 325 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 326
9b984dae
KP		 327 if (!is_edp(intel_dp))
328 return;
453c5420 329
4be73780 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 335 }
336}
337
9ee32fea
DV		 338static uint32_t
339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
340{
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 345 uint32_t status;
346 bool done;
347
ef04f00d 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 349 if (has_aux_irq)
b18ac466 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 351 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 352 else
353 done = wait_for_atomic(C, 10) == 0;
354 if (!done)
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
356 has_aux_irq);
357#undef C
358
359 return status;
360}
361
ec5b01dd 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 363{
174edf1f
PZ		 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 366
ec5b01dd
DL		 367 /*
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 370 */
ec5b01dd
DL		 371 return index ? 0 : intel_hrawclk(dev) / 2;
372}
373
374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
375{
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
378
379 if (index)
380 return 0;
381
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 385 else
b84a1cf8 386 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 387 } else {
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 }
390}
391
392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
393{
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397
398 if (intel_dig_port->port == PORT_A) {
399 if (index)
400 return 0;
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
bc86625a
CW		 404 switch (index) {
405 case 0: return 63;
406 case 1: return 72;
407 default: return 0;
408 }
ec5b01dd 409 } else {
bc86625a 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 411 }
b84a1cf8
RV		 412}
413
ec5b01dd
DL		 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 return index ? 0 : 100;
417}
418
5ed12a19
DL		 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
420 bool has_aux_irq,
421 int send_bytes,
422 uint32_t aux_clock_divider)
423{
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
427
428 if (IS_GEN6(dev))
429 precharge = 3;
430 else
431 precharge = 5;
432
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
435 else
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
437
438 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 439 DP_AUX_CH_CTL_DONE |
5ed12a19 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 442 timeout |
788d4433 443 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 447}
448
b84a1cf8
RV		 449static int
450intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
453{
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
bc86625a 459 uint32_t aux_clock_divider;
b84a1cf8
RV		 460 int i, ret, recv_bytes;
461 uint32_t status;
5ed12a19 462 int try, clock = 0;
4e6b788c 463 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 464 bool vdd;
465
466 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 467
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
470 * deep sleep states.
471 */
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
473
474 intel_dp_check_edp(intel_dp);
5eb08b69 475
c67a470b
PZ		 476 intel_aux_display_runtime_get(dev_priv);
477
11bee43e
JB		 478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
ef04f00d 480 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
482 break;
483 msleep(1);
484 }
485
486 if (try == 3) {
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
488 I915_READ(ch_ctl));
9ee32fea
DV		 489 ret = -EBUSY;
490 goto out;
4f7f7b7e
CW		 491 }
492
46a5ae9f
PZ		 493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
495 ret = -E2BIG;
496 goto out;
497 }
498
ec5b01dd 499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
501 has_aux_irq,
502 send_bytes,
503 aux_clock_divider);
5ed12a19 504
bc86625a
CW		 505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
511
512 /* Send the command and wait for it to complete */
5ed12a19 513 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 514
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
516
517 /* Clear done status and any errors */
518 I915_WRITE(ch_ctl,
519 status |
520 DP_AUX_CH_CTL_DONE |
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
523
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
526 continue;
527 if (status & DP_AUX_CH_CTL_DONE)
528 break;
529 }
4f7f7b7e 530 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 531 break;
532 }
533
a4fc5ed6 534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 536 ret = -EBUSY;
537 goto out;
a4fc5ed6
KP		 538 }
539
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
542 */
a5b3da54 543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 545 ret = -EIO;
546 goto out;
a5b3da54 547 }
1ae8c0a5
KP		 548
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
a5b3da54 551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 553 ret = -ETIMEDOUT;
554 goto out;
a4fc5ed6
KP		 555 }
556
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
0206e353 562
4f7f7b7e
CW		 563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
a4fc5ed6 566
9ee32fea
DV		 567 ret = recv_bytes;
568out:
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 570 intel_aux_display_runtime_put(dev_priv);
9ee32fea 571
884f19e9
JN		 572 if (vdd)
573 edp_panel_vdd_off(intel_dp, false);
574
9ee32fea 575 return ret;
a4fc5ed6
KP		 576}
577
9d1a1031
JN		 578#define HEADER_SIZE 4
579static ssize_t
580intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 581{
9d1a1031
JN		 582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
583 uint8_t txbuf[20], rxbuf[20];
584 size_t txsize, rxsize;
a4fc5ed6 585 int ret;
a4fc5ed6 586
9d1a1031
JN		 587 txbuf[0] = msg->request << 4;
588 txbuf[1] = msg->address >> 8;
589 txbuf[2] = msg->address & 0xff;
590 txbuf[3] = msg->size - 1;
46a5ae9f 591
9d1a1031
JN		 592 switch (msg->request & ~DP_AUX_I2C_MOT) {
593 case DP_AUX_NATIVE_WRITE:
594 case DP_AUX_I2C_WRITE:
595 txsize = HEADER_SIZE + msg->size;
596 rxsize = 1;
f51a44b9 597
9d1a1031
JN		 598 if (WARN_ON(txsize > 20))
599 return -E2BIG;
a4fc5ed6 600
9d1a1031 601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 602
9d1a1031
JN		 603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
604 if (ret > 0) {
605 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 606
9d1a1031
JN		 607 /* Return payload size. */
608 ret = msg->size;
609 }
610 break;
46a5ae9f 611
9d1a1031
JN		 612 case DP_AUX_NATIVE_READ:
613 case DP_AUX_I2C_READ:
614 txsize = HEADER_SIZE;
615 rxsize = msg->size + 1;
a4fc5ed6 616
9d1a1031
JN		 617 if (WARN_ON(rxsize > 20))
618 return -E2BIG;
a4fc5ed6 619
9d1a1031
JN		 620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
621 if (ret > 0) {
622 msg->reply = rxbuf[0] >> 4;
623 /*
624 * Assume happy day, and copy the data. The caller is
625 * expected to check msg->reply before touching it.
626 *
627 * Return payload size.
628 */
629 ret--;
630 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 631 }
9d1a1031
JN		 632 break;
633
634 default:
635 ret = -EINVAL;
636 break;
a4fc5ed6 637 }
f51a44b9 638
9d1a1031
JN		 639 return ret;
640}
641
642static void
643intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
644{
645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
646
647 intel_dp->aux.dev = dev->dev;
648 intel_dp->aux.transfer = intel_dp_aux_transfer;
a4fc5ed6
KP		 649}
650
651static int
ab2c0672
DA		 652intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
653 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 654{
ab2c0672 655 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 656 struct intel_dp *intel_dp = container_of(adapter,
657 struct intel_dp,
658 adapter);
ab2c0672
DA		 659 uint16_t address = algo_data->address;
660 uint8_t msg[5];
661 uint8_t reply[2];
8316f337 662 unsigned retry;
ab2c0672
DA		 663 int msg_bytes;
664 int reply_bytes;
665 int ret;
666
667 /* Set up the command byte */
668 if (mode & MODE_I2C_READ)
6b27f7f0 669 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 670 else
6b27f7f0 671 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 672
673 if (!(mode & MODE_I2C_STOP))
6b27f7f0 674 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 675
ab2c0672
DA		 676 msg[1] = address >> 8;
677 msg[2] = address;
678
679 switch (mode) {
680 case MODE_I2C_WRITE:
681 msg[3] = 0;
682 msg[4] = write_byte;
683 msg_bytes = 5;
684 reply_bytes = 1;
685 break;
686 case MODE_I2C_READ:
687 msg[3] = 0;
688 msg_bytes = 4;
689 reply_bytes = 2;
690 break;
691 default:
692 msg_bytes = 3;
693 reply_bytes = 1;
694 break;
695 }
696
58c67ce9
JN		 697 /*
698 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
699 * required to retry at least seven times upon receiving AUX_DEFER
700 * before giving up the AUX transaction.
701 */
702 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 703 ret = intel_dp_aux_ch(intel_dp,
704 msg, msg_bytes,
705 reply, reply_bytes);
ab2c0672 706 if (ret < 0) {
3ff99164 707 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 708 goto out;
ab2c0672 709 }
8316f337 710
6b27f7f0
TR		 711 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
712 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 713 /* I2C-over-AUX Reply field is only valid
714 * when paired with AUX ACK.
715 */
716 break;
6b27f7f0 717 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 718 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 719 ret = -EREMOTEIO;
720 goto out;
6b27f7f0 721 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 722 /*
723 * For now, just give more slack to branch devices. We
724 * could check the DPCD for I2C bit rate capabilities,
725 * and if available, adjust the interval. We could also
726 * be more careful with DP-to-Legacy adapters where a
727 * long legacy cable may force very low I2C bit rates.
728 */
729 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
730 DP_DWN_STRM_PORT_PRESENT)
731 usleep_range(500, 600);
732 else
733 usleep_range(300, 400);
8316f337
DF		 734 continue;
735 default:
736 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
737 reply[0]);
8a5e6aeb
PZ		 738 ret = -EREMOTEIO;
739 goto out;
8316f337
DF		 740 }
741
6b27f7f0
TR		 742 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
743 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 744 if (mode == MODE_I2C_READ) {
745 *read_byte = reply[1];
746 }
8a5e6aeb
PZ		 747 ret = reply_bytes - 1;
748 goto out;
6b27f7f0 749 case DP_AUX_I2C_REPLY_NACK:
8316f337 750 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 751 ret = -EREMOTEIO;
752 goto out;
6b27f7f0 753 case DP_AUX_I2C_REPLY_DEFER:
8316f337 754 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 755 udelay(100);
756 break;
757 default:
8316f337 758 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 759 ret = -EREMOTEIO;
760 goto out;
ab2c0672
DA		 761 }
762 }
8316f337
DF		 763
764 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 765 ret = -EREMOTEIO;
766
767out:
8a5e6aeb 768 return ret;
a4fc5ed6
KP		 769}
770
80f65de3
ID		 771static void
772intel_dp_connector_unregister(struct intel_connector *intel_connector)
773{
774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
775
776 sysfs_remove_link(&intel_connector->base.kdev->kobj,
777 intel_dp->adapter.dev.kobj.name);
778 intel_connector_unregister(intel_connector);
779}
780
a4fc5ed6 781static int
ea5b213a 782intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 783 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 784{
0b5c541b
KP		 785 int ret;
786
d54e9d28 787 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 788 intel_dp->algo.running = false;
789 intel_dp->algo.address = 0;
790 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
791
0206e353 792 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 793 intel_dp->adapter.owner = THIS_MODULE;
794 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 795 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 796 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
797 intel_dp->adapter.algo_data = &intel_dp->algo;
80f65de3 798 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
ea5b213a 799
0b5c541b 800 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
80f65de3
ID		 801 if (ret < 0)
802 return ret;
803
804 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
805 &intel_dp->adapter.dev.kobj,
806 intel_dp->adapter.dev.kobj.name);
807
808 if (ret < 0)
809 i2c_del_adapter(&intel_dp->adapter);
810
0b5c541b 811 return ret;
a4fc5ed6
KP		 812}
813
c6bb3538
DV		 814static void
815intel_dp_set_clock(struct intel_encoder *encoder,
816 struct intel_crtc_config *pipe_config, int link_bw)
817{
818 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 819 const struct dp_link_dpll *divisor = NULL;
820 int i, count = 0;
c6bb3538
DV		 821
822 if (IS_G4X(dev)) {
9dd4ffdf
CML		 823 divisor = gen4_dpll;
824 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 825 } else if (IS_HASWELL(dev)) {
826 /* Haswell has special-purpose DP DDI clocks. */
827 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 828 divisor = pch_dpll;
829 count = ARRAY_SIZE(pch_dpll);
c6bb3538 830 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 831 divisor = vlv_dpll;
832 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 833 }
9dd4ffdf
CML		 834
835 if (divisor && count) {
836 for (i = 0; i < count; i++) {
837 if (link_bw == divisor[i].link_bw) {
838 pipe_config->dpll = divisor[i].dpll;
839 pipe_config->clock_set = true;
840 break;
841 }
842 }
c6bb3538
DV		 843 }
844}
845
00c09d70 846bool
5bfe2ac0
DV		 847intel_dp_compute_config(struct intel_encoder *encoder,
848 struct intel_crtc_config *pipe_config)
a4fc5ed6 849{
5bfe2ac0 850 struct drm_device *dev = encoder->base.dev;
36008365 851 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 852 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 853 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 854 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 855 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 856 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 857 int lane_count, clock;
397fe157 858 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 859 /* Conveniently, the link BW constants become indices with a shift...*/
860 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 861 int bpp, mode_rate;
06ea66b6 862 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 863 int link_avail, link_clock;
a4fc5ed6 864
bc7d38a4 865 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 866 pipe_config->has_pch_encoder = true;
867
03afc4a2 868 pipe_config->has_dp_encoder = true;
a4fc5ed6 869
dd06f90e
JN		 870 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
871 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
872 adjusted_mode);
2dd24552
JB		 873 if (!HAS_PCH_SPLIT(dev))
874 intel_gmch_panel_fitting(intel_crtc, pipe_config,
875 intel_connector->panel.fitting_mode);
876 else
b074cec8
JB		 877 intel_pch_panel_fitting(intel_crtc, pipe_config,
878 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 879 }
880
cb1793ce 881 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 882 return false;
883
083f9560
DV		 884 DRM_DEBUG_KMS("DP link computation with max lane count %i "
885 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 886 max_lane_count, bws[max_clock],
887 adjusted_mode->crtc_clock);
083f9560 888
36008365
DV		 889 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
890 * bpc in between. */
3e7ca985 891 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 892 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
893 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 894 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
895 dev_priv->vbt.edp_bpp);
6da7f10d 896 bpp = dev_priv->vbt.edp_bpp;
7984211e 897 }
657445fe 898
36008365 899 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 900 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
901 bpp);
36008365 902
38aecea0
DV		 903 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
904 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 905 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
906 link_avail = intel_dp_max_data_rate(link_clock,
907 lane_count);
908
909 if (mode_rate <= link_avail) {
910 goto found;
911 }
912 }
913 }
914 }
c4867936 915
36008365 916 return false;
3685a8f3 917
36008365 918found:
55bc60db
VS		 919 if (intel_dp->color_range_auto) {
920 /*
921 * See:
922 * CEA-861-E - 5.1 Default Encoding Parameters
923 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
924 */
18316c8c 925 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 926 intel_dp->color_range = DP_COLOR_RANGE_16_235;
927 else
928 intel_dp->color_range = 0;
929 }
930
3685a8f3 931 if (intel_dp->color_range)
50f3b016 932 pipe_config->limited_color_range = true;
a4fc5ed6 933
36008365
DV		 934 intel_dp->link_bw = bws[clock];
935 intel_dp->lane_count = lane_count;
657445fe 936 pipe_config->pipe_bpp = bpp;
ff9a6750 937 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 938
36008365
DV		 939 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
940 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 941 pipe_config->port_clock, bpp);
36008365
DV		 942 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
943 mode_rate, link_avail);
a4fc5ed6 944
03afc4a2 945 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 946 adjusted_mode->crtc_clock,
947 pipe_config->port_clock,
03afc4a2 948 &pipe_config->dp_m_n);
9d1a455b 949
c6bb3538
DV		 950 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
951
03afc4a2 952 return true;
a4fc5ed6
KP		 953}
954
7c62a164 955static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 956{
7c62a164
DV		 957 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
958 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
959 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 960 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 dpa_ctl;
962
ff9a6750 963 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 964 dpa_ctl = I915_READ(DP_A);
965 dpa_ctl &= ~DP_PLL_FREQ_MASK;
966
ff9a6750 967 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 968 /* For a long time we've carried around a ILK-DevA w/a for the
969 * 160MHz clock. If we're really unlucky, it's still required.
970 */
971 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 972 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 973 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 974 } else {
975 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 976 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 977 }
1ce17038 978
ea9b6006
DV		 979 I915_WRITE(DP_A, dpa_ctl);
980
981 POSTING_READ(DP_A);
982 udelay(500);
983}
984
b934223d 985static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 986{
b934223d 987 struct drm_device *dev = encoder->base.dev;
417e822d 988 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 989 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 990 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 991 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
992 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 993
417e822d 994 /*
1a2eb460 995 * There are four kinds of DP registers:
417e822d
KP		 996 *
997 * IBX PCH
1a2eb460
KP		 998 * SNB CPU
999 * IVB CPU
417e822d
KP		 1000 * CPT PCH
1001 *
1002 * IBX PCH and CPU are the same for almost everything,
1003 * except that the CPU DP PLL is configured in this
1004 * register
1005 *
1006 * CPT PCH is quite different, having many bits moved
1007 * to the TRANS_DP_CTL register instead. That
1008 * configuration happens (oddly) in ironlake_pch_enable
1009 */
9c9e7927 1010
417e822d
KP		 1011 /* Preserve the BIOS-computed detected bit. This is
1012 * supposed to be read-only.
1013 */
1014 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1015
417e822d 1016 /* Handle DP bits in common between all three register formats */
417e822d 1017 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1018 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1019
e0dac65e
WF		 1020 if (intel_dp->has_audio) {
1021 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1022 pipe_name(crtc->pipe));
ea5b213a 1023 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1024 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1025 }
247d89f6 1026
417e822d 1027 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1028
bc7d38a4 1029 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1030 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1031 intel_dp->DP |= DP_SYNC_HS_HIGH;
1032 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1033 intel_dp->DP |= DP_SYNC_VS_HIGH;
1034 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1035
6aba5b6c 1036 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1037 intel_dp->DP |= DP_ENHANCED_FRAMING;
1038
7c62a164 1039 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1040 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1041 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1042 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1043
1044 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1045 intel_dp->DP |= DP_SYNC_HS_HIGH;
1046 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1047 intel_dp->DP |= DP_SYNC_VS_HIGH;
1048 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1049
6aba5b6c 1050 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1051 intel_dp->DP |= DP_ENHANCED_FRAMING;
1052
7c62a164 1053 if (crtc->pipe == 1)
417e822d 1054 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1055 } else {
1056 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1057 }
ea9b6006 1058
bc7d38a4 1059 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1060 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1061}
1062
ffd6749d
PZ		 1063#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1064#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1065
1a5ef5b7
PZ		 1066#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1067#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1068
ffd6749d
PZ		 1069#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1070#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1071
4be73780 1072static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1073 u32 mask,
1074 u32 value)
bd943159 1075{
30add22d 1076 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1077 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1078 u32 pp_stat_reg, pp_ctrl_reg;
1079
bf13e81b
JN		 1080 pp_stat_reg = _pp_stat_reg(intel_dp);
1081 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1082
99ea7127 1083 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1084 mask, value,
1085 I915_READ(pp_stat_reg),
1086 I915_READ(pp_ctrl_reg));
32ce697c 1087
453c5420 1088 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1089 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1090 I915_READ(pp_stat_reg),
1091 I915_READ(pp_ctrl_reg));
32ce697c 1092 }
54c136d4
CW		 1093
1094 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1095}
32ce697c 1096
4be73780 1097static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1098{
1099 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1100 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1101}
1102
4be73780 1103static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1104{
1105 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1106 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1107}
1108
4be73780 1109static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1110{
1111 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1112
1113 /* When we disable the VDD override bit last we have to do the manual
1114 * wait. */
1115 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1116 intel_dp->panel_power_cycle_delay);
1117
4be73780 1118 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1119}
1120
4be73780 1121static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1122{
1123 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1124 intel_dp->backlight_on_delay);
1125}
1126
4be73780 1127static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1128{
1129 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1130 intel_dp->backlight_off_delay);
1131}
99ea7127 1132
832dd3c1
KP		 1133/* Read the current pp_control value, unlocking the register if it
1134 * is locked
1135 */
1136
453c5420 1137static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1138{
453c5420
JB		 1139 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 u32 control;
832dd3c1 1142
bf13e81b 1143 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1144 control &= ~PANEL_UNLOCK_MASK;
1145 control |= PANEL_UNLOCK_REGS;
1146 return control;
bd943159
KP		 1147}
1148
adddaaf4 1149static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1150{
30add22d 1151 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1152 struct drm_i915_private *dev_priv = dev->dev_private;
1153 u32 pp;
453c5420 1154 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1155 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1156
97af61f5 1157 if (!is_edp(intel_dp))
adddaaf4 1158 return false;
bd943159
KP		 1159
1160 intel_dp->want_panel_vdd = true;
99ea7127 1161
4be73780 1162 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1163 return need_to_disable;
b0665d57 1164
e9cb81a2
PZ		 1165 intel_runtime_pm_get(dev_priv);
1166
b0665d57 1167 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1168
4be73780
DV		 1169 if (!edp_have_panel_power(intel_dp))
1170 wait_panel_power_cycle(intel_dp);
99ea7127 1171
453c5420 1172 pp = ironlake_get_pp_control(intel_dp);
5d613501 1173 pp |= EDP_FORCE_VDD;
ebf33b18 1174
bf13e81b
JN		 1175 pp_stat_reg = _pp_stat_reg(intel_dp);
1176 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1177
1178 I915_WRITE(pp_ctrl_reg, pp);
1179 POSTING_READ(pp_ctrl_reg);
1180 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1181 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1182 /*
1183 * If the panel wasn't on, delay before accessing aux channel
1184 */
4be73780 1185 if (!edp_have_panel_power(intel_dp)) {
bd943159 1186 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1187 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1188 }
adddaaf4
JN		 1189
1190 return need_to_disable;
1191}
1192
1193static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1194{
1195 if (is_edp(intel_dp)) {
1196 bool vdd = _edp_panel_vdd_on(intel_dp);
1197
1198 WARN(!vdd, "eDP VDD already requested on\n");
1199 }
5d613501
JB		 1200}
1201
4be73780 1202static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1203{
30add22d 1204 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 u32 pp;
453c5420 1207 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1208
a0e99e68
DV		 1209 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1210
4be73780 1211 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1212 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1213
453c5420 1214 pp = ironlake_get_pp_control(intel_dp);
bd943159 1215 pp &= ~EDP_FORCE_VDD;
bd943159 1216
9f08ef59
PZ		 1217 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1218 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1219
1220 I915_WRITE(pp_ctrl_reg, pp);
1221 POSTING_READ(pp_ctrl_reg);
99ea7127 1222
453c5420
JB		 1223 /* Make sure sequencer is idle before allowing subsequent activity */
1224 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1225 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1226
1227 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1228 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1229
1230 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1231 }
1232}
5d613501 1233
4be73780 1234static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1235{
1236 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1237 struct intel_dp, panel_vdd_work);
30add22d 1238 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1239
627f7675 1240 mutex_lock(&dev->mode_config.mutex);
4be73780 1241 edp_panel_vdd_off_sync(intel_dp);
627f7675 1242 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1243}
1244
4be73780 1245static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1246{
97af61f5
KP		 1247 if (!is_edp(intel_dp))
1248 return;
5d613501 1249
bd943159 1250 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1251
bd943159
KP		 1252 intel_dp->want_panel_vdd = false;
1253
1254 if (sync) {
4be73780 1255 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1256 } else {
1257 /*
1258 * Queue the timer to fire a long
1259 * time from now (relative to the power down delay)
1260 * to keep the panel power up across a sequence of operations
1261 */
1262 schedule_delayed_work(&intel_dp->panel_vdd_work,
1263 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1264 }
5d613501
JB		 1265}
1266
4be73780 1267void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1268{
30add22d 1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1270 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1271 u32 pp;
453c5420 1272 u32 pp_ctrl_reg;
9934c132 1273
97af61f5 1274 if (!is_edp(intel_dp))
bd943159 1275 return;
99ea7127
KP		 1276
1277 DRM_DEBUG_KMS("Turn eDP power on\n");
1278
4be73780 1279 if (edp_have_panel_power(intel_dp)) {
99ea7127 1280 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1281 return;
99ea7127 1282 }
9934c132 1283
4be73780 1284 wait_panel_power_cycle(intel_dp);
37c6c9b0 1285
bf13e81b 1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1287 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1288 if (IS_GEN5(dev)) {
1289 /* ILK workaround: disable reset around power sequence */
1290 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
05ce1a49 1293 }
37c6c9b0 1294
1c0ae80a 1295 pp |= POWER_TARGET_ON;
99ea7127
KP		 1296 if (!IS_GEN5(dev))
1297 pp |= PANEL_POWER_RESET;
1298
453c5420
JB		 1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
9934c132 1301
4be73780 1302 wait_panel_on(intel_dp);
dce56b3c 1303 intel_dp->last_power_on = jiffies;
9934c132 1304
05ce1a49
KP		 1305 if (IS_GEN5(dev)) {
1306 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1307 I915_WRITE(pp_ctrl_reg, pp);
1308 POSTING_READ(pp_ctrl_reg);
05ce1a49 1309 }
9934c132
JB		 1310}
1311
4be73780 1312void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1313{
30add22d 1314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1315 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1316 u32 pp;
453c5420 1317 u32 pp_ctrl_reg;
9934c132 1318
97af61f5
KP		 1319 if (!is_edp(intel_dp))
1320 return;
37c6c9b0 1321
99ea7127 1322 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1323
4be73780 1324 edp_wait_backlight_off(intel_dp);
dce56b3c 1325
453c5420 1326 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1327 /* We need to switch off panel power _and_ force vdd, for otherwise some
1328 * panels get very unhappy and cease to work. */
b3064154
PJ		 1329 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1330 EDP_BLC_ENABLE);
453c5420 1331
bf13e81b 1332 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1333
1334 I915_WRITE(pp_ctrl_reg, pp);
1335 POSTING_READ(pp_ctrl_reg);
9934c132 1336
dce56b3c 1337 intel_dp->last_power_cycle = jiffies;
4be73780 1338 wait_panel_off(intel_dp);
9934c132
JB		 1339}
1340
4be73780 1341void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1342{
da63a9f2
PZ		 1343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1344 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 u32 pp;
453c5420 1347 u32 pp_ctrl_reg;
32f9d658 1348
f01eca2e
KP		 1349 if (!is_edp(intel_dp))
1350 return;
1351
28c97730 1352 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1353 /*
1354 * If we enable the backlight right away following a panel power
1355 * on, we may see slight flicker as the panel syncs with the eDP
1356 * link. So delay a bit to make sure the image is solid before
1357 * allowing it to appear.
1358 */
4be73780 1359 wait_backlight_on(intel_dp);
453c5420 1360 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1361 pp |= EDP_BLC_ENABLE;
453c5420 1362
bf13e81b 1363 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1364
1365 I915_WRITE(pp_ctrl_reg, pp);
1366 POSTING_READ(pp_ctrl_reg);
035aa3de 1367
752aa88a 1368 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1369}
1370
4be73780 1371void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1372{
30add22d 1373 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 u32 pp;
453c5420 1376 u32 pp_ctrl_reg;
32f9d658 1377
f01eca2e
KP		 1378 if (!is_edp(intel_dp))
1379 return;
1380
752aa88a 1381 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1382
28c97730 1383 DRM_DEBUG_KMS("\n");
453c5420 1384 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1385 pp &= ~EDP_BLC_ENABLE;
453c5420 1386
bf13e81b 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1388
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
dce56b3c 1391 intel_dp->last_backlight_off = jiffies;
32f9d658 1392}
a4fc5ed6 1393
2bd2ad64 1394static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1395{
da63a9f2
PZ		 1396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1397 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1398 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1399 struct drm_i915_private *dev_priv = dev->dev_private;
1400 u32 dpa_ctl;
1401
2bd2ad64
DV		 1402 assert_pipe_disabled(dev_priv,
1403 to_intel_crtc(crtc)->pipe);
1404
d240f20f
JB		 1405 DRM_DEBUG_KMS("\n");
1406 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1407 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1408 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1409
1410 /* We don't adjust intel_dp->DP while tearing down the link, to
1411 * facilitate link retraining (e.g. after hotplug). Hence clear all
1412 * enable bits here to ensure that we don't enable too much. */
1413 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1414 intel_dp->DP |= DP_PLL_ENABLE;
1415 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1416 POSTING_READ(DP_A);
1417 udelay(200);
d240f20f
JB		 1418}
1419
2bd2ad64 1420static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1421{
da63a9f2
PZ		 1422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1423 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1424 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 u32 dpa_ctl;
1427
2bd2ad64
DV		 1428 assert_pipe_disabled(dev_priv,
1429 to_intel_crtc(crtc)->pipe);
1430
d240f20f 1431 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1432 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1433 "dp pll off, should be on\n");
1434 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1435
1436 /* We can't rely on the value tracked for the DP register in
1437 * intel_dp->DP because link_down must not change that (otherwise link
1438 * re-training will fail. */
298b0b39 1439 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1440 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1441 POSTING_READ(DP_A);
d240f20f
JB		 1442 udelay(200);
1443}
1444
c7ad3810 1445/* If the sink supports it, try to set the power state appropriately */
c19b0669 1446void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1447{
1448 int ret, i;
1449
1450 /* Should have a valid DPCD by this point */
1451 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1452 return;
1453
1454 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1455 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1456 DP_SET_POWER_D3);
c7ad3810
JB		 1457 if (ret != 1)
1458 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1459 } else {
1460 /*
1461 * When turning on, we need to retry for 1ms to give the sink
1462 * time to wake up.
1463 */
1464 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1465 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1466 DP_SET_POWER_D0);
c7ad3810
JB		 1467 if (ret == 1)
1468 break;
1469 msleep(1);
1470 }
1471 }
1472}
1473
19d8fe15
DV		 1474static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1475 enum pipe *pipe)
d240f20f 1476{
19d8fe15 1477 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1478 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1479 struct drm_device *dev = encoder->base.dev;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1481 enum intel_display_power_domain power_domain;
1482 u32 tmp;
1483
1484 power_domain = intel_display_port_power_domain(encoder);
1485 if (!intel_display_power_enabled(dev_priv, power_domain))
1486 return false;
1487
1488 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1489
1490 if (!(tmp & DP_PORT_EN))
1491 return false;
1492
bc7d38a4 1493 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1494 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1495 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1496 *pipe = PORT_TO_PIPE(tmp);
1497 } else {
1498 u32 trans_sel;
1499 u32 trans_dp;
1500 int i;
1501
1502 switch (intel_dp->output_reg) {
1503 case PCH_DP_B:
1504 trans_sel = TRANS_DP_PORT_SEL_B;
1505 break;
1506 case PCH_DP_C:
1507 trans_sel = TRANS_DP_PORT_SEL_C;
1508 break;
1509 case PCH_DP_D:
1510 trans_sel = TRANS_DP_PORT_SEL_D;
1511 break;
1512 default:
1513 return true;
1514 }
1515
1516 for_each_pipe(i) {
1517 trans_dp = I915_READ(TRANS_DP_CTL(i));
1518 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1519 *pipe = i;
1520 return true;
1521 }
1522 }
19d8fe15 1523
4a0833ec
DV		 1524 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1525 intel_dp->output_reg);
1526 }
d240f20f 1527
19d8fe15
DV		 1528 return true;
1529}
d240f20f 1530
045ac3b5
JB		 1531static void intel_dp_get_config(struct intel_encoder *encoder,
1532 struct intel_crtc_config *pipe_config)
1533{
1534 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1535 u32 tmp, flags = 0;
63000ef6
XZ		 1536 struct drm_device *dev = encoder->base.dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 enum port port = dp_to_dig_port(intel_dp)->port;
1539 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1540 int dotclock;
045ac3b5 1541
63000ef6
XZ		 1542 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1543 tmp = I915_READ(intel_dp->output_reg);
1544 if (tmp & DP_SYNC_HS_HIGH)
1545 flags |= DRM_MODE_FLAG_PHSYNC;
1546 else
1547 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1548
63000ef6
XZ		 1549 if (tmp & DP_SYNC_VS_HIGH)
1550 flags |= DRM_MODE_FLAG_PVSYNC;
1551 else
1552 flags |= DRM_MODE_FLAG_NVSYNC;
1553 } else {
1554 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1555 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1556 flags |= DRM_MODE_FLAG_PHSYNC;
1557 else
1558 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1559
63000ef6
XZ		 1560 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1561 flags |= DRM_MODE_FLAG_PVSYNC;
1562 else
1563 flags |= DRM_MODE_FLAG_NVSYNC;
1564 }
045ac3b5
JB		 1565
1566 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1567
eb14cb74
VS		 1568 pipe_config->has_dp_encoder = true;
1569
1570 intel_dp_get_m_n(crtc, pipe_config);
1571
18442d08 1572 if (port == PORT_A) {
f1f644dc
JB		 1573 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1574 pipe_config->port_clock = 162000;
1575 else
1576 pipe_config->port_clock = 270000;
1577 }
18442d08
VS		 1578
1579 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1580 &pipe_config->dp_m_n);
1581
1582 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1583 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1584
241bfc38 1585 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1586
c6cd2ee2
JN		 1587 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1588 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1589 /*
1590 * This is a big fat ugly hack.
1591 *
1592 * Some machines in UEFI boot mode provide us a VBT that has 18
1593 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1594 * unknown we fail to light up. Yet the same BIOS boots up with
1595 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1596 * max, not what it tells us to use.
1597 *
1598 * Note: This will still be broken if the eDP panel is not lit
1599 * up by the BIOS, and thus we can't get the mode at module
1600 * load.
1601 */
1602 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1603 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1604 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1605 }
045ac3b5
JB		 1606}
1607
a031d709 1608static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1609{
a031d709
RV		 1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611
1612 return dev_priv->psr.sink_support;
2293bb5c
SK		 1613}
1614
2b28bb1b
RV		 1615static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1616{
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618
18b5992c 1619 if (!HAS_PSR(dev))
2b28bb1b
RV		 1620 return false;
1621
18b5992c 1622 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1623}
1624
1625static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1626 struct edp_vsc_psr *vsc_psr)
1627{
1628 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1629 struct drm_device *dev = dig_port->base.base.dev;
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1632 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1633 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1634 uint32_t *data = (uint32_t *) vsc_psr;
1635 unsigned int i;
1636
1637 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1638 the video DIP being updated before program video DIP data buffer
1639 registers for DIP being updated. */
1640 I915_WRITE(ctl_reg, 0);
1641 POSTING_READ(ctl_reg);
1642
1643 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1644 if (i < sizeof(struct edp_vsc_psr))
1645 I915_WRITE(data_reg + i, *data++);
1646 else
1647 I915_WRITE(data_reg + i, 0);
1648 }
1649
1650 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1651 POSTING_READ(ctl_reg);
1652}
1653
1654static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1655{
1656 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 struct edp_vsc_psr psr_vsc;
1659
1660 if (intel_dp->psr_setup_done)
1661 return;
1662
1663 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1664 memset(&psr_vsc, 0, sizeof(psr_vsc));
1665 psr_vsc.sdp_header.HB0 = 0;
1666 psr_vsc.sdp_header.HB1 = 0x7;
1667 psr_vsc.sdp_header.HB2 = 0x2;
1668 psr_vsc.sdp_header.HB3 = 0x8;
1669 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1670
1671 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1672 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1673 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1674
1675 intel_dp->psr_setup_done = true;
1676}
1677
1678static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1679{
1680 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1681 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1682 uint32_t aux_clock_divider;
2b28bb1b
RV		 1683 int precharge = 0x3;
1684 int msg_size = 5; /* Header(4) + Message(1) */
1685
ec5b01dd
DL		 1686 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1687
2b28bb1b
RV		 1688 /* Enable PSR in sink */
1689 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1690 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1691 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1692 else
9d1a1031
JN		 1693 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1694 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1695
1696 /* Setup AUX registers */
18b5992c
BW		 1697 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1698 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1699 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1700 DP_AUX_CH_CTL_TIME_OUT_400us |
1701 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1702 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1703 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1704}
1705
1706static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1707{
1708 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710 uint32_t max_sleep_time = 0x1f;
1711 uint32_t idle_frames = 1;
1712 uint32_t val = 0x0;
ed8546ac 1713 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1714
1715 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1716 val |= EDP_PSR_LINK_STANDBY;
1717 val |= EDP_PSR_TP2_TP3_TIME_0us;
1718 val |= EDP_PSR_TP1_TIME_0us;
1719 val |= EDP_PSR_SKIP_AUX_EXIT;
1720 } else
1721 val |= EDP_PSR_LINK_DISABLE;
1722
18b5992c 1723 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1724 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1725 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1726 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1727 EDP_PSR_ENABLE);
1728}
1729
3f51e471
RV		 1730static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1731{
1732 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1733 struct drm_device *dev = dig_port->base.base.dev;
1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 struct drm_crtc *crtc = dig_port->base.base.crtc;
1736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1737 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1738 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1739
a031d709
RV		 1740 dev_priv->psr.source_ok = false;
1741
18b5992c 1742 if (!HAS_PSR(dev)) {
3f51e471 1743 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1744 return false;
1745 }
1746
1747 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1748 (dig_port->port != PORT_A)) {
1749 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1750 return false;
1751 }
1752
d330a953 1753 if (!i915.enable_psr) {
105b7c11 1754 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1755 return false;
1756 }
1757
cd234b0b
CW		 1758 crtc = dig_port->base.base.crtc;
1759 if (crtc == NULL) {
1760 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1761 return false;
1762 }
1763
1764 intel_crtc = to_intel_crtc(crtc);
20ddf665 1765 if (!intel_crtc_active(crtc)) {
3f51e471 1766 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1767 return false;
1768 }
1769
cd234b0b 1770 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1771 if (obj->tiling_mode != I915_TILING_X ||
1772 obj->fence_reg == I915_FENCE_REG_NONE) {
1773 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1774 return false;
1775 }
1776
1777 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1778 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1779 return false;
1780 }
1781
1782 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1783 S3D_ENABLE) {
1784 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1785 return false;
1786 }
1787
ca73b4f0 1788 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1789 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1790 return false;
1791 }
1792
a031d709 1793 dev_priv->psr.source_ok = true;
3f51e471
RV		 1794 return true;
1795}
1796
3d739d92 1797static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1798{
1799 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1800
3f51e471
RV		 1801 if (!intel_edp_psr_match_conditions(intel_dp) ||
1802 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1803 return;
1804
1805 /* Setup PSR once */
1806 intel_edp_psr_setup(intel_dp);
1807
1808 /* Enable PSR on the panel */
1809 intel_edp_psr_enable_sink(intel_dp);
1810
1811 /* Enable PSR on the host */
1812 intel_edp_psr_enable_source(intel_dp);
1813}
1814
3d739d92
RV		 1815void intel_edp_psr_enable(struct intel_dp *intel_dp)
1816{
1817 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1818
1819 if (intel_edp_psr_match_conditions(intel_dp) &&
1820 !intel_edp_is_psr_enabled(dev))
1821 intel_edp_psr_do_enable(intel_dp);
1822}
1823
2b28bb1b
RV		 1824void intel_edp_psr_disable(struct intel_dp *intel_dp)
1825{
1826 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1827 struct drm_i915_private *dev_priv = dev->dev_private;
1828
1829 if (!intel_edp_is_psr_enabled(dev))
1830 return;
1831
18b5992c
BW		 1832 I915_WRITE(EDP_PSR_CTL(dev),
1833 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1834
1835 /* Wait till PSR is idle */
18b5992c 1836 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1837 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1838 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1839}
1840
3d739d92
RV		 1841void intel_edp_psr_update(struct drm_device *dev)
1842{
1843 struct intel_encoder *encoder;
1844 struct intel_dp *intel_dp = NULL;
1845
1846 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1847 if (encoder->type == INTEL_OUTPUT_EDP) {
1848 intel_dp = enc_to_intel_dp(&encoder->base);
1849
a031d709 1850 if (!is_edp_psr(dev))
3d739d92
RV		 1851 return;
1852
1853 if (!intel_edp_psr_match_conditions(intel_dp))
1854 intel_edp_psr_disable(intel_dp);
1855 else
1856 if (!intel_edp_is_psr_enabled(dev))
1857 intel_edp_psr_do_enable(intel_dp);
1858 }
1859}
1860
e8cb4558 1861static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1862{
e8cb4558 1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1864 enum port port = dp_to_dig_port(intel_dp)->port;
1865 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1866
1867 /* Make sure the panel is off before trying to change the mode. But also
1868 * ensure that we have vdd while we switch off the panel. */
b3064154 1869 edp_panel_vdd_on(intel_dp);
4be73780 1870 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1871 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1872 intel_edp_panel_off(intel_dp);
b3064154 1873 edp_panel_vdd_off(intel_dp, true);
3739850b
DV		 1874
1875 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1876 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1877 intel_dp_link_down(intel_dp);
d240f20f
JB		 1878}
1879
2bd2ad64 1880static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1881{
2bd2ad64 1882 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1883 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1884 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1885
982a3866 1886 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1887 intel_dp_link_down(intel_dp);
b2634017
JB		 1888 if (!IS_VALLEYVIEW(dev))
1889 ironlake_edp_pll_off(intel_dp);
3739850b 1890 }
2bd2ad64
DV		 1891}
1892
e8cb4558 1893static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1894{
e8cb4558
DV		 1895 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1896 struct drm_device *dev = encoder->base.dev;
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1899
0c33d8d7
DV		 1900 if (WARN_ON(dp_reg & DP_PORT_EN))
1901 return;
5d613501 1902
4be73780 1903 edp_panel_vdd_on(intel_dp);
f01eca2e 1904 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1905 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1906 intel_edp_panel_on(intel_dp);
1907 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1908 intel_dp_complete_link_train(intel_dp);
3ab9c637 1909 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1910}
89b667f8 1911
ecff4f3b
JN		 1912static void g4x_enable_dp(struct intel_encoder *encoder)
1913{
828f5c6e
JN		 1914 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1915
ecff4f3b 1916 intel_enable_dp(encoder);
4be73780 1917 intel_edp_backlight_on(intel_dp);
ab1f90f9 1918}
89b667f8 1919
ab1f90f9
JN		 1920static void vlv_enable_dp(struct intel_encoder *encoder)
1921{
828f5c6e
JN		 1922 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1923
4be73780 1924 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1925}
1926
ecff4f3b 1927static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1928{
1929 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1930 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1931
1932 if (dport->port == PORT_A)
1933 ironlake_edp_pll_on(intel_dp);
1934}
1935
1936static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1937{
2bd2ad64 1938 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1939 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1940 struct drm_device *dev = encoder->base.dev;
89b667f8 1941 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1942 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1943 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1944 int pipe = intel_crtc->pipe;
bf13e81b 1945 struct edp_power_seq power_seq;
ab1f90f9 1946 u32 val;
a4fc5ed6 1947
ab1f90f9 1948 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1949
ab3c759a 1950 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1951 val = 0;
1952 if (pipe)
1953 val |= (1<<21);
1954 else
1955 val &= ~(1<<21);
1956 val |= 0x001000c4;
ab3c759a
CML		 1957 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1958 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1959 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1960
ab1f90f9
JN		 1961 mutex_unlock(&dev_priv->dpio_lock);
1962
2cac613b
ID		 1963 if (is_edp(intel_dp)) {
1964 /* init power sequencer on this pipe and port */
1965 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1966 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1967 &power_seq);
1968 }
bf13e81b 1969
ab1f90f9
JN		 1970 intel_enable_dp(encoder);
1971
e4607fcf 1972 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1973}
1974
ecff4f3b 1975static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1976{
1977 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1978 struct drm_device *dev = encoder->base.dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1980 struct intel_crtc *intel_crtc =
1981 to_intel_crtc(encoder->base.crtc);
e4607fcf 1982 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1983 int pipe = intel_crtc->pipe;
89b667f8 1984
89b667f8 1985 /* Program Tx lane resets to default */
0980a60f 1986 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1987 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1988 DPIO_PCS_TX_LANE2_RESET |
1989 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1990 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1991 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1992 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1993 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1994 DPIO_PCS_CLK_SOFT_RESET);
1995
1996 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1997 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1998 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1999 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2000 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2001}
2002
2003/*
df0c237d
JB		 2004 * Native read with retry for link status and receiver capability reads for
2005 * cases where the sink may still be asleep.
9d1a1031
JN		 2006 *
2007 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2008 * supposed to retry 3 times per the spec.
a4fc5ed6 2009 */
9d1a1031
JN		 2010static ssize_t
2011intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2012 void *buffer, size_t size)
a4fc5ed6 2013{
9d1a1031
JN		 2014 ssize_t ret;
2015 int i;
61da5fab 2016
61da5fab 2017 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2018 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2019 if (ret == size)
2020 return ret;
61da5fab
JB		 2021 msleep(1);
2022 }
a4fc5ed6 2023
9d1a1031 2024 return ret;
a4fc5ed6
KP		 2025}
2026
2027/*
2028 * Fetch AUX CH registers 0x202 - 0x207 which contain
2029 * link status information
2030 */
2031static bool
93f62dad 2032intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2033{
9d1a1031
JN		 2034 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2035 DP_LANE0_1_STATUS,
2036 link_status,
2037 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2038}
2039
a4fc5ed6
KP		 2040/*
2041 * These are source-specific values; current Intel hardware supports
2042 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2043 */
a4fc5ed6
KP		 2044
2045static uint8_t
1a2eb460 2046intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2047{
30add22d 2048 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2049 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2050
8f93f4f1 2051 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2052 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2053 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2054 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2055 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2056 return DP_TRAIN_VOLTAGE_SWING_1200;
2057 else
2058 return DP_TRAIN_VOLTAGE_SWING_800;
2059}
2060
2061static uint8_t
2062intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2063{
30add22d 2064 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2065 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2066
8f93f4f1
PZ		 2067 if (IS_BROADWELL(dev)) {
2068 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2069 case DP_TRAIN_VOLTAGE_SWING_400:
2070 case DP_TRAIN_VOLTAGE_SWING_600:
2071 return DP_TRAIN_PRE_EMPHASIS_6;
2072 case DP_TRAIN_VOLTAGE_SWING_800:
2073 return DP_TRAIN_PRE_EMPHASIS_3_5;
2074 case DP_TRAIN_VOLTAGE_SWING_1200:
2075 default:
2076 return DP_TRAIN_PRE_EMPHASIS_0;
2077 }
2078 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2079 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2080 case DP_TRAIN_VOLTAGE_SWING_400:
2081 return DP_TRAIN_PRE_EMPHASIS_9_5;
2082 case DP_TRAIN_VOLTAGE_SWING_600:
2083 return DP_TRAIN_PRE_EMPHASIS_6;
2084 case DP_TRAIN_VOLTAGE_SWING_800:
2085 return DP_TRAIN_PRE_EMPHASIS_3_5;
2086 case DP_TRAIN_VOLTAGE_SWING_1200:
2087 default:
2088 return DP_TRAIN_PRE_EMPHASIS_0;
2089 }
e2fa6fba
P		 2090 } else if (IS_VALLEYVIEW(dev)) {
2091 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2092 case DP_TRAIN_VOLTAGE_SWING_400:
2093 return DP_TRAIN_PRE_EMPHASIS_9_5;
2094 case DP_TRAIN_VOLTAGE_SWING_600:
2095 return DP_TRAIN_PRE_EMPHASIS_6;
2096 case DP_TRAIN_VOLTAGE_SWING_800:
2097 return DP_TRAIN_PRE_EMPHASIS_3_5;
2098 case DP_TRAIN_VOLTAGE_SWING_1200:
2099 default:
2100 return DP_TRAIN_PRE_EMPHASIS_0;
2101 }
bc7d38a4 2102 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2103 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2104 case DP_TRAIN_VOLTAGE_SWING_400:
2105 return DP_TRAIN_PRE_EMPHASIS_6;
2106 case DP_TRAIN_VOLTAGE_SWING_600:
2107 case DP_TRAIN_VOLTAGE_SWING_800:
2108 return DP_TRAIN_PRE_EMPHASIS_3_5;
2109 default:
2110 return DP_TRAIN_PRE_EMPHASIS_0;
2111 }
2112 } else {
2113 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2114 case DP_TRAIN_VOLTAGE_SWING_400:
2115 return DP_TRAIN_PRE_EMPHASIS_6;
2116 case DP_TRAIN_VOLTAGE_SWING_600:
2117 return DP_TRAIN_PRE_EMPHASIS_6;
2118 case DP_TRAIN_VOLTAGE_SWING_800:
2119 return DP_TRAIN_PRE_EMPHASIS_3_5;
2120 case DP_TRAIN_VOLTAGE_SWING_1200:
2121 default:
2122 return DP_TRAIN_PRE_EMPHASIS_0;
2123 }
a4fc5ed6
KP		 2124 }
2125}
2126
e2fa6fba
P		 2127static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2128{
2129 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2130 struct drm_i915_private *dev_priv = dev->dev_private;
2131 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2132 struct intel_crtc *intel_crtc =
2133 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2134 unsigned long demph_reg_value, preemph_reg_value,
2135 uniqtranscale_reg_value;
2136 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2137 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2138 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2139
2140 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2141 case DP_TRAIN_PRE_EMPHASIS_0:
2142 preemph_reg_value = 0x0004000;
2143 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2144 case DP_TRAIN_VOLTAGE_SWING_400:
2145 demph_reg_value = 0x2B405555;
2146 uniqtranscale_reg_value = 0x552AB83A;
2147 break;
2148 case DP_TRAIN_VOLTAGE_SWING_600:
2149 demph_reg_value = 0x2B404040;
2150 uniqtranscale_reg_value = 0x5548B83A;
2151 break;
2152 case DP_TRAIN_VOLTAGE_SWING_800:
2153 demph_reg_value = 0x2B245555;
2154 uniqtranscale_reg_value = 0x5560B83A;
2155 break;
2156 case DP_TRAIN_VOLTAGE_SWING_1200:
2157 demph_reg_value = 0x2B405555;
2158 uniqtranscale_reg_value = 0x5598DA3A;
2159 break;
2160 default:
2161 return 0;
2162 }
2163 break;
2164 case DP_TRAIN_PRE_EMPHASIS_3_5:
2165 preemph_reg_value = 0x0002000;
2166 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2167 case DP_TRAIN_VOLTAGE_SWING_400:
2168 demph_reg_value = 0x2B404040;
2169 uniqtranscale_reg_value = 0x5552B83A;
2170 break;
2171 case DP_TRAIN_VOLTAGE_SWING_600:
2172 demph_reg_value = 0x2B404848;
2173 uniqtranscale_reg_value = 0x5580B83A;
2174 break;
2175 case DP_TRAIN_VOLTAGE_SWING_800:
2176 demph_reg_value = 0x2B404040;
2177 uniqtranscale_reg_value = 0x55ADDA3A;
2178 break;
2179 default:
2180 return 0;
2181 }
2182 break;
2183 case DP_TRAIN_PRE_EMPHASIS_6:
2184 preemph_reg_value = 0x0000000;
2185 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2186 case DP_TRAIN_VOLTAGE_SWING_400:
2187 demph_reg_value = 0x2B305555;
2188 uniqtranscale_reg_value = 0x5570B83A;
2189 break;
2190 case DP_TRAIN_VOLTAGE_SWING_600:
2191 demph_reg_value = 0x2B2B4040;
2192 uniqtranscale_reg_value = 0x55ADDA3A;
2193 break;
2194 default:
2195 return 0;
2196 }
2197 break;
2198 case DP_TRAIN_PRE_EMPHASIS_9_5:
2199 preemph_reg_value = 0x0006000;
2200 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2201 case DP_TRAIN_VOLTAGE_SWING_400:
2202 demph_reg_value = 0x1B405555;
2203 uniqtranscale_reg_value = 0x55ADDA3A;
2204 break;
2205 default:
2206 return 0;
2207 }
2208 break;
2209 default:
2210 return 0;
2211 }
2212
0980a60f 2213 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2214 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2215 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2216 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2217 uniqtranscale_reg_value);
ab3c759a
CML		 2218 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2219 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2220 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2221 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2222 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2223
2224 return 0;
2225}
2226
a4fc5ed6 2227static void
0301b3ac
JN		 2228intel_get_adjust_train(struct intel_dp *intel_dp,
2229 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2230{
2231 uint8_t v = 0;
2232 uint8_t p = 0;
2233 int lane;
1a2eb460
KP		 2234 uint8_t voltage_max;
2235 uint8_t preemph_max;
a4fc5ed6 2236
33a34e4e 2237 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2238 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2239 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2240
2241 if (this_v > v)
2242 v = this_v;
2243 if (this_p > p)
2244 p = this_p;
2245 }
2246
1a2eb460 2247 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2248 if (v >= voltage_max)
2249 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2250
1a2eb460
KP		 2251 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2252 if (p >= preemph_max)
2253 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2254
2255 for (lane = 0; lane < 4; lane++)
33a34e4e 2256 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2257}
2258
2259static uint32_t
f0a3424e 2260intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2261{
3cf2efb1 2262 uint32_t signal_levels = 0;
a4fc5ed6 2263
3cf2efb1 2264 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2265 case DP_TRAIN_VOLTAGE_SWING_400:
2266 default:
2267 signal_levels |= DP_VOLTAGE_0_4;
2268 break;
2269 case DP_TRAIN_VOLTAGE_SWING_600:
2270 signal_levels |= DP_VOLTAGE_0_6;
2271 break;
2272 case DP_TRAIN_VOLTAGE_SWING_800:
2273 signal_levels |= DP_VOLTAGE_0_8;
2274 break;
2275 case DP_TRAIN_VOLTAGE_SWING_1200:
2276 signal_levels |= DP_VOLTAGE_1_2;
2277 break;
2278 }
3cf2efb1 2279 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2280 case DP_TRAIN_PRE_EMPHASIS_0:
2281 default:
2282 signal_levels |= DP_PRE_EMPHASIS_0;
2283 break;
2284 case DP_TRAIN_PRE_EMPHASIS_3_5:
2285 signal_levels |= DP_PRE_EMPHASIS_3_5;
2286 break;
2287 case DP_TRAIN_PRE_EMPHASIS_6:
2288 signal_levels |= DP_PRE_EMPHASIS_6;
2289 break;
2290 case DP_TRAIN_PRE_EMPHASIS_9_5:
2291 signal_levels |= DP_PRE_EMPHASIS_9_5;
2292 break;
2293 }
2294 return signal_levels;
2295}
2296
e3421a18
ZW		 2297/* Gen6's DP voltage swing and pre-emphasis control */
2298static uint32_t
2299intel_gen6_edp_signal_levels(uint8_t train_set)
2300{
3c5a62b5
YL		 2301 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2302 DP_TRAIN_PRE_EMPHASIS_MASK);
2303 switch (signal_levels) {
e3421a18 2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2305 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2306 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2307 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2308 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2309 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2310 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2311 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2312 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2313 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2315 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2316 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2317 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2318 default:
3c5a62b5
YL		 2319 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2320 "0x%x\n", signal_levels);
2321 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2322 }
2323}
2324
1a2eb460
KP		 2325/* Gen7's DP voltage swing and pre-emphasis control */
2326static uint32_t
2327intel_gen7_edp_signal_levels(uint8_t train_set)
2328{
2329 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2330 DP_TRAIN_PRE_EMPHASIS_MASK);
2331 switch (signal_levels) {
2332 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2333 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2334 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2335 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2336 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2337 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2338
2339 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2340 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2341 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2342 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2343
2344 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2345 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2346 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2347 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2348
2349 default:
2350 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2351 "0x%x\n", signal_levels);
2352 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2353 }
2354}
2355
d6c0d722
PZ		 2356/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2357static uint32_t
f0a3424e 2358intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2359{
d6c0d722
PZ		 2360 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2361 DP_TRAIN_PRE_EMPHASIS_MASK);
2362 switch (signal_levels) {
2363 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2364 return DDI_BUF_EMP_400MV_0DB_HSW;
2365 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2366 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2367 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2368 return DDI_BUF_EMP_400MV_6DB_HSW;
2369 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2370 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2371
d6c0d722
PZ		 2372 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2373 return DDI_BUF_EMP_600MV_0DB_HSW;
2374 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2375 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2376 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2377 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2378
d6c0d722
PZ		 2379 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2380 return DDI_BUF_EMP_800MV_0DB_HSW;
2381 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2382 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2383 default:
2384 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2385 "0x%x\n", signal_levels);
2386 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2387 }
a4fc5ed6
KP		 2388}
2389
8f93f4f1
PZ		 2390static uint32_t
2391intel_bdw_signal_levels(uint8_t train_set)
2392{
2393 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2394 DP_TRAIN_PRE_EMPHASIS_MASK);
2395 switch (signal_levels) {
2396 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2397 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2398 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2399 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2400 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2401 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2402
2403 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2404 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2405 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2406 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2407 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2408 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2409
2410 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2411 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2412 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2413 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2414
2415 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2416 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2417
2418 default:
2419 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2420 "0x%x\n", signal_levels);
2421 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2422 }
2423}
2424
f0a3424e
PZ		 2425/* Properly updates "DP" with the correct signal levels. */
2426static void
2427intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2428{
2429 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2430 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2431 struct drm_device *dev = intel_dig_port->base.base.dev;
2432 uint32_t signal_levels, mask;
2433 uint8_t train_set = intel_dp->train_set[0];
2434
8f93f4f1
PZ		 2435 if (IS_BROADWELL(dev)) {
2436 signal_levels = intel_bdw_signal_levels(train_set);
2437 mask = DDI_BUF_EMP_MASK;
2438 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2439 signal_levels = intel_hsw_signal_levels(train_set);
2440 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2441 } else if (IS_VALLEYVIEW(dev)) {
2442 signal_levels = intel_vlv_signal_levels(intel_dp);
2443 mask = 0;
bc7d38a4 2444 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2445 signal_levels = intel_gen7_edp_signal_levels(train_set);
2446 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2447 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2448 signal_levels = intel_gen6_edp_signal_levels(train_set);
2449 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2450 } else {
2451 signal_levels = intel_gen4_signal_levels(train_set);
2452 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2453 }
2454
2455 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2456
2457 *DP = (*DP & ~mask) | signal_levels;
2458}
2459
a4fc5ed6 2460static bool
ea5b213a 2461intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2462 uint32_t *DP,
58e10eb9 2463 uint8_t dp_train_pat)
a4fc5ed6 2464{
174edf1f
PZ		 2465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2466 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2467 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2468 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2469 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2470 int ret, len;
a4fc5ed6 2471
22b8bf17 2472 if (HAS_DDI(dev)) {
3ab9c637 2473 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2474
2475 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2476 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2477 else
2478 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2479
2480 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2481 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2482 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2483 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2484
2485 break;
2486 case DP_TRAINING_PATTERN_1:
2487 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2488 break;
2489 case DP_TRAINING_PATTERN_2:
2490 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2491 break;
2492 case DP_TRAINING_PATTERN_3:
2493 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2494 break;
2495 }
174edf1f 2496 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2497
bc7d38a4 2498 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2499 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2500
2501 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2502 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2503 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2504 break;
2505 case DP_TRAINING_PATTERN_1:
70aff66c 2506 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2507 break;
2508 case DP_TRAINING_PATTERN_2:
70aff66c 2509 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2510 break;
2511 case DP_TRAINING_PATTERN_3:
2512 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2513 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2514 break;
2515 }
2516
2517 } else {
70aff66c 2518 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2519
2520 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2521 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2522 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2523 break;
2524 case DP_TRAINING_PATTERN_1:
70aff66c 2525 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2526 break;
2527 case DP_TRAINING_PATTERN_2:
70aff66c 2528 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2529 break;
2530 case DP_TRAINING_PATTERN_3:
2531 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2532 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2533 break;
2534 }
2535 }
2536
70aff66c 2537 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2538 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2539
2cdfe6c8
JN		 2540 buf[0] = dp_train_pat;
2541 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2542 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2543 /* don't write DP_TRAINING_LANEx_SET on disable */
2544 len = 1;
2545 } else {
2546 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2547 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2548 len = intel_dp->lane_count + 1;
47ea7542 2549 }
a4fc5ed6 2550
9d1a1031
JN		 2551 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2552 buf, len);
2cdfe6c8
JN		 2553
2554 return ret == len;
a4fc5ed6
KP		 2555}
2556
70aff66c
JN		 2557static bool
2558intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2559 uint8_t dp_train_pat)
2560{
953d22e8 2561 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2562 intel_dp_set_signal_levels(intel_dp, DP);
2563 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2564}
2565
2566static bool
2567intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2568 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2569{
2570 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2571 struct drm_device *dev = intel_dig_port->base.base.dev;
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2573 int ret;
2574
2575 intel_get_adjust_train(intel_dp, link_status);
2576 intel_dp_set_signal_levels(intel_dp, DP);
2577
2578 I915_WRITE(intel_dp->output_reg, *DP);
2579 POSTING_READ(intel_dp->output_reg);
2580
9d1a1031
JN		 2581 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2582 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2583
2584 return ret == intel_dp->lane_count;
2585}
2586
3ab9c637
ID		 2587static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2588{
2589 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2590 struct drm_device *dev = intel_dig_port->base.base.dev;
2591 struct drm_i915_private *dev_priv = dev->dev_private;
2592 enum port port = intel_dig_port->port;
2593 uint32_t val;
2594
2595 if (!HAS_DDI(dev))
2596 return;
2597
2598 val = I915_READ(DP_TP_CTL(port));
2599 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2600 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2601 I915_WRITE(DP_TP_CTL(port), val);
2602
2603 /*
2604 * On PORT_A we can have only eDP in SST mode. There the only reason
2605 * we need to set idle transmission mode is to work around a HW issue
2606 * where we enable the pipe while not in idle link-training mode.
2607 * In this case there is requirement to wait for a minimum number of
2608 * idle patterns to be sent.
2609 */
2610 if (port == PORT_A)
2611 return;
2612
2613 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2614 1))
2615 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2616}
2617
33a34e4e 2618/* Enable corresponding port and start training pattern 1 */
c19b0669 2619void
33a34e4e 2620intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2621{
da63a9f2 2622 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2623 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2624 int i;
2625 uint8_t voltage;
cdb0e95b 2626 int voltage_tries, loop_tries;
ea5b213a 2627 uint32_t DP = intel_dp->DP;
6aba5b6c 2628 uint8_t link_config[2];
a4fc5ed6 2629
affa9354 2630 if (HAS_DDI(dev))
c19b0669
PZ		 2631 intel_ddi_prepare_link_retrain(encoder);
2632
3cf2efb1 2633 /* Write the link configuration data */
6aba5b6c
JN		 2634 link_config[0] = intel_dp->link_bw;
2635 link_config[1] = intel_dp->lane_count;
2636 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2637 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2638 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2639
2640 link_config[0] = 0;
2641 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2642 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2643
2644 DP |= DP_PORT_EN;
1a2eb460 2645
70aff66c
JN		 2646 /* clock recovery */
2647 if (!intel_dp_reset_link_train(intel_dp, &DP,
2648 DP_TRAINING_PATTERN_1 |
2649 DP_LINK_SCRAMBLING_DISABLE)) {
2650 DRM_ERROR("failed to enable link training\n");
2651 return;
2652 }
2653
a4fc5ed6 2654 voltage = 0xff;
cdb0e95b
KP		 2655 voltage_tries = 0;
2656 loop_tries = 0;
a4fc5ed6 2657 for (;;) {
70aff66c 2658 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2659
a7c9655f 2660 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2661 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2662 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2663 break;
93f62dad 2664 }
a4fc5ed6 2665
01916270 2666 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2667 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2668 break;
2669 }
2670
2671 /* Check to see if we've tried the max voltage */
2672 for (i = 0; i < intel_dp->lane_count; i++)
2673 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2674 break;
3b4f819d 2675 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2676 ++loop_tries;
2677 if (loop_tries == 5) {
3def84b3 2678 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2679 break;
2680 }
70aff66c
JN		 2681 intel_dp_reset_link_train(intel_dp, &DP,
2682 DP_TRAINING_PATTERN_1 |
2683 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2684 voltage_tries = 0;
2685 continue;
2686 }
a4fc5ed6 2687
3cf2efb1 2688 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2689 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2690 ++voltage_tries;
b06fbda3 2691 if (voltage_tries == 5) {
3def84b3 2692 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2693 break;
2694 }
2695 } else
2696 voltage_tries = 0;
2697 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2698
70aff66c
JN		 2699 /* Update training set as requested by target */
2700 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2701 DRM_ERROR("failed to update link training\n");
2702 break;
2703 }
a4fc5ed6
KP		 2704 }
2705
33a34e4e
JB		 2706 intel_dp->DP = DP;
2707}
2708
c19b0669 2709void
33a34e4e
JB		 2710intel_dp_complete_link_train(struct intel_dp *intel_dp)
2711{
33a34e4e 2712 bool channel_eq = false;
37f80975 2713 int tries, cr_tries;
33a34e4e 2714 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2715 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2716
2717 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2718 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2719 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2720
a4fc5ed6 2721 /* channel equalization */
70aff66c 2722 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2723 training_pattern |
70aff66c
JN		 2724 DP_LINK_SCRAMBLING_DISABLE)) {
2725 DRM_ERROR("failed to start channel equalization\n");
2726 return;
2727 }
2728
a4fc5ed6 2729 tries = 0;
37f80975 2730 cr_tries = 0;
a4fc5ed6
KP		 2731 channel_eq = false;
2732 for (;;) {
70aff66c 2733 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2734
37f80975
JB		 2735 if (cr_tries > 5) {
2736 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2737 break;
2738 }
2739
a7c9655f 2740 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2741 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2742 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2743 break;
70aff66c 2744 }
a4fc5ed6 2745
37f80975 2746 /* Make sure clock is still ok */
01916270 2747 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2748 intel_dp_start_link_train(intel_dp);
70aff66c 2749 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2750 training_pattern |
70aff66c 2751 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2752 cr_tries++;
2753 continue;
2754 }
2755
1ffdff13 2756 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2757 channel_eq = true;
2758 break;
2759 }
a4fc5ed6 2760
37f80975
JB		 2761 /* Try 5 times, then try clock recovery if that fails */
2762 if (tries > 5) {
2763 intel_dp_link_down(intel_dp);
2764 intel_dp_start_link_train(intel_dp);
70aff66c 2765 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2766 training_pattern |
70aff66c 2767 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2768 tries = 0;
2769 cr_tries++;
2770 continue;
2771 }
a4fc5ed6 2772
70aff66c
JN		 2773 /* Update training set as requested by target */
2774 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2775 DRM_ERROR("failed to update link training\n");
2776 break;
2777 }
3cf2efb1 2778 ++tries;
869184a6 2779 }
3cf2efb1 2780
3ab9c637
ID		 2781 intel_dp_set_idle_link_train(intel_dp);
2782
2783 intel_dp->DP = DP;
2784
d6c0d722 2785 if (channel_eq)
07f42258 2786 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2787
3ab9c637
ID		 2788}
2789
2790void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2791{
70aff66c 2792 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2793 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2794}
2795
2796static void
ea5b213a 2797intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2798{
da63a9f2 2799 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2800 enum port port = intel_dig_port->port;
da63a9f2 2801 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2802 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2803 struct intel_crtc *intel_crtc =
2804 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2805 uint32_t DP = intel_dp->DP;
a4fc5ed6 2806
c19b0669
PZ		 2807 /*
2808 * DDI code has a strict mode set sequence and we should try to respect
2809 * it, otherwise we might hang the machine in many different ways. So we
2810 * really should be disabling the port only on a complete crtc_disable
2811 * sequence. This function is just called under two conditions on DDI
2812 * code:
2813 * - Link train failed while doing crtc_enable, and on this case we
2814 * really should respect the mode set sequence and wait for a
2815 * crtc_disable.
2816 * - Someone turned the monitor off and intel_dp_check_link_status
2817 * called us. We don't need to disable the whole port on this case, so
2818 * when someone turns the monitor on again,
2819 * intel_ddi_prepare_link_retrain will take care of redoing the link
2820 * train.
2821 */
affa9354 2822 if (HAS_DDI(dev))
c19b0669
PZ		 2823 return;
2824
0c33d8d7 2825 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2826 return;
2827
28c97730 2828 DRM_DEBUG_KMS("\n");
32f9d658 2829
bc7d38a4 2830 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2831 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2832 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2833 } else {
2834 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2835 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2836 }
fe255d00 2837 POSTING_READ(intel_dp->output_reg);
5eb08b69 2838
ab527efc
DV		 2839 /* We don't really know why we're doing this */
2840 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2841
493a7081 2842 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2843 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2844 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2845
5bddd17f
EA		 2846 /* Hardware workaround: leaving our transcoder select
2847 * set to transcoder B while it's off will prevent the
2848 * corresponding HDMI output on transcoder A.
2849 *
2850 * Combine this with another hardware workaround:
2851 * transcoder select bit can only be cleared while the
2852 * port is enabled.
2853 */
2854 DP &= ~DP_PIPEB_SELECT;
2855 I915_WRITE(intel_dp->output_reg, DP);
2856
2857 /* Changes to enable or select take place the vblank
2858 * after being written.
2859 */
ff50afe9
DV		 2860 if (WARN_ON(crtc == NULL)) {
2861 /* We should never try to disable a port without a crtc
2862 * attached. For paranoia keep the code around for a
2863 * bit. */
31acbcc4
CW		 2864 POSTING_READ(intel_dp->output_reg);
2865 msleep(50);
2866 } else
ab527efc 2867 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2868 }
2869
832afda6 2870 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2871 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2872 POSTING_READ(intel_dp->output_reg);
f01eca2e 2873 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2874}
2875
26d61aad
KP		 2876static bool
2877intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2878{
a031d709
RV		 2879 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2880 struct drm_device *dev = dig_port->base.base.dev;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882
577c7a50
DL		 2883 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2884
9d1a1031
JN		 2885 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2886 sizeof(intel_dp->dpcd)) < 0)
edb39244 2887 return false; /* aux transfer failed */
92fd8fd1 2888
577c7a50
DL		 2889 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2890 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2891 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2892
edb39244
AJ		 2893 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2894 return false; /* DPCD not present */
2895
2293bb5c
SK		 2896 /* Check if the panel supports PSR */
2897 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2898 if (is_edp(intel_dp)) {
9d1a1031
JN		 2899 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2900 intel_dp->psr_dpcd,
2901 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2902 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2903 dev_priv->psr.sink_support = true;
50003939 2904 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2905 }
50003939
JN		 2906 }
2907
06ea66b6
TP		 2908 /* Training Pattern 3 support */
2909 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2910 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2911 intel_dp->use_tps3 = true;
2912 DRM_DEBUG_KMS("Displayport TPS3 supported");
2913 } else
2914 intel_dp->use_tps3 = false;
2915
edb39244
AJ		 2916 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2917 DP_DWN_STRM_PORT_PRESENT))
2918 return true; /* native DP sink */
2919
2920 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2921 return true; /* no per-port downstream info */
2922
9d1a1031
JN		 2923 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2924 intel_dp->downstream_ports,
2925 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2926 return false; /* downstream port status fetch failed */
2927
2928 return true;
92fd8fd1
KP		 2929}
2930
0d198328
AJ		 2931static void
2932intel_dp_probe_oui(struct intel_dp *intel_dp)
2933{
2934 u8 buf[3];
2935
2936 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2937 return;
2938
4be73780 2939 edp_panel_vdd_on(intel_dp);
351cfc34 2940
9d1a1031 2941 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2942 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2943 buf[0], buf[1], buf[2]);
2944
9d1a1031 2945 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2946 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2947 buf[0], buf[1], buf[2]);
351cfc34 2948
4be73780 2949 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2950}
2951
d2e216d0
RV		 2952int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2953{
2954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2955 struct drm_device *dev = intel_dig_port->base.base.dev;
2956 struct intel_crtc *intel_crtc =
2957 to_intel_crtc(intel_dig_port->base.base.crtc);
2958 u8 buf[1];
2959
9d1a1031 2960 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2961 return -EAGAIN;
2962
2963 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2964 return -ENOTTY;
2965
9d1a1031
JN		 2966 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2967 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2968 return -EAGAIN;
2969
2970 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2971 intel_wait_for_vblank(dev, intel_crtc->pipe);
2972 intel_wait_for_vblank(dev, intel_crtc->pipe);
2973
9d1a1031 2974 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2975 return -EAGAIN;
2976
9d1a1031 2977 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2978 return 0;
2979}
2980
a60f0e38
JB		 2981static bool
2982intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2983{
9d1a1031
JN		 2984 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2985 DP_DEVICE_SERVICE_IRQ_VECTOR,
2986 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2987}
2988
2989static void
2990intel_dp_handle_test_request(struct intel_dp *intel_dp)
2991{
2992 /* NAK by default */
9d1a1031 2993 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2994}
2995
a4fc5ed6
KP		 2996/*
2997 * According to DP spec
2998 * 5.1.2:
2999 * 1. Read DPCD
3000 * 2. Configure link according to Receiver Capabilities
3001 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3002 * 4. Check link status on receipt of hot-plug interrupt
3003 */
3004
00c09d70 3005void
ea5b213a 3006intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3007{
da63a9f2 3008 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3009 u8 sink_irq_vector;
93f62dad 3010 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3011
da63a9f2 3012 if (!intel_encoder->connectors_active)
d2b996ac 3013 return;
59cd09e1 3014
da63a9f2 3015 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3016 return;
3017
92fd8fd1 3018 /* Try to read receiver status if the link appears to be up */
93f62dad 3019 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3020 return;
3021 }
3022
92fd8fd1 3023 /* Now read the DPCD to see if it's actually running */
26d61aad 3024 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3025 return;
3026 }
3027
a60f0e38
JB		 3028 /* Try to read the source of the interrupt */
3029 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3030 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3031 /* Clear interrupt source */
9d1a1031
JN		 3032 drm_dp_dpcd_writeb(&intel_dp->aux,
3033 DP_DEVICE_SERVICE_IRQ_VECTOR,
3034 sink_irq_vector);
a60f0e38
JB		 3035
3036 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3037 intel_dp_handle_test_request(intel_dp);
3038 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3039 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3040 }
3041
1ffdff13 3042 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3043 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3044 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3045 intel_dp_start_link_train(intel_dp);
3046 intel_dp_complete_link_train(intel_dp);
3ab9c637 3047 intel_dp_stop_link_train(intel_dp);
33a34e4e 3048 }
a4fc5ed6 3049}
a4fc5ed6 3050
caf9ab24 3051/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3052static enum drm_connector_status
26d61aad 3053intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3054{
caf9ab24 3055 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3056 uint8_t type;
3057
3058 if (!intel_dp_get_dpcd(intel_dp))
3059 return connector_status_disconnected;
3060
3061 /* if there's no downstream port, we're done */
3062 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3063 return connector_status_connected;
caf9ab24
AJ		 3064
3065 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3066 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3067 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3068 uint8_t reg;
9d1a1031
JN		 3069
3070 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3071 &reg, 1) < 0)
caf9ab24 3072 return connector_status_unknown;
9d1a1031 3073
23235177
AJ		 3074 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3075 : connector_status_disconnected;
caf9ab24
AJ		 3076 }
3077
3078 /* If no HPD, poke DDC gently */
3079 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 3080 return connector_status_connected;
caf9ab24
AJ		 3081
3082 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3083 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3084 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3085 if (type == DP_DS_PORT_TYPE_VGA ||
3086 type == DP_DS_PORT_TYPE_NON_EDID)
3087 return connector_status_unknown;
3088 } else {
3089 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3090 DP_DWN_STRM_PORT_TYPE_MASK;
3091 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3092 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3093 return connector_status_unknown;
3094 }
caf9ab24
AJ		 3095
3096 /* Anything else is out of spec, warn and ignore */
3097 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3098 return connector_status_disconnected;
71ba9000
AJ		 3099}
3100
5eb08b69 3101static enum drm_connector_status
a9756bb5 3102ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3103{
30add22d 3104 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3107 enum drm_connector_status status;
3108
fe16d949
CW		 3109 /* Can't disconnect eDP, but you can close the lid... */
3110 if (is_edp(intel_dp)) {
30add22d 3111 status = intel_panel_detect(dev);
fe16d949
CW		 3112 if (status == connector_status_unknown)
3113 status = connector_status_connected;
3114 return status;
3115 }
01cb9ea6 3116
1b469639
DL		 3117 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3118 return connector_status_disconnected;
3119
26d61aad 3120 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3121}
3122
a4fc5ed6 3123static enum drm_connector_status
a9756bb5 3124g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3125{
30add22d 3126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3127 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3128 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3129 uint32_t bit;
5eb08b69 3130
35aad75f
JB		 3131 /* Can't disconnect eDP, but you can close the lid... */
3132 if (is_edp(intel_dp)) {
3133 enum drm_connector_status status;
3134
3135 status = intel_panel_detect(dev);
3136 if (status == connector_status_unknown)
3137 status = connector_status_connected;
3138 return status;
3139 }
3140
232a6ee9
TP		 3141 if (IS_VALLEYVIEW(dev)) {
3142 switch (intel_dig_port->port) {
3143 case PORT_B:
3144 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3145 break;
3146 case PORT_C:
3147 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3148 break;
3149 case PORT_D:
3150 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3151 break;
3152 default:
3153 return connector_status_unknown;
3154 }
3155 } else {
3156 switch (intel_dig_port->port) {
3157 case PORT_B:
3158 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3159 break;
3160 case PORT_C:
3161 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3162 break;
3163 case PORT_D:
3164 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3165 break;
3166 default:
3167 return connector_status_unknown;
3168 }
a4fc5ed6
KP		 3169 }
3170
10f76a38 3171 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3172 return connector_status_disconnected;
3173
26d61aad 3174 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3175}
3176
8c241fef
KP		 3177static struct edid *
3178intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3179{
9cd300e0 3180 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3181
9cd300e0
JN		 3182 /* use cached edid if we have one */
3183 if (intel_connector->edid) {
9cd300e0
JN		 3184 /* invalid edid */
3185 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3186 return NULL;
3187
55e9edeb 3188 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3189 }
8c241fef 3190
9cd300e0 3191 return drm_get_edid(connector, adapter);
8c241fef
KP		 3192}
3193
3194static int
3195intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3196{
9cd300e0 3197 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3198
9cd300e0
JN		 3199 /* use cached edid if we have one */
3200 if (intel_connector->edid) {
3201 /* invalid edid */
3202 if (IS_ERR(intel_connector->edid))
3203 return 0;
3204
3205 return intel_connector_update_modes(connector,
3206 intel_connector->edid);
d6f24d0f
JB		 3207 }
3208
9cd300e0 3209 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3210}
3211
a9756bb5
ZW		 3212static enum drm_connector_status
3213intel_dp_detect(struct drm_connector *connector, bool force)
3214{
3215 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3217 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3218 struct drm_device *dev = connector->dev;
c8c8fb33 3219 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3220 enum drm_connector_status status;
671dedd2 3221 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3222 struct edid *edid = NULL;
3223
c8c8fb33
PZ		 3224 intel_runtime_pm_get(dev_priv);
3225
671dedd2
ID		 3226 power_domain = intel_display_port_power_domain(intel_encoder);
3227 intel_display_power_get(dev_priv, power_domain);
3228
164c8598
CW		 3229 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3230 connector->base.id, drm_get_connector_name(connector));
3231
a9756bb5
ZW		 3232 intel_dp->has_audio = false;
3233
3234 if (HAS_PCH_SPLIT(dev))
3235 status = ironlake_dp_detect(intel_dp);
3236 else
3237 status = g4x_dp_detect(intel_dp);
1b9be9d0 3238
a9756bb5 3239 if (status != connector_status_connected)
c8c8fb33 3240 goto out;
a9756bb5 3241
0d198328
AJ		 3242 intel_dp_probe_oui(intel_dp);
3243
c3e5f67b
DV		 3244 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3245 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3246 } else {
8c241fef 3247 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3248 if (edid) {
3249 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3250 kfree(edid);
3251 }
a9756bb5
ZW		 3252 }
3253
d63885da
PZ		 3254 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3255 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3256 status = connector_status_connected;
3257
3258out:
671dedd2
ID		 3259 intel_display_power_put(dev_priv, power_domain);
3260
c8c8fb33 3261 intel_runtime_pm_put(dev_priv);
671dedd2 3262
c8c8fb33 3263 return status;
a4fc5ed6
KP		 3264}
3265
3266static int intel_dp_get_modes(struct drm_connector *connector)
3267{
df0e9248 3268 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3270 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3271 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3272 struct drm_device *dev = connector->dev;
671dedd2
ID		 3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 enum intel_display_power_domain power_domain;
32f9d658 3275 int ret;
a4fc5ed6
KP		 3276
3277 /* We should parse the EDID data and find out if it has an audio sink
3278 */
3279
671dedd2
ID		 3280 power_domain = intel_display_port_power_domain(intel_encoder);
3281 intel_display_power_get(dev_priv, power_domain);
3282
8c241fef 3283 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
671dedd2 3284 intel_display_power_put(dev_priv, power_domain);
f8779fda 3285 if (ret)
32f9d658
ZW		 3286 return ret;
3287
f8779fda 3288 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3289 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3290 struct drm_display_mode *mode;
dd06f90e
JN		 3291 mode = drm_mode_duplicate(dev,
3292 intel_connector->panel.fixed_mode);
f8779fda 3293 if (mode) {
32f9d658
ZW		 3294 drm_mode_probed_add(connector, mode);
3295 return 1;
3296 }
3297 }
3298 return 0;
a4fc5ed6
KP		 3299}
3300
1aad7ac0
CW		 3301static bool
3302intel_dp_detect_audio(struct drm_connector *connector)
3303{
3304 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3305 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3306 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3307 struct drm_device *dev = connector->dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3310 struct edid *edid;
3311 bool has_audio = false;
3312
671dedd2
ID		 3313 power_domain = intel_display_port_power_domain(intel_encoder);
3314 intel_display_power_get(dev_priv, power_domain);
3315
8c241fef 3316 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3317 if (edid) {
3318 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3319 kfree(edid);
3320 }
3321
671dedd2
ID		 3322 intel_display_power_put(dev_priv, power_domain);
3323
1aad7ac0
CW		 3324 return has_audio;
3325}
3326
f684960e
CW		 3327static int
3328intel_dp_set_property(struct drm_connector *connector,
3329 struct drm_property *property,
3330 uint64_t val)
3331{
e953fd7b 3332 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3333 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3334 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3335 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3336 int ret;
3337
662595df 3338 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3339 if (ret)
3340 return ret;
3341
3f43c48d 3342 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3343 int i = val;
3344 bool has_audio;
3345
3346 if (i == intel_dp->force_audio)
f684960e
CW		 3347 return 0;
3348
1aad7ac0 3349 intel_dp->force_audio = i;
f684960e 3350
c3e5f67b 3351 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3352 has_audio = intel_dp_detect_audio(connector);
3353 else
c3e5f67b 3354 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3355
3356 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3357 return 0;
3358
1aad7ac0 3359 intel_dp->has_audio = has_audio;
f684960e
CW		 3360 goto done;
3361 }
3362
e953fd7b 3363 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3364 bool old_auto = intel_dp->color_range_auto;
3365 uint32_t old_range = intel_dp->color_range;
3366
55bc60db
VS		 3367 switch (val) {
3368 case INTEL_BROADCAST_RGB_AUTO:
3369 intel_dp->color_range_auto = true;
3370 break;
3371 case INTEL_BROADCAST_RGB_FULL:
3372 intel_dp->color_range_auto = false;
3373 intel_dp->color_range = 0;
3374 break;
3375 case INTEL_BROADCAST_RGB_LIMITED:
3376 intel_dp->color_range_auto = false;
3377 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3378 break;
3379 default:
3380 return -EINVAL;
3381 }
ae4edb80
DV		 3382
3383 if (old_auto == intel_dp->color_range_auto &&
3384 old_range == intel_dp->color_range)
3385 return 0;
3386
e953fd7b
CW		 3387 goto done;
3388 }
3389
53b41837
YN		 3390 if (is_edp(intel_dp) &&
3391 property == connector->dev->mode_config.scaling_mode_property) {
3392 if (val == DRM_MODE_SCALE_NONE) {
3393 DRM_DEBUG_KMS("no scaling not supported\n");
3394 return -EINVAL;
3395 }
3396
3397 if (intel_connector->panel.fitting_mode == val) {
3398 /* the eDP scaling property is not changed */
3399 return 0;
3400 }
3401 intel_connector->panel.fitting_mode = val;
3402
3403 goto done;
3404 }
3405
f684960e
CW		 3406 return -EINVAL;
3407
3408done:
c0c36b94
CW		 3409 if (intel_encoder->base.crtc)
3410 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3411
3412 return 0;
3413}
3414
a4fc5ed6 3415static void
73845adf 3416intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3417{
1d508706 3418 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3419
9cd300e0
JN		 3420 if (!IS_ERR_OR_NULL(intel_connector->edid))
3421 kfree(intel_connector->edid);
3422
acd8db10
PZ		 3423 /* Can't call is_edp() since the encoder may have been destroyed
3424 * already. */
3425 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3426 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3427
a4fc5ed6 3428 drm_connector_cleanup(connector);
55f78c43 3429 kfree(connector);
a4fc5ed6
KP		 3430}
3431
00c09d70 3432void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3433{
da63a9f2
PZ		 3434 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3435 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3436 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3437
3438 i2c_del_adapter(&intel_dp->adapter);
3439 drm_encoder_cleanup(encoder);
bd943159
KP		 3440 if (is_edp(intel_dp)) {
3441 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3442 mutex_lock(&dev->mode_config.mutex);
4be73780 3443 edp_panel_vdd_off_sync(intel_dp);
bd173813 3444 mutex_unlock(&dev->mode_config.mutex);
bd943159 3445 }
da63a9f2 3446 kfree(intel_dig_port);
24d05927
DV		 3447}
3448
a4fc5ed6 3449static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3450 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3451 .detect = intel_dp_detect,
3452 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3453 .set_property = intel_dp_set_property,
73845adf 3454 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3455};
3456
3457static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3458 .get_modes = intel_dp_get_modes,
3459 .mode_valid = intel_dp_mode_valid,
df0e9248 3460 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3461};
3462
a4fc5ed6 3463static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3464 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3465};
3466
995b6762 3467static void
21d40d37 3468intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3469{
fa90ecef 3470 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3471
885a5014 3472 intel_dp_check_link_status(intel_dp);
c8110e52 3473}
6207937d 3474
e3421a18
ZW		 3475/* Return which DP Port should be selected for Transcoder DP control */
3476int
0206e353 3477intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3478{
3479 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3480 struct intel_encoder *intel_encoder;
3481 struct intel_dp *intel_dp;
e3421a18 3482
fa90ecef
PZ		 3483 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3484 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3485
fa90ecef
PZ		 3486 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3487 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3488 return intel_dp->output_reg;
e3421a18 3489 }
ea5b213a 3490
e3421a18
ZW		 3491 return -1;
3492}
3493
36e83a18 3494/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3495bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3496{
3497 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3498 union child_device_config *p_child;
36e83a18 3499 int i;
5d8a7752
VS		 3500 static const short port_mapping[] = {
3501 [PORT_B] = PORT_IDPB,
3502 [PORT_C] = PORT_IDPC,
3503 [PORT_D] = PORT_IDPD,
3504 };
36e83a18 3505
3b32a35b
VS		 3506 if (port == PORT_A)
3507 return true;
3508
41aa3448 3509 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3510 return false;
3511
41aa3448
RV		 3512 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3513 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3514
5d8a7752 3515 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3516 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3517 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3518 return true;
3519 }
3520 return false;
3521}
3522
f684960e
CW		 3523static void
3524intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3525{
53b41837
YN		 3526 struct intel_connector *intel_connector = to_intel_connector(connector);
3527
3f43c48d 3528 intel_attach_force_audio_property(connector);
e953fd7b 3529 intel_attach_broadcast_rgb_property(connector);
55bc60db 3530 intel_dp->color_range_auto = true;
53b41837
YN		 3531
3532 if (is_edp(intel_dp)) {
3533 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3534 drm_object_attach_property(
3535 &connector->base,
53b41837 3536 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3537 DRM_MODE_SCALE_ASPECT);
3538 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3539 }
f684960e
CW		 3540}
3541
dada1a9f
ID		 3542static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3543{
3544 intel_dp->last_power_cycle = jiffies;
3545 intel_dp->last_power_on = jiffies;
3546 intel_dp->last_backlight_off = jiffies;
3547}
3548
67a54566
DV		 3549static void
3550intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3551 struct intel_dp *intel_dp,
3552 struct edp_power_seq *out)
67a54566
DV		 3553{
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555 struct edp_power_seq cur, vbt, spec, final;
3556 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3557 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3558
3559 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3560 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3561 pp_on_reg = PCH_PP_ON_DELAYS;
3562 pp_off_reg = PCH_PP_OFF_DELAYS;
3563 pp_div_reg = PCH_PP_DIVISOR;
3564 } else {
bf13e81b
JN		 3565 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3566
3567 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3568 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3569 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3570 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3571 }
67a54566
DV		 3572
3573 /* Workaround: Need to write PP_CONTROL with the unlock key as
3574 * the very first thing. */
453c5420 3575 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3576 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3577
453c5420
JB		 3578 pp_on = I915_READ(pp_on_reg);
3579 pp_off = I915_READ(pp_off_reg);
3580 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3581
3582 /* Pull timing values out of registers */
3583 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3584 PANEL_POWER_UP_DELAY_SHIFT;
3585
3586 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3587 PANEL_LIGHT_ON_DELAY_SHIFT;
3588
3589 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3590 PANEL_LIGHT_OFF_DELAY_SHIFT;
3591
3592 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3593 PANEL_POWER_DOWN_DELAY_SHIFT;
3594
3595 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3596 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3597
3598 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3599 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3600
41aa3448 3601 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3602
3603 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3604 * our hw here, which are all in 100usec. */
3605 spec.t1_t3 = 210 * 10;
3606 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3607 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3608 spec.t10 = 500 * 10;
3609 /* This one is special and actually in units of 100ms, but zero
3610 * based in the hw (so we need to add 100 ms). But the sw vbt
3611 * table multiplies it with 1000 to make it in units of 100usec,
3612 * too. */
3613 spec.t11_t12 = (510 + 100) * 10;
3614
3615 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3616 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3617
3618 /* Use the max of the register settings and vbt. If both are
3619 * unset, fall back to the spec limits. */
3620#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3621 spec.field : \
3622 max(cur.field, vbt.field))
3623 assign_final(t1_t3);
3624 assign_final(t8);
3625 assign_final(t9);
3626 assign_final(t10);
3627 assign_final(t11_t12);
3628#undef assign_final
3629
3630#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3631 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3632 intel_dp->backlight_on_delay = get_delay(t8);
3633 intel_dp->backlight_off_delay = get_delay(t9);
3634 intel_dp->panel_power_down_delay = get_delay(t10);
3635 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3636#undef get_delay
3637
f30d26e4
JN		 3638 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3639 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3640 intel_dp->panel_power_cycle_delay);
3641
3642 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3643 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3644
3645 if (out)
3646 *out = final;
3647}
3648
3649static void
3650intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3651 struct intel_dp *intel_dp,
3652 struct edp_power_seq *seq)
3653{
3654 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3655 u32 pp_on, pp_off, pp_div, port_sel = 0;
3656 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3657 int pp_on_reg, pp_off_reg, pp_div_reg;
3658
3659 if (HAS_PCH_SPLIT(dev)) {
3660 pp_on_reg = PCH_PP_ON_DELAYS;
3661 pp_off_reg = PCH_PP_OFF_DELAYS;
3662 pp_div_reg = PCH_PP_DIVISOR;
3663 } else {
bf13e81b
JN		 3664 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3665
3666 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3667 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3668 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3669 }
3670
b2f19d1a
PZ		 3671 /*
3672 * And finally store the new values in the power sequencer. The
3673 * backlight delays are set to 1 because we do manual waits on them. For
3674 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3675 * we'll end up waiting for the backlight off delay twice: once when we
3676 * do the manual sleep, and once when we disable the panel and wait for
3677 * the PP_STATUS bit to become zero.
3678 */
f30d26e4 3679 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3680 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3681 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3682 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3683 /* Compute the divisor for the pp clock, simply match the Bspec
3684 * formula. */
453c5420 3685 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3686 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3687 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3688
3689 /* Haswell doesn't have any port selection bits for the panel
3690 * power sequencer any more. */
bc7d38a4 3691 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3692 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3693 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3694 else
3695 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3696 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3697 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3698 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3699 else
a24c144c 3700 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3701 }
3702
453c5420
JB		 3703 pp_on |= port_sel;
3704
3705 I915_WRITE(pp_on_reg, pp_on);
3706 I915_WRITE(pp_off_reg, pp_off);
3707 I915_WRITE(pp_div_reg, pp_div);
67a54566 3708
67a54566 3709 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3710 I915_READ(pp_on_reg),
3711 I915_READ(pp_off_reg),
3712 I915_READ(pp_div_reg));
f684960e
CW		 3713}
3714
ed92f0b2 3715static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3716 struct intel_connector *intel_connector,
3717 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3718{
3719 struct drm_connector *connector = &intel_connector->base;
3720 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3721 struct drm_device *dev = intel_dig_port->base.base.dev;
3722 struct drm_i915_private *dev_priv = dev->dev_private;
3723 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3724 bool has_dpcd;
3725 struct drm_display_mode *scan;
3726 struct edid *edid;
3727
3728 if (!is_edp(intel_dp))
3729 return true;
3730
ed92f0b2 3731 /* Cache DPCD and EDID for edp. */
4be73780 3732 edp_panel_vdd_on(intel_dp);
ed92f0b2 3733 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3734 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3735
3736 if (has_dpcd) {
3737 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3738 dev_priv->no_aux_handshake =
3739 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3740 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3741 } else {
3742 /* if this fails, presume the device is a ghost */
3743 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3744 return false;
3745 }
3746
3747 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3748 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3749
ed92f0b2
PZ		 3750 edid = drm_get_edid(connector, &intel_dp->adapter);
3751 if (edid) {
3752 if (drm_add_edid_modes(connector, edid)) {
3753 drm_mode_connector_update_edid_property(connector,
3754 edid);
3755 drm_edid_to_eld(connector, edid);
3756 } else {
3757 kfree(edid);
3758 edid = ERR_PTR(-EINVAL);
3759 }
3760 } else {
3761 edid = ERR_PTR(-ENOENT);
3762 }
3763 intel_connector->edid = edid;
3764
3765 /* prefer fixed mode from EDID if available */
3766 list_for_each_entry(scan, &connector->probed_modes, head) {
3767 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3768 fixed_mode = drm_mode_duplicate(dev, scan);
3769 break;
3770 }
3771 }
3772
3773 /* fallback to VBT if available for eDP */
3774 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3775 fixed_mode = drm_mode_duplicate(dev,
3776 dev_priv->vbt.lfp_lvds_vbt_mode);
3777 if (fixed_mode)
3778 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3779 }
3780
4b6ed685 3781 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3782 intel_panel_setup_backlight(connector);
3783
3784 return true;
3785}
3786
16c25533 3787bool
f0fec3f2
PZ		 3788intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3789 struct intel_connector *intel_connector)
a4fc5ed6 3790{
f0fec3f2
PZ		 3791 struct drm_connector *connector = &intel_connector->base;
3792 struct intel_dp *intel_dp = &intel_dig_port->dp;
3793 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3794 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3795 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3796 enum port port = intel_dig_port->port;
0095e6dc 3797 struct edp_power_seq power_seq = { 0 };
5eb08b69 3798 const char *name = NULL;
b2a14755 3799 int type, error;
a4fc5ed6 3800
ec5b01dd
DL		 3801 /* intel_dp vfuncs */
3802 if (IS_VALLEYVIEW(dev))
3803 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3804 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3805 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3806 else if (HAS_PCH_SPLIT(dev))
3807 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3808 else
3809 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3810
153b1100
DL		 3811 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3812
0767935e
DV		 3813 /* Preserve the current hw state. */
3814 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3815 intel_dp->attached_connector = intel_connector;
3d3dc149 3816
3b32a35b 3817 if (intel_dp_is_edp(dev, port))
b329530c 3818 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3819 else
3820 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3821
f7d24902
ID		 3822 /*
3823 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3824 * for DP the encoder type can be set by the caller to
3825 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3826 */
3827 if (type == DRM_MODE_CONNECTOR_eDP)
3828 intel_encoder->type = INTEL_OUTPUT_EDP;
3829
e7281eab
ID		 3830 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3831 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3832 port_name(port));
3833
b329530c 3834 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3835 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3836
a4fc5ed6
KP		 3837 connector->interlace_allowed = true;
3838 connector->doublescan_allowed = 0;
3839
f0fec3f2 3840 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3841 edp_panel_vdd_work);
a4fc5ed6 3842
df0e9248 3843 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3844 drm_sysfs_connector_add(connector);
3845
affa9354 3846 if (HAS_DDI(dev))
bcbc889b
PZ		 3847 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3848 else
3849 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3850 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3851
9ed35ab1
PZ		 3852 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3853 if (HAS_DDI(dev)) {
3854 switch (intel_dig_port->port) {
3855 case PORT_A:
3856 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3857 break;
3858 case PORT_B:
3859 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3860 break;
3861 case PORT_C:
3862 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3863 break;
3864 case PORT_D:
3865 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3866 break;
3867 default:
3868 BUG();
3869 }
3870 }
e8cb4558 3871
a4fc5ed6 3872 /* Set up the DDC bus. */
ab9d7c30
PZ		 3873 switch (port) {
3874 case PORT_A:
1d843f9d 3875 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3876 name = "DPDDC-A";
3877 break;
3878 case PORT_B:
1d843f9d 3879 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3880 name = "DPDDC-B";
3881 break;
3882 case PORT_C:
1d843f9d 3883 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3884 name = "DPDDC-C";
3885 break;
3886 case PORT_D:
1d843f9d 3887 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3888 name = "DPDDC-D";
3889 break;
3890 default:
ad1c0b19 3891 BUG();
5eb08b69
ZW		 3892 }
3893
dada1a9f
ID		 3894 if (is_edp(intel_dp)) {
3895 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3896 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3897 }
0095e6dc 3898
9d1a1031
JN		 3899 intel_dp_aux_init(intel_dp, intel_connector);
3900
b2a14755
PZ		 3901 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3902 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3903 error, port_name(port));
c1f05264 3904
2b28bb1b
RV		 3905 intel_dp->psr_setup_done = false;
3906
0095e6dc 3907 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3908 i2c_del_adapter(&intel_dp->adapter);
3909 if (is_edp(intel_dp)) {
3910 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3911 mutex_lock(&dev->mode_config.mutex);
4be73780 3912 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3913 mutex_unlock(&dev->mode_config.mutex);
3914 }
b2f246a8
PZ		 3915 drm_sysfs_connector_remove(connector);
3916 drm_connector_cleanup(connector);
16c25533 3917 return false;
b2f246a8 3918 }
32f9d658 3919
f684960e
CW		 3920 intel_dp_add_properties(intel_dp, connector);
3921
a4fc5ed6
KP		 3922 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3923 * 0xd. Failure to do so will result in spurious interrupts being
3924 * generated on the port when a cable is not attached.
3925 */
3926 if (IS_G4X(dev) && !IS_GM45(dev)) {
3927 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3928 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3929 }
16c25533
PZ		 3930
3931 return true;
a4fc5ed6 3932}
f0fec3f2
PZ		 3933
3934void
3935intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3936{
3937 struct intel_digital_port *intel_dig_port;
3938 struct intel_encoder *intel_encoder;
3939 struct drm_encoder *encoder;
3940 struct intel_connector *intel_connector;
3941
b14c5679 3942 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3943 if (!intel_dig_port)
3944 return;
3945
b14c5679 3946 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3947 if (!intel_connector) {
3948 kfree(intel_dig_port);
3949 return;
3950 }
3951
3952 intel_encoder = &intel_dig_port->base;
3953 encoder = &intel_encoder->base;
3954
3955 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3956 DRM_MODE_ENCODER_TMDS);
3957
5bfe2ac0 3958 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3959 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3960 intel_encoder->disable = intel_disable_dp;
3961 intel_encoder->post_disable = intel_post_disable_dp;
3962 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3963 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3964 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3965 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3966 intel_encoder->pre_enable = vlv_pre_enable_dp;
3967 intel_encoder->enable = vlv_enable_dp;
3968 } else {
ecff4f3b
JN		 3969 intel_encoder->pre_enable = g4x_pre_enable_dp;
3970 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3971 }
f0fec3f2 3972
174edf1f 3973 intel_dig_port->port = port;
f0fec3f2
PZ		 3974 intel_dig_port->dp.output_reg = output_reg;
3975
00c09d70 3976 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3977 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3978 intel_encoder->cloneable = false;
3979 intel_encoder->hot_plug = intel_dp_hot_plug;
3980
15b1d171
PZ		 3981 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3982 drm_encoder_cleanup(encoder);
3983 kfree(intel_dig_port);
b2f246a8 3984 kfree(intel_connector);
15b1d171 3985 }
f0fec3f2 3986}
Linux kernel - Deliverables
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