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drm/i915: Don't use link_bw to select between TP1 and TP3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15 97 324000, 432000, 540000 };
fe51bfb9
VS		 98static const int chv_rates[] = { 162000, 202500, 210000, 216000,
99 243000, 270000, 324000, 405000,
100 420000, 432000, 540000 };
f4896f15 101static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 102
cfcb0fc9
JB		 103/**
104 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
105 * @intel_dp: DP struct
106 *
107 * If a CPU or PCH DP output is attached to an eDP panel, this function
108 * will return true, and false otherwise.
109 */
110static bool is_edp(struct intel_dp *intel_dp)
111{
da63a9f2
PZ		 112 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
113
114 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 115}
116
68b4d824 117static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 118{
68b4d824
ID		 119 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
120
121 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 122}
123
df0e9248
CW		 124static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
125{
fa90ecef 126 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 127}
128
ea5b213a 129static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 130static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 131static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 132static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 133static void vlv_steal_power_sequencer(struct drm_device *dev,
134 enum pipe pipe);
a4fc5ed6 135
ed4e9c1d
VS		 136static int
137intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 138{
7183dc29 139 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 140
141 switch (max_link_bw) {
142 case DP_LINK_BW_1_62:
143 case DP_LINK_BW_2_7:
1db10e28 144 case DP_LINK_BW_5_4:
d4eead50 145 break;
a4fc5ed6 146 default:
d4eead50
ID		 147 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
148 max_link_bw);
a4fc5ed6
KP		 149 max_link_bw = DP_LINK_BW_1_62;
150 break;
151 }
152 return max_link_bw;
153}
154
eeb6324d
PZ		 155static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
156{
157 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
158 struct drm_device *dev = intel_dig_port->base.base.dev;
159 u8 source_max, sink_max;
160
161 source_max = 4;
162 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
163 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
164 source_max = 2;
165
166 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
167
168 return min(source_max, sink_max);
169}
170
cd9dde44
AJ		 171/*
172 * The units on the numbers in the next two are... bizarre. Examples will
173 * make it clearer; this one parallels an example in the eDP spec.
174 *
175 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
176 *
177 * 270000 * 1 * 8 / 10 == 216000
178 *
179 * The actual data capacity of that configuration is 2.16Gbit/s, so the
180 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
181 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
182 * 119000. At 18bpp that's 2142000 kilobits per second.
183 *
184 * Thus the strange-looking division by 10 in intel_dp_link_required, to
185 * get the result in decakilobits instead of kilobits.
186 */
187
a4fc5ed6 188static int
c898261c 189intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 190{
cd9dde44 191 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 192}
193
fe27d53e
DA		 194static int
195intel_dp_max_data_rate(int max_link_clock, int max_lanes)
196{
197 return (max_link_clock * max_lanes * 8) / 10;
198}
199
c19de8eb 200static enum drm_mode_status
a4fc5ed6
KP		 201intel_dp_mode_valid(struct drm_connector *connector,
202 struct drm_display_mode *mode)
203{
df0e9248 204 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 205 struct intel_connector *intel_connector = to_intel_connector(connector);
206 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 207 int target_clock = mode->clock;
208 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 209
dd06f90e
JN		 210 if (is_edp(intel_dp) && fixed_mode) {
211 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 212 return MODE_PANEL;
213
dd06f90e 214 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 215 return MODE_PANEL;
03afc4a2
DV		 216
217 target_clock = fixed_mode->clock;
7de56f43
ZY		 218 }
219
50fec21a 220 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 221 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 222
223 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
224 mode_rate = intel_dp_link_required(target_clock, 18);
225
226 if (mode_rate > max_rate)
c4867936 227 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 228
229 if (mode->clock < 10000)
230 return MODE_CLOCK_LOW;
231
0af78a2b
DV		 232 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
233 return MODE_H_ILLEGAL;
234
a4fc5ed6
KP		 235 return MODE_OK;
236}
237
a4f1289e 238uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 239{
240 int i;
241 uint32_t v = 0;
242
243 if (src_bytes > 4)
244 src_bytes = 4;
245 for (i = 0; i < src_bytes; i++)
246 v |= ((uint32_t) src[i]) << ((3-i) * 8);
247 return v;
248}
249
c2af70e2 250static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
bf13e81b
JN		 293static void
294intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 295 struct intel_dp *intel_dp);
bf13e81b
JN		 296static void
297intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 298 struct intel_dp *intel_dp);
bf13e81b 299
773538e8
VS		 300static void pps_lock(struct intel_dp *intel_dp)
301{
302 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
303 struct intel_encoder *encoder = &intel_dig_port->base;
304 struct drm_device *dev = encoder->base.dev;
305 struct drm_i915_private *dev_priv = dev->dev_private;
306 enum intel_display_power_domain power_domain;
307
308 /*
309 * See vlv_power_sequencer_reset() why we need
310 * a power domain reference here.
311 */
312 power_domain = intel_display_port_power_domain(encoder);
313 intel_display_power_get(dev_priv, power_domain);
314
315 mutex_lock(&dev_priv->pps_mutex);
316}
317
318static void pps_unlock(struct intel_dp *intel_dp)
319{
320 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
321 struct intel_encoder *encoder = &intel_dig_port->base;
322 struct drm_device *dev = encoder->base.dev;
323 struct drm_i915_private *dev_priv = dev->dev_private;
324 enum intel_display_power_domain power_domain;
325
326 mutex_unlock(&dev_priv->pps_mutex);
327
328 power_domain = intel_display_port_power_domain(encoder);
329 intel_display_power_put(dev_priv, power_domain);
330}
331
961a0db0
VS		 332static void
333vlv_power_sequencer_kick(struct intel_dp *intel_dp)
334{
335 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
336 struct drm_device *dev = intel_dig_port->base.base.dev;
337 struct drm_i915_private *dev_priv = dev->dev_private;
338 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 339 bool pll_enabled;
961a0db0
VS		 340 uint32_t DP;
341
342 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
343 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
344 pipe_name(pipe), port_name(intel_dig_port->port)))
345 return;
346
347 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
348 pipe_name(pipe), port_name(intel_dig_port->port));
349
350 /* Preserve the BIOS-computed detected bit. This is
351 * supposed to be read-only.
352 */
353 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
354 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
355 DP |= DP_PORT_WIDTH(1);
356 DP |= DP_LINK_TRAIN_PAT_1;
357
358 if (IS_CHERRYVIEW(dev))
359 DP |= DP_PIPE_SELECT_CHV(pipe);
360 else if (pipe == PIPE_B)
361 DP |= DP_PIPEB_SELECT;
362
d288f65f
VS		 363 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
364
365 /*
366 * The DPLL for the pipe must be enabled for this to work.
367 * So enable temporarily it if it's not already enabled.
368 */
369 if (!pll_enabled)
370 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
371 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
372
961a0db0
VS		 373 /*
374 * Similar magic as in intel_dp_enable_port().
375 * We _must_ do this port enable + disable trick
376 * to make this power seqeuencer lock onto the port.
377 * Otherwise even VDD force bit won't work.
378 */
379 I915_WRITE(intel_dp->output_reg, DP);
380 POSTING_READ(intel_dp->output_reg);
381
382 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
383 POSTING_READ(intel_dp->output_reg);
384
385 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
386 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 387
388 if (!pll_enabled)
389 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 390}
391
bf13e81b
JN		 392static enum pipe
393vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
394{
395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 396 struct drm_device *dev = intel_dig_port->base.base.dev;
397 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 398 struct intel_encoder *encoder;
399 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 400 enum pipe pipe;
bf13e81b 401
e39b999a 402 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 403
a8c3344e
VS		 404 /* We should never land here with regular DP ports */
405 WARN_ON(!is_edp(intel_dp));
406
a4a5d2f8
VS		 407 if (intel_dp->pps_pipe != INVALID_PIPE)
408 return intel_dp->pps_pipe;
409
410 /*
411 * We don't have power sequencer currently.
412 * Pick one that's not used by other ports.
413 */
414 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
415 base.head) {
416 struct intel_dp *tmp;
417
418 if (encoder->type != INTEL_OUTPUT_EDP)
419 continue;
420
421 tmp = enc_to_intel_dp(&encoder->base);
422
423 if (tmp->pps_pipe != INVALID_PIPE)
424 pipes &= ~(1 << tmp->pps_pipe);
425 }
426
427 /*
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
430 */
431 if (WARN_ON(pipes == 0))
a8c3344e
VS		 432 pipe = PIPE_A;
433 else
434 pipe = ffs(pipes) - 1;
a4a5d2f8 435
a8c3344e
VS		 436 vlv_steal_power_sequencer(dev, pipe);
437 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 438
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp->pps_pipe),
441 port_name(intel_dig_port->port));
442
443 /* init power sequencer on this pipe and port */
36b5f425
VS		 444 intel_dp_init_panel_power_sequencer(dev, intel_dp);
445 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 446
961a0db0
VS		 447 /*
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
450 */
451 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 452
453 return intel_dp->pps_pipe;
454}
455
6491ab27
VS		 456typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
457 enum pipe pipe);
458
459static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
460 enum pipe pipe)
461{
462 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
463}
464
465static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
466 enum pipe pipe)
467{
468 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
469}
470
471static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
472 enum pipe pipe)
473{
474 return true;
475}
bf13e81b 476
a4a5d2f8 477static enum pipe
6491ab27
VS		 478vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
479 enum port port,
480 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 481{
482 enum pipe pipe;
bf13e81b 483
bf13e81b
JN		 484 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
485 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
486 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 487
488 if (port_sel != PANEL_PORT_SELECT_VLV(port))
489 continue;
490
6491ab27
VS		 491 if (!pipe_check(dev_priv, pipe))
492 continue;
493
a4a5d2f8 494 return pipe;
bf13e81b
JN		 495 }
496
a4a5d2f8
VS		 497 return INVALID_PIPE;
498}
499
500static void
501vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
502{
503 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
504 struct drm_device *dev = intel_dig_port->base.base.dev;
505 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 506 enum port port = intel_dig_port->port;
507
508 lockdep_assert_held(&dev_priv->pps_mutex);
509
510 /* try to find a pipe with this port selected */
6491ab27
VS		 511 /* first pick one where the panel is on */
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_has_pp_on);
514 /* didn't find one? pick one where vdd is on */
515 if (intel_dp->pps_pipe == INVALID_PIPE)
516 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
517 vlv_pipe_has_vdd_on);
518 /* didn't find one? pick one with just the correct port */
519 if (intel_dp->pps_pipe == INVALID_PIPE)
520 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
521 vlv_pipe_any);
a4a5d2f8
VS		 522
523 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
524 if (intel_dp->pps_pipe == INVALID_PIPE) {
525 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
526 port_name(port));
527 return;
bf13e81b
JN		 528 }
529
a4a5d2f8
VS		 530 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
531 port_name(port), pipe_name(intel_dp->pps_pipe));
532
36b5f425
VS		 533 intel_dp_init_panel_power_sequencer(dev, intel_dp);
534 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 535}
536
773538e8
VS		 537void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
538{
539 struct drm_device *dev = dev_priv->dev;
540 struct intel_encoder *encoder;
541
542 if (WARN_ON(!IS_VALLEYVIEW(dev)))
543 return;
544
545 /*
546 * We can't grab pps_mutex here due to deadlock with power_domain
547 * mutex when power_domain functions are called while holding pps_mutex.
548 * That also means that in order to use pps_pipe the code needs to
549 * hold both a power domain reference and pps_mutex, and the power domain
550 * reference get/put must be done while _not_ holding pps_mutex.
551 * pps_{lock,unlock}() do these steps in the correct order, so one
552 * should use them always.
553 */
554
555 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
556 struct intel_dp *intel_dp;
557
558 if (encoder->type != INTEL_OUTPUT_EDP)
559 continue;
560
561 intel_dp = enc_to_intel_dp(&encoder->base);
562 intel_dp->pps_pipe = INVALID_PIPE;
563 }
bf13e81b
JN		 564}
565
566static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
567{
568 struct drm_device *dev = intel_dp_to_dev(intel_dp);
569
b0a08bec
VK		 570 if (IS_BROXTON(dev))
571 return BXT_PP_CONTROL(0);
572 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 573 return PCH_PP_CONTROL;
574 else
575 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
576}
577
578static u32 _pp_stat_reg(struct intel_dp *intel_dp)
579{
580 struct drm_device *dev = intel_dp_to_dev(intel_dp);
581
b0a08bec
VK		 582 if (IS_BROXTON(dev))
583 return BXT_PP_STATUS(0);
584 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 585 return PCH_PP_STATUS;
586 else
587 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
588}
589
01527b31
CT		 590/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
591 This function only applicable when panel PM state is not to be tracked */
592static int edp_notify_handler(struct notifier_block *this, unsigned long code,
593 void *unused)
594{
595 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
596 edp_notifier);
597 struct drm_device *dev = intel_dp_to_dev(intel_dp);
598 struct drm_i915_private *dev_priv = dev->dev_private;
599 u32 pp_div;
600 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 601
602 if (!is_edp(intel_dp) || code != SYS_RESTART)
603 return 0;
604
773538e8 605 pps_lock(intel_dp);
e39b999a 606
01527b31 607 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 608 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
609
01527b31
CT		 610 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
611 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
612 pp_div = I915_READ(pp_div_reg);
613 pp_div &= PP_REFERENCE_DIVIDER_MASK;
614
615 /* 0x1F write to PP_DIV_REG sets max cycle delay */
616 I915_WRITE(pp_div_reg, pp_div | 0x1F);
617 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
618 msleep(intel_dp->panel_power_cycle_delay);
619 }
620
773538e8 621 pps_unlock(intel_dp);
e39b999a 622
01527b31
CT		 623 return 0;
624}
625
4be73780 626static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 627{
30add22d 628 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 629 struct drm_i915_private *dev_priv = dev->dev_private;
630
e39b999a
VS		 631 lockdep_assert_held(&dev_priv->pps_mutex);
632
9a42356b
VS		 633 if (IS_VALLEYVIEW(dev) &&
634 intel_dp->pps_pipe == INVALID_PIPE)
635 return false;
636
bf13e81b 637 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 638}
639
4be73780 640static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 641{
30add22d 642 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 643 struct drm_i915_private *dev_priv = dev->dev_private;
644
e39b999a
VS		 645 lockdep_assert_held(&dev_priv->pps_mutex);
646
9a42356b
VS		 647 if (IS_VALLEYVIEW(dev) &&
648 intel_dp->pps_pipe == INVALID_PIPE)
649 return false;
650
773538e8 651 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 652}
653
9b984dae
KP		 654static void
655intel_dp_check_edp(struct intel_dp *intel_dp)
656{
30add22d 657 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 658 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 659
9b984dae
KP		 660 if (!is_edp(intel_dp))
661 return;
453c5420 662
4be73780 663 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 664 WARN(1, "eDP powered off while attempting aux channel communication.\n");
665 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 666 I915_READ(_pp_stat_reg(intel_dp)),
667 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 668 }
669}
670
9ee32fea
DV		 671static uint32_t
672intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
673{
674 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
675 struct drm_device *dev = intel_dig_port->base.base.dev;
676 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 677 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 678 uint32_t status;
679 bool done;
680
ef04f00d 681#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 682 if (has_aux_irq)
b18ac466 683 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 684 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 685 else
686 done = wait_for_atomic(C, 10) == 0;
687 if (!done)
688 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
689 has_aux_irq);
690#undef C
691
692 return status;
693}
694
ec5b01dd 695static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 696{
174edf1f
PZ		 697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 699
ec5b01dd
DL		 700 /*
701 * The clock divider is based off the hrawclk, and would like to run at
702 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 703 */
ec5b01dd
DL		 704 return index ? 0 : intel_hrawclk(dev) / 2;
705}
706
707static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
708{
709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
710 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 711 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 712
713 if (index)
714 return 0;
715
716 if (intel_dig_port->port == PORT_A) {
05024da3
VS		 717 return DIV_ROUND_UP(dev_priv->cdclk_freq, 2000);
718
ec5b01dd
DL		 719 } else {
720 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
721 }
722}
723
724static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
725{
726 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
727 struct drm_device *dev = intel_dig_port->base.base.dev;
728 struct drm_i915_private *dev_priv = dev->dev_private;
729
730 if (intel_dig_port->port == PORT_A) {
731 if (index)
732 return 0;
05024da3 733 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
2c55c336
JN		 734 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
735 /* Workaround for non-ULT HSW */
bc86625a
CW		 736 switch (index) {
737 case 0: return 63;
738 case 1: return 72;
739 default: return 0;
740 }
ec5b01dd 741 } else {
bc86625a 742 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 743 }
b84a1cf8
RV		 744}
745
ec5b01dd
DL		 746static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
747{
748 return index ? 0 : 100;
749}
750
b6b5e383
DL		 751static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
752{
753 /*
754 * SKL doesn't need us to program the AUX clock divider (Hardware will
755 * derive the clock from CDCLK automatically). We still implement the
756 * get_aux_clock_divider vfunc to plug-in into the existing code.
757 */
758 return index ? 0 : 1;
759}
760
5ed12a19
DL		 761static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
762 bool has_aux_irq,
763 int send_bytes,
764 uint32_t aux_clock_divider)
765{
766 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
767 struct drm_device *dev = intel_dig_port->base.base.dev;
768 uint32_t precharge, timeout;
769
770 if (IS_GEN6(dev))
771 precharge = 3;
772 else
773 precharge = 5;
774
775 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
776 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
777 else
778 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
779
780 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 781 DP_AUX_CH_CTL_DONE |
5ed12a19 782 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 783 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 784 timeout |
788d4433 785 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 786 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
787 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 788 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 789}
790
b9ca5fad
DL		 791static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
792 bool has_aux_irq,
793 int send_bytes,
794 uint32_t unused)
795{
796 return DP_AUX_CH_CTL_SEND_BUSY |
797 DP_AUX_CH_CTL_DONE |
798 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
799 DP_AUX_CH_CTL_TIME_OUT_ERROR |
800 DP_AUX_CH_CTL_TIME_OUT_1600us |
801 DP_AUX_CH_CTL_RECEIVE_ERROR |
802 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
803 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
804}
805
b84a1cf8
RV		 806static int
807intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 808 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 809 uint8_t *recv, int recv_size)
810{
811 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
812 struct drm_device *dev = intel_dig_port->base.base.dev;
813 struct drm_i915_private *dev_priv = dev->dev_private;
814 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
815 uint32_t ch_data = ch_ctl + 4;
bc86625a 816 uint32_t aux_clock_divider;
b84a1cf8
RV		 817 int i, ret, recv_bytes;
818 uint32_t status;
5ed12a19 819 int try, clock = 0;
4e6b788c 820 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 821 bool vdd;
822
773538e8 823 pps_lock(intel_dp);
e39b999a 824
72c3500a
VS		 825 /*
826 * We will be called with VDD already enabled for dpcd/edid/oui reads.
827 * In such cases we want to leave VDD enabled and it's up to upper layers
828 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
829 * ourselves.
830 */
1e0560e0 831 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 832
833 /* dp aux is extremely sensitive to irq latency, hence request the
834 * lowest possible wakeup latency and so prevent the cpu from going into
835 * deep sleep states.
836 */
837 pm_qos_update_request(&dev_priv->pm_qos, 0);
838
839 intel_dp_check_edp(intel_dp);
5eb08b69 840
c67a470b
PZ		 841 intel_aux_display_runtime_get(dev_priv);
842
11bee43e
JB		 843 /* Try to wait for any previous AUX channel activity */
844 for (try = 0; try < 3; try++) {
ef04f00d 845 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 846 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
847 break;
848 msleep(1);
849 }
850
851 if (try == 3) {
02196c77
MK		 852 static u32 last_status = -1;
853 const u32 status = I915_READ(ch_ctl);
854
855 if (status != last_status) {
856 WARN(1, "dp_aux_ch not started status 0x%08x\n",
857 status);
858 last_status = status;
859 }
860
9ee32fea
DV		 861 ret = -EBUSY;
862 goto out;
4f7f7b7e
CW		 863 }
864
46a5ae9f
PZ		 865 /* Only 5 data registers! */
866 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
867 ret = -E2BIG;
868 goto out;
869 }
870
ec5b01dd 871 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 872 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
873 has_aux_irq,
874 send_bytes,
875 aux_clock_divider);
5ed12a19 876
bc86625a
CW		 877 /* Must try at least 3 times according to DP spec */
878 for (try = 0; try < 5; try++) {
879 /* Load the send data into the aux channel data registers */
880 for (i = 0; i < send_bytes; i += 4)
881 I915_WRITE(ch_data + i,
a4f1289e
RV		 882 intel_dp_pack_aux(send + i,
883 send_bytes - i));
bc86625a
CW		 884
885 /* Send the command and wait for it to complete */
5ed12a19 886 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 887
888 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
889
890 /* Clear done status and any errors */
891 I915_WRITE(ch_ctl,
892 status |
893 DP_AUX_CH_CTL_DONE |
894 DP_AUX_CH_CTL_TIME_OUT_ERROR |
895 DP_AUX_CH_CTL_RECEIVE_ERROR);
896
74ebf294 897 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 898 continue;
74ebf294
TP		 899
900 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
901 * 400us delay required for errors and timeouts
902 * Timeout errors from the HW already meet this
903 * requirement so skip to next iteration
904 */
905 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
906 usleep_range(400, 500);
bc86625a 907 continue;
74ebf294 908 }
bc86625a 909 if (status & DP_AUX_CH_CTL_DONE)
e058c945 910 goto done;
bc86625a 911 }
a4fc5ed6
KP		 912 }
913
a4fc5ed6 914 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 915 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 916 ret = -EBUSY;
917 goto out;
a4fc5ed6
KP		 918 }
919
e058c945 920done:
a4fc5ed6
KP		 921 /* Check for timeout or receive error.
922 * Timeouts occur when the sink is not connected
923 */
a5b3da54 924 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 925 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 926 ret = -EIO;
927 goto out;
a5b3da54 928 }
1ae8c0a5
KP		 929
930 /* Timeouts occur when the device isn't connected, so they're
931 * "normal" -- don't fill the kernel log with these */
a5b3da54 932 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 933 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 934 ret = -ETIMEDOUT;
935 goto out;
a4fc5ed6
KP		 936 }
937
938 /* Unload any bytes sent back from the other side */
939 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
940 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 941 if (recv_bytes > recv_size)
942 recv_bytes = recv_size;
0206e353 943
4f7f7b7e 944 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 945 intel_dp_unpack_aux(I915_READ(ch_data + i),
946 recv + i, recv_bytes - i);
a4fc5ed6 947
9ee32fea
DV		 948 ret = recv_bytes;
949out:
950 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 951 intel_aux_display_runtime_put(dev_priv);
9ee32fea 952
884f19e9
JN		 953 if (vdd)
954 edp_panel_vdd_off(intel_dp, false);
955
773538e8 956 pps_unlock(intel_dp);
e39b999a 957
9ee32fea 958 return ret;
a4fc5ed6
KP		 959}
960
a6c8aff0
JN		 961#define BARE_ADDRESS_SIZE 3
962#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 963static ssize_t
964intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 965{
9d1a1031
JN		 966 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
967 uint8_t txbuf[20], rxbuf[20];
968 size_t txsize, rxsize;
a4fc5ed6 969 int ret;
a4fc5ed6 970
d2d9cbbd
VS		 971 txbuf[0] = (msg->request << 4) |
972 ((msg->address >> 16) & 0xf);
973 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 974 txbuf[2] = msg->address & 0xff;
975 txbuf[3] = msg->size - 1;
46a5ae9f 976
9d1a1031
JN		 977 switch (msg->request & ~DP_AUX_I2C_MOT) {
978 case DP_AUX_NATIVE_WRITE:
979 case DP_AUX_I2C_WRITE:
a6c8aff0 980 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 981 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 982
9d1a1031
JN		 983 if (WARN_ON(txsize > 20))
984 return -E2BIG;
a4fc5ed6 985
9d1a1031 986 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 987
9d1a1031
JN		 988 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
989 if (ret > 0) {
990 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 991
a1ddefd8
JN		 992 if (ret > 1) {
993 /* Number of bytes written in a short write. */
994 ret = clamp_t(int, rxbuf[1], 0, msg->size);
995 } else {
996 /* Return payload size. */
997 ret = msg->size;
998 }
9d1a1031
JN		 999 }
1000 break;
46a5ae9f 1001
9d1a1031
JN		 1002 case DP_AUX_NATIVE_READ:
1003 case DP_AUX_I2C_READ:
a6c8aff0 1004 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1005 rxsize = msg->size + 1;
a4fc5ed6 1006
9d1a1031
JN		 1007 if (WARN_ON(rxsize > 20))
1008 return -E2BIG;
a4fc5ed6 1009
9d1a1031
JN		 1010 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1011 if (ret > 0) {
1012 msg->reply = rxbuf[0] >> 4;
1013 /*
1014 * Assume happy day, and copy the data. The caller is
1015 * expected to check msg->reply before touching it.
1016 *
1017 * Return payload size.
1018 */
1019 ret--;
1020 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1021 }
9d1a1031
JN		 1022 break;
1023
1024 default:
1025 ret = -EINVAL;
1026 break;
a4fc5ed6 1027 }
f51a44b9 1028
9d1a1031 1029 return ret;
a4fc5ed6
KP		 1030}
1031
9d1a1031
JN		 1032static void
1033intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1034{
1035 struct drm_device *dev = intel_dp_to_dev(intel_dp);
500ea70d 1036 struct drm_i915_private *dev_priv = dev->dev_private;
33ad6626
JN		 1037 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1038 enum port port = intel_dig_port->port;
500ea70d 1039 struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
0b99836f 1040 const char *name = NULL;
500ea70d 1041 uint32_t porte_aux_ctl_reg = DPA_AUX_CH_CTL;
ab2c0672
DA		 1042 int ret;
1043
500ea70d
RV		 1044 /* On SKL we don't have Aux for port E so we rely on VBT to set
1045 * a proper alternate aux channel.
1046 */
1047 if (IS_SKYLAKE(dev) && port == PORT_E) {
1048 switch (info->alternate_aux_channel) {
1049 case DP_AUX_B:
1050 porte_aux_ctl_reg = DPB_AUX_CH_CTL;
1051 break;
1052 case DP_AUX_C:
1053 porte_aux_ctl_reg = DPC_AUX_CH_CTL;
1054 break;
1055 case DP_AUX_D:
1056 porte_aux_ctl_reg = DPD_AUX_CH_CTL;
1057 break;
1058 case DP_AUX_A:
1059 default:
1060 porte_aux_ctl_reg = DPA_AUX_CH_CTL;
1061 }
1062 }
1063
33ad6626
JN		 1064 switch (port) {
1065 case PORT_A:
1066 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1067 name = "DPDDC-A";
ab2c0672 1068 break;
33ad6626
JN		 1069 case PORT_B:
1070 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1071 name = "DPDDC-B";
ab2c0672 1072 break;
33ad6626
JN		 1073 case PORT_C:
1074 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1075 name = "DPDDC-C";
ab2c0672 1076 break;
33ad6626
JN		 1077 case PORT_D:
1078 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1079 name = "DPDDC-D";
33ad6626 1080 break;
500ea70d
RV		 1081 case PORT_E:
1082 intel_dp->aux_ch_ctl_reg = porte_aux_ctl_reg;
1083 name = "DPDDC-E";
1084 break;
33ad6626
JN		 1085 default:
1086 BUG();
ab2c0672
DA		 1087 }
1088
1b1aad75
DL		 1089 /*
1090 * The AUX_CTL register is usually DP_CTL + 0x10.
1091 *
1092 * On Haswell and Broadwell though:
1093 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1094 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1095 *
1096 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1097 */
500ea70d 1098 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && port != PORT_E)
33ad6626 1099 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1100
0b99836f 1101 intel_dp->aux.name = name;
9d1a1031
JN		 1102 intel_dp->aux.dev = dev->dev;
1103 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1104
0b99836f
JN		 1105 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1106 connector->base.kdev->kobj.name);
8316f337 1107
4f71d0cb 1108 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1109 if (ret < 0) {
4f71d0cb 1110 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1111 name, ret);
1112 return;
ab2c0672 1113 }
8a5e6aeb 1114
0b99836f
JN		 1115 ret = sysfs_create_link(&connector->base.kdev->kobj,
1116 &intel_dp->aux.ddc.dev.kobj,
1117 intel_dp->aux.ddc.dev.kobj.name);
1118 if (ret < 0) {
1119 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1120 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1121 }
a4fc5ed6
KP		 1122}
1123
80f65de3
ID		 1124static void
1125intel_dp_connector_unregister(struct intel_connector *intel_connector)
1126{
1127 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1128
0e32b39c
DA		 1129 if (!intel_connector->mst_port)
1130 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1131 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1132 intel_connector_unregister(intel_connector);
1133}
1134
5416d871 1135static void
840b32b7 1136skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
5416d871
DL		 1137{
1138 u32 ctrl1;
1139
dd3cd74a
ACO		 1140 memset(&pipe_config->dpll_hw_state, 0,
1141 sizeof(pipe_config->dpll_hw_state));
1142
5416d871
DL		 1143 pipe_config->ddi_pll_sel = SKL_DPLL0;
1144 pipe_config->dpll_hw_state.cfgcr1 = 0;
1145 pipe_config->dpll_hw_state.cfgcr2 = 0;
1146
1147 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
840b32b7 1148 switch (pipe_config->port_clock / 2) {
c3346ef6 1149 case 81000:
71cd8423 1150 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5416d871
DL		 1151 SKL_DPLL0);
1152 break;
c3346ef6 1153 case 135000:
71cd8423 1154 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
5416d871
DL		 1155 SKL_DPLL0);
1156 break;
c3346ef6 1157 case 270000:
71cd8423 1158 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
5416d871
DL		 1159 SKL_DPLL0);
1160 break;
c3346ef6 1161 case 162000:
71cd8423 1162 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
c3346ef6
SJ		 1163 SKL_DPLL0);
1164 break;
1165 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1166 results in CDCLK change. Need to handle the change of CDCLK by
1167 disabling pipes and re-enabling them */
1168 case 108000:
71cd8423 1169 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
c3346ef6
SJ		 1170 SKL_DPLL0);
1171 break;
1172 case 216000:
71cd8423 1173 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
c3346ef6
SJ		 1174 SKL_DPLL0);
1175 break;
1176
5416d871
DL		 1177 }
1178 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1179}
1180
0e50338c 1181static void
840b32b7 1182hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
0e50338c 1183{
ee46f3c7
ACO		 1184 memset(&pipe_config->dpll_hw_state, 0,
1185 sizeof(pipe_config->dpll_hw_state));
1186
840b32b7
VS		 1187 switch (pipe_config->port_clock / 2) {
1188 case 81000:
0e50338c
DV		 1189 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1190 break;
840b32b7 1191 case 135000:
0e50338c
DV		 1192 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1193 break;
840b32b7 1194 case 270000:
0e50338c
DV		 1195 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1196 break;
1197 }
1198}
1199
fc0f8e25 1200static int
12f6a2e2 1201intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1202{
94ca719e
VS		 1203 if (intel_dp->num_sink_rates) {
1204 *sink_rates = intel_dp->sink_rates;
1205 return intel_dp->num_sink_rates;
fc0f8e25 1206 }
12f6a2e2
VS		 1207
1208 *sink_rates = default_rates;
1209
1210 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1211}
1212
a8f3ef61 1213static int
1db10e28 1214intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
a8f3ef61 1215{
64987fc5
SJ		 1216 if (IS_BROXTON(dev)) {
1217 *source_rates = bxt_rates;
1218 return ARRAY_SIZE(bxt_rates);
1219 } else if (IS_SKYLAKE(dev)) {
637a9c63
SJ		 1220 *source_rates = skl_rates;
1221 return ARRAY_SIZE(skl_rates);
fe51bfb9
VS		 1222 } else if (IS_CHERRYVIEW(dev)) {
1223 *source_rates = chv_rates;
1224 return ARRAY_SIZE(chv_rates);
a8f3ef61 1225 }
636280ba
VS		 1226
1227 *source_rates = default_rates;
1228
1db10e28
VS		 1229 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1230 /* WaDisableHBR2:skl */
1231 return (DP_LINK_BW_2_7 >> 3) + 1;
1232 else if (INTEL_INFO(dev)->gen >= 8 ||
1233 (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1234 return (DP_LINK_BW_5_4 >> 3) + 1;
1235 else
1236 return (DP_LINK_BW_2_7 >> 3) + 1;
a8f3ef61
SJ		 1237}
1238
c6bb3538
DV		 1239static void
1240intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1241 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1242{
1243 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1244 const struct dp_link_dpll *divisor = NULL;
1245 int i, count = 0;
c6bb3538
DV		 1246
1247 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1248 divisor = gen4_dpll;
1249 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1250 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1251 divisor = pch_dpll;
1252 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1253 } else if (IS_CHERRYVIEW(dev)) {
1254 divisor = chv_dpll;
1255 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1256 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1257 divisor = vlv_dpll;
1258 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1259 }
9dd4ffdf
CML		 1260
1261 if (divisor && count) {
1262 for (i = 0; i < count; i++) {
840b32b7 1263 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1264 pipe_config->dpll = divisor[i].dpll;
1265 pipe_config->clock_set = true;
1266 break;
1267 }
1268 }
c6bb3538
DV		 1269 }
1270}
1271
2ecae76a
VS		 1272static int intersect_rates(const int *source_rates, int source_len,
1273 const int *sink_rates, int sink_len,
94ca719e 1274 int *common_rates)
a8f3ef61
SJ		 1275{
1276 int i = 0, j = 0, k = 0;
1277
a8f3ef61
SJ		 1278 while (i < source_len && j < sink_len) {
1279 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1280 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1281 return k;
94ca719e 1282 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1283 ++k;
1284 ++i;
1285 ++j;
1286 } else if (source_rates[i] < sink_rates[j]) {
1287 ++i;
1288 } else {
1289 ++j;
1290 }
1291 }
1292 return k;
1293}
1294
94ca719e
VS		 1295static int intel_dp_common_rates(struct intel_dp *intel_dp,
1296 int *common_rates)
2ecae76a
VS		 1297{
1298 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1299 const int *source_rates, *sink_rates;
1300 int source_len, sink_len;
1301
1302 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1303 source_len = intel_dp_source_rates(dev, &source_rates);
1304
1305 return intersect_rates(source_rates, source_len,
1306 sink_rates, sink_len,
94ca719e 1307 common_rates);
2ecae76a
VS		 1308}
1309
0336400e
VS		 1310static void snprintf_int_array(char *str, size_t len,
1311 const int *array, int nelem)
1312{
1313 int i;
1314
1315 str[0] = '\0';
1316
1317 for (i = 0; i < nelem; i++) {
b2f505be 1318 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1319 if (r >= len)
1320 return;
1321 str += r;
1322 len -= r;
1323 }
1324}
1325
1326static void intel_dp_print_rates(struct intel_dp *intel_dp)
1327{
1328 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1329 const int *source_rates, *sink_rates;
94ca719e
VS		 1330 int source_len, sink_len, common_len;
1331 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1332 char str[128]; /* FIXME: too big for stack? */
1333
1334 if ((drm_debug & DRM_UT_KMS) == 0)
1335 return;
1336
1337 source_len = intel_dp_source_rates(dev, &source_rates);
1338 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1339 DRM_DEBUG_KMS("source rates: %s\n", str);
1340
1341 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1342 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1343 DRM_DEBUG_KMS("sink rates: %s\n", str);
1344
94ca719e
VS		 1345 common_len = intel_dp_common_rates(intel_dp, common_rates);
1346 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1347 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1348}
1349
f4896f15 1350static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1351{
1352 int i = 0;
1353
1354 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1355 if (find == rates[i])
1356 break;
1357
1358 return i;
1359}
1360
50fec21a
VS		 1361int
1362intel_dp_max_link_rate(struct intel_dp *intel_dp)
1363{
1364 int rates[DP_MAX_SUPPORTED_RATES] = {};
1365 int len;
1366
94ca719e 1367 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1368 if (WARN_ON(len <= 0))
1369 return 162000;
1370
1371 return rates[rate_to_index(0, rates) - 1];
1372}
1373
ed4e9c1d
VS		 1374int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1375{
94ca719e 1376 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1377}
1378
00c09d70 1379bool
5bfe2ac0 1380intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1381 struct intel_crtc_state *pipe_config)
a4fc5ed6 1382{
5bfe2ac0 1383 struct drm_device *dev = encoder->base.dev;
36008365 1384 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1385 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1386 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1387 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1388 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1389 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1390 int lane_count, clock;
56071a20 1391 int min_lane_count = 1;
eeb6324d 1392 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1393 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1394 int min_clock = 0;
a8f3ef61 1395 int max_clock;
083f9560 1396 int bpp, mode_rate;
ff9a6750 1397 int link_avail, link_clock;
94ca719e
VS		 1398 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1399 int common_len;
a8f3ef61 1400
94ca719e 1401 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1402
1403 /* No common link rates between source and sink */
94ca719e 1404 WARN_ON(common_len <= 0);
a8f3ef61 1405
94ca719e 1406 max_clock = common_len - 1;
a4fc5ed6 1407
bc7d38a4 1408 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1409 pipe_config->has_pch_encoder = true;
1410
03afc4a2 1411 pipe_config->has_dp_encoder = true;
f769cd24 1412 pipe_config->has_drrs = false;
9fcb1704 1413 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1414
dd06f90e
JN		 1415 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1416 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1417 adjusted_mode);
a1b2278e
CK		 1418
1419 if (INTEL_INFO(dev)->gen >= 9) {
1420 int ret;
e435d6e5 1421 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1422 if (ret)
1423 return ret;
1424 }
1425
2dd24552
JB		 1426 if (!HAS_PCH_SPLIT(dev))
1427 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1428 intel_connector->panel.fitting_mode);
1429 else
b074cec8
JB		 1430 intel_pch_panel_fitting(intel_crtc, pipe_config,
1431 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1432 }
1433
cb1793ce 1434 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1435 return false;
1436
083f9560 1437 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1438 "max bw %d pixel clock %iKHz\n",
94ca719e 1439 max_lane_count, common_rates[max_clock],
241bfc38 1440 adjusted_mode->crtc_clock);
083f9560 1441
36008365
DV		 1442 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1443 * bpc in between. */
3e7ca985 1444 bpp = pipe_config->pipe_bpp;
56071a20 1445 if (is_edp(intel_dp)) {
22ce5628
TS		 1446
1447 /* Get bpp from vbt only for panels that dont have bpp in edid */
1448 if (intel_connector->base.display_info.bpc == 0 &&
1449 (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
56071a20
JN		 1450 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1451 dev_priv->vbt.edp_bpp);
1452 bpp = dev_priv->vbt.edp_bpp;
1453 }
1454
344c5bbc
JN		 1455 /*
1456 * Use the maximum clock and number of lanes the eDP panel
1457 * advertizes being capable of. The panels are generally
1458 * designed to support only a single clock and lane
1459 * configuration, and typically these values correspond to the
1460 * native resolution of the panel.
1461 */
1462 min_lane_count = max_lane_count;
1463 min_clock = max_clock;
7984211e 1464 }
657445fe 1465
36008365 1466 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1467 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1468 bpp);
36008365 1469
c6930992 1470 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1471 for (lane_count = min_lane_count;
1472 lane_count <= max_lane_count;
1473 lane_count <<= 1) {
1474
94ca719e 1475 link_clock = common_rates[clock];
36008365
DV		 1476 link_avail = intel_dp_max_data_rate(link_clock,
1477 lane_count);
1478
1479 if (mode_rate <= link_avail) {
1480 goto found;
1481 }
1482 }
1483 }
1484 }
c4867936 1485
36008365 1486 return false;
3685a8f3 1487
36008365 1488found:
55bc60db
VS		 1489 if (intel_dp->color_range_auto) {
1490 /*
1491 * See:
1492 * CEA-861-E - 5.1 Default Encoding Parameters
1493 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1494 */
0f2a2a75
VS		 1495 pipe_config->limited_color_range =
1496 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1497 } else {
1498 pipe_config->limited_color_range =
1499 intel_dp->limited_color_range;
55bc60db
VS		 1500 }
1501
90a6b7b0 1502 pipe_config->lane_count = lane_count;
a8f3ef61 1503
94ca719e 1504 if (intel_dp->num_sink_rates) {
bc27b7d3 1505 intel_dp->link_bw = 0;
a8f3ef61 1506 intel_dp->rate_select =
94ca719e 1507 intel_dp_rate_select(intel_dp, common_rates[clock]);
bc27b7d3
VS		 1508 } else {
1509 intel_dp->link_bw =
94ca719e 1510 drm_dp_link_rate_to_bw_code(common_rates[clock]);
bc27b7d3 1511 intel_dp->rate_select = 0;
a8f3ef61
SJ		 1512 }
1513
657445fe 1514 pipe_config->pipe_bpp = bpp;
94ca719e 1515 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1516
36008365 1517 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
90a6b7b0 1518 intel_dp->link_bw, pipe_config->lane_count,
ff9a6750 1519 pipe_config->port_clock, bpp);
36008365
DV		 1520 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1521 mode_rate, link_avail);
a4fc5ed6 1522
03afc4a2 1523 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1524 adjusted_mode->crtc_clock,
1525 pipe_config->port_clock,
03afc4a2 1526 &pipe_config->dp_m_n);
9d1a455b 1527
439d7ac0 1528 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1529 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1530 pipe_config->has_drrs = true;
439d7ac0
PB		 1531 intel_link_compute_m_n(bpp, lane_count,
1532 intel_connector->panel.downclock_mode->clock,
1533 pipe_config->port_clock,
1534 &pipe_config->dp_m2_n2);
1535 }
1536
5416d871 1537 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
840b32b7 1538 skl_edp_set_pll_config(pipe_config);
977bb38d
S		 1539 else if (IS_BROXTON(dev))
1540 /* handled in ddi */;
5416d871 1541 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
840b32b7 1542 hsw_dp_set_ddi_pll_sel(pipe_config);
0e50338c 1543 else
840b32b7 1544 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1545
03afc4a2 1546 return true;
a4fc5ed6
KP		 1547}
1548
7c62a164 1549static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1550{
7c62a164
DV		 1551 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1552 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1553 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 u32 dpa_ctl;
1556
6e3c9717
ACO		 1557 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1558 crtc->config->port_clock);
ea9b6006
DV		 1559 dpa_ctl = I915_READ(DP_A);
1560 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1561
6e3c9717 1562 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1563 /* For a long time we've carried around a ILK-DevA w/a for the
1564 * 160MHz clock. If we're really unlucky, it's still required.
1565 */
1566 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1567 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1568 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1569 } else {
1570 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1571 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1572 }
1ce17038 1573
ea9b6006
DV		 1574 I915_WRITE(DP_A, dpa_ctl);
1575
1576 POSTING_READ(DP_A);
1577 udelay(500);
1578}
1579
8ac33ed3 1580static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1581{
b934223d 1582 struct drm_device *dev = encoder->base.dev;
417e822d 1583 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1584 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1585 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1586 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1587 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1588
417e822d 1589 /*
1a2eb460 1590 * There are four kinds of DP registers:
417e822d
KP		 1591 *
1592 * IBX PCH
1a2eb460
KP		 1593 * SNB CPU
1594 * IVB CPU
417e822d
KP		 1595 * CPT PCH
1596 *
1597 * IBX PCH and CPU are the same for almost everything,
1598 * except that the CPU DP PLL is configured in this
1599 * register
1600 *
1601 * CPT PCH is quite different, having many bits moved
1602 * to the TRANS_DP_CTL register instead. That
1603 * configuration happens (oddly) in ironlake_pch_enable
1604 */
9c9e7927 1605
417e822d
KP		 1606 /* Preserve the BIOS-computed detected bit. This is
1607 * supposed to be read-only.
1608 */
1609 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1610
417e822d 1611 /* Handle DP bits in common between all three register formats */
417e822d 1612 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1613 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1614
6e3c9717 1615 if (crtc->config->has_audio)
ea5b213a 1616 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1617
417e822d 1618 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1619
39e5fa88 1620 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1621 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1622 intel_dp->DP |= DP_SYNC_HS_HIGH;
1623 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1624 intel_dp->DP |= DP_SYNC_VS_HIGH;
1625 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1626
6aba5b6c 1627 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1628 intel_dp->DP |= DP_ENHANCED_FRAMING;
1629
7c62a164 1630 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1631 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1632 u32 trans_dp;
1633
39e5fa88 1634 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1635
1636 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1637 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1638 trans_dp |= TRANS_DP_ENH_FRAMING;
1639 else
1640 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1641 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1642 } else {
0f2a2a75
VS		 1643 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1644 crtc->config->limited_color_range)
1645 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1646
1647 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1648 intel_dp->DP |= DP_SYNC_HS_HIGH;
1649 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1650 intel_dp->DP |= DP_SYNC_VS_HIGH;
1651 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1652
6aba5b6c 1653 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1654 intel_dp->DP |= DP_ENHANCED_FRAMING;
1655
39e5fa88 1656 if (IS_CHERRYVIEW(dev))
44f37d1f 1657 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1658 else if (crtc->pipe == PIPE_B)
1659 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1660 }
a4fc5ed6
KP		 1661}
1662
ffd6749d
PZ		 1663#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1664#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1665
1a5ef5b7
PZ		 1666#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1667#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1668
ffd6749d
PZ		 1669#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1670#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1671
4be73780 1672static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1673 u32 mask,
1674 u32 value)
bd943159 1675{
30add22d 1676 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1677 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1678 u32 pp_stat_reg, pp_ctrl_reg;
1679
e39b999a
VS		 1680 lockdep_assert_held(&dev_priv->pps_mutex);
1681
bf13e81b
JN		 1682 pp_stat_reg = _pp_stat_reg(intel_dp);
1683 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1684
99ea7127 1685 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1686 mask, value,
1687 I915_READ(pp_stat_reg),
1688 I915_READ(pp_ctrl_reg));
32ce697c 1689
453c5420 1690 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1691 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1692 I915_READ(pp_stat_reg),
1693 I915_READ(pp_ctrl_reg));
32ce697c 1694 }
54c136d4
CW		 1695
1696 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1697}
32ce697c 1698
4be73780 1699static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1700{
1701 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1702 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1703}
1704
4be73780 1705static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1706{
1707 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1708 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1709}
1710
4be73780 1711static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1712{
1713 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1714
1715 /* When we disable the VDD override bit last we have to do the manual
1716 * wait. */
1717 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1718 intel_dp->panel_power_cycle_delay);
1719
4be73780 1720 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1721}
1722
4be73780 1723static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1724{
1725 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1726 intel_dp->backlight_on_delay);
1727}
1728
4be73780 1729static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1730{
1731 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1732 intel_dp->backlight_off_delay);
1733}
99ea7127 1734
832dd3c1
KP		 1735/* Read the current pp_control value, unlocking the register if it
1736 * is locked
1737 */
1738
453c5420 1739static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1740{
453c5420
JB		 1741 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 u32 control;
832dd3c1 1744
e39b999a
VS		 1745 lockdep_assert_held(&dev_priv->pps_mutex);
1746
bf13e81b 1747 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1748 if (!IS_BROXTON(dev)) {
1749 control &= ~PANEL_UNLOCK_MASK;
1750 control |= PANEL_UNLOCK_REGS;
1751 }
832dd3c1 1752 return control;
bd943159
KP		 1753}
1754
951468f3
VS		 1755/*
1756 * Must be paired with edp_panel_vdd_off().
1757 * Must hold pps_mutex around the whole on/off sequence.
1758 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1759 */
1e0560e0 1760static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1761{
30add22d 1762 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1763 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1764 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1765 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1766 enum intel_display_power_domain power_domain;
5d613501 1767 u32 pp;
453c5420 1768 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1769 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1770
e39b999a
VS		 1771 lockdep_assert_held(&dev_priv->pps_mutex);
1772
97af61f5 1773 if (!is_edp(intel_dp))
adddaaf4 1774 return false;
bd943159 1775
2c623c11 1776 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1777 intel_dp->want_panel_vdd = true;
99ea7127 1778
4be73780 1779 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1780 return need_to_disable;
b0665d57 1781
4e6e1a54
ID		 1782 power_domain = intel_display_port_power_domain(intel_encoder);
1783 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1784
3936fcf4
VS		 1785 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1786 port_name(intel_dig_port->port));
bd943159 1787
4be73780
DV		 1788 if (!edp_have_panel_power(intel_dp))
1789 wait_panel_power_cycle(intel_dp);
99ea7127 1790
453c5420 1791 pp = ironlake_get_pp_control(intel_dp);
5d613501 1792 pp |= EDP_FORCE_VDD;
ebf33b18 1793
bf13e81b
JN		 1794 pp_stat_reg = _pp_stat_reg(intel_dp);
1795 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1796
1797 I915_WRITE(pp_ctrl_reg, pp);
1798 POSTING_READ(pp_ctrl_reg);
1799 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1800 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1801 /*
1802 * If the panel wasn't on, delay before accessing aux channel
1803 */
4be73780 1804 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1805 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1806 port_name(intel_dig_port->port));
f01eca2e 1807 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1808 }
adddaaf4
JN		 1809
1810 return need_to_disable;
1811}
1812
951468f3
VS		 1813/*
1814 * Must be paired with intel_edp_panel_vdd_off() or
1815 * intel_edp_panel_off().
1816 * Nested calls to these functions are not allowed since
1817 * we drop the lock. Caller must use some higher level
1818 * locking to prevent nested calls from other threads.
1819 */
b80d6c78 1820void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1821{
c695b6b6 1822 bool vdd;
adddaaf4 1823
c695b6b6
VS		 1824 if (!is_edp(intel_dp))
1825 return;
1826
773538e8 1827 pps_lock(intel_dp);
c695b6b6 1828 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1829 pps_unlock(intel_dp);
c695b6b6 1830
e2c719b7 1831 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1832 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1833}
1834
4be73780 1835static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1836{
30add22d 1837 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1838 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1839 struct intel_digital_port *intel_dig_port =
1840 dp_to_dig_port(intel_dp);
1841 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1842 enum intel_display_power_domain power_domain;
5d613501 1843 u32 pp;
453c5420 1844 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1845
e39b999a 1846 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1847
15e899a0 1848 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1849
15e899a0 1850 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1851 return;
b0665d57 1852
3936fcf4
VS		 1853 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1854 port_name(intel_dig_port->port));
bd943159 1855
be2c9196
VS		 1856 pp = ironlake_get_pp_control(intel_dp);
1857 pp &= ~EDP_FORCE_VDD;
453c5420 1858
be2c9196
VS		 1859 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1860 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1861
be2c9196
VS		 1862 I915_WRITE(pp_ctrl_reg, pp);
1863 POSTING_READ(pp_ctrl_reg);
90791a5c 1864
be2c9196
VS		 1865 /* Make sure sequencer is idle before allowing subsequent activity */
1866 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1867 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1868
be2c9196
VS		 1869 if ((pp & POWER_TARGET_ON) == 0)
1870 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1871
be2c9196
VS		 1872 power_domain = intel_display_port_power_domain(intel_encoder);
1873 intel_display_power_put(dev_priv, power_domain);
bd943159 1874}
5d613501 1875
4be73780 1876static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1877{
1878 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1879 struct intel_dp, panel_vdd_work);
bd943159 1880
773538e8 1881 pps_lock(intel_dp);
15e899a0
VS		 1882 if (!intel_dp->want_panel_vdd)
1883 edp_panel_vdd_off_sync(intel_dp);
773538e8 1884 pps_unlock(intel_dp);
bd943159
KP		 1885}
1886
aba86890
ID		 1887static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1888{
1889 unsigned long delay;
1890
1891 /*
1892 * Queue the timer to fire a long time from now (relative to the power
1893 * down delay) to keep the panel power up across a sequence of
1894 * operations.
1895 */
1896 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1897 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1898}
1899
951468f3
VS		 1900/*
1901 * Must be paired with edp_panel_vdd_on().
1902 * Must hold pps_mutex around the whole on/off sequence.
1903 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1904 */
4be73780 1905static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1906{
e39b999a
VS		 1907 struct drm_i915_private *dev_priv =
1908 intel_dp_to_dev(intel_dp)->dev_private;
1909
1910 lockdep_assert_held(&dev_priv->pps_mutex);
1911
97af61f5
KP		 1912 if (!is_edp(intel_dp))
1913 return;
5d613501 1914
e2c719b7 1915 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1916 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1917
bd943159
KP		 1918 intel_dp->want_panel_vdd = false;
1919
aba86890 1920 if (sync)
4be73780 1921 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1922 else
1923 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1924}
1925
9f0fb5be 1926static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1927{
30add22d 1928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1929 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1930 u32 pp;
453c5420 1931 u32 pp_ctrl_reg;
9934c132 1932
9f0fb5be
VS		 1933 lockdep_assert_held(&dev_priv->pps_mutex);
1934
97af61f5 1935 if (!is_edp(intel_dp))
bd943159 1936 return;
99ea7127 1937
3936fcf4
VS		 1938 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1939 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1940
e7a89ace
VS		 1941 if (WARN(edp_have_panel_power(intel_dp),
1942 "eDP port %c panel power already on\n",
1943 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1944 return;
9934c132 1945
4be73780 1946 wait_panel_power_cycle(intel_dp);
37c6c9b0 1947
bf13e81b 1948 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1949 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1950 if (IS_GEN5(dev)) {
1951 /* ILK workaround: disable reset around power sequence */
1952 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1953 I915_WRITE(pp_ctrl_reg, pp);
1954 POSTING_READ(pp_ctrl_reg);
05ce1a49 1955 }
37c6c9b0 1956
1c0ae80a 1957 pp |= POWER_TARGET_ON;
99ea7127
KP		 1958 if (!IS_GEN5(dev))
1959 pp |= PANEL_POWER_RESET;
1960
453c5420
JB		 1961 I915_WRITE(pp_ctrl_reg, pp);
1962 POSTING_READ(pp_ctrl_reg);
9934c132 1963
4be73780 1964 wait_panel_on(intel_dp);
dce56b3c 1965 intel_dp->last_power_on = jiffies;
9934c132 1966
05ce1a49
KP		 1967 if (IS_GEN5(dev)) {
1968 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1969 I915_WRITE(pp_ctrl_reg, pp);
1970 POSTING_READ(pp_ctrl_reg);
05ce1a49 1971 }
9f0fb5be 1972}
e39b999a 1973
9f0fb5be
VS		 1974void intel_edp_panel_on(struct intel_dp *intel_dp)
1975{
1976 if (!is_edp(intel_dp))
1977 return;
1978
1979 pps_lock(intel_dp);
1980 edp_panel_on(intel_dp);
773538e8 1981 pps_unlock(intel_dp);
9934c132
JB		 1982}
1983
9f0fb5be
VS		 1984
1985static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1986{
4e6e1a54
ID		 1987 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1988 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1989 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1990 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1991 enum intel_display_power_domain power_domain;
99ea7127 1992 u32 pp;
453c5420 1993 u32 pp_ctrl_reg;
9934c132 1994
9f0fb5be
VS		 1995 lockdep_assert_held(&dev_priv->pps_mutex);
1996
97af61f5
KP		 1997 if (!is_edp(intel_dp))
1998 return;
37c6c9b0 1999
3936fcf4
VS		 2000 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2001 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2002
3936fcf4
VS		 2003 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2004 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2005
453c5420 2006 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2007 /* We need to switch off panel power _and_ force vdd, for otherwise some
2008 * panels get very unhappy and cease to work. */
b3064154
PJ		 2009 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2010 EDP_BLC_ENABLE);
453c5420 2011
bf13e81b 2012 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2013
849e39f5
PZ		 2014 intel_dp->want_panel_vdd = false;
2015
453c5420
JB		 2016 I915_WRITE(pp_ctrl_reg, pp);
2017 POSTING_READ(pp_ctrl_reg);
9934c132 2018
dce56b3c 2019 intel_dp->last_power_cycle = jiffies;
4be73780 2020 wait_panel_off(intel_dp);
849e39f5
PZ		 2021
2022 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 2023 power_domain = intel_display_port_power_domain(intel_encoder);
2024 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2025}
e39b999a 2026
9f0fb5be
VS		 2027void intel_edp_panel_off(struct intel_dp *intel_dp)
2028{
2029 if (!is_edp(intel_dp))
2030 return;
e39b999a 2031
9f0fb5be
VS		 2032 pps_lock(intel_dp);
2033 edp_panel_off(intel_dp);
773538e8 2034 pps_unlock(intel_dp);
9934c132
JB		 2035}
2036
1250d107
JN		 2037/* Enable backlight in the panel power control. */
2038static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2039{
da63a9f2
PZ		 2040 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2041 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2042 struct drm_i915_private *dev_priv = dev->dev_private;
2043 u32 pp;
453c5420 2044 u32 pp_ctrl_reg;
32f9d658 2045
01cb9ea6
JB		 2046 /*
2047 * If we enable the backlight right away following a panel power
2048 * on, we may see slight flicker as the panel syncs with the eDP
2049 * link. So delay a bit to make sure the image is solid before
2050 * allowing it to appear.
2051 */
4be73780 2052 wait_backlight_on(intel_dp);
e39b999a 2053
773538e8 2054 pps_lock(intel_dp);
e39b999a 2055
453c5420 2056 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2057 pp |= EDP_BLC_ENABLE;
453c5420 2058
bf13e81b 2059 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2060
2061 I915_WRITE(pp_ctrl_reg, pp);
2062 POSTING_READ(pp_ctrl_reg);
e39b999a 2063
773538e8 2064 pps_unlock(intel_dp);
32f9d658
ZW		 2065}
2066
1250d107
JN		 2067/* Enable backlight PWM and backlight PP control. */
2068void intel_edp_backlight_on(struct intel_dp *intel_dp)
2069{
2070 if (!is_edp(intel_dp))
2071 return;
2072
2073 DRM_DEBUG_KMS("\n");
2074
2075 intel_panel_enable_backlight(intel_dp->attached_connector);
2076 _intel_edp_backlight_on(intel_dp);
2077}
2078
2079/* Disable backlight in the panel power control. */
2080static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2081{
30add22d 2082 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 u32 pp;
453c5420 2085 u32 pp_ctrl_reg;
32f9d658 2086
f01eca2e
KP		 2087 if (!is_edp(intel_dp))
2088 return;
2089
773538e8 2090 pps_lock(intel_dp);
e39b999a 2091
453c5420 2092 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2093 pp &= ~EDP_BLC_ENABLE;
453c5420 2094
bf13e81b 2095 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2096
2097 I915_WRITE(pp_ctrl_reg, pp);
2098 POSTING_READ(pp_ctrl_reg);
f7d2323c 2099
773538e8 2100 pps_unlock(intel_dp);
e39b999a
VS		 2101
2102 intel_dp->last_backlight_off = jiffies;
f7d2323c 2103 edp_wait_backlight_off(intel_dp);
1250d107 2104}
f7d2323c 2105
1250d107
JN		 2106/* Disable backlight PP control and backlight PWM. */
2107void intel_edp_backlight_off(struct intel_dp *intel_dp)
2108{
2109 if (!is_edp(intel_dp))
2110 return;
2111
2112 DRM_DEBUG_KMS("\n");
f7d2323c 2113
1250d107 2114 _intel_edp_backlight_off(intel_dp);
f7d2323c 2115 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2116}
a4fc5ed6 2117
73580fb7
JN		 2118/*
2119 * Hook for controlling the panel power control backlight through the bl_power
2120 * sysfs attribute. Take care to handle multiple calls.
2121 */
2122static void intel_edp_backlight_power(struct intel_connector *connector,
2123 bool enable)
2124{
2125 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2126 bool is_enabled;
2127
773538e8 2128 pps_lock(intel_dp);
e39b999a 2129 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2130 pps_unlock(intel_dp);
73580fb7
JN		 2131
2132 if (is_enabled == enable)
2133 return;
2134
23ba9373
JN		 2135 DRM_DEBUG_KMS("panel power control backlight %s\n",
2136 enable ? "enable" : "disable");
73580fb7
JN		 2137
2138 if (enable)
2139 _intel_edp_backlight_on(intel_dp);
2140 else
2141 _intel_edp_backlight_off(intel_dp);
2142}
2143
2bd2ad64 2144static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2145{
da63a9f2
PZ		 2146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2147 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2148 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 u32 dpa_ctl;
2151
2bd2ad64
DV		 2152 assert_pipe_disabled(dev_priv,
2153 to_intel_crtc(crtc)->pipe);
2154
d240f20f
JB		 2155 DRM_DEBUG_KMS("\n");
2156 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2157 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2158 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2159
2160 /* We don't adjust intel_dp->DP while tearing down the link, to
2161 * facilitate link retraining (e.g. after hotplug). Hence clear all
2162 * enable bits here to ensure that we don't enable too much. */
2163 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2164 intel_dp->DP |= DP_PLL_ENABLE;
2165 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2166 POSTING_READ(DP_A);
2167 udelay(200);
d240f20f
JB		 2168}
2169
2bd2ad64 2170static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2171{
da63a9f2
PZ		 2172 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2173 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2174 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2175 struct drm_i915_private *dev_priv = dev->dev_private;
2176 u32 dpa_ctl;
2177
2bd2ad64
DV		 2178 assert_pipe_disabled(dev_priv,
2179 to_intel_crtc(crtc)->pipe);
2180
d240f20f 2181 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2182 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2183 "dp pll off, should be on\n");
2184 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2185
2186 /* We can't rely on the value tracked for the DP register in
2187 * intel_dp->DP because link_down must not change that (otherwise link
2188 * re-training will fail. */
298b0b39 2189 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2190 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2191 POSTING_READ(DP_A);
d240f20f
JB		 2192 udelay(200);
2193}
2194
c7ad3810 2195/* If the sink supports it, try to set the power state appropriately */
c19b0669 2196void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2197{
2198 int ret, i;
2199
2200 /* Should have a valid DPCD by this point */
2201 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2202 return;
2203
2204 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2205 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2206 DP_SET_POWER_D3);
c7ad3810
JB		 2207 } else {
2208 /*
2209 * When turning on, we need to retry for 1ms to give the sink
2210 * time to wake up.
2211 */
2212 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2213 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2214 DP_SET_POWER_D0);
c7ad3810
JB		 2215 if (ret == 1)
2216 break;
2217 msleep(1);
2218 }
2219 }
f9cac721
JN		 2220
2221 if (ret != 1)
2222 DRM_DEBUG_KMS("failed to %s sink power state\n",
2223 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2224}
2225
19d8fe15
DV		 2226static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2227 enum pipe *pipe)
d240f20f 2228{
19d8fe15 2229 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2230 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2231 struct drm_device *dev = encoder->base.dev;
2232 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2233 enum intel_display_power_domain power_domain;
2234 u32 tmp;
2235
2236 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2237 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2238 return false;
2239
2240 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2241
2242 if (!(tmp & DP_PORT_EN))
2243 return false;
2244
39e5fa88 2245 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2246 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2247 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2248 enum pipe p;
19d8fe15 2249
adc289d7
VS		 2250 for_each_pipe(dev_priv, p) {
2251 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2252 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2253 *pipe = p;
19d8fe15
DV		 2254 return true;
2255 }
2256 }
19d8fe15 2257
4a0833ec
DV		 2258 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2259 intel_dp->output_reg);
39e5fa88
VS		 2260 } else if (IS_CHERRYVIEW(dev)) {
2261 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2262 } else {
2263 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2264 }
d240f20f 2265
19d8fe15
DV		 2266 return true;
2267}
d240f20f 2268
045ac3b5 2269static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2270 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2271{
2272 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2273 u32 tmp, flags = 0;
63000ef6
XZ		 2274 struct drm_device *dev = encoder->base.dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 enum port port = dp_to_dig_port(intel_dp)->port;
2277 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2278 int dotclock;
045ac3b5 2279
9ed109a7 2280 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2281
2282 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2283
39e5fa88 2284 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2285 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2286
2287 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2288 flags |= DRM_MODE_FLAG_PHSYNC;
2289 else
2290 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2291
b81e34c2 2292 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2293 flags |= DRM_MODE_FLAG_PVSYNC;
2294 else
2295 flags |= DRM_MODE_FLAG_NVSYNC;
2296 } else {
39e5fa88 2297 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2298 flags |= DRM_MODE_FLAG_PHSYNC;
2299 else
2300 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2301
39e5fa88 2302 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2303 flags |= DRM_MODE_FLAG_PVSYNC;
2304 else
2305 flags |= DRM_MODE_FLAG_NVSYNC;
2306 }
045ac3b5 2307
2d112de7 2308 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2309
8c875fca
VS		 2310 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2311 tmp & DP_COLOR_RANGE_16_235)
2312 pipe_config->limited_color_range = true;
2313
eb14cb74
VS		 2314 pipe_config->has_dp_encoder = true;
2315
90a6b7b0
VS		 2316 pipe_config->lane_count =
2317 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2318
eb14cb74
VS		 2319 intel_dp_get_m_n(crtc, pipe_config);
2320
18442d08 2321 if (port == PORT_A) {
f1f644dc
JB		 2322 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2323 pipe_config->port_clock = 162000;
2324 else
2325 pipe_config->port_clock = 270000;
2326 }
18442d08
VS		 2327
2328 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2329 &pipe_config->dp_m_n);
2330
2331 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2332 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2333
2d112de7 2334 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2335
c6cd2ee2
JN		 2336 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2337 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2338 /*
2339 * This is a big fat ugly hack.
2340 *
2341 * Some machines in UEFI boot mode provide us a VBT that has 18
2342 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2343 * unknown we fail to light up. Yet the same BIOS boots up with
2344 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2345 * max, not what it tells us to use.
2346 *
2347 * Note: This will still be broken if the eDP panel is not lit
2348 * up by the BIOS, and thus we can't get the mode at module
2349 * load.
2350 */
2351 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2352 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2353 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2354 }
045ac3b5
JB		 2355}
2356
e8cb4558 2357static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2358{
e8cb4558 2359 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2360 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2361 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2362
6e3c9717 2363 if (crtc->config->has_audio)
495a5bb8 2364 intel_audio_codec_disable(encoder);
6cb49835 2365
b32c6f48
RV		 2366 if (HAS_PSR(dev) && !HAS_DDI(dev))
2367 intel_psr_disable(intel_dp);
2368
6cb49835
DV		 2369 /* Make sure the panel is off before trying to change the mode. But also
2370 * ensure that we have vdd while we switch off the panel. */
24f3e092 2371 intel_edp_panel_vdd_on(intel_dp);
4be73780 2372 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2373 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2374 intel_edp_panel_off(intel_dp);
3739850b 2375
08aff3fe
VS		 2376 /* disable the port before the pipe on g4x */
2377 if (INTEL_INFO(dev)->gen < 5)
3739850b 2378 intel_dp_link_down(intel_dp);
d240f20f
JB		 2379}
2380
08aff3fe 2381static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2382{
2bd2ad64 2383 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2384 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2385
49277c31 2386 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2387 if (port == PORT_A)
2388 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2389}
2390
2391static void vlv_post_disable_dp(struct intel_encoder *encoder)
2392{
2393 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2394
2395 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2396}
2397
580d3811
VS		 2398static void chv_post_disable_dp(struct intel_encoder *encoder)
2399{
2400 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2401 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2402 struct drm_device *dev = encoder->base.dev;
2403 struct drm_i915_private *dev_priv = dev->dev_private;
2404 struct intel_crtc *intel_crtc =
2405 to_intel_crtc(encoder->base.crtc);
2406 enum dpio_channel ch = vlv_dport_to_channel(dport);
2407 enum pipe pipe = intel_crtc->pipe;
2408 u32 val;
2409
2410 intel_dp_link_down(intel_dp);
2411
a580516d 2412 mutex_lock(&dev_priv->sb_lock);
580d3811
VS		 2413
2414 /* Propagate soft reset to data lane reset */
97fd4d5c 2415 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2416 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2417 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2418
97fd4d5c
VS		 2419 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2420 val |= CHV_PCS_REQ_SOFTRESET_EN;
2421 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2422
2423 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2424 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2425 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2426
2427 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2428 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2429 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811 2430
a580516d 2431 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2432}
2433
7b13b58a
VS		 2434static void
2435_intel_dp_set_link_train(struct intel_dp *intel_dp,
2436 uint32_t *DP,
2437 uint8_t dp_train_pat)
2438{
2439 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2440 struct drm_device *dev = intel_dig_port->base.base.dev;
2441 struct drm_i915_private *dev_priv = dev->dev_private;
2442 enum port port = intel_dig_port->port;
2443
2444 if (HAS_DDI(dev)) {
2445 uint32_t temp = I915_READ(DP_TP_CTL(port));
2446
2447 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2448 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2449 else
2450 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2451
2452 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2453 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2454 case DP_TRAINING_PATTERN_DISABLE:
2455 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2456
2457 break;
2458 case DP_TRAINING_PATTERN_1:
2459 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2460 break;
2461 case DP_TRAINING_PATTERN_2:
2462 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2463 break;
2464 case DP_TRAINING_PATTERN_3:
2465 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2466 break;
2467 }
2468 I915_WRITE(DP_TP_CTL(port), temp);
2469
39e5fa88
VS		 2470 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2471 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2472 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2473
2474 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2475 case DP_TRAINING_PATTERN_DISABLE:
2476 *DP |= DP_LINK_TRAIN_OFF_CPT;
2477 break;
2478 case DP_TRAINING_PATTERN_1:
2479 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2480 break;
2481 case DP_TRAINING_PATTERN_2:
2482 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2483 break;
2484 case DP_TRAINING_PATTERN_3:
2485 DRM_ERROR("DP training pattern 3 not supported\n");
2486 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2487 break;
2488 }
2489
2490 } else {
2491 if (IS_CHERRYVIEW(dev))
2492 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2493 else
2494 *DP &= ~DP_LINK_TRAIN_MASK;
2495
2496 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2497 case DP_TRAINING_PATTERN_DISABLE:
2498 *DP |= DP_LINK_TRAIN_OFF;
2499 break;
2500 case DP_TRAINING_PATTERN_1:
2501 *DP |= DP_LINK_TRAIN_PAT_1;
2502 break;
2503 case DP_TRAINING_PATTERN_2:
2504 *DP |= DP_LINK_TRAIN_PAT_2;
2505 break;
2506 case DP_TRAINING_PATTERN_3:
2507 if (IS_CHERRYVIEW(dev)) {
2508 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2509 } else {
2510 DRM_ERROR("DP training pattern 3 not supported\n");
2511 *DP |= DP_LINK_TRAIN_PAT_2;
2512 }
2513 break;
2514 }
2515 }
2516}
2517
2518static void intel_dp_enable_port(struct intel_dp *intel_dp)
2519{
2520 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2521 struct drm_i915_private *dev_priv = dev->dev_private;
2522
7b13b58a
VS		 2523 /* enable with pattern 1 (as per spec) */
2524 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2525 DP_TRAINING_PATTERN_1);
2526
2527 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2528 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2529
2530 /*
2531 * Magic for VLV/CHV. We _must_ first set up the register
2532 * without actually enabling the port, and then do another
2533 * write to enable the port. Otherwise link training will
2534 * fail when the power sequencer is freshly used for this port.
2535 */
2536 intel_dp->DP |= DP_PORT_EN;
2537
2538 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2539 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2540}
2541
e8cb4558 2542static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2543{
e8cb4558
DV		 2544 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2545 struct drm_device *dev = encoder->base.dev;
2546 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2547 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2548 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
9b6de0a1 2549 unsigned int lane_mask = 0x0;
5d613501 2550
0c33d8d7
DV		 2551 if (WARN_ON(dp_reg & DP_PORT_EN))
2552 return;
5d613501 2553
093e3f13
VS		 2554 pps_lock(intel_dp);
2555
2556 if (IS_VALLEYVIEW(dev))
2557 vlv_init_panel_power_sequencer(intel_dp);
2558
7b13b58a 2559 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2560
2561 edp_panel_vdd_on(intel_dp);
2562 edp_panel_on(intel_dp);
2563 edp_panel_vdd_off(intel_dp, true);
2564
2565 pps_unlock(intel_dp);
2566
61234fa5 2567 if (IS_VALLEYVIEW(dev))
9b6de0a1
VS		 2568 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2569 lane_mask);
61234fa5 2570
f01eca2e 2571 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2572 intel_dp_start_link_train(intel_dp);
33a34e4e 2573 intel_dp_complete_link_train(intel_dp);
3ab9c637 2574 intel_dp_stop_link_train(intel_dp);
c1dec79a 2575
6e3c9717 2576 if (crtc->config->has_audio) {
c1dec79a
JN		 2577 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2578 pipe_name(crtc->pipe));
2579 intel_audio_codec_enable(encoder);
2580 }
ab1f90f9 2581}
89b667f8 2582
ecff4f3b
JN		 2583static void g4x_enable_dp(struct intel_encoder *encoder)
2584{
828f5c6e
JN		 2585 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2586
ecff4f3b 2587 intel_enable_dp(encoder);
4be73780 2588 intel_edp_backlight_on(intel_dp);
ab1f90f9 2589}
89b667f8 2590
ab1f90f9
JN		 2591static void vlv_enable_dp(struct intel_encoder *encoder)
2592{
828f5c6e
JN		 2593 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2594
4be73780 2595 intel_edp_backlight_on(intel_dp);
b32c6f48 2596 intel_psr_enable(intel_dp);
d240f20f
JB		 2597}
2598
ecff4f3b 2599static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2600{
2601 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2602 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2603
8ac33ed3
DV		 2604 intel_dp_prepare(encoder);
2605
d41f1efb
DV		 2606 /* Only ilk+ has port A */
2607 if (dport->port == PORT_A) {
2608 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2609 ironlake_edp_pll_on(intel_dp);
d41f1efb 2610 }
ab1f90f9
JN		 2611}
2612
83b84597
VS		 2613static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2614{
2615 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2616 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2617 enum pipe pipe = intel_dp->pps_pipe;
2618 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2619
2620 edp_panel_vdd_off_sync(intel_dp);
2621
2622 /*
2623 * VLV seems to get confused when multiple power seqeuencers
2624 * have the same port selected (even if only one has power/vdd
2625 * enabled). The failure manifests as vlv_wait_port_ready() failing
2626 * CHV on the other hand doesn't seem to mind having the same port
2627 * selected in multiple power seqeuencers, but let's clear the
2628 * port select always when logically disconnecting a power sequencer
2629 * from a port.
2630 */
2631 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2632 pipe_name(pipe), port_name(intel_dig_port->port));
2633 I915_WRITE(pp_on_reg, 0);
2634 POSTING_READ(pp_on_reg);
2635
2636 intel_dp->pps_pipe = INVALID_PIPE;
2637}
2638
a4a5d2f8
VS		 2639static void vlv_steal_power_sequencer(struct drm_device *dev,
2640 enum pipe pipe)
2641{
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct intel_encoder *encoder;
2644
2645 lockdep_assert_held(&dev_priv->pps_mutex);
2646
ac3c12e4
VS		 2647 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2648 return;
2649
a4a5d2f8
VS		 2650 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2651 base.head) {
2652 struct intel_dp *intel_dp;
773538e8 2653 enum port port;
a4a5d2f8
VS		 2654
2655 if (encoder->type != INTEL_OUTPUT_EDP)
2656 continue;
2657
2658 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2659 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2660
2661 if (intel_dp->pps_pipe != pipe)
2662 continue;
2663
2664 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2665 pipe_name(pipe), port_name(port));
a4a5d2f8 2666
e02f9a06 2667 WARN(encoder->base.crtc,
034e43c6
VS		 2668 "stealing pipe %c power sequencer from active eDP port %c\n",
2669 pipe_name(pipe), port_name(port));
a4a5d2f8 2670
a4a5d2f8 2671 /* make sure vdd is off before we steal it */
83b84597 2672 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2673 }
2674}
2675
2676static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2677{
2678 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2679 struct intel_encoder *encoder = &intel_dig_port->base;
2680 struct drm_device *dev = encoder->base.dev;
2681 struct drm_i915_private *dev_priv = dev->dev_private;
2682 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2683
2684 lockdep_assert_held(&dev_priv->pps_mutex);
2685
093e3f13
VS		 2686 if (!is_edp(intel_dp))
2687 return;
2688
a4a5d2f8
VS		 2689 if (intel_dp->pps_pipe == crtc->pipe)
2690 return;
2691
2692 /*
2693 * If another power sequencer was being used on this
2694 * port previously make sure to turn off vdd there while
2695 * we still have control of it.
2696 */
2697 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2698 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2699
2700 /*
2701 * We may be stealing the power
2702 * sequencer from another port.
2703 */
2704 vlv_steal_power_sequencer(dev, crtc->pipe);
2705
2706 /* now it's all ours */
2707 intel_dp->pps_pipe = crtc->pipe;
2708
2709 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2710 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2711
2712 /* init power sequencer on this pipe and port */
36b5f425
VS		 2713 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2714 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2715}
2716
ab1f90f9 2717static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2718{
2bd2ad64 2719 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2720 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2721 struct drm_device *dev = encoder->base.dev;
89b667f8 2722 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2723 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2724 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2725 int pipe = intel_crtc->pipe;
2726 u32 val;
a4fc5ed6 2727
a580516d 2728 mutex_lock(&dev_priv->sb_lock);
89b667f8 2729
ab3c759a 2730 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2731 val = 0;
2732 if (pipe)
2733 val |= (1<<21);
2734 else
2735 val &= ~(1<<21);
2736 val |= 0x001000c4;
ab3c759a
CML		 2737 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2738 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2739 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2740
a580516d 2741 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2742
2743 intel_enable_dp(encoder);
89b667f8
JB		 2744}
2745
ecff4f3b 2746static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2747{
2748 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2749 struct drm_device *dev = encoder->base.dev;
2750 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2751 struct intel_crtc *intel_crtc =
2752 to_intel_crtc(encoder->base.crtc);
e4607fcf 2753 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2754 int pipe = intel_crtc->pipe;
89b667f8 2755
8ac33ed3
DV		 2756 intel_dp_prepare(encoder);
2757
89b667f8 2758 /* Program Tx lane resets to default */
a580516d 2759 mutex_lock(&dev_priv->sb_lock);
ab3c759a 2760 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2761 DPIO_PCS_TX_LANE2_RESET |
2762 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2763 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2764 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2765 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2766 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2767 DPIO_PCS_CLK_SOFT_RESET);
2768
2769 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2770 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2771 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2772 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
a580516d 2773 mutex_unlock(&dev_priv->sb_lock);
a4fc5ed6
KP		 2774}
2775
e4a1d846
CML		 2776static void chv_pre_enable_dp(struct intel_encoder *encoder)
2777{
2778 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2779 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2780 struct drm_device *dev = encoder->base.dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2782 struct intel_crtc *intel_crtc =
2783 to_intel_crtc(encoder->base.crtc);
2784 enum dpio_channel ch = vlv_dport_to_channel(dport);
2785 int pipe = intel_crtc->pipe;
2e523e98 2786 int data, i, stagger;
949c1d43 2787 u32 val;
e4a1d846 2788
a580516d 2789 mutex_lock(&dev_priv->sb_lock);
949c1d43 2790
570e2a74
VS		 2791 /* allow hardware to manage TX FIFO reset source */
2792 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2793 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2794 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2795
2796 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2797 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2798 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2799
949c1d43 2800 /* Deassert soft data lane reset*/
97fd4d5c 2801 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2802 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2803 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2804
2805 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2806 val |= CHV_PCS_REQ_SOFTRESET_EN;
2807 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2808
2809 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2810 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2811 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2812
97fd4d5c 2813 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2814 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2815 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2816
2817 /* Program Tx lane latency optimal setting*/
e4a1d846 2818 for (i = 0; i < 4; i++) {
e4a1d846
CML		 2819 /* Set the upar bit */
2820 data = (i == 1) ? 0x0 : 0x1;
2821 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2822 data << DPIO_UPAR_SHIFT);
2823 }
2824
2825 /* Data lane stagger programming */
2e523e98
VS		 2826 if (intel_crtc->config->port_clock > 270000)
2827 stagger = 0x18;
2828 else if (intel_crtc->config->port_clock > 135000)
2829 stagger = 0xd;
2830 else if (intel_crtc->config->port_clock > 67500)
2831 stagger = 0x7;
2832 else if (intel_crtc->config->port_clock > 33750)
2833 stagger = 0x4;
2834 else
2835 stagger = 0x2;
2836
2837 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2838 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2839 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2840
2841 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2842 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2843 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2844
2845 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2846 DPIO_LANESTAGGER_STRAP(stagger) |
2847 DPIO_LANESTAGGER_STRAP_OVRD |
2848 DPIO_TX1_STAGGER_MASK(0x1f) |
2849 DPIO_TX1_STAGGER_MULT(6) |
2850 DPIO_TX2_STAGGER_MULT(0));
2851
2852 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2853 DPIO_LANESTAGGER_STRAP(stagger) |
2854 DPIO_LANESTAGGER_STRAP_OVRD |
2855 DPIO_TX1_STAGGER_MASK(0x1f) |
2856 DPIO_TX1_STAGGER_MULT(7) |
2857 DPIO_TX2_STAGGER_MULT(5));
e4a1d846 2858
a580516d 2859 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 2860
e4a1d846 2861 intel_enable_dp(encoder);
e4a1d846
CML		 2862}
2863
9197c88b
VS		 2864static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2865{
2866 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2867 struct drm_device *dev = encoder->base.dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 struct intel_crtc *intel_crtc =
2870 to_intel_crtc(encoder->base.crtc);
2871 enum dpio_channel ch = vlv_dport_to_channel(dport);
2872 enum pipe pipe = intel_crtc->pipe;
2873 u32 val;
2874
625695f8
VS		 2875 intel_dp_prepare(encoder);
2876
a580516d 2877 mutex_lock(&dev_priv->sb_lock);
9197c88b 2878
b9e5ac3c
VS		 2879 /* program left/right clock distribution */
2880 if (pipe != PIPE_B) {
2881 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2882 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2883 if (ch == DPIO_CH0)
2884 val |= CHV_BUFLEFTENA1_FORCE;
2885 if (ch == DPIO_CH1)
2886 val |= CHV_BUFRIGHTENA1_FORCE;
2887 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2888 } else {
2889 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2890 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2891 if (ch == DPIO_CH0)
2892 val |= CHV_BUFLEFTENA2_FORCE;
2893 if (ch == DPIO_CH1)
2894 val |= CHV_BUFRIGHTENA2_FORCE;
2895 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2896 }
2897
9197c88b
VS		 2898 /* program clock channel usage */
2899 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2900 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2901 if (pipe != PIPE_B)
2902 val &= ~CHV_PCS_USEDCLKCHANNEL;
2903 else
2904 val |= CHV_PCS_USEDCLKCHANNEL;
2905 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2906
2907 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2908 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2909 if (pipe != PIPE_B)
2910 val &= ~CHV_PCS_USEDCLKCHANNEL;
2911 else
2912 val |= CHV_PCS_USEDCLKCHANNEL;
2913 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2914
2915 /*
2916 * This a a bit weird since generally CL
2917 * matches the pipe, but here we need to
2918 * pick the CL based on the port.
2919 */
2920 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2921 if (pipe != PIPE_B)
2922 val &= ~CHV_CMN_USEDCLKCHANNEL;
2923 else
2924 val |= CHV_CMN_USEDCLKCHANNEL;
2925 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2926
a580516d 2927 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 2928}
2929
a4fc5ed6 2930/*
df0c237d
JB		 2931 * Native read with retry for link status and receiver capability reads for
2932 * cases where the sink may still be asleep.
9d1a1031
JN		 2933 *
2934 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2935 * supposed to retry 3 times per the spec.
a4fc5ed6 2936 */
9d1a1031
JN		 2937static ssize_t
2938intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2939 void *buffer, size_t size)
a4fc5ed6 2940{
9d1a1031
JN		 2941 ssize_t ret;
2942 int i;
61da5fab 2943
f6a19066
VS		 2944 /*
2945 * Sometime we just get the same incorrect byte repeated
2946 * over the entire buffer. Doing just one throw away read
2947 * initially seems to "solve" it.
2948 */
2949 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2950
61da5fab 2951 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2952 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2953 if (ret == size)
2954 return ret;
61da5fab
JB		 2955 msleep(1);
2956 }
a4fc5ed6 2957
9d1a1031 2958 return ret;
a4fc5ed6
KP		 2959}
2960
2961/*
2962 * Fetch AUX CH registers 0x202 - 0x207 which contain
2963 * link status information
2964 */
2965static bool
93f62dad 2966intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2967{
9d1a1031
JN		 2968 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2969 DP_LANE0_1_STATUS,
2970 link_status,
2971 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2972}
2973
1100244e 2974/* These are source-specific values. */
a4fc5ed6 2975static uint8_t
1a2eb460 2976intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2977{
30add22d 2978 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2979 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2980 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2981
9314726b
VK		 2982 if (IS_BROXTON(dev))
2983 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2984 else if (INTEL_INFO(dev)->gen >= 9) {
9e458034 2985 if (dev_priv->edp_low_vswing && port == PORT_A)
7ad14a29 2986 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2987 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2988 } else if (IS_VALLEYVIEW(dev))
bd60018a 2989 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2990 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2991 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2992 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2993 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2994 else
bd60018a 2995 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2996}
2997
2998static uint8_t
2999intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3000{
30add22d 3001 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3002 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3003
5a9d1f1a
DL		 3004 if (INTEL_INFO(dev)->gen >= 9) {
3005 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3009 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3011 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3012 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3013 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3014 default:
3015 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3016 }
3017 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3018 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3019 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3020 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3022 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3023 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3024 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3025 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3026 default:
bd60018a 3027 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3028 }
e2fa6fba
P		 3029 } else if (IS_VALLEYVIEW(dev)) {
3030 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3031 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3032 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3033 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3034 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3035 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3036 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3038 default:
bd60018a 3039 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3040 }
bc7d38a4 3041 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3042 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3043 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3044 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3047 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3048 default:
bd60018a 3049 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3050 }
3051 } else {
3052 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3054 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3056 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3058 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3060 default:
bd60018a 3061 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3062 }
a4fc5ed6
KP		 3063 }
3064}
3065
5829975c 3066static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3067{
3068 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3071 struct intel_crtc *intel_crtc =
3072 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3073 unsigned long demph_reg_value, preemph_reg_value,
3074 uniqtranscale_reg_value;
3075 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3076 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3077 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3078
3079 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3080 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3081 preemph_reg_value = 0x0004000;
3082 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3083 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3084 demph_reg_value = 0x2B405555;
3085 uniqtranscale_reg_value = 0x552AB83A;
3086 break;
bd60018a 3087 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3088 demph_reg_value = 0x2B404040;
3089 uniqtranscale_reg_value = 0x5548B83A;
3090 break;
bd60018a 3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3092 demph_reg_value = 0x2B245555;
3093 uniqtranscale_reg_value = 0x5560B83A;
3094 break;
bd60018a 3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3096 demph_reg_value = 0x2B405555;
3097 uniqtranscale_reg_value = 0x5598DA3A;
3098 break;
3099 default:
3100 return 0;
3101 }
3102 break;
bd60018a 3103 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3104 preemph_reg_value = 0x0002000;
3105 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3106 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3107 demph_reg_value = 0x2B404040;
3108 uniqtranscale_reg_value = 0x5552B83A;
3109 break;
bd60018a 3110 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3111 demph_reg_value = 0x2B404848;
3112 uniqtranscale_reg_value = 0x5580B83A;
3113 break;
bd60018a 3114 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3115 demph_reg_value = 0x2B404040;
3116 uniqtranscale_reg_value = 0x55ADDA3A;
3117 break;
3118 default:
3119 return 0;
3120 }
3121 break;
bd60018a 3122 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3123 preemph_reg_value = 0x0000000;
3124 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3126 demph_reg_value = 0x2B305555;
3127 uniqtranscale_reg_value = 0x5570B83A;
3128 break;
bd60018a 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3130 demph_reg_value = 0x2B2B4040;
3131 uniqtranscale_reg_value = 0x55ADDA3A;
3132 break;
3133 default:
3134 return 0;
3135 }
3136 break;
bd60018a 3137 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3138 preemph_reg_value = 0x0006000;
3139 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3140 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3141 demph_reg_value = 0x1B405555;
3142 uniqtranscale_reg_value = 0x55ADDA3A;
3143 break;
3144 default:
3145 return 0;
3146 }
3147 break;
3148 default:
3149 return 0;
3150 }
3151
a580516d 3152 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 3153 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3154 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3155 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3156 uniqtranscale_reg_value);
ab3c759a
CML		 3157 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3158 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3159 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3160 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
a580516d 3161 mutex_unlock(&dev_priv->sb_lock);
e2fa6fba
P		 3162
3163 return 0;
3164}
3165
5829975c 3166static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3167{
3168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3171 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3172 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3173 uint8_t train_set = intel_dp->train_set[0];
3174 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3175 enum pipe pipe = intel_crtc->pipe;
3176 int i;
e4a1d846
CML		 3177
3178 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3179 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3180 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3182 deemph_reg_value = 128;
3183 margin_reg_value = 52;
3184 break;
bd60018a 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3186 deemph_reg_value = 128;
3187 margin_reg_value = 77;
3188 break;
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3190 deemph_reg_value = 128;
3191 margin_reg_value = 102;
3192 break;
bd60018a 3193 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3194 deemph_reg_value = 128;
3195 margin_reg_value = 154;
3196 /* FIXME extra to set for 1200 */
3197 break;
3198 default:
3199 return 0;
3200 }
3201 break;
bd60018a 3202 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3203 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3205 deemph_reg_value = 85;
3206 margin_reg_value = 78;
3207 break;
bd60018a 3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3209 deemph_reg_value = 85;
3210 margin_reg_value = 116;
3211 break;
bd60018a 3212 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3213 deemph_reg_value = 85;
3214 margin_reg_value = 154;
3215 break;
3216 default:
3217 return 0;
3218 }
3219 break;
bd60018a 3220 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3221 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3222 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3223 deemph_reg_value = 64;
3224 margin_reg_value = 104;
3225 break;
bd60018a 3226 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3227 deemph_reg_value = 64;
3228 margin_reg_value = 154;
3229 break;
3230 default:
3231 return 0;
3232 }
3233 break;
bd60018a 3234 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3235 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3237 deemph_reg_value = 43;
3238 margin_reg_value = 154;
3239 break;
3240 default:
3241 return 0;
3242 }
3243 break;
3244 default:
3245 return 0;
3246 }
3247
a580516d 3248 mutex_lock(&dev_priv->sb_lock);
e4a1d846
CML		 3249
3250 /* Clear calc init */
1966e59e
VS		 3251 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3252 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3253 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3254 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3255 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3256
3257 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3258 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3259 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3260 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3261 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3262
a02ef3c7
VS		 3263 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3264 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3265 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3266 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3267
3268 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3269 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3270 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3271 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3272
e4a1d846 3273 /* Program swing deemph */
f72df8db
VS		 3274 for (i = 0; i < 4; i++) {
3275 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3276 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3277 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3278 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3279 }
e4a1d846
CML		 3280
3281 /* Program swing margin */
f72df8db
VS		 3282 for (i = 0; i < 4; i++) {
3283 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3284 val &= ~DPIO_SWING_MARGIN000_MASK;
3285 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3286 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3287 }
e4a1d846
CML		 3288
3289 /* Disable unique transition scale */
f72df8db
VS		 3290 for (i = 0; i < 4; i++) {
3291 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3292 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3293 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3294 }
e4a1d846
CML		 3295
3296 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3297 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3298 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3299 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3300
3301 /*
3302 * The document said it needs to set bit 27 for ch0 and bit 26
3303 * for ch1. Might be a typo in the doc.
3304 * For now, for this unique transition scale selection, set bit
3305 * 27 for ch0 and ch1.
3306 */
f72df8db
VS		 3307 for (i = 0; i < 4; i++) {
3308 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3309 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3310 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3311 }
e4a1d846 3312
f72df8db
VS		 3313 for (i = 0; i < 4; i++) {
3314 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3315 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3316 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3317 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3318 }
e4a1d846
CML		 3319 }
3320
3321 /* Start swing calculation */
1966e59e
VS		 3322 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3323 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3324 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3325
3326 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3327 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3328 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3329
3330 /* LRC Bypass */
3331 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3332 val |= DPIO_LRC_BYPASS;
3333 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3334
a580516d 3335 mutex_unlock(&dev_priv->sb_lock);
e4a1d846
CML		 3336
3337 return 0;
3338}
3339
a4fc5ed6 3340static void
0301b3ac
JN		 3341intel_get_adjust_train(struct intel_dp *intel_dp,
3342 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 3343{
90a6b7b0
VS		 3344 struct intel_crtc *crtc =
3345 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
a4fc5ed6
KP		 3346 uint8_t v = 0;
3347 uint8_t p = 0;
3348 int lane;
1a2eb460
KP		 3349 uint8_t voltage_max;
3350 uint8_t preemph_max;
a4fc5ed6 3351
90a6b7b0 3352 for (lane = 0; lane < crtc->config->lane_count; lane++) {
0f037bde
DV		 3353 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3354 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3355
3356 if (this_v > v)
3357 v = this_v;
3358 if (this_p > p)
3359 p = this_p;
3360 }
3361
1a2eb460 3362 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3363 if (v >= voltage_max)
3364 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3365
1a2eb460
KP		 3366 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3367 if (p >= preemph_max)
3368 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3369
3370 for (lane = 0; lane < 4; lane++)
33a34e4e 3371 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3372}
3373
3374static uint32_t
5829975c 3375gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3376{
3cf2efb1 3377 uint32_t signal_levels = 0;
a4fc5ed6 3378
3cf2efb1 3379 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3381 default:
3382 signal_levels |= DP_VOLTAGE_0_4;
3383 break;
bd60018a 3384 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3385 signal_levels |= DP_VOLTAGE_0_6;
3386 break;
bd60018a 3387 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3388 signal_levels |= DP_VOLTAGE_0_8;
3389 break;
bd60018a 3390 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3391 signal_levels |= DP_VOLTAGE_1_2;
3392 break;
3393 }
3cf2efb1 3394 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3395 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3396 default:
3397 signal_levels |= DP_PRE_EMPHASIS_0;
3398 break;
bd60018a 3399 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3400 signal_levels |= DP_PRE_EMPHASIS_3_5;
3401 break;
bd60018a 3402 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3403 signal_levels |= DP_PRE_EMPHASIS_6;
3404 break;
bd60018a 3405 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3406 signal_levels |= DP_PRE_EMPHASIS_9_5;
3407 break;
3408 }
3409 return signal_levels;
3410}
3411
e3421a18
ZW		 3412/* Gen6's DP voltage swing and pre-emphasis control */
3413static uint32_t
5829975c 3414gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3415{
3c5a62b5
YL		 3416 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3417 DP_TRAIN_PRE_EMPHASIS_MASK);
3418 switch (signal_levels) {
bd60018a
SJ		 3419 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3420 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3421 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3422 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3423 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3424 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3425 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3426 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3427 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3428 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3429 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3430 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3431 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3432 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3433 default:
3c5a62b5
YL		 3434 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3435 "0x%x\n", signal_levels);
3436 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3437 }
3438}
3439
1a2eb460
KP		 3440/* Gen7's DP voltage swing and pre-emphasis control */
3441static uint32_t
5829975c 3442gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3443{
3444 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3445 DP_TRAIN_PRE_EMPHASIS_MASK);
3446 switch (signal_levels) {
bd60018a 3447 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3448 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3449 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3450 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3451 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3452 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3453
bd60018a 3454 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3455 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3456 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3457 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3458
bd60018a 3459 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3460 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3461 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3462 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3463
3464 default:
3465 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3466 "0x%x\n", signal_levels);
3467 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3468 }
3469}
3470
f0a3424e
PZ		 3471/* Properly updates "DP" with the correct signal levels. */
3472static void
3473intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3474{
3475 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3476 enum port port = intel_dig_port->port;
f0a3424e 3477 struct drm_device *dev = intel_dig_port->base.base.dev;
f8896f5d 3478 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3479 uint8_t train_set = intel_dp->train_set[0];
3480
f8896f5d
DW		 3481 if (HAS_DDI(dev)) {
3482 signal_levels = ddi_signal_levels(intel_dp);
3483
3484 if (IS_BROXTON(dev))
3485 signal_levels = 0;
3486 else
3487 mask = DDI_BUF_EMP_MASK;
e4a1d846 3488 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3489 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3490 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3491 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3492 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3493 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3494 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3495 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3496 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3497 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3498 } else {
5829975c 3499 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3500 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3501 }
3502
96fb9f9b
VK		 3503 if (mask)
3504 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3505
3506 DRM_DEBUG_KMS("Using vswing level %d\n",
3507 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3508 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3509 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3510 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e
PZ		 3511
3512 *DP = (*DP & ~mask) | signal_levels;
3513}
3514
a4fc5ed6 3515static bool
ea5b213a 3516intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3517 uint32_t *DP,
58e10eb9 3518 uint8_t dp_train_pat)
a4fc5ed6 3519{
174edf1f 3520 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3521 struct drm_i915_private *dev_priv =
3522 to_i915(intel_dig_port->base.base.dev);
3523 struct intel_crtc *crtc =
3524 to_intel_crtc(intel_dig_port->base.base.crtc);
2cdfe6c8
JN		 3525 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3526 int ret, len;
a4fc5ed6 3527
7b13b58a 3528 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3529
70aff66c 3530 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3531 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3532
2cdfe6c8
JN		 3533 buf[0] = dp_train_pat;
3534 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3535 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3536 /* don't write DP_TRAINING_LANEx_SET on disable */
3537 len = 1;
3538 } else {
3539 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
90a6b7b0
VS		 3540 memcpy(buf + 1, intel_dp->train_set, crtc->config->lane_count);
3541 len = crtc->config->lane_count + 1;
47ea7542 3542 }
a4fc5ed6 3543
9d1a1031
JN		 3544 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3545 buf, len);
2cdfe6c8
JN		 3546
3547 return ret == len;
a4fc5ed6
KP		 3548}
3549
70aff66c
JN		 3550static bool
3551intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3552 uint8_t dp_train_pat)
3553{
4e96c977
MK		 3554 if (!intel_dp->train_set_valid)
3555 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3556 intel_dp_set_signal_levels(intel_dp, DP);
3557 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3558}
3559
3560static bool
3561intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3562 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3563{
3564 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3565 struct drm_i915_private *dev_priv =
3566 to_i915(intel_dig_port->base.base.dev);
3567 struct intel_crtc *crtc =
3568 to_intel_crtc(intel_dig_port->base.base.crtc);
70aff66c
JN		 3569 int ret;
3570
3571 intel_get_adjust_train(intel_dp, link_status);
3572 intel_dp_set_signal_levels(intel_dp, DP);
3573
3574 I915_WRITE(intel_dp->output_reg, *DP);
3575 POSTING_READ(intel_dp->output_reg);
3576
9d1a1031 3577 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
90a6b7b0 3578 intel_dp->train_set, crtc->config->lane_count);
70aff66c 3579
90a6b7b0 3580 return ret == crtc->config->lane_count;
70aff66c
JN		 3581}
3582
3ab9c637
ID		 3583static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3584{
3585 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3586 struct drm_device *dev = intel_dig_port->base.base.dev;
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588 enum port port = intel_dig_port->port;
3589 uint32_t val;
3590
3591 if (!HAS_DDI(dev))
3592 return;
3593
3594 val = I915_READ(DP_TP_CTL(port));
3595 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3596 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3597 I915_WRITE(DP_TP_CTL(port), val);
3598
3599 /*
3600 * On PORT_A we can have only eDP in SST mode. There the only reason
3601 * we need to set idle transmission mode is to work around a HW issue
3602 * where we enable the pipe while not in idle link-training mode.
3603 * In this case there is requirement to wait for a minimum number of
3604 * idle patterns to be sent.
3605 */
3606 if (port == PORT_A)
3607 return;
3608
3609 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3610 1))
3611 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3612}
3613
33a34e4e 3614/* Enable corresponding port and start training pattern 1 */
c19b0669 3615void
33a34e4e 3616intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3617{
da63a9f2 3618 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
90a6b7b0
VS		 3619 struct intel_crtc *crtc =
3620 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
c19b0669 3621 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3622 int i;
3623 uint8_t voltage;
cdb0e95b 3624 int voltage_tries, loop_tries;
ea5b213a 3625 uint32_t DP = intel_dp->DP;
6aba5b6c 3626 uint8_t link_config[2];
a4fc5ed6 3627
affa9354 3628 if (HAS_DDI(dev))
c19b0669
PZ		 3629 intel_ddi_prepare_link_retrain(encoder);
3630
3cf2efb1 3631 /* Write the link configuration data */
6aba5b6c 3632 link_config[0] = intel_dp->link_bw;
90a6b7b0 3633 link_config[1] = crtc->config->lane_count;
6aba5b6c
JN		 3634 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3635 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3636 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
94ca719e 3637 if (intel_dp->num_sink_rates)
a8f3ef61
SJ		 3638 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3639 &intel_dp->rate_select, 1);
6aba5b6c
JN		 3640
3641 link_config[0] = 0;
3642 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3643 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3644
3645 DP |= DP_PORT_EN;
1a2eb460 3646
70aff66c
JN		 3647 /* clock recovery */
3648 if (!intel_dp_reset_link_train(intel_dp, &DP,
3649 DP_TRAINING_PATTERN_1 |
3650 DP_LINK_SCRAMBLING_DISABLE)) {
3651 DRM_ERROR("failed to enable link training\n");
3652 return;
3653 }
3654
a4fc5ed6 3655 voltage = 0xff;
cdb0e95b
KP		 3656 voltage_tries = 0;
3657 loop_tries = 0;
a4fc5ed6 3658 for (;;) {
70aff66c 3659 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3660
a7c9655f 3661 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3662 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3663 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3664 break;
93f62dad 3665 }
a4fc5ed6 3666
90a6b7b0 3667 if (drm_dp_clock_recovery_ok(link_status, crtc->config->lane_count)) {
93f62dad 3668 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3669 break;
3670 }
3671
4e96c977
MK		 3672 /*
3673 * if we used previously trained voltage and pre-emphasis values
3674 * and we don't get clock recovery, reset link training values
3675 */
3676 if (intel_dp->train_set_valid) {
3677 DRM_DEBUG_KMS("clock recovery not ok, reset");
3678 /* clear the flag as we are not reusing train set */
3679 intel_dp->train_set_valid = false;
3680 if (!intel_dp_reset_link_train(intel_dp, &DP,
3681 DP_TRAINING_PATTERN_1 |
3682 DP_LINK_SCRAMBLING_DISABLE)) {
3683 DRM_ERROR("failed to enable link training\n");
3684 return;
3685 }
3686 continue;
3687 }
3688
3cf2efb1 3689 /* Check to see if we've tried the max voltage */
90a6b7b0 3690 for (i = 0; i < crtc->config->lane_count; i++)
3cf2efb1 3691 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3692 break;
90a6b7b0 3693 if (i == crtc->config->lane_count) {
b06fbda3
DV		 3694 ++loop_tries;
3695 if (loop_tries == 5) {
3def84b3 3696 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3697 break;
3698 }
70aff66c
JN		 3699 intel_dp_reset_link_train(intel_dp, &DP,
3700 DP_TRAINING_PATTERN_1 |
3701 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3702 voltage_tries = 0;
3703 continue;
3704 }
a4fc5ed6 3705
3cf2efb1 3706 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3707 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3708 ++voltage_tries;
b06fbda3 3709 if (voltage_tries == 5) {
3def84b3 3710 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3711 break;
3712 }
3713 } else
3714 voltage_tries = 0;
3715 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3716
70aff66c
JN		 3717 /* Update training set as requested by target */
3718 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3719 DRM_ERROR("failed to update link training\n");
3720 break;
3721 }
a4fc5ed6
KP		 3722 }
3723
33a34e4e
JB		 3724 intel_dp->DP = DP;
3725}
3726
c19b0669 3727void
33a34e4e
JB		 3728intel_dp_complete_link_train(struct intel_dp *intel_dp)
3729{
90a6b7b0
VS		 3730 struct intel_crtc *crtc =
3731 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
33a34e4e 3732 bool channel_eq = false;
37f80975 3733 int tries, cr_tries;
33a34e4e 3734 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3735 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3736
a79b8165
VS		 3737 /* Training Pattern 3 for HBR2 or 1.2 devices that support it*/
3738 if (crtc->config->port_clock == 540000 || intel_dp->use_tps3)
06ea66b6 3739 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3740
a4fc5ed6 3741 /* channel equalization */
70aff66c 3742 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3743 training_pattern |
70aff66c
JN		 3744 DP_LINK_SCRAMBLING_DISABLE)) {
3745 DRM_ERROR("failed to start channel equalization\n");
3746 return;
3747 }
3748
a4fc5ed6 3749 tries = 0;
37f80975 3750 cr_tries = 0;
a4fc5ed6
KP		 3751 channel_eq = false;
3752 for (;;) {
70aff66c 3753 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3754
37f80975
JB		 3755 if (cr_tries > 5) {
3756 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3757 break;
3758 }
3759
a7c9655f 3760 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3761 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3762 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3763 break;
70aff66c 3764 }
a4fc5ed6 3765
37f80975 3766 /* Make sure clock is still ok */
90a6b7b0
VS		 3767 if (!drm_dp_clock_recovery_ok(link_status,
3768 crtc->config->lane_count)) {
4e96c977 3769 intel_dp->train_set_valid = false;
37f80975 3770 intel_dp_start_link_train(intel_dp);
70aff66c 3771 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3772 training_pattern |
70aff66c 3773 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3774 cr_tries++;
3775 continue;
3776 }
3777
90a6b7b0
VS		 3778 if (drm_dp_channel_eq_ok(link_status,
3779 crtc->config->lane_count)) {
3cf2efb1
CW		 3780 channel_eq = true;
3781 break;
3782 }
a4fc5ed6 3783
37f80975
JB		 3784 /* Try 5 times, then try clock recovery if that fails */
3785 if (tries > 5) {
4e96c977 3786 intel_dp->train_set_valid = false;
37f80975 3787 intel_dp_start_link_train(intel_dp);
70aff66c 3788 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3789 training_pattern |
70aff66c 3790 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3791 tries = 0;
3792 cr_tries++;
3793 continue;
3794 }
a4fc5ed6 3795
70aff66c
JN		 3796 /* Update training set as requested by target */
3797 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3798 DRM_ERROR("failed to update link training\n");
3799 break;
3800 }
3cf2efb1 3801 ++tries;
869184a6 3802 }
3cf2efb1 3803
3ab9c637
ID		 3804 intel_dp_set_idle_link_train(intel_dp);
3805
3806 intel_dp->DP = DP;
3807
4e96c977 3808 if (channel_eq) {
5fa836a9 3809 intel_dp->train_set_valid = true;
07f42258 3810 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
4e96c977 3811 }
3ab9c637
ID		 3812}
3813
3814void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3815{
70aff66c 3816 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3817 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3818}
3819
3820static void
ea5b213a 3821intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3822{
da63a9f2 3823 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3824 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3825 enum port port = intel_dig_port->port;
da63a9f2 3826 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3827 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3828 uint32_t DP = intel_dp->DP;
a4fc5ed6 3829
bc76e320 3830 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3831 return;
3832
0c33d8d7 3833 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3834 return;
3835
28c97730 3836 DRM_DEBUG_KMS("\n");
32f9d658 3837
39e5fa88
VS		 3838 if ((IS_GEN7(dev) && port == PORT_A) ||
3839 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3840 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3841 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3842 } else {
aad3d14d
VS		 3843 if (IS_CHERRYVIEW(dev))
3844 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3845 else
3846 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3847 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3848 }
1612c8bd 3849 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3850 POSTING_READ(intel_dp->output_reg);
5eb08b69 3851
1612c8bd
VS		 3852 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3853 I915_WRITE(intel_dp->output_reg, DP);
3854 POSTING_READ(intel_dp->output_reg);
3855
3856 /*
3857 * HW workaround for IBX, we need to move the port
3858 * to transcoder A after disabling it to allow the
3859 * matching HDMI port to be enabled on transcoder A.
3860 */
3861 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3862 /* always enable with pattern 1 (as per spec) */
3863 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3864 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3865 I915_WRITE(intel_dp->output_reg, DP);
3866 POSTING_READ(intel_dp->output_reg);
3867
3868 DP &= ~DP_PORT_EN;
5bddd17f 3869 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3870 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3871 }
3872
f01eca2e 3873 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3874}
3875
26d61aad
KP		 3876static bool
3877intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3878{
a031d709
RV		 3879 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3880 struct drm_device *dev = dig_port->base.base.dev;
3881 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3882 uint8_t rev;
a031d709 3883
9d1a1031
JN		 3884 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3885 sizeof(intel_dp->dpcd)) < 0)
edb39244 3886 return false; /* aux transfer failed */
92fd8fd1 3887
a8e98153 3888 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3889
edb39244
AJ		 3890 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3891 return false; /* DPCD not present */
3892
2293bb5c
SK		 3893 /* Check if the panel supports PSR */
3894 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3895 if (is_edp(intel_dp)) {
9d1a1031
JN		 3896 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3897 intel_dp->psr_dpcd,
3898 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3899 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3900 dev_priv->psr.sink_support = true;
50003939 3901 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3902 }
474d1ec4
SJ		 3903
3904 if (INTEL_INFO(dev)->gen >= 9 &&
3905 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3906 uint8_t frame_sync_cap;
3907
3908 dev_priv->psr.sink_support = true;
3909 intel_dp_dpcd_read_wake(&intel_dp->aux,
3910 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3911 &frame_sync_cap, 1);
3912 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3913 /* PSR2 needs frame sync as well */
3914 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3915 DRM_DEBUG_KMS("PSR2 %s on sink",
3916 dev_priv->psr.psr2_support ? "supported" : "not supported");
3917 }
50003939
JN		 3918 }
3919
7809a611 3920 /* Training Pattern 3 support, both source and sink */
06ea66b6 3921 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3922 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3923 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3924 intel_dp->use_tps3 = true;
f8d8a672 3925 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3926 } else
3927 intel_dp->use_tps3 = false;
3928
fc0f8e25
SJ		 3929 /* Intermediate frequency support */
3930 if (is_edp(intel_dp) &&
3931 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3932 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3933 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3934 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3935 int i;
3936
fc0f8e25
SJ		 3937 intel_dp_dpcd_read_wake(&intel_dp->aux,
3938 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3939 sink_rates,
3940 sizeof(sink_rates));
ea2d8a42 3941
94ca719e
VS		 3942 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3943 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3944
3945 if (val == 0)
3946 break;
3947
af77b974
SJ		 3948 /* Value read is in kHz while drm clock is saved in deca-kHz */
3949 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3950 }
94ca719e 3951 intel_dp->num_sink_rates = i;
fc0f8e25 3952 }
0336400e
VS		 3953
3954 intel_dp_print_rates(intel_dp);
3955
edb39244
AJ		 3956 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3957 DP_DWN_STRM_PORT_PRESENT))
3958 return true; /* native DP sink */
3959
3960 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3961 return true; /* no per-port downstream info */
3962
9d1a1031
JN		 3963 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3964 intel_dp->downstream_ports,
3965 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3966 return false; /* downstream port status fetch failed */
3967
3968 return true;
92fd8fd1
KP		 3969}
3970
0d198328
AJ		 3971static void
3972intel_dp_probe_oui(struct intel_dp *intel_dp)
3973{
3974 u8 buf[3];
3975
3976 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3977 return;
3978
9d1a1031 3979 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3980 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3981 buf[0], buf[1], buf[2]);
3982
9d1a1031 3983 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3984 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3985 buf[0], buf[1], buf[2]);
3986}
3987
0e32b39c
DA		 3988static bool
3989intel_dp_probe_mst(struct intel_dp *intel_dp)
3990{
3991 u8 buf[1];
3992
3993 if (!intel_dp->can_mst)
3994 return false;
3995
3996 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3997 return false;
3998
0e32b39c
DA		 3999 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
4000 if (buf[0] & DP_MST_CAP) {
4001 DRM_DEBUG_KMS("Sink is MST capable\n");
4002 intel_dp->is_mst = true;
4003 } else {
4004 DRM_DEBUG_KMS("Sink is not MST capable\n");
4005 intel_dp->is_mst = false;
4006 }
4007 }
0e32b39c
DA		 4008
4009 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4010 return intel_dp->is_mst;
4011}
4012
e5a1cab5 4013static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 4014{
082dcc7c
RV		 4015 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4016 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 4017 u8 buf;
e5a1cab5 4018 int ret = 0;
d2e216d0 4019
082dcc7c
RV		 4020 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
4021 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 4022 ret = -EIO;
4023 goto out;
4373f0f2
PZ		 4024 }
4025
082dcc7c 4026 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 4027 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 4028 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 4029 ret = -EIO;
4030 goto out;
4031 }
d2e216d0 4032
621d4c76 4033 intel_dp->sink_crc.started = false;
e5a1cab5 4034 out:
082dcc7c 4035 hsw_enable_ips(intel_crtc);
e5a1cab5 4036 return ret;
082dcc7c
RV		 4037}
4038
4039static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
4040{
4041 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4042 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4043 u8 buf;
e5a1cab5
RV		 4044 int ret;
4045
621d4c76 4046 if (intel_dp->sink_crc.started) {
e5a1cab5
RV		 4047 ret = intel_dp_sink_crc_stop(intel_dp);
4048 if (ret)
4049 return ret;
4050 }
082dcc7c
RV		 4051
4052 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4053 return -EIO;
4054
4055 if (!(buf & DP_TEST_CRC_SUPPORTED))
4056 return -ENOTTY;
4057
621d4c76
RV		 4058 intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
4059
082dcc7c
RV		 4060 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4061 return -EIO;
4062
4063 hsw_disable_ips(intel_crtc);
1dda5f93 4064
9d1a1031 4065 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 4066 buf | DP_TEST_SINK_START) < 0) {
4067 hsw_enable_ips(intel_crtc);
4068 return -EIO;
4373f0f2
PZ		 4069 }
4070
621d4c76 4071 intel_dp->sink_crc.started = true;
082dcc7c
RV		 4072 return 0;
4073}
4074
4075int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4076{
4077 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4078 struct drm_device *dev = dig_port->base.base.dev;
4079 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4080 u8 buf;
621d4c76 4081 int count, ret;
082dcc7c 4082 int attempts = 6;
aabc95dc 4083 bool old_equal_new;
082dcc7c
RV		 4084
4085 ret = intel_dp_sink_crc_start(intel_dp);
4086 if (ret)
4087 return ret;
4088
ad9dc91b 4089 do {
621d4c76
RV		 4090 intel_wait_for_vblank(dev, intel_crtc->pipe);
4091
1dda5f93 4092 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 4093 DP_TEST_SINK_MISC, &buf) < 0) {
4094 ret = -EIO;
afe0d67e 4095 goto stop;
4373f0f2 4096 }
621d4c76 4097 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 4098
621d4c76
RV		 4099 /*
4100 * Count might be reset during the loop. In this case
4101 * last known count needs to be reset as well.
4102 */
4103 if (count == 0)
4104 intel_dp->sink_crc.last_count = 0;
4105
4106 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4107 ret = -EIO;
4108 goto stop;
4109 }
aabc95dc
RV		 4110
4111 old_equal_new = (count == intel_dp->sink_crc.last_count &&
4112 !memcmp(intel_dp->sink_crc.last_crc, crc,
4113 6 * sizeof(u8)));
4114
4115 } while (--attempts && (count == 0 || old_equal_new));
621d4c76
RV		 4116
4117 intel_dp->sink_crc.last_count = buf & DP_TEST_COUNT_MASK;
4118 memcpy(intel_dp->sink_crc.last_crc, crc, 6 * sizeof(u8));
ad9dc91b
RV		 4119
4120 if (attempts == 0) {
aabc95dc
RV		 4121 if (old_equal_new) {
4122 DRM_DEBUG_KMS("Unreliable Sink CRC counter: Current returned CRC is identical to the previous one\n");
4123 } else {
4124 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4125 ret = -ETIMEDOUT;
4126 goto stop;
4127 }
ad9dc91b 4128 }
d2e216d0 4129
afe0d67e 4130stop:
082dcc7c 4131 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 4132 return ret;
d2e216d0
RV		 4133}
4134
a60f0e38
JB		 4135static bool
4136intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4137{
9d1a1031
JN		 4138 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4139 DP_DEVICE_SERVICE_IRQ_VECTOR,
4140 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4141}
4142
0e32b39c
DA		 4143static bool
4144intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4145{
4146 int ret;
4147
4148 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4149 DP_SINK_COUNT_ESI,
4150 sink_irq_vector, 14);
4151 if (ret != 14)
4152 return false;
4153
4154 return true;
4155}
4156
c5d5ab7a
TP		 4157static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4158{
4159 uint8_t test_result = DP_TEST_ACK;
4160 return test_result;
4161}
4162
4163static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4164{
4165 uint8_t test_result = DP_TEST_NAK;
4166 return test_result;
4167}
4168
4169static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4170{
c5d5ab7a 4171 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4172 struct intel_connector *intel_connector = intel_dp->attached_connector;
4173 struct drm_connector *connector = &intel_connector->base;
4174
4175 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4176 connector->edid_corrupt ||
559be30c
TP		 4177 intel_dp->aux.i2c_defer_count > 6) {
4178 /* Check EDID read for NACKs, DEFERs and corruption
4179 * (DP CTS 1.2 Core r1.1)
4180 * 4.2.2.4 : Failed EDID read, I2C_NAK
4181 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4182 * 4.2.2.6 : EDID corruption detected
4183 * Use failsafe mode for all cases
4184 */
4185 if (intel_dp->aux.i2c_nack_count > 0 ||
4186 intel_dp->aux.i2c_defer_count > 0)
4187 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4188 intel_dp->aux.i2c_nack_count,
4189 intel_dp->aux.i2c_defer_count);
4190 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4191 } else {
f79b468e
TS		 4192 struct edid *block = intel_connector->detect_edid;
4193
4194 /* We have to write the checksum
4195 * of the last block read
4196 */
4197 block += intel_connector->detect_edid->extensions;
4198
559be30c
TP		 4199 if (!drm_dp_dpcd_write(&intel_dp->aux,
4200 DP_TEST_EDID_CHECKSUM,
f79b468e 4201 &block->checksum,
5a1cc655 4202 1))
559be30c
TP		 4203 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4204
4205 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4206 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4207 }
4208
4209 /* Set test active flag here so userspace doesn't interrupt things */
4210 intel_dp->compliance_test_active = 1;
4211
c5d5ab7a
TP		 4212 return test_result;
4213}
4214
4215static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4216{
c5d5ab7a
TP		 4217 uint8_t test_result = DP_TEST_NAK;
4218 return test_result;
4219}
4220
4221static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4222{
4223 uint8_t response = DP_TEST_NAK;
4224 uint8_t rxdata = 0;
4225 int status = 0;
4226
559be30c 4227 intel_dp->compliance_test_active = 0;
c5d5ab7a 4228 intel_dp->compliance_test_type = 0;
559be30c
TP		 4229 intel_dp->compliance_test_data = 0;
4230
c5d5ab7a
TP		 4231 intel_dp->aux.i2c_nack_count = 0;
4232 intel_dp->aux.i2c_defer_count = 0;
4233
4234 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4235 if (status <= 0) {
4236 DRM_DEBUG_KMS("Could not read test request from sink\n");
4237 goto update_status;
4238 }
4239
4240 switch (rxdata) {
4241 case DP_TEST_LINK_TRAINING:
4242 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4243 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4244 response = intel_dp_autotest_link_training(intel_dp);
4245 break;
4246 case DP_TEST_LINK_VIDEO_PATTERN:
4247 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4248 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4249 response = intel_dp_autotest_video_pattern(intel_dp);
4250 break;
4251 case DP_TEST_LINK_EDID_READ:
4252 DRM_DEBUG_KMS("EDID test requested\n");
4253 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4254 response = intel_dp_autotest_edid(intel_dp);
4255 break;
4256 case DP_TEST_LINK_PHY_TEST_PATTERN:
4257 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4258 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4259 response = intel_dp_autotest_phy_pattern(intel_dp);
4260 break;
4261 default:
4262 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4263 break;
4264 }
4265
4266update_status:
4267 status = drm_dp_dpcd_write(&intel_dp->aux,
4268 DP_TEST_RESPONSE,
4269 &response, 1);
4270 if (status <= 0)
4271 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4272}
4273
0e32b39c
DA		 4274static int
4275intel_dp_check_mst_status(struct intel_dp *intel_dp)
4276{
90a6b7b0
VS		 4277 struct intel_crtc *crtc =
4278 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
0e32b39c
DA		 4279 bool bret;
4280
4281 if (intel_dp->is_mst) {
4282 u8 esi[16] = { 0 };
4283 int ret = 0;
4284 int retry;
4285 bool handled;
4286 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4287go_again:
4288 if (bret == true) {
4289
4290 /* check link status - esi[10] = 0x200c */
90a6b7b0
VS		 4291 if (intel_dp->active_mst_links &&
4292 !drm_dp_channel_eq_ok(&esi[10], crtc->config->lane_count)) {
0e32b39c
DA		 4293 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4294 intel_dp_start_link_train(intel_dp);
4295 intel_dp_complete_link_train(intel_dp);
4296 intel_dp_stop_link_train(intel_dp);
4297 }
4298
6f34cc39 4299 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4300 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4301
4302 if (handled) {
4303 for (retry = 0; retry < 3; retry++) {
4304 int wret;
4305 wret = drm_dp_dpcd_write(&intel_dp->aux,
4306 DP_SINK_COUNT_ESI+1,
4307 &esi[1], 3);
4308 if (wret == 3) {
4309 break;
4310 }
4311 }
4312
4313 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4314 if (bret == true) {
6f34cc39 4315 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4316 goto go_again;
4317 }
4318 } else
4319 ret = 0;
4320
4321 return ret;
4322 } else {
4323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4324 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4325 intel_dp->is_mst = false;
4326 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4327 /* send a hotplug event */
4328 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4329 }
4330 }
4331 return -EINVAL;
4332}
4333
a4fc5ed6
KP		 4334/*
4335 * According to DP spec
4336 * 5.1.2:
4337 * 1. Read DPCD
4338 * 2. Configure link according to Receiver Capabilities
4339 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4340 * 4. Check link status on receipt of hot-plug interrupt
4341 */
a5146200 4342static void
ea5b213a 4343intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4344{
5b215bcf 4345 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4346 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
90a6b7b0
VS		 4347 struct intel_crtc *crtc =
4348 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
a60f0e38 4349 u8 sink_irq_vector;
93f62dad 4350 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4351
5b215bcf
DA		 4352 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4353
e02f9a06 4354 if (!intel_encoder->base.crtc)
a4fc5ed6
KP		 4355 return;
4356
1a125d8a
ID		 4357 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4358 return;
4359
92fd8fd1 4360 /* Try to read receiver status if the link appears to be up */
93f62dad 4361 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4362 return;
4363 }
4364
92fd8fd1 4365 /* Now read the DPCD to see if it's actually running */
26d61aad 4366 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4367 return;
4368 }
4369
a60f0e38
JB		 4370 /* Try to read the source of the interrupt */
4371 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4372 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4373 /* Clear interrupt source */
9d1a1031
JN		 4374 drm_dp_dpcd_writeb(&intel_dp->aux,
4375 DP_DEVICE_SERVICE_IRQ_VECTOR,
4376 sink_irq_vector);
a60f0e38
JB		 4377
4378 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4379 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4380 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4381 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4382 }
4383
90a6b7b0 4384 if (!drm_dp_channel_eq_ok(link_status, crtc->config->lane_count)) {
92fd8fd1 4385 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4386 intel_encoder->base.name);
33a34e4e
JB		 4387 intel_dp_start_link_train(intel_dp);
4388 intel_dp_complete_link_train(intel_dp);
3ab9c637 4389 intel_dp_stop_link_train(intel_dp);
33a34e4e 4390 }
a4fc5ed6 4391}
a4fc5ed6 4392
caf9ab24 4393/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4394static enum drm_connector_status
26d61aad 4395intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4396{
caf9ab24 4397 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4398 uint8_t type;
4399
4400 if (!intel_dp_get_dpcd(intel_dp))
4401 return connector_status_disconnected;
4402
4403 /* if there's no downstream port, we're done */
4404 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4405 return connector_status_connected;
caf9ab24
AJ		 4406
4407 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4408 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4409 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4410 uint8_t reg;
9d1a1031
JN		 4411
4412 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4413 &reg, 1) < 0)
caf9ab24 4414 return connector_status_unknown;
9d1a1031 4415
23235177
AJ		 4416 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4417 : connector_status_disconnected;
caf9ab24
AJ		 4418 }
4419
4420 /* If no HPD, poke DDC gently */
0b99836f 4421 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4422 return connector_status_connected;
caf9ab24
AJ		 4423
4424 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4425 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4426 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4427 if (type == DP_DS_PORT_TYPE_VGA ||
4428 type == DP_DS_PORT_TYPE_NON_EDID)
4429 return connector_status_unknown;
4430 } else {
4431 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4432 DP_DWN_STRM_PORT_TYPE_MASK;
4433 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4434 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4435 return connector_status_unknown;
4436 }
caf9ab24
AJ		 4437
4438 /* Anything else is out of spec, warn and ignore */
4439 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4440 return connector_status_disconnected;
71ba9000
AJ		 4441}
4442
d410b56d
CW		 4443static enum drm_connector_status
4444edp_detect(struct intel_dp *intel_dp)
4445{
4446 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4447 enum drm_connector_status status;
4448
4449 status = intel_panel_detect(dev);
4450 if (status == connector_status_unknown)
4451 status = connector_status_connected;
4452
4453 return status;
4454}
4455
5eb08b69 4456static enum drm_connector_status
a9756bb5 4457ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4458{
30add22d 4459 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4460 struct drm_i915_private *dev_priv = dev->dev_private;
4461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4462
1b469639
DL		 4463 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4464 return connector_status_disconnected;
4465
26d61aad 4466 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4467}
4468
2a592bec
DA		 4469static int g4x_digital_port_connected(struct drm_device *dev,
4470 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4471{
a4fc5ed6 4472 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4473 uint32_t bit;
5eb08b69 4474
232a6ee9
TP		 4475 if (IS_VALLEYVIEW(dev)) {
4476 switch (intel_dig_port->port) {
4477 case PORT_B:
4478 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4479 break;
4480 case PORT_C:
4481 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4482 break;
4483 case PORT_D:
4484 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4485 break;
4486 default:
2a592bec 4487 return -EINVAL;
232a6ee9
TP		 4488 }
4489 } else {
4490 switch (intel_dig_port->port) {
4491 case PORT_B:
4492 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4493 break;
4494 case PORT_C:
4495 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4496 break;
4497 case PORT_D:
4498 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4499 break;
4500 default:
2a592bec 4501 return -EINVAL;
232a6ee9 4502 }
a4fc5ed6
KP		 4503 }
4504
10f76a38 4505 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4506 return 0;
4507 return 1;
4508}
4509
4510static enum drm_connector_status
4511g4x_dp_detect(struct intel_dp *intel_dp)
4512{
4513 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4514 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4515 int ret;
4516
4517 /* Can't disconnect eDP, but you can close the lid... */
4518 if (is_edp(intel_dp)) {
4519 enum drm_connector_status status;
4520
4521 status = intel_panel_detect(dev);
4522 if (status == connector_status_unknown)
4523 status = connector_status_connected;
4524 return status;
4525 }
4526
4527 ret = g4x_digital_port_connected(dev, intel_dig_port);
4528 if (ret == -EINVAL)
4529 return connector_status_unknown;
4530 else if (ret == 0)
a4fc5ed6
KP		 4531 return connector_status_disconnected;
4532
26d61aad 4533 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4534}
4535
8c241fef 4536static struct edid *
beb60608 4537intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4538{
beb60608 4539 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4540
9cd300e0
JN		 4541 /* use cached edid if we have one */
4542 if (intel_connector->edid) {
9cd300e0
JN		 4543 /* invalid edid */
4544 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4545 return NULL;
4546
55e9edeb 4547 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4548 } else
4549 return drm_get_edid(&intel_connector->base,
4550 &intel_dp->aux.ddc);
4551}
8c241fef 4552
beb60608
CW		 4553static void
4554intel_dp_set_edid(struct intel_dp *intel_dp)
4555{
4556 struct intel_connector *intel_connector = intel_dp->attached_connector;
4557 struct edid *edid;
8c241fef 4558
beb60608
CW		 4559 edid = intel_dp_get_edid(intel_dp);
4560 intel_connector->detect_edid = edid;
4561
4562 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4563 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4564 else
4565 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4566}
4567
beb60608
CW		 4568static void
4569intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4570{
beb60608 4571 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4572
beb60608
CW		 4573 kfree(intel_connector->detect_edid);
4574 intel_connector->detect_edid = NULL;
9cd300e0 4575
beb60608
CW		 4576 intel_dp->has_audio = false;
4577}
d6f24d0f 4578
beb60608
CW		 4579static enum intel_display_power_domain
4580intel_dp_power_get(struct intel_dp *dp)
4581{
4582 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4583 enum intel_display_power_domain power_domain;
4584
4585 power_domain = intel_display_port_power_domain(encoder);
4586 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4587
4588 return power_domain;
4589}
d6f24d0f 4590
beb60608
CW		 4591static void
4592intel_dp_power_put(struct intel_dp *dp,
4593 enum intel_display_power_domain power_domain)
4594{
4595 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4596 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4597}
4598
a9756bb5
ZW		 4599static enum drm_connector_status
4600intel_dp_detect(struct drm_connector *connector, bool force)
4601{
4602 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4603 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4604 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4605 struct drm_device *dev = connector->dev;
a9756bb5 4606 enum drm_connector_status status;
671dedd2 4607 enum intel_display_power_domain power_domain;
0e32b39c 4608 bool ret;
09b1eb13 4609 u8 sink_irq_vector;
a9756bb5 4610
164c8598 4611 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4612 connector->base.id, connector->name);
beb60608 4613 intel_dp_unset_edid(intel_dp);
164c8598 4614
0e32b39c
DA		 4615 if (intel_dp->is_mst) {
4616 /* MST devices are disconnected from a monitor POV */
4617 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4618 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4619 return connector_status_disconnected;
0e32b39c
DA		 4620 }
4621
beb60608 4622 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4623
d410b56d
CW		 4624 /* Can't disconnect eDP, but you can close the lid... */
4625 if (is_edp(intel_dp))
4626 status = edp_detect(intel_dp);
4627 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4628 status = ironlake_dp_detect(intel_dp);
4629 else
4630 status = g4x_dp_detect(intel_dp);
4631 if (status != connector_status_connected)
c8c8fb33 4632 goto out;
a9756bb5 4633
0d198328
AJ		 4634 intel_dp_probe_oui(intel_dp);
4635
0e32b39c
DA		 4636 ret = intel_dp_probe_mst(intel_dp);
4637 if (ret) {
4638 /* if we are in MST mode then this connector
4639 won't appear connected or have anything with EDID on it */
4640 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4641 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4642 status = connector_status_disconnected;
4643 goto out;
4644 }
4645
beb60608 4646 intel_dp_set_edid(intel_dp);
a9756bb5 4647
d63885da
PZ		 4648 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4649 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4650 status = connector_status_connected;
4651
09b1eb13
TP		 4652 /* Try to read the source of the interrupt */
4653 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4654 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4655 /* Clear interrupt source */
4656 drm_dp_dpcd_writeb(&intel_dp->aux,
4657 DP_DEVICE_SERVICE_IRQ_VECTOR,
4658 sink_irq_vector);
4659
4660 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4661 intel_dp_handle_test_request(intel_dp);
4662 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4663 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4664 }
4665
c8c8fb33 4666out:
beb60608 4667 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4668 return status;
a4fc5ed6
KP		 4669}
4670
beb60608
CW		 4671static void
4672intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4673{
df0e9248 4674 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4675 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4676 enum intel_display_power_domain power_domain;
a4fc5ed6 4677
beb60608
CW		 4678 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4679 connector->base.id, connector->name);
4680 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4681
beb60608
CW		 4682 if (connector->status != connector_status_connected)
4683 return;
671dedd2 4684
beb60608
CW		 4685 power_domain = intel_dp_power_get(intel_dp);
4686
4687 intel_dp_set_edid(intel_dp);
4688
4689 intel_dp_power_put(intel_dp, power_domain);
4690
4691 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4692 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4693}
4694
4695static int intel_dp_get_modes(struct drm_connector *connector)
4696{
4697 struct intel_connector *intel_connector = to_intel_connector(connector);
4698 struct edid *edid;
4699
4700 edid = intel_connector->detect_edid;
4701 if (edid) {
4702 int ret = intel_connector_update_modes(connector, edid);
4703 if (ret)
4704 return ret;
4705 }
32f9d658 4706
f8779fda 4707 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4708 if (is_edp(intel_attached_dp(connector)) &&
4709 intel_connector->panel.fixed_mode) {
f8779fda 4710 struct drm_display_mode *mode;
beb60608
CW		 4711
4712 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4713 intel_connector->panel.fixed_mode);
f8779fda 4714 if (mode) {
32f9d658
ZW		 4715 drm_mode_probed_add(connector, mode);
4716 return 1;
4717 }
4718 }
beb60608 4719
32f9d658 4720 return 0;
a4fc5ed6
KP		 4721}
4722
1aad7ac0
CW		 4723static bool
4724intel_dp_detect_audio(struct drm_connector *connector)
4725{
1aad7ac0 4726 bool has_audio = false;
beb60608 4727 struct edid *edid;
1aad7ac0 4728
beb60608
CW		 4729 edid = to_intel_connector(connector)->detect_edid;
4730 if (edid)
1aad7ac0 4731 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4732
1aad7ac0
CW		 4733 return has_audio;
4734}
4735
f684960e
CW		 4736static int
4737intel_dp_set_property(struct drm_connector *connector,
4738 struct drm_property *property,
4739 uint64_t val)
4740{
e953fd7b 4741 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4742 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4743 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4744 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4745 int ret;
4746
662595df 4747 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4748 if (ret)
4749 return ret;
4750
3f43c48d 4751 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4752 int i = val;
4753 bool has_audio;
4754
4755 if (i == intel_dp->force_audio)
f684960e
CW		 4756 return 0;
4757
1aad7ac0 4758 intel_dp->force_audio = i;
f684960e 4759
c3e5f67b 4760 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4761 has_audio = intel_dp_detect_audio(connector);
4762 else
c3e5f67b 4763 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4764
4765 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4766 return 0;
4767
1aad7ac0 4768 intel_dp->has_audio = has_audio;
f684960e
CW		 4769 goto done;
4770 }
4771
e953fd7b 4772 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4773 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4774 bool old_range = intel_dp->limited_color_range;
ae4edb80 4775
55bc60db
VS		 4776 switch (val) {
4777 case INTEL_BROADCAST_RGB_AUTO:
4778 intel_dp->color_range_auto = true;
4779 break;
4780 case INTEL_BROADCAST_RGB_FULL:
4781 intel_dp->color_range_auto = false;
0f2a2a75 4782 intel_dp->limited_color_range = false;
55bc60db
VS		 4783 break;
4784 case INTEL_BROADCAST_RGB_LIMITED:
4785 intel_dp->color_range_auto = false;
0f2a2a75 4786 intel_dp->limited_color_range = true;
55bc60db
VS		 4787 break;
4788 default:
4789 return -EINVAL;
4790 }
ae4edb80
DV		 4791
4792 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4793 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4794 return 0;
4795
e953fd7b
CW		 4796 goto done;
4797 }
4798
53b41837
YN		 4799 if (is_edp(intel_dp) &&
4800 property == connector->dev->mode_config.scaling_mode_property) {
4801 if (val == DRM_MODE_SCALE_NONE) {
4802 DRM_DEBUG_KMS("no scaling not supported\n");
4803 return -EINVAL;
4804 }
4805
4806 if (intel_connector->panel.fitting_mode == val) {
4807 /* the eDP scaling property is not changed */
4808 return 0;
4809 }
4810 intel_connector->panel.fitting_mode = val;
4811
4812 goto done;
4813 }
4814
f684960e
CW		 4815 return -EINVAL;
4816
4817done:
c0c36b94
CW		 4818 if (intel_encoder->base.crtc)
4819 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4820
4821 return 0;
4822}
4823
a4fc5ed6 4824static void
73845adf 4825intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4826{
1d508706 4827 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4828
10e972d3 4829 kfree(intel_connector->detect_edid);
beb60608 4830
9cd300e0
JN		 4831 if (!IS_ERR_OR_NULL(intel_connector->edid))
4832 kfree(intel_connector->edid);
4833
acd8db10
PZ		 4834 /* Can't call is_edp() since the encoder may have been destroyed
4835 * already. */
4836 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4837 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4838
a4fc5ed6 4839 drm_connector_cleanup(connector);
55f78c43 4840 kfree(connector);
a4fc5ed6
KP		 4841}
4842
00c09d70 4843void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4844{
da63a9f2
PZ		 4845 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4846 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4847
4f71d0cb 4848 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4849 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4850 if (is_edp(intel_dp)) {
4851 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4852 /*
4853 * vdd might still be enabled do to the delayed vdd off.
4854 * Make sure vdd is actually turned off here.
4855 */
773538e8 4856 pps_lock(intel_dp);
4be73780 4857 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4858 pps_unlock(intel_dp);
4859
01527b31
CT		 4860 if (intel_dp->edp_notifier.notifier_call) {
4861 unregister_reboot_notifier(&intel_dp->edp_notifier);
4862 intel_dp->edp_notifier.notifier_call = NULL;
4863 }
bd943159 4864 }
c8bd0e49 4865 drm_encoder_cleanup(encoder);
da63a9f2 4866 kfree(intel_dig_port);
24d05927
DV		 4867}
4868
07f9cd0b
ID		 4869static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4870{
4871 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4872
4873 if (!is_edp(intel_dp))
4874 return;
4875
951468f3
VS		 4876 /*
4877 * vdd might still be enabled do to the delayed vdd off.
4878 * Make sure vdd is actually turned off here.
4879 */
afa4e53a 4880 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4881 pps_lock(intel_dp);
07f9cd0b 4882 edp_panel_vdd_off_sync(intel_dp);
773538e8 4883 pps_unlock(intel_dp);
07f9cd0b
ID		 4884}
4885
49e6bc51
VS		 4886static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4887{
4888 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4889 struct drm_device *dev = intel_dig_port->base.base.dev;
4890 struct drm_i915_private *dev_priv = dev->dev_private;
4891 enum intel_display_power_domain power_domain;
4892
4893 lockdep_assert_held(&dev_priv->pps_mutex);
4894
4895 if (!edp_have_panel_vdd(intel_dp))
4896 return;
4897
4898 /*
4899 * The VDD bit needs a power domain reference, so if the bit is
4900 * already enabled when we boot or resume, grab this reference and
4901 * schedule a vdd off, so we don't hold on to the reference
4902 * indefinitely.
4903 */
4904 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4905 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4906 intel_display_power_get(dev_priv, power_domain);
4907
4908 edp_panel_vdd_schedule_off(intel_dp);
4909}
4910
6d93c0c4
ID		 4911static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4912{
49e6bc51
VS		 4913 struct intel_dp *intel_dp;
4914
4915 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4916 return;
4917
4918 intel_dp = enc_to_intel_dp(encoder);
4919
4920 pps_lock(intel_dp);
4921
4922 /*
4923 * Read out the current power sequencer assignment,
4924 * in case the BIOS did something with it.
4925 */
4926 if (IS_VALLEYVIEW(encoder->dev))
4927 vlv_initial_power_sequencer_setup(intel_dp);
4928
4929 intel_edp_panel_vdd_sanitize(intel_dp);
4930
4931 pps_unlock(intel_dp);
6d93c0c4
ID		 4932}
4933
a4fc5ed6 4934static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4935 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4936 .detect = intel_dp_detect,
beb60608 4937 .force = intel_dp_force,
a4fc5ed6 4938 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4939 .set_property = intel_dp_set_property,
2545e4a6 4940 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4941 .destroy = intel_dp_connector_destroy,
c6f95f27 4942 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4943 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4944};
4945
4946static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4947 .get_modes = intel_dp_get_modes,
4948 .mode_valid = intel_dp_mode_valid,
df0e9248 4949 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4950};
4951
a4fc5ed6 4952static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4953 .reset = intel_dp_encoder_reset,
24d05927 4954 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4955};
4956
b2c5c181 4957enum irqreturn
13cf5504
DA		 4958intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4959{
4960 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4961 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4962 struct drm_device *dev = intel_dig_port->base.base.dev;
4963 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4964 enum intel_display_power_domain power_domain;
b2c5c181 4965 enum irqreturn ret = IRQ_NONE;
1c767b33 4966
0e32b39c
DA		 4967 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4968 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4969
7a7f84cc
VS		 4970 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4971 /*
4972 * vdd off can generate a long pulse on eDP which
4973 * would require vdd on to handle it, and thus we
4974 * would end up in an endless cycle of
4975 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4976 */
4977 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4978 port_name(intel_dig_port->port));
a8b3d52f 4979 return IRQ_HANDLED;
7a7f84cc
VS		 4980 }
4981
26fbb774
VS		 4982 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4983 port_name(intel_dig_port->port),
0e32b39c 4984 long_hpd ? "long" : "short");
13cf5504 4985
1c767b33
ID		 4986 power_domain = intel_display_port_power_domain(intel_encoder);
4987 intel_display_power_get(dev_priv, power_domain);
4988
0e32b39c 4989 if (long_hpd) {
5fa836a9
MK		 4990 /* indicate that we need to restart link training */
4991 intel_dp->train_set_valid = false;
2a592bec
DA		 4992
4993 if (HAS_PCH_SPLIT(dev)) {
4994 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4995 goto mst_fail;
4996 } else {
4997 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4998 goto mst_fail;
4999 }
0e32b39c
DA		 5000
5001 if (!intel_dp_get_dpcd(intel_dp)) {
5002 goto mst_fail;
5003 }
5004
5005 intel_dp_probe_oui(intel_dp);
5006
5007 if (!intel_dp_probe_mst(intel_dp))
5008 goto mst_fail;
5009
5010 } else {
5011 if (intel_dp->is_mst) {
1c767b33 5012 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 5013 goto mst_fail;
5014 }
5015
5016 if (!intel_dp->is_mst) {
5017 /*
5018 * we'll check the link status via the normal hot plug path later -
5019 * but for short hpds we should check it now
5020 */
5b215bcf 5021 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 5022 intel_dp_check_link_status(intel_dp);
5b215bcf 5023 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 5024 }
5025 }
b2c5c181
DV		 5026
5027 ret = IRQ_HANDLED;
5028
1c767b33 5029 goto put_power;
0e32b39c
DA		 5030mst_fail:
5031 /* if we were in MST mode, and device is not there get out of MST mode */
5032 if (intel_dp->is_mst) {
5033 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5034 intel_dp->is_mst = false;
5035 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
5036 }
1c767b33
ID		 5037put_power:
5038 intel_display_power_put(dev_priv, power_domain);
5039
5040 return ret;
13cf5504
DA		 5041}
5042
e3421a18
ZW		 5043/* Return which DP Port should be selected for Transcoder DP control */
5044int
0206e353 5045intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 5046{
5047 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 5048 struct intel_encoder *intel_encoder;
5049 struct intel_dp *intel_dp;
e3421a18 5050
fa90ecef
PZ		 5051 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5052 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 5053
fa90ecef
PZ		 5054 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
5055 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 5056 return intel_dp->output_reg;
e3421a18 5057 }
ea5b213a 5058
e3421a18
ZW		 5059 return -1;
5060}
5061
36e83a18 5062/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 5063bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 5064{
5065 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 5066 union child_device_config *p_child;
36e83a18 5067 int i;
5d8a7752
VS		 5068 static const short port_mapping[] = {
5069 [PORT_B] = PORT_IDPB,
5070 [PORT_C] = PORT_IDPC,
5071 [PORT_D] = PORT_IDPD,
5072 };
36e83a18 5073
3b32a35b
VS		 5074 if (port == PORT_A)
5075 return true;
5076
41aa3448 5077 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 5078 return false;
5079
41aa3448
RV		 5080 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5081 p_child = dev_priv->vbt.child_dev + i;
36e83a18 5082
5d8a7752 5083 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 5084 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5085 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 5086 return true;
5087 }
5088 return false;
5089}
5090
0e32b39c 5091void
f684960e
CW		 5092intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5093{
53b41837
YN		 5094 struct intel_connector *intel_connector = to_intel_connector(connector);
5095
3f43c48d 5096 intel_attach_force_audio_property(connector);
e953fd7b 5097 intel_attach_broadcast_rgb_property(connector);
55bc60db 5098 intel_dp->color_range_auto = true;
53b41837
YN		 5099
5100 if (is_edp(intel_dp)) {
5101 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 5102 drm_object_attach_property(
5103 &connector->base,
53b41837 5104 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 5105 DRM_MODE_SCALE_ASPECT);
5106 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5107 }
f684960e
CW		 5108}
5109
dada1a9f
ID		 5110static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5111{
5112 intel_dp->last_power_cycle = jiffies;
5113 intel_dp->last_power_on = jiffies;
5114 intel_dp->last_backlight_off = jiffies;
5115}
5116
67a54566
DV		 5117static void
5118intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5119 struct intel_dp *intel_dp)
67a54566
DV		 5120{
5121 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5122 struct edp_power_seq cur, vbt, spec,
5123 *final = &intel_dp->pps_delays;
b0a08bec
VK		 5124 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5125 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg = 0;
453c5420 5126
e39b999a
VS		 5127 lockdep_assert_held(&dev_priv->pps_mutex);
5128
81ddbc69
VS		 5129 /* already initialized? */
5130 if (final->t11_t12 != 0)
5131 return;
5132
b0a08bec
VK		 5133 if (IS_BROXTON(dev)) {
5134 /*
5135 * TODO: BXT has 2 sets of PPS registers.
5136 * Correct Register for Broxton need to be identified
5137 * using VBT. hardcoding for now
5138 */
5139 pp_ctrl_reg = BXT_PP_CONTROL(0);
5140 pp_on_reg = BXT_PP_ON_DELAYS(0);
5141 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5142 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5143 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5144 pp_on_reg = PCH_PP_ON_DELAYS;
5145 pp_off_reg = PCH_PP_OFF_DELAYS;
5146 pp_div_reg = PCH_PP_DIVISOR;
5147 } else {
bf13e81b
JN		 5148 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5149
5150 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5151 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5152 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5153 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5154 }
67a54566
DV		 5155
5156 /* Workaround: Need to write PP_CONTROL with the unlock key as
5157 * the very first thing. */
b0a08bec 5158 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5159
453c5420
JB		 5160 pp_on = I915_READ(pp_on_reg);
5161 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 5162 if (!IS_BROXTON(dev)) {
5163 I915_WRITE(pp_ctrl_reg, pp_ctl);
5164 pp_div = I915_READ(pp_div_reg);
5165 }
67a54566
DV		 5166
5167 /* Pull timing values out of registers */
5168 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5169 PANEL_POWER_UP_DELAY_SHIFT;
5170
5171 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5172 PANEL_LIGHT_ON_DELAY_SHIFT;
5173
5174 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5175 PANEL_LIGHT_OFF_DELAY_SHIFT;
5176
5177 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5178 PANEL_POWER_DOWN_DELAY_SHIFT;
5179
b0a08bec
VK		 5180 if (IS_BROXTON(dev)) {
5181 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5182 BXT_POWER_CYCLE_DELAY_SHIFT;
5183 if (tmp > 0)
5184 cur.t11_t12 = (tmp - 1) * 1000;
5185 else
5186 cur.t11_t12 = 0;
5187 } else {
5188 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5189 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5190 }
67a54566
DV		 5191
5192 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5193 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5194
41aa3448 5195 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5196
5197 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5198 * our hw here, which are all in 100usec. */
5199 spec.t1_t3 = 210 * 10;
5200 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5201 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5202 spec.t10 = 500 * 10;
5203 /* This one is special and actually in units of 100ms, but zero
5204 * based in the hw (so we need to add 100 ms). But the sw vbt
5205 * table multiplies it with 1000 to make it in units of 100usec,
5206 * too. */
5207 spec.t11_t12 = (510 + 100) * 10;
5208
5209 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5210 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5211
5212 /* Use the max of the register settings and vbt. If both are
5213 * unset, fall back to the spec limits. */
36b5f425 5214#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5215 spec.field : \
5216 max(cur.field, vbt.field))
5217 assign_final(t1_t3);
5218 assign_final(t8);
5219 assign_final(t9);
5220 assign_final(t10);
5221 assign_final(t11_t12);
5222#undef assign_final
5223
36b5f425 5224#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5225 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5226 intel_dp->backlight_on_delay = get_delay(t8);
5227 intel_dp->backlight_off_delay = get_delay(t9);
5228 intel_dp->panel_power_down_delay = get_delay(t10);
5229 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5230#undef get_delay
5231
f30d26e4
JN		 5232 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5233 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5234 intel_dp->panel_power_cycle_delay);
5235
5236 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5237 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5238}
5239
5240static void
5241intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5242 struct intel_dp *intel_dp)
f30d26e4
JN		 5243{
5244 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5245 u32 pp_on, pp_off, pp_div, port_sel = 0;
5246 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
b0a08bec 5247 int pp_on_reg, pp_off_reg, pp_div_reg = 0, pp_ctrl_reg;
ad933b56 5248 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5249 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5250
e39b999a 5251 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5252
b0a08bec
VK		 5253 if (IS_BROXTON(dev)) {
5254 /*
5255 * TODO: BXT has 2 sets of PPS registers.
5256 * Correct Register for Broxton need to be identified
5257 * using VBT. hardcoding for now
5258 */
5259 pp_ctrl_reg = BXT_PP_CONTROL(0);
5260 pp_on_reg = BXT_PP_ON_DELAYS(0);
5261 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5262
5263 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 5264 pp_on_reg = PCH_PP_ON_DELAYS;
5265 pp_off_reg = PCH_PP_OFF_DELAYS;
5266 pp_div_reg = PCH_PP_DIVISOR;
5267 } else {
bf13e81b
JN		 5268 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5269
5270 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5271 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5272 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5273 }
5274
b2f19d1a
PZ		 5275 /*
5276 * And finally store the new values in the power sequencer. The
5277 * backlight delays are set to 1 because we do manual waits on them. For
5278 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5279 * we'll end up waiting for the backlight off delay twice: once when we
5280 * do the manual sleep, and once when we disable the panel and wait for
5281 * the PP_STATUS bit to become zero.
5282 */
f30d26e4 5283 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5284 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5285 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5286 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5287 /* Compute the divisor for the pp clock, simply match the Bspec
5288 * formula. */
b0a08bec
VK		 5289 if (IS_BROXTON(dev)) {
5290 pp_div = I915_READ(pp_ctrl_reg);
5291 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5292 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5293 << BXT_POWER_CYCLE_DELAY_SHIFT);
5294 } else {
5295 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5296 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5297 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5298 }
67a54566
DV		 5299
5300 /* Haswell doesn't have any port selection bits for the panel
5301 * power sequencer any more. */
bc7d38a4 5302 if (IS_VALLEYVIEW(dev)) {
ad933b56 5303 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5304 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5305 if (port == PORT_A)
a24c144c 5306 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5307 else
a24c144c 5308 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5309 }
5310
453c5420
JB		 5311 pp_on |= port_sel;
5312
5313 I915_WRITE(pp_on_reg, pp_on);
5314 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 5315 if (IS_BROXTON(dev))
5316 I915_WRITE(pp_ctrl_reg, pp_div);
5317 else
5318 I915_WRITE(pp_div_reg, pp_div);
67a54566 5319
67a54566 5320 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5321 I915_READ(pp_on_reg),
5322 I915_READ(pp_off_reg),
b0a08bec
VK		 5323 IS_BROXTON(dev) ?
5324 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 5325 I915_READ(pp_div_reg));
f684960e
CW		 5326}
5327
b33a2815
VK		 5328/**
5329 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5330 * @dev: DRM device
5331 * @refresh_rate: RR to be programmed
5332 *
5333 * This function gets called when refresh rate (RR) has to be changed from
5334 * one frequency to another. Switches can be between high and low RR
5335 * supported by the panel or to any other RR based on media playback (in
5336 * this case, RR value needs to be passed from user space).
5337 *
5338 * The caller of this function needs to take a lock on dev_priv->drrs.
5339 */
96178eeb 5340static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5341{
5342 struct drm_i915_private *dev_priv = dev->dev_private;
5343 struct intel_encoder *encoder;
96178eeb
VK		 5344 struct intel_digital_port *dig_port = NULL;
5345 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5346 struct intel_crtc_state *config = NULL;
439d7ac0 5347 struct intel_crtc *intel_crtc = NULL;
439d7ac0 5348 u32 reg, val;
96178eeb 5349 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5350
5351 if (refresh_rate <= 0) {
5352 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5353 return;
5354 }
5355
96178eeb
VK		 5356 if (intel_dp == NULL) {
5357 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5358 return;
5359 }
5360
1fcc9d1c 5361 /*
e4d59f6b
RV		 5362 * FIXME: This needs proper synchronization with psr state for some
5363 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5364 */
439d7ac0 5365
96178eeb
VK		 5366 dig_port = dp_to_dig_port(intel_dp);
5367 encoder = &dig_port->base;
723f9aab 5368 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5369
5370 if (!intel_crtc) {
5371 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5372 return;
5373 }
5374
6e3c9717 5375 config = intel_crtc->config;
439d7ac0 5376
96178eeb 5377 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5378 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5379 return;
5380 }
5381
96178eeb
VK		 5382 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5383 refresh_rate)
439d7ac0
PB		 5384 index = DRRS_LOW_RR;
5385
96178eeb 5386 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5387 DRM_DEBUG_KMS(
5388 "DRRS requested for previously set RR...ignoring\n");
5389 return;
5390 }
5391
5392 if (!intel_crtc->active) {
5393 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5394 return;
5395 }
5396
44395bfe 5397 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5398 switch (index) {
5399 case DRRS_HIGH_RR:
5400 intel_dp_set_m_n(intel_crtc, M1_N1);
5401 break;
5402 case DRRS_LOW_RR:
5403 intel_dp_set_m_n(intel_crtc, M2_N2);
5404 break;
5405 case DRRS_MAX_RR:
5406 default:
5407 DRM_ERROR("Unsupported refreshrate type\n");
5408 }
5409 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 5410 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 5411 val = I915_READ(reg);
a4c30b1d 5412
439d7ac0 5413 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5414 if (IS_VALLEYVIEW(dev))
5415 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5416 else
5417 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5418 } else {
6fa7aec1
VK		 5419 if (IS_VALLEYVIEW(dev))
5420 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5421 else
5422 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5423 }
5424 I915_WRITE(reg, val);
5425 }
5426
4e9ac947
VK		 5427 dev_priv->drrs.refresh_rate_type = index;
5428
5429 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5430}
5431
b33a2815
VK		 5432/**
5433 * intel_edp_drrs_enable - init drrs struct if supported
5434 * @intel_dp: DP struct
5435 *
5436 * Initializes frontbuffer_bits and drrs.dp
5437 */
c395578e
VK		 5438void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5439{
5440 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5443 struct drm_crtc *crtc = dig_port->base.base.crtc;
5444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5445
5446 if (!intel_crtc->config->has_drrs) {
5447 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5448 return;
5449 }
5450
5451 mutex_lock(&dev_priv->drrs.mutex);
5452 if (WARN_ON(dev_priv->drrs.dp)) {
5453 DRM_ERROR("DRRS already enabled\n");
5454 goto unlock;
5455 }
5456
5457 dev_priv->drrs.busy_frontbuffer_bits = 0;
5458
5459 dev_priv->drrs.dp = intel_dp;
5460
5461unlock:
5462 mutex_unlock(&dev_priv->drrs.mutex);
5463}
5464
b33a2815
VK		 5465/**
5466 * intel_edp_drrs_disable - Disable DRRS
5467 * @intel_dp: DP struct
5468 *
5469 */
c395578e
VK		 5470void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5471{
5472 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5473 struct drm_i915_private *dev_priv = dev->dev_private;
5474 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5475 struct drm_crtc *crtc = dig_port->base.base.crtc;
5476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5477
5478 if (!intel_crtc->config->has_drrs)
5479 return;
5480
5481 mutex_lock(&dev_priv->drrs.mutex);
5482 if (!dev_priv->drrs.dp) {
5483 mutex_unlock(&dev_priv->drrs.mutex);
5484 return;
5485 }
5486
5487 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5488 intel_dp_set_drrs_state(dev_priv->dev,
5489 intel_dp->attached_connector->panel.
5490 fixed_mode->vrefresh);
5491
5492 dev_priv->drrs.dp = NULL;
5493 mutex_unlock(&dev_priv->drrs.mutex);
5494
5495 cancel_delayed_work_sync(&dev_priv->drrs.work);
5496}
5497
4e9ac947
VK		 5498static void intel_edp_drrs_downclock_work(struct work_struct *work)
5499{
5500 struct drm_i915_private *dev_priv =
5501 container_of(work, typeof(*dev_priv), drrs.work.work);
5502 struct intel_dp *intel_dp;
5503
5504 mutex_lock(&dev_priv->drrs.mutex);
5505
5506 intel_dp = dev_priv->drrs.dp;
5507
5508 if (!intel_dp)
5509 goto unlock;
5510
439d7ac0 5511 /*
4e9ac947
VK		 5512 * The delayed work can race with an invalidate hence we need to
5513 * recheck.
439d7ac0
PB		 5514 */
5515
4e9ac947
VK		 5516 if (dev_priv->drrs.busy_frontbuffer_bits)
5517 goto unlock;
439d7ac0 5518
4e9ac947
VK		 5519 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5520 intel_dp_set_drrs_state(dev_priv->dev,
5521 intel_dp->attached_connector->panel.
5522 downclock_mode->vrefresh);
439d7ac0 5523
4e9ac947 5524unlock:
4e9ac947 5525 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5526}
5527
b33a2815 5528/**
0ddfd203 5529 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5530 * @dev: DRM device
5531 * @frontbuffer_bits: frontbuffer plane tracking bits
5532 *
0ddfd203
R		 5533 * This function gets called everytime rendering on the given planes start.
5534 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5535 *
5536 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5537 */
a93fad0f
VK		 5538void intel_edp_drrs_invalidate(struct drm_device *dev,
5539 unsigned frontbuffer_bits)
5540{
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542 struct drm_crtc *crtc;
5543 enum pipe pipe;
5544
9da7d693 5545 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5546 return;
5547
88f933a8 5548 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5549
a93fad0f 5550 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5551 if (!dev_priv->drrs.dp) {
5552 mutex_unlock(&dev_priv->drrs.mutex);
5553 return;
5554 }
5555
a93fad0f
VK		 5556 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5557 pipe = to_intel_crtc(crtc)->pipe;
5558
c1d038c6
DV		 5559 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5560 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5561
0ddfd203 5562 /* invalidate means busy screen hence upclock */
c1d038c6 5563 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5564 intel_dp_set_drrs_state(dev_priv->dev,
5565 dev_priv->drrs.dp->attached_connector->panel.
5566 fixed_mode->vrefresh);
a93fad0f 5567
a93fad0f
VK		 5568 mutex_unlock(&dev_priv->drrs.mutex);
5569}
5570
b33a2815 5571/**
0ddfd203 5572 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5573 * @dev: DRM device
5574 * @frontbuffer_bits: frontbuffer plane tracking bits
5575 *
0ddfd203
R		 5576 * This function gets called every time rendering on the given planes has
5577 * completed or flip on a crtc is completed. So DRRS should be upclocked
5578 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5579 * if no other planes are dirty.
b33a2815
VK		 5580 *
5581 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5582 */
a93fad0f
VK		 5583void intel_edp_drrs_flush(struct drm_device *dev,
5584 unsigned frontbuffer_bits)
5585{
5586 struct drm_i915_private *dev_priv = dev->dev_private;
5587 struct drm_crtc *crtc;
5588 enum pipe pipe;
5589
9da7d693 5590 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5591 return;
5592
88f933a8 5593 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5594
a93fad0f 5595 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5596 if (!dev_priv->drrs.dp) {
5597 mutex_unlock(&dev_priv->drrs.mutex);
5598 return;
5599 }
5600
a93fad0f
VK		 5601 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5602 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5603
5604 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5605 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5606
0ddfd203 5607 /* flush means busy screen hence upclock */
c1d038c6 5608 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5609 intel_dp_set_drrs_state(dev_priv->dev,
5610 dev_priv->drrs.dp->attached_connector->panel.
5611 fixed_mode->vrefresh);
5612
5613 /*
5614 * flush also means no more activity hence schedule downclock, if all
5615 * other fbs are quiescent too
5616 */
5617 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5618 schedule_delayed_work(&dev_priv->drrs.work,
5619 msecs_to_jiffies(1000));
5620 mutex_unlock(&dev_priv->drrs.mutex);
5621}
5622
b33a2815
VK		 5623/**
5624 * DOC: Display Refresh Rate Switching (DRRS)
5625 *
5626 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5627 * which enables swtching between low and high refresh rates,
5628 * dynamically, based on the usage scenario. This feature is applicable
5629 * for internal panels.
5630 *
5631 * Indication that the panel supports DRRS is given by the panel EDID, which
5632 * would list multiple refresh rates for one resolution.
5633 *
5634 * DRRS is of 2 types - static and seamless.
5635 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5636 * (may appear as a blink on screen) and is used in dock-undock scenario.
5637 * Seamless DRRS involves changing RR without any visual effect to the user
5638 * and can be used during normal system usage. This is done by programming
5639 * certain registers.
5640 *
5641 * Support for static/seamless DRRS may be indicated in the VBT based on
5642 * inputs from the panel spec.
5643 *
5644 * DRRS saves power by switching to low RR based on usage scenarios.
5645 *
5646 * eDP DRRS:-
5647 * The implementation is based on frontbuffer tracking implementation.
5648 * When there is a disturbance on the screen triggered by user activity or a
5649 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5650 * When there is no movement on screen, after a timeout of 1 second, a switch
5651 * to low RR is made.
5652 * For integration with frontbuffer tracking code,
5653 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5654 *
5655 * DRRS can be further extended to support other internal panels and also
5656 * the scenario of video playback wherein RR is set based on the rate
5657 * requested by userspace.
5658 */
5659
5660/**
5661 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5662 * @intel_connector: eDP connector
5663 * @fixed_mode: preferred mode of panel
5664 *
5665 * This function is called only once at driver load to initialize basic
5666 * DRRS stuff.
5667 *
5668 * Returns:
5669 * Downclock mode if panel supports it, else return NULL.
5670 * DRRS support is determined by the presence of downclock mode (apart
5671 * from VBT setting).
5672 */
4f9db5b5 5673static struct drm_display_mode *
96178eeb
VK		 5674intel_dp_drrs_init(struct intel_connector *intel_connector,
5675 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5676{
5677 struct drm_connector *connector = &intel_connector->base;
96178eeb 5678 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5679 struct drm_i915_private *dev_priv = dev->dev_private;
5680 struct drm_display_mode *downclock_mode = NULL;
5681
9da7d693
DV		 5682 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5683 mutex_init(&dev_priv->drrs.mutex);
5684
4f9db5b5
PB		 5685 if (INTEL_INFO(dev)->gen <= 6) {
5686 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5687 return NULL;
5688 }
5689
5690 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5691 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5692 return NULL;
5693 }
5694
5695 downclock_mode = intel_find_panel_downclock
5696 (dev, fixed_mode, connector);
5697
5698 if (!downclock_mode) {
a1d26342 5699 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5700 return NULL;
5701 }
5702
96178eeb 5703 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5704
96178eeb 5705 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5706 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5707 return downclock_mode;
5708}
5709
ed92f0b2 5710static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5711 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5712{
5713 struct drm_connector *connector = &intel_connector->base;
5714 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5715 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5716 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5717 struct drm_i915_private *dev_priv = dev->dev_private;
5718 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5719 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5720 bool has_dpcd;
5721 struct drm_display_mode *scan;
5722 struct edid *edid;
6517d273 5723 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5724
5725 if (!is_edp(intel_dp))
5726 return true;
5727
49e6bc51
VS		 5728 pps_lock(intel_dp);
5729 intel_edp_panel_vdd_sanitize(intel_dp);
5730 pps_unlock(intel_dp);
63635217 5731
ed92f0b2 5732 /* Cache DPCD and EDID for edp. */
ed92f0b2 5733 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5734
5735 if (has_dpcd) {
5736 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5737 dev_priv->no_aux_handshake =
5738 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5739 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5740 } else {
5741 /* if this fails, presume the device is a ghost */
5742 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5743 return false;
5744 }
5745
5746 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5747 pps_lock(intel_dp);
36b5f425 5748 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5749 pps_unlock(intel_dp);
ed92f0b2 5750
060c8778 5751 mutex_lock(&dev->mode_config.mutex);
0b99836f 5752 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5753 if (edid) {
5754 if (drm_add_edid_modes(connector, edid)) {
5755 drm_mode_connector_update_edid_property(connector,
5756 edid);
5757 drm_edid_to_eld(connector, edid);
5758 } else {
5759 kfree(edid);
5760 edid = ERR_PTR(-EINVAL);
5761 }
5762 } else {
5763 edid = ERR_PTR(-ENOENT);
5764 }
5765 intel_connector->edid = edid;
5766
5767 /* prefer fixed mode from EDID if available */
5768 list_for_each_entry(scan, &connector->probed_modes, head) {
5769 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5770 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5771 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5772 intel_connector, fixed_mode);
ed92f0b2
PZ		 5773 break;
5774 }
5775 }
5776
5777 /* fallback to VBT if available for eDP */
5778 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5779 fixed_mode = drm_mode_duplicate(dev,
5780 dev_priv->vbt.lfp_lvds_vbt_mode);
5781 if (fixed_mode)
5782 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5783 }
060c8778 5784 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5785
01527b31
CT		 5786 if (IS_VALLEYVIEW(dev)) {
5787 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5788 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5789
5790 /*
5791 * Figure out the current pipe for the initial backlight setup.
5792 * If the current pipe isn't valid, try the PPS pipe, and if that
5793 * fails just assume pipe A.
5794 */
5795 if (IS_CHERRYVIEW(dev))
5796 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5797 else
5798 pipe = PORT_TO_PIPE(intel_dp->DP);
5799
5800 if (pipe != PIPE_A && pipe != PIPE_B)
5801 pipe = intel_dp->pps_pipe;
5802
5803 if (pipe != PIPE_A && pipe != PIPE_B)
5804 pipe = PIPE_A;
5805
5806 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5807 pipe_name(pipe));
01527b31
CT		 5808 }
5809
4f9db5b5 5810 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5811 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5812 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5813
5814 return true;
5815}
5816
16c25533 5817bool
f0fec3f2
PZ		 5818intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5819 struct intel_connector *intel_connector)
a4fc5ed6 5820{
f0fec3f2
PZ		 5821 struct drm_connector *connector = &intel_connector->base;
5822 struct intel_dp *intel_dp = &intel_dig_port->dp;
5823 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5824 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5825 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5826 enum port port = intel_dig_port->port;
0b99836f 5827 int type;
a4fc5ed6 5828
a4a5d2f8
VS		 5829 intel_dp->pps_pipe = INVALID_PIPE;
5830
ec5b01dd 5831 /* intel_dp vfuncs */
b6b5e383
DL		 5832 if (INTEL_INFO(dev)->gen >= 9)
5833 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5834 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5835 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5836 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5837 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5838 else if (HAS_PCH_SPLIT(dev))
5839 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5840 else
5841 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5842
b9ca5fad
DL		 5843 if (INTEL_INFO(dev)->gen >= 9)
5844 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5845 else
5846 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5847
0767935e
DV		 5848 /* Preserve the current hw state. */
5849 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5850 intel_dp->attached_connector = intel_connector;
3d3dc149 5851
3b32a35b 5852 if (intel_dp_is_edp(dev, port))
b329530c 5853 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5854 else
5855 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5856
f7d24902
ID		 5857 /*
5858 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5859 * for DP the encoder type can be set by the caller to
5860 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5861 */
5862 if (type == DRM_MODE_CONNECTOR_eDP)
5863 intel_encoder->type = INTEL_OUTPUT_EDP;
5864
c17ed5b5
VS		 5865 /* eDP only on port B and/or C on vlv/chv */
5866 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5867 port != PORT_B && port != PORT_C))
5868 return false;
5869
e7281eab
ID		 5870 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5871 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5872 port_name(port));
5873
b329530c 5874 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5875 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5876
a4fc5ed6
KP		 5877 connector->interlace_allowed = true;
5878 connector->doublescan_allowed = 0;
5879
f0fec3f2 5880 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5881 edp_panel_vdd_work);
a4fc5ed6 5882
df0e9248 5883 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5884 drm_connector_register(connector);
a4fc5ed6 5885
affa9354 5886 if (HAS_DDI(dev))
bcbc889b
PZ		 5887 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5888 else
5889 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5890 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5891
0b99836f 5892 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5893 switch (port) {
5894 case PORT_A:
1d843f9d 5895 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5896 break;
5897 case PORT_B:
1d843f9d 5898 intel_encoder->hpd_pin = HPD_PORT_B;
cf1d5883
SJ		 5899 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
5900 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5901 break;
5902 case PORT_C:
1d843f9d 5903 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5904 break;
5905 case PORT_D:
1d843f9d 5906 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5907 break;
5908 default:
ad1c0b19 5909 BUG();
5eb08b69
ZW		 5910 }
5911
dada1a9f 5912 if (is_edp(intel_dp)) {
773538e8 5913 pps_lock(intel_dp);
1e74a324
VS		 5914 intel_dp_init_panel_power_timestamps(intel_dp);
5915 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5916 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5917 else
36b5f425 5918 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5919 pps_unlock(intel_dp);
dada1a9f 5920 }
0095e6dc 5921
9d1a1031 5922 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5923
0e32b39c 5924 /* init MST on ports that can support it */
0c9b3715
JN		 5925 if (HAS_DP_MST(dev) &&
5926 (port == PORT_B || port == PORT_C || port == PORT_D))
5927 intel_dp_mst_encoder_init(intel_dig_port,
5928 intel_connector->base.base.id);
0e32b39c 5929
36b5f425 5930 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5931 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5932 if (is_edp(intel_dp)) {
5933 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5934 /*
5935 * vdd might still be enabled do to the delayed vdd off.
5936 * Make sure vdd is actually turned off here.
5937 */
773538e8 5938 pps_lock(intel_dp);
4be73780 5939 edp_panel_vdd_off_sync(intel_dp);
773538e8 5940 pps_unlock(intel_dp);
15b1d171 5941 }
34ea3d38 5942 drm_connector_unregister(connector);
b2f246a8 5943 drm_connector_cleanup(connector);
16c25533 5944 return false;
b2f246a8 5945 }
32f9d658 5946
f684960e
CW		 5947 intel_dp_add_properties(intel_dp, connector);
5948
a4fc5ed6
KP		 5949 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5950 * 0xd. Failure to do so will result in spurious interrupts being
5951 * generated on the port when a cable is not attached.
5952 */
5953 if (IS_G4X(dev) && !IS_GM45(dev)) {
5954 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5955 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5956 }
16c25533 5957
aa7471d2
JN		 5958 i915_debugfs_connector_add(connector);
5959
16c25533 5960 return true;
a4fc5ed6 5961}
f0fec3f2
PZ		 5962
5963void
5964intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5965{
13cf5504 5966 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5967 struct intel_digital_port *intel_dig_port;
5968 struct intel_encoder *intel_encoder;
5969 struct drm_encoder *encoder;
5970 struct intel_connector *intel_connector;
5971
b14c5679 5972 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5973 if (!intel_dig_port)
5974 return;
5975
08d9bc92 5976 intel_connector = intel_connector_alloc();
f0fec3f2
PZ		 5977 if (!intel_connector) {
5978 kfree(intel_dig_port);
5979 return;
5980 }
5981
5982 intel_encoder = &intel_dig_port->base;
5983 encoder = &intel_encoder->base;
5984
5985 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5986 DRM_MODE_ENCODER_TMDS);
5987
5bfe2ac0 5988 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5989 intel_encoder->disable = intel_disable_dp;
00c09d70 5990 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5991 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5992 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5993 if (IS_CHERRYVIEW(dev)) {
9197c88b 5994 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5995 intel_encoder->pre_enable = chv_pre_enable_dp;
5996 intel_encoder->enable = vlv_enable_dp;
580d3811 5997 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5998 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5999 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 6000 intel_encoder->pre_enable = vlv_pre_enable_dp;
6001 intel_encoder->enable = vlv_enable_dp;
49277c31 6002 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 6003 } else {
ecff4f3b
JN		 6004 intel_encoder->pre_enable = g4x_pre_enable_dp;
6005 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 6006 if (INTEL_INFO(dev)->gen >= 5)
6007 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 6008 }
f0fec3f2 6009
174edf1f 6010 intel_dig_port->port = port;
f0fec3f2
PZ		 6011 intel_dig_port->dp.output_reg = output_reg;
6012
00c09d70 6013 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 6014 if (IS_CHERRYVIEW(dev)) {
6015 if (port == PORT_D)
6016 intel_encoder->crtc_mask = 1 << 2;
6017 else
6018 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6019 } else {
6020 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6021 }
bc079e8b 6022 intel_encoder->cloneable = 0;
f0fec3f2 6023
13cf5504 6024 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 6025 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 6026
15b1d171
PZ		 6027 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
6028 drm_encoder_cleanup(encoder);
6029 kfree(intel_dig_port);
b2f246a8 6030 kfree(intel_connector);
15b1d171 6031 }
f0fec3f2 6032}
0e32b39c
DA		 6033
6034void intel_dp_mst_suspend(struct drm_device *dev)
6035{
6036 struct drm_i915_private *dev_priv = dev->dev_private;
6037 int i;
6038
6039 /* disable MST */
6040 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6041 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6042 if (!intel_dig_port)
6043 continue;
6044
6045 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6046 if (!intel_dig_port->dp.can_mst)
6047 continue;
6048 if (intel_dig_port->dp.is_mst)
6049 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6050 }
6051 }
6052}
6053
6054void intel_dp_mst_resume(struct drm_device *dev)
6055{
6056 struct drm_i915_private *dev_priv = dev->dev_private;
6057 int i;
6058
6059 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6060 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6061 if (!intel_dig_port)
6062 continue;
6063 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6064 int ret;
6065
6066 if (!intel_dig_port->dp.can_mst)
6067 continue;
6068
6069 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6070 if (ret != 0) {
6071 intel_dp_check_mst_status(&intel_dig_port->dp);
6072 }
6073 }
6074 }
6075}
Linux kernel - Deliverables
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