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drm/i915/dp: fix up VLV DP handling v2
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
cd9dde44
AJ		 151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
a4fc5ed6 168static int
c898261c 169intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 170{
cd9dde44 171 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 172}
173
fe27d53e
DA		 174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
a4fc5ed6
KP		 180static int
181intel_dp_mode_valid(struct drm_connector *connector,
182 struct drm_display_mode *mode)
183{
df0e9248 184 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 185 struct intel_connector *intel_connector = to_intel_connector(connector);
186 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 187 int target_clock = mode->clock;
188 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 189
dd06f90e
JN		 190 if (is_edp(intel_dp) && fixed_mode) {
191 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 192 return MODE_PANEL;
193
dd06f90e 194 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 195 return MODE_PANEL;
196 }
197
36008365
DV		 198 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
199 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
200
201 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
202 mode_rate = intel_dp_link_required(target_clock, 18);
203
204 if (mode_rate > max_rate)
c4867936 205 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 206
207 if (mode->clock < 10000)
208 return MODE_CLOCK_LOW;
209
0af78a2b
DV		 210 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
211 return MODE_H_ILLEGAL;
212
a4fc5ed6
KP		 213 return MODE_OK;
214}
215
216static uint32_t
217pack_aux(uint8_t *src, int src_bytes)
218{
219 int i;
220 uint32_t v = 0;
221
222 if (src_bytes > 4)
223 src_bytes = 4;
224 for (i = 0; i < src_bytes; i++)
225 v |= ((uint32_t) src[i]) << ((3-i) * 8);
226 return v;
227}
228
229static void
230unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
231{
232 int i;
233 if (dst_bytes > 4)
234 dst_bytes = 4;
235 for (i = 0; i < dst_bytes; i++)
236 dst[i] = src >> ((3-i) * 8);
237}
238
fb0f8fbf
KP		 239/* hrawclock is 1/4 the FSB frequency */
240static int
241intel_hrawclk(struct drm_device *dev)
242{
243 struct drm_i915_private *dev_priv = dev->dev_private;
244 uint32_t clkcfg;
245
9473c8f4
VP		 246 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
247 if (IS_VALLEYVIEW(dev))
248 return 200;
249
fb0f8fbf
KP		 250 clkcfg = I915_READ(CLKCFG);
251 switch (clkcfg & CLKCFG_FSB_MASK) {
252 case CLKCFG_FSB_400:
253 return 100;
254 case CLKCFG_FSB_533:
255 return 133;
256 case CLKCFG_FSB_667:
257 return 166;
258 case CLKCFG_FSB_800:
259 return 200;
260 case CLKCFG_FSB_1067:
261 return 266;
262 case CLKCFG_FSB_1333:
263 return 333;
264 /* these two are just a guess; one of them might be right */
265 case CLKCFG_FSB_1600:
266 case CLKCFG_FSB_1600_ALT:
267 return 400;
268 default:
269 return 133;
270 }
271}
272
ebf33b18
KP		 273static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
274{
30add22d 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 276 struct drm_i915_private *dev_priv = dev->dev_private;
277
278 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
279}
280
281static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
282{
30add22d 283 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 284 struct drm_i915_private *dev_priv = dev->dev_private;
285
286 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
287}
288
9b984dae
KP		 289static void
290intel_dp_check_edp(struct intel_dp *intel_dp)
291{
30add22d 292 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 293 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 294
9b984dae
KP		 295 if (!is_edp(intel_dp))
296 return;
ebf33b18 297 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 298 WARN(1, "eDP powered off while attempting aux channel communication.\n");
299 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 300 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 301 I915_READ(PCH_PP_CONTROL));
302 }
303}
304
9ee32fea
DV		 305static uint32_t
306intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
307{
308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
309 struct drm_device *dev = intel_dig_port->base.base.dev;
310 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 311 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 312 uint32_t status;
313 bool done;
314
ef04f00d 315#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 316 if (has_aux_irq)
b90f5176
PZ		 317 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
318 msecs_to_jiffies(10));
9ee32fea
DV		 319 else
320 done = wait_for_atomic(C, 10) == 0;
321 if (!done)
322 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
323 has_aux_irq);
324#undef C
325
326 return status;
327}
328
a4fc5ed6 329static int
ea5b213a 330intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 331 uint8_t *send, int send_bytes,
332 uint8_t *recv, int recv_size)
333{
174edf1f
PZ		 334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 336 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 337 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 338 uint32_t ch_data = ch_ctl + 4;
9ee32fea 339 int i, ret, recv_bytes;
a4fc5ed6 340 uint32_t status;
fb0f8fbf 341 uint32_t aux_clock_divider;
6b4e0a93 342 int try, precharge;
9ee32fea
DV		 343 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
344
345 /* dp aux is extremely sensitive to irq latency, hence request the
346 * lowest possible wakeup latency and so prevent the cpu from going into
347 * deep sleep states.
348 */
349 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 350
9b984dae 351 intel_dp_check_edp(intel_dp);
a4fc5ed6 352 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 353 * and would like to run at 2MHz. So, take the
354 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 355 *
356 * Note that PCH attached eDP panels should use a 125MHz input
357 * clock divider.
a4fc5ed6 358 */
1c95822a 359 if (is_cpu_edp(intel_dp)) {
affa9354 360 if (HAS_DDI(dev))
b8fc2f6a
PZ		 361 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
362 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 363 aux_clock_divider = 100;
364 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 365 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 366 else
367 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
368 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 369 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 370 else
371 aux_clock_divider = intel_hrawclk(dev) / 2;
372
6b4e0a93
DV		 373 if (IS_GEN6(dev))
374 precharge = 3;
375 else
376 precharge = 5;
377
11bee43e
JB		 378 /* Try to wait for any previous AUX channel activity */
379 for (try = 0; try < 3; try++) {
ef04f00d 380 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 381 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
382 break;
383 msleep(1);
384 }
385
386 if (try == 3) {
387 WARN(1, "dp_aux_ch not started status 0x%08x\n",
388 I915_READ(ch_ctl));
9ee32fea
DV		 389 ret = -EBUSY;
390 goto out;
4f7f7b7e
CW		 391 }
392
fb0f8fbf
KP		 393 /* Must try at least 3 times according to DP spec */
394 for (try = 0; try < 5; try++) {
395 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 396 for (i = 0; i < send_bytes; i += 4)
397 I915_WRITE(ch_data + i,
398 pack_aux(send + i, send_bytes - i));
0206e353 399
fb0f8fbf 400 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 401 I915_WRITE(ch_ctl,
402 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 403 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 404 DP_AUX_CH_CTL_TIME_OUT_400us |
405 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
406 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
407 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
408 DP_AUX_CH_CTL_DONE |
409 DP_AUX_CH_CTL_TIME_OUT_ERROR |
410 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 411
412 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 413
fb0f8fbf 414 /* Clear done status and any errors */
4f7f7b7e
CW		 415 I915_WRITE(ch_ctl,
416 status |
417 DP_AUX_CH_CTL_DONE |
418 DP_AUX_CH_CTL_TIME_OUT_ERROR |
419 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 420
421 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
422 DP_AUX_CH_CTL_RECEIVE_ERROR))
423 continue;
4f7f7b7e 424 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 425 break;
426 }
427
a4fc5ed6 428 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 429 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 430 ret = -EBUSY;
431 goto out;
a4fc5ed6
KP		 432 }
433
434 /* Check for timeout or receive error.
435 * Timeouts occur when the sink is not connected
436 */
a5b3da54 437 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 438 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 439 ret = -EIO;
440 goto out;
a5b3da54 441 }
1ae8c0a5
KP		 442
443 /* Timeouts occur when the device isn't connected, so they're
444 * "normal" -- don't fill the kernel log with these */
a5b3da54 445 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 446 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 447 ret = -ETIMEDOUT;
448 goto out;
a4fc5ed6
KP		 449 }
450
451 /* Unload any bytes sent back from the other side */
452 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
453 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 454 if (recv_bytes > recv_size)
455 recv_bytes = recv_size;
0206e353 456
4f7f7b7e
CW		 457 for (i = 0; i < recv_bytes; i += 4)
458 unpack_aux(I915_READ(ch_data + i),
459 recv + i, recv_bytes - i);
a4fc5ed6 460
9ee32fea
DV		 461 ret = recv_bytes;
462out:
463 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
464
465 return ret;
a4fc5ed6
KP		 466}
467
468/* Write data to the aux channel in native mode */
469static int
ea5b213a 470intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 471 uint16_t address, uint8_t *send, int send_bytes)
472{
473 int ret;
474 uint8_t msg[20];
475 int msg_bytes;
476 uint8_t ack;
477
9b984dae 478 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 479 if (send_bytes > 16)
480 return -1;
481 msg[0] = AUX_NATIVE_WRITE << 4;
482 msg[1] = address >> 8;
eebc863e 483 msg[2] = address & 0xff;
a4fc5ed6
KP		 484 msg[3] = send_bytes - 1;
485 memcpy(&msg[4], send, send_bytes);
486 msg_bytes = send_bytes + 4;
487 for (;;) {
ea5b213a 488 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 489 if (ret < 0)
490 return ret;
491 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
492 break;
493 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
494 udelay(100);
495 else
a5b3da54 496 return -EIO;
a4fc5ed6
KP		 497 }
498 return send_bytes;
499}
500
501/* Write a single byte to the aux channel in native mode */
502static int
ea5b213a 503intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 504 uint16_t address, uint8_t byte)
505{
ea5b213a 506 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 507}
508
509/* read bytes from a native aux channel */
510static int
ea5b213a 511intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 512 uint16_t address, uint8_t *recv, int recv_bytes)
513{
514 uint8_t msg[4];
515 int msg_bytes;
516 uint8_t reply[20];
517 int reply_bytes;
518 uint8_t ack;
519 int ret;
520
9b984dae 521 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 522 msg[0] = AUX_NATIVE_READ << 4;
523 msg[1] = address >> 8;
524 msg[2] = address & 0xff;
525 msg[3] = recv_bytes - 1;
526
527 msg_bytes = 4;
528 reply_bytes = recv_bytes + 1;
529
530 for (;;) {
ea5b213a 531 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 532 reply, reply_bytes);
a5b3da54
KP		 533 if (ret == 0)
534 return -EPROTO;
535 if (ret < 0)
a4fc5ed6
KP		 536 return ret;
537 ack = reply[0];
538 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
539 memcpy(recv, reply + 1, ret - 1);
540 return ret - 1;
541 }
542 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
543 udelay(100);
544 else
a5b3da54 545 return -EIO;
a4fc5ed6
KP		 546 }
547}
548
549static int
ab2c0672
DA		 550intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
551 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 552{
ab2c0672 553 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 554 struct intel_dp *intel_dp = container_of(adapter,
555 struct intel_dp,
556 adapter);
ab2c0672
DA		 557 uint16_t address = algo_data->address;
558 uint8_t msg[5];
559 uint8_t reply[2];
8316f337 560 unsigned retry;
ab2c0672
DA		 561 int msg_bytes;
562 int reply_bytes;
563 int ret;
564
9b984dae 565 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 566 /* Set up the command byte */
567 if (mode & MODE_I2C_READ)
568 msg[0] = AUX_I2C_READ << 4;
569 else
570 msg[0] = AUX_I2C_WRITE << 4;
571
572 if (!(mode & MODE_I2C_STOP))
573 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 574
ab2c0672
DA		 575 msg[1] = address >> 8;
576 msg[2] = address;
577
578 switch (mode) {
579 case MODE_I2C_WRITE:
580 msg[3] = 0;
581 msg[4] = write_byte;
582 msg_bytes = 5;
583 reply_bytes = 1;
584 break;
585 case MODE_I2C_READ:
586 msg[3] = 0;
587 msg_bytes = 4;
588 reply_bytes = 2;
589 break;
590 default:
591 msg_bytes = 3;
592 reply_bytes = 1;
593 break;
594 }
595
8316f337
DF		 596 for (retry = 0; retry < 5; retry++) {
597 ret = intel_dp_aux_ch(intel_dp,
598 msg, msg_bytes,
599 reply, reply_bytes);
ab2c0672 600 if (ret < 0) {
3ff99164 601 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 602 return ret;
603 }
8316f337
DF		 604
605 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
606 case AUX_NATIVE_REPLY_ACK:
607 /* I2C-over-AUX Reply field is only valid
608 * when paired with AUX ACK.
609 */
610 break;
611 case AUX_NATIVE_REPLY_NACK:
612 DRM_DEBUG_KMS("aux_ch native nack\n");
613 return -EREMOTEIO;
614 case AUX_NATIVE_REPLY_DEFER:
615 udelay(100);
616 continue;
617 default:
618 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
619 reply[0]);
620 return -EREMOTEIO;
621 }
622
ab2c0672
DA		 623 switch (reply[0] & AUX_I2C_REPLY_MASK) {
624 case AUX_I2C_REPLY_ACK:
625 if (mode == MODE_I2C_READ) {
626 *read_byte = reply[1];
627 }
628 return reply_bytes - 1;
629 case AUX_I2C_REPLY_NACK:
8316f337 630 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 631 return -EREMOTEIO;
632 case AUX_I2C_REPLY_DEFER:
8316f337 633 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 634 udelay(100);
635 break;
636 default:
8316f337 637 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 638 return -EREMOTEIO;
639 }
640 }
8316f337
DF		 641
642 DRM_ERROR("too many retries, giving up\n");
643 return -EREMOTEIO;
a4fc5ed6
KP		 644}
645
646static int
ea5b213a 647intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 648 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 649{
0b5c541b
KP		 650 int ret;
651
d54e9d28 652 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 653 intel_dp->algo.running = false;
654 intel_dp->algo.address = 0;
655 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
656
0206e353 657 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 658 intel_dp->adapter.owner = THIS_MODULE;
659 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 660 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 661 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
662 intel_dp->adapter.algo_data = &intel_dp->algo;
663 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
664
0b5c541b
KP		 665 ironlake_edp_panel_vdd_on(intel_dp);
666 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 667 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 668 return ret;
a4fc5ed6
KP		 669}
670
00c09d70 671bool
5bfe2ac0
DV		 672intel_dp_compute_config(struct intel_encoder *encoder,
673 struct intel_crtc_config *pipe_config)
a4fc5ed6 674{
5bfe2ac0 675 struct drm_device *dev = encoder->base.dev;
36008365 676 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0
DV		 677 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
678 struct drm_display_mode *mode = &pipe_config->requested_mode;
679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
dd06f90e 680 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 681 int lane_count, clock;
397fe157 682 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 683 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 684 int bpp, mode_rate;
a4fc5ed6 685 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 686 int target_clock, link_avail, link_clock;
a4fc5ed6 687
5bfe2ac0
DV		 688 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
689 pipe_config->has_pch_encoder = true;
690
dd06f90e
JN		 691 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
692 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
693 adjusted_mode);
53b41837
YN		 694 intel_pch_panel_fitting(dev,
695 intel_connector->panel.fitting_mode,
1d8e1c75 696 mode, adjusted_mode);
0d3a1bee 697 }
36008365
DV		 698 /* We need to take the panel's fixed mode into account. */
699 target_clock = adjusted_mode->clock;
0d3a1bee 700
cb1793ce 701 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 702 return false;
703
083f9560
DV		 704 DRM_DEBUG_KMS("DP link computation with max lane count %i "
705 "max bw %02x pixel clock %iKHz\n",
71244653 706 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 707
36008365
DV		 708 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
709 * bpc in between. */
710 bpp = 8*3;
711 if (is_edp(intel_dp) && dev_priv->edp.bpp)
712 bpp = min_t(int, bpp, dev_priv->edp.bpp);
713
714 for (; bpp >= 6*3; bpp -= 2*3) {
715 mode_rate = intel_dp_link_required(target_clock, bpp);
716
717 for (clock = 0; clock <= max_clock; clock++) {
718 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
719 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
720 link_avail = intel_dp_max_data_rate(link_clock,
721 lane_count);
722
723 if (mode_rate <= link_avail) {
724 goto found;
725 }
726 }
727 }
728 }
c4867936 729
36008365 730 return false;
3685a8f3 731
36008365 732found:
55bc60db
VS		 733 if (intel_dp->color_range_auto) {
734 /*
735 * See:
736 * CEA-861-E - 5.1 Default Encoding Parameters
737 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
738 */
18316c8c 739 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 740 intel_dp->color_range = DP_COLOR_RANGE_16_235;
741 else
742 intel_dp->color_range = 0;
743 }
744
3685a8f3 745 if (intel_dp->color_range)
50f3b016 746 pipe_config->limited_color_range = true;
3685a8f3 747
36008365
DV		 748 intel_dp->link_bw = bws[clock];
749 intel_dp->lane_count = lane_count;
750 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
751 pipe_config->pipe_bpp = bpp;
fe27d53e 752
36008365
DV		 753 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
754 intel_dp->link_bw, intel_dp->lane_count,
755 adjusted_mode->clock, bpp);
756 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
757 mode_rate, link_avail);
758
759 return true;
a4fc5ed6
KP		 760}
761
a4fc5ed6
KP		 762void
763intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
764 struct drm_display_mode *adjusted_mode)
765{
766 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 767 struct intel_encoder *intel_encoder;
768 struct intel_dp *intel_dp;
a4fc5ed6
KP		 769 struct drm_i915_private *dev_priv = dev->dev_private;
770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 771 int lane_count = 4;
e69d0bc1 772 struct intel_link_m_n m_n;
9db4a9c7 773 int pipe = intel_crtc->pipe;
afe2fcf5 774 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 775
776 /*
21d40d37 777 * Find the lane count in the intel_encoder private
a4fc5ed6 778 */
fa90ecef
PZ		 779 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
780 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 781
fa90ecef
PZ		 782 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
783 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 784 {
ea5b213a 785 lane_count = intel_dp->lane_count;
51190667 786 break;
a4fc5ed6
KP		 787 }
788 }
789
790 /*
791 * Compute the GMCH and Link ratios. The '3' here is
792 * the number of bytes_per_pixel post-LUT, which we always
793 * set up for 8-bits of R/G/B, or 3 bytes total.
794 */
965e0c48 795 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane_count,
e69d0bc1 796 mode->clock, adjusted_mode->clock, &m_n);
a4fc5ed6 797
22b8bf17 798 if (HAS_DDI(dev)) {
afe2fcf5
PZ		 799 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
800 TU_SIZE(m_n.tu) | m_n.gmch_m);
801 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
802 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
803 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 804 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 805 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 806 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
807 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
808 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 809 } else if (IS_VALLEYVIEW(dev)) {
810 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
811 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
812 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
813 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 814 } else {
9db4a9c7 815 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 816 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 817 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
818 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
819 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 820 }
821}
822
247d89f6
PZ		 823void intel_dp_init_link_config(struct intel_dp *intel_dp)
824{
825 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
826 intel_dp->link_configuration[0] = intel_dp->link_bw;
827 intel_dp->link_configuration[1] = intel_dp->lane_count;
828 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
829 /*
830 * Check for DPCD version > 1.1 and enhanced framing support
831 */
832 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
833 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
834 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
835 }
836}
837
ea9b6006
DV		 838static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
839{
840 struct drm_device *dev = crtc->dev;
841 struct drm_i915_private *dev_priv = dev->dev_private;
842 u32 dpa_ctl;
843
844 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
845 dpa_ctl = I915_READ(DP_A);
846 dpa_ctl &= ~DP_PLL_FREQ_MASK;
847
848 if (clock < 200000) {
1ce17038
DV		 849 /* For a long time we've carried around a ILK-DevA w/a for the
850 * 160MHz clock. If we're really unlucky, it's still required.
851 */
852 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 853 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 854 } else {
855 dpa_ctl |= DP_PLL_FREQ_270MHZ;
856 }
1ce17038 857
ea9b6006
DV		 858 I915_WRITE(DP_A, dpa_ctl);
859
860 POSTING_READ(DP_A);
861 udelay(500);
862}
863
a4fc5ed6
KP		 864static void
865intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
866 struct drm_display_mode *adjusted_mode)
867{
e3421a18 868 struct drm_device *dev = encoder->dev;
417e822d 869 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 870 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 871 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 872 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
873
417e822d 874 /*
1a2eb460 875 * There are four kinds of DP registers:
417e822d
KP		 876 *
877 * IBX PCH
1a2eb460
KP		 878 * SNB CPU
879 * IVB CPU
417e822d
KP		 880 * CPT PCH
881 *
882 * IBX PCH and CPU are the same for almost everything,
883 * except that the CPU DP PLL is configured in this
884 * register
885 *
886 * CPT PCH is quite different, having many bits moved
887 * to the TRANS_DP_CTL register instead. That
888 * configuration happens (oddly) in ironlake_pch_enable
889 */
9c9e7927 890
417e822d
KP		 891 /* Preserve the BIOS-computed detected bit. This is
892 * supposed to be read-only.
893 */
894 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 895
417e822d 896 /* Handle DP bits in common between all three register formats */
417e822d 897 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 898
ea5b213a 899 switch (intel_dp->lane_count) {
a4fc5ed6 900 case 1:
ea5b213a 901 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 902 break;
903 case 2:
ea5b213a 904 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 905 break;
906 case 4:
ea5b213a 907 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 908 break;
909 }
e0dac65e
WF		 910 if (intel_dp->has_audio) {
911 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
912 pipe_name(intel_crtc->pipe));
ea5b213a 913 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 914 intel_write_eld(encoder, adjusted_mode);
915 }
247d89f6
PZ		 916
917 intel_dp_init_link_config(intel_dp);
a4fc5ed6 918
417e822d 919 /* Split out the IBX/CPU vs CPT settings */
32f9d658 920
19c03924 921 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 922 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
923 intel_dp->DP |= DP_SYNC_HS_HIGH;
924 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
925 intel_dp->DP |= DP_SYNC_VS_HIGH;
926 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
927
928 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
929 intel_dp->DP |= DP_ENHANCED_FRAMING;
930
931 intel_dp->DP |= intel_crtc->pipe << 29;
932
933 /* don't miss out required setting for eDP */
1a2eb460
KP		 934 if (adjusted_mode->clock < 200000)
935 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
936 else
937 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
938 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
b2634017 939 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 940 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 941
942 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
943 intel_dp->DP |= DP_SYNC_HS_HIGH;
944 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
945 intel_dp->DP |= DP_SYNC_VS_HIGH;
946 intel_dp->DP |= DP_LINK_TRAIN_OFF;
947
948 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
949 intel_dp->DP |= DP_ENHANCED_FRAMING;
950
951 if (intel_crtc->pipe == 1)
952 intel_dp->DP |= DP_PIPEB_SELECT;
953
b2634017 954 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
417e822d 955 /* don't miss out required setting for eDP */
417e822d
KP		 956 if (adjusted_mode->clock < 200000)
957 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
958 else
959 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
960 }
961 } else {
962 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 963 }
ea9b6006 964
5d66d5b6 965 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 966 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 967}
968
99ea7127
KP		 969#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
970#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
971
972#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
973#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
974
975#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
976#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
977
978static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
979 u32 mask,
980 u32 value)
bd943159 981{
30add22d 982 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 983 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 984
99ea7127
KP		 985 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
986 mask, value,
987 I915_READ(PCH_PP_STATUS),
988 I915_READ(PCH_PP_CONTROL));
32ce697c 989
99ea7127
KP		 990 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
991 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
992 I915_READ(PCH_PP_STATUS),
993 I915_READ(PCH_PP_CONTROL));
32ce697c 994 }
99ea7127 995}
32ce697c 996
99ea7127
KP		 997static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
998{
999 DRM_DEBUG_KMS("Wait for panel power on\n");
1000 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1001}
1002
99ea7127
KP		 1003static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1004{
1005 DRM_DEBUG_KMS("Wait for panel power off time\n");
1006 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1007}
1008
1009static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1010{
1011 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1012 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1013}
1014
1015
832dd3c1
KP		 1016/* Read the current pp_control value, unlocking the register if it
1017 * is locked
1018 */
1019
1020static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1021{
1022 u32 control = I915_READ(PCH_PP_CONTROL);
1023
1024 control &= ~PANEL_UNLOCK_MASK;
1025 control |= PANEL_UNLOCK_REGS;
1026 return control;
bd943159
KP		 1027}
1028
82a4d9c0 1029void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1030{
30add22d 1031 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1032 struct drm_i915_private *dev_priv = dev->dev_private;
1033 u32 pp;
1034
97af61f5
KP		 1035 if (!is_edp(intel_dp))
1036 return;
f01eca2e 1037 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1038
bd943159
KP		 1039 WARN(intel_dp->want_panel_vdd,
1040 "eDP VDD already requested on\n");
1041
1042 intel_dp->want_panel_vdd = true;
99ea7127 1043
bd943159
KP		 1044 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1045 DRM_DEBUG_KMS("eDP VDD already on\n");
1046 return;
1047 }
1048
99ea7127
KP		 1049 if (!ironlake_edp_have_panel_power(intel_dp))
1050 ironlake_wait_panel_power_cycle(intel_dp);
1051
832dd3c1 1052 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1053 pp |= EDP_FORCE_VDD;
1054 I915_WRITE(PCH_PP_CONTROL, pp);
1055 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1056 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1057 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1058
1059 /*
1060 * If the panel wasn't on, delay before accessing aux channel
1061 */
1062 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1063 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1064 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1065 }
5d613501
JB		 1066}
1067
bd943159 1068static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1069{
30add22d 1070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1071 struct drm_i915_private *dev_priv = dev->dev_private;
1072 u32 pp;
1073
a0e99e68
DV		 1074 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1075
bd943159 1076 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1077 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1078 pp &= ~EDP_FORCE_VDD;
1079 I915_WRITE(PCH_PP_CONTROL, pp);
1080 POSTING_READ(PCH_PP_CONTROL);
1081
1082 /* Make sure sequencer is idle before allowing subsequent activity */
1083 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1084 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1085
1086 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1087 }
1088}
5d613501 1089
bd943159
KP		 1090static void ironlake_panel_vdd_work(struct work_struct *__work)
1091{
1092 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1093 struct intel_dp, panel_vdd_work);
30add22d 1094 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1095
627f7675 1096 mutex_lock(&dev->mode_config.mutex);
bd943159 1097 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1098 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1099}
1100
82a4d9c0 1101void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1102{
97af61f5
KP		 1103 if (!is_edp(intel_dp))
1104 return;
5d613501 1105
bd943159
KP		 1106 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1107 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1108
bd943159
KP		 1109 intel_dp->want_panel_vdd = false;
1110
1111 if (sync) {
1112 ironlake_panel_vdd_off_sync(intel_dp);
1113 } else {
1114 /*
1115 * Queue the timer to fire a long
1116 * time from now (relative to the power down delay)
1117 * to keep the panel power up across a sequence of operations
1118 */
1119 schedule_delayed_work(&intel_dp->panel_vdd_work,
1120 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1121 }
5d613501
JB		 1122}
1123
82a4d9c0 1124void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1125{
30add22d 1126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1127 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1128 u32 pp;
9934c132 1129
97af61f5 1130 if (!is_edp(intel_dp))
bd943159 1131 return;
99ea7127
KP		 1132
1133 DRM_DEBUG_KMS("Turn eDP power on\n");
1134
1135 if (ironlake_edp_have_panel_power(intel_dp)) {
1136 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1137 return;
99ea7127 1138 }
9934c132 1139
99ea7127 1140 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1141
99ea7127 1142 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1143 if (IS_GEN5(dev)) {
1144 /* ILK workaround: disable reset around power sequence */
1145 pp &= ~PANEL_POWER_RESET;
1146 I915_WRITE(PCH_PP_CONTROL, pp);
1147 POSTING_READ(PCH_PP_CONTROL);
1148 }
37c6c9b0 1149
1c0ae80a 1150 pp |= POWER_TARGET_ON;
99ea7127
KP		 1151 if (!IS_GEN5(dev))
1152 pp |= PANEL_POWER_RESET;
1153
9934c132 1154 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1155 POSTING_READ(PCH_PP_CONTROL);
9934c132 1156
99ea7127 1157 ironlake_wait_panel_on(intel_dp);
9934c132 1158
05ce1a49
KP		 1159 if (IS_GEN5(dev)) {
1160 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1161 I915_WRITE(PCH_PP_CONTROL, pp);
1162 POSTING_READ(PCH_PP_CONTROL);
1163 }
9934c132
JB		 1164}
1165
82a4d9c0 1166void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1167{
30add22d 1168 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1169 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1170 u32 pp;
9934c132 1171
97af61f5
KP		 1172 if (!is_edp(intel_dp))
1173 return;
37c6c9b0 1174
99ea7127 1175 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1176
6cb49835 1177 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1178
99ea7127 1179 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1180 /* We need to switch off panel power _and_ force vdd, for otherwise some
1181 * panels get very unhappy and cease to work. */
1182 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1183 I915_WRITE(PCH_PP_CONTROL, pp);
1184 POSTING_READ(PCH_PP_CONTROL);
9934c132 1185
35a38556
DV		 1186 intel_dp->want_panel_vdd = false;
1187
99ea7127 1188 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1189}
1190
d6c50ff8 1191void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1192{
da63a9f2
PZ		 1193 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1194 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1195 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1196 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1197 u32 pp;
1198
f01eca2e
KP		 1199 if (!is_edp(intel_dp))
1200 return;
1201
28c97730 1202 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1203 /*
1204 * If we enable the backlight right away following a panel power
1205 * on, we may see slight flicker as the panel syncs with the eDP
1206 * link. So delay a bit to make sure the image is solid before
1207 * allowing it to appear.
1208 */
f01eca2e 1209 msleep(intel_dp->backlight_on_delay);
832dd3c1 1210 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1211 pp |= EDP_BLC_ENABLE;
1212 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1213 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1214
1215 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1216}
1217
d6c50ff8 1218void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1219{
30add22d 1220 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1221 struct drm_i915_private *dev_priv = dev->dev_private;
1222 u32 pp;
1223
f01eca2e
KP		 1224 if (!is_edp(intel_dp))
1225 return;
1226
035aa3de
DV		 1227 intel_panel_disable_backlight(dev);
1228
28c97730 1229 DRM_DEBUG_KMS("\n");
832dd3c1 1230 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1231 pp &= ~EDP_BLC_ENABLE;
1232 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1233 POSTING_READ(PCH_PP_CONTROL);
1234 msleep(intel_dp->backlight_off_delay);
32f9d658 1235}
a4fc5ed6 1236
2bd2ad64 1237static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1238{
da63a9f2
PZ		 1239 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1240 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1241 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 u32 dpa_ctl;
1244
2bd2ad64
DV		 1245 assert_pipe_disabled(dev_priv,
1246 to_intel_crtc(crtc)->pipe);
1247
d240f20f
JB		 1248 DRM_DEBUG_KMS("\n");
1249 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1250 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1251 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1252
1253 /* We don't adjust intel_dp->DP while tearing down the link, to
1254 * facilitate link retraining (e.g. after hotplug). Hence clear all
1255 * enable bits here to ensure that we don't enable too much. */
1256 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1257 intel_dp->DP |= DP_PLL_ENABLE;
1258 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1259 POSTING_READ(DP_A);
1260 udelay(200);
d240f20f
JB		 1261}
1262
2bd2ad64 1263static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1264{
da63a9f2
PZ		 1265 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1266 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1267 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1268 struct drm_i915_private *dev_priv = dev->dev_private;
1269 u32 dpa_ctl;
1270
2bd2ad64
DV		 1271 assert_pipe_disabled(dev_priv,
1272 to_intel_crtc(crtc)->pipe);
1273
d240f20f 1274 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1275 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1276 "dp pll off, should be on\n");
1277 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1278
1279 /* We can't rely on the value tracked for the DP register in
1280 * intel_dp->DP because link_down must not change that (otherwise link
1281 * re-training will fail. */
298b0b39 1282 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1283 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1284 POSTING_READ(DP_A);
d240f20f
JB		 1285 udelay(200);
1286}
1287
c7ad3810 1288/* If the sink supports it, try to set the power state appropriately */
c19b0669 1289void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1290{
1291 int ret, i;
1292
1293 /* Should have a valid DPCD by this point */
1294 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1295 return;
1296
1297 if (mode != DRM_MODE_DPMS_ON) {
1298 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1299 DP_SET_POWER_D3);
1300 if (ret != 1)
1301 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1302 } else {
1303 /*
1304 * When turning on, we need to retry for 1ms to give the sink
1305 * time to wake up.
1306 */
1307 for (i = 0; i < 3; i++) {
1308 ret = intel_dp_aux_native_write_1(intel_dp,
1309 DP_SET_POWER,
1310 DP_SET_POWER_D0);
1311 if (ret == 1)
1312 break;
1313 msleep(1);
1314 }
1315 }
1316}
1317
19d8fe15
DV		 1318static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1319 enum pipe *pipe)
d240f20f 1320{
19d8fe15
DV		 1321 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1322 struct drm_device *dev = encoder->base.dev;
1323 struct drm_i915_private *dev_priv = dev->dev_private;
1324 u32 tmp = I915_READ(intel_dp->output_reg);
1325
1326 if (!(tmp & DP_PORT_EN))
1327 return false;
1328
5d66d5b6 1329 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV		 1330 *pipe = PORT_TO_PIPE_CPT(tmp);
1331 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1332 *pipe = PORT_TO_PIPE(tmp);
1333 } else {
1334 u32 trans_sel;
1335 u32 trans_dp;
1336 int i;
1337
1338 switch (intel_dp->output_reg) {
1339 case PCH_DP_B:
1340 trans_sel = TRANS_DP_PORT_SEL_B;
1341 break;
1342 case PCH_DP_C:
1343 trans_sel = TRANS_DP_PORT_SEL_C;
1344 break;
1345 case PCH_DP_D:
1346 trans_sel = TRANS_DP_PORT_SEL_D;
1347 break;
1348 default:
1349 return true;
1350 }
1351
1352 for_each_pipe(i) {
1353 trans_dp = I915_READ(TRANS_DP_CTL(i));
1354 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1355 *pipe = i;
1356 return true;
1357 }
1358 }
19d8fe15 1359
4a0833ec
DV		 1360 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1361 intel_dp->output_reg);
1362 }
d240f20f 1363
deb18211 1364 return false;
19d8fe15 1365}
d240f20f 1366
e8cb4558 1367static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1368{
e8cb4558 1369 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1370
1371 /* Make sure the panel is off before trying to change the mode. But also
1372 * ensure that we have vdd while we switch off the panel. */
1373 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1374 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1375 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1376 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1377
1378 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1379 if (!is_cpu_edp(intel_dp))
1380 intel_dp_link_down(intel_dp);
d240f20f
JB		 1381}
1382
2bd2ad64 1383static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1384{
2bd2ad64 1385 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1386 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1387
3739850b
DV		 1388 if (is_cpu_edp(intel_dp)) {
1389 intel_dp_link_down(intel_dp);
b2634017
JB		 1390 if (!IS_VALLEYVIEW(dev))
1391 ironlake_edp_pll_off(intel_dp);
3739850b 1392 }
2bd2ad64
DV		 1393}
1394
e8cb4558 1395static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1396{
e8cb4558
DV		 1397 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1398 struct drm_device *dev = encoder->base.dev;
1399 struct drm_i915_private *dev_priv = dev->dev_private;
1400 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1401
0c33d8d7
DV		 1402 if (WARN_ON(dp_reg & DP_PORT_EN))
1403 return;
5d613501 1404
97af61f5 1405 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1406 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1407 intel_dp_start_link_train(intel_dp);
97af61f5 1408 ironlake_edp_panel_on(intel_dp);
bd943159 1409 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1410 intel_dp_complete_link_train(intel_dp);
f01eca2e 1411 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1412}
1413
2bd2ad64 1414static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1415{
2bd2ad64 1416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1417 struct drm_device *dev = encoder->base.dev;
a4fc5ed6 1418
b2634017 1419 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
2bd2ad64 1420 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1421}
1422
1423/*
df0c237d
JB		 1424 * Native read with retry for link status and receiver capability reads for
1425 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1426 */
1427static bool
df0c237d
JB		 1428intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1429 uint8_t *recv, int recv_bytes)
a4fc5ed6 1430{
61da5fab
JB		 1431 int ret, i;
1432
df0c237d
JB		 1433 /*
1434 * Sinks are *supposed* to come up within 1ms from an off state,
1435 * but we're also supposed to retry 3 times per the spec.
1436 */
61da5fab 1437 for (i = 0; i < 3; i++) {
df0c237d
JB		 1438 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1439 recv_bytes);
1440 if (ret == recv_bytes)
61da5fab
JB		 1441 return true;
1442 msleep(1);
1443 }
a4fc5ed6 1444
61da5fab 1445 return false;
a4fc5ed6
KP		 1446}
1447
1448/*
1449 * Fetch AUX CH registers 0x202 - 0x207 which contain
1450 * link status information
1451 */
1452static bool
93f62dad 1453intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1454{
df0c237d
JB		 1455 return intel_dp_aux_native_read_retry(intel_dp,
1456 DP_LANE0_1_STATUS,
93f62dad 1457 link_status,
df0c237d 1458 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1459}
1460
a4fc5ed6
KP		 1461#if 0
1462static char *voltage_names[] = {
1463 "0.4V", "0.6V", "0.8V", "1.2V"
1464};
1465static char *pre_emph_names[] = {
1466 "0dB", "3.5dB", "6dB", "9.5dB"
1467};
1468static char *link_train_names[] = {
1469 "pattern 1", "pattern 2", "idle", "off"
1470};
1471#endif
1472
1473/*
1474 * These are source-specific values; current Intel hardware supports
1475 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1476 */
a4fc5ed6
KP		 1477
1478static uint8_t
1a2eb460 1479intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1480{
30add22d 1481 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1482
1483 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1484 return DP_TRAIN_VOLTAGE_SWING_800;
1485 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1486 return DP_TRAIN_VOLTAGE_SWING_1200;
1487 else
1488 return DP_TRAIN_VOLTAGE_SWING_800;
1489}
1490
1491static uint8_t
1492intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1493{
30add22d 1494 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1495
22b8bf17 1496 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1497 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1498 case DP_TRAIN_VOLTAGE_SWING_400:
1499 return DP_TRAIN_PRE_EMPHASIS_9_5;
1500 case DP_TRAIN_VOLTAGE_SWING_600:
1501 return DP_TRAIN_PRE_EMPHASIS_6;
1502 case DP_TRAIN_VOLTAGE_SWING_800:
1503 return DP_TRAIN_PRE_EMPHASIS_3_5;
1504 case DP_TRAIN_VOLTAGE_SWING_1200:
1505 default:
1506 return DP_TRAIN_PRE_EMPHASIS_0;
1507 }
1508 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1509 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1510 case DP_TRAIN_VOLTAGE_SWING_400:
1511 return DP_TRAIN_PRE_EMPHASIS_6;
1512 case DP_TRAIN_VOLTAGE_SWING_600:
1513 case DP_TRAIN_VOLTAGE_SWING_800:
1514 return DP_TRAIN_PRE_EMPHASIS_3_5;
1515 default:
1516 return DP_TRAIN_PRE_EMPHASIS_0;
1517 }
1518 } else {
1519 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1520 case DP_TRAIN_VOLTAGE_SWING_400:
1521 return DP_TRAIN_PRE_EMPHASIS_6;
1522 case DP_TRAIN_VOLTAGE_SWING_600:
1523 return DP_TRAIN_PRE_EMPHASIS_6;
1524 case DP_TRAIN_VOLTAGE_SWING_800:
1525 return DP_TRAIN_PRE_EMPHASIS_3_5;
1526 case DP_TRAIN_VOLTAGE_SWING_1200:
1527 default:
1528 return DP_TRAIN_PRE_EMPHASIS_0;
1529 }
a4fc5ed6
KP		 1530 }
1531}
1532
1533static void
93f62dad 1534intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1535{
1536 uint8_t v = 0;
1537 uint8_t p = 0;
1538 int lane;
1a2eb460
KP		 1539 uint8_t voltage_max;
1540 uint8_t preemph_max;
a4fc5ed6 1541
33a34e4e 1542 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1543 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1544 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1545
1546 if (this_v > v)
1547 v = this_v;
1548 if (this_p > p)
1549 p = this_p;
1550 }
1551
1a2eb460 1552 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1553 if (v >= voltage_max)
1554 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1555
1a2eb460
KP		 1556 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1557 if (p >= preemph_max)
1558 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1559
1560 for (lane = 0; lane < 4; lane++)
33a34e4e 1561 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1562}
1563
1564static uint32_t
f0a3424e 1565intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1566{
3cf2efb1 1567 uint32_t signal_levels = 0;
a4fc5ed6 1568
3cf2efb1 1569 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1570 case DP_TRAIN_VOLTAGE_SWING_400:
1571 default:
1572 signal_levels |= DP_VOLTAGE_0_4;
1573 break;
1574 case DP_TRAIN_VOLTAGE_SWING_600:
1575 signal_levels |= DP_VOLTAGE_0_6;
1576 break;
1577 case DP_TRAIN_VOLTAGE_SWING_800:
1578 signal_levels |= DP_VOLTAGE_0_8;
1579 break;
1580 case DP_TRAIN_VOLTAGE_SWING_1200:
1581 signal_levels |= DP_VOLTAGE_1_2;
1582 break;
1583 }
3cf2efb1 1584 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1585 case DP_TRAIN_PRE_EMPHASIS_0:
1586 default:
1587 signal_levels |= DP_PRE_EMPHASIS_0;
1588 break;
1589 case DP_TRAIN_PRE_EMPHASIS_3_5:
1590 signal_levels |= DP_PRE_EMPHASIS_3_5;
1591 break;
1592 case DP_TRAIN_PRE_EMPHASIS_6:
1593 signal_levels |= DP_PRE_EMPHASIS_6;
1594 break;
1595 case DP_TRAIN_PRE_EMPHASIS_9_5:
1596 signal_levels |= DP_PRE_EMPHASIS_9_5;
1597 break;
1598 }
1599 return signal_levels;
1600}
1601
e3421a18
ZW		 1602/* Gen6's DP voltage swing and pre-emphasis control */
1603static uint32_t
1604intel_gen6_edp_signal_levels(uint8_t train_set)
1605{
3c5a62b5
YL		 1606 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1607 DP_TRAIN_PRE_EMPHASIS_MASK);
1608 switch (signal_levels) {
e3421a18 1609 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1610 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1611 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1612 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1613 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1614 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1615 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1616 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1617 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1618 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1619 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1620 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1621 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1622 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1623 default:
3c5a62b5
YL		 1624 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1625 "0x%x\n", signal_levels);
1626 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1627 }
1628}
1629
1a2eb460
KP		 1630/* Gen7's DP voltage swing and pre-emphasis control */
1631static uint32_t
1632intel_gen7_edp_signal_levels(uint8_t train_set)
1633{
1634 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1635 DP_TRAIN_PRE_EMPHASIS_MASK);
1636 switch (signal_levels) {
1637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1638 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1640 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1641 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1642 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1643
1644 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1645 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1646 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1647 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1648
1649 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1650 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1651 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1652 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1653
1654 default:
1655 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1656 "0x%x\n", signal_levels);
1657 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1658 }
1659}
1660
d6c0d722
PZ		 1661/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1662static uint32_t
f0a3424e 1663intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1664{
d6c0d722
PZ		 1665 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1666 DP_TRAIN_PRE_EMPHASIS_MASK);
1667 switch (signal_levels) {
1668 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1669 return DDI_BUF_EMP_400MV_0DB_HSW;
1670 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1671 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1672 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1673 return DDI_BUF_EMP_400MV_6DB_HSW;
1674 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1675 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1676
d6c0d722
PZ		 1677 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1678 return DDI_BUF_EMP_600MV_0DB_HSW;
1679 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1680 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1681 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1682 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1683
d6c0d722
PZ		 1684 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1685 return DDI_BUF_EMP_800MV_0DB_HSW;
1686 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1687 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1688 default:
1689 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1690 "0x%x\n", signal_levels);
1691 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1692 }
a4fc5ed6
KP		 1693}
1694
f0a3424e
PZ		 1695/* Properly updates "DP" with the correct signal levels. */
1696static void
1697intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1698{
1699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1700 struct drm_device *dev = intel_dig_port->base.base.dev;
1701 uint32_t signal_levels, mask;
1702 uint8_t train_set = intel_dp->train_set[0];
1703
22b8bf17 1704 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1705 signal_levels = intel_hsw_signal_levels(train_set);
1706 mask = DDI_BUF_EMP_MASK;
1707 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1708 signal_levels = intel_gen7_edp_signal_levels(train_set);
1709 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1710 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1711 signal_levels = intel_gen6_edp_signal_levels(train_set);
1712 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1713 } else {
1714 signal_levels = intel_gen4_signal_levels(train_set);
1715 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1716 }
1717
1718 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1719
1720 *DP = (*DP & ~mask) | signal_levels;
1721}
1722
a4fc5ed6 1723static bool
ea5b213a 1724intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1725 uint32_t dp_reg_value,
58e10eb9 1726 uint8_t dp_train_pat)
a4fc5ed6 1727{
174edf1f
PZ		 1728 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1729 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1730 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1731 enum port port = intel_dig_port->port;
a4fc5ed6 1732 int ret;
d6c0d722 1733 uint32_t temp;
a4fc5ed6 1734
22b8bf17 1735 if (HAS_DDI(dev)) {
174edf1f 1736 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1737
1738 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1739 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1740 else
1741 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1742
1743 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1744 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1745 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1746
10aa17c8
PZ		 1747 if (port != PORT_A) {
1748 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1749 I915_WRITE(DP_TP_CTL(port), temp);
1750
1751 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1752 DP_TP_STATUS_IDLE_DONE), 1))
1753 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1754
1755 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1756 }
d6c0d722 1757
d6c0d722
PZ		 1758 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1759
1760 break;
1761 case DP_TRAINING_PATTERN_1:
1762 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1763 break;
1764 case DP_TRAINING_PATTERN_2:
1765 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1766 break;
1767 case DP_TRAINING_PATTERN_3:
1768 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1769 break;
1770 }
174edf1f 1771 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1772
1773 } else if (HAS_PCH_CPT(dev) &&
1774 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1775 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1776
1777 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1778 case DP_TRAINING_PATTERN_DISABLE:
1779 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1780 break;
1781 case DP_TRAINING_PATTERN_1:
1782 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1783 break;
1784 case DP_TRAINING_PATTERN_2:
1785 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1786 break;
1787 case DP_TRAINING_PATTERN_3:
1788 DRM_ERROR("DP training pattern 3 not supported\n");
1789 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1790 break;
1791 }
1792
1793 } else {
1794 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1795
1796 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1797 case DP_TRAINING_PATTERN_DISABLE:
1798 dp_reg_value |= DP_LINK_TRAIN_OFF;
1799 break;
1800 case DP_TRAINING_PATTERN_1:
1801 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1802 break;
1803 case DP_TRAINING_PATTERN_2:
1804 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1805 break;
1806 case DP_TRAINING_PATTERN_3:
1807 DRM_ERROR("DP training pattern 3 not supported\n");
1808 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1809 break;
1810 }
1811 }
1812
ea5b213a
CW		 1813 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1814 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1815
ea5b213a 1816 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1817 DP_TRAINING_PATTERN_SET,
1818 dp_train_pat);
1819
47ea7542
PZ		 1820 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1821 DP_TRAINING_PATTERN_DISABLE) {
1822 ret = intel_dp_aux_native_write(intel_dp,
1823 DP_TRAINING_LANE0_SET,
1824 intel_dp->train_set,
1825 intel_dp->lane_count);
1826 if (ret != intel_dp->lane_count)
1827 return false;
1828 }
a4fc5ed6
KP		 1829
1830 return true;
1831}
1832
33a34e4e 1833/* Enable corresponding port and start training pattern 1 */
c19b0669 1834void
33a34e4e 1835intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1836{
da63a9f2 1837 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1838 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1839 int i;
1840 uint8_t voltage;
1841 bool clock_recovery = false;
cdb0e95b 1842 int voltage_tries, loop_tries;
ea5b213a 1843 uint32_t DP = intel_dp->DP;
a4fc5ed6 1844
affa9354 1845 if (HAS_DDI(dev))
c19b0669
PZ		 1846 intel_ddi_prepare_link_retrain(encoder);
1847
3cf2efb1
CW		 1848 /* Write the link configuration data */
1849 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1850 intel_dp->link_configuration,
1851 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1852
1853 DP |= DP_PORT_EN;
1a2eb460 1854
33a34e4e 1855 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1856 voltage = 0xff;
cdb0e95b
KP		 1857 voltage_tries = 0;
1858 loop_tries = 0;
a4fc5ed6
KP		 1859 clock_recovery = false;
1860 for (;;) {
33a34e4e 1861 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1862 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 1863
1864 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 1865
a7c9655f 1866 /* Set training pattern 1 */
47ea7542 1867 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1868 DP_TRAINING_PATTERN_1 |
1869 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1870 break;
a4fc5ed6 1871
a7c9655f 1872 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1873 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1874 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1875 break;
93f62dad 1876 }
a4fc5ed6 1877
01916270 1878 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1879 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1880 clock_recovery = true;
1881 break;
1882 }
1883
1884 /* Check to see if we've tried the max voltage */
1885 for (i = 0; i < intel_dp->lane_count; i++)
1886 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1887 break;
0d710688 1888 if (i == intel_dp->lane_count && voltage_tries == 5) {
b06fbda3
DV		 1889 ++loop_tries;
1890 if (loop_tries == 5) {
cdb0e95b
KP		 1891 DRM_DEBUG_KMS("too many full retries, give up\n");
1892 break;
1893 }
1894 memset(intel_dp->train_set, 0, 4);
1895 voltage_tries = 0;
1896 continue;
1897 }
a4fc5ed6 1898
3cf2efb1 1899 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1900 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1901 ++voltage_tries;
b06fbda3
DV		 1902 if (voltage_tries == 5) {
1903 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1904 break;
1905 }
1906 } else
1907 voltage_tries = 0;
1908 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1909
3cf2efb1 1910 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1911 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1912 }
1913
33a34e4e
JB		 1914 intel_dp->DP = DP;
1915}
1916
c19b0669 1917void
33a34e4e
JB		 1918intel_dp_complete_link_train(struct intel_dp *intel_dp)
1919{
33a34e4e 1920 bool channel_eq = false;
37f80975 1921 int tries, cr_tries;
33a34e4e
JB		 1922 uint32_t DP = intel_dp->DP;
1923
a4fc5ed6
KP		 1924 /* channel equalization */
1925 tries = 0;
37f80975 1926 cr_tries = 0;
a4fc5ed6
KP		 1927 channel_eq = false;
1928 for (;;) {
93f62dad 1929 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1930
37f80975
JB		 1931 if (cr_tries > 5) {
1932 DRM_ERROR("failed to train DP, aborting\n");
1933 intel_dp_link_down(intel_dp);
1934 break;
1935 }
1936
f0a3424e 1937 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 1938
a4fc5ed6 1939 /* channel eq pattern */
47ea7542 1940 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1941 DP_TRAINING_PATTERN_2 |
1942 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1943 break;
1944
a7c9655f 1945 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1946 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1947 break;
a4fc5ed6 1948
37f80975 1949 /* Make sure clock is still ok */
01916270 1950 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1951 intel_dp_start_link_train(intel_dp);
1952 cr_tries++;
1953 continue;
1954 }
1955
1ffdff13 1956 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1957 channel_eq = true;
1958 break;
1959 }
a4fc5ed6 1960
37f80975
JB		 1961 /* Try 5 times, then try clock recovery if that fails */
1962 if (tries > 5) {
1963 intel_dp_link_down(intel_dp);
1964 intel_dp_start_link_train(intel_dp);
1965 tries = 0;
1966 cr_tries++;
1967 continue;
1968 }
a4fc5ed6 1969
3cf2efb1 1970 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1971 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1972 ++tries;
869184a6 1973 }
3cf2efb1 1974
d6c0d722
PZ		 1975 if (channel_eq)
1976 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1977
47ea7542 1978 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1979}
1980
1981static void
ea5b213a 1982intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1983{
da63a9f2
PZ		 1984 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1985 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1986 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 1987 struct intel_crtc *intel_crtc =
1988 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 1989 uint32_t DP = intel_dp->DP;
a4fc5ed6 1990
c19b0669
PZ		 1991 /*
1992 * DDI code has a strict mode set sequence and we should try to respect
1993 * it, otherwise we might hang the machine in many different ways. So we
1994 * really should be disabling the port only on a complete crtc_disable
1995 * sequence. This function is just called under two conditions on DDI
1996 * code:
1997 * - Link train failed while doing crtc_enable, and on this case we
1998 * really should respect the mode set sequence and wait for a
1999 * crtc_disable.
2000 * - Someone turned the monitor off and intel_dp_check_link_status
2001 * called us. We don't need to disable the whole port on this case, so
2002 * when someone turns the monitor on again,
2003 * intel_ddi_prepare_link_retrain will take care of redoing the link
2004 * train.
2005 */
affa9354 2006 if (HAS_DDI(dev))
c19b0669
PZ		 2007 return;
2008
0c33d8d7 2009 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2010 return;
2011
28c97730 2012 DRM_DEBUG_KMS("\n");
32f9d658 2013
1a2eb460 2014 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2015 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2016 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2017 } else {
2018 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2019 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2020 }
fe255d00 2021 POSTING_READ(intel_dp->output_reg);
5eb08b69 2022
ab527efc
DV		 2023 /* We don't really know why we're doing this */
2024 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2025
493a7081 2026 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2027 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2028 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2029
5bddd17f
EA		 2030 /* Hardware workaround: leaving our transcoder select
2031 * set to transcoder B while it's off will prevent the
2032 * corresponding HDMI output on transcoder A.
2033 *
2034 * Combine this with another hardware workaround:
2035 * transcoder select bit can only be cleared while the
2036 * port is enabled.
2037 */
2038 DP &= ~DP_PIPEB_SELECT;
2039 I915_WRITE(intel_dp->output_reg, DP);
2040
2041 /* Changes to enable or select take place the vblank
2042 * after being written.
2043 */
ff50afe9
DV		 2044 if (WARN_ON(crtc == NULL)) {
2045 /* We should never try to disable a port without a crtc
2046 * attached. For paranoia keep the code around for a
2047 * bit. */
31acbcc4
CW		 2048 POSTING_READ(intel_dp->output_reg);
2049 msleep(50);
2050 } else
ab527efc 2051 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2052 }
2053
832afda6 2054 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2055 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2056 POSTING_READ(intel_dp->output_reg);
f01eca2e 2057 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2058}
2059
26d61aad
KP		 2060static bool
2061intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2062{
577c7a50
DL		 2063 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2064
92fd8fd1 2065 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2066 sizeof(intel_dp->dpcd)) == 0)
2067 return false; /* aux transfer failed */
92fd8fd1 2068
577c7a50
DL		 2069 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2070 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2071 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2072
edb39244
AJ		 2073 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2074 return false; /* DPCD not present */
2075
2076 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2077 DP_DWN_STRM_PORT_PRESENT))
2078 return true; /* native DP sink */
2079
2080 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2081 return true; /* no per-port downstream info */
2082
2083 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2084 intel_dp->downstream_ports,
2085 DP_MAX_DOWNSTREAM_PORTS) == 0)
2086 return false; /* downstream port status fetch failed */
2087
2088 return true;
92fd8fd1
KP		 2089}
2090
0d198328
AJ		 2091static void
2092intel_dp_probe_oui(struct intel_dp *intel_dp)
2093{
2094 u8 buf[3];
2095
2096 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2097 return;
2098
351cfc34
DV		 2099 ironlake_edp_panel_vdd_on(intel_dp);
2100
0d198328
AJ		 2101 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2102 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2103 buf[0], buf[1], buf[2]);
2104
2105 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2106 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2107 buf[0], buf[1], buf[2]);
351cfc34
DV		 2108
2109 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2110}
2111
a60f0e38
JB		 2112static bool
2113intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2114{
2115 int ret;
2116
2117 ret = intel_dp_aux_native_read_retry(intel_dp,
2118 DP_DEVICE_SERVICE_IRQ_VECTOR,
2119 sink_irq_vector, 1);
2120 if (!ret)
2121 return false;
2122
2123 return true;
2124}
2125
2126static void
2127intel_dp_handle_test_request(struct intel_dp *intel_dp)
2128{
2129 /* NAK by default */
9324cf7f 2130 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2131}
2132
a4fc5ed6
KP		 2133/*
2134 * According to DP spec
2135 * 5.1.2:
2136 * 1. Read DPCD
2137 * 2. Configure link according to Receiver Capabilities
2138 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2139 * 4. Check link status on receipt of hot-plug interrupt
2140 */
2141
00c09d70 2142void
ea5b213a 2143intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2144{
da63a9f2 2145 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2146 u8 sink_irq_vector;
93f62dad 2147 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2148
da63a9f2 2149 if (!intel_encoder->connectors_active)
d2b996ac 2150 return;
59cd09e1 2151
da63a9f2 2152 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2153 return;
2154
92fd8fd1 2155 /* Try to read receiver status if the link appears to be up */
93f62dad 2156 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2157 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2158 return;
2159 }
2160
92fd8fd1 2161 /* Now read the DPCD to see if it's actually running */
26d61aad 2162 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2163 intel_dp_link_down(intel_dp);
2164 return;
2165 }
2166
a60f0e38
JB		 2167 /* Try to read the source of the interrupt */
2168 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2169 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2170 /* Clear interrupt source */
2171 intel_dp_aux_native_write_1(intel_dp,
2172 DP_DEVICE_SERVICE_IRQ_VECTOR,
2173 sink_irq_vector);
2174
2175 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2176 intel_dp_handle_test_request(intel_dp);
2177 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2178 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2179 }
2180
1ffdff13 2181 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2182 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2183 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2184 intel_dp_start_link_train(intel_dp);
2185 intel_dp_complete_link_train(intel_dp);
2186 }
a4fc5ed6 2187}
a4fc5ed6 2188
caf9ab24 2189/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2190static enum drm_connector_status
26d61aad 2191intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2192{
caf9ab24
AJ		 2193 uint8_t *dpcd = intel_dp->dpcd;
2194 bool hpd;
2195 uint8_t type;
2196
2197 if (!intel_dp_get_dpcd(intel_dp))
2198 return connector_status_disconnected;
2199
2200 /* if there's no downstream port, we're done */
2201 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2202 return connector_status_connected;
caf9ab24
AJ		 2203
2204 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2205 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2206 if (hpd) {
23235177 2207 uint8_t reg;
caf9ab24 2208 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2209 &reg, 1))
caf9ab24 2210 return connector_status_unknown;
23235177
AJ		 2211 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2212 : connector_status_disconnected;
caf9ab24
AJ		 2213 }
2214
2215 /* If no HPD, poke DDC gently */
2216 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2217 return connector_status_connected;
caf9ab24
AJ		 2218
2219 /* Well we tried, say unknown for unreliable port types */
2220 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2221 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2222 return connector_status_unknown;
2223
2224 /* Anything else is out of spec, warn and ignore */
2225 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2226 return connector_status_disconnected;
71ba9000
AJ		 2227}
2228
5eb08b69 2229static enum drm_connector_status
a9756bb5 2230ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2231{
30add22d 2232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2235 enum drm_connector_status status;
2236
fe16d949
CW		 2237 /* Can't disconnect eDP, but you can close the lid... */
2238 if (is_edp(intel_dp)) {
30add22d 2239 status = intel_panel_detect(dev);
fe16d949
CW		 2240 if (status == connector_status_unknown)
2241 status = connector_status_connected;
2242 return status;
2243 }
01cb9ea6 2244
1b469639
DL		 2245 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2246 return connector_status_disconnected;
2247
26d61aad 2248 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2249}
2250
a4fc5ed6 2251static enum drm_connector_status
a9756bb5 2252g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2253{
30add22d 2254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2255 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2256 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2257 uint32_t bit;
5eb08b69 2258
35aad75f
JB		 2259 /* Can't disconnect eDP, but you can close the lid... */
2260 if (is_edp(intel_dp)) {
2261 enum drm_connector_status status;
2262
2263 status = intel_panel_detect(dev);
2264 if (status == connector_status_unknown)
2265 status = connector_status_connected;
2266 return status;
2267 }
2268
34f2be46
VS		 2269 switch (intel_dig_port->port) {
2270 case PORT_B:
26739f12 2271 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2272 break;
34f2be46 2273 case PORT_C:
26739f12 2274 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2275 break;
34f2be46 2276 case PORT_D:
26739f12 2277 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2278 break;
2279 default:
2280 return connector_status_unknown;
2281 }
2282
10f76a38 2283 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2284 return connector_status_disconnected;
2285
26d61aad 2286 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2287}
2288
8c241fef
KP		 2289static struct edid *
2290intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2291{
9cd300e0 2292 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2293
9cd300e0
JN		 2294 /* use cached edid if we have one */
2295 if (intel_connector->edid) {
2296 struct edid *edid;
2297 int size;
2298
2299 /* invalid edid */
2300 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2301 return NULL;
2302
9cd300e0 2303 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2304 edid = kmalloc(size, GFP_KERNEL);
2305 if (!edid)
2306 return NULL;
2307
9cd300e0 2308 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2309 return edid;
2310 }
8c241fef 2311
9cd300e0 2312 return drm_get_edid(connector, adapter);
8c241fef
KP		 2313}
2314
2315static int
2316intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2317{
9cd300e0 2318 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2319
9cd300e0
JN		 2320 /* use cached edid if we have one */
2321 if (intel_connector->edid) {
2322 /* invalid edid */
2323 if (IS_ERR(intel_connector->edid))
2324 return 0;
2325
2326 return intel_connector_update_modes(connector,
2327 intel_connector->edid);
d6f24d0f
JB		 2328 }
2329
9cd300e0 2330 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2331}
2332
a9756bb5
ZW		 2333static enum drm_connector_status
2334intel_dp_detect(struct drm_connector *connector, bool force)
2335{
2336 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2338 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2339 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2340 enum drm_connector_status status;
2341 struct edid *edid = NULL;
2342
2343 intel_dp->has_audio = false;
2344
2345 if (HAS_PCH_SPLIT(dev))
2346 status = ironlake_dp_detect(intel_dp);
2347 else
2348 status = g4x_dp_detect(intel_dp);
1b9be9d0 2349
a9756bb5
ZW		 2350 if (status != connector_status_connected)
2351 return status;
2352
0d198328
AJ		 2353 intel_dp_probe_oui(intel_dp);
2354
c3e5f67b
DV		 2355 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2356 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2357 } else {
8c241fef 2358 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2359 if (edid) {
2360 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2361 kfree(edid);
2362 }
a9756bb5
ZW		 2363 }
2364
d63885da
PZ		 2365 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2366 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2367 return connector_status_connected;
a4fc5ed6
KP		 2368}
2369
2370static int intel_dp_get_modes(struct drm_connector *connector)
2371{
df0e9248 2372 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2373 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2374 struct drm_device *dev = connector->dev;
32f9d658 2375 int ret;
a4fc5ed6
KP		 2376
2377 /* We should parse the EDID data and find out if it has an audio sink
2378 */
2379
8c241fef 2380 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2381 if (ret)
32f9d658
ZW		 2382 return ret;
2383
f8779fda 2384 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2385 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2386 struct drm_display_mode *mode;
dd06f90e
JN		 2387 mode = drm_mode_duplicate(dev,
2388 intel_connector->panel.fixed_mode);
f8779fda 2389 if (mode) {
32f9d658
ZW		 2390 drm_mode_probed_add(connector, mode);
2391 return 1;
2392 }
2393 }
2394 return 0;
a4fc5ed6
KP		 2395}
2396
1aad7ac0
CW		 2397static bool
2398intel_dp_detect_audio(struct drm_connector *connector)
2399{
2400 struct intel_dp *intel_dp = intel_attached_dp(connector);
2401 struct edid *edid;
2402 bool has_audio = false;
2403
8c241fef 2404 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2405 if (edid) {
2406 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2407 kfree(edid);
2408 }
2409
2410 return has_audio;
2411}
2412
f684960e
CW		 2413static int
2414intel_dp_set_property(struct drm_connector *connector,
2415 struct drm_property *property,
2416 uint64_t val)
2417{
e953fd7b 2418 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2419 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2420 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2421 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2422 int ret;
2423
662595df 2424 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2425 if (ret)
2426 return ret;
2427
3f43c48d 2428 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2429 int i = val;
2430 bool has_audio;
2431
2432 if (i == intel_dp->force_audio)
f684960e
CW		 2433 return 0;
2434
1aad7ac0 2435 intel_dp->force_audio = i;
f684960e 2436
c3e5f67b 2437 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2438 has_audio = intel_dp_detect_audio(connector);
2439 else
c3e5f67b 2440 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2441
2442 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2443 return 0;
2444
1aad7ac0 2445 intel_dp->has_audio = has_audio;
f684960e
CW		 2446 goto done;
2447 }
2448
e953fd7b 2449 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2450 switch (val) {
2451 case INTEL_BROADCAST_RGB_AUTO:
2452 intel_dp->color_range_auto = true;
2453 break;
2454 case INTEL_BROADCAST_RGB_FULL:
2455 intel_dp->color_range_auto = false;
2456 intel_dp->color_range = 0;
2457 break;
2458 case INTEL_BROADCAST_RGB_LIMITED:
2459 intel_dp->color_range_auto = false;
2460 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2461 break;
2462 default:
2463 return -EINVAL;
2464 }
e953fd7b
CW		 2465 goto done;
2466 }
2467
53b41837
YN		 2468 if (is_edp(intel_dp) &&
2469 property == connector->dev->mode_config.scaling_mode_property) {
2470 if (val == DRM_MODE_SCALE_NONE) {
2471 DRM_DEBUG_KMS("no scaling not supported\n");
2472 return -EINVAL;
2473 }
2474
2475 if (intel_connector->panel.fitting_mode == val) {
2476 /* the eDP scaling property is not changed */
2477 return 0;
2478 }
2479 intel_connector->panel.fitting_mode = val;
2480
2481 goto done;
2482 }
2483
f684960e
CW		 2484 return -EINVAL;
2485
2486done:
c0c36b94
CW		 2487 if (intel_encoder->base.crtc)
2488 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2489
2490 return 0;
2491}
2492
a4fc5ed6 2493static void
0206e353 2494intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2495{
aaa6fd2a 2496 struct drm_device *dev = connector->dev;
be3cd5e3 2497 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2498 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2499
9cd300e0
JN		 2500 if (!IS_ERR_OR_NULL(intel_connector->edid))
2501 kfree(intel_connector->edid);
2502
1d508706 2503 if (is_edp(intel_dp)) {
aaa6fd2a 2504 intel_panel_destroy_backlight(dev);
1d508706
JN		 2505 intel_panel_fini(&intel_connector->panel);
2506 }
aaa6fd2a 2507
a4fc5ed6
KP		 2508 drm_sysfs_connector_remove(connector);
2509 drm_connector_cleanup(connector);
55f78c43 2510 kfree(connector);
a4fc5ed6
KP		 2511}
2512
00c09d70 2513void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2514{
da63a9f2
PZ		 2515 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2516 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2517
2518 i2c_del_adapter(&intel_dp->adapter);
2519 drm_encoder_cleanup(encoder);
bd943159
KP		 2520 if (is_edp(intel_dp)) {
2521 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2522 ironlake_panel_vdd_off_sync(intel_dp);
2523 }
da63a9f2 2524 kfree(intel_dig_port);
24d05927
DV		 2525}
2526
a4fc5ed6 2527static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2528 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2529};
2530
2531static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2532 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2533 .detect = intel_dp_detect,
2534 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2535 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2536 .destroy = intel_dp_destroy,
2537};
2538
2539static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2540 .get_modes = intel_dp_get_modes,
2541 .mode_valid = intel_dp_mode_valid,
df0e9248 2542 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2543};
2544
a4fc5ed6 2545static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2546 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2547};
2548
995b6762 2549static void
21d40d37 2550intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2551{
fa90ecef 2552 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2553
885a5014 2554 intel_dp_check_link_status(intel_dp);
c8110e52 2555}
6207937d 2556
e3421a18
ZW		 2557/* Return which DP Port should be selected for Transcoder DP control */
2558int
0206e353 2559intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2560{
2561 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2562 struct intel_encoder *intel_encoder;
2563 struct intel_dp *intel_dp;
e3421a18 2564
fa90ecef
PZ		 2565 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2566 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2567
fa90ecef
PZ		 2568 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2569 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2570 return intel_dp->output_reg;
e3421a18 2571 }
ea5b213a 2572
e3421a18
ZW		 2573 return -1;
2574}
2575
36e83a18 2576/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2577bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2578{
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct child_device_config *p_child;
2581 int i;
2582
2583 if (!dev_priv->child_dev_num)
2584 return false;
2585
2586 for (i = 0; i < dev_priv->child_dev_num; i++) {
2587 p_child = dev_priv->child_dev + i;
2588
2589 if (p_child->dvo_port == PORT_IDPD &&
2590 p_child->device_type == DEVICE_TYPE_eDP)
2591 return true;
2592 }
2593 return false;
2594}
2595
f684960e
CW		 2596static void
2597intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2598{
53b41837
YN		 2599 struct intel_connector *intel_connector = to_intel_connector(connector);
2600
3f43c48d 2601 intel_attach_force_audio_property(connector);
e953fd7b 2602 intel_attach_broadcast_rgb_property(connector);
55bc60db 2603 intel_dp->color_range_auto = true;
53b41837
YN		 2604
2605 if (is_edp(intel_dp)) {
2606 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2607 drm_object_attach_property(
2608 &connector->base,
53b41837 2609 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2610 DRM_MODE_SCALE_ASPECT);
2611 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2612 }
f684960e
CW		 2613}
2614
67a54566
DV		 2615static void
2616intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2617 struct intel_dp *intel_dp,
2618 struct edp_power_seq *out)
67a54566
DV		 2619{
2620 struct drm_i915_private *dev_priv = dev->dev_private;
2621 struct edp_power_seq cur, vbt, spec, final;
2622 u32 pp_on, pp_off, pp_div, pp;
2623
2624 /* Workaround: Need to write PP_CONTROL with the unlock key as
2625 * the very first thing. */
2626 pp = ironlake_get_pp_control(dev_priv);
2627 I915_WRITE(PCH_PP_CONTROL, pp);
2628
2629 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2630 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2631 pp_div = I915_READ(PCH_PP_DIVISOR);
2632
2633 /* Pull timing values out of registers */
2634 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2635 PANEL_POWER_UP_DELAY_SHIFT;
2636
2637 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2638 PANEL_LIGHT_ON_DELAY_SHIFT;
2639
2640 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2641 PANEL_LIGHT_OFF_DELAY_SHIFT;
2642
2643 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2644 PANEL_POWER_DOWN_DELAY_SHIFT;
2645
2646 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2647 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2648
2649 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2650 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2651
2652 vbt = dev_priv->edp.pps;
2653
2654 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2655 * our hw here, which are all in 100usec. */
2656 spec.t1_t3 = 210 * 10;
2657 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2658 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2659 spec.t10 = 500 * 10;
2660 /* This one is special and actually in units of 100ms, but zero
2661 * based in the hw (so we need to add 100 ms). But the sw vbt
2662 * table multiplies it with 1000 to make it in units of 100usec,
2663 * too. */
2664 spec.t11_t12 = (510 + 100) * 10;
2665
2666 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2667 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2668
2669 /* Use the max of the register settings and vbt. If both are
2670 * unset, fall back to the spec limits. */
2671#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2672 spec.field : \
2673 max(cur.field, vbt.field))
2674 assign_final(t1_t3);
2675 assign_final(t8);
2676 assign_final(t9);
2677 assign_final(t10);
2678 assign_final(t11_t12);
2679#undef assign_final
2680
2681#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2682 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2683 intel_dp->backlight_on_delay = get_delay(t8);
2684 intel_dp->backlight_off_delay = get_delay(t9);
2685 intel_dp->panel_power_down_delay = get_delay(t10);
2686 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2687#undef get_delay
2688
f30d26e4
JN		 2689 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2690 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2691 intel_dp->panel_power_cycle_delay);
2692
2693 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2694 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2695
2696 if (out)
2697 *out = final;
2698}
2699
2700static void
2701intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2702 struct intel_dp *intel_dp,
2703 struct edp_power_seq *seq)
2704{
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 u32 pp_on, pp_off, pp_div;
2707
67a54566 2708 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2709 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2710 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2711 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2712 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2713 /* Compute the divisor for the pp clock, simply match the Bspec
2714 * formula. */
2715 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2716 << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2717 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2718 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2719
2720 /* Haswell doesn't have any port selection bits for the panel
2721 * power sequencer any more. */
2722 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2723 if (is_cpu_edp(intel_dp))
2724 pp_on |= PANEL_POWER_PORT_DP_A;
2725 else
2726 pp_on |= PANEL_POWER_PORT_DP_D;
2727 }
2728
2729 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2730 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2731 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2732
67a54566
DV		 2733 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2734 I915_READ(PCH_PP_ON_DELAYS),
2735 I915_READ(PCH_PP_OFF_DELAYS),
2736 I915_READ(PCH_PP_DIVISOR));
f684960e
CW		 2737}
2738
a4fc5ed6 2739void
f0fec3f2
PZ		 2740intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2741 struct intel_connector *intel_connector)
a4fc5ed6 2742{
f0fec3f2
PZ		 2743 struct drm_connector *connector = &intel_connector->base;
2744 struct intel_dp *intel_dp = &intel_dig_port->dp;
2745 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2746 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2747 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2748 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2749 struct edp_power_seq power_seq = { 0 };
174edf1f 2750 enum port port = intel_dig_port->port;
5eb08b69 2751 const char *name = NULL;
b329530c 2752 int type;
a4fc5ed6 2753
0767935e
DV		 2754 /* Preserve the current hw state. */
2755 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2756 intel_dp->attached_connector = intel_connector;
3d3dc149 2757
f0fec3f2 2758 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2759 if (intel_dpd_is_edp(dev))
ea5b213a 2760 intel_dp->is_pch_edp = true;
b329530c 2761
19c03924
GB		 2762 /*
2763 * FIXME : We need to initialize built-in panels before external panels.
2764 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2765 */
f0fec3f2 2766 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2767 type = DRM_MODE_CONNECTOR_eDP;
2768 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2769 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2770 type = DRM_MODE_CONNECTOR_eDP;
2771 intel_encoder->type = INTEL_OUTPUT_EDP;
2772 } else {
00c09d70
PZ		 2773 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2774 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2775 * rewrite it.
2776 */
b329530c 2777 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2778 }
2779
b329530c 2780 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2781 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2782
eb1f8e4f 2783 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2784 connector->interlace_allowed = true;
2785 connector->doublescan_allowed = 0;
2786
f0fec3f2
PZ		 2787 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2788 ironlake_panel_vdd_work);
a4fc5ed6 2789
df0e9248 2790 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2791 drm_sysfs_connector_add(connector);
2792
affa9354 2793 if (HAS_DDI(dev))
bcbc889b
PZ		 2794 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2795 else
2796 intel_connector->get_hw_state = intel_connector_get_hw_state;
2797
9ed35ab1
PZ		 2798 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2799 if (HAS_DDI(dev)) {
2800 switch (intel_dig_port->port) {
2801 case PORT_A:
2802 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2803 break;
2804 case PORT_B:
2805 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2806 break;
2807 case PORT_C:
2808 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2809 break;
2810 case PORT_D:
2811 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2812 break;
2813 default:
2814 BUG();
2815 }
2816 }
e8cb4558 2817
a4fc5ed6 2818 /* Set up the DDC bus. */
ab9d7c30
PZ		 2819 switch (port) {
2820 case PORT_A:
1d843f9d 2821 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 2822 name = "DPDDC-A";
2823 break;
2824 case PORT_B:
1d843f9d 2825 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 2826 name = "DPDDC-B";
2827 break;
2828 case PORT_C:
1d843f9d 2829 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 2830 name = "DPDDC-C";
2831 break;
2832 case PORT_D:
1d843f9d 2833 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 2834 name = "DPDDC-D";
2835 break;
2836 default:
ad1c0b19 2837 BUG();
5eb08b69
ZW		 2838 }
2839
67a54566 2840 if (is_edp(intel_dp))
f30d26e4 2841 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 2842
2843 intel_dp_i2c_init(intel_dp, intel_connector, name);
2844
67a54566 2845 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2846 if (is_edp(intel_dp)) {
2847 bool ret;
f8779fda 2848 struct drm_display_mode *scan;
c1f05264 2849 struct edid *edid;
5d613501
JB		 2850
2851 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2852 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2853 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2854
59f3e272 2855 if (ret) {
7183dc29
JB		 2856 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2857 dev_priv->no_aux_handshake =
2858 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2859 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2860 } else {
3d3dc149 2861 /* if this fails, presume the device is a ghost */
48898b03 2862 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2863 intel_dp_encoder_destroy(&intel_encoder->base);
2864 intel_dp_destroy(connector);
3d3dc149 2865 return;
89667383 2866 }
89667383 2867
f30d26e4
JN		 2868 /* We now know it's not a ghost, init power sequence regs. */
2869 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2870 &power_seq);
2871
d6f24d0f
JB		 2872 ironlake_edp_panel_vdd_on(intel_dp);
2873 edid = drm_get_edid(connector, &intel_dp->adapter);
2874 if (edid) {
9cd300e0
JN		 2875 if (drm_add_edid_modes(connector, edid)) {
2876 drm_mode_connector_update_edid_property(connector, edid);
2877 drm_edid_to_eld(connector, edid);
2878 } else {
2879 kfree(edid);
2880 edid = ERR_PTR(-EINVAL);
2881 }
2882 } else {
2883 edid = ERR_PTR(-ENOENT);
d6f24d0f 2884 }
9cd300e0 2885 intel_connector->edid = edid;
f8779fda
JN		 2886
2887 /* prefer fixed mode from EDID if available */
2888 list_for_each_entry(scan, &connector->probed_modes, head) {
2889 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2890 fixed_mode = drm_mode_duplicate(dev, scan);
2891 break;
2892 }
d6f24d0f 2893 }
f8779fda
JN		 2894
2895 /* fallback to VBT if available for eDP */
2896 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2897 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2898 if (fixed_mode)
2899 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2900 }
f8779fda 2901
d6f24d0f
JB		 2902 ironlake_edp_panel_vdd_off(intel_dp, false);
2903 }
552fb0b7 2904
4d926461 2905 if (is_edp(intel_dp)) {
dd06f90e 2906 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2907 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2908 }
2909
f684960e
CW		 2910 intel_dp_add_properties(intel_dp, connector);
2911
a4fc5ed6
KP		 2912 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2913 * 0xd. Failure to do so will result in spurious interrupts being
2914 * generated on the port when a cable is not attached.
2915 */
2916 if (IS_G4X(dev) && !IS_GM45(dev)) {
2917 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2918 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2919 }
2920}
f0fec3f2
PZ		 2921
2922void
2923intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2924{
2925 struct intel_digital_port *intel_dig_port;
2926 struct intel_encoder *intel_encoder;
2927 struct drm_encoder *encoder;
2928 struct intel_connector *intel_connector;
2929
2930 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2931 if (!intel_dig_port)
2932 return;
2933
2934 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2935 if (!intel_connector) {
2936 kfree(intel_dig_port);
2937 return;
2938 }
2939
2940 intel_encoder = &intel_dig_port->base;
2941 encoder = &intel_encoder->base;
2942
2943 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2944 DRM_MODE_ENCODER_TMDS);
00c09d70 2945 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2946
5bfe2ac0 2947 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 2948 intel_encoder->enable = intel_enable_dp;
2949 intel_encoder->pre_enable = intel_pre_enable_dp;
2950 intel_encoder->disable = intel_disable_dp;
2951 intel_encoder->post_disable = intel_post_disable_dp;
2952 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2953
174edf1f 2954 intel_dig_port->port = port;
f0fec3f2
PZ		 2955 intel_dig_port->dp.output_reg = output_reg;
2956
00c09d70 2957 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2958 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2959 intel_encoder->cloneable = false;
2960 intel_encoder->hot_plug = intel_dp_hot_plug;
2961
2962 intel_dp_init_connector(intel_dig_port, intel_connector);
2963}
Linux kernel - Deliverables
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