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drm/i915: Use symbolic irqreturn for ->hpd_pulse
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 117static void vlv_steal_power_sequencer(struct drm_device *dev,
118 enum pipe pipe);
a4fc5ed6 119
0e32b39c 120int
ea5b213a 121intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 122{
7183dc29 123 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 124 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 125
126 switch (max_link_bw) {
127 case DP_LINK_BW_1_62:
128 case DP_LINK_BW_2_7:
129 break;
d4eead50 130 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 131 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
132 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 133 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
134 max_link_bw = DP_LINK_BW_5_4;
135 else
136 max_link_bw = DP_LINK_BW_2_7;
d4eead50 137 break;
a4fc5ed6 138 default:
d4eead50
ID		 139 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
140 max_link_bw);
a4fc5ed6
KP		 141 max_link_bw = DP_LINK_BW_1_62;
142 break;
143 }
144 return max_link_bw;
145}
146
eeb6324d
PZ		 147static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
148{
149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
150 struct drm_device *dev = intel_dig_port->base.base.dev;
151 u8 source_max, sink_max;
152
153 source_max = 4;
154 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
155 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
156 source_max = 2;
157
158 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
159
160 return min(source_max, sink_max);
161}
162
cd9dde44
AJ		 163/*
164 * The units on the numbers in the next two are... bizarre. Examples will
165 * make it clearer; this one parallels an example in the eDP spec.
166 *
167 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
168 *
169 * 270000 * 1 * 8 / 10 == 216000
170 *
171 * The actual data capacity of that configuration is 2.16Gbit/s, so the
172 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
173 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
174 * 119000. At 18bpp that's 2142000 kilobits per second.
175 *
176 * Thus the strange-looking division by 10 in intel_dp_link_required, to
177 * get the result in decakilobits instead of kilobits.
178 */
179
a4fc5ed6 180static int
c898261c 181intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 182{
cd9dde44 183 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 184}
185
fe27d53e
DA		 186static int
187intel_dp_max_data_rate(int max_link_clock, int max_lanes)
188{
189 return (max_link_clock * max_lanes * 8) / 10;
190}
191
c19de8eb 192static enum drm_mode_status
a4fc5ed6
KP		 193intel_dp_mode_valid(struct drm_connector *connector,
194 struct drm_display_mode *mode)
195{
df0e9248 196 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 197 struct intel_connector *intel_connector = to_intel_connector(connector);
198 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 199 int target_clock = mode->clock;
200 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 201
dd06f90e
JN		 202 if (is_edp(intel_dp) && fixed_mode) {
203 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 204 return MODE_PANEL;
205
dd06f90e 206 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 207 return MODE_PANEL;
03afc4a2
DV		 208
209 target_clock = fixed_mode->clock;
7de56f43
ZY		 210 }
211
36008365 212 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 213 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 214
215 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
216 mode_rate = intel_dp_link_required(target_clock, 18);
217
218 if (mode_rate > max_rate)
c4867936 219 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 220
221 if (mode->clock < 10000)
222 return MODE_CLOCK_LOW;
223
0af78a2b
DV		 224 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
225 return MODE_H_ILLEGAL;
226
a4fc5ed6
KP		 227 return MODE_OK;
228}
229
a4f1289e 230uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 231{
232 int i;
233 uint32_t v = 0;
234
235 if (src_bytes > 4)
236 src_bytes = 4;
237 for (i = 0; i < src_bytes; i++)
238 v |= ((uint32_t) src[i]) << ((3-i) * 8);
239 return v;
240}
241
a4f1289e 242void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
961a0db0
VS		 324static void
325vlv_power_sequencer_kick(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 331 bool pll_enabled;
961a0db0
VS		 332 uint32_t DP;
333
334 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
335 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
336 pipe_name(pipe), port_name(intel_dig_port->port)))
337 return;
338
339 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
340 pipe_name(pipe), port_name(intel_dig_port->port));
341
342 /* Preserve the BIOS-computed detected bit. This is
343 * supposed to be read-only.
344 */
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
346 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
347 DP |= DP_PORT_WIDTH(1);
348 DP |= DP_LINK_TRAIN_PAT_1;
349
350 if (IS_CHERRYVIEW(dev))
351 DP |= DP_PIPE_SELECT_CHV(pipe);
352 else if (pipe == PIPE_B)
353 DP |= DP_PIPEB_SELECT;
354
d288f65f
VS		 355 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
356
357 /*
358 * The DPLL for the pipe must be enabled for this to work.
359 * So enable temporarily it if it's not already enabled.
360 */
361 if (!pll_enabled)
362 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
364
961a0db0
VS		 365 /*
366 * Similar magic as in intel_dp_enable_port().
367 * We _must_ do this port enable + disable trick
368 * to make this power seqeuencer lock onto the port.
369 * Otherwise even VDD force bit won't work.
370 */
371 I915_WRITE(intel_dp->output_reg, DP);
372 POSTING_READ(intel_dp->output_reg);
373
374 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
375 POSTING_READ(intel_dp->output_reg);
376
377 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
378 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 379
380 if (!pll_enabled)
381 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 382}
383
bf13e81b
JN		 384static enum pipe
385vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
386{
387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 388 struct drm_device *dev = intel_dig_port->base.base.dev;
389 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 390 struct intel_encoder *encoder;
391 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 392 enum pipe pipe;
bf13e81b 393
e39b999a 394 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 395
a8c3344e
VS		 396 /* We should never land here with regular DP ports */
397 WARN_ON(!is_edp(intel_dp));
398
a4a5d2f8
VS		 399 if (intel_dp->pps_pipe != INVALID_PIPE)
400 return intel_dp->pps_pipe;
401
402 /*
403 * We don't have power sequencer currently.
404 * Pick one that's not used by other ports.
405 */
406 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
407 base.head) {
408 struct intel_dp *tmp;
409
410 if (encoder->type != INTEL_OUTPUT_EDP)
411 continue;
412
413 tmp = enc_to_intel_dp(&encoder->base);
414
415 if (tmp->pps_pipe != INVALID_PIPE)
416 pipes &= ~(1 << tmp->pps_pipe);
417 }
418
419 /*
420 * Didn't find one. This should not happen since there
421 * are two power sequencers and up to two eDP ports.
422 */
423 if (WARN_ON(pipes == 0))
a8c3344e
VS		 424 pipe = PIPE_A;
425 else
426 pipe = ffs(pipes) - 1;
a4a5d2f8 427
a8c3344e
VS		 428 vlv_steal_power_sequencer(dev, pipe);
429 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 430
431 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
432 pipe_name(intel_dp->pps_pipe),
433 port_name(intel_dig_port->port));
434
435 /* init power sequencer on this pipe and port */
36b5f425
VS		 436 intel_dp_init_panel_power_sequencer(dev, intel_dp);
437 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 438
961a0db0
VS		 439 /*
440 * Even vdd force doesn't work until we've made
441 * the power sequencer lock in on the port.
442 */
443 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 444
445 return intel_dp->pps_pipe;
446}
447
6491ab27
VS		 448typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
449 enum pipe pipe);
450
451static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
452 enum pipe pipe)
453{
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
455}
456
457static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
461}
462
463static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return true;
467}
bf13e81b 468
a4a5d2f8 469static enum pipe
6491ab27
VS		 470vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
471 enum port port,
472 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 473{
474 enum pipe pipe;
bf13e81b 475
bf13e81b
JN		 476 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
477 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
478 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 479
480 if (port_sel != PANEL_PORT_SELECT_VLV(port))
481 continue;
482
6491ab27
VS		 483 if (!pipe_check(dev_priv, pipe))
484 continue;
485
a4a5d2f8 486 return pipe;
bf13e81b
JN		 487 }
488
a4a5d2f8
VS		 489 return INVALID_PIPE;
490}
491
492static void
493vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
494{
495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
496 struct drm_device *dev = intel_dig_port->base.base.dev;
497 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 498 enum port port = intel_dig_port->port;
499
500 lockdep_assert_held(&dev_priv->pps_mutex);
501
502 /* try to find a pipe with this port selected */
6491ab27
VS		 503 /* first pick one where the panel is on */
504 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
505 vlv_pipe_has_pp_on);
506 /* didn't find one? pick one where vdd is on */
507 if (intel_dp->pps_pipe == INVALID_PIPE)
508 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
509 vlv_pipe_has_vdd_on);
510 /* didn't find one? pick one with just the correct port */
511 if (intel_dp->pps_pipe == INVALID_PIPE)
512 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
513 vlv_pipe_any);
a4a5d2f8
VS		 514
515 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
516 if (intel_dp->pps_pipe == INVALID_PIPE) {
517 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
518 port_name(port));
519 return;
bf13e81b
JN		 520 }
521
a4a5d2f8
VS		 522 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
523 port_name(port), pipe_name(intel_dp->pps_pipe));
524
36b5f425
VS		 525 intel_dp_init_panel_power_sequencer(dev, intel_dp);
526 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 527}
528
773538e8
VS		 529void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
530{
531 struct drm_device *dev = dev_priv->dev;
532 struct intel_encoder *encoder;
533
534 if (WARN_ON(!IS_VALLEYVIEW(dev)))
535 return;
536
537 /*
538 * We can't grab pps_mutex here due to deadlock with power_domain
539 * mutex when power_domain functions are called while holding pps_mutex.
540 * That also means that in order to use pps_pipe the code needs to
541 * hold both a power domain reference and pps_mutex, and the power domain
542 * reference get/put must be done while _not_ holding pps_mutex.
543 * pps_{lock,unlock}() do these steps in the correct order, so one
544 * should use them always.
545 */
546
547 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
548 struct intel_dp *intel_dp;
549
550 if (encoder->type != INTEL_OUTPUT_EDP)
551 continue;
552
553 intel_dp = enc_to_intel_dp(&encoder->base);
554 intel_dp->pps_pipe = INVALID_PIPE;
555 }
bf13e81b
JN		 556}
557
558static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
562 if (HAS_PCH_SPLIT(dev))
563 return PCH_PP_CONTROL;
564 else
565 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
566}
567
568static u32 _pp_stat_reg(struct intel_dp *intel_dp)
569{
570 struct drm_device *dev = intel_dp_to_dev(intel_dp);
571
572 if (HAS_PCH_SPLIT(dev))
573 return PCH_PP_STATUS;
574 else
575 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
576}
577
01527b31
CT		 578/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
579 This function only applicable when panel PM state is not to be tracked */
580static int edp_notify_handler(struct notifier_block *this, unsigned long code,
581 void *unused)
582{
583 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
584 edp_notifier);
585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
586 struct drm_i915_private *dev_priv = dev->dev_private;
587 u32 pp_div;
588 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 589
590 if (!is_edp(intel_dp) || code != SYS_RESTART)
591 return 0;
592
773538e8 593 pps_lock(intel_dp);
e39b999a 594
01527b31 595 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 596 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
597
01527b31
CT		 598 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
599 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
600 pp_div = I915_READ(pp_div_reg);
601 pp_div &= PP_REFERENCE_DIVIDER_MASK;
602
603 /* 0x1F write to PP_DIV_REG sets max cycle delay */
604 I915_WRITE(pp_div_reg, pp_div | 0x1F);
605 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
606 msleep(intel_dp->panel_power_cycle_delay);
607 }
608
773538e8 609 pps_unlock(intel_dp);
e39b999a 610
01527b31
CT		 611 return 0;
612}
613
4be73780 614static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 615{
30add22d 616 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 617 struct drm_i915_private *dev_priv = dev->dev_private;
618
e39b999a
VS		 619 lockdep_assert_held(&dev_priv->pps_mutex);
620
9a42356b
VS		 621 if (IS_VALLEYVIEW(dev) &&
622 intel_dp->pps_pipe == INVALID_PIPE)
623 return false;
624
bf13e81b 625 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 626}
627
4be73780 628static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 629{
30add22d 630 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 631 struct drm_i915_private *dev_priv = dev->dev_private;
632
e39b999a
VS		 633 lockdep_assert_held(&dev_priv->pps_mutex);
634
9a42356b
VS		 635 if (IS_VALLEYVIEW(dev) &&
636 intel_dp->pps_pipe == INVALID_PIPE)
637 return false;
638
773538e8 639 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 640}
641
9b984dae
KP		 642static void
643intel_dp_check_edp(struct intel_dp *intel_dp)
644{
30add22d 645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 646 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 647
9b984dae
KP		 648 if (!is_edp(intel_dp))
649 return;
453c5420 650
4be73780 651 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 652 WARN(1, "eDP powered off while attempting aux channel communication.\n");
653 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 654 I915_READ(_pp_stat_reg(intel_dp)),
655 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 656 }
657}
658
9ee32fea
DV		 659static uint32_t
660intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
661{
662 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
663 struct drm_device *dev = intel_dig_port->base.base.dev;
664 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 665 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 666 uint32_t status;
667 bool done;
668
ef04f00d 669#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 670 if (has_aux_irq)
b18ac466 671 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 672 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 673 else
674 done = wait_for_atomic(C, 10) == 0;
675 if (!done)
676 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
677 has_aux_irq);
678#undef C
679
680 return status;
681}
682
ec5b01dd 683static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 684{
174edf1f
PZ		 685 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
686 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 687
ec5b01dd
DL		 688 /*
689 * The clock divider is based off the hrawclk, and would like to run at
690 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 691 */
ec5b01dd
DL		 692 return index ? 0 : intel_hrawclk(dev) / 2;
693}
694
695static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
696{
697 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
698 struct drm_device *dev = intel_dig_port->base.base.dev;
699
700 if (index)
701 return 0;
702
703 if (intel_dig_port->port == PORT_A) {
704 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 705 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 706 else
b84a1cf8 707 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 708 } else {
709 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
710 }
711}
712
713static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
714{
715 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
716 struct drm_device *dev = intel_dig_port->base.base.dev;
717 struct drm_i915_private *dev_priv = dev->dev_private;
718
719 if (intel_dig_port->port == PORT_A) {
720 if (index)
721 return 0;
722 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 723 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
724 /* Workaround for non-ULT HSW */
bc86625a
CW		 725 switch (index) {
726 case 0: return 63;
727 case 1: return 72;
728 default: return 0;
729 }
ec5b01dd 730 } else {
bc86625a 731 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 732 }
b84a1cf8
RV		 733}
734
ec5b01dd
DL		 735static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
736{
737 return index ? 0 : 100;
738}
739
b6b5e383
DL		 740static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
741{
742 /*
743 * SKL doesn't need us to program the AUX clock divider (Hardware will
744 * derive the clock from CDCLK automatically). We still implement the
745 * get_aux_clock_divider vfunc to plug-in into the existing code.
746 */
747 return index ? 0 : 1;
748}
749
5ed12a19
DL		 750static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
751 bool has_aux_irq,
752 int send_bytes,
753 uint32_t aux_clock_divider)
754{
755 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
756 struct drm_device *dev = intel_dig_port->base.base.dev;
757 uint32_t precharge, timeout;
758
759 if (IS_GEN6(dev))
760 precharge = 3;
761 else
762 precharge = 5;
763
764 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
765 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
766 else
767 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
768
769 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 770 DP_AUX_CH_CTL_DONE |
5ed12a19 771 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 772 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 773 timeout |
788d4433 774 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 775 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
776 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 777 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 778}
779
b9ca5fad
DL		 780static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
781 bool has_aux_irq,
782 int send_bytes,
783 uint32_t unused)
784{
785 return DP_AUX_CH_CTL_SEND_BUSY |
786 DP_AUX_CH_CTL_DONE |
787 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788 DP_AUX_CH_CTL_TIME_OUT_ERROR |
789 DP_AUX_CH_CTL_TIME_OUT_1600us |
790 DP_AUX_CH_CTL_RECEIVE_ERROR |
791 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
792 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
793}
794
b84a1cf8
RV		 795static int
796intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 797 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 798 uint8_t *recv, int recv_size)
799{
800 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
801 struct drm_device *dev = intel_dig_port->base.base.dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
804 uint32_t ch_data = ch_ctl + 4;
bc86625a 805 uint32_t aux_clock_divider;
b84a1cf8
RV		 806 int i, ret, recv_bytes;
807 uint32_t status;
5ed12a19 808 int try, clock = 0;
4e6b788c 809 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 810 bool vdd;
811
773538e8 812 pps_lock(intel_dp);
e39b999a 813
72c3500a
VS		 814 /*
815 * We will be called with VDD already enabled for dpcd/edid/oui reads.
816 * In such cases we want to leave VDD enabled and it's up to upper layers
817 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
818 * ourselves.
819 */
1e0560e0 820 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 821
822 /* dp aux is extremely sensitive to irq latency, hence request the
823 * lowest possible wakeup latency and so prevent the cpu from going into
824 * deep sleep states.
825 */
826 pm_qos_update_request(&dev_priv->pm_qos, 0);
827
828 intel_dp_check_edp(intel_dp);
5eb08b69 829
c67a470b
PZ		 830 intel_aux_display_runtime_get(dev_priv);
831
11bee43e
JB		 832 /* Try to wait for any previous AUX channel activity */
833 for (try = 0; try < 3; try++) {
ef04f00d 834 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 835 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
836 break;
837 msleep(1);
838 }
839
840 if (try == 3) {
841 WARN(1, "dp_aux_ch not started status 0x%08x\n",
842 I915_READ(ch_ctl));
9ee32fea
DV		 843 ret = -EBUSY;
844 goto out;
4f7f7b7e
CW		 845 }
846
46a5ae9f
PZ		 847 /* Only 5 data registers! */
848 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
849 ret = -E2BIG;
850 goto out;
851 }
852
ec5b01dd 853 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 854 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
855 has_aux_irq,
856 send_bytes,
857 aux_clock_divider);
5ed12a19 858
bc86625a
CW		 859 /* Must try at least 3 times according to DP spec */
860 for (try = 0; try < 5; try++) {
861 /* Load the send data into the aux channel data registers */
862 for (i = 0; i < send_bytes; i += 4)
863 I915_WRITE(ch_data + i,
a4f1289e
RV		 864 intel_dp_pack_aux(send + i,
865 send_bytes - i));
bc86625a
CW		 866
867 /* Send the command and wait for it to complete */
5ed12a19 868 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 869
870 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
871
872 /* Clear done status and any errors */
873 I915_WRITE(ch_ctl,
874 status |
875 DP_AUX_CH_CTL_DONE |
876 DP_AUX_CH_CTL_TIME_OUT_ERROR |
877 DP_AUX_CH_CTL_RECEIVE_ERROR);
878
879 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
880 DP_AUX_CH_CTL_RECEIVE_ERROR))
881 continue;
882 if (status & DP_AUX_CH_CTL_DONE)
883 break;
884 }
4f7f7b7e 885 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 886 break;
887 }
888
a4fc5ed6 889 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 890 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 891 ret = -EBUSY;
892 goto out;
a4fc5ed6
KP		 893 }
894
895 /* Check for timeout or receive error.
896 * Timeouts occur when the sink is not connected
897 */
a5b3da54 898 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 899 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 900 ret = -EIO;
901 goto out;
a5b3da54 902 }
1ae8c0a5
KP		 903
904 /* Timeouts occur when the device isn't connected, so they're
905 * "normal" -- don't fill the kernel log with these */
a5b3da54 906 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 907 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 908 ret = -ETIMEDOUT;
909 goto out;
a4fc5ed6
KP		 910 }
911
912 /* Unload any bytes sent back from the other side */
913 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
914 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 915 if (recv_bytes > recv_size)
916 recv_bytes = recv_size;
0206e353 917
4f7f7b7e 918 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 919 intel_dp_unpack_aux(I915_READ(ch_data + i),
920 recv + i, recv_bytes - i);
a4fc5ed6 921
9ee32fea
DV		 922 ret = recv_bytes;
923out:
924 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 925 intel_aux_display_runtime_put(dev_priv);
9ee32fea 926
884f19e9
JN		 927 if (vdd)
928 edp_panel_vdd_off(intel_dp, false);
929
773538e8 930 pps_unlock(intel_dp);
e39b999a 931
9ee32fea 932 return ret;
a4fc5ed6
KP		 933}
934
a6c8aff0
JN		 935#define BARE_ADDRESS_SIZE 3
936#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 937static ssize_t
938intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 939{
9d1a1031
JN		 940 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
941 uint8_t txbuf[20], rxbuf[20];
942 size_t txsize, rxsize;
a4fc5ed6 943 int ret;
a4fc5ed6 944
9d1a1031
JN		 945 txbuf[0] = msg->request << 4;
946 txbuf[1] = msg->address >> 8;
947 txbuf[2] = msg->address & 0xff;
948 txbuf[3] = msg->size - 1;
46a5ae9f 949
9d1a1031
JN		 950 switch (msg->request & ~DP_AUX_I2C_MOT) {
951 case DP_AUX_NATIVE_WRITE:
952 case DP_AUX_I2C_WRITE:
a6c8aff0 953 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 954 rxsize = 1;
f51a44b9 955
9d1a1031
JN		 956 if (WARN_ON(txsize > 20))
957 return -E2BIG;
a4fc5ed6 958
9d1a1031 959 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 960
9d1a1031
JN		 961 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
962 if (ret > 0) {
963 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 964
9d1a1031
JN		 965 /* Return payload size. */
966 ret = msg->size;
967 }
968 break;
46a5ae9f 969
9d1a1031
JN		 970 case DP_AUX_NATIVE_READ:
971 case DP_AUX_I2C_READ:
a6c8aff0 972 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 973 rxsize = msg->size + 1;
a4fc5ed6 974
9d1a1031
JN		 975 if (WARN_ON(rxsize > 20))
976 return -E2BIG;
a4fc5ed6 977
9d1a1031
JN		 978 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
979 if (ret > 0) {
980 msg->reply = rxbuf[0] >> 4;
981 /*
982 * Assume happy day, and copy the data. The caller is
983 * expected to check msg->reply before touching it.
984 *
985 * Return payload size.
986 */
987 ret--;
988 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 989 }
9d1a1031
JN		 990 break;
991
992 default:
993 ret = -EINVAL;
994 break;
a4fc5ed6 995 }
f51a44b9 996
9d1a1031 997 return ret;
a4fc5ed6
KP		 998}
999
9d1a1031
JN		 1000static void
1001intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1002{
1003 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1004 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1005 enum port port = intel_dig_port->port;
0b99836f 1006 const char *name = NULL;
ab2c0672
DA		 1007 int ret;
1008
33ad6626
JN		 1009 switch (port) {
1010 case PORT_A:
1011 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1012 name = "DPDDC-A";
ab2c0672 1013 break;
33ad6626
JN		 1014 case PORT_B:
1015 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1016 name = "DPDDC-B";
ab2c0672 1017 break;
33ad6626
JN		 1018 case PORT_C:
1019 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1020 name = "DPDDC-C";
ab2c0672 1021 break;
33ad6626
JN		 1022 case PORT_D:
1023 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1024 name = "DPDDC-D";
33ad6626
JN		 1025 break;
1026 default:
1027 BUG();
ab2c0672
DA		 1028 }
1029
1b1aad75
DL		 1030 /*
1031 * The AUX_CTL register is usually DP_CTL + 0x10.
1032 *
1033 * On Haswell and Broadwell though:
1034 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1035 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1036 *
1037 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1038 */
1039 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1040 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1041
0b99836f 1042 intel_dp->aux.name = name;
9d1a1031
JN		 1043 intel_dp->aux.dev = dev->dev;
1044 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1045
0b99836f
JN		 1046 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1047 connector->base.kdev->kobj.name);
8316f337 1048
4f71d0cb 1049 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1050 if (ret < 0) {
4f71d0cb 1051 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1052 name, ret);
1053 return;
ab2c0672 1054 }
8a5e6aeb 1055
0b99836f
JN		 1056 ret = sysfs_create_link(&connector->base.kdev->kobj,
1057 &intel_dp->aux.ddc.dev.kobj,
1058 intel_dp->aux.ddc.dev.kobj.name);
1059 if (ret < 0) {
1060 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1061 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1062 }
a4fc5ed6
KP		 1063}
1064
80f65de3
ID		 1065static void
1066intel_dp_connector_unregister(struct intel_connector *intel_connector)
1067{
1068 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1069
0e32b39c
DA		 1070 if (!intel_connector->mst_port)
1071 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1072 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1073 intel_connector_unregister(intel_connector);
1074}
1075
5416d871 1076static void
5cec258b 1077skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
5416d871
DL		 1078{
1079 u32 ctrl1;
1080
1081 pipe_config->ddi_pll_sel = SKL_DPLL0;
1082 pipe_config->dpll_hw_state.cfgcr1 = 0;
1083 pipe_config->dpll_hw_state.cfgcr2 = 0;
1084
1085 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1086 switch (link_bw) {
1087 case DP_LINK_BW_1_62:
1088 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
1089 SKL_DPLL0);
1090 break;
1091 case DP_LINK_BW_2_7:
1092 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
1093 SKL_DPLL0);
1094 break;
1095 case DP_LINK_BW_5_4:
1096 ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
1097 SKL_DPLL0);
1098 break;
1099 }
1100 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1101}
1102
0e50338c 1103static void
5cec258b 1104hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c
DV		 1105{
1106 switch (link_bw) {
1107 case DP_LINK_BW_1_62:
1108 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1109 break;
1110 case DP_LINK_BW_2_7:
1111 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1112 break;
1113 case DP_LINK_BW_5_4:
1114 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1115 break;
1116 }
1117}
1118
c6bb3538
DV		 1119static void
1120intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1121 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1122{
1123 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1124 const struct dp_link_dpll *divisor = NULL;
1125 int i, count = 0;
c6bb3538
DV		 1126
1127 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1128 divisor = gen4_dpll;
1129 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1130 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1131 divisor = pch_dpll;
1132 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1133 } else if (IS_CHERRYVIEW(dev)) {
1134 divisor = chv_dpll;
1135 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1136 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1137 divisor = vlv_dpll;
1138 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1139 }
9dd4ffdf
CML		 1140
1141 if (divisor && count) {
1142 for (i = 0; i < count; i++) {
1143 if (link_bw == divisor[i].link_bw) {
1144 pipe_config->dpll = divisor[i].dpll;
1145 pipe_config->clock_set = true;
1146 break;
1147 }
1148 }
c6bb3538
DV		 1149 }
1150}
1151
00c09d70 1152bool
5bfe2ac0 1153intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1154 struct intel_crtc_state *pipe_config)
a4fc5ed6 1155{
5bfe2ac0 1156 struct drm_device *dev = encoder->base.dev;
36008365 1157 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1158 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1159 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1160 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1161 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1162 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1163 int lane_count, clock;
56071a20 1164 int min_lane_count = 1;
eeb6324d 1165 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1166 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1167 int min_clock = 0;
06ea66b6 1168 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1169 int bpp, mode_rate;
06ea66b6 1170 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1171 int link_avail, link_clock;
a4fc5ed6 1172
bc7d38a4 1173 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1174 pipe_config->has_pch_encoder = true;
1175
03afc4a2 1176 pipe_config->has_dp_encoder = true;
f769cd24 1177 pipe_config->has_drrs = false;
9ed109a7 1178 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1179
dd06f90e
JN		 1180 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1181 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1182 adjusted_mode);
2dd24552
JB		 1183 if (!HAS_PCH_SPLIT(dev))
1184 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1185 intel_connector->panel.fitting_mode);
1186 else
b074cec8
JB		 1187 intel_pch_panel_fitting(intel_crtc, pipe_config,
1188 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1189 }
1190
cb1793ce 1191 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1192 return false;
1193
083f9560
DV		 1194 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1195 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1196 max_lane_count, bws[max_clock],
1197 adjusted_mode->crtc_clock);
083f9560 1198
36008365
DV		 1199 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1200 * bpc in between. */
3e7ca985 1201 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1202 if (is_edp(intel_dp)) {
1203 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1204 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1205 dev_priv->vbt.edp_bpp);
1206 bpp = dev_priv->vbt.edp_bpp;
1207 }
1208
344c5bbc
JN		 1209 /*
1210 * Use the maximum clock and number of lanes the eDP panel
1211 * advertizes being capable of. The panels are generally
1212 * designed to support only a single clock and lane
1213 * configuration, and typically these values correspond to the
1214 * native resolution of the panel.
1215 */
1216 min_lane_count = max_lane_count;
1217 min_clock = max_clock;
7984211e 1218 }
657445fe 1219
36008365 1220 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1221 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1222 bpp);
36008365 1223
c6930992
DA		 1224 for (clock = min_clock; clock <= max_clock; clock++) {
1225 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1226 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1227 link_avail = intel_dp_max_data_rate(link_clock,
1228 lane_count);
1229
1230 if (mode_rate <= link_avail) {
1231 goto found;
1232 }
1233 }
1234 }
1235 }
c4867936 1236
36008365 1237 return false;
3685a8f3 1238
36008365 1239found:
55bc60db
VS		 1240 if (intel_dp->color_range_auto) {
1241 /*
1242 * See:
1243 * CEA-861-E - 5.1 Default Encoding Parameters
1244 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1245 */
18316c8c 1246 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1247 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1248 else
1249 intel_dp->color_range = 0;
1250 }
1251
3685a8f3 1252 if (intel_dp->color_range)
50f3b016 1253 pipe_config->limited_color_range = true;
a4fc5ed6 1254
36008365
DV		 1255 intel_dp->link_bw = bws[clock];
1256 intel_dp->lane_count = lane_count;
657445fe 1257 pipe_config->pipe_bpp = bpp;
ff9a6750 1258 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1259
36008365
DV		 1260 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1261 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1262 pipe_config->port_clock, bpp);
36008365
DV		 1263 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1264 mode_rate, link_avail);
a4fc5ed6 1265
03afc4a2 1266 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1267 adjusted_mode->crtc_clock,
1268 pipe_config->port_clock,
03afc4a2 1269 &pipe_config->dp_m_n);
9d1a455b 1270
439d7ac0 1271 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1272 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1273 pipe_config->has_drrs = true;
439d7ac0
PB		 1274 intel_link_compute_m_n(bpp, lane_count,
1275 intel_connector->panel.downclock_mode->clock,
1276 pipe_config->port_clock,
1277 &pipe_config->dp_m2_n2);
1278 }
1279
5416d871
DL		 1280 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
1281 skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
1282 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1283 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1284 else
1285 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1286
03afc4a2 1287 return true;
a4fc5ed6
KP		 1288}
1289
7c62a164 1290static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1291{
7c62a164
DV		 1292 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1293 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1294 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 u32 dpa_ctl;
1297
6e3c9717
ACO		 1298 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1299 crtc->config->port_clock);
ea9b6006
DV		 1300 dpa_ctl = I915_READ(DP_A);
1301 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1302
6e3c9717 1303 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1304 /* For a long time we've carried around a ILK-DevA w/a for the
1305 * 160MHz clock. If we're really unlucky, it's still required.
1306 */
1307 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1308 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1309 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1310 } else {
1311 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1312 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1313 }
1ce17038 1314
ea9b6006
DV		 1315 I915_WRITE(DP_A, dpa_ctl);
1316
1317 POSTING_READ(DP_A);
1318 udelay(500);
1319}
1320
8ac33ed3 1321static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1322{
b934223d 1323 struct drm_device *dev = encoder->base.dev;
417e822d 1324 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1325 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1326 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1327 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1328 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1329
417e822d 1330 /*
1a2eb460 1331 * There are four kinds of DP registers:
417e822d
KP		 1332 *
1333 * IBX PCH
1a2eb460
KP		 1334 * SNB CPU
1335 * IVB CPU
417e822d
KP		 1336 * CPT PCH
1337 *
1338 * IBX PCH and CPU are the same for almost everything,
1339 * except that the CPU DP PLL is configured in this
1340 * register
1341 *
1342 * CPT PCH is quite different, having many bits moved
1343 * to the TRANS_DP_CTL register instead. That
1344 * configuration happens (oddly) in ironlake_pch_enable
1345 */
9c9e7927 1346
417e822d
KP		 1347 /* Preserve the BIOS-computed detected bit. This is
1348 * supposed to be read-only.
1349 */
1350 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1351
417e822d 1352 /* Handle DP bits in common between all three register formats */
417e822d 1353 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1354 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1355
6e3c9717 1356 if (crtc->config->has_audio)
ea5b213a 1357 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1358
417e822d 1359 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1360
bc7d38a4 1361 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1362 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1363 intel_dp->DP |= DP_SYNC_HS_HIGH;
1364 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1365 intel_dp->DP |= DP_SYNC_VS_HIGH;
1366 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1367
6aba5b6c 1368 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1369 intel_dp->DP |= DP_ENHANCED_FRAMING;
1370
7c62a164 1371 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1372 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1373 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1374 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1375
1376 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1377 intel_dp->DP |= DP_SYNC_HS_HIGH;
1378 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1379 intel_dp->DP |= DP_SYNC_VS_HIGH;
1380 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1381
6aba5b6c 1382 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1383 intel_dp->DP |= DP_ENHANCED_FRAMING;
1384
44f37d1f
CML		 1385 if (!IS_CHERRYVIEW(dev)) {
1386 if (crtc->pipe == 1)
1387 intel_dp->DP |= DP_PIPEB_SELECT;
1388 } else {
1389 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1390 }
417e822d
KP		 1391 } else {
1392 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1393 }
a4fc5ed6
KP		 1394}
1395
ffd6749d
PZ		 1396#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1397#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1398
1a5ef5b7
PZ		 1399#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1400#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1401
ffd6749d
PZ		 1402#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1403#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1404
4be73780 1405static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1406 u32 mask,
1407 u32 value)
bd943159 1408{
30add22d 1409 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1410 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1411 u32 pp_stat_reg, pp_ctrl_reg;
1412
e39b999a
VS		 1413 lockdep_assert_held(&dev_priv->pps_mutex);
1414
bf13e81b
JN		 1415 pp_stat_reg = _pp_stat_reg(intel_dp);
1416 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1417
99ea7127 1418 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1419 mask, value,
1420 I915_READ(pp_stat_reg),
1421 I915_READ(pp_ctrl_reg));
32ce697c 1422
453c5420 1423 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1424 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1425 I915_READ(pp_stat_reg),
1426 I915_READ(pp_ctrl_reg));
32ce697c 1427 }
54c136d4
CW		 1428
1429 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1430}
32ce697c 1431
4be73780 1432static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1433{
1434 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1435 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1436}
1437
4be73780 1438static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1439{
1440 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1441 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1442}
1443
4be73780 1444static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1445{
1446 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1447
1448 /* When we disable the VDD override bit last we have to do the manual
1449 * wait. */
1450 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1451 intel_dp->panel_power_cycle_delay);
1452
4be73780 1453 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1454}
1455
4be73780 1456static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1457{
1458 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1459 intel_dp->backlight_on_delay);
1460}
1461
4be73780 1462static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1463{
1464 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1465 intel_dp->backlight_off_delay);
1466}
99ea7127 1467
832dd3c1
KP		 1468/* Read the current pp_control value, unlocking the register if it
1469 * is locked
1470 */
1471
453c5420 1472static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1473{
453c5420
JB		 1474 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1475 struct drm_i915_private *dev_priv = dev->dev_private;
1476 u32 control;
832dd3c1 1477
e39b999a
VS		 1478 lockdep_assert_held(&dev_priv->pps_mutex);
1479
bf13e81b 1480 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1481 control &= ~PANEL_UNLOCK_MASK;
1482 control |= PANEL_UNLOCK_REGS;
1483 return control;
bd943159
KP		 1484}
1485
951468f3
VS		 1486/*
1487 * Must be paired with edp_panel_vdd_off().
1488 * Must hold pps_mutex around the whole on/off sequence.
1489 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1490 */
1e0560e0 1491static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1492{
30add22d 1493 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1495 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1496 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1497 enum intel_display_power_domain power_domain;
5d613501 1498 u32 pp;
453c5420 1499 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1500 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1501
e39b999a
VS		 1502 lockdep_assert_held(&dev_priv->pps_mutex);
1503
97af61f5 1504 if (!is_edp(intel_dp))
adddaaf4 1505 return false;
bd943159 1506
2c623c11 1507 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1508 intel_dp->want_panel_vdd = true;
99ea7127 1509
4be73780 1510 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1511 return need_to_disable;
b0665d57 1512
4e6e1a54
ID		 1513 power_domain = intel_display_port_power_domain(intel_encoder);
1514 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1515
3936fcf4
VS		 1516 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1517 port_name(intel_dig_port->port));
bd943159 1518
4be73780
DV		 1519 if (!edp_have_panel_power(intel_dp))
1520 wait_panel_power_cycle(intel_dp);
99ea7127 1521
453c5420 1522 pp = ironlake_get_pp_control(intel_dp);
5d613501 1523 pp |= EDP_FORCE_VDD;
ebf33b18 1524
bf13e81b
JN		 1525 pp_stat_reg = _pp_stat_reg(intel_dp);
1526 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1527
1528 I915_WRITE(pp_ctrl_reg, pp);
1529 POSTING_READ(pp_ctrl_reg);
1530 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1531 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1532 /*
1533 * If the panel wasn't on, delay before accessing aux channel
1534 */
4be73780 1535 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1536 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1537 port_name(intel_dig_port->port));
f01eca2e 1538 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1539 }
adddaaf4
JN		 1540
1541 return need_to_disable;
1542}
1543
951468f3
VS		 1544/*
1545 * Must be paired with intel_edp_panel_vdd_off() or
1546 * intel_edp_panel_off().
1547 * Nested calls to these functions are not allowed since
1548 * we drop the lock. Caller must use some higher level
1549 * locking to prevent nested calls from other threads.
1550 */
b80d6c78 1551void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1552{
c695b6b6 1553 bool vdd;
adddaaf4 1554
c695b6b6
VS		 1555 if (!is_edp(intel_dp))
1556 return;
1557
773538e8 1558 pps_lock(intel_dp);
c695b6b6 1559 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1560 pps_unlock(intel_dp);
c695b6b6 1561
e2c719b7 1562 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1563 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1564}
1565
4be73780 1566static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1567{
30add22d 1568 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1569 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1570 struct intel_digital_port *intel_dig_port =
1571 dp_to_dig_port(intel_dp);
1572 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1573 enum intel_display_power_domain power_domain;
5d613501 1574 u32 pp;
453c5420 1575 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1576
e39b999a 1577 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1578
15e899a0 1579 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1580
15e899a0 1581 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1582 return;
b0665d57 1583
3936fcf4
VS		 1584 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1585 port_name(intel_dig_port->port));
bd943159 1586
be2c9196
VS		 1587 pp = ironlake_get_pp_control(intel_dp);
1588 pp &= ~EDP_FORCE_VDD;
453c5420 1589
be2c9196
VS		 1590 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1591 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1592
be2c9196
VS		 1593 I915_WRITE(pp_ctrl_reg, pp);
1594 POSTING_READ(pp_ctrl_reg);
90791a5c 1595
be2c9196
VS		 1596 /* Make sure sequencer is idle before allowing subsequent activity */
1597 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1598 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1599
be2c9196
VS		 1600 if ((pp & POWER_TARGET_ON) == 0)
1601 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1602
be2c9196
VS		 1603 power_domain = intel_display_port_power_domain(intel_encoder);
1604 intel_display_power_put(dev_priv, power_domain);
bd943159 1605}
5d613501 1606
4be73780 1607static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1608{
1609 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1610 struct intel_dp, panel_vdd_work);
bd943159 1611
773538e8 1612 pps_lock(intel_dp);
15e899a0
VS		 1613 if (!intel_dp->want_panel_vdd)
1614 edp_panel_vdd_off_sync(intel_dp);
773538e8 1615 pps_unlock(intel_dp);
bd943159
KP		 1616}
1617
aba86890
ID		 1618static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1619{
1620 unsigned long delay;
1621
1622 /*
1623 * Queue the timer to fire a long time from now (relative to the power
1624 * down delay) to keep the panel power up across a sequence of
1625 * operations.
1626 */
1627 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1628 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1629}
1630
951468f3
VS		 1631/*
1632 * Must be paired with edp_panel_vdd_on().
1633 * Must hold pps_mutex around the whole on/off sequence.
1634 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1635 */
4be73780 1636static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1637{
e39b999a
VS		 1638 struct drm_i915_private *dev_priv =
1639 intel_dp_to_dev(intel_dp)->dev_private;
1640
1641 lockdep_assert_held(&dev_priv->pps_mutex);
1642
97af61f5
KP		 1643 if (!is_edp(intel_dp))
1644 return;
5d613501 1645
e2c719b7 1646 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1647 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1648
bd943159
KP		 1649 intel_dp->want_panel_vdd = false;
1650
aba86890 1651 if (sync)
4be73780 1652 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1653 else
1654 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1655}
1656
9f0fb5be 1657static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1658{
30add22d 1659 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1660 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1661 u32 pp;
453c5420 1662 u32 pp_ctrl_reg;
9934c132 1663
9f0fb5be
VS		 1664 lockdep_assert_held(&dev_priv->pps_mutex);
1665
97af61f5 1666 if (!is_edp(intel_dp))
bd943159 1667 return;
99ea7127 1668
3936fcf4
VS		 1669 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1670 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1671
e7a89ace
VS		 1672 if (WARN(edp_have_panel_power(intel_dp),
1673 "eDP port %c panel power already on\n",
1674 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1675 return;
9934c132 1676
4be73780 1677 wait_panel_power_cycle(intel_dp);
37c6c9b0 1678
bf13e81b 1679 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1680 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1681 if (IS_GEN5(dev)) {
1682 /* ILK workaround: disable reset around power sequence */
1683 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1684 I915_WRITE(pp_ctrl_reg, pp);
1685 POSTING_READ(pp_ctrl_reg);
05ce1a49 1686 }
37c6c9b0 1687
1c0ae80a 1688 pp |= POWER_TARGET_ON;
99ea7127
KP		 1689 if (!IS_GEN5(dev))
1690 pp |= PANEL_POWER_RESET;
1691
453c5420
JB		 1692 I915_WRITE(pp_ctrl_reg, pp);
1693 POSTING_READ(pp_ctrl_reg);
9934c132 1694
4be73780 1695 wait_panel_on(intel_dp);
dce56b3c 1696 intel_dp->last_power_on = jiffies;
9934c132 1697
05ce1a49
KP		 1698 if (IS_GEN5(dev)) {
1699 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1700 I915_WRITE(pp_ctrl_reg, pp);
1701 POSTING_READ(pp_ctrl_reg);
05ce1a49 1702 }
9f0fb5be 1703}
e39b999a 1704
9f0fb5be
VS		 1705void intel_edp_panel_on(struct intel_dp *intel_dp)
1706{
1707 if (!is_edp(intel_dp))
1708 return;
1709
1710 pps_lock(intel_dp);
1711 edp_panel_on(intel_dp);
773538e8 1712 pps_unlock(intel_dp);
9934c132
JB		 1713}
1714
9f0fb5be
VS		 1715
1716static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1717{
4e6e1a54
ID		 1718 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1719 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1720 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1721 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1722 enum intel_display_power_domain power_domain;
99ea7127 1723 u32 pp;
453c5420 1724 u32 pp_ctrl_reg;
9934c132 1725
9f0fb5be
VS		 1726 lockdep_assert_held(&dev_priv->pps_mutex);
1727
97af61f5
KP		 1728 if (!is_edp(intel_dp))
1729 return;
37c6c9b0 1730
3936fcf4
VS		 1731 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1732 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1733
3936fcf4
VS		 1734 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1735 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1736
453c5420 1737 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1738 /* We need to switch off panel power _and_ force vdd, for otherwise some
1739 * panels get very unhappy and cease to work. */
b3064154
PJ		 1740 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1741 EDP_BLC_ENABLE);
453c5420 1742
bf13e81b 1743 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1744
849e39f5
PZ		 1745 intel_dp->want_panel_vdd = false;
1746
453c5420
JB		 1747 I915_WRITE(pp_ctrl_reg, pp);
1748 POSTING_READ(pp_ctrl_reg);
9934c132 1749
dce56b3c 1750 intel_dp->last_power_cycle = jiffies;
4be73780 1751 wait_panel_off(intel_dp);
849e39f5
PZ		 1752
1753 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1754 power_domain = intel_display_port_power_domain(intel_encoder);
1755 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1756}
e39b999a 1757
9f0fb5be
VS		 1758void intel_edp_panel_off(struct intel_dp *intel_dp)
1759{
1760 if (!is_edp(intel_dp))
1761 return;
e39b999a 1762
9f0fb5be
VS		 1763 pps_lock(intel_dp);
1764 edp_panel_off(intel_dp);
773538e8 1765 pps_unlock(intel_dp);
9934c132
JB		 1766}
1767
1250d107
JN		 1768/* Enable backlight in the panel power control. */
1769static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1770{
da63a9f2
PZ		 1771 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1772 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 u32 pp;
453c5420 1775 u32 pp_ctrl_reg;
32f9d658 1776
01cb9ea6
JB		 1777 /*
1778 * If we enable the backlight right away following a panel power
1779 * on, we may see slight flicker as the panel syncs with the eDP
1780 * link. So delay a bit to make sure the image is solid before
1781 * allowing it to appear.
1782 */
4be73780 1783 wait_backlight_on(intel_dp);
e39b999a 1784
773538e8 1785 pps_lock(intel_dp);
e39b999a 1786
453c5420 1787 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1788 pp |= EDP_BLC_ENABLE;
453c5420 1789
bf13e81b 1790 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1791
1792 I915_WRITE(pp_ctrl_reg, pp);
1793 POSTING_READ(pp_ctrl_reg);
e39b999a 1794
773538e8 1795 pps_unlock(intel_dp);
32f9d658
ZW		 1796}
1797
1250d107
JN		 1798/* Enable backlight PWM and backlight PP control. */
1799void intel_edp_backlight_on(struct intel_dp *intel_dp)
1800{
1801 if (!is_edp(intel_dp))
1802 return;
1803
1804 DRM_DEBUG_KMS("\n");
1805
1806 intel_panel_enable_backlight(intel_dp->attached_connector);
1807 _intel_edp_backlight_on(intel_dp);
1808}
1809
1810/* Disable backlight in the panel power control. */
1811static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1812{
30add22d 1813 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1814 struct drm_i915_private *dev_priv = dev->dev_private;
1815 u32 pp;
453c5420 1816 u32 pp_ctrl_reg;
32f9d658 1817
f01eca2e
KP		 1818 if (!is_edp(intel_dp))
1819 return;
1820
773538e8 1821 pps_lock(intel_dp);
e39b999a 1822
453c5420 1823 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1824 pp &= ~EDP_BLC_ENABLE;
453c5420 1825
bf13e81b 1826 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1827
1828 I915_WRITE(pp_ctrl_reg, pp);
1829 POSTING_READ(pp_ctrl_reg);
f7d2323c 1830
773538e8 1831 pps_unlock(intel_dp);
e39b999a
VS		 1832
1833 intel_dp->last_backlight_off = jiffies;
f7d2323c 1834 edp_wait_backlight_off(intel_dp);
1250d107 1835}
f7d2323c 1836
1250d107
JN		 1837/* Disable backlight PP control and backlight PWM. */
1838void intel_edp_backlight_off(struct intel_dp *intel_dp)
1839{
1840 if (!is_edp(intel_dp))
1841 return;
1842
1843 DRM_DEBUG_KMS("\n");
f7d2323c 1844
1250d107 1845 _intel_edp_backlight_off(intel_dp);
f7d2323c 1846 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1847}
a4fc5ed6 1848
73580fb7
JN		 1849/*
1850 * Hook for controlling the panel power control backlight through the bl_power
1851 * sysfs attribute. Take care to handle multiple calls.
1852 */
1853static void intel_edp_backlight_power(struct intel_connector *connector,
1854 bool enable)
1855{
1856 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1857 bool is_enabled;
1858
773538e8 1859 pps_lock(intel_dp);
e39b999a 1860 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1861 pps_unlock(intel_dp);
73580fb7
JN		 1862
1863 if (is_enabled == enable)
1864 return;
1865
23ba9373
JN		 1866 DRM_DEBUG_KMS("panel power control backlight %s\n",
1867 enable ? "enable" : "disable");
73580fb7
JN		 1868
1869 if (enable)
1870 _intel_edp_backlight_on(intel_dp);
1871 else
1872 _intel_edp_backlight_off(intel_dp);
1873}
1874
2bd2ad64 1875static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1876{
da63a9f2
PZ		 1877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1878 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1879 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1880 struct drm_i915_private *dev_priv = dev->dev_private;
1881 u32 dpa_ctl;
1882
2bd2ad64
DV		 1883 assert_pipe_disabled(dev_priv,
1884 to_intel_crtc(crtc)->pipe);
1885
d240f20f
JB		 1886 DRM_DEBUG_KMS("\n");
1887 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1888 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1889 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1890
1891 /* We don't adjust intel_dp->DP while tearing down the link, to
1892 * facilitate link retraining (e.g. after hotplug). Hence clear all
1893 * enable bits here to ensure that we don't enable too much. */
1894 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1895 intel_dp->DP |= DP_PLL_ENABLE;
1896 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1897 POSTING_READ(DP_A);
1898 udelay(200);
d240f20f
JB		 1899}
1900
2bd2ad64 1901static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1902{
da63a9f2
PZ		 1903 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1904 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1905 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 u32 dpa_ctl;
1908
2bd2ad64
DV		 1909 assert_pipe_disabled(dev_priv,
1910 to_intel_crtc(crtc)->pipe);
1911
d240f20f 1912 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1913 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1914 "dp pll off, should be on\n");
1915 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1916
1917 /* We can't rely on the value tracked for the DP register in
1918 * intel_dp->DP because link_down must not change that (otherwise link
1919 * re-training will fail. */
298b0b39 1920 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1921 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1922 POSTING_READ(DP_A);
d240f20f
JB		 1923 udelay(200);
1924}
1925
c7ad3810 1926/* If the sink supports it, try to set the power state appropriately */
c19b0669 1927void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1928{
1929 int ret, i;
1930
1931 /* Should have a valid DPCD by this point */
1932 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1933 return;
1934
1935 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1936 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1937 DP_SET_POWER_D3);
c7ad3810
JB		 1938 } else {
1939 /*
1940 * When turning on, we need to retry for 1ms to give the sink
1941 * time to wake up.
1942 */
1943 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1944 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1945 DP_SET_POWER_D0);
c7ad3810
JB		 1946 if (ret == 1)
1947 break;
1948 msleep(1);
1949 }
1950 }
f9cac721
JN		 1951
1952 if (ret != 1)
1953 DRM_DEBUG_KMS("failed to %s sink power state\n",
1954 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1955}
1956
19d8fe15
DV		 1957static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1958 enum pipe *pipe)
d240f20f 1959{
19d8fe15 1960 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1961 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1962 struct drm_device *dev = encoder->base.dev;
1963 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1964 enum intel_display_power_domain power_domain;
1965 u32 tmp;
1966
1967 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1968 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1969 return false;
1970
1971 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1972
1973 if (!(tmp & DP_PORT_EN))
1974 return false;
1975
bc7d38a4 1976 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1977 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1978 } else if (IS_CHERRYVIEW(dev)) {
1979 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1980 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1981 *pipe = PORT_TO_PIPE(tmp);
1982 } else {
1983 u32 trans_sel;
1984 u32 trans_dp;
1985 int i;
1986
1987 switch (intel_dp->output_reg) {
1988 case PCH_DP_B:
1989 trans_sel = TRANS_DP_PORT_SEL_B;
1990 break;
1991 case PCH_DP_C:
1992 trans_sel = TRANS_DP_PORT_SEL_C;
1993 break;
1994 case PCH_DP_D:
1995 trans_sel = TRANS_DP_PORT_SEL_D;
1996 break;
1997 default:
1998 return true;
1999 }
2000
055e393f 2001 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2002 trans_dp = I915_READ(TRANS_DP_CTL(i));
2003 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2004 *pipe = i;
2005 return true;
2006 }
2007 }
19d8fe15 2008
4a0833ec
DV		 2009 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2010 intel_dp->output_reg);
2011 }
d240f20f 2012
19d8fe15
DV		 2013 return true;
2014}
d240f20f 2015
045ac3b5 2016static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2017 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2018{
2019 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2020 u32 tmp, flags = 0;
63000ef6
XZ		 2021 struct drm_device *dev = encoder->base.dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 enum port port = dp_to_dig_port(intel_dp)->port;
2024 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2025 int dotclock;
045ac3b5 2026
9ed109a7
DV		 2027 tmp = I915_READ(intel_dp->output_reg);
2028 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
2029 pipe_config->has_audio = true;
2030
63000ef6 2031 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2032 if (tmp & DP_SYNC_HS_HIGH)
2033 flags |= DRM_MODE_FLAG_PHSYNC;
2034 else
2035 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2036
63000ef6
XZ		 2037 if (tmp & DP_SYNC_VS_HIGH)
2038 flags |= DRM_MODE_FLAG_PVSYNC;
2039 else
2040 flags |= DRM_MODE_FLAG_NVSYNC;
2041 } else {
2042 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2043 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2044 flags |= DRM_MODE_FLAG_PHSYNC;
2045 else
2046 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2047
63000ef6
XZ		 2048 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2049 flags |= DRM_MODE_FLAG_PVSYNC;
2050 else
2051 flags |= DRM_MODE_FLAG_NVSYNC;
2052 }
045ac3b5 2053
2d112de7 2054 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2055
8c875fca
VS		 2056 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2057 tmp & DP_COLOR_RANGE_16_235)
2058 pipe_config->limited_color_range = true;
2059
eb14cb74
VS		 2060 pipe_config->has_dp_encoder = true;
2061
2062 intel_dp_get_m_n(crtc, pipe_config);
2063
18442d08 2064 if (port == PORT_A) {
f1f644dc
JB		 2065 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2066 pipe_config->port_clock = 162000;
2067 else
2068 pipe_config->port_clock = 270000;
2069 }
18442d08
VS		 2070
2071 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2072 &pipe_config->dp_m_n);
2073
2074 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2075 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2076
2d112de7 2077 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2078
c6cd2ee2
JN		 2079 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2080 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2081 /*
2082 * This is a big fat ugly hack.
2083 *
2084 * Some machines in UEFI boot mode provide us a VBT that has 18
2085 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2086 * unknown we fail to light up. Yet the same BIOS boots up with
2087 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2088 * max, not what it tells us to use.
2089 *
2090 * Note: This will still be broken if the eDP panel is not lit
2091 * up by the BIOS, and thus we can't get the mode at module
2092 * load.
2093 */
2094 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2095 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2096 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2097 }
045ac3b5
JB		 2098}
2099
e8cb4558 2100static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2101{
e8cb4558 2102 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2103 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2104 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2105
6e3c9717 2106 if (crtc->config->has_audio)
495a5bb8 2107 intel_audio_codec_disable(encoder);
6cb49835 2108
b32c6f48
RV		 2109 if (HAS_PSR(dev) && !HAS_DDI(dev))
2110 intel_psr_disable(intel_dp);
2111
6cb49835
DV		 2112 /* Make sure the panel is off before trying to change the mode. But also
2113 * ensure that we have vdd while we switch off the panel. */
24f3e092 2114 intel_edp_panel_vdd_on(intel_dp);
4be73780 2115 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2116 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2117 intel_edp_panel_off(intel_dp);
3739850b 2118
08aff3fe
VS		 2119 /* disable the port before the pipe on g4x */
2120 if (INTEL_INFO(dev)->gen < 5)
3739850b 2121 intel_dp_link_down(intel_dp);
d240f20f
JB		 2122}
2123
08aff3fe 2124static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2125{
2bd2ad64 2126 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2127 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2128
49277c31 2129 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2130 if (port == PORT_A)
2131 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2132}
2133
2134static void vlv_post_disable_dp(struct intel_encoder *encoder)
2135{
2136 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2137
2138 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2139}
2140
580d3811
VS		 2141static void chv_post_disable_dp(struct intel_encoder *encoder)
2142{
2143 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2144 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2145 struct drm_device *dev = encoder->base.dev;
2146 struct drm_i915_private *dev_priv = dev->dev_private;
2147 struct intel_crtc *intel_crtc =
2148 to_intel_crtc(encoder->base.crtc);
2149 enum dpio_channel ch = vlv_dport_to_channel(dport);
2150 enum pipe pipe = intel_crtc->pipe;
2151 u32 val;
2152
2153 intel_dp_link_down(intel_dp);
2154
2155 mutex_lock(&dev_priv->dpio_lock);
2156
2157 /* Propagate soft reset to data lane reset */
97fd4d5c 2158 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2159 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2160 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2161
97fd4d5c
VS		 2162 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2163 val |= CHV_PCS_REQ_SOFTRESET_EN;
2164 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2165
2166 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2167 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2168 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2169
2170 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2171 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2172 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2173
2174 mutex_unlock(&dev_priv->dpio_lock);
2175}
2176
7b13b58a
VS		 2177static void
2178_intel_dp_set_link_train(struct intel_dp *intel_dp,
2179 uint32_t *DP,
2180 uint8_t dp_train_pat)
2181{
2182 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2183 struct drm_device *dev = intel_dig_port->base.base.dev;
2184 struct drm_i915_private *dev_priv = dev->dev_private;
2185 enum port port = intel_dig_port->port;
2186
2187 if (HAS_DDI(dev)) {
2188 uint32_t temp = I915_READ(DP_TP_CTL(port));
2189
2190 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2191 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2192 else
2193 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2194
2195 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2196 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2197 case DP_TRAINING_PATTERN_DISABLE:
2198 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2199
2200 break;
2201 case DP_TRAINING_PATTERN_1:
2202 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2203 break;
2204 case DP_TRAINING_PATTERN_2:
2205 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2206 break;
2207 case DP_TRAINING_PATTERN_3:
2208 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2209 break;
2210 }
2211 I915_WRITE(DP_TP_CTL(port), temp);
2212
2213 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2214 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2215
2216 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2217 case DP_TRAINING_PATTERN_DISABLE:
2218 *DP |= DP_LINK_TRAIN_OFF_CPT;
2219 break;
2220 case DP_TRAINING_PATTERN_1:
2221 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2222 break;
2223 case DP_TRAINING_PATTERN_2:
2224 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2225 break;
2226 case DP_TRAINING_PATTERN_3:
2227 DRM_ERROR("DP training pattern 3 not supported\n");
2228 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2229 break;
2230 }
2231
2232 } else {
2233 if (IS_CHERRYVIEW(dev))
2234 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2235 else
2236 *DP &= ~DP_LINK_TRAIN_MASK;
2237
2238 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2239 case DP_TRAINING_PATTERN_DISABLE:
2240 *DP |= DP_LINK_TRAIN_OFF;
2241 break;
2242 case DP_TRAINING_PATTERN_1:
2243 *DP |= DP_LINK_TRAIN_PAT_1;
2244 break;
2245 case DP_TRAINING_PATTERN_2:
2246 *DP |= DP_LINK_TRAIN_PAT_2;
2247 break;
2248 case DP_TRAINING_PATTERN_3:
2249 if (IS_CHERRYVIEW(dev)) {
2250 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2251 } else {
2252 DRM_ERROR("DP training pattern 3 not supported\n");
2253 *DP |= DP_LINK_TRAIN_PAT_2;
2254 }
2255 break;
2256 }
2257 }
2258}
2259
2260static void intel_dp_enable_port(struct intel_dp *intel_dp)
2261{
2262 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2263 struct drm_i915_private *dev_priv = dev->dev_private;
2264
7b13b58a
VS		 2265 /* enable with pattern 1 (as per spec) */
2266 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2267 DP_TRAINING_PATTERN_1);
2268
2269 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2270 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2271
2272 /*
2273 * Magic for VLV/CHV. We _must_ first set up the register
2274 * without actually enabling the port, and then do another
2275 * write to enable the port. Otherwise link training will
2276 * fail when the power sequencer is freshly used for this port.
2277 */
2278 intel_dp->DP |= DP_PORT_EN;
2279
2280 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2281 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2282}
2283
e8cb4558 2284static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2285{
e8cb4558
DV		 2286 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2287 struct drm_device *dev = encoder->base.dev;
2288 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2289 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2290 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2291
0c33d8d7
DV		 2292 if (WARN_ON(dp_reg & DP_PORT_EN))
2293 return;
5d613501 2294
093e3f13
VS		 2295 pps_lock(intel_dp);
2296
2297 if (IS_VALLEYVIEW(dev))
2298 vlv_init_panel_power_sequencer(intel_dp);
2299
7b13b58a 2300 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2301
2302 edp_panel_vdd_on(intel_dp);
2303 edp_panel_on(intel_dp);
2304 edp_panel_vdd_off(intel_dp, true);
2305
2306 pps_unlock(intel_dp);
2307
61234fa5
VS		 2308 if (IS_VALLEYVIEW(dev))
2309 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2310
f01eca2e 2311 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2312 intel_dp_start_link_train(intel_dp);
33a34e4e 2313 intel_dp_complete_link_train(intel_dp);
3ab9c637 2314 intel_dp_stop_link_train(intel_dp);
c1dec79a 2315
6e3c9717 2316 if (crtc->config->has_audio) {
c1dec79a
JN		 2317 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2318 pipe_name(crtc->pipe));
2319 intel_audio_codec_enable(encoder);
2320 }
ab1f90f9 2321}
89b667f8 2322
ecff4f3b
JN		 2323static void g4x_enable_dp(struct intel_encoder *encoder)
2324{
828f5c6e
JN		 2325 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2326
ecff4f3b 2327 intel_enable_dp(encoder);
4be73780 2328 intel_edp_backlight_on(intel_dp);
ab1f90f9 2329}
89b667f8 2330
ab1f90f9
JN		 2331static void vlv_enable_dp(struct intel_encoder *encoder)
2332{
828f5c6e
JN		 2333 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2334
4be73780 2335 intel_edp_backlight_on(intel_dp);
b32c6f48 2336 intel_psr_enable(intel_dp);
d240f20f
JB		 2337}
2338
ecff4f3b 2339static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2340{
2341 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2342 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2343
8ac33ed3
DV		 2344 intel_dp_prepare(encoder);
2345
d41f1efb
DV		 2346 /* Only ilk+ has port A */
2347 if (dport->port == PORT_A) {
2348 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2349 ironlake_edp_pll_on(intel_dp);
d41f1efb 2350 }
ab1f90f9
JN		 2351}
2352
83b84597
VS		 2353static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2354{
2355 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2356 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2357 enum pipe pipe = intel_dp->pps_pipe;
2358 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2359
2360 edp_panel_vdd_off_sync(intel_dp);
2361
2362 /*
2363 * VLV seems to get confused when multiple power seqeuencers
2364 * have the same port selected (even if only one has power/vdd
2365 * enabled). The failure manifests as vlv_wait_port_ready() failing
2366 * CHV on the other hand doesn't seem to mind having the same port
2367 * selected in multiple power seqeuencers, but let's clear the
2368 * port select always when logically disconnecting a power sequencer
2369 * from a port.
2370 */
2371 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2372 pipe_name(pipe), port_name(intel_dig_port->port));
2373 I915_WRITE(pp_on_reg, 0);
2374 POSTING_READ(pp_on_reg);
2375
2376 intel_dp->pps_pipe = INVALID_PIPE;
2377}
2378
a4a5d2f8
VS		 2379static void vlv_steal_power_sequencer(struct drm_device *dev,
2380 enum pipe pipe)
2381{
2382 struct drm_i915_private *dev_priv = dev->dev_private;
2383 struct intel_encoder *encoder;
2384
2385 lockdep_assert_held(&dev_priv->pps_mutex);
2386
ac3c12e4
VS		 2387 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2388 return;
2389
a4a5d2f8
VS		 2390 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2391 base.head) {
2392 struct intel_dp *intel_dp;
773538e8 2393 enum port port;
a4a5d2f8
VS		 2394
2395 if (encoder->type != INTEL_OUTPUT_EDP)
2396 continue;
2397
2398 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2399 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2400
2401 if (intel_dp->pps_pipe != pipe)
2402 continue;
2403
2404 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2405 pipe_name(pipe), port_name(port));
a4a5d2f8 2406
034e43c6
VS		 2407 WARN(encoder->connectors_active,
2408 "stealing pipe %c power sequencer from active eDP port %c\n",
2409 pipe_name(pipe), port_name(port));
a4a5d2f8 2410
a4a5d2f8 2411 /* make sure vdd is off before we steal it */
83b84597 2412 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2413 }
2414}
2415
2416static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2417{
2418 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2419 struct intel_encoder *encoder = &intel_dig_port->base;
2420 struct drm_device *dev = encoder->base.dev;
2421 struct drm_i915_private *dev_priv = dev->dev_private;
2422 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2423
2424 lockdep_assert_held(&dev_priv->pps_mutex);
2425
093e3f13
VS		 2426 if (!is_edp(intel_dp))
2427 return;
2428
a4a5d2f8
VS		 2429 if (intel_dp->pps_pipe == crtc->pipe)
2430 return;
2431
2432 /*
2433 * If another power sequencer was being used on this
2434 * port previously make sure to turn off vdd there while
2435 * we still have control of it.
2436 */
2437 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2438 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2439
2440 /*
2441 * We may be stealing the power
2442 * sequencer from another port.
2443 */
2444 vlv_steal_power_sequencer(dev, crtc->pipe);
2445
2446 /* now it's all ours */
2447 intel_dp->pps_pipe = crtc->pipe;
2448
2449 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2450 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2451
2452 /* init power sequencer on this pipe and port */
36b5f425
VS		 2453 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2454 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2455}
2456
ab1f90f9 2457static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2458{
2bd2ad64 2459 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2460 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2461 struct drm_device *dev = encoder->base.dev;
89b667f8 2462 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2463 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2464 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2465 int pipe = intel_crtc->pipe;
2466 u32 val;
a4fc5ed6 2467
ab1f90f9 2468 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2469
ab3c759a 2470 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2471 val = 0;
2472 if (pipe)
2473 val |= (1<<21);
2474 else
2475 val &= ~(1<<21);
2476 val |= 0x001000c4;
ab3c759a
CML		 2477 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2478 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2479 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2480
ab1f90f9
JN		 2481 mutex_unlock(&dev_priv->dpio_lock);
2482
2483 intel_enable_dp(encoder);
89b667f8
JB		 2484}
2485
ecff4f3b 2486static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2487{
2488 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2489 struct drm_device *dev = encoder->base.dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2491 struct intel_crtc *intel_crtc =
2492 to_intel_crtc(encoder->base.crtc);
e4607fcf 2493 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2494 int pipe = intel_crtc->pipe;
89b667f8 2495
8ac33ed3
DV		 2496 intel_dp_prepare(encoder);
2497
89b667f8 2498 /* Program Tx lane resets to default */
0980a60f 2499 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2500 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2501 DPIO_PCS_TX_LANE2_RESET |
2502 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2503 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2504 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2505 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2506 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2507 DPIO_PCS_CLK_SOFT_RESET);
2508
2509 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2510 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2511 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2512 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2513 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2514}
2515
e4a1d846
CML		 2516static void chv_pre_enable_dp(struct intel_encoder *encoder)
2517{
2518 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2519 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2520 struct drm_device *dev = encoder->base.dev;
2521 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2522 struct intel_crtc *intel_crtc =
2523 to_intel_crtc(encoder->base.crtc);
2524 enum dpio_channel ch = vlv_dport_to_channel(dport);
2525 int pipe = intel_crtc->pipe;
2526 int data, i;
949c1d43 2527 u32 val;
e4a1d846 2528
e4a1d846 2529 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2530
570e2a74
VS		 2531 /* allow hardware to manage TX FIFO reset source */
2532 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2533 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2534 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2535
2536 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2537 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2538 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2539
949c1d43 2540 /* Deassert soft data lane reset*/
97fd4d5c 2541 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2542 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2543 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2544
2545 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2546 val |= CHV_PCS_REQ_SOFTRESET_EN;
2547 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2548
2549 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2550 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2551 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2552
97fd4d5c 2553 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2554 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2555 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2556
2557 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2558 for (i = 0; i < 4; i++) {
2559 /* Set the latency optimal bit */
2560 data = (i == 1) ? 0x0 : 0x6;
2561 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2562 data << DPIO_FRC_LATENCY_SHFIT);
2563
2564 /* Set the upar bit */
2565 data = (i == 1) ? 0x0 : 0x1;
2566 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2567 data << DPIO_UPAR_SHIFT);
2568 }
2569
2570 /* Data lane stagger programming */
2571 /* FIXME: Fix up value only after power analysis */
2572
2573 mutex_unlock(&dev_priv->dpio_lock);
2574
e4a1d846 2575 intel_enable_dp(encoder);
e4a1d846
CML		 2576}
2577
9197c88b
VS		 2578static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2579{
2580 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2581 struct drm_device *dev = encoder->base.dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct intel_crtc *intel_crtc =
2584 to_intel_crtc(encoder->base.crtc);
2585 enum dpio_channel ch = vlv_dport_to_channel(dport);
2586 enum pipe pipe = intel_crtc->pipe;
2587 u32 val;
2588
625695f8
VS		 2589 intel_dp_prepare(encoder);
2590
9197c88b
VS		 2591 mutex_lock(&dev_priv->dpio_lock);
2592
b9e5ac3c
VS		 2593 /* program left/right clock distribution */
2594 if (pipe != PIPE_B) {
2595 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2596 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2597 if (ch == DPIO_CH0)
2598 val |= CHV_BUFLEFTENA1_FORCE;
2599 if (ch == DPIO_CH1)
2600 val |= CHV_BUFRIGHTENA1_FORCE;
2601 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2602 } else {
2603 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2604 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2605 if (ch == DPIO_CH0)
2606 val |= CHV_BUFLEFTENA2_FORCE;
2607 if (ch == DPIO_CH1)
2608 val |= CHV_BUFRIGHTENA2_FORCE;
2609 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2610 }
2611
9197c88b
VS		 2612 /* program clock channel usage */
2613 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2614 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2615 if (pipe != PIPE_B)
2616 val &= ~CHV_PCS_USEDCLKCHANNEL;
2617 else
2618 val |= CHV_PCS_USEDCLKCHANNEL;
2619 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2620
2621 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2622 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2623 if (pipe != PIPE_B)
2624 val &= ~CHV_PCS_USEDCLKCHANNEL;
2625 else
2626 val |= CHV_PCS_USEDCLKCHANNEL;
2627 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2628
2629 /*
2630 * This a a bit weird since generally CL
2631 * matches the pipe, but here we need to
2632 * pick the CL based on the port.
2633 */
2634 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2635 if (pipe != PIPE_B)
2636 val &= ~CHV_CMN_USEDCLKCHANNEL;
2637 else
2638 val |= CHV_CMN_USEDCLKCHANNEL;
2639 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2640
2641 mutex_unlock(&dev_priv->dpio_lock);
2642}
2643
a4fc5ed6 2644/*
df0c237d
JB		 2645 * Native read with retry for link status and receiver capability reads for
2646 * cases where the sink may still be asleep.
9d1a1031
JN		 2647 *
2648 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2649 * supposed to retry 3 times per the spec.
a4fc5ed6 2650 */
9d1a1031
JN		 2651static ssize_t
2652intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2653 void *buffer, size_t size)
a4fc5ed6 2654{
9d1a1031
JN		 2655 ssize_t ret;
2656 int i;
61da5fab 2657
f6a19066
VS		 2658 /*
2659 * Sometime we just get the same incorrect byte repeated
2660 * over the entire buffer. Doing just one throw away read
2661 * initially seems to "solve" it.
2662 */
2663 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2664
61da5fab 2665 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2666 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2667 if (ret == size)
2668 return ret;
61da5fab
JB		 2669 msleep(1);
2670 }
a4fc5ed6 2671
9d1a1031 2672 return ret;
a4fc5ed6
KP		 2673}
2674
2675/*
2676 * Fetch AUX CH registers 0x202 - 0x207 which contain
2677 * link status information
2678 */
2679static bool
93f62dad 2680intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2681{
9d1a1031
JN		 2682 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2683 DP_LANE0_1_STATUS,
2684 link_status,
2685 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2686}
2687
1100244e 2688/* These are source-specific values. */
a4fc5ed6 2689static uint8_t
1a2eb460 2690intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2691{
30add22d 2692 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2693 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2694
5a9d1f1a
DL		 2695 if (INTEL_INFO(dev)->gen >= 9)
2696 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2697 else if (IS_VALLEYVIEW(dev))
bd60018a 2698 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2699 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2700 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2701 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2702 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2703 else
bd60018a 2704 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2705}
2706
2707static uint8_t
2708intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2709{
30add22d 2710 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2711 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2712
5a9d1f1a
DL		 2713 if (INTEL_INFO(dev)->gen >= 9) {
2714 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2715 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2716 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2717 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2718 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2719 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2720 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2721 default:
2722 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2723 }
2724 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2725 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2726 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2727 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2728 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2729 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2730 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2731 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2732 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2733 default:
bd60018a 2734 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2735 }
e2fa6fba
P		 2736 } else if (IS_VALLEYVIEW(dev)) {
2737 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2738 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2739 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2740 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2741 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2742 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2743 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2744 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2745 default:
bd60018a 2746 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2747 }
bc7d38a4 2748 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2749 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2750 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2751 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2752 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2753 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2754 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2755 default:
bd60018a 2756 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2757 }
2758 } else {
2759 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2760 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2761 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2762 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2763 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2764 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2765 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2766 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2767 default:
bd60018a 2768 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2769 }
a4fc5ed6
KP		 2770 }
2771}
2772
e2fa6fba
P		 2773static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2774{
2775 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2778 struct intel_crtc *intel_crtc =
2779 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2780 unsigned long demph_reg_value, preemph_reg_value,
2781 uniqtranscale_reg_value;
2782 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2783 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2784 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2785
2786 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2787 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2788 preemph_reg_value = 0x0004000;
2789 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2790 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2791 demph_reg_value = 0x2B405555;
2792 uniqtranscale_reg_value = 0x552AB83A;
2793 break;
bd60018a 2794 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2795 demph_reg_value = 0x2B404040;
2796 uniqtranscale_reg_value = 0x5548B83A;
2797 break;
bd60018a 2798 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2799 demph_reg_value = 0x2B245555;
2800 uniqtranscale_reg_value = 0x5560B83A;
2801 break;
bd60018a 2802 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2803 demph_reg_value = 0x2B405555;
2804 uniqtranscale_reg_value = 0x5598DA3A;
2805 break;
2806 default:
2807 return 0;
2808 }
2809 break;
bd60018a 2810 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2811 preemph_reg_value = 0x0002000;
2812 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2813 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2814 demph_reg_value = 0x2B404040;
2815 uniqtranscale_reg_value = 0x5552B83A;
2816 break;
bd60018a 2817 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2818 demph_reg_value = 0x2B404848;
2819 uniqtranscale_reg_value = 0x5580B83A;
2820 break;
bd60018a 2821 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2822 demph_reg_value = 0x2B404040;
2823 uniqtranscale_reg_value = 0x55ADDA3A;
2824 break;
2825 default:
2826 return 0;
2827 }
2828 break;
bd60018a 2829 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2830 preemph_reg_value = 0x0000000;
2831 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2832 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2833 demph_reg_value = 0x2B305555;
2834 uniqtranscale_reg_value = 0x5570B83A;
2835 break;
bd60018a 2836 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2837 demph_reg_value = 0x2B2B4040;
2838 uniqtranscale_reg_value = 0x55ADDA3A;
2839 break;
2840 default:
2841 return 0;
2842 }
2843 break;
bd60018a 2844 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2845 preemph_reg_value = 0x0006000;
2846 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2847 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2848 demph_reg_value = 0x1B405555;
2849 uniqtranscale_reg_value = 0x55ADDA3A;
2850 break;
2851 default:
2852 return 0;
2853 }
2854 break;
2855 default:
2856 return 0;
2857 }
2858
0980a60f 2859 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2860 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2861 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2862 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2863 uniqtranscale_reg_value);
ab3c759a
CML		 2864 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2865 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2866 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2867 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2868 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2869
2870 return 0;
2871}
2872
e4a1d846
CML		 2873static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2874{
2875 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2878 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2879 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2880 uint8_t train_set = intel_dp->train_set[0];
2881 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2882 enum pipe pipe = intel_crtc->pipe;
2883 int i;
e4a1d846
CML		 2884
2885 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2886 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2887 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2889 deemph_reg_value = 128;
2890 margin_reg_value = 52;
2891 break;
bd60018a 2892 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2893 deemph_reg_value = 128;
2894 margin_reg_value = 77;
2895 break;
bd60018a 2896 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2897 deemph_reg_value = 128;
2898 margin_reg_value = 102;
2899 break;
bd60018a 2900 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2901 deemph_reg_value = 128;
2902 margin_reg_value = 154;
2903 /* FIXME extra to set for 1200 */
2904 break;
2905 default:
2906 return 0;
2907 }
2908 break;
bd60018a 2909 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2910 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2911 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2912 deemph_reg_value = 85;
2913 margin_reg_value = 78;
2914 break;
bd60018a 2915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2916 deemph_reg_value = 85;
2917 margin_reg_value = 116;
2918 break;
bd60018a 2919 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2920 deemph_reg_value = 85;
2921 margin_reg_value = 154;
2922 break;
2923 default:
2924 return 0;
2925 }
2926 break;
bd60018a 2927 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2928 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2929 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2930 deemph_reg_value = 64;
2931 margin_reg_value = 104;
2932 break;
bd60018a 2933 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2934 deemph_reg_value = 64;
2935 margin_reg_value = 154;
2936 break;
2937 default:
2938 return 0;
2939 }
2940 break;
bd60018a 2941 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2942 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2944 deemph_reg_value = 43;
2945 margin_reg_value = 154;
2946 break;
2947 default:
2948 return 0;
2949 }
2950 break;
2951 default:
2952 return 0;
2953 }
2954
2955 mutex_lock(&dev_priv->dpio_lock);
2956
2957 /* Clear calc init */
1966e59e
VS		 2958 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2959 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2960 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2961 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 2962 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2963
2964 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2965 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 2966 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
2967 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 2968 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 2969
a02ef3c7
VS		 2970 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
2971 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2972 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2973 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
2974
2975 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
2976 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
2977 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
2978 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
2979
e4a1d846 2980 /* Program swing deemph */
f72df8db
VS		 2981 for (i = 0; i < 4; i++) {
2982 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2983 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2984 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2985 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2986 }
e4a1d846
CML		 2987
2988 /* Program swing margin */
f72df8db
VS		 2989 for (i = 0; i < 4; i++) {
2990 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2991 val &= ~DPIO_SWING_MARGIN000_MASK;
2992 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2993 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2994 }
e4a1d846
CML		 2995
2996 /* Disable unique transition scale */
f72df8db
VS		 2997 for (i = 0; i < 4; i++) {
2998 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2999 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3000 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3001 }
e4a1d846
CML		 3002
3003 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3004 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3005 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3006 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3007
3008 /*
3009 * The document said it needs to set bit 27 for ch0 and bit 26
3010 * for ch1. Might be a typo in the doc.
3011 * For now, for this unique transition scale selection, set bit
3012 * 27 for ch0 and ch1.
3013 */
f72df8db
VS		 3014 for (i = 0; i < 4; i++) {
3015 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3016 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3017 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3018 }
e4a1d846 3019
f72df8db
VS		 3020 for (i = 0; i < 4; i++) {
3021 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3022 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3023 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3024 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3025 }
e4a1d846
CML		 3026 }
3027
3028 /* Start swing calculation */
1966e59e
VS		 3029 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3030 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3031 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3032
3033 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3034 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3035 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3036
3037 /* LRC Bypass */
3038 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3039 val |= DPIO_LRC_BYPASS;
3040 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3041
3042 mutex_unlock(&dev_priv->dpio_lock);
3043
3044 return 0;
3045}
3046
a4fc5ed6 3047static void
0301b3ac
JN		 3048intel_get_adjust_train(struct intel_dp *intel_dp,
3049 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3050{
3051 uint8_t v = 0;
3052 uint8_t p = 0;
3053 int lane;
1a2eb460
KP		 3054 uint8_t voltage_max;
3055 uint8_t preemph_max;
a4fc5ed6 3056
33a34e4e 3057 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3058 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3059 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3060
3061 if (this_v > v)
3062 v = this_v;
3063 if (this_p > p)
3064 p = this_p;
3065 }
3066
1a2eb460 3067 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3068 if (v >= voltage_max)
3069 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3070
1a2eb460
KP		 3071 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3072 if (p >= preemph_max)
3073 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3074
3075 for (lane = 0; lane < 4; lane++)
33a34e4e 3076 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3077}
3078
3079static uint32_t
f0a3424e 3080intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3081{
3cf2efb1 3082 uint32_t signal_levels = 0;
a4fc5ed6 3083
3cf2efb1 3084 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3085 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3086 default:
3087 signal_levels |= DP_VOLTAGE_0_4;
3088 break;
bd60018a 3089 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3090 signal_levels |= DP_VOLTAGE_0_6;
3091 break;
bd60018a 3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3093 signal_levels |= DP_VOLTAGE_0_8;
3094 break;
bd60018a 3095 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3096 signal_levels |= DP_VOLTAGE_1_2;
3097 break;
3098 }
3cf2efb1 3099 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3100 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3101 default:
3102 signal_levels |= DP_PRE_EMPHASIS_0;
3103 break;
bd60018a 3104 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3105 signal_levels |= DP_PRE_EMPHASIS_3_5;
3106 break;
bd60018a 3107 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3108 signal_levels |= DP_PRE_EMPHASIS_6;
3109 break;
bd60018a 3110 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3111 signal_levels |= DP_PRE_EMPHASIS_9_5;
3112 break;
3113 }
3114 return signal_levels;
3115}
3116
e3421a18
ZW		 3117/* Gen6's DP voltage swing and pre-emphasis control */
3118static uint32_t
3119intel_gen6_edp_signal_levels(uint8_t train_set)
3120{
3c5a62b5
YL		 3121 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3122 DP_TRAIN_PRE_EMPHASIS_MASK);
3123 switch (signal_levels) {
bd60018a
SJ		 3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3125 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3126 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3127 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3128 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3130 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3131 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3134 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3137 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3138 default:
3c5a62b5
YL		 3139 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3140 "0x%x\n", signal_levels);
3141 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3142 }
3143}
3144
1a2eb460
KP		 3145/* Gen7's DP voltage swing and pre-emphasis control */
3146static uint32_t
3147intel_gen7_edp_signal_levels(uint8_t train_set)
3148{
3149 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3150 DP_TRAIN_PRE_EMPHASIS_MASK);
3151 switch (signal_levels) {
bd60018a 3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3153 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3155 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3157 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3158
bd60018a 3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3160 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3161 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3162 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3163
bd60018a 3164 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3165 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3166 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3167 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3168
3169 default:
3170 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3171 "0x%x\n", signal_levels);
3172 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3173 }
3174}
3175
d6c0d722
PZ		 3176/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3177static uint32_t
f0a3424e 3178intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3179{
d6c0d722
PZ		 3180 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3181 DP_TRAIN_PRE_EMPHASIS_MASK);
3182 switch (signal_levels) {
bd60018a 3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3184 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3186 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3188 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3190 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3191
bd60018a 3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3193 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3195 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3196 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3197 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3198
bd60018a 3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3200 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3202 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3203 default:
3204 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3205 "0x%x\n", signal_levels);
c5fe6a06 3206 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3207 }
a4fc5ed6
KP		 3208}
3209
f0a3424e
PZ		 3210/* Properly updates "DP" with the correct signal levels. */
3211static void
3212intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3213{
3214 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3215 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3216 struct drm_device *dev = intel_dig_port->base.base.dev;
3217 uint32_t signal_levels, mask;
3218 uint8_t train_set = intel_dp->train_set[0];
3219
5a9d1f1a 3220 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3221 signal_levels = intel_hsw_signal_levels(train_set);
3222 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3223 } else if (IS_CHERRYVIEW(dev)) {
3224 signal_levels = intel_chv_signal_levels(intel_dp);
3225 mask = 0;
e2fa6fba
P		 3226 } else if (IS_VALLEYVIEW(dev)) {
3227 signal_levels = intel_vlv_signal_levels(intel_dp);
3228 mask = 0;
bc7d38a4 3229 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3230 signal_levels = intel_gen7_edp_signal_levels(train_set);
3231 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3232 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3233 signal_levels = intel_gen6_edp_signal_levels(train_set);
3234 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3235 } else {
3236 signal_levels = intel_gen4_signal_levels(train_set);
3237 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3238 }
3239
3240 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3241
3242 *DP = (*DP & ~mask) | signal_levels;
3243}
3244
a4fc5ed6 3245static bool
ea5b213a 3246intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3247 uint32_t *DP,
58e10eb9 3248 uint8_t dp_train_pat)
a4fc5ed6 3249{
174edf1f
PZ		 3250 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3251 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3252 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3253 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3254 int ret, len;
a4fc5ed6 3255
7b13b58a 3256 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3257
70aff66c 3258 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3259 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3260
2cdfe6c8
JN		 3261 buf[0] = dp_train_pat;
3262 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3263 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3264 /* don't write DP_TRAINING_LANEx_SET on disable */
3265 len = 1;
3266 } else {
3267 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3268 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3269 len = intel_dp->lane_count + 1;
47ea7542 3270 }
a4fc5ed6 3271
9d1a1031
JN		 3272 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3273 buf, len);
2cdfe6c8
JN		 3274
3275 return ret == len;
a4fc5ed6
KP		 3276}
3277
70aff66c
JN		 3278static bool
3279intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3280 uint8_t dp_train_pat)
3281{
953d22e8 3282 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3283 intel_dp_set_signal_levels(intel_dp, DP);
3284 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3285}
3286
3287static bool
3288intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3289 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3290{
3291 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3292 struct drm_device *dev = intel_dig_port->base.base.dev;
3293 struct drm_i915_private *dev_priv = dev->dev_private;
3294 int ret;
3295
3296 intel_get_adjust_train(intel_dp, link_status);
3297 intel_dp_set_signal_levels(intel_dp, DP);
3298
3299 I915_WRITE(intel_dp->output_reg, *DP);
3300 POSTING_READ(intel_dp->output_reg);
3301
9d1a1031
JN		 3302 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3303 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3304
3305 return ret == intel_dp->lane_count;
3306}
3307
3ab9c637
ID		 3308static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3309{
3310 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3311 struct drm_device *dev = intel_dig_port->base.base.dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313 enum port port = intel_dig_port->port;
3314 uint32_t val;
3315
3316 if (!HAS_DDI(dev))
3317 return;
3318
3319 val = I915_READ(DP_TP_CTL(port));
3320 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3321 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3322 I915_WRITE(DP_TP_CTL(port), val);
3323
3324 /*
3325 * On PORT_A we can have only eDP in SST mode. There the only reason
3326 * we need to set idle transmission mode is to work around a HW issue
3327 * where we enable the pipe while not in idle link-training mode.
3328 * In this case there is requirement to wait for a minimum number of
3329 * idle patterns to be sent.
3330 */
3331 if (port == PORT_A)
3332 return;
3333
3334 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3335 1))
3336 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3337}
3338
33a34e4e 3339/* Enable corresponding port and start training pattern 1 */
c19b0669 3340void
33a34e4e 3341intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3342{
da63a9f2 3343 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3344 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3345 int i;
3346 uint8_t voltage;
cdb0e95b 3347 int voltage_tries, loop_tries;
ea5b213a 3348 uint32_t DP = intel_dp->DP;
6aba5b6c 3349 uint8_t link_config[2];
a4fc5ed6 3350
affa9354 3351 if (HAS_DDI(dev))
c19b0669
PZ		 3352 intel_ddi_prepare_link_retrain(encoder);
3353
3cf2efb1 3354 /* Write the link configuration data */
6aba5b6c
JN		 3355 link_config[0] = intel_dp->link_bw;
3356 link_config[1] = intel_dp->lane_count;
3357 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3358 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3359 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3360
3361 link_config[0] = 0;
3362 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3363 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3364
3365 DP |= DP_PORT_EN;
1a2eb460 3366
70aff66c
JN		 3367 /* clock recovery */
3368 if (!intel_dp_reset_link_train(intel_dp, &DP,
3369 DP_TRAINING_PATTERN_1 |
3370 DP_LINK_SCRAMBLING_DISABLE)) {
3371 DRM_ERROR("failed to enable link training\n");
3372 return;
3373 }
3374
a4fc5ed6 3375 voltage = 0xff;
cdb0e95b
KP		 3376 voltage_tries = 0;
3377 loop_tries = 0;
a4fc5ed6 3378 for (;;) {
70aff66c 3379 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3380
a7c9655f 3381 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3382 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3383 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3384 break;
93f62dad 3385 }
a4fc5ed6 3386
01916270 3387 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3388 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3389 break;
3390 }
3391
3392 /* Check to see if we've tried the max voltage */
3393 for (i = 0; i < intel_dp->lane_count; i++)
3394 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3395 break;
3b4f819d 3396 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3397 ++loop_tries;
3398 if (loop_tries == 5) {
3def84b3 3399 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3400 break;
3401 }
70aff66c
JN		 3402 intel_dp_reset_link_train(intel_dp, &DP,
3403 DP_TRAINING_PATTERN_1 |
3404 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3405 voltage_tries = 0;
3406 continue;
3407 }
a4fc5ed6 3408
3cf2efb1 3409 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3410 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3411 ++voltage_tries;
b06fbda3 3412 if (voltage_tries == 5) {
3def84b3 3413 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3414 break;
3415 }
3416 } else
3417 voltage_tries = 0;
3418 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3419
70aff66c
JN		 3420 /* Update training set as requested by target */
3421 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3422 DRM_ERROR("failed to update link training\n");
3423 break;
3424 }
a4fc5ed6
KP		 3425 }
3426
33a34e4e
JB		 3427 intel_dp->DP = DP;
3428}
3429
c19b0669 3430void
33a34e4e
JB		 3431intel_dp_complete_link_train(struct intel_dp *intel_dp)
3432{
33a34e4e 3433 bool channel_eq = false;
37f80975 3434 int tries, cr_tries;
33a34e4e 3435 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3436 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3437
3438 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3439 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3440 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3441
a4fc5ed6 3442 /* channel equalization */
70aff66c 3443 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3444 training_pattern |
70aff66c
JN		 3445 DP_LINK_SCRAMBLING_DISABLE)) {
3446 DRM_ERROR("failed to start channel equalization\n");
3447 return;
3448 }
3449
a4fc5ed6 3450 tries = 0;
37f80975 3451 cr_tries = 0;
a4fc5ed6
KP		 3452 channel_eq = false;
3453 for (;;) {
70aff66c 3454 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3455
37f80975
JB		 3456 if (cr_tries > 5) {
3457 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3458 break;
3459 }
3460
a7c9655f 3461 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3462 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3463 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3464 break;
70aff66c 3465 }
a4fc5ed6 3466
37f80975 3467 /* Make sure clock is still ok */
01916270 3468 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3469 intel_dp_start_link_train(intel_dp);
70aff66c 3470 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3471 training_pattern |
70aff66c 3472 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3473 cr_tries++;
3474 continue;
3475 }
3476
1ffdff13 3477 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3478 channel_eq = true;
3479 break;
3480 }
a4fc5ed6 3481
37f80975
JB		 3482 /* Try 5 times, then try clock recovery if that fails */
3483 if (tries > 5) {
37f80975 3484 intel_dp_start_link_train(intel_dp);
70aff66c 3485 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3486 training_pattern |
70aff66c 3487 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3488 tries = 0;
3489 cr_tries++;
3490 continue;
3491 }
a4fc5ed6 3492
70aff66c
JN		 3493 /* Update training set as requested by target */
3494 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3495 DRM_ERROR("failed to update link training\n");
3496 break;
3497 }
3cf2efb1 3498 ++tries;
869184a6 3499 }
3cf2efb1 3500
3ab9c637
ID		 3501 intel_dp_set_idle_link_train(intel_dp);
3502
3503 intel_dp->DP = DP;
3504
d6c0d722 3505 if (channel_eq)
07f42258 3506 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3507
3ab9c637
ID		 3508}
3509
3510void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3511{
70aff66c 3512 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3513 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3514}
3515
3516static void
ea5b213a 3517intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3518{
da63a9f2 3519 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3520 enum port port = intel_dig_port->port;
da63a9f2 3521 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3522 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3523 struct intel_crtc *intel_crtc =
3524 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3525 uint32_t DP = intel_dp->DP;
a4fc5ed6 3526
bc76e320 3527 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3528 return;
3529
0c33d8d7 3530 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3531 return;
3532
28c97730 3533 DRM_DEBUG_KMS("\n");
32f9d658 3534
bc7d38a4 3535 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3536 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3537 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3538 } else {
aad3d14d
VS		 3539 if (IS_CHERRYVIEW(dev))
3540 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3541 else
3542 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3543 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3544 }
fe255d00 3545 POSTING_READ(intel_dp->output_reg);
5eb08b69 3546
493a7081 3547 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3548 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3549 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3550
5bddd17f
EA		 3551 /* Hardware workaround: leaving our transcoder select
3552 * set to transcoder B while it's off will prevent the
3553 * corresponding HDMI output on transcoder A.
3554 *
3555 * Combine this with another hardware workaround:
3556 * transcoder select bit can only be cleared while the
3557 * port is enabled.
3558 */
3559 DP &= ~DP_PIPEB_SELECT;
3560 I915_WRITE(intel_dp->output_reg, DP);
3561
3562 /* Changes to enable or select take place the vblank
3563 * after being written.
3564 */
ff50afe9
DV		 3565 if (WARN_ON(crtc == NULL)) {
3566 /* We should never try to disable a port without a crtc
3567 * attached. For paranoia keep the code around for a
3568 * bit. */
31acbcc4
CW		 3569 POSTING_READ(intel_dp->output_reg);
3570 msleep(50);
3571 } else
ab527efc 3572 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3573 }
3574
832afda6 3575 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3576 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3577 POSTING_READ(intel_dp->output_reg);
f01eca2e 3578 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3579}
3580
26d61aad
KP		 3581static bool
3582intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3583{
a031d709
RV		 3584 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3585 struct drm_device *dev = dig_port->base.base.dev;
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587
9d1a1031
JN		 3588 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3589 sizeof(intel_dp->dpcd)) < 0)
edb39244 3590 return false; /* aux transfer failed */
92fd8fd1 3591
a8e98153 3592 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3593
edb39244
AJ		 3594 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3595 return false; /* DPCD not present */
3596
2293bb5c
SK		 3597 /* Check if the panel supports PSR */
3598 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3599 if (is_edp(intel_dp)) {
9d1a1031
JN		 3600 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3601 intel_dp->psr_dpcd,
3602 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3603 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3604 dev_priv->psr.sink_support = true;
50003939 3605 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3606 }
50003939
JN		 3607 }
3608
7809a611 3609 /* Training Pattern 3 support, both source and sink */
06ea66b6 3610 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3611 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3612 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3613 intel_dp->use_tps3 = true;
f8d8a672 3614 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3615 } else
3616 intel_dp->use_tps3 = false;
3617
edb39244
AJ		 3618 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3619 DP_DWN_STRM_PORT_PRESENT))
3620 return true; /* native DP sink */
3621
3622 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3623 return true; /* no per-port downstream info */
3624
9d1a1031
JN		 3625 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3626 intel_dp->downstream_ports,
3627 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3628 return false; /* downstream port status fetch failed */
3629
3630 return true;
92fd8fd1
KP		 3631}
3632
0d198328
AJ		 3633static void
3634intel_dp_probe_oui(struct intel_dp *intel_dp)
3635{
3636 u8 buf[3];
3637
3638 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3639 return;
3640
9d1a1031 3641 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3642 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3643 buf[0], buf[1], buf[2]);
3644
9d1a1031 3645 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3646 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3647 buf[0], buf[1], buf[2]);
3648}
3649
0e32b39c
DA		 3650static bool
3651intel_dp_probe_mst(struct intel_dp *intel_dp)
3652{
3653 u8 buf[1];
3654
3655 if (!intel_dp->can_mst)
3656 return false;
3657
3658 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3659 return false;
3660
0e32b39c
DA		 3661 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3662 if (buf[0] & DP_MST_CAP) {
3663 DRM_DEBUG_KMS("Sink is MST capable\n");
3664 intel_dp->is_mst = true;
3665 } else {
3666 DRM_DEBUG_KMS("Sink is not MST capable\n");
3667 intel_dp->is_mst = false;
3668 }
3669 }
0e32b39c
DA		 3670
3671 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3672 return intel_dp->is_mst;
3673}
3674
d2e216d0
RV		 3675int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3676{
3677 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3678 struct drm_device *dev = intel_dig_port->base.base.dev;
3679 struct intel_crtc *intel_crtc =
3680 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3681 u8 buf;
3682 int test_crc_count;
3683 int attempts = 6;
d2e216d0 3684
ad9dc91b 3685 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3686 return -EIO;
d2e216d0 3687
ad9dc91b 3688 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3689 return -ENOTTY;
3690
1dda5f93
RV		 3691 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3692 return -EIO;
3693
9d1a1031 3694 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3695 buf | DP_TEST_SINK_START) < 0)
bda0381e 3696 return -EIO;
d2e216d0 3697
1dda5f93 3698 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3699 return -EIO;
ad9dc91b 3700 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3701
ad9dc91b 3702 do {
1dda5f93
RV		 3703 if (drm_dp_dpcd_readb(&intel_dp->aux,
3704 DP_TEST_SINK_MISC, &buf) < 0)
3705 return -EIO;
ad9dc91b
RV		 3706 intel_wait_for_vblank(dev, intel_crtc->pipe);
3707 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3708
3709 if (attempts == 0) {
90bd1f46
DV		 3710 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
3711 return -ETIMEDOUT;
ad9dc91b 3712 }
d2e216d0 3713
9d1a1031 3714 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3715 return -EIO;
d2e216d0 3716
1dda5f93
RV		 3717 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3718 return -EIO;
3719 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3720 buf & ~DP_TEST_SINK_START) < 0)
3721 return -EIO;
ce31d9f4 3722
d2e216d0
RV		 3723 return 0;
3724}
3725
a60f0e38
JB		 3726static bool
3727intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3728{
9d1a1031
JN		 3729 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3730 DP_DEVICE_SERVICE_IRQ_VECTOR,
3731 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3732}
3733
0e32b39c
DA		 3734static bool
3735intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3736{
3737 int ret;
3738
3739 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3740 DP_SINK_COUNT_ESI,
3741 sink_irq_vector, 14);
3742 if (ret != 14)
3743 return false;
3744
3745 return true;
3746}
3747
a60f0e38
JB		 3748static void
3749intel_dp_handle_test_request(struct intel_dp *intel_dp)
3750{
3751 /* NAK by default */
9d1a1031 3752 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3753}
3754
0e32b39c
DA		 3755static int
3756intel_dp_check_mst_status(struct intel_dp *intel_dp)
3757{
3758 bool bret;
3759
3760 if (intel_dp->is_mst) {
3761 u8 esi[16] = { 0 };
3762 int ret = 0;
3763 int retry;
3764 bool handled;
3765 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3766go_again:
3767 if (bret == true) {
3768
3769 /* check link status - esi[10] = 0x200c */
3770 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3771 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3772 intel_dp_start_link_train(intel_dp);
3773 intel_dp_complete_link_train(intel_dp);
3774 intel_dp_stop_link_train(intel_dp);
3775 }
3776
6f34cc39 3777 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3778 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3779
3780 if (handled) {
3781 for (retry = 0; retry < 3; retry++) {
3782 int wret;
3783 wret = drm_dp_dpcd_write(&intel_dp->aux,
3784 DP_SINK_COUNT_ESI+1,
3785 &esi[1], 3);
3786 if (wret == 3) {
3787 break;
3788 }
3789 }
3790
3791 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3792 if (bret == true) {
6f34cc39 3793 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3794 goto go_again;
3795 }
3796 } else
3797 ret = 0;
3798
3799 return ret;
3800 } else {
3801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3802 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3803 intel_dp->is_mst = false;
3804 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3805 /* send a hotplug event */
3806 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3807 }
3808 }
3809 return -EINVAL;
3810}
3811
a4fc5ed6
KP		 3812/*
3813 * According to DP spec
3814 * 5.1.2:
3815 * 1. Read DPCD
3816 * 2. Configure link according to Receiver Capabilities
3817 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3818 * 4. Check link status on receipt of hot-plug interrupt
3819 */
00c09d70 3820void
ea5b213a 3821intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3822{
5b215bcf 3823 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3824 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3825 u8 sink_irq_vector;
93f62dad 3826 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3827
5b215bcf
DA		 3828 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3829
da63a9f2 3830 if (!intel_encoder->connectors_active)
d2b996ac 3831 return;
59cd09e1 3832
da63a9f2 3833 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3834 return;
3835
1a125d8a
ID		 3836 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3837 return;
3838
92fd8fd1 3839 /* Try to read receiver status if the link appears to be up */
93f62dad 3840 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3841 return;
3842 }
3843
92fd8fd1 3844 /* Now read the DPCD to see if it's actually running */
26d61aad 3845 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3846 return;
3847 }
3848
a60f0e38
JB		 3849 /* Try to read the source of the interrupt */
3850 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3851 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3852 /* Clear interrupt source */
9d1a1031
JN		 3853 drm_dp_dpcd_writeb(&intel_dp->aux,
3854 DP_DEVICE_SERVICE_IRQ_VECTOR,
3855 sink_irq_vector);
a60f0e38
JB		 3856
3857 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3858 intel_dp_handle_test_request(intel_dp);
3859 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3860 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3861 }
3862
1ffdff13 3863 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3864 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3865 intel_encoder->base.name);
33a34e4e
JB		 3866 intel_dp_start_link_train(intel_dp);
3867 intel_dp_complete_link_train(intel_dp);
3ab9c637 3868 intel_dp_stop_link_train(intel_dp);
33a34e4e 3869 }
a4fc5ed6 3870}
a4fc5ed6 3871
caf9ab24 3872/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3873static enum drm_connector_status
26d61aad 3874intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3875{
caf9ab24 3876 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3877 uint8_t type;
3878
3879 if (!intel_dp_get_dpcd(intel_dp))
3880 return connector_status_disconnected;
3881
3882 /* if there's no downstream port, we're done */
3883 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3884 return connector_status_connected;
caf9ab24
AJ		 3885
3886 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3887 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3888 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3889 uint8_t reg;
9d1a1031
JN		 3890
3891 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3892 &reg, 1) < 0)
caf9ab24 3893 return connector_status_unknown;
9d1a1031 3894
23235177
AJ		 3895 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3896 : connector_status_disconnected;
caf9ab24
AJ		 3897 }
3898
3899 /* If no HPD, poke DDC gently */
0b99836f 3900 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3901 return connector_status_connected;
caf9ab24
AJ		 3902
3903 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3904 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3905 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3906 if (type == DP_DS_PORT_TYPE_VGA ||
3907 type == DP_DS_PORT_TYPE_NON_EDID)
3908 return connector_status_unknown;
3909 } else {
3910 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3911 DP_DWN_STRM_PORT_TYPE_MASK;
3912 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3913 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3914 return connector_status_unknown;
3915 }
caf9ab24
AJ		 3916
3917 /* Anything else is out of spec, warn and ignore */
3918 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3919 return connector_status_disconnected;
71ba9000
AJ		 3920}
3921
d410b56d
CW		 3922static enum drm_connector_status
3923edp_detect(struct intel_dp *intel_dp)
3924{
3925 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3926 enum drm_connector_status status;
3927
3928 status = intel_panel_detect(dev);
3929 if (status == connector_status_unknown)
3930 status = connector_status_connected;
3931
3932 return status;
3933}
3934
5eb08b69 3935static enum drm_connector_status
a9756bb5 3936ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3937{
30add22d 3938 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3939 struct drm_i915_private *dev_priv = dev->dev_private;
3940 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3941
1b469639
DL		 3942 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3943 return connector_status_disconnected;
3944
26d61aad 3945 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3946}
3947
2a592bec
DA		 3948static int g4x_digital_port_connected(struct drm_device *dev,
3949 struct intel_digital_port *intel_dig_port)
a4fc5ed6 3950{
a4fc5ed6 3951 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 3952 uint32_t bit;
5eb08b69 3953
232a6ee9
TP		 3954 if (IS_VALLEYVIEW(dev)) {
3955 switch (intel_dig_port->port) {
3956 case PORT_B:
3957 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3958 break;
3959 case PORT_C:
3960 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3961 break;
3962 case PORT_D:
3963 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3964 break;
3965 default:
2a592bec 3966 return -EINVAL;
232a6ee9
TP		 3967 }
3968 } else {
3969 switch (intel_dig_port->port) {
3970 case PORT_B:
3971 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3972 break;
3973 case PORT_C:
3974 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3975 break;
3976 case PORT_D:
3977 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3978 break;
3979 default:
2a592bec 3980 return -EINVAL;
232a6ee9 3981 }
a4fc5ed6
KP		 3982 }
3983
10f76a38 3984 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 3985 return 0;
3986 return 1;
3987}
3988
3989static enum drm_connector_status
3990g4x_dp_detect(struct intel_dp *intel_dp)
3991{
3992 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3993 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3994 int ret;
3995
3996 /* Can't disconnect eDP, but you can close the lid... */
3997 if (is_edp(intel_dp)) {
3998 enum drm_connector_status status;
3999
4000 status = intel_panel_detect(dev);
4001 if (status == connector_status_unknown)
4002 status = connector_status_connected;
4003 return status;
4004 }
4005
4006 ret = g4x_digital_port_connected(dev, intel_dig_port);
4007 if (ret == -EINVAL)
4008 return connector_status_unknown;
4009 else if (ret == 0)
a4fc5ed6
KP		 4010 return connector_status_disconnected;
4011
26d61aad 4012 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4013}
4014
8c241fef 4015static struct edid *
beb60608 4016intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4017{
beb60608 4018 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4019
9cd300e0
JN		 4020 /* use cached edid if we have one */
4021 if (intel_connector->edid) {
9cd300e0
JN		 4022 /* invalid edid */
4023 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4024 return NULL;
4025
55e9edeb 4026 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4027 } else
4028 return drm_get_edid(&intel_connector->base,
4029 &intel_dp->aux.ddc);
4030}
8c241fef 4031
beb60608
CW		 4032static void
4033intel_dp_set_edid(struct intel_dp *intel_dp)
4034{
4035 struct intel_connector *intel_connector = intel_dp->attached_connector;
4036 struct edid *edid;
8c241fef 4037
beb60608
CW		 4038 edid = intel_dp_get_edid(intel_dp);
4039 intel_connector->detect_edid = edid;
4040
4041 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4042 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4043 else
4044 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4045}
4046
beb60608
CW		 4047static void
4048intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4049{
beb60608 4050 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4051
beb60608
CW		 4052 kfree(intel_connector->detect_edid);
4053 intel_connector->detect_edid = NULL;
9cd300e0 4054
beb60608
CW		 4055 intel_dp->has_audio = false;
4056}
d6f24d0f 4057
beb60608
CW		 4058static enum intel_display_power_domain
4059intel_dp_power_get(struct intel_dp *dp)
4060{
4061 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4062 enum intel_display_power_domain power_domain;
4063
4064 power_domain = intel_display_port_power_domain(encoder);
4065 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4066
4067 return power_domain;
4068}
d6f24d0f 4069
beb60608
CW		 4070static void
4071intel_dp_power_put(struct intel_dp *dp,
4072 enum intel_display_power_domain power_domain)
4073{
4074 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4075 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4076}
4077
a9756bb5
ZW		 4078static enum drm_connector_status
4079intel_dp_detect(struct drm_connector *connector, bool force)
4080{
4081 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4082 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4083 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4084 struct drm_device *dev = connector->dev;
a9756bb5 4085 enum drm_connector_status status;
671dedd2 4086 enum intel_display_power_domain power_domain;
0e32b39c 4087 bool ret;
a9756bb5 4088
164c8598 4089 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4090 connector->base.id, connector->name);
beb60608 4091 intel_dp_unset_edid(intel_dp);
164c8598 4092
0e32b39c
DA		 4093 if (intel_dp->is_mst) {
4094 /* MST devices are disconnected from a monitor POV */
4095 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4096 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4097 return connector_status_disconnected;
0e32b39c
DA		 4098 }
4099
beb60608 4100 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4101
d410b56d
CW		 4102 /* Can't disconnect eDP, but you can close the lid... */
4103 if (is_edp(intel_dp))
4104 status = edp_detect(intel_dp);
4105 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4106 status = ironlake_dp_detect(intel_dp);
4107 else
4108 status = g4x_dp_detect(intel_dp);
4109 if (status != connector_status_connected)
c8c8fb33 4110 goto out;
a9756bb5 4111
0d198328
AJ		 4112 intel_dp_probe_oui(intel_dp);
4113
0e32b39c
DA		 4114 ret = intel_dp_probe_mst(intel_dp);
4115 if (ret) {
4116 /* if we are in MST mode then this connector
4117 won't appear connected or have anything with EDID on it */
4118 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4119 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4120 status = connector_status_disconnected;
4121 goto out;
4122 }
4123
beb60608 4124 intel_dp_set_edid(intel_dp);
a9756bb5 4125
d63885da
PZ		 4126 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4127 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4128 status = connector_status_connected;
4129
4130out:
beb60608 4131 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4132 return status;
a4fc5ed6
KP		 4133}
4134
beb60608
CW		 4135static void
4136intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4137{
df0e9248 4138 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4139 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4140 enum intel_display_power_domain power_domain;
a4fc5ed6 4141
beb60608
CW		 4142 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4143 connector->base.id, connector->name);
4144 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4145
beb60608
CW		 4146 if (connector->status != connector_status_connected)
4147 return;
671dedd2 4148
beb60608
CW		 4149 power_domain = intel_dp_power_get(intel_dp);
4150
4151 intel_dp_set_edid(intel_dp);
4152
4153 intel_dp_power_put(intel_dp, power_domain);
4154
4155 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4156 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4157}
4158
4159static int intel_dp_get_modes(struct drm_connector *connector)
4160{
4161 struct intel_connector *intel_connector = to_intel_connector(connector);
4162 struct edid *edid;
4163
4164 edid = intel_connector->detect_edid;
4165 if (edid) {
4166 int ret = intel_connector_update_modes(connector, edid);
4167 if (ret)
4168 return ret;
4169 }
32f9d658 4170
f8779fda 4171 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4172 if (is_edp(intel_attached_dp(connector)) &&
4173 intel_connector->panel.fixed_mode) {
f8779fda 4174 struct drm_display_mode *mode;
beb60608
CW		 4175
4176 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4177 intel_connector->panel.fixed_mode);
f8779fda 4178 if (mode) {
32f9d658
ZW		 4179 drm_mode_probed_add(connector, mode);
4180 return 1;
4181 }
4182 }
beb60608 4183
32f9d658 4184 return 0;
a4fc5ed6
KP		 4185}
4186
1aad7ac0
CW		 4187static bool
4188intel_dp_detect_audio(struct drm_connector *connector)
4189{
1aad7ac0 4190 bool has_audio = false;
beb60608 4191 struct edid *edid;
1aad7ac0 4192
beb60608
CW		 4193 edid = to_intel_connector(connector)->detect_edid;
4194 if (edid)
1aad7ac0 4195 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4196
1aad7ac0
CW		 4197 return has_audio;
4198}
4199
f684960e
CW		 4200static int
4201intel_dp_set_property(struct drm_connector *connector,
4202 struct drm_property *property,
4203 uint64_t val)
4204{
e953fd7b 4205 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4206 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4207 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4208 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4209 int ret;
4210
662595df 4211 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4212 if (ret)
4213 return ret;
4214
3f43c48d 4215 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4216 int i = val;
4217 bool has_audio;
4218
4219 if (i == intel_dp->force_audio)
f684960e
CW		 4220 return 0;
4221
1aad7ac0 4222 intel_dp->force_audio = i;
f684960e 4223
c3e5f67b 4224 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4225 has_audio = intel_dp_detect_audio(connector);
4226 else
c3e5f67b 4227 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4228
4229 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4230 return 0;
4231
1aad7ac0 4232 intel_dp->has_audio = has_audio;
f684960e
CW		 4233 goto done;
4234 }
4235
e953fd7b 4236 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4237 bool old_auto = intel_dp->color_range_auto;
4238 uint32_t old_range = intel_dp->color_range;
4239
55bc60db
VS		 4240 switch (val) {
4241 case INTEL_BROADCAST_RGB_AUTO:
4242 intel_dp->color_range_auto = true;
4243 break;
4244 case INTEL_BROADCAST_RGB_FULL:
4245 intel_dp->color_range_auto = false;
4246 intel_dp->color_range = 0;
4247 break;
4248 case INTEL_BROADCAST_RGB_LIMITED:
4249 intel_dp->color_range_auto = false;
4250 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4251 break;
4252 default:
4253 return -EINVAL;
4254 }
ae4edb80
DV		 4255
4256 if (old_auto == intel_dp->color_range_auto &&
4257 old_range == intel_dp->color_range)
4258 return 0;
4259
e953fd7b
CW		 4260 goto done;
4261 }
4262
53b41837
YN		 4263 if (is_edp(intel_dp) &&
4264 property == connector->dev->mode_config.scaling_mode_property) {
4265 if (val == DRM_MODE_SCALE_NONE) {
4266 DRM_DEBUG_KMS("no scaling not supported\n");
4267 return -EINVAL;
4268 }
4269
4270 if (intel_connector->panel.fitting_mode == val) {
4271 /* the eDP scaling property is not changed */
4272 return 0;
4273 }
4274 intel_connector->panel.fitting_mode = val;
4275
4276 goto done;
4277 }
4278
f684960e
CW		 4279 return -EINVAL;
4280
4281done:
c0c36b94
CW		 4282 if (intel_encoder->base.crtc)
4283 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4284
4285 return 0;
4286}
4287
a4fc5ed6 4288static void
73845adf 4289intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4290{
1d508706 4291 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4292
10e972d3 4293 kfree(intel_connector->detect_edid);
beb60608 4294
9cd300e0
JN		 4295 if (!IS_ERR_OR_NULL(intel_connector->edid))
4296 kfree(intel_connector->edid);
4297
acd8db10
PZ		 4298 /* Can't call is_edp() since the encoder may have been destroyed
4299 * already. */
4300 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4301 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4302
a4fc5ed6 4303 drm_connector_cleanup(connector);
55f78c43 4304 kfree(connector);
a4fc5ed6
KP		 4305}
4306
00c09d70 4307void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4308{
da63a9f2
PZ		 4309 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4310 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4311
4f71d0cb 4312 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4313 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4314 if (is_edp(intel_dp)) {
4315 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4316 /*
4317 * vdd might still be enabled do to the delayed vdd off.
4318 * Make sure vdd is actually turned off here.
4319 */
773538e8 4320 pps_lock(intel_dp);
4be73780 4321 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4322 pps_unlock(intel_dp);
4323
01527b31
CT		 4324 if (intel_dp->edp_notifier.notifier_call) {
4325 unregister_reboot_notifier(&intel_dp->edp_notifier);
4326 intel_dp->edp_notifier.notifier_call = NULL;
4327 }
bd943159 4328 }
c8bd0e49 4329 drm_encoder_cleanup(encoder);
da63a9f2 4330 kfree(intel_dig_port);
24d05927
DV		 4331}
4332
07f9cd0b
ID		 4333static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4334{
4335 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4336
4337 if (!is_edp(intel_dp))
4338 return;
4339
951468f3
VS		 4340 /*
4341 * vdd might still be enabled do to the delayed vdd off.
4342 * Make sure vdd is actually turned off here.
4343 */
afa4e53a 4344 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4345 pps_lock(intel_dp);
07f9cd0b 4346 edp_panel_vdd_off_sync(intel_dp);
773538e8 4347 pps_unlock(intel_dp);
07f9cd0b
ID		 4348}
4349
49e6bc51
VS		 4350static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4351{
4352 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4353 struct drm_device *dev = intel_dig_port->base.base.dev;
4354 struct drm_i915_private *dev_priv = dev->dev_private;
4355 enum intel_display_power_domain power_domain;
4356
4357 lockdep_assert_held(&dev_priv->pps_mutex);
4358
4359 if (!edp_have_panel_vdd(intel_dp))
4360 return;
4361
4362 /*
4363 * The VDD bit needs a power domain reference, so if the bit is
4364 * already enabled when we boot or resume, grab this reference and
4365 * schedule a vdd off, so we don't hold on to the reference
4366 * indefinitely.
4367 */
4368 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4369 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4370 intel_display_power_get(dev_priv, power_domain);
4371
4372 edp_panel_vdd_schedule_off(intel_dp);
4373}
4374
6d93c0c4
ID		 4375static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4376{
49e6bc51
VS		 4377 struct intel_dp *intel_dp;
4378
4379 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4380 return;
4381
4382 intel_dp = enc_to_intel_dp(encoder);
4383
4384 pps_lock(intel_dp);
4385
4386 /*
4387 * Read out the current power sequencer assignment,
4388 * in case the BIOS did something with it.
4389 */
4390 if (IS_VALLEYVIEW(encoder->dev))
4391 vlv_initial_power_sequencer_setup(intel_dp);
4392
4393 intel_edp_panel_vdd_sanitize(intel_dp);
4394
4395 pps_unlock(intel_dp);
6d93c0c4
ID		 4396}
4397
a4fc5ed6 4398static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4399 .dpms = intel_connector_dpms,
a4fc5ed6 4400 .detect = intel_dp_detect,
beb60608 4401 .force = intel_dp_force,
a4fc5ed6 4402 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4403 .set_property = intel_dp_set_property,
73845adf 4404 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4405};
4406
4407static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4408 .get_modes = intel_dp_get_modes,
4409 .mode_valid = intel_dp_mode_valid,
df0e9248 4410 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4411};
4412
a4fc5ed6 4413static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4414 .reset = intel_dp_encoder_reset,
24d05927 4415 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4416};
4417
0e32b39c 4418void
21d40d37 4419intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4420{
0e32b39c 4421 return;
c8110e52 4422}
6207937d 4423
b2c5c181 4424enum irqreturn
13cf5504
DA		 4425intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4426{
4427 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4428 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4429 struct drm_device *dev = intel_dig_port->base.base.dev;
4430 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4431 enum intel_display_power_domain power_domain;
b2c5c181 4432 enum irqreturn ret = IRQ_NONE;
1c767b33 4433
0e32b39c
DA		 4434 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4435 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4436
7a7f84cc
VS		 4437 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4438 /*
4439 * vdd off can generate a long pulse on eDP which
4440 * would require vdd on to handle it, and thus we
4441 * would end up in an endless cycle of
4442 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4443 */
4444 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4445 port_name(intel_dig_port->port));
4446 return false;
4447 }
4448
26fbb774
VS		 4449 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4450 port_name(intel_dig_port->port),
0e32b39c 4451 long_hpd ? "long" : "short");
13cf5504 4452
1c767b33
ID		 4453 power_domain = intel_display_port_power_domain(intel_encoder);
4454 intel_display_power_get(dev_priv, power_domain);
4455
0e32b39c 4456 if (long_hpd) {
2a592bec
DA		 4457
4458 if (HAS_PCH_SPLIT(dev)) {
4459 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4460 goto mst_fail;
4461 } else {
4462 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4463 goto mst_fail;
4464 }
0e32b39c
DA		 4465
4466 if (!intel_dp_get_dpcd(intel_dp)) {
4467 goto mst_fail;
4468 }
4469
4470 intel_dp_probe_oui(intel_dp);
4471
4472 if (!intel_dp_probe_mst(intel_dp))
4473 goto mst_fail;
4474
4475 } else {
4476 if (intel_dp->is_mst) {
1c767b33 4477 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4478 goto mst_fail;
4479 }
4480
4481 if (!intel_dp->is_mst) {
4482 /*
4483 * we'll check the link status via the normal hot plug path later -
4484 * but for short hpds we should check it now
4485 */
5b215bcf 4486 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4487 intel_dp_check_link_status(intel_dp);
5b215bcf 4488 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4489 }
4490 }
b2c5c181
DV		 4491
4492 ret = IRQ_HANDLED;
4493
1c767b33 4494 goto put_power;
0e32b39c
DA		 4495mst_fail:
4496 /* if we were in MST mode, and device is not there get out of MST mode */
4497 if (intel_dp->is_mst) {
4498 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4499 intel_dp->is_mst = false;
4500 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4501 }
1c767b33
ID		 4502put_power:
4503 intel_display_power_put(dev_priv, power_domain);
4504
4505 return ret;
13cf5504
DA		 4506}
4507
e3421a18
ZW		 4508/* Return which DP Port should be selected for Transcoder DP control */
4509int
0206e353 4510intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4511{
4512 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4513 struct intel_encoder *intel_encoder;
4514 struct intel_dp *intel_dp;
e3421a18 4515
fa90ecef
PZ		 4516 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4517 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4518
fa90ecef
PZ		 4519 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4520 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4521 return intel_dp->output_reg;
e3421a18 4522 }
ea5b213a 4523
e3421a18
ZW		 4524 return -1;
4525}
4526
36e83a18 4527/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4528bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4529{
4530 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4531 union child_device_config *p_child;
36e83a18 4532 int i;
5d8a7752
VS		 4533 static const short port_mapping[] = {
4534 [PORT_B] = PORT_IDPB,
4535 [PORT_C] = PORT_IDPC,
4536 [PORT_D] = PORT_IDPD,
4537 };
36e83a18 4538
3b32a35b
VS		 4539 if (port == PORT_A)
4540 return true;
4541
41aa3448 4542 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4543 return false;
4544
41aa3448
RV		 4545 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4546 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4547
5d8a7752 4548 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4549 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4550 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4551 return true;
4552 }
4553 return false;
4554}
4555
0e32b39c 4556void
f684960e
CW		 4557intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4558{
53b41837
YN		 4559 struct intel_connector *intel_connector = to_intel_connector(connector);
4560
3f43c48d 4561 intel_attach_force_audio_property(connector);
e953fd7b 4562 intel_attach_broadcast_rgb_property(connector);
55bc60db 4563 intel_dp->color_range_auto = true;
53b41837
YN		 4564
4565 if (is_edp(intel_dp)) {
4566 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4567 drm_object_attach_property(
4568 &connector->base,
53b41837 4569 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4570 DRM_MODE_SCALE_ASPECT);
4571 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4572 }
f684960e
CW		 4573}
4574
dada1a9f
ID		 4575static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4576{
4577 intel_dp->last_power_cycle = jiffies;
4578 intel_dp->last_power_on = jiffies;
4579 intel_dp->last_backlight_off = jiffies;
4580}
4581
67a54566
DV		 4582static void
4583intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4584 struct intel_dp *intel_dp)
67a54566
DV		 4585{
4586 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4587 struct edp_power_seq cur, vbt, spec,
4588 *final = &intel_dp->pps_delays;
67a54566 4589 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4590 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4591
e39b999a
VS		 4592 lockdep_assert_held(&dev_priv->pps_mutex);
4593
81ddbc69
VS		 4594 /* already initialized? */
4595 if (final->t11_t12 != 0)
4596 return;
4597
453c5420 4598 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4599 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4600 pp_on_reg = PCH_PP_ON_DELAYS;
4601 pp_off_reg = PCH_PP_OFF_DELAYS;
4602 pp_div_reg = PCH_PP_DIVISOR;
4603 } else {
bf13e81b
JN		 4604 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4605
4606 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4607 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4608 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4609 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4610 }
67a54566
DV		 4611
4612 /* Workaround: Need to write PP_CONTROL with the unlock key as
4613 * the very first thing. */
453c5420 4614 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4615 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4616
453c5420
JB		 4617 pp_on = I915_READ(pp_on_reg);
4618 pp_off = I915_READ(pp_off_reg);
4619 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4620
4621 /* Pull timing values out of registers */
4622 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4623 PANEL_POWER_UP_DELAY_SHIFT;
4624
4625 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4626 PANEL_LIGHT_ON_DELAY_SHIFT;
4627
4628 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4629 PANEL_LIGHT_OFF_DELAY_SHIFT;
4630
4631 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4632 PANEL_POWER_DOWN_DELAY_SHIFT;
4633
4634 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4635 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4636
4637 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4638 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4639
41aa3448 4640 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4641
4642 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4643 * our hw here, which are all in 100usec. */
4644 spec.t1_t3 = 210 * 10;
4645 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4646 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4647 spec.t10 = 500 * 10;
4648 /* This one is special and actually in units of 100ms, but zero
4649 * based in the hw (so we need to add 100 ms). But the sw vbt
4650 * table multiplies it with 1000 to make it in units of 100usec,
4651 * too. */
4652 spec.t11_t12 = (510 + 100) * 10;
4653
4654 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4655 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4656
4657 /* Use the max of the register settings and vbt. If both are
4658 * unset, fall back to the spec limits. */
36b5f425 4659#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4660 spec.field : \
4661 max(cur.field, vbt.field))
4662 assign_final(t1_t3);
4663 assign_final(t8);
4664 assign_final(t9);
4665 assign_final(t10);
4666 assign_final(t11_t12);
4667#undef assign_final
4668
36b5f425 4669#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4670 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4671 intel_dp->backlight_on_delay = get_delay(t8);
4672 intel_dp->backlight_off_delay = get_delay(t9);
4673 intel_dp->panel_power_down_delay = get_delay(t10);
4674 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4675#undef get_delay
4676
f30d26e4
JN		 4677 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4678 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4679 intel_dp->panel_power_cycle_delay);
4680
4681 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4682 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4683}
4684
4685static void
4686intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4687 struct intel_dp *intel_dp)
f30d26e4
JN		 4688{
4689 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4690 u32 pp_on, pp_off, pp_div, port_sel = 0;
4691 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4692 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4693 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4694 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4695
e39b999a 4696 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4697
4698 if (HAS_PCH_SPLIT(dev)) {
4699 pp_on_reg = PCH_PP_ON_DELAYS;
4700 pp_off_reg = PCH_PP_OFF_DELAYS;
4701 pp_div_reg = PCH_PP_DIVISOR;
4702 } else {
bf13e81b
JN		 4703 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4704
4705 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4706 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4707 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4708 }
4709
b2f19d1a
PZ		 4710 /*
4711 * And finally store the new values in the power sequencer. The
4712 * backlight delays are set to 1 because we do manual waits on them. For
4713 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4714 * we'll end up waiting for the backlight off delay twice: once when we
4715 * do the manual sleep, and once when we disable the panel and wait for
4716 * the PP_STATUS bit to become zero.
4717 */
f30d26e4 4718 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4719 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4720 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4721 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4722 /* Compute the divisor for the pp clock, simply match the Bspec
4723 * formula. */
453c5420 4724 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4725 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4726 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4727
4728 /* Haswell doesn't have any port selection bits for the panel
4729 * power sequencer any more. */
bc7d38a4 4730 if (IS_VALLEYVIEW(dev)) {
ad933b56 4731 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4732 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4733 if (port == PORT_A)
a24c144c 4734 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4735 else
a24c144c 4736 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4737 }
4738
453c5420
JB		 4739 pp_on |= port_sel;
4740
4741 I915_WRITE(pp_on_reg, pp_on);
4742 I915_WRITE(pp_off_reg, pp_off);
4743 I915_WRITE(pp_div_reg, pp_div);
67a54566 4744
67a54566 4745 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4746 I915_READ(pp_on_reg),
4747 I915_READ(pp_off_reg),
4748 I915_READ(pp_div_reg));
f684960e
CW		 4749}
4750
96178eeb 4751static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 4752{
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 struct intel_encoder *encoder;
96178eeb
VK		 4755 struct intel_digital_port *dig_port = NULL;
4756 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 4757 struct intel_crtc_state *config = NULL;
439d7ac0 4758 struct intel_crtc *intel_crtc = NULL;
439d7ac0 4759 u32 reg, val;
96178eeb 4760 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 4761
4762 if (refresh_rate <= 0) {
4763 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4764 return;
4765 }
4766
96178eeb
VK		 4767 if (intel_dp == NULL) {
4768 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 4769 return;
4770 }
4771
1fcc9d1c 4772 /*
e4d59f6b
RV		 4773 * FIXME: This needs proper synchronization with psr state for some
4774 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 4775 */
439d7ac0 4776
96178eeb
VK		 4777 dig_port = dp_to_dig_port(intel_dp);
4778 encoder = &dig_port->base;
439d7ac0
PB		 4779 intel_crtc = encoder->new_crtc;
4780
4781 if (!intel_crtc) {
4782 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4783 return;
4784 }
4785
6e3c9717 4786 config = intel_crtc->config;
439d7ac0 4787
96178eeb 4788 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 4789 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4790 return;
4791 }
4792
96178eeb
VK		 4793 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
4794 refresh_rate)
439d7ac0
PB		 4795 index = DRRS_LOW_RR;
4796
96178eeb 4797 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 4798 DRM_DEBUG_KMS(
4799 "DRRS requested for previously set RR...ignoring\n");
4800 return;
4801 }
4802
4803 if (!intel_crtc->active) {
4804 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4805 return;
4806 }
4807
4808 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
6e3c9717 4809 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0
PB		 4810 val = I915_READ(reg);
4811 if (index > DRRS_HIGH_RR) {
4812 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4813 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4814 } else {
4815 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4816 }
4817 I915_WRITE(reg, val);
4818 }
4819
4820 /*
4821 * mutex taken to ensure that there is no race between differnt
4822 * drrs calls trying to update refresh rate. This scenario may occur
4823 * in future when idleness detection based DRRS in kernel and
4824 * possible calls from user space to set differnt RR are made.
4825 */
4826
96178eeb 4827 mutex_lock(&dev_priv->drrs.mutex);
439d7ac0 4828
96178eeb 4829 dev_priv->drrs.refresh_rate_type = index;
439d7ac0 4830
96178eeb 4831 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 4832
4833 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4834}
4835
4f9db5b5 4836static struct drm_display_mode *
96178eeb
VK		 4837intel_dp_drrs_init(struct intel_connector *intel_connector,
4838 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 4839{
4840 struct drm_connector *connector = &intel_connector->base;
96178eeb 4841 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 4842 struct drm_i915_private *dev_priv = dev->dev_private;
4843 struct drm_display_mode *downclock_mode = NULL;
4844
4845 if (INTEL_INFO(dev)->gen <= 6) {
4846 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4847 return NULL;
4848 }
4849
4850 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4851 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4852 return NULL;
4853 }
4854
4855 downclock_mode = intel_find_panel_downclock
4856 (dev, fixed_mode, connector);
4857
4858 if (!downclock_mode) {
4079b8d1 4859 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4860 return NULL;
4861 }
4862
96178eeb 4863 mutex_init(&dev_priv->drrs.mutex);
439d7ac0 4864
96178eeb 4865 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 4866
96178eeb 4867 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4868 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4869 return downclock_mode;
4870}
4871
ed92f0b2 4872static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 4873 struct intel_connector *intel_connector)
ed92f0b2
PZ		 4874{
4875 struct drm_connector *connector = &intel_connector->base;
4876 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4877 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4878 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4879 struct drm_i915_private *dev_priv = dev->dev_private;
4880 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4881 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4882 bool has_dpcd;
4883 struct drm_display_mode *scan;
4884 struct edid *edid;
6517d273 4885 enum pipe pipe = INVALID_PIPE;
ed92f0b2 4886
96178eeb 4887 dev_priv->drrs.type = DRRS_NOT_SUPPORTED;
4f9db5b5 4888
ed92f0b2
PZ		 4889 if (!is_edp(intel_dp))
4890 return true;
4891
49e6bc51
VS		 4892 pps_lock(intel_dp);
4893 intel_edp_panel_vdd_sanitize(intel_dp);
4894 pps_unlock(intel_dp);
63635217 4895
ed92f0b2 4896 /* Cache DPCD and EDID for edp. */
ed92f0b2 4897 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 4898
4899 if (has_dpcd) {
4900 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4901 dev_priv->no_aux_handshake =
4902 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4903 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4904 } else {
4905 /* if this fails, presume the device is a ghost */
4906 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4907 return false;
4908 }
4909
4910 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4911 pps_lock(intel_dp);
36b5f425 4912 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 4913 pps_unlock(intel_dp);
ed92f0b2 4914
060c8778 4915 mutex_lock(&dev->mode_config.mutex);
0b99836f 4916 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4917 if (edid) {
4918 if (drm_add_edid_modes(connector, edid)) {
4919 drm_mode_connector_update_edid_property(connector,
4920 edid);
4921 drm_edid_to_eld(connector, edid);
4922 } else {
4923 kfree(edid);
4924 edid = ERR_PTR(-EINVAL);
4925 }
4926 } else {
4927 edid = ERR_PTR(-ENOENT);
4928 }
4929 intel_connector->edid = edid;
4930
4931 /* prefer fixed mode from EDID if available */
4932 list_for_each_entry(scan, &connector->probed_modes, head) {
4933 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4934 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 4935 downclock_mode = intel_dp_drrs_init(
4f9db5b5 4936 intel_connector, fixed_mode);
ed92f0b2
PZ		 4937 break;
4938 }
4939 }
4940
4941 /* fallback to VBT if available for eDP */
4942 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4943 fixed_mode = drm_mode_duplicate(dev,
4944 dev_priv->vbt.lfp_lvds_vbt_mode);
4945 if (fixed_mode)
4946 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4947 }
060c8778 4948 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4949
01527b31
CT		 4950 if (IS_VALLEYVIEW(dev)) {
4951 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4952 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 4953
4954 /*
4955 * Figure out the current pipe for the initial backlight setup.
4956 * If the current pipe isn't valid, try the PPS pipe, and if that
4957 * fails just assume pipe A.
4958 */
4959 if (IS_CHERRYVIEW(dev))
4960 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
4961 else
4962 pipe = PORT_TO_PIPE(intel_dp->DP);
4963
4964 if (pipe != PIPE_A && pipe != PIPE_B)
4965 pipe = intel_dp->pps_pipe;
4966
4967 if (pipe != PIPE_A && pipe != PIPE_B)
4968 pipe = PIPE_A;
4969
4970 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
4971 pipe_name(pipe));
01527b31
CT		 4972 }
4973
4f9db5b5 4974 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4975 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 4976 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 4977
4978 return true;
4979}
4980
16c25533 4981bool
f0fec3f2
PZ		 4982intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4983 struct intel_connector *intel_connector)
a4fc5ed6 4984{
f0fec3f2
PZ		 4985 struct drm_connector *connector = &intel_connector->base;
4986 struct intel_dp *intel_dp = &intel_dig_port->dp;
4987 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4988 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4989 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4990 enum port port = intel_dig_port->port;
0b99836f 4991 int type;
a4fc5ed6 4992
a4a5d2f8
VS		 4993 intel_dp->pps_pipe = INVALID_PIPE;
4994
ec5b01dd 4995 /* intel_dp vfuncs */
b6b5e383
DL		 4996 if (INTEL_INFO(dev)->gen >= 9)
4997 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
4998 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 4999 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5000 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5001 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5002 else if (HAS_PCH_SPLIT(dev))
5003 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5004 else
5005 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5006
b9ca5fad
DL		 5007 if (INTEL_INFO(dev)->gen >= 9)
5008 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5009 else
5010 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5011
0767935e
DV		 5012 /* Preserve the current hw state. */
5013 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5014 intel_dp->attached_connector = intel_connector;
3d3dc149 5015
3b32a35b 5016 if (intel_dp_is_edp(dev, port))
b329530c 5017 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5018 else
5019 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5020
f7d24902
ID		 5021 /*
5022 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5023 * for DP the encoder type can be set by the caller to
5024 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5025 */
5026 if (type == DRM_MODE_CONNECTOR_eDP)
5027 intel_encoder->type = INTEL_OUTPUT_EDP;
5028
c17ed5b5
VS		 5029 /* eDP only on port B and/or C on vlv/chv */
5030 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5031 port != PORT_B && port != PORT_C))
5032 return false;
5033
e7281eab
ID		 5034 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5035 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5036 port_name(port));
5037
b329530c 5038 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5039 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5040
a4fc5ed6
KP		 5041 connector->interlace_allowed = true;
5042 connector->doublescan_allowed = 0;
5043
f0fec3f2 5044 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5045 edp_panel_vdd_work);
a4fc5ed6 5046
df0e9248 5047 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5048 drm_connector_register(connector);
a4fc5ed6 5049
affa9354 5050 if (HAS_DDI(dev))
bcbc889b
PZ		 5051 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5052 else
5053 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5054 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5055
0b99836f 5056 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5057 switch (port) {
5058 case PORT_A:
1d843f9d 5059 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5060 break;
5061 case PORT_B:
1d843f9d 5062 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5063 break;
5064 case PORT_C:
1d843f9d 5065 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5066 break;
5067 case PORT_D:
1d843f9d 5068 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5069 break;
5070 default:
ad1c0b19 5071 BUG();
5eb08b69
ZW		 5072 }
5073
dada1a9f 5074 if (is_edp(intel_dp)) {
773538e8 5075 pps_lock(intel_dp);
1e74a324
VS		 5076 intel_dp_init_panel_power_timestamps(intel_dp);
5077 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5078 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5079 else
36b5f425 5080 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5081 pps_unlock(intel_dp);
dada1a9f 5082 }
0095e6dc 5083
9d1a1031 5084 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5085
0e32b39c 5086 /* init MST on ports that can support it */
c86ea3d0 5087 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
0e32b39c 5088 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5089 intel_dp_mst_encoder_init(intel_dig_port,
5090 intel_connector->base.base.id);
0e32b39c
DA		 5091 }
5092 }
5093
36b5f425 5094 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5095 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5096 if (is_edp(intel_dp)) {
5097 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5098 /*
5099 * vdd might still be enabled do to the delayed vdd off.
5100 * Make sure vdd is actually turned off here.
5101 */
773538e8 5102 pps_lock(intel_dp);
4be73780 5103 edp_panel_vdd_off_sync(intel_dp);
773538e8 5104 pps_unlock(intel_dp);
15b1d171 5105 }
34ea3d38 5106 drm_connector_unregister(connector);
b2f246a8 5107 drm_connector_cleanup(connector);
16c25533 5108 return false;
b2f246a8 5109 }
32f9d658 5110
f684960e
CW		 5111 intel_dp_add_properties(intel_dp, connector);
5112
a4fc5ed6
KP		 5113 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5114 * 0xd. Failure to do so will result in spurious interrupts being
5115 * generated on the port when a cable is not attached.
5116 */
5117 if (IS_G4X(dev) && !IS_GM45(dev)) {
5118 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5119 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5120 }
16c25533
PZ		 5121
5122 return true;
a4fc5ed6 5123}
f0fec3f2
PZ		 5124
5125void
5126intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5127{
13cf5504 5128 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5129 struct intel_digital_port *intel_dig_port;
5130 struct intel_encoder *intel_encoder;
5131 struct drm_encoder *encoder;
5132 struct intel_connector *intel_connector;
5133
b14c5679 5134 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5135 if (!intel_dig_port)
5136 return;
5137
b14c5679 5138 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5139 if (!intel_connector) {
5140 kfree(intel_dig_port);
5141 return;
5142 }
5143
5144 intel_encoder = &intel_dig_port->base;
5145 encoder = &intel_encoder->base;
5146
5147 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5148 DRM_MODE_ENCODER_TMDS);
5149
5bfe2ac0 5150 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5151 intel_encoder->disable = intel_disable_dp;
00c09d70 5152 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5153 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5154 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5155 if (IS_CHERRYVIEW(dev)) {
9197c88b 5156 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5157 intel_encoder->pre_enable = chv_pre_enable_dp;
5158 intel_encoder->enable = vlv_enable_dp;
580d3811 5159 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5160 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5161 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5162 intel_encoder->pre_enable = vlv_pre_enable_dp;
5163 intel_encoder->enable = vlv_enable_dp;
49277c31 5164 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5165 } else {
ecff4f3b
JN		 5166 intel_encoder->pre_enable = g4x_pre_enable_dp;
5167 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5168 if (INTEL_INFO(dev)->gen >= 5)
5169 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5170 }
f0fec3f2 5171
174edf1f 5172 intel_dig_port->port = port;
f0fec3f2
PZ		 5173 intel_dig_port->dp.output_reg = output_reg;
5174
00c09d70 5175 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5176 if (IS_CHERRYVIEW(dev)) {
5177 if (port == PORT_D)
5178 intel_encoder->crtc_mask = 1 << 2;
5179 else
5180 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5181 } else {
5182 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5183 }
bc079e8b 5184 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5185 intel_encoder->hot_plug = intel_dp_hot_plug;
5186
13cf5504
DA		 5187 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5188 dev_priv->hpd_irq_port[port] = intel_dig_port;
5189
15b1d171
PZ		 5190 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5191 drm_encoder_cleanup(encoder);
5192 kfree(intel_dig_port);
b2f246a8 5193 kfree(intel_connector);
15b1d171 5194 }
f0fec3f2 5195}
0e32b39c
DA		 5196
5197void intel_dp_mst_suspend(struct drm_device *dev)
5198{
5199 struct drm_i915_private *dev_priv = dev->dev_private;
5200 int i;
5201
5202 /* disable MST */
5203 for (i = 0; i < I915_MAX_PORTS; i++) {
5204 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5205 if (!intel_dig_port)
5206 continue;
5207
5208 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5209 if (!intel_dig_port->dp.can_mst)
5210 continue;
5211 if (intel_dig_port->dp.is_mst)
5212 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5213 }
5214 }
5215}
5216
5217void intel_dp_mst_resume(struct drm_device *dev)
5218{
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 int i;
5221
5222 for (i = 0; i < I915_MAX_PORTS; i++) {
5223 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5224 if (!intel_dig_port)
5225 continue;
5226 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5227 int ret;
5228
5229 if (!intel_dig_port->dp.can_mst)
5230 continue;
5231
5232 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5233 if (ret != 0) {
5234 intel_dp_check_mst_status(&intel_dig_port->dp);
5235 }
5236 }
5237 }
5238}
Linux kernel - Deliverables
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