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drm/i915: Add messages useful for HPD storm detection debugging (v2)
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
68b4d824 55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 56{
68b4d824
ID		 57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 60}
61
df0e9248
CW		 62static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63{
fa90ecef 64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 65}
66
ea5b213a 67static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 68
a4fc5ed6 69static int
ea5b213a 70intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 71{
7183dc29 72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
d4eead50
ID		 78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
80 break;
a4fc5ed6 81 default:
d4eead50
ID		 82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
83 max_link_bw);
a4fc5ed6
KP		 84 max_link_bw = DP_LINK_BW_1_62;
85 break;
86 }
87 return max_link_bw;
88}
89
cd9dde44
AJ		 90/*
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
93 *
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
95 *
96 * 270000 * 1 * 8 / 10 == 216000
97 *
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
102 *
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
105 */
106
a4fc5ed6 107static int
c898261c 108intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 109{
cd9dde44 110 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 111}
112
fe27d53e
DA		 113static int
114intel_dp_max_data_rate(int max_link_clock, int max_lanes)
115{
116 return (max_link_clock * max_lanes * 8) / 10;
117}
118
a4fc5ed6
KP		 119static int
120intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
122{
df0e9248 123 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 128
dd06f90e
JN		 129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 131 return MODE_PANEL;
132
dd06f90e 133 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 134 return MODE_PANEL;
03afc4a2
DV		 135
136 target_clock = fixed_mode->clock;
7de56f43
ZY		 137 }
138
36008365
DV		 139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
141
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
144
145 if (mode_rate > max_rate)
c4867936 146 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 147
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
150
0af78a2b
DV		 151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
153
a4fc5ed6
KP		 154 return MODE_OK;
155}
156
157static uint32_t
158pack_aux(uint8_t *src, int src_bytes)
159{
160 int i;
161 uint32_t v = 0;
162
163 if (src_bytes > 4)
164 src_bytes = 4;
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
167 return v;
168}
169
170static void
171unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
172{
173 int i;
174 if (dst_bytes > 4)
175 dst_bytes = 4;
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
178}
179
fb0f8fbf
KP		 180/* hrawclock is 1/4 the FSB frequency */
181static int
182intel_hrawclk(struct drm_device *dev)
183{
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
9473c8f4
VP		 187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
fb0f8fbf
KP		 191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212}
213
ebf33b18
KP		 214static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
215{
30add22d 216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 217 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 218 u32 pp_stat_reg;
ebf33b18 219
453c5420
JB		 220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 222}
223
224static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
225{
30add22d 226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 227 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 228 u32 pp_ctrl_reg;
ebf33b18 229
453c5420
JB		 230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 232}
233
9b984dae
KP		 234static void
235intel_dp_check_edp(struct intel_dp *intel_dp)
236{
30add22d 237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 238 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 239 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 240
9b984dae
KP		 241 if (!is_edp(intel_dp))
242 return;
453c5420
JB		 243
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
246
ebf33b18 247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
9b984dae
KP		 252 }
253}
254
9ee32fea
DV		 255static uint32_t
256intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
257{
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 262 uint32_t status;
263 bool done;
264
ef04f00d 265#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 266 if (has_aux_irq)
b18ac466 267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 268 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 269 else
270 done = wait_for_atomic(C, 10) == 0;
271 if (!done)
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
273 has_aux_irq);
274#undef C
275
276 return status;
277}
278
b84a1cf8 279static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp)
a4fc5ed6 280{
174edf1f
PZ		 281 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
282 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 283 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 284
a4fc5ed6 285 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 286 * and would like to run at 2MHz. So, take the
287 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 288 *
289 * Note that PCH attached eDP panels should use a 125MHz input
290 * clock divider.
a4fc5ed6 291 */
a62d0834 292 if (IS_VALLEYVIEW(dev)) {
b84a1cf8 293 return 100;
a62d0834 294 } else if (intel_dig_port->port == PORT_A) {
affa9354 295 if (HAS_DDI(dev))
b84a1cf8 296 return DIV_ROUND_CLOSEST(
b2b877ff 297 intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 298 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 299 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 300 else
b84a1cf8 301 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 302 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
303 /* Workaround for non-ULT HSW */
b84a1cf8 304 return 74;
2c55c336 305 } else if (HAS_PCH_SPLIT(dev)) {
b84a1cf8 306 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 307 } else {
b84a1cf8 308 return intel_hrawclk(dev) / 2;
2c55c336 309 }
b84a1cf8
RV		 310}
311
312static int
313intel_dp_aux_ch(struct intel_dp *intel_dp,
314 uint8_t *send, int send_bytes,
315 uint8_t *recv, int recv_size)
316{
317 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
318 struct drm_device *dev = intel_dig_port->base.base.dev;
319 struct drm_i915_private *dev_priv = dev->dev_private;
320 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
321 uint32_t ch_data = ch_ctl + 4;
322 int i, ret, recv_bytes;
323 uint32_t status;
324 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp);
325 int try, precharge;
326 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
327
328 /* dp aux is extremely sensitive to irq latency, hence request the
329 * lowest possible wakeup latency and so prevent the cpu from going into
330 * deep sleep states.
331 */
332 pm_qos_update_request(&dev_priv->pm_qos, 0);
333
334 intel_dp_check_edp(intel_dp);
5eb08b69 335
6b4e0a93
DV		 336 if (IS_GEN6(dev))
337 precharge = 3;
338 else
339 precharge = 5;
340
11bee43e
JB		 341 /* Try to wait for any previous AUX channel activity */
342 for (try = 0; try < 3; try++) {
ef04f00d 343 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 344 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
345 break;
346 msleep(1);
347 }
348
349 if (try == 3) {
350 WARN(1, "dp_aux_ch not started status 0x%08x\n",
351 I915_READ(ch_ctl));
9ee32fea
DV		 352 ret = -EBUSY;
353 goto out;
4f7f7b7e
CW		 354 }
355
fb0f8fbf
KP		 356 /* Must try at least 3 times according to DP spec */
357 for (try = 0; try < 5; try++) {
358 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 359 for (i = 0; i < send_bytes; i += 4)
360 I915_WRITE(ch_data + i,
361 pack_aux(send + i, send_bytes - i));
0206e353 362
fb0f8fbf 363 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 364 I915_WRITE(ch_ctl,
365 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 366 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 367 DP_AUX_CH_CTL_TIME_OUT_400us |
368 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
369 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
370 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
371 DP_AUX_CH_CTL_DONE |
372 DP_AUX_CH_CTL_TIME_OUT_ERROR |
373 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 374
375 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 376
fb0f8fbf 377 /* Clear done status and any errors */
4f7f7b7e
CW		 378 I915_WRITE(ch_ctl,
379 status |
380 DP_AUX_CH_CTL_DONE |
381 DP_AUX_CH_CTL_TIME_OUT_ERROR |
382 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 383
384 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
385 DP_AUX_CH_CTL_RECEIVE_ERROR))
386 continue;
4f7f7b7e 387 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 388 break;
389 }
390
a4fc5ed6 391 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 392 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 393 ret = -EBUSY;
394 goto out;
a4fc5ed6
KP		 395 }
396
397 /* Check for timeout or receive error.
398 * Timeouts occur when the sink is not connected
399 */
a5b3da54 400 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 401 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 402 ret = -EIO;
403 goto out;
a5b3da54 404 }
1ae8c0a5
KP		 405
406 /* Timeouts occur when the device isn't connected, so they're
407 * "normal" -- don't fill the kernel log with these */
a5b3da54 408 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 409 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 410 ret = -ETIMEDOUT;
411 goto out;
a4fc5ed6
KP		 412 }
413
414 /* Unload any bytes sent back from the other side */
415 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
416 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 417 if (recv_bytes > recv_size)
418 recv_bytes = recv_size;
0206e353 419
4f7f7b7e
CW		 420 for (i = 0; i < recv_bytes; i += 4)
421 unpack_aux(I915_READ(ch_data + i),
422 recv + i, recv_bytes - i);
a4fc5ed6 423
9ee32fea
DV		 424 ret = recv_bytes;
425out:
426 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
427
428 return ret;
a4fc5ed6
KP		 429}
430
431/* Write data to the aux channel in native mode */
432static int
ea5b213a 433intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 434 uint16_t address, uint8_t *send, int send_bytes)
435{
436 int ret;
437 uint8_t msg[20];
438 int msg_bytes;
439 uint8_t ack;
440
9b984dae 441 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 442 if (send_bytes > 16)
443 return -1;
444 msg[0] = AUX_NATIVE_WRITE << 4;
445 msg[1] = address >> 8;
eebc863e 446 msg[2] = address & 0xff;
a4fc5ed6
KP		 447 msg[3] = send_bytes - 1;
448 memcpy(&msg[4], send, send_bytes);
449 msg_bytes = send_bytes + 4;
450 for (;;) {
ea5b213a 451 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 452 if (ret < 0)
453 return ret;
454 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
455 break;
456 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
457 udelay(100);
458 else
a5b3da54 459 return -EIO;
a4fc5ed6
KP		 460 }
461 return send_bytes;
462}
463
464/* Write a single byte to the aux channel in native mode */
465static int
ea5b213a 466intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 467 uint16_t address, uint8_t byte)
468{
ea5b213a 469 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 470}
471
472/* read bytes from a native aux channel */
473static int
ea5b213a 474intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 475 uint16_t address, uint8_t *recv, int recv_bytes)
476{
477 uint8_t msg[4];
478 int msg_bytes;
479 uint8_t reply[20];
480 int reply_bytes;
481 uint8_t ack;
482 int ret;
483
9b984dae 484 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 485 msg[0] = AUX_NATIVE_READ << 4;
486 msg[1] = address >> 8;
487 msg[2] = address & 0xff;
488 msg[3] = recv_bytes - 1;
489
490 msg_bytes = 4;
491 reply_bytes = recv_bytes + 1;
492
493 for (;;) {
ea5b213a 494 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 495 reply, reply_bytes);
a5b3da54
KP		 496 if (ret == 0)
497 return -EPROTO;
498 if (ret < 0)
a4fc5ed6
KP		 499 return ret;
500 ack = reply[0];
501 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
502 memcpy(recv, reply + 1, ret - 1);
503 return ret - 1;
504 }
505 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
506 udelay(100);
507 else
a5b3da54 508 return -EIO;
a4fc5ed6
KP		 509 }
510}
511
512static int
ab2c0672
DA		 513intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
514 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 515{
ab2c0672 516 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 517 struct intel_dp *intel_dp = container_of(adapter,
518 struct intel_dp,
519 adapter);
ab2c0672
DA		 520 uint16_t address = algo_data->address;
521 uint8_t msg[5];
522 uint8_t reply[2];
8316f337 523 unsigned retry;
ab2c0672
DA		 524 int msg_bytes;
525 int reply_bytes;
526 int ret;
527
9b984dae 528 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 529 /* Set up the command byte */
530 if (mode & MODE_I2C_READ)
531 msg[0] = AUX_I2C_READ << 4;
532 else
533 msg[0] = AUX_I2C_WRITE << 4;
534
535 if (!(mode & MODE_I2C_STOP))
536 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 537
ab2c0672
DA		 538 msg[1] = address >> 8;
539 msg[2] = address;
540
541 switch (mode) {
542 case MODE_I2C_WRITE:
543 msg[3] = 0;
544 msg[4] = write_byte;
545 msg_bytes = 5;
546 reply_bytes = 1;
547 break;
548 case MODE_I2C_READ:
549 msg[3] = 0;
550 msg_bytes = 4;
551 reply_bytes = 2;
552 break;
553 default:
554 msg_bytes = 3;
555 reply_bytes = 1;
556 break;
557 }
558
8316f337
DF		 559 for (retry = 0; retry < 5; retry++) {
560 ret = intel_dp_aux_ch(intel_dp,
561 msg, msg_bytes,
562 reply, reply_bytes);
ab2c0672 563 if (ret < 0) {
3ff99164 564 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 565 return ret;
566 }
8316f337
DF		 567
568 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
569 case AUX_NATIVE_REPLY_ACK:
570 /* I2C-over-AUX Reply field is only valid
571 * when paired with AUX ACK.
572 */
573 break;
574 case AUX_NATIVE_REPLY_NACK:
575 DRM_DEBUG_KMS("aux_ch native nack\n");
576 return -EREMOTEIO;
577 case AUX_NATIVE_REPLY_DEFER:
578 udelay(100);
579 continue;
580 default:
581 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
582 reply[0]);
583 return -EREMOTEIO;
584 }
585
ab2c0672
DA		 586 switch (reply[0] & AUX_I2C_REPLY_MASK) {
587 case AUX_I2C_REPLY_ACK:
588 if (mode == MODE_I2C_READ) {
589 *read_byte = reply[1];
590 }
591 return reply_bytes - 1;
592 case AUX_I2C_REPLY_NACK:
8316f337 593 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 594 return -EREMOTEIO;
595 case AUX_I2C_REPLY_DEFER:
8316f337 596 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 597 udelay(100);
598 break;
599 default:
8316f337 600 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 601 return -EREMOTEIO;
602 }
603 }
8316f337
DF		 604
605 DRM_ERROR("too many retries, giving up\n");
606 return -EREMOTEIO;
a4fc5ed6
KP		 607}
608
609static int
ea5b213a 610intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 611 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 612{
0b5c541b
KP		 613 int ret;
614
d54e9d28 615 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 616 intel_dp->algo.running = false;
617 intel_dp->algo.address = 0;
618 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
619
0206e353 620 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 621 intel_dp->adapter.owner = THIS_MODULE;
622 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 623 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 624 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
625 intel_dp->adapter.algo_data = &intel_dp->algo;
626 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
627
0b5c541b
KP		 628 ironlake_edp_panel_vdd_on(intel_dp);
629 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 630 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 631 return ret;
a4fc5ed6
KP		 632}
633
c6bb3538
DV		 634static void
635intel_dp_set_clock(struct intel_encoder *encoder,
636 struct intel_crtc_config *pipe_config, int link_bw)
637{
638 struct drm_device *dev = encoder->base.dev;
639
640 if (IS_G4X(dev)) {
641 if (link_bw == DP_LINK_BW_1_62) {
642 pipe_config->dpll.p1 = 2;
643 pipe_config->dpll.p2 = 10;
644 pipe_config->dpll.n = 2;
645 pipe_config->dpll.m1 = 23;
646 pipe_config->dpll.m2 = 8;
647 } else {
648 pipe_config->dpll.p1 = 1;
649 pipe_config->dpll.p2 = 10;
650 pipe_config->dpll.n = 1;
651 pipe_config->dpll.m1 = 14;
652 pipe_config->dpll.m2 = 2;
653 }
654 pipe_config->clock_set = true;
655 } else if (IS_HASWELL(dev)) {
656 /* Haswell has special-purpose DP DDI clocks. */
657 } else if (HAS_PCH_SPLIT(dev)) {
658 if (link_bw == DP_LINK_BW_1_62) {
659 pipe_config->dpll.n = 1;
660 pipe_config->dpll.p1 = 2;
661 pipe_config->dpll.p2 = 10;
662 pipe_config->dpll.m1 = 12;
663 pipe_config->dpll.m2 = 9;
664 } else {
665 pipe_config->dpll.n = 2;
666 pipe_config->dpll.p1 = 1;
667 pipe_config->dpll.p2 = 10;
668 pipe_config->dpll.m1 = 14;
669 pipe_config->dpll.m2 = 8;
670 }
671 pipe_config->clock_set = true;
672 } else if (IS_VALLEYVIEW(dev)) {
673 /* FIXME: Need to figure out optimized DP clocks for vlv. */
674 }
675}
676
00c09d70 677bool
5bfe2ac0
DV		 678intel_dp_compute_config(struct intel_encoder *encoder,
679 struct intel_crtc_config *pipe_config)
a4fc5ed6 680{
5bfe2ac0 681 struct drm_device *dev = encoder->base.dev;
36008365 682 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 683 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 684 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 685 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 686 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 687 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 688 int lane_count, clock;
397fe157 689 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 690 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 691 int bpp, mode_rate;
a4fc5ed6 692 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 693 int link_avail, link_clock;
a4fc5ed6 694
bc7d38a4 695 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 696 pipe_config->has_pch_encoder = true;
697
03afc4a2 698 pipe_config->has_dp_encoder = true;
a4fc5ed6 699
dd06f90e
JN		 700 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
701 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
702 adjusted_mode);
2dd24552
JB		 703 if (!HAS_PCH_SPLIT(dev))
704 intel_gmch_panel_fitting(intel_crtc, pipe_config,
705 intel_connector->panel.fitting_mode);
706 else
b074cec8
JB		 707 intel_pch_panel_fitting(intel_crtc, pipe_config,
708 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 709 }
710
cb1793ce 711 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 712 return false;
713
083f9560
DV		 714 DRM_DEBUG_KMS("DP link computation with max lane count %i "
715 "max bw %02x pixel clock %iKHz\n",
71244653 716 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 717
36008365
DV		 718 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
719 * bpc in between. */
3e7ca985 720 bpp = pipe_config->pipe_bpp;
7984211e
ID		 721 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
722 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
723 dev_priv->vbt.edp_bpp);
e1b73cba 724 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
7984211e 725 }
657445fe 726
36008365 727 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 728 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 729
730 for (clock = 0; clock <= max_clock; clock++) {
731 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
732 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
733 link_avail = intel_dp_max_data_rate(link_clock,
734 lane_count);
735
736 if (mode_rate <= link_avail) {
737 goto found;
738 }
739 }
740 }
741 }
c4867936 742
36008365 743 return false;
3685a8f3 744
36008365 745found:
55bc60db
VS		 746 if (intel_dp->color_range_auto) {
747 /*
748 * See:
749 * CEA-861-E - 5.1 Default Encoding Parameters
750 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
751 */
18316c8c 752 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 753 intel_dp->color_range = DP_COLOR_RANGE_16_235;
754 else
755 intel_dp->color_range = 0;
756 }
757
3685a8f3 758 if (intel_dp->color_range)
50f3b016 759 pipe_config->limited_color_range = true;
a4fc5ed6 760
36008365
DV		 761 intel_dp->link_bw = bws[clock];
762 intel_dp->lane_count = lane_count;
657445fe 763 pipe_config->pipe_bpp = bpp;
ff9a6750 764 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 765
36008365
DV		 766 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
767 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 768 pipe_config->port_clock, bpp);
36008365
DV		 769 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
770 mode_rate, link_avail);
a4fc5ed6 771
03afc4a2 772 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 773 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 774 &pipe_config->dp_m_n);
9d1a455b 775
c6bb3538
DV		 776 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
777
03afc4a2 778 return true;
a4fc5ed6
KP		 779}
780
247d89f6
PZ		 781void intel_dp_init_link_config(struct intel_dp *intel_dp)
782{
783 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
784 intel_dp->link_configuration[0] = intel_dp->link_bw;
785 intel_dp->link_configuration[1] = intel_dp->lane_count;
786 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
787 /*
788 * Check for DPCD version > 1.1 and enhanced framing support
789 */
790 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
791 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
792 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
793 }
794}
795
7c62a164 796static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 797{
7c62a164
DV		 798 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
799 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
800 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 801 struct drm_i915_private *dev_priv = dev->dev_private;
802 u32 dpa_ctl;
803
ff9a6750 804 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 805 dpa_ctl = I915_READ(DP_A);
806 dpa_ctl &= ~DP_PLL_FREQ_MASK;
807
ff9a6750 808 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 809 /* For a long time we've carried around a ILK-DevA w/a for the
810 * 160MHz clock. If we're really unlucky, it's still required.
811 */
812 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 813 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 814 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 815 } else {
816 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 817 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 818 }
1ce17038 819
ea9b6006
DV		 820 I915_WRITE(DP_A, dpa_ctl);
821
822 POSTING_READ(DP_A);
823 udelay(500);
824}
825
a4fc5ed6
KP		 826static void
827intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
828 struct drm_display_mode *adjusted_mode)
829{
e3421a18 830 struct drm_device *dev = encoder->dev;
417e822d 831 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 832 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
bc7d38a4 833 enum port port = dp_to_dig_port(intel_dp)->port;
7c62a164 834 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
a4fc5ed6 835
417e822d 836 /*
1a2eb460 837 * There are four kinds of DP registers:
417e822d
KP		 838 *
839 * IBX PCH
1a2eb460
KP		 840 * SNB CPU
841 * IVB CPU
417e822d
KP		 842 * CPT PCH
843 *
844 * IBX PCH and CPU are the same for almost everything,
845 * except that the CPU DP PLL is configured in this
846 * register
847 *
848 * CPT PCH is quite different, having many bits moved
849 * to the TRANS_DP_CTL register instead. That
850 * configuration happens (oddly) in ironlake_pch_enable
851 */
9c9e7927 852
417e822d
KP		 853 /* Preserve the BIOS-computed detected bit. This is
854 * supposed to be read-only.
855 */
856 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 857
417e822d 858 /* Handle DP bits in common between all three register formats */
417e822d 859 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 860 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 861
e0dac65e
WF		 862 if (intel_dp->has_audio) {
863 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 864 pipe_name(crtc->pipe));
ea5b213a 865 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 866 intel_write_eld(encoder, adjusted_mode);
867 }
247d89f6
PZ		 868
869 intel_dp_init_link_config(intel_dp);
a4fc5ed6 870
417e822d 871 /* Split out the IBX/CPU vs CPT settings */
32f9d658 872
bc7d38a4 873 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 874 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
875 intel_dp->DP |= DP_SYNC_HS_HIGH;
876 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
877 intel_dp->DP |= DP_SYNC_VS_HIGH;
878 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
879
880 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
881 intel_dp->DP |= DP_ENHANCED_FRAMING;
882
7c62a164 883 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 884 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 885 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 886 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 887
888 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
889 intel_dp->DP |= DP_SYNC_HS_HIGH;
890 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
891 intel_dp->DP |= DP_SYNC_VS_HIGH;
892 intel_dp->DP |= DP_LINK_TRAIN_OFF;
893
894 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
895 intel_dp->DP |= DP_ENHANCED_FRAMING;
896
7c62a164 897 if (crtc->pipe == 1)
417e822d 898 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 899 } else {
900 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 901 }
ea9b6006 902
bc7d38a4 903 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 904 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 905}
906
99ea7127
KP		 907#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
908#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
909
910#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
911#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
912
913#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
914#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
915
916static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
917 u32 mask,
918 u32 value)
bd943159 919{
30add22d 920 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 921 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 922 u32 pp_stat_reg, pp_ctrl_reg;
923
924 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
925 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 926
99ea7127 927 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 928 mask, value,
929 I915_READ(pp_stat_reg),
930 I915_READ(pp_ctrl_reg));
32ce697c 931
453c5420 932 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 933 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 934 I915_READ(pp_stat_reg),
935 I915_READ(pp_ctrl_reg));
32ce697c 936 }
99ea7127 937}
32ce697c 938
99ea7127
KP		 939static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
940{
941 DRM_DEBUG_KMS("Wait for panel power on\n");
942 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 943}
944
99ea7127
KP		 945static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
946{
947 DRM_DEBUG_KMS("Wait for panel power off time\n");
948 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
949}
950
951static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
952{
953 DRM_DEBUG_KMS("Wait for panel power cycle\n");
954 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
955}
956
957
832dd3c1
KP		 958/* Read the current pp_control value, unlocking the register if it
959 * is locked
960 */
961
453c5420 962static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 963{
453c5420
JB		 964 struct drm_device *dev = intel_dp_to_dev(intel_dp);
965 struct drm_i915_private *dev_priv = dev->dev_private;
966 u32 control;
967 u32 pp_ctrl_reg;
968
969 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
970 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 971
972 control &= ~PANEL_UNLOCK_MASK;
973 control |= PANEL_UNLOCK_REGS;
974 return control;
bd943159
KP		 975}
976
82a4d9c0 977void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 978{
30add22d 979 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 980 struct drm_i915_private *dev_priv = dev->dev_private;
981 u32 pp;
453c5420 982 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 983
97af61f5
KP		 984 if (!is_edp(intel_dp))
985 return;
f01eca2e 986 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 987
bd943159
KP		 988 WARN(intel_dp->want_panel_vdd,
989 "eDP VDD already requested on\n");
990
991 intel_dp->want_panel_vdd = true;
99ea7127 992
bd943159
KP		 993 if (ironlake_edp_have_panel_vdd(intel_dp)) {
994 DRM_DEBUG_KMS("eDP VDD already on\n");
995 return;
996 }
997
99ea7127
KP		 998 if (!ironlake_edp_have_panel_power(intel_dp))
999 ironlake_wait_panel_power_cycle(intel_dp);
1000
453c5420 1001 pp = ironlake_get_pp_control(intel_dp);
5d613501 1002 pp |= EDP_FORCE_VDD;
ebf33b18 1003
453c5420
JB		 1004 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1005 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1006
1007 I915_WRITE(pp_ctrl_reg, pp);
1008 POSTING_READ(pp_ctrl_reg);
1009 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1010 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1011 /*
1012 * If the panel wasn't on, delay before accessing aux channel
1013 */
1014 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1015 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1016 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1017 }
5d613501
JB		 1018}
1019
bd943159 1020static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1021{
30add22d 1022 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1023 struct drm_i915_private *dev_priv = dev->dev_private;
1024 u32 pp;
453c5420 1025 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1026
a0e99e68
DV		 1027 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1028
bd943159 1029 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1030 pp = ironlake_get_pp_control(intel_dp);
bd943159 1031 pp &= ~EDP_FORCE_VDD;
bd943159 1032
453c5420
JB		 1033 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1034 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1035
1036 I915_WRITE(pp_ctrl_reg, pp);
1037 POSTING_READ(pp_ctrl_reg);
99ea7127 1038
453c5420
JB		 1039 /* Make sure sequencer is idle before allowing subsequent activity */
1040 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1041 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1042 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1043 }
1044}
5d613501 1045
bd943159
KP		 1046static void ironlake_panel_vdd_work(struct work_struct *__work)
1047{
1048 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1049 struct intel_dp, panel_vdd_work);
30add22d 1050 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1051
627f7675 1052 mutex_lock(&dev->mode_config.mutex);
bd943159 1053 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1054 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1055}
1056
82a4d9c0 1057void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1058{
97af61f5
KP		 1059 if (!is_edp(intel_dp))
1060 return;
5d613501 1061
bd943159
KP		 1062 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1063 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1064
bd943159
KP		 1065 intel_dp->want_panel_vdd = false;
1066
1067 if (sync) {
1068 ironlake_panel_vdd_off_sync(intel_dp);
1069 } else {
1070 /*
1071 * Queue the timer to fire a long
1072 * time from now (relative to the power down delay)
1073 * to keep the panel power up across a sequence of operations
1074 */
1075 schedule_delayed_work(&intel_dp->panel_vdd_work,
1076 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1077 }
5d613501
JB		 1078}
1079
82a4d9c0 1080void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1081{
30add22d 1082 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1083 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1084 u32 pp;
453c5420 1085 u32 pp_ctrl_reg;
9934c132 1086
97af61f5 1087 if (!is_edp(intel_dp))
bd943159 1088 return;
99ea7127
KP		 1089
1090 DRM_DEBUG_KMS("Turn eDP power on\n");
1091
1092 if (ironlake_edp_have_panel_power(intel_dp)) {
1093 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1094 return;
99ea7127 1095 }
9934c132 1096
99ea7127 1097 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1098
453c5420 1099 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1100 if (IS_GEN5(dev)) {
1101 /* ILK workaround: disable reset around power sequence */
1102 pp &= ~PANEL_POWER_RESET;
1103 I915_WRITE(PCH_PP_CONTROL, pp);
1104 POSTING_READ(PCH_PP_CONTROL);
1105 }
37c6c9b0 1106
1c0ae80a 1107 pp |= POWER_TARGET_ON;
99ea7127
KP		 1108 if (!IS_GEN5(dev))
1109 pp |= PANEL_POWER_RESET;
1110
453c5420
JB		 1111 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1112
1113 I915_WRITE(pp_ctrl_reg, pp);
1114 POSTING_READ(pp_ctrl_reg);
9934c132 1115
99ea7127 1116 ironlake_wait_panel_on(intel_dp);
9934c132 1117
05ce1a49
KP		 1118 if (IS_GEN5(dev)) {
1119 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1120 I915_WRITE(PCH_PP_CONTROL, pp);
1121 POSTING_READ(PCH_PP_CONTROL);
1122 }
9934c132
JB		 1123}
1124
82a4d9c0 1125void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1126{
30add22d 1127 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1128 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1129 u32 pp;
453c5420 1130 u32 pp_ctrl_reg;
9934c132 1131
97af61f5
KP		 1132 if (!is_edp(intel_dp))
1133 return;
37c6c9b0 1134
99ea7127 1135 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1136
6cb49835 1137 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1138
453c5420 1139 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1140 /* We need to switch off panel power _and_ force vdd, for otherwise some
1141 * panels get very unhappy and cease to work. */
1142 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1143
1144 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1145
1146 I915_WRITE(pp_ctrl_reg, pp);
1147 POSTING_READ(pp_ctrl_reg);
9934c132 1148
35a38556
DV		 1149 intel_dp->want_panel_vdd = false;
1150
99ea7127 1151 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1152}
1153
d6c50ff8 1154void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1155{
da63a9f2
PZ		 1156 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1157 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1158 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1159 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1160 u32 pp;
453c5420 1161 u32 pp_ctrl_reg;
32f9d658 1162
f01eca2e
KP		 1163 if (!is_edp(intel_dp))
1164 return;
1165
28c97730 1166 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1167 /*
1168 * If we enable the backlight right away following a panel power
1169 * on, we may see slight flicker as the panel syncs with the eDP
1170 * link. So delay a bit to make sure the image is solid before
1171 * allowing it to appear.
1172 */
f01eca2e 1173 msleep(intel_dp->backlight_on_delay);
453c5420 1174 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1175 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1176
1177 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1178
1179 I915_WRITE(pp_ctrl_reg, pp);
1180 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1181
1182 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1183}
1184
d6c50ff8 1185void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1186{
30add22d 1187 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 u32 pp;
453c5420 1190 u32 pp_ctrl_reg;
32f9d658 1191
f01eca2e
KP		 1192 if (!is_edp(intel_dp))
1193 return;
1194
035aa3de
DV		 1195 intel_panel_disable_backlight(dev);
1196
28c97730 1197 DRM_DEBUG_KMS("\n");
453c5420 1198 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1199 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1200
1201 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1202
1203 I915_WRITE(pp_ctrl_reg, pp);
1204 POSTING_READ(pp_ctrl_reg);
f01eca2e 1205 msleep(intel_dp->backlight_off_delay);
32f9d658 1206}
a4fc5ed6 1207
2bd2ad64 1208static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1209{
da63a9f2
PZ		 1210 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1211 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1212 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 u32 dpa_ctl;
1215
2bd2ad64
DV		 1216 assert_pipe_disabled(dev_priv,
1217 to_intel_crtc(crtc)->pipe);
1218
d240f20f
JB		 1219 DRM_DEBUG_KMS("\n");
1220 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1221 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1222 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1223
1224 /* We don't adjust intel_dp->DP while tearing down the link, to
1225 * facilitate link retraining (e.g. after hotplug). Hence clear all
1226 * enable bits here to ensure that we don't enable too much. */
1227 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1228 intel_dp->DP |= DP_PLL_ENABLE;
1229 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1230 POSTING_READ(DP_A);
1231 udelay(200);
d240f20f
JB		 1232}
1233
2bd2ad64 1234static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1235{
da63a9f2
PZ		 1236 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1237 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1238 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1239 struct drm_i915_private *dev_priv = dev->dev_private;
1240 u32 dpa_ctl;
1241
2bd2ad64
DV		 1242 assert_pipe_disabled(dev_priv,
1243 to_intel_crtc(crtc)->pipe);
1244
d240f20f 1245 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1246 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1247 "dp pll off, should be on\n");
1248 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1249
1250 /* We can't rely on the value tracked for the DP register in
1251 * intel_dp->DP because link_down must not change that (otherwise link
1252 * re-training will fail. */
298b0b39 1253 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1254 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1255 POSTING_READ(DP_A);
d240f20f
JB		 1256 udelay(200);
1257}
1258
c7ad3810 1259/* If the sink supports it, try to set the power state appropriately */
c19b0669 1260void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1261{
1262 int ret, i;
1263
1264 /* Should have a valid DPCD by this point */
1265 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1266 return;
1267
1268 if (mode != DRM_MODE_DPMS_ON) {
1269 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1270 DP_SET_POWER_D3);
1271 if (ret != 1)
1272 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1273 } else {
1274 /*
1275 * When turning on, we need to retry for 1ms to give the sink
1276 * time to wake up.
1277 */
1278 for (i = 0; i < 3; i++) {
1279 ret = intel_dp_aux_native_write_1(intel_dp,
1280 DP_SET_POWER,
1281 DP_SET_POWER_D0);
1282 if (ret == 1)
1283 break;
1284 msleep(1);
1285 }
1286 }
1287}
1288
19d8fe15
DV		 1289static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1290 enum pipe *pipe)
d240f20f 1291{
19d8fe15 1292 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1293 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1294 struct drm_device *dev = encoder->base.dev;
1295 struct drm_i915_private *dev_priv = dev->dev_private;
1296 u32 tmp = I915_READ(intel_dp->output_reg);
1297
1298 if (!(tmp & DP_PORT_EN))
1299 return false;
1300
bc7d38a4 1301 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1302 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1303 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1304 *pipe = PORT_TO_PIPE(tmp);
1305 } else {
1306 u32 trans_sel;
1307 u32 trans_dp;
1308 int i;
1309
1310 switch (intel_dp->output_reg) {
1311 case PCH_DP_B:
1312 trans_sel = TRANS_DP_PORT_SEL_B;
1313 break;
1314 case PCH_DP_C:
1315 trans_sel = TRANS_DP_PORT_SEL_C;
1316 break;
1317 case PCH_DP_D:
1318 trans_sel = TRANS_DP_PORT_SEL_D;
1319 break;
1320 default:
1321 return true;
1322 }
1323
1324 for_each_pipe(i) {
1325 trans_dp = I915_READ(TRANS_DP_CTL(i));
1326 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1327 *pipe = i;
1328 return true;
1329 }
1330 }
19d8fe15 1331
4a0833ec
DV		 1332 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1333 intel_dp->output_reg);
1334 }
d240f20f 1335
19d8fe15
DV		 1336 return true;
1337}
d240f20f 1338
045ac3b5
JB		 1339static void intel_dp_get_config(struct intel_encoder *encoder,
1340 struct intel_crtc_config *pipe_config)
1341{
1342 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1343 u32 tmp, flags = 0;
63000ef6
XZ		 1344 struct drm_device *dev = encoder->base.dev;
1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 enum port port = dp_to_dig_port(intel_dp)->port;
1347 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 1348
63000ef6
XZ		 1349 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1350 tmp = I915_READ(intel_dp->output_reg);
1351 if (tmp & DP_SYNC_HS_HIGH)
1352 flags |= DRM_MODE_FLAG_PHSYNC;
1353 else
1354 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1355
63000ef6
XZ		 1356 if (tmp & DP_SYNC_VS_HIGH)
1357 flags |= DRM_MODE_FLAG_PVSYNC;
1358 else
1359 flags |= DRM_MODE_FLAG_NVSYNC;
1360 } else {
1361 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1362 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1363 flags |= DRM_MODE_FLAG_PHSYNC;
1364 else
1365 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1366
63000ef6
XZ		 1367 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1368 flags |= DRM_MODE_FLAG_PVSYNC;
1369 else
1370 flags |= DRM_MODE_FLAG_NVSYNC;
1371 }
045ac3b5
JB		 1372
1373 pipe_config->adjusted_mode.flags |= flags;
f1f644dc
JB		 1374
1375 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1376 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1377 pipe_config->port_clock = 162000;
1378 else
1379 pipe_config->port_clock = 270000;
1380 }
045ac3b5
JB		 1381}
1382
2293bb5c
SK		 1383static bool is_edp_psr(struct intel_dp *intel_dp)
1384{
1385 return is_edp(intel_dp) &&
1386 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1387}
1388
2b28bb1b
RV		 1389static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1390{
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392
1393 if (!IS_HASWELL(dev))
1394 return false;
1395
1396 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1397}
1398
1399static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1400 struct edp_vsc_psr *vsc_psr)
1401{
1402 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1403 struct drm_device *dev = dig_port->base.base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1406 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1407 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1408 uint32_t *data = (uint32_t *) vsc_psr;
1409 unsigned int i;
1410
1411 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1412 the video DIP being updated before program video DIP data buffer
1413 registers for DIP being updated. */
1414 I915_WRITE(ctl_reg, 0);
1415 POSTING_READ(ctl_reg);
1416
1417 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1418 if (i < sizeof(struct edp_vsc_psr))
1419 I915_WRITE(data_reg + i, *data++);
1420 else
1421 I915_WRITE(data_reg + i, 0);
1422 }
1423
1424 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1425 POSTING_READ(ctl_reg);
1426}
1427
1428static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1429{
1430 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 struct edp_vsc_psr psr_vsc;
1433
1434 if (intel_dp->psr_setup_done)
1435 return;
1436
1437 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1438 memset(&psr_vsc, 0, sizeof(psr_vsc));
1439 psr_vsc.sdp_header.HB0 = 0;
1440 psr_vsc.sdp_header.HB1 = 0x7;
1441 psr_vsc.sdp_header.HB2 = 0x2;
1442 psr_vsc.sdp_header.HB3 = 0x8;
1443 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1444
1445 /* Avoid continuous PSR exit by masking memup and hpd */
1446 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1447 EDP_PSR_DEBUG_MASK_HPD);
1448
1449 intel_dp->psr_setup_done = true;
1450}
1451
1452static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1453{
1454 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1455 struct drm_i915_private *dev_priv = dev->dev_private;
1456 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp);
1457 int precharge = 0x3;
1458 int msg_size = 5; /* Header(4) + Message(1) */
1459
1460 /* Enable PSR in sink */
1461 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1462 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1463 DP_PSR_ENABLE &
1464 ~DP_PSR_MAIN_LINK_ACTIVE);
1465 else
1466 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1467 DP_PSR_ENABLE |
1468 DP_PSR_MAIN_LINK_ACTIVE);
1469
1470 /* Setup AUX registers */
1471 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1472 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1473 I915_WRITE(EDP_PSR_AUX_CTL,
1474 DP_AUX_CH_CTL_TIME_OUT_400us |
1475 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1476 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1477 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1478}
1479
1480static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1481{
1482 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 uint32_t max_sleep_time = 0x1f;
1485 uint32_t idle_frames = 1;
1486 uint32_t val = 0x0;
1487
1488 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1489 val |= EDP_PSR_LINK_STANDBY;
1490 val |= EDP_PSR_TP2_TP3_TIME_0us;
1491 val |= EDP_PSR_TP1_TIME_0us;
1492 val |= EDP_PSR_SKIP_AUX_EXIT;
1493 } else
1494 val |= EDP_PSR_LINK_DISABLE;
1495
1496 I915_WRITE(EDP_PSR_CTL, val |
1497 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1498 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1499 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1500 EDP_PSR_ENABLE);
1501}
1502
3f51e471
RV		 1503static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1504{
1505 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1506 struct drm_device *dev = dig_port->base.base.dev;
1507 struct drm_i915_private *dev_priv = dev->dev_private;
1508 struct drm_crtc *crtc = dig_port->base.base.crtc;
1509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1510 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1511 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1512
1513 if (!IS_HASWELL(dev)) {
1514 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1515 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1516 return false;
1517 }
1518
1519 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1520 (dig_port->port != PORT_A)) {
1521 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1522 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1523 return false;
1524 }
1525
1526 if (!is_edp_psr(intel_dp)) {
1527 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1528 dev_priv->no_psr_reason = PSR_NO_SINK;
1529 return false;
1530 }
1531
105b7c11
RV		 1532 if (!i915_enable_psr) {
1533 DRM_DEBUG_KMS("PSR disable by flag\n");
1534 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1535 return false;
1536 }
1537
3f51e471
RV		 1538 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1539 DRM_DEBUG_KMS("crtc not active for PSR\n");
1540 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1541 return false;
1542 }
1543
1544 if (obj->tiling_mode != I915_TILING_X ||
1545 obj->fence_reg == I915_FENCE_REG_NONE) {
1546 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1547 dev_priv->no_psr_reason = PSR_NOT_TILED;
1548 return false;
1549 }
1550
1551 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1552 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1553 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1554 return false;
1555 }
1556
1557 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1558 S3D_ENABLE) {
1559 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1560 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1561 return false;
1562 }
1563
1564 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1565 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1566 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1567 return false;
1568 }
1569
1570 return true;
1571}
1572
3d739d92 1573static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1574{
1575 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1576
3f51e471
RV		 1577 if (!intel_edp_psr_match_conditions(intel_dp) ||
1578 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1579 return;
1580
1581 /* Setup PSR once */
1582 intel_edp_psr_setup(intel_dp);
1583
1584 /* Enable PSR on the panel */
1585 intel_edp_psr_enable_sink(intel_dp);
1586
1587 /* Enable PSR on the host */
1588 intel_edp_psr_enable_source(intel_dp);
1589}
1590
3d739d92
RV		 1591void intel_edp_psr_enable(struct intel_dp *intel_dp)
1592{
1593 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1594
1595 if (intel_edp_psr_match_conditions(intel_dp) &&
1596 !intel_edp_is_psr_enabled(dev))
1597 intel_edp_psr_do_enable(intel_dp);
1598}
1599
2b28bb1b
RV		 1600void intel_edp_psr_disable(struct intel_dp *intel_dp)
1601{
1602 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604
1605 if (!intel_edp_is_psr_enabled(dev))
1606 return;
1607
1608 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1609
1610 /* Wait till PSR is idle */
1611 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1612 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1613 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1614}
1615
3d739d92
RV		 1616void intel_edp_psr_update(struct drm_device *dev)
1617{
1618 struct intel_encoder *encoder;
1619 struct intel_dp *intel_dp = NULL;
1620
1621 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1622 if (encoder->type == INTEL_OUTPUT_EDP) {
1623 intel_dp = enc_to_intel_dp(&encoder->base);
1624
1625 if (!is_edp_psr(intel_dp))
1626 return;
1627
1628 if (!intel_edp_psr_match_conditions(intel_dp))
1629 intel_edp_psr_disable(intel_dp);
1630 else
1631 if (!intel_edp_is_psr_enabled(dev))
1632 intel_edp_psr_do_enable(intel_dp);
1633 }
1634}
1635
e8cb4558 1636static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1637{
e8cb4558 1638 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1639 enum port port = dp_to_dig_port(intel_dp)->port;
1640 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1641
1642 /* Make sure the panel is off before trying to change the mode. But also
1643 * ensure that we have vdd while we switch off the panel. */
1644 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1645 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1646 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1647 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1648
1649 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1650 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1651 intel_dp_link_down(intel_dp);
d240f20f
JB		 1652}
1653
2bd2ad64 1654static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1655{
2bd2ad64 1656 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1657 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1658 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1659
982a3866 1660 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1661 intel_dp_link_down(intel_dp);
b2634017
JB		 1662 if (!IS_VALLEYVIEW(dev))
1663 ironlake_edp_pll_off(intel_dp);
3739850b 1664 }
2bd2ad64
DV		 1665}
1666
e8cb4558 1667static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1668{
e8cb4558
DV		 1669 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1670 struct drm_device *dev = encoder->base.dev;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1673
0c33d8d7
DV		 1674 if (WARN_ON(dp_reg & DP_PORT_EN))
1675 return;
5d613501 1676
97af61f5 1677 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1678 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1679 intel_dp_start_link_train(intel_dp);
97af61f5 1680 ironlake_edp_panel_on(intel_dp);
bd943159 1681 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1682 intel_dp_complete_link_train(intel_dp);
3ab9c637 1683 intel_dp_stop_link_train(intel_dp);
f01eca2e 1684 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB		 1685
1686 if (IS_VALLEYVIEW(dev)) {
1687 struct intel_digital_port *dport =
1688 enc_to_dig_port(&encoder->base);
1689 int channel = vlv_dport_to_channel(dport);
1690
1691 vlv_wait_port_ready(dev_priv, channel);
1692 }
d240f20f
JB		 1693}
1694
2bd2ad64 1695static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1696{
2bd2ad64 1697 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1698 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1699 struct drm_device *dev = encoder->base.dev;
89b667f8 1700 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1701
bc7d38a4 1702 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
2bd2ad64 1703 ironlake_edp_pll_on(intel_dp);
89b667f8
JB		 1704
1705 if (IS_VALLEYVIEW(dev)) {
89b667f8
JB		 1706 struct intel_crtc *intel_crtc =
1707 to_intel_crtc(encoder->base.crtc);
1708 int port = vlv_dport_to_channel(dport);
1709 int pipe = intel_crtc->pipe;
1710 u32 val;
1711
ae99258f 1712 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
89b667f8
JB		 1713 val = 0;
1714 if (pipe)
1715 val |= (1<<21);
1716 else
1717 val &= ~(1<<21);
1718 val |= 0x001000c4;
ae99258f 1719 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
89b667f8 1720
ae99258f 1721 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
89b667f8 1722 0x00760018);
ae99258f 1723 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
89b667f8
JB		 1724 0x00400888);
1725 }
1726}
1727
1728static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1729{
1730 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1731 struct drm_device *dev = encoder->base.dev;
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 int port = vlv_dport_to_channel(dport);
1734
1735 if (!IS_VALLEYVIEW(dev))
1736 return;
1737
89b667f8 1738 /* Program Tx lane resets to default */
ae99258f 1739 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
89b667f8
JB		 1740 DPIO_PCS_TX_LANE2_RESET |
1741 DPIO_PCS_TX_LANE1_RESET);
ae99258f 1742 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
89b667f8
JB		 1743 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1744 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1745 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1746 DPIO_PCS_CLK_SOFT_RESET);
1747
1748 /* Fix up inter-pair skew failure */
ae99258f
JN		 1749 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1750 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1751 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP		 1752}
1753
1754/*
df0c237d
JB		 1755 * Native read with retry for link status and receiver capability reads for
1756 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1757 */
1758static bool
df0c237d
JB		 1759intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1760 uint8_t *recv, int recv_bytes)
a4fc5ed6 1761{
61da5fab
JB		 1762 int ret, i;
1763
df0c237d
JB		 1764 /*
1765 * Sinks are *supposed* to come up within 1ms from an off state,
1766 * but we're also supposed to retry 3 times per the spec.
1767 */
61da5fab 1768 for (i = 0; i < 3; i++) {
df0c237d
JB		 1769 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1770 recv_bytes);
1771 if (ret == recv_bytes)
61da5fab
JB		 1772 return true;
1773 msleep(1);
1774 }
a4fc5ed6 1775
61da5fab 1776 return false;
a4fc5ed6
KP		 1777}
1778
1779/*
1780 * Fetch AUX CH registers 0x202 - 0x207 which contain
1781 * link status information
1782 */
1783static bool
93f62dad 1784intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1785{
df0c237d
JB		 1786 return intel_dp_aux_native_read_retry(intel_dp,
1787 DP_LANE0_1_STATUS,
93f62dad 1788 link_status,
df0c237d 1789 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1790}
1791
a4fc5ed6
KP		 1792#if 0
1793static char *voltage_names[] = {
1794 "0.4V", "0.6V", "0.8V", "1.2V"
1795};
1796static char *pre_emph_names[] = {
1797 "0dB", "3.5dB", "6dB", "9.5dB"
1798};
1799static char *link_train_names[] = {
1800 "pattern 1", "pattern 2", "idle", "off"
1801};
1802#endif
1803
1804/*
1805 * These are source-specific values; current Intel hardware supports
1806 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1807 */
a4fc5ed6
KP		 1808
1809static uint8_t
1a2eb460 1810intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1811{
30add22d 1812 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1813 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1814
e2fa6fba
P		 1815 if (IS_VALLEYVIEW(dev))
1816 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1817 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1818 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1819 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1820 return DP_TRAIN_VOLTAGE_SWING_1200;
1821 else
1822 return DP_TRAIN_VOLTAGE_SWING_800;
1823}
1824
1825static uint8_t
1826intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1827{
30add22d 1828 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1829 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1830
22b8bf17 1831 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1832 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1833 case DP_TRAIN_VOLTAGE_SWING_400:
1834 return DP_TRAIN_PRE_EMPHASIS_9_5;
1835 case DP_TRAIN_VOLTAGE_SWING_600:
1836 return DP_TRAIN_PRE_EMPHASIS_6;
1837 case DP_TRAIN_VOLTAGE_SWING_800:
1838 return DP_TRAIN_PRE_EMPHASIS_3_5;
1839 case DP_TRAIN_VOLTAGE_SWING_1200:
1840 default:
1841 return DP_TRAIN_PRE_EMPHASIS_0;
1842 }
e2fa6fba
P		 1843 } else if (IS_VALLEYVIEW(dev)) {
1844 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1845 case DP_TRAIN_VOLTAGE_SWING_400:
1846 return DP_TRAIN_PRE_EMPHASIS_9_5;
1847 case DP_TRAIN_VOLTAGE_SWING_600:
1848 return DP_TRAIN_PRE_EMPHASIS_6;
1849 case DP_TRAIN_VOLTAGE_SWING_800:
1850 return DP_TRAIN_PRE_EMPHASIS_3_5;
1851 case DP_TRAIN_VOLTAGE_SWING_1200:
1852 default:
1853 return DP_TRAIN_PRE_EMPHASIS_0;
1854 }
bc7d38a4 1855 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1856 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1857 case DP_TRAIN_VOLTAGE_SWING_400:
1858 return DP_TRAIN_PRE_EMPHASIS_6;
1859 case DP_TRAIN_VOLTAGE_SWING_600:
1860 case DP_TRAIN_VOLTAGE_SWING_800:
1861 return DP_TRAIN_PRE_EMPHASIS_3_5;
1862 default:
1863 return DP_TRAIN_PRE_EMPHASIS_0;
1864 }
1865 } else {
1866 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1867 case DP_TRAIN_VOLTAGE_SWING_400:
1868 return DP_TRAIN_PRE_EMPHASIS_6;
1869 case DP_TRAIN_VOLTAGE_SWING_600:
1870 return DP_TRAIN_PRE_EMPHASIS_6;
1871 case DP_TRAIN_VOLTAGE_SWING_800:
1872 return DP_TRAIN_PRE_EMPHASIS_3_5;
1873 case DP_TRAIN_VOLTAGE_SWING_1200:
1874 default:
1875 return DP_TRAIN_PRE_EMPHASIS_0;
1876 }
a4fc5ed6
KP		 1877 }
1878}
1879
e2fa6fba
P		 1880static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1881{
1882 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1885 unsigned long demph_reg_value, preemph_reg_value,
1886 uniqtranscale_reg_value;
1887 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1888 int port = vlv_dport_to_channel(dport);
e2fa6fba
P		 1889
1890 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1891 case DP_TRAIN_PRE_EMPHASIS_0:
1892 preemph_reg_value = 0x0004000;
1893 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1894 case DP_TRAIN_VOLTAGE_SWING_400:
1895 demph_reg_value = 0x2B405555;
1896 uniqtranscale_reg_value = 0x552AB83A;
1897 break;
1898 case DP_TRAIN_VOLTAGE_SWING_600:
1899 demph_reg_value = 0x2B404040;
1900 uniqtranscale_reg_value = 0x5548B83A;
1901 break;
1902 case DP_TRAIN_VOLTAGE_SWING_800:
1903 demph_reg_value = 0x2B245555;
1904 uniqtranscale_reg_value = 0x5560B83A;
1905 break;
1906 case DP_TRAIN_VOLTAGE_SWING_1200:
1907 demph_reg_value = 0x2B405555;
1908 uniqtranscale_reg_value = 0x5598DA3A;
1909 break;
1910 default:
1911 return 0;
1912 }
1913 break;
1914 case DP_TRAIN_PRE_EMPHASIS_3_5:
1915 preemph_reg_value = 0x0002000;
1916 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1917 case DP_TRAIN_VOLTAGE_SWING_400:
1918 demph_reg_value = 0x2B404040;
1919 uniqtranscale_reg_value = 0x5552B83A;
1920 break;
1921 case DP_TRAIN_VOLTAGE_SWING_600:
1922 demph_reg_value = 0x2B404848;
1923 uniqtranscale_reg_value = 0x5580B83A;
1924 break;
1925 case DP_TRAIN_VOLTAGE_SWING_800:
1926 demph_reg_value = 0x2B404040;
1927 uniqtranscale_reg_value = 0x55ADDA3A;
1928 break;
1929 default:
1930 return 0;
1931 }
1932 break;
1933 case DP_TRAIN_PRE_EMPHASIS_6:
1934 preemph_reg_value = 0x0000000;
1935 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1936 case DP_TRAIN_VOLTAGE_SWING_400:
1937 demph_reg_value = 0x2B305555;
1938 uniqtranscale_reg_value = 0x5570B83A;
1939 break;
1940 case DP_TRAIN_VOLTAGE_SWING_600:
1941 demph_reg_value = 0x2B2B4040;
1942 uniqtranscale_reg_value = 0x55ADDA3A;
1943 break;
1944 default:
1945 return 0;
1946 }
1947 break;
1948 case DP_TRAIN_PRE_EMPHASIS_9_5:
1949 preemph_reg_value = 0x0006000;
1950 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1951 case DP_TRAIN_VOLTAGE_SWING_400:
1952 demph_reg_value = 0x1B405555;
1953 uniqtranscale_reg_value = 0x55ADDA3A;
1954 break;
1955 default:
1956 return 0;
1957 }
1958 break;
1959 default:
1960 return 0;
1961 }
1962
ae99258f
JN		 1963 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1964 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1965 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
e2fa6fba 1966 uniqtranscale_reg_value);
ae99258f
JN		 1967 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1968 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1969 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1970 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P		 1971
1972 return 0;
1973}
1974
a4fc5ed6 1975static void
93f62dad 1976intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1977{
1978 uint8_t v = 0;
1979 uint8_t p = 0;
1980 int lane;
1a2eb460
KP		 1981 uint8_t voltage_max;
1982 uint8_t preemph_max;
a4fc5ed6 1983
33a34e4e 1984 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1985 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1986 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1987
1988 if (this_v > v)
1989 v = this_v;
1990 if (this_p > p)
1991 p = this_p;
1992 }
1993
1a2eb460 1994 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1995 if (v >= voltage_max)
1996 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1997
1a2eb460
KP		 1998 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1999 if (p >= preemph_max)
2000 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2001
2002 for (lane = 0; lane < 4; lane++)
33a34e4e 2003 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2004}
2005
2006static uint32_t
f0a3424e 2007intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2008{
3cf2efb1 2009 uint32_t signal_levels = 0;
a4fc5ed6 2010
3cf2efb1 2011 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2012 case DP_TRAIN_VOLTAGE_SWING_400:
2013 default:
2014 signal_levels |= DP_VOLTAGE_0_4;
2015 break;
2016 case DP_TRAIN_VOLTAGE_SWING_600:
2017 signal_levels |= DP_VOLTAGE_0_6;
2018 break;
2019 case DP_TRAIN_VOLTAGE_SWING_800:
2020 signal_levels |= DP_VOLTAGE_0_8;
2021 break;
2022 case DP_TRAIN_VOLTAGE_SWING_1200:
2023 signal_levels |= DP_VOLTAGE_1_2;
2024 break;
2025 }
3cf2efb1 2026 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2027 case DP_TRAIN_PRE_EMPHASIS_0:
2028 default:
2029 signal_levels |= DP_PRE_EMPHASIS_0;
2030 break;
2031 case DP_TRAIN_PRE_EMPHASIS_3_5:
2032 signal_levels |= DP_PRE_EMPHASIS_3_5;
2033 break;
2034 case DP_TRAIN_PRE_EMPHASIS_6:
2035 signal_levels |= DP_PRE_EMPHASIS_6;
2036 break;
2037 case DP_TRAIN_PRE_EMPHASIS_9_5:
2038 signal_levels |= DP_PRE_EMPHASIS_9_5;
2039 break;
2040 }
2041 return signal_levels;
2042}
2043
e3421a18
ZW		 2044/* Gen6's DP voltage swing and pre-emphasis control */
2045static uint32_t
2046intel_gen6_edp_signal_levels(uint8_t train_set)
2047{
3c5a62b5
YL		 2048 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2049 DP_TRAIN_PRE_EMPHASIS_MASK);
2050 switch (signal_levels) {
e3421a18 2051 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2052 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2053 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2054 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2055 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2056 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2057 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2058 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2059 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2060 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2061 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2062 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2063 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2064 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2065 default:
3c5a62b5
YL		 2066 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2067 "0x%x\n", signal_levels);
2068 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2069 }
2070}
2071
1a2eb460
KP		 2072/* Gen7's DP voltage swing and pre-emphasis control */
2073static uint32_t
2074intel_gen7_edp_signal_levels(uint8_t train_set)
2075{
2076 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2077 DP_TRAIN_PRE_EMPHASIS_MASK);
2078 switch (signal_levels) {
2079 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2080 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2081 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2082 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2083 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2084 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2085
2086 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2087 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2088 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2089 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2090
2091 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2092 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2093 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2094 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2095
2096 default:
2097 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2098 "0x%x\n", signal_levels);
2099 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2100 }
2101}
2102
d6c0d722
PZ		 2103/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2104static uint32_t
f0a3424e 2105intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2106{
d6c0d722
PZ		 2107 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2108 DP_TRAIN_PRE_EMPHASIS_MASK);
2109 switch (signal_levels) {
2110 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2111 return DDI_BUF_EMP_400MV_0DB_HSW;
2112 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2113 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2114 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2115 return DDI_BUF_EMP_400MV_6DB_HSW;
2116 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2117 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2118
d6c0d722
PZ		 2119 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2120 return DDI_BUF_EMP_600MV_0DB_HSW;
2121 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2122 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2123 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2124 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2125
d6c0d722
PZ		 2126 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2127 return DDI_BUF_EMP_800MV_0DB_HSW;
2128 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2129 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2130 default:
2131 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2132 "0x%x\n", signal_levels);
2133 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2134 }
a4fc5ed6
KP		 2135}
2136
f0a3424e
PZ		 2137/* Properly updates "DP" with the correct signal levels. */
2138static void
2139intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2140{
2141 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2142 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2143 struct drm_device *dev = intel_dig_port->base.base.dev;
2144 uint32_t signal_levels, mask;
2145 uint8_t train_set = intel_dp->train_set[0];
2146
22b8bf17 2147 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2148 signal_levels = intel_hsw_signal_levels(train_set);
2149 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2150 } else if (IS_VALLEYVIEW(dev)) {
2151 signal_levels = intel_vlv_signal_levels(intel_dp);
2152 mask = 0;
bc7d38a4 2153 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2154 signal_levels = intel_gen7_edp_signal_levels(train_set);
2155 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2156 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2157 signal_levels = intel_gen6_edp_signal_levels(train_set);
2158 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2159 } else {
2160 signal_levels = intel_gen4_signal_levels(train_set);
2161 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2162 }
2163
2164 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2165
2166 *DP = (*DP & ~mask) | signal_levels;
2167}
2168
a4fc5ed6 2169static bool
ea5b213a 2170intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 2171 uint32_t dp_reg_value,
58e10eb9 2172 uint8_t dp_train_pat)
a4fc5ed6 2173{
174edf1f
PZ		 2174 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2175 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2176 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2177 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 2178 int ret;
2179
22b8bf17 2180 if (HAS_DDI(dev)) {
3ab9c637 2181 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2182
2183 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2184 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2185 else
2186 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2187
2188 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2189 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2190 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2191 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2192
2193 break;
2194 case DP_TRAINING_PATTERN_1:
2195 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2196 break;
2197 case DP_TRAINING_PATTERN_2:
2198 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2199 break;
2200 case DP_TRAINING_PATTERN_3:
2201 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2202 break;
2203 }
174edf1f 2204 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2205
bc7d38a4 2206 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 2207 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2208
2209 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2210 case DP_TRAINING_PATTERN_DISABLE:
2211 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2212 break;
2213 case DP_TRAINING_PATTERN_1:
2214 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2215 break;
2216 case DP_TRAINING_PATTERN_2:
2217 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2218 break;
2219 case DP_TRAINING_PATTERN_3:
2220 DRM_ERROR("DP training pattern 3 not supported\n");
2221 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2222 break;
2223 }
2224
2225 } else {
2226 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2227
2228 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2229 case DP_TRAINING_PATTERN_DISABLE:
2230 dp_reg_value |= DP_LINK_TRAIN_OFF;
2231 break;
2232 case DP_TRAINING_PATTERN_1:
2233 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2234 break;
2235 case DP_TRAINING_PATTERN_2:
2236 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2237 break;
2238 case DP_TRAINING_PATTERN_3:
2239 DRM_ERROR("DP training pattern 3 not supported\n");
2240 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2241 break;
2242 }
2243 }
2244
ea5b213a
CW		 2245 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2246 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2247
ea5b213a 2248 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2249 DP_TRAINING_PATTERN_SET,
2250 dp_train_pat);
2251
47ea7542
PZ		 2252 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2253 DP_TRAINING_PATTERN_DISABLE) {
2254 ret = intel_dp_aux_native_write(intel_dp,
2255 DP_TRAINING_LANE0_SET,
2256 intel_dp->train_set,
2257 intel_dp->lane_count);
2258 if (ret != intel_dp->lane_count)
2259 return false;
2260 }
a4fc5ed6
KP		 2261
2262 return true;
2263}
2264
3ab9c637
ID		 2265static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2266{
2267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2268 struct drm_device *dev = intel_dig_port->base.base.dev;
2269 struct drm_i915_private *dev_priv = dev->dev_private;
2270 enum port port = intel_dig_port->port;
2271 uint32_t val;
2272
2273 if (!HAS_DDI(dev))
2274 return;
2275
2276 val = I915_READ(DP_TP_CTL(port));
2277 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2278 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2279 I915_WRITE(DP_TP_CTL(port), val);
2280
2281 /*
2282 * On PORT_A we can have only eDP in SST mode. There the only reason
2283 * we need to set idle transmission mode is to work around a HW issue
2284 * where we enable the pipe while not in idle link-training mode.
2285 * In this case there is requirement to wait for a minimum number of
2286 * idle patterns to be sent.
2287 */
2288 if (port == PORT_A)
2289 return;
2290
2291 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2292 1))
2293 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2294}
2295
33a34e4e 2296/* Enable corresponding port and start training pattern 1 */
c19b0669 2297void
33a34e4e 2298intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2299{
da63a9f2 2300 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2301 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2302 int i;
2303 uint8_t voltage;
2304 bool clock_recovery = false;
cdb0e95b 2305 int voltage_tries, loop_tries;
ea5b213a 2306 uint32_t DP = intel_dp->DP;
a4fc5ed6 2307
affa9354 2308 if (HAS_DDI(dev))
c19b0669
PZ		 2309 intel_ddi_prepare_link_retrain(encoder);
2310
3cf2efb1
CW		 2311 /* Write the link configuration data */
2312 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2313 intel_dp->link_configuration,
2314 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2315
2316 DP |= DP_PORT_EN;
1a2eb460 2317
33a34e4e 2318 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2319 voltage = 0xff;
cdb0e95b
KP		 2320 voltage_tries = 0;
2321 loop_tries = 0;
a4fc5ed6
KP		 2322 clock_recovery = false;
2323 for (;;) {
33a34e4e 2324 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2325 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2326
2327 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2328
a7c9655f 2329 /* Set training pattern 1 */
47ea7542 2330 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2331 DP_TRAINING_PATTERN_1 |
2332 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2333 break;
a4fc5ed6 2334
a7c9655f 2335 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2336 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2337 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2338 break;
93f62dad 2339 }
a4fc5ed6 2340
01916270 2341 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2342 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2343 clock_recovery = true;
2344 break;
2345 }
2346
2347 /* Check to see if we've tried the max voltage */
2348 for (i = 0; i < intel_dp->lane_count; i++)
2349 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2350 break;
3b4f819d 2351 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2352 ++loop_tries;
2353 if (loop_tries == 5) {
cdb0e95b
KP		 2354 DRM_DEBUG_KMS("too many full retries, give up\n");
2355 break;
2356 }
2357 memset(intel_dp->train_set, 0, 4);
2358 voltage_tries = 0;
2359 continue;
2360 }
a4fc5ed6 2361
3cf2efb1 2362 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2363 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2364 ++voltage_tries;
b06fbda3
DV		 2365 if (voltage_tries == 5) {
2366 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2367 break;
2368 }
2369 } else
2370 voltage_tries = 0;
2371 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2372
3cf2efb1 2373 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2374 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2375 }
2376
33a34e4e
JB		 2377 intel_dp->DP = DP;
2378}
2379
c19b0669 2380void
33a34e4e
JB		 2381intel_dp_complete_link_train(struct intel_dp *intel_dp)
2382{
33a34e4e 2383 bool channel_eq = false;
37f80975 2384 int tries, cr_tries;
33a34e4e
JB		 2385 uint32_t DP = intel_dp->DP;
2386
a4fc5ed6
KP		 2387 /* channel equalization */
2388 tries = 0;
37f80975 2389 cr_tries = 0;
a4fc5ed6
KP		 2390 channel_eq = false;
2391 for (;;) {
93f62dad 2392 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2393
37f80975
JB		 2394 if (cr_tries > 5) {
2395 DRM_ERROR("failed to train DP, aborting\n");
2396 intel_dp_link_down(intel_dp);
2397 break;
2398 }
2399
f0a3424e 2400 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2401
a4fc5ed6 2402 /* channel eq pattern */
47ea7542 2403 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2404 DP_TRAINING_PATTERN_2 |
2405 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2406 break;
2407
a7c9655f 2408 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2409 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2410 break;
a4fc5ed6 2411
37f80975 2412 /* Make sure clock is still ok */
01916270 2413 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2414 intel_dp_start_link_train(intel_dp);
2415 cr_tries++;
2416 continue;
2417 }
2418
1ffdff13 2419 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2420 channel_eq = true;
2421 break;
2422 }
a4fc5ed6 2423
37f80975
JB		 2424 /* Try 5 times, then try clock recovery if that fails */
2425 if (tries > 5) {
2426 intel_dp_link_down(intel_dp);
2427 intel_dp_start_link_train(intel_dp);
2428 tries = 0;
2429 cr_tries++;
2430 continue;
2431 }
a4fc5ed6 2432
3cf2efb1 2433 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2434 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2435 ++tries;
869184a6 2436 }
3cf2efb1 2437
3ab9c637
ID		 2438 intel_dp_set_idle_link_train(intel_dp);
2439
2440 intel_dp->DP = DP;
2441
d6c0d722 2442 if (channel_eq)
07f42258 2443 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2444
3ab9c637
ID		 2445}
2446
2447void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2448{
2449 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2450 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2451}
2452
2453static void
ea5b213a 2454intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2455{
da63a9f2 2456 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2457 enum port port = intel_dig_port->port;
da63a9f2 2458 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2459 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2460 struct intel_crtc *intel_crtc =
2461 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2462 uint32_t DP = intel_dp->DP;
a4fc5ed6 2463
c19b0669
PZ		 2464 /*
2465 * DDI code has a strict mode set sequence and we should try to respect
2466 * it, otherwise we might hang the machine in many different ways. So we
2467 * really should be disabling the port only on a complete crtc_disable
2468 * sequence. This function is just called under two conditions on DDI
2469 * code:
2470 * - Link train failed while doing crtc_enable, and on this case we
2471 * really should respect the mode set sequence and wait for a
2472 * crtc_disable.
2473 * - Someone turned the monitor off and intel_dp_check_link_status
2474 * called us. We don't need to disable the whole port on this case, so
2475 * when someone turns the monitor on again,
2476 * intel_ddi_prepare_link_retrain will take care of redoing the link
2477 * train.
2478 */
affa9354 2479 if (HAS_DDI(dev))
c19b0669
PZ		 2480 return;
2481
0c33d8d7 2482 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2483 return;
2484
28c97730 2485 DRM_DEBUG_KMS("\n");
32f9d658 2486
bc7d38a4 2487 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2488 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2489 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2490 } else {
2491 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2492 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2493 }
fe255d00 2494 POSTING_READ(intel_dp->output_reg);
5eb08b69 2495
ab527efc
DV		 2496 /* We don't really know why we're doing this */
2497 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2498
493a7081 2499 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2500 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2501 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2502
5bddd17f
EA		 2503 /* Hardware workaround: leaving our transcoder select
2504 * set to transcoder B while it's off will prevent the
2505 * corresponding HDMI output on transcoder A.
2506 *
2507 * Combine this with another hardware workaround:
2508 * transcoder select bit can only be cleared while the
2509 * port is enabled.
2510 */
2511 DP &= ~DP_PIPEB_SELECT;
2512 I915_WRITE(intel_dp->output_reg, DP);
2513
2514 /* Changes to enable or select take place the vblank
2515 * after being written.
2516 */
ff50afe9
DV		 2517 if (WARN_ON(crtc == NULL)) {
2518 /* We should never try to disable a port without a crtc
2519 * attached. For paranoia keep the code around for a
2520 * bit. */
31acbcc4
CW		 2521 POSTING_READ(intel_dp->output_reg);
2522 msleep(50);
2523 } else
ab527efc 2524 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2525 }
2526
832afda6 2527 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2528 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2529 POSTING_READ(intel_dp->output_reg);
f01eca2e 2530 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2531}
2532
26d61aad
KP		 2533static bool
2534intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2535{
577c7a50
DL		 2536 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2537
92fd8fd1 2538 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2539 sizeof(intel_dp->dpcd)) == 0)
2540 return false; /* aux transfer failed */
92fd8fd1 2541
577c7a50
DL		 2542 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2543 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2544 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2545
edb39244
AJ		 2546 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2547 return false; /* DPCD not present */
2548
2293bb5c
SK		 2549 /* Check if the panel supports PSR */
2550 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2551 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2552 intel_dp->psr_dpcd,
2553 sizeof(intel_dp->psr_dpcd));
2554 if (is_edp_psr(intel_dp))
2555 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
edb39244
AJ		 2556 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2557 DP_DWN_STRM_PORT_PRESENT))
2558 return true; /* native DP sink */
2559
2560 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2561 return true; /* no per-port downstream info */
2562
2563 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2564 intel_dp->downstream_ports,
2565 DP_MAX_DOWNSTREAM_PORTS) == 0)
2566 return false; /* downstream port status fetch failed */
2567
2568 return true;
92fd8fd1
KP		 2569}
2570
0d198328
AJ		 2571static void
2572intel_dp_probe_oui(struct intel_dp *intel_dp)
2573{
2574 u8 buf[3];
2575
2576 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2577 return;
2578
351cfc34
DV		 2579 ironlake_edp_panel_vdd_on(intel_dp);
2580
0d198328
AJ		 2581 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2582 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2583 buf[0], buf[1], buf[2]);
2584
2585 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2586 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2587 buf[0], buf[1], buf[2]);
351cfc34
DV		 2588
2589 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2590}
2591
a60f0e38
JB		 2592static bool
2593intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2594{
2595 int ret;
2596
2597 ret = intel_dp_aux_native_read_retry(intel_dp,
2598 DP_DEVICE_SERVICE_IRQ_VECTOR,
2599 sink_irq_vector, 1);
2600 if (!ret)
2601 return false;
2602
2603 return true;
2604}
2605
2606static void
2607intel_dp_handle_test_request(struct intel_dp *intel_dp)
2608{
2609 /* NAK by default */
9324cf7f 2610 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2611}
2612
a4fc5ed6
KP		 2613/*
2614 * According to DP spec
2615 * 5.1.2:
2616 * 1. Read DPCD
2617 * 2. Configure link according to Receiver Capabilities
2618 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2619 * 4. Check link status on receipt of hot-plug interrupt
2620 */
2621
00c09d70 2622void
ea5b213a 2623intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2624{
da63a9f2 2625 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2626 u8 sink_irq_vector;
93f62dad 2627 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2628
da63a9f2 2629 if (!intel_encoder->connectors_active)
d2b996ac 2630 return;
59cd09e1 2631
da63a9f2 2632 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2633 return;
2634
92fd8fd1 2635 /* Try to read receiver status if the link appears to be up */
93f62dad 2636 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2637 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2638 return;
2639 }
2640
92fd8fd1 2641 /* Now read the DPCD to see if it's actually running */
26d61aad 2642 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2643 intel_dp_link_down(intel_dp);
2644 return;
2645 }
2646
a60f0e38
JB		 2647 /* Try to read the source of the interrupt */
2648 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2649 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2650 /* Clear interrupt source */
2651 intel_dp_aux_native_write_1(intel_dp,
2652 DP_DEVICE_SERVICE_IRQ_VECTOR,
2653 sink_irq_vector);
2654
2655 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2656 intel_dp_handle_test_request(intel_dp);
2657 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2658 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2659 }
2660
1ffdff13 2661 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2662 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2663 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2664 intel_dp_start_link_train(intel_dp);
2665 intel_dp_complete_link_train(intel_dp);
3ab9c637 2666 intel_dp_stop_link_train(intel_dp);
33a34e4e 2667 }
a4fc5ed6 2668}
a4fc5ed6 2669
caf9ab24 2670/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2671static enum drm_connector_status
26d61aad 2672intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2673{
caf9ab24
AJ		 2674 uint8_t *dpcd = intel_dp->dpcd;
2675 bool hpd;
2676 uint8_t type;
2677
2678 if (!intel_dp_get_dpcd(intel_dp))
2679 return connector_status_disconnected;
2680
2681 /* if there's no downstream port, we're done */
2682 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2683 return connector_status_connected;
caf9ab24
AJ		 2684
2685 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2686 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2687 if (hpd) {
23235177 2688 uint8_t reg;
caf9ab24 2689 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2690 &reg, 1))
caf9ab24 2691 return connector_status_unknown;
23235177
AJ		 2692 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2693 : connector_status_disconnected;
caf9ab24
AJ		 2694 }
2695
2696 /* If no HPD, poke DDC gently */
2697 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2698 return connector_status_connected;
caf9ab24
AJ		 2699
2700 /* Well we tried, say unknown for unreliable port types */
2701 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2702 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2703 return connector_status_unknown;
2704
2705 /* Anything else is out of spec, warn and ignore */
2706 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2707 return connector_status_disconnected;
71ba9000
AJ		 2708}
2709
5eb08b69 2710static enum drm_connector_status
a9756bb5 2711ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2712{
30add22d 2713 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2716 enum drm_connector_status status;
2717
fe16d949
CW		 2718 /* Can't disconnect eDP, but you can close the lid... */
2719 if (is_edp(intel_dp)) {
30add22d 2720 status = intel_panel_detect(dev);
fe16d949
CW		 2721 if (status == connector_status_unknown)
2722 status = connector_status_connected;
2723 return status;
2724 }
01cb9ea6 2725
1b469639
DL		 2726 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2727 return connector_status_disconnected;
2728
26d61aad 2729 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2730}
2731
a4fc5ed6 2732static enum drm_connector_status
a9756bb5 2733g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2734{
30add22d 2735 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2736 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2737 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2738 uint32_t bit;
5eb08b69 2739
35aad75f
JB		 2740 /* Can't disconnect eDP, but you can close the lid... */
2741 if (is_edp(intel_dp)) {
2742 enum drm_connector_status status;
2743
2744 status = intel_panel_detect(dev);
2745 if (status == connector_status_unknown)
2746 status = connector_status_connected;
2747 return status;
2748 }
2749
34f2be46
VS		 2750 switch (intel_dig_port->port) {
2751 case PORT_B:
26739f12 2752 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2753 break;
34f2be46 2754 case PORT_C:
26739f12 2755 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2756 break;
34f2be46 2757 case PORT_D:
26739f12 2758 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2759 break;
2760 default:
2761 return connector_status_unknown;
2762 }
2763
10f76a38 2764 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2765 return connector_status_disconnected;
2766
26d61aad 2767 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2768}
2769
8c241fef
KP		 2770static struct edid *
2771intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2772{
9cd300e0 2773 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2774
9cd300e0
JN		 2775 /* use cached edid if we have one */
2776 if (intel_connector->edid) {
2777 struct edid *edid;
2778 int size;
2779
2780 /* invalid edid */
2781 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2782 return NULL;
2783
9cd300e0 2784 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2785 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2786 if (!edid)
2787 return NULL;
2788
d6f24d0f
JB		 2789 return edid;
2790 }
8c241fef 2791
9cd300e0 2792 return drm_get_edid(connector, adapter);
8c241fef
KP		 2793}
2794
2795static int
2796intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2797{
9cd300e0 2798 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2799
9cd300e0
JN		 2800 /* use cached edid if we have one */
2801 if (intel_connector->edid) {
2802 /* invalid edid */
2803 if (IS_ERR(intel_connector->edid))
2804 return 0;
2805
2806 return intel_connector_update_modes(connector,
2807 intel_connector->edid);
d6f24d0f
JB		 2808 }
2809
9cd300e0 2810 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2811}
2812
a9756bb5
ZW		 2813static enum drm_connector_status
2814intel_dp_detect(struct drm_connector *connector, bool force)
2815{
2816 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2817 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2818 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2819 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2820 enum drm_connector_status status;
2821 struct edid *edid = NULL;
2822
164c8598
CW		 2823 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2824 connector->base.id, drm_get_connector_name(connector));
2825
a9756bb5
ZW		 2826 intel_dp->has_audio = false;
2827
2828 if (HAS_PCH_SPLIT(dev))
2829 status = ironlake_dp_detect(intel_dp);
2830 else
2831 status = g4x_dp_detect(intel_dp);
1b9be9d0 2832
a9756bb5
ZW		 2833 if (status != connector_status_connected)
2834 return status;
2835
0d198328
AJ		 2836 intel_dp_probe_oui(intel_dp);
2837
c3e5f67b
DV		 2838 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2839 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2840 } else {
8c241fef 2841 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2842 if (edid) {
2843 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2844 kfree(edid);
2845 }
a9756bb5
ZW		 2846 }
2847
d63885da
PZ		 2848 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2849 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2850 return connector_status_connected;
a4fc5ed6
KP		 2851}
2852
2853static int intel_dp_get_modes(struct drm_connector *connector)
2854{
df0e9248 2855 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2856 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2857 struct drm_device *dev = connector->dev;
32f9d658 2858 int ret;
a4fc5ed6
KP		 2859
2860 /* We should parse the EDID data and find out if it has an audio sink
2861 */
2862
8c241fef 2863 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2864 if (ret)
32f9d658
ZW		 2865 return ret;
2866
f8779fda 2867 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2868 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2869 struct drm_display_mode *mode;
dd06f90e
JN		 2870 mode = drm_mode_duplicate(dev,
2871 intel_connector->panel.fixed_mode);
f8779fda 2872 if (mode) {
32f9d658
ZW		 2873 drm_mode_probed_add(connector, mode);
2874 return 1;
2875 }
2876 }
2877 return 0;
a4fc5ed6
KP		 2878}
2879
1aad7ac0
CW		 2880static bool
2881intel_dp_detect_audio(struct drm_connector *connector)
2882{
2883 struct intel_dp *intel_dp = intel_attached_dp(connector);
2884 struct edid *edid;
2885 bool has_audio = false;
2886
8c241fef 2887 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2888 if (edid) {
2889 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2890 kfree(edid);
2891 }
2892
2893 return has_audio;
2894}
2895
f684960e
CW		 2896static int
2897intel_dp_set_property(struct drm_connector *connector,
2898 struct drm_property *property,
2899 uint64_t val)
2900{
e953fd7b 2901 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2902 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2903 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2904 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2905 int ret;
2906
662595df 2907 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2908 if (ret)
2909 return ret;
2910
3f43c48d 2911 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2912 int i = val;
2913 bool has_audio;
2914
2915 if (i == intel_dp->force_audio)
f684960e
CW		 2916 return 0;
2917
1aad7ac0 2918 intel_dp->force_audio = i;
f684960e 2919
c3e5f67b 2920 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2921 has_audio = intel_dp_detect_audio(connector);
2922 else
c3e5f67b 2923 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2924
2925 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2926 return 0;
2927
1aad7ac0 2928 intel_dp->has_audio = has_audio;
f684960e
CW		 2929 goto done;
2930 }
2931
e953fd7b 2932 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2933 bool old_auto = intel_dp->color_range_auto;
2934 uint32_t old_range = intel_dp->color_range;
2935
55bc60db
VS		 2936 switch (val) {
2937 case INTEL_BROADCAST_RGB_AUTO:
2938 intel_dp->color_range_auto = true;
2939 break;
2940 case INTEL_BROADCAST_RGB_FULL:
2941 intel_dp->color_range_auto = false;
2942 intel_dp->color_range = 0;
2943 break;
2944 case INTEL_BROADCAST_RGB_LIMITED:
2945 intel_dp->color_range_auto = false;
2946 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2947 break;
2948 default:
2949 return -EINVAL;
2950 }
ae4edb80
DV		 2951
2952 if (old_auto == intel_dp->color_range_auto &&
2953 old_range == intel_dp->color_range)
2954 return 0;
2955
e953fd7b
CW		 2956 goto done;
2957 }
2958
53b41837
YN		 2959 if (is_edp(intel_dp) &&
2960 property == connector->dev->mode_config.scaling_mode_property) {
2961 if (val == DRM_MODE_SCALE_NONE) {
2962 DRM_DEBUG_KMS("no scaling not supported\n");
2963 return -EINVAL;
2964 }
2965
2966 if (intel_connector->panel.fitting_mode == val) {
2967 /* the eDP scaling property is not changed */
2968 return 0;
2969 }
2970 intel_connector->panel.fitting_mode = val;
2971
2972 goto done;
2973 }
2974
f684960e
CW		 2975 return -EINVAL;
2976
2977done:
c0c36b94
CW		 2978 if (intel_encoder->base.crtc)
2979 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2980
2981 return 0;
2982}
2983
a4fc5ed6 2984static void
73845adf 2985intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 2986{
1d508706 2987 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2988
9cd300e0
JN		 2989 if (!IS_ERR_OR_NULL(intel_connector->edid))
2990 kfree(intel_connector->edid);
2991
acd8db10
PZ		 2992 /* Can't call is_edp() since the encoder may have been destroyed
2993 * already. */
2994 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 2995 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2996
a4fc5ed6
KP		 2997 drm_sysfs_connector_remove(connector);
2998 drm_connector_cleanup(connector);
55f78c43 2999 kfree(connector);
a4fc5ed6
KP		 3000}
3001
00c09d70 3002void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3003{
da63a9f2
PZ		 3004 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3005 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3006 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3007
3008 i2c_del_adapter(&intel_dp->adapter);
3009 drm_encoder_cleanup(encoder);
bd943159
KP		 3010 if (is_edp(intel_dp)) {
3011 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3012 mutex_lock(&dev->mode_config.mutex);
bd943159 3013 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3014 mutex_unlock(&dev->mode_config.mutex);
bd943159 3015 }
da63a9f2 3016 kfree(intel_dig_port);
24d05927
DV		 3017}
3018
a4fc5ed6 3019static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 3020 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 3021};
3022
3023static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3024 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3025 .detect = intel_dp_detect,
3026 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3027 .set_property = intel_dp_set_property,
73845adf 3028 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3029};
3030
3031static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3032 .get_modes = intel_dp_get_modes,
3033 .mode_valid = intel_dp_mode_valid,
df0e9248 3034 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3035};
3036
a4fc5ed6 3037static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3038 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3039};
3040
995b6762 3041static void
21d40d37 3042intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3043{
fa90ecef 3044 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3045
885a5014 3046 intel_dp_check_link_status(intel_dp);
c8110e52 3047}
6207937d 3048
e3421a18
ZW		 3049/* Return which DP Port should be selected for Transcoder DP control */
3050int
0206e353 3051intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3052{
3053 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3054 struct intel_encoder *intel_encoder;
3055 struct intel_dp *intel_dp;
e3421a18 3056
fa90ecef
PZ		 3057 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3058 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3059
fa90ecef
PZ		 3060 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3061 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3062 return intel_dp->output_reg;
e3421a18 3063 }
ea5b213a 3064
e3421a18
ZW		 3065 return -1;
3066}
3067
36e83a18 3068/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3069bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3070{
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct child_device_config *p_child;
3073 int i;
3074
41aa3448 3075 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3076 return false;
3077
41aa3448
RV		 3078 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3079 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 3080
3081 if (p_child->dvo_port == PORT_IDPD &&
3082 p_child->device_type == DEVICE_TYPE_eDP)
3083 return true;
3084 }
3085 return false;
3086}
3087
f684960e
CW		 3088static void
3089intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3090{
53b41837
YN		 3091 struct intel_connector *intel_connector = to_intel_connector(connector);
3092
3f43c48d 3093 intel_attach_force_audio_property(connector);
e953fd7b 3094 intel_attach_broadcast_rgb_property(connector);
55bc60db 3095 intel_dp->color_range_auto = true;
53b41837
YN		 3096
3097 if (is_edp(intel_dp)) {
3098 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3099 drm_object_attach_property(
3100 &connector->base,
53b41837 3101 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3102 DRM_MODE_SCALE_ASPECT);
3103 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3104 }
f684960e
CW		 3105}
3106
67a54566
DV		 3107static void
3108intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3109 struct intel_dp *intel_dp,
3110 struct edp_power_seq *out)
67a54566
DV		 3111{
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3113 struct edp_power_seq cur, vbt, spec, final;
3114 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 3115 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3116
3117 if (HAS_PCH_SPLIT(dev)) {
3118 pp_control_reg = PCH_PP_CONTROL;
3119 pp_on_reg = PCH_PP_ON_DELAYS;
3120 pp_off_reg = PCH_PP_OFF_DELAYS;
3121 pp_div_reg = PCH_PP_DIVISOR;
3122 } else {
3123 pp_control_reg = PIPEA_PP_CONTROL;
3124 pp_on_reg = PIPEA_PP_ON_DELAYS;
3125 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3126 pp_div_reg = PIPEA_PP_DIVISOR;
3127 }
67a54566
DV		 3128
3129 /* Workaround: Need to write PP_CONTROL with the unlock key as
3130 * the very first thing. */
453c5420
JB		 3131 pp = ironlake_get_pp_control(intel_dp);
3132 I915_WRITE(pp_control_reg, pp);
67a54566 3133
453c5420
JB		 3134 pp_on = I915_READ(pp_on_reg);
3135 pp_off = I915_READ(pp_off_reg);
3136 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3137
3138 /* Pull timing values out of registers */
3139 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3140 PANEL_POWER_UP_DELAY_SHIFT;
3141
3142 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3143 PANEL_LIGHT_ON_DELAY_SHIFT;
3144
3145 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3146 PANEL_LIGHT_OFF_DELAY_SHIFT;
3147
3148 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3149 PANEL_POWER_DOWN_DELAY_SHIFT;
3150
3151 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3152 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3153
3154 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3155 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3156
41aa3448 3157 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3158
3159 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3160 * our hw here, which are all in 100usec. */
3161 spec.t1_t3 = 210 * 10;
3162 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3163 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3164 spec.t10 = 500 * 10;
3165 /* This one is special and actually in units of 100ms, but zero
3166 * based in the hw (so we need to add 100 ms). But the sw vbt
3167 * table multiplies it with 1000 to make it in units of 100usec,
3168 * too. */
3169 spec.t11_t12 = (510 + 100) * 10;
3170
3171 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3172 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3173
3174 /* Use the max of the register settings and vbt. If both are
3175 * unset, fall back to the spec limits. */
3176#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3177 spec.field : \
3178 max(cur.field, vbt.field))
3179 assign_final(t1_t3);
3180 assign_final(t8);
3181 assign_final(t9);
3182 assign_final(t10);
3183 assign_final(t11_t12);
3184#undef assign_final
3185
3186#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3187 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3188 intel_dp->backlight_on_delay = get_delay(t8);
3189 intel_dp->backlight_off_delay = get_delay(t9);
3190 intel_dp->panel_power_down_delay = get_delay(t10);
3191 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3192#undef get_delay
3193
f30d26e4
JN		 3194 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3195 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3196 intel_dp->panel_power_cycle_delay);
3197
3198 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3199 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3200
3201 if (out)
3202 *out = final;
3203}
3204
3205static void
3206intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3207 struct intel_dp *intel_dp,
3208 struct edp_power_seq *seq)
3209{
3210 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3211 u32 pp_on, pp_off, pp_div, port_sel = 0;
3212 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3213 int pp_on_reg, pp_off_reg, pp_div_reg;
3214
3215 if (HAS_PCH_SPLIT(dev)) {
3216 pp_on_reg = PCH_PP_ON_DELAYS;
3217 pp_off_reg = PCH_PP_OFF_DELAYS;
3218 pp_div_reg = PCH_PP_DIVISOR;
3219 } else {
3220 pp_on_reg = PIPEA_PP_ON_DELAYS;
3221 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3222 pp_div_reg = PIPEA_PP_DIVISOR;
3223 }
3224
67a54566 3225 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3226 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3227 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3228 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3229 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3230 /* Compute the divisor for the pp clock, simply match the Bspec
3231 * formula. */
453c5420 3232 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3233 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3234 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3235
3236 /* Haswell doesn't have any port selection bits for the panel
3237 * power sequencer any more. */
bc7d38a4
ID		 3238 if (IS_VALLEYVIEW(dev)) {
3239 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3240 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3241 if (dp_to_dig_port(intel_dp)->port == PORT_A)
453c5420 3242 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 3243 else
453c5420 3244 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 3245 }
3246
453c5420
JB		 3247 pp_on |= port_sel;
3248
3249 I915_WRITE(pp_on_reg, pp_on);
3250 I915_WRITE(pp_off_reg, pp_off);
3251 I915_WRITE(pp_div_reg, pp_div);
67a54566 3252
67a54566 3253 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3254 I915_READ(pp_on_reg),
3255 I915_READ(pp_off_reg),
3256 I915_READ(pp_div_reg));
f684960e
CW		 3257}
3258
ed92f0b2
PZ		 3259static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3260 struct intel_connector *intel_connector)
3261{
3262 struct drm_connector *connector = &intel_connector->base;
3263 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3264 struct drm_device *dev = intel_dig_port->base.base.dev;
3265 struct drm_i915_private *dev_priv = dev->dev_private;
3266 struct drm_display_mode *fixed_mode = NULL;
3267 struct edp_power_seq power_seq = { 0 };
3268 bool has_dpcd;
3269 struct drm_display_mode *scan;
3270 struct edid *edid;
3271
3272 if (!is_edp(intel_dp))
3273 return true;
3274
3275 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3276
3277 /* Cache DPCD and EDID for edp. */
3278 ironlake_edp_panel_vdd_on(intel_dp);
3279 has_dpcd = intel_dp_get_dpcd(intel_dp);
3280 ironlake_edp_panel_vdd_off(intel_dp, false);
3281
3282 if (has_dpcd) {
3283 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3284 dev_priv->no_aux_handshake =
3285 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3286 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3287 } else {
3288 /* if this fails, presume the device is a ghost */
3289 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3290 return false;
3291 }
3292
3293 /* We now know it's not a ghost, init power sequence regs. */
3294 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3295 &power_seq);
3296
3297 ironlake_edp_panel_vdd_on(intel_dp);
3298 edid = drm_get_edid(connector, &intel_dp->adapter);
3299 if (edid) {
3300 if (drm_add_edid_modes(connector, edid)) {
3301 drm_mode_connector_update_edid_property(connector,
3302 edid);
3303 drm_edid_to_eld(connector, edid);
3304 } else {
3305 kfree(edid);
3306 edid = ERR_PTR(-EINVAL);
3307 }
3308 } else {
3309 edid = ERR_PTR(-ENOENT);
3310 }
3311 intel_connector->edid = edid;
3312
3313 /* prefer fixed mode from EDID if available */
3314 list_for_each_entry(scan, &connector->probed_modes, head) {
3315 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3316 fixed_mode = drm_mode_duplicate(dev, scan);
3317 break;
3318 }
3319 }
3320
3321 /* fallback to VBT if available for eDP */
3322 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3323 fixed_mode = drm_mode_duplicate(dev,
3324 dev_priv->vbt.lfp_lvds_vbt_mode);
3325 if (fixed_mode)
3326 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3327 }
3328
3329 ironlake_edp_panel_vdd_off(intel_dp, false);
3330
3331 intel_panel_init(&intel_connector->panel, fixed_mode);
3332 intel_panel_setup_backlight(connector);
3333
3334 return true;
3335}
3336
16c25533 3337bool
f0fec3f2
PZ		 3338intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3339 struct intel_connector *intel_connector)
a4fc5ed6 3340{
f0fec3f2
PZ		 3341 struct drm_connector *connector = &intel_connector->base;
3342 struct intel_dp *intel_dp = &intel_dig_port->dp;
3343 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3344 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3345 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3346 enum port port = intel_dig_port->port;
5eb08b69 3347 const char *name = NULL;
b2a14755 3348 int type, error;
a4fc5ed6 3349
0767935e
DV		 3350 /* Preserve the current hw state. */
3351 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3352 intel_dp->attached_connector = intel_connector;
3d3dc149 3353
f7d24902 3354 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3355 /*
3356 * FIXME : We need to initialize built-in panels before external panels.
3357 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3358 */
f7d24902
ID		 3359 switch (port) {
3360 case PORT_A:
b329530c 3361 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3362 break;
3363 case PORT_C:
3364 if (IS_VALLEYVIEW(dev))
3365 type = DRM_MODE_CONNECTOR_eDP;
3366 break;
3367 case PORT_D:
3368 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3369 type = DRM_MODE_CONNECTOR_eDP;
3370 break;
3371 default: /* silence GCC warning */
3372 break;
b329530c
AJ		 3373 }
3374
f7d24902
ID		 3375 /*
3376 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3377 * for DP the encoder type can be set by the caller to
3378 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3379 */
3380 if (type == DRM_MODE_CONNECTOR_eDP)
3381 intel_encoder->type = INTEL_OUTPUT_EDP;
3382
e7281eab
ID		 3383 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3384 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3385 port_name(port));
3386
b329530c 3387 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3388 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3389
a4fc5ed6
KP		 3390 connector->interlace_allowed = true;
3391 connector->doublescan_allowed = 0;
3392
f0fec3f2
PZ		 3393 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3394 ironlake_panel_vdd_work);
a4fc5ed6 3395
df0e9248 3396 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3397 drm_sysfs_connector_add(connector);
3398
affa9354 3399 if (HAS_DDI(dev))
bcbc889b
PZ		 3400 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3401 else
3402 intel_connector->get_hw_state = intel_connector_get_hw_state;
3403
9ed35ab1
PZ		 3404 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3405 if (HAS_DDI(dev)) {
3406 switch (intel_dig_port->port) {
3407 case PORT_A:
3408 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3409 break;
3410 case PORT_B:
3411 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3412 break;
3413 case PORT_C:
3414 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3415 break;
3416 case PORT_D:
3417 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3418 break;
3419 default:
3420 BUG();
3421 }
3422 }
e8cb4558 3423
a4fc5ed6 3424 /* Set up the DDC bus. */
ab9d7c30
PZ		 3425 switch (port) {
3426 case PORT_A:
1d843f9d 3427 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3428 name = "DPDDC-A";
3429 break;
3430 case PORT_B:
1d843f9d 3431 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3432 name = "DPDDC-B";
3433 break;
3434 case PORT_C:
1d843f9d 3435 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3436 name = "DPDDC-C";
3437 break;
3438 case PORT_D:
1d843f9d 3439 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3440 name = "DPDDC-D";
3441 break;
3442 default:
ad1c0b19 3443 BUG();
5eb08b69
ZW		 3444 }
3445
b2a14755
PZ		 3446 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3447 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3448 error, port_name(port));
c1f05264 3449
2b28bb1b
RV		 3450 intel_dp->psr_setup_done = false;
3451
b2f246a8 3452 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3453 i2c_del_adapter(&intel_dp->adapter);
3454 if (is_edp(intel_dp)) {
3455 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3456 mutex_lock(&dev->mode_config.mutex);
3457 ironlake_panel_vdd_off_sync(intel_dp);
3458 mutex_unlock(&dev->mode_config.mutex);
3459 }
b2f246a8
PZ		 3460 drm_sysfs_connector_remove(connector);
3461 drm_connector_cleanup(connector);
16c25533 3462 return false;
b2f246a8 3463 }
32f9d658 3464
f684960e
CW		 3465 intel_dp_add_properties(intel_dp, connector);
3466
a4fc5ed6
KP		 3467 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3468 * 0xd. Failure to do so will result in spurious interrupts being
3469 * generated on the port when a cable is not attached.
3470 */
3471 if (IS_G4X(dev) && !IS_GM45(dev)) {
3472 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3473 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3474 }
16c25533
PZ		 3475
3476 return true;
a4fc5ed6 3477}
f0fec3f2
PZ		 3478
3479void
3480intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3481{
3482 struct intel_digital_port *intel_dig_port;
3483 struct intel_encoder *intel_encoder;
3484 struct drm_encoder *encoder;
3485 struct intel_connector *intel_connector;
3486
3487 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3488 if (!intel_dig_port)
3489 return;
3490
3491 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3492 if (!intel_connector) {
3493 kfree(intel_dig_port);
3494 return;
3495 }
3496
3497 intel_encoder = &intel_dig_port->base;
3498 encoder = &intel_encoder->base;
3499
3500 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3501 DRM_MODE_ENCODER_TMDS);
00c09d70 3502 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3503
5bfe2ac0 3504 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3505 intel_encoder->enable = intel_enable_dp;
3506 intel_encoder->pre_enable = intel_pre_enable_dp;
3507 intel_encoder->disable = intel_disable_dp;
3508 intel_encoder->post_disable = intel_post_disable_dp;
3509 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3510 intel_encoder->get_config = intel_dp_get_config;
89b667f8
JB		 3511 if (IS_VALLEYVIEW(dev))
3512 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3513
174edf1f 3514 intel_dig_port->port = port;
f0fec3f2
PZ		 3515 intel_dig_port->dp.output_reg = output_reg;
3516
00c09d70 3517 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3518 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3519 intel_encoder->cloneable = false;
3520 intel_encoder->hot_plug = intel_dp_hot_plug;
3521
15b1d171
PZ		 3522 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3523 drm_encoder_cleanup(encoder);
3524 kfree(intel_dig_port);
b2f246a8 3525 kfree(intel_connector);
15b1d171 3526 }
f0fec3f2 3527}
Linux kernel - Deliverables
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