projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Replace big nested if block with early return
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
ad933b56 311 if (port_sel == PANEL_PORT_SELECT_VLV(port))
bf13e81b
JN		 312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
01527b31
CT		 339/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341static int edp_notify_handler(struct notifier_block *this, unsigned long code,
342 void *unused)
343{
344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
345 edp_notifier);
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 u32 pp_div;
349 u32 pp_ctrl_reg, pp_div_reg;
350 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
351
352 if (!is_edp(intel_dp) || code != SYS_RESTART)
353 return 0;
354
355 if (IS_VALLEYVIEW(dev)) {
356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358 pp_div = I915_READ(pp_div_reg);
359 pp_div &= PP_REFERENCE_DIVIDER_MASK;
360
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg, pp_div | 0x1F);
363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364 msleep(intel_dp->panel_power_cycle_delay);
365 }
366
367 return 0;
368}
369
4be73780 370static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 371{
30add22d 372 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 373 struct drm_i915_private *dev_priv = dev->dev_private;
374
bf13e81b 375 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 376}
377
4be73780 378static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 379{
30add22d 380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 381 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
383 struct intel_encoder *intel_encoder = &intel_dig_port->base;
384 enum intel_display_power_domain power_domain;
ebf33b18 385
bb4932c4
ID		 386 power_domain = intel_display_port_power_domain(intel_encoder);
387 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 388 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 389}
390
9b984dae
KP		 391static void
392intel_dp_check_edp(struct intel_dp *intel_dp)
393{
30add22d 394 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 395 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 396
9b984dae
KP		 397 if (!is_edp(intel_dp))
398 return;
453c5420 399
4be73780 400 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 403 I915_READ(_pp_stat_reg(intel_dp)),
404 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 405 }
406}
407
9ee32fea
DV		 408static uint32_t
409intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
410{
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 414 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 415 uint32_t status;
416 bool done;
417
ef04f00d 418#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 419 if (has_aux_irq)
b18ac466 420 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 421 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 422 else
423 done = wait_for_atomic(C, 10) == 0;
424 if (!done)
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
426 has_aux_irq);
427#undef C
428
429 return status;
430}
431
ec5b01dd 432static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 433{
174edf1f
PZ		 434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 436
ec5b01dd
DL		 437 /*
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 440 */
ec5b01dd
DL		 441 return index ? 0 : intel_hrawclk(dev) / 2;
442}
443
444static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448
449 if (index)
450 return 0;
451
452 if (intel_dig_port->port == PORT_A) {
453 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 455 else
b84a1cf8 456 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 457 } else {
458 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
459 }
460}
461
462static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
463{
464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
465 struct drm_device *dev = intel_dig_port->base.base.dev;
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 if (intel_dig_port->port == PORT_A) {
469 if (index)
470 return 0;
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 472 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
473 /* Workaround for non-ULT HSW */
bc86625a
CW		 474 switch (index) {
475 case 0: return 63;
476 case 1: return 72;
477 default: return 0;
478 }
ec5b01dd 479 } else {
bc86625a 480 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 481 }
b84a1cf8
RV		 482}
483
ec5b01dd
DL		 484static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
485{
486 return index ? 0 : 100;
487}
488
5ed12a19
DL		 489static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
490 bool has_aux_irq,
491 int send_bytes,
492 uint32_t aux_clock_divider)
493{
494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
495 struct drm_device *dev = intel_dig_port->base.base.dev;
496 uint32_t precharge, timeout;
497
498 if (IS_GEN6(dev))
499 precharge = 3;
500 else
501 precharge = 5;
502
503 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
504 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
505 else
506 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
507
508 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 509 DP_AUX_CH_CTL_DONE |
5ed12a19 510 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 511 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 512 timeout |
788d4433 513 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 514 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
515 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 516 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 517}
518
b84a1cf8
RV		 519static int
520intel_dp_aux_ch(struct intel_dp *intel_dp,
521 uint8_t *send, int send_bytes,
522 uint8_t *recv, int recv_size)
523{
524 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
525 struct drm_device *dev = intel_dig_port->base.base.dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
528 uint32_t ch_data = ch_ctl + 4;
bc86625a 529 uint32_t aux_clock_divider;
b84a1cf8
RV		 530 int i, ret, recv_bytes;
531 uint32_t status;
5ed12a19 532 int try, clock = 0;
4e6b788c 533 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 534 bool vdd;
535
72c3500a
VS		 536 /*
537 * We will be called with VDD already enabled for dpcd/edid/oui reads.
538 * In such cases we want to leave VDD enabled and it's up to upper layers
539 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
540 * ourselves.
541 */
1e0560e0 542 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 543
544 /* dp aux is extremely sensitive to irq latency, hence request the
545 * lowest possible wakeup latency and so prevent the cpu from going into
546 * deep sleep states.
547 */
548 pm_qos_update_request(&dev_priv->pm_qos, 0);
549
550 intel_dp_check_edp(intel_dp);
5eb08b69 551
c67a470b
PZ		 552 intel_aux_display_runtime_get(dev_priv);
553
11bee43e
JB		 554 /* Try to wait for any previous AUX channel activity */
555 for (try = 0; try < 3; try++) {
ef04f00d 556 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 557 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
558 break;
559 msleep(1);
560 }
561
562 if (try == 3) {
563 WARN(1, "dp_aux_ch not started status 0x%08x\n",
564 I915_READ(ch_ctl));
9ee32fea
DV		 565 ret = -EBUSY;
566 goto out;
4f7f7b7e
CW		 567 }
568
46a5ae9f
PZ		 569 /* Only 5 data registers! */
570 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
571 ret = -E2BIG;
572 goto out;
573 }
574
ec5b01dd 575 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 576 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
577 has_aux_irq,
578 send_bytes,
579 aux_clock_divider);
5ed12a19 580
bc86625a
CW		 581 /* Must try at least 3 times according to DP spec */
582 for (try = 0; try < 5; try++) {
583 /* Load the send data into the aux channel data registers */
584 for (i = 0; i < send_bytes; i += 4)
585 I915_WRITE(ch_data + i,
586 pack_aux(send + i, send_bytes - i));
587
588 /* Send the command and wait for it to complete */
5ed12a19 589 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 590
591 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
592
593 /* Clear done status and any errors */
594 I915_WRITE(ch_ctl,
595 status |
596 DP_AUX_CH_CTL_DONE |
597 DP_AUX_CH_CTL_TIME_OUT_ERROR |
598 DP_AUX_CH_CTL_RECEIVE_ERROR);
599
600 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
601 DP_AUX_CH_CTL_RECEIVE_ERROR))
602 continue;
603 if (status & DP_AUX_CH_CTL_DONE)
604 break;
605 }
4f7f7b7e 606 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 607 break;
608 }
609
a4fc5ed6 610 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 611 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 612 ret = -EBUSY;
613 goto out;
a4fc5ed6
KP		 614 }
615
616 /* Check for timeout or receive error.
617 * Timeouts occur when the sink is not connected
618 */
a5b3da54 619 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 620 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 621 ret = -EIO;
622 goto out;
a5b3da54 623 }
1ae8c0a5
KP		 624
625 /* Timeouts occur when the device isn't connected, so they're
626 * "normal" -- don't fill the kernel log with these */
a5b3da54 627 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 628 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 629 ret = -ETIMEDOUT;
630 goto out;
a4fc5ed6
KP		 631 }
632
633 /* Unload any bytes sent back from the other side */
634 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
635 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 636 if (recv_bytes > recv_size)
637 recv_bytes = recv_size;
0206e353 638
4f7f7b7e
CW		 639 for (i = 0; i < recv_bytes; i += 4)
640 unpack_aux(I915_READ(ch_data + i),
641 recv + i, recv_bytes - i);
a4fc5ed6 642
9ee32fea
DV		 643 ret = recv_bytes;
644out:
645 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 646 intel_aux_display_runtime_put(dev_priv);
9ee32fea 647
884f19e9
JN		 648 if (vdd)
649 edp_panel_vdd_off(intel_dp, false);
650
9ee32fea 651 return ret;
a4fc5ed6
KP		 652}
653
a6c8aff0
JN		 654#define BARE_ADDRESS_SIZE 3
655#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 656static ssize_t
657intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 658{
9d1a1031
JN		 659 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
660 uint8_t txbuf[20], rxbuf[20];
661 size_t txsize, rxsize;
a4fc5ed6 662 int ret;
a4fc5ed6 663
9d1a1031
JN		 664 txbuf[0] = msg->request << 4;
665 txbuf[1] = msg->address >> 8;
666 txbuf[2] = msg->address & 0xff;
667 txbuf[3] = msg->size - 1;
46a5ae9f 668
9d1a1031
JN		 669 switch (msg->request & ~DP_AUX_I2C_MOT) {
670 case DP_AUX_NATIVE_WRITE:
671 case DP_AUX_I2C_WRITE:
a6c8aff0 672 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 673 rxsize = 1;
f51a44b9 674
9d1a1031
JN		 675 if (WARN_ON(txsize > 20))
676 return -E2BIG;
a4fc5ed6 677
9d1a1031 678 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 679
9d1a1031
JN		 680 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
681 if (ret > 0) {
682 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 683
9d1a1031
JN		 684 /* Return payload size. */
685 ret = msg->size;
686 }
687 break;
46a5ae9f 688
9d1a1031
JN		 689 case DP_AUX_NATIVE_READ:
690 case DP_AUX_I2C_READ:
a6c8aff0 691 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 692 rxsize = msg->size + 1;
a4fc5ed6 693
9d1a1031
JN		 694 if (WARN_ON(rxsize > 20))
695 return -E2BIG;
a4fc5ed6 696
9d1a1031
JN		 697 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
698 if (ret > 0) {
699 msg->reply = rxbuf[0] >> 4;
700 /*
701 * Assume happy day, and copy the data. The caller is
702 * expected to check msg->reply before touching it.
703 *
704 * Return payload size.
705 */
706 ret--;
707 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 708 }
9d1a1031
JN		 709 break;
710
711 default:
712 ret = -EINVAL;
713 break;
a4fc5ed6 714 }
f51a44b9 715
9d1a1031 716 return ret;
a4fc5ed6
KP		 717}
718
9d1a1031
JN		 719static void
720intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
721{
722 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 723 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
724 enum port port = intel_dig_port->port;
0b99836f 725 const char *name = NULL;
ab2c0672
DA		 726 int ret;
727
33ad6626
JN		 728 switch (port) {
729 case PORT_A:
730 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 731 name = "DPDDC-A";
ab2c0672 732 break;
33ad6626
JN		 733 case PORT_B:
734 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 735 name = "DPDDC-B";
ab2c0672 736 break;
33ad6626
JN		 737 case PORT_C:
738 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 739 name = "DPDDC-C";
ab2c0672 740 break;
33ad6626
JN		 741 case PORT_D:
742 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 743 name = "DPDDC-D";
33ad6626
JN		 744 break;
745 default:
746 BUG();
ab2c0672
DA		 747 }
748
33ad6626
JN		 749 if (!HAS_DDI(dev))
750 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 751
0b99836f 752 intel_dp->aux.name = name;
9d1a1031
JN		 753 intel_dp->aux.dev = dev->dev;
754 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 755
0b99836f
JN		 756 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
757 connector->base.kdev->kobj.name);
8316f337 758
4f71d0cb 759 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 760 if (ret < 0) {
4f71d0cb 761 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 762 name, ret);
763 return;
ab2c0672 764 }
8a5e6aeb 765
0b99836f
JN		 766 ret = sysfs_create_link(&connector->base.kdev->kobj,
767 &intel_dp->aux.ddc.dev.kobj,
768 intel_dp->aux.ddc.dev.kobj.name);
769 if (ret < 0) {
770 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 771 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 772 }
a4fc5ed6
KP		 773}
774
80f65de3
ID		 775static void
776intel_dp_connector_unregister(struct intel_connector *intel_connector)
777{
778 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
779
0e32b39c
DA		 780 if (!intel_connector->mst_port)
781 sysfs_remove_link(&intel_connector->base.kdev->kobj,
782 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 783 intel_connector_unregister(intel_connector);
784}
785
0e50338c
DV		 786static void
787hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
788{
789 switch (link_bw) {
790 case DP_LINK_BW_1_62:
791 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
792 break;
793 case DP_LINK_BW_2_7:
794 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
795 break;
796 case DP_LINK_BW_5_4:
797 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
798 break;
799 }
800}
801
c6bb3538
DV		 802static void
803intel_dp_set_clock(struct intel_encoder *encoder,
804 struct intel_crtc_config *pipe_config, int link_bw)
805{
806 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 807 const struct dp_link_dpll *divisor = NULL;
808 int i, count = 0;
c6bb3538
DV		 809
810 if (IS_G4X(dev)) {
9dd4ffdf
CML		 811 divisor = gen4_dpll;
812 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 813 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 814 divisor = pch_dpll;
815 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 816 } else if (IS_CHERRYVIEW(dev)) {
817 divisor = chv_dpll;
818 count = ARRAY_SIZE(chv_dpll);
c6bb3538 819 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 820 divisor = vlv_dpll;
821 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 822 }
9dd4ffdf
CML		 823
824 if (divisor && count) {
825 for (i = 0; i < count; i++) {
826 if (link_bw == divisor[i].link_bw) {
827 pipe_config->dpll = divisor[i].dpll;
828 pipe_config->clock_set = true;
829 break;
830 }
831 }
c6bb3538
DV		 832 }
833}
834
00c09d70 835bool
5bfe2ac0
DV		 836intel_dp_compute_config(struct intel_encoder *encoder,
837 struct intel_crtc_config *pipe_config)
a4fc5ed6 838{
5bfe2ac0 839 struct drm_device *dev = encoder->base.dev;
36008365 840 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 841 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 843 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 844 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 845 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 846 int lane_count, clock;
56071a20 847 int min_lane_count = 1;
eeb6324d 848 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 849 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 850 int min_clock = 0;
06ea66b6 851 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 852 int bpp, mode_rate;
06ea66b6 853 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 854 int link_avail, link_clock;
a4fc5ed6 855
bc7d38a4 856 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 857 pipe_config->has_pch_encoder = true;
858
03afc4a2 859 pipe_config->has_dp_encoder = true;
f769cd24 860 pipe_config->has_drrs = false;
9ed109a7 861 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 862
dd06f90e
JN		 863 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
864 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
865 adjusted_mode);
2dd24552
JB		 866 if (!HAS_PCH_SPLIT(dev))
867 intel_gmch_panel_fitting(intel_crtc, pipe_config,
868 intel_connector->panel.fitting_mode);
869 else
b074cec8
JB		 870 intel_pch_panel_fitting(intel_crtc, pipe_config,
871 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 872 }
873
cb1793ce 874 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 875 return false;
876
083f9560
DV		 877 DRM_DEBUG_KMS("DP link computation with max lane count %i "
878 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 879 max_lane_count, bws[max_clock],
880 adjusted_mode->crtc_clock);
083f9560 881
36008365
DV		 882 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
883 * bpc in between. */
3e7ca985 884 bpp = pipe_config->pipe_bpp;
56071a20
JN		 885 if (is_edp(intel_dp)) {
886 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
887 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
888 dev_priv->vbt.edp_bpp);
889 bpp = dev_priv->vbt.edp_bpp;
890 }
891
f4cdbc21
JN		 892 if (IS_BROADWELL(dev)) {
893 /* Yes, it's an ugly hack. */
894 min_lane_count = max_lane_count;
895 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
896 min_lane_count);
897 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 898 min_lane_count = min(dev_priv->vbt.edp_lanes,
899 max_lane_count);
900 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
901 min_lane_count);
902 }
903
904 if (dev_priv->vbt.edp_rate) {
905 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
906 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
907 bws[min_clock]);
908 }
7984211e 909 }
657445fe 910
36008365 911 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 912 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
913 bpp);
36008365 914
c6930992
DA		 915 for (clock = min_clock; clock <= max_clock; clock++) {
916 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 917 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
918 link_avail = intel_dp_max_data_rate(link_clock,
919 lane_count);
920
921 if (mode_rate <= link_avail) {
922 goto found;
923 }
924 }
925 }
926 }
c4867936 927
36008365 928 return false;
3685a8f3 929
36008365 930found:
55bc60db
VS		 931 if (intel_dp->color_range_auto) {
932 /*
933 * See:
934 * CEA-861-E - 5.1 Default Encoding Parameters
935 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
936 */
18316c8c 937 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 938 intel_dp->color_range = DP_COLOR_RANGE_16_235;
939 else
940 intel_dp->color_range = 0;
941 }
942
3685a8f3 943 if (intel_dp->color_range)
50f3b016 944 pipe_config->limited_color_range = true;
a4fc5ed6 945
36008365
DV		 946 intel_dp->link_bw = bws[clock];
947 intel_dp->lane_count = lane_count;
657445fe 948 pipe_config->pipe_bpp = bpp;
ff9a6750 949 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 950
36008365
DV		 951 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
952 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 953 pipe_config->port_clock, bpp);
36008365
DV		 954 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
955 mode_rate, link_avail);
a4fc5ed6 956
03afc4a2 957 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 958 adjusted_mode->crtc_clock,
959 pipe_config->port_clock,
03afc4a2 960 &pipe_config->dp_m_n);
9d1a455b 961
439d7ac0
PB		 962 if (intel_connector->panel.downclock_mode != NULL &&
963 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 964 pipe_config->has_drrs = true;
439d7ac0
PB		 965 intel_link_compute_m_n(bpp, lane_count,
966 intel_connector->panel.downclock_mode->clock,
967 pipe_config->port_clock,
968 &pipe_config->dp_m2_n2);
969 }
970
ea155f32 971 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 972 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
973 else
974 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 975
03afc4a2 976 return true;
a4fc5ed6
KP		 977}
978
7c62a164 979static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 980{
7c62a164
DV		 981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
982 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
983 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 dpa_ctl;
986
ff9a6750 987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 988 dpa_ctl = I915_READ(DP_A);
989 dpa_ctl &= ~DP_PLL_FREQ_MASK;
990
ff9a6750 991 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 992 /* For a long time we've carried around a ILK-DevA w/a for the
993 * 160MHz clock. If we're really unlucky, it's still required.
994 */
995 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 996 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 997 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 998 } else {
999 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1000 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1001 }
1ce17038 1002
ea9b6006
DV		 1003 I915_WRITE(DP_A, dpa_ctl);
1004
1005 POSTING_READ(DP_A);
1006 udelay(500);
1007}
1008
8ac33ed3 1009static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1010{
b934223d 1011 struct drm_device *dev = encoder->base.dev;
417e822d 1012 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1013 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1014 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1015 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1016 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1017
417e822d 1018 /*
1a2eb460 1019 * There are four kinds of DP registers:
417e822d
KP		 1020 *
1021 * IBX PCH
1a2eb460
KP		 1022 * SNB CPU
1023 * IVB CPU
417e822d
KP		 1024 * CPT PCH
1025 *
1026 * IBX PCH and CPU are the same for almost everything,
1027 * except that the CPU DP PLL is configured in this
1028 * register
1029 *
1030 * CPT PCH is quite different, having many bits moved
1031 * to the TRANS_DP_CTL register instead. That
1032 * configuration happens (oddly) in ironlake_pch_enable
1033 */
9c9e7927 1034
417e822d
KP		 1035 /* Preserve the BIOS-computed detected bit. This is
1036 * supposed to be read-only.
1037 */
1038 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1039
417e822d 1040 /* Handle DP bits in common between all three register formats */
417e822d 1041 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1042 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1043
9ed109a7 1044 if (crtc->config.has_audio) {
e0dac65e 1045 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1046 pipe_name(crtc->pipe));
ea5b213a 1047 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1048 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1049 }
247d89f6 1050
417e822d 1051 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1052
bc7d38a4 1053 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1054 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1055 intel_dp->DP |= DP_SYNC_HS_HIGH;
1056 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1057 intel_dp->DP |= DP_SYNC_VS_HIGH;
1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059
6aba5b6c 1060 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1061 intel_dp->DP |= DP_ENHANCED_FRAMING;
1062
7c62a164 1063 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1064 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1065 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1066 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1067
1068 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1069 intel_dp->DP |= DP_SYNC_HS_HIGH;
1070 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1071 intel_dp->DP |= DP_SYNC_VS_HIGH;
1072 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1073
6aba5b6c 1074 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1075 intel_dp->DP |= DP_ENHANCED_FRAMING;
1076
44f37d1f
CML		 1077 if (!IS_CHERRYVIEW(dev)) {
1078 if (crtc->pipe == 1)
1079 intel_dp->DP |= DP_PIPEB_SELECT;
1080 } else {
1081 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1082 }
417e822d
KP		 1083 } else {
1084 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1085 }
a4fc5ed6
KP		 1086}
1087
ffd6749d
PZ		 1088#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1089#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1090
1a5ef5b7
PZ		 1091#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1092#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1093
ffd6749d
PZ		 1094#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1095#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1096
4be73780 1097static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1098 u32 mask,
1099 u32 value)
bd943159 1100{
30add22d 1101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1102 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1103 u32 pp_stat_reg, pp_ctrl_reg;
1104
bf13e81b
JN		 1105 pp_stat_reg = _pp_stat_reg(intel_dp);
1106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1107
99ea7127 1108 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1109 mask, value,
1110 I915_READ(pp_stat_reg),
1111 I915_READ(pp_ctrl_reg));
32ce697c 1112
453c5420 1113 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1114 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1115 I915_READ(pp_stat_reg),
1116 I915_READ(pp_ctrl_reg));
32ce697c 1117 }
54c136d4
CW		 1118
1119 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1120}
32ce697c 1121
4be73780 1122static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1123{
1124 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1125 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1126}
1127
4be73780 1128static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1129{
1130 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1131 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1132}
1133
4be73780 1134static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1135{
1136 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1137
1138 /* When we disable the VDD override bit last we have to do the manual
1139 * wait. */
1140 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1141 intel_dp->panel_power_cycle_delay);
1142
4be73780 1143 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1144}
1145
4be73780 1146static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1147{
1148 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1149 intel_dp->backlight_on_delay);
1150}
1151
4be73780 1152static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1153{
1154 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1155 intel_dp->backlight_off_delay);
1156}
99ea7127 1157
832dd3c1
KP		 1158/* Read the current pp_control value, unlocking the register if it
1159 * is locked
1160 */
1161
453c5420 1162static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1163{
453c5420
JB		 1164 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 control;
832dd3c1 1167
bf13e81b 1168 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1169 control &= ~PANEL_UNLOCK_MASK;
1170 control |= PANEL_UNLOCK_REGS;
1171 return control;
bd943159
KP		 1172}
1173
1e0560e0 1174static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1175{
30add22d 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1179 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1180 enum intel_display_power_domain power_domain;
5d613501 1181 u32 pp;
453c5420 1182 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1183 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1184
97af61f5 1185 if (!is_edp(intel_dp))
adddaaf4 1186 return false;
bd943159
KP		 1187
1188 intel_dp->want_panel_vdd = true;
99ea7127 1189
4be73780 1190 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1191 return need_to_disable;
b0665d57 1192
4e6e1a54
ID		 1193 power_domain = intel_display_port_power_domain(intel_encoder);
1194 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1195
b0665d57 1196 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1197
4be73780
DV		 1198 if (!edp_have_panel_power(intel_dp))
1199 wait_panel_power_cycle(intel_dp);
99ea7127 1200
453c5420 1201 pp = ironlake_get_pp_control(intel_dp);
5d613501 1202 pp |= EDP_FORCE_VDD;
ebf33b18 1203
bf13e81b
JN		 1204 pp_stat_reg = _pp_stat_reg(intel_dp);
1205 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1206
1207 I915_WRITE(pp_ctrl_reg, pp);
1208 POSTING_READ(pp_ctrl_reg);
1209 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1210 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1211 /*
1212 * If the panel wasn't on, delay before accessing aux channel
1213 */
4be73780 1214 if (!edp_have_panel_power(intel_dp)) {
bd943159 1215 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1216 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1217 }
adddaaf4
JN		 1218
1219 return need_to_disable;
1220}
1221
b80d6c78 1222void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1223{
1224 if (is_edp(intel_dp)) {
1e0560e0 1225 bool vdd = edp_panel_vdd_on(intel_dp);
adddaaf4
JN		 1226
1227 WARN(!vdd, "eDP VDD already requested on\n");
1228 }
5d613501
JB		 1229}
1230
4be73780 1231static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1232{
30add22d 1233 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1234 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1235 struct intel_digital_port *intel_dig_port =
1236 dp_to_dig_port(intel_dp);
1237 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1238 enum intel_display_power_domain power_domain;
5d613501 1239 u32 pp;
453c5420 1240 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1241
51fd371b 1242 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1243
be2c9196
VS		 1244 if (intel_dp->want_panel_vdd || !edp_have_panel_vdd(intel_dp))
1245 return;
4e6e1a54 1246
be2c9196 1247 DRM_DEBUG_KMS("Turning eDP VDD off\n");
b0665d57 1248
be2c9196
VS		 1249 pp = ironlake_get_pp_control(intel_dp);
1250 pp &= ~EDP_FORCE_VDD;
bd943159 1251
be2c9196
VS		 1252 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1253 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1254
be2c9196
VS		 1255 I915_WRITE(pp_ctrl_reg, pp);
1256 POSTING_READ(pp_ctrl_reg);
99ea7127 1257
be2c9196
VS		 1258 /* Make sure sequencer is idle before allowing subsequent activity */
1259 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1260 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1261
be2c9196
VS		 1262 if ((pp & POWER_TARGET_ON) == 0)
1263 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1264
be2c9196
VS		 1265 power_domain = intel_display_port_power_domain(intel_encoder);
1266 intel_display_power_put(dev_priv, power_domain);
bd943159 1267}
5d613501 1268
4be73780 1269static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1270{
1271 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1272 struct intel_dp, panel_vdd_work);
30add22d 1273 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1274
51fd371b 1275 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1276 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1277 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1278}
1279
aba86890
ID		 1280static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1281{
1282 unsigned long delay;
1283
1284 /*
1285 * Queue the timer to fire a long time from now (relative to the power
1286 * down delay) to keep the panel power up across a sequence of
1287 * operations.
1288 */
1289 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1290 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1291}
1292
4be73780 1293static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1294{
97af61f5
KP		 1295 if (!is_edp(intel_dp))
1296 return;
5d613501 1297
bd943159 1298 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1299
bd943159
KP		 1300 intel_dp->want_panel_vdd = false;
1301
aba86890 1302 if (sync)
4be73780 1303 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1304 else
1305 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1306}
1307
1e0560e0
VS		 1308static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1309{
1310 edp_panel_vdd_off(intel_dp, sync);
1311}
1312
4be73780 1313void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1314{
30add22d 1315 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1316 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1317 u32 pp;
453c5420 1318 u32 pp_ctrl_reg;
9934c132 1319
97af61f5 1320 if (!is_edp(intel_dp))
bd943159 1321 return;
99ea7127
KP		 1322
1323 DRM_DEBUG_KMS("Turn eDP power on\n");
1324
4be73780 1325 if (edp_have_panel_power(intel_dp)) {
99ea7127 1326 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1327 return;
99ea7127 1328 }
9934c132 1329
4be73780 1330 wait_panel_power_cycle(intel_dp);
37c6c9b0 1331
bf13e81b 1332 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1333 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1334 if (IS_GEN5(dev)) {
1335 /* ILK workaround: disable reset around power sequence */
1336 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1337 I915_WRITE(pp_ctrl_reg, pp);
1338 POSTING_READ(pp_ctrl_reg);
05ce1a49 1339 }
37c6c9b0 1340
1c0ae80a 1341 pp |= POWER_TARGET_ON;
99ea7127
KP		 1342 if (!IS_GEN5(dev))
1343 pp |= PANEL_POWER_RESET;
1344
453c5420
JB		 1345 I915_WRITE(pp_ctrl_reg, pp);
1346 POSTING_READ(pp_ctrl_reg);
9934c132 1347
4be73780 1348 wait_panel_on(intel_dp);
dce56b3c 1349 intel_dp->last_power_on = jiffies;
9934c132 1350
05ce1a49
KP		 1351 if (IS_GEN5(dev)) {
1352 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1353 I915_WRITE(pp_ctrl_reg, pp);
1354 POSTING_READ(pp_ctrl_reg);
05ce1a49 1355 }
9934c132
JB		 1356}
1357
4be73780 1358void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1359{
4e6e1a54
ID		 1360 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1361 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1362 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1363 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1364 enum intel_display_power_domain power_domain;
99ea7127 1365 u32 pp;
453c5420 1366 u32 pp_ctrl_reg;
9934c132 1367
97af61f5
KP		 1368 if (!is_edp(intel_dp))
1369 return;
37c6c9b0 1370
99ea7127 1371 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1372
24f3e092
JN		 1373 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1374
453c5420 1375 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1376 /* We need to switch off panel power _and_ force vdd, for otherwise some
1377 * panels get very unhappy and cease to work. */
b3064154
PJ		 1378 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1379 EDP_BLC_ENABLE);
453c5420 1380
bf13e81b 1381 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1382
849e39f5
PZ		 1383 intel_dp->want_panel_vdd = false;
1384
453c5420
JB		 1385 I915_WRITE(pp_ctrl_reg, pp);
1386 POSTING_READ(pp_ctrl_reg);
9934c132 1387
dce56b3c 1388 intel_dp->last_power_cycle = jiffies;
4be73780 1389 wait_panel_off(intel_dp);
849e39f5
PZ		 1390
1391 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1392 power_domain = intel_display_port_power_domain(intel_encoder);
1393 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1394}
1395
1250d107
JN		 1396/* Enable backlight in the panel power control. */
1397static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1398{
da63a9f2
PZ		 1399 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1400 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1401 struct drm_i915_private *dev_priv = dev->dev_private;
1402 u32 pp;
453c5420 1403 u32 pp_ctrl_reg;
32f9d658 1404
01cb9ea6
JB		 1405 /*
1406 * If we enable the backlight right away following a panel power
1407 * on, we may see slight flicker as the panel syncs with the eDP
1408 * link. So delay a bit to make sure the image is solid before
1409 * allowing it to appear.
1410 */
4be73780 1411 wait_backlight_on(intel_dp);
453c5420 1412 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1413 pp |= EDP_BLC_ENABLE;
453c5420 1414
bf13e81b 1415 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1416
1417 I915_WRITE(pp_ctrl_reg, pp);
1418 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1419}
1420
1250d107
JN		 1421/* Enable backlight PWM and backlight PP control. */
1422void intel_edp_backlight_on(struct intel_dp *intel_dp)
1423{
1424 if (!is_edp(intel_dp))
1425 return;
1426
1427 DRM_DEBUG_KMS("\n");
1428
1429 intel_panel_enable_backlight(intel_dp->attached_connector);
1430 _intel_edp_backlight_on(intel_dp);
1431}
1432
1433/* Disable backlight in the panel power control. */
1434static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1435{
30add22d 1436 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1437 struct drm_i915_private *dev_priv = dev->dev_private;
1438 u32 pp;
453c5420 1439 u32 pp_ctrl_reg;
32f9d658 1440
453c5420 1441 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1442 pp &= ~EDP_BLC_ENABLE;
453c5420 1443
bf13e81b 1444 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1445
1446 I915_WRITE(pp_ctrl_reg, pp);
1447 POSTING_READ(pp_ctrl_reg);
dce56b3c 1448 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1449
1450 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1451}
1452
1453/* Disable backlight PP control and backlight PWM. */
1454void intel_edp_backlight_off(struct intel_dp *intel_dp)
1455{
1456 if (!is_edp(intel_dp))
1457 return;
1458
1459 DRM_DEBUG_KMS("\n");
f7d2323c 1460
1250d107 1461 _intel_edp_backlight_off(intel_dp);
f7d2323c 1462 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1463}
a4fc5ed6 1464
73580fb7
JN		 1465/*
1466 * Hook for controlling the panel power control backlight through the bl_power
1467 * sysfs attribute. Take care to handle multiple calls.
1468 */
1469static void intel_edp_backlight_power(struct intel_connector *connector,
1470 bool enable)
1471{
1472 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1473 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1474
1475 if (is_enabled == enable)
1476 return;
1477
1478 DRM_DEBUG_KMS("\n");
1479
1480 if (enable)
1481 _intel_edp_backlight_on(intel_dp);
1482 else
1483 _intel_edp_backlight_off(intel_dp);
1484}
1485
2bd2ad64 1486static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1487{
da63a9f2
PZ		 1488 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1489 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1490 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1491 struct drm_i915_private *dev_priv = dev->dev_private;
1492 u32 dpa_ctl;
1493
2bd2ad64
DV		 1494 assert_pipe_disabled(dev_priv,
1495 to_intel_crtc(crtc)->pipe);
1496
d240f20f
JB		 1497 DRM_DEBUG_KMS("\n");
1498 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1499 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1500 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1501
1502 /* We don't adjust intel_dp->DP while tearing down the link, to
1503 * facilitate link retraining (e.g. after hotplug). Hence clear all
1504 * enable bits here to ensure that we don't enable too much. */
1505 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1506 intel_dp->DP |= DP_PLL_ENABLE;
1507 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1508 POSTING_READ(DP_A);
1509 udelay(200);
d240f20f
JB		 1510}
1511
2bd2ad64 1512static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1513{
da63a9f2
PZ		 1514 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1515 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1516 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518 u32 dpa_ctl;
1519
2bd2ad64
DV		 1520 assert_pipe_disabled(dev_priv,
1521 to_intel_crtc(crtc)->pipe);
1522
d240f20f 1523 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1524 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1525 "dp pll off, should be on\n");
1526 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1527
1528 /* We can't rely on the value tracked for the DP register in
1529 * intel_dp->DP because link_down must not change that (otherwise link
1530 * re-training will fail. */
298b0b39 1531 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1532 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1533 POSTING_READ(DP_A);
d240f20f
JB		 1534 udelay(200);
1535}
1536
c7ad3810 1537/* If the sink supports it, try to set the power state appropriately */
c19b0669 1538void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1539{
1540 int ret, i;
1541
1542 /* Should have a valid DPCD by this point */
1543 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1544 return;
1545
1546 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1547 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1548 DP_SET_POWER_D3);
c7ad3810
JB		 1549 if (ret != 1)
1550 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1551 } else {
1552 /*
1553 * When turning on, we need to retry for 1ms to give the sink
1554 * time to wake up.
1555 */
1556 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1557 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1558 DP_SET_POWER_D0);
c7ad3810
JB		 1559 if (ret == 1)
1560 break;
1561 msleep(1);
1562 }
1563 }
1564}
1565
19d8fe15
DV		 1566static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1567 enum pipe *pipe)
d240f20f 1568{
19d8fe15 1569 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1570 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1571 struct drm_device *dev = encoder->base.dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1573 enum intel_display_power_domain power_domain;
1574 u32 tmp;
1575
1576 power_domain = intel_display_port_power_domain(encoder);
1577 if (!intel_display_power_enabled(dev_priv, power_domain))
1578 return false;
1579
1580 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1581
1582 if (!(tmp & DP_PORT_EN))
1583 return false;
1584
bc7d38a4 1585 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1586 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1587 } else if (IS_CHERRYVIEW(dev)) {
1588 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1589 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1590 *pipe = PORT_TO_PIPE(tmp);
1591 } else {
1592 u32 trans_sel;
1593 u32 trans_dp;
1594 int i;
1595
1596 switch (intel_dp->output_reg) {
1597 case PCH_DP_B:
1598 trans_sel = TRANS_DP_PORT_SEL_B;
1599 break;
1600 case PCH_DP_C:
1601 trans_sel = TRANS_DP_PORT_SEL_C;
1602 break;
1603 case PCH_DP_D:
1604 trans_sel = TRANS_DP_PORT_SEL_D;
1605 break;
1606 default:
1607 return true;
1608 }
1609
055e393f 1610 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1611 trans_dp = I915_READ(TRANS_DP_CTL(i));
1612 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1613 *pipe = i;
1614 return true;
1615 }
1616 }
19d8fe15 1617
4a0833ec
DV		 1618 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1619 intel_dp->output_reg);
1620 }
d240f20f 1621
19d8fe15
DV		 1622 return true;
1623}
d240f20f 1624
045ac3b5
JB		 1625static void intel_dp_get_config(struct intel_encoder *encoder,
1626 struct intel_crtc_config *pipe_config)
1627{
1628 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1629 u32 tmp, flags = 0;
63000ef6
XZ		 1630 struct drm_device *dev = encoder->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 enum port port = dp_to_dig_port(intel_dp)->port;
1633 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1634 int dotclock;
045ac3b5 1635
9ed109a7
DV		 1636 tmp = I915_READ(intel_dp->output_reg);
1637 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1638 pipe_config->has_audio = true;
1639
63000ef6 1640 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1641 if (tmp & DP_SYNC_HS_HIGH)
1642 flags |= DRM_MODE_FLAG_PHSYNC;
1643 else
1644 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1645
63000ef6
XZ		 1646 if (tmp & DP_SYNC_VS_HIGH)
1647 flags |= DRM_MODE_FLAG_PVSYNC;
1648 else
1649 flags |= DRM_MODE_FLAG_NVSYNC;
1650 } else {
1651 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1652 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1653 flags |= DRM_MODE_FLAG_PHSYNC;
1654 else
1655 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1656
63000ef6
XZ		 1657 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1658 flags |= DRM_MODE_FLAG_PVSYNC;
1659 else
1660 flags |= DRM_MODE_FLAG_NVSYNC;
1661 }
045ac3b5
JB		 1662
1663 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1664
eb14cb74
VS		 1665 pipe_config->has_dp_encoder = true;
1666
1667 intel_dp_get_m_n(crtc, pipe_config);
1668
18442d08 1669 if (port == PORT_A) {
f1f644dc
JB		 1670 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1671 pipe_config->port_clock = 162000;
1672 else
1673 pipe_config->port_clock = 270000;
1674 }
18442d08
VS		 1675
1676 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1677 &pipe_config->dp_m_n);
1678
1679 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1680 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1681
241bfc38 1682 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1683
c6cd2ee2
JN		 1684 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1685 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1686 /*
1687 * This is a big fat ugly hack.
1688 *
1689 * Some machines in UEFI boot mode provide us a VBT that has 18
1690 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1691 * unknown we fail to light up. Yet the same BIOS boots up with
1692 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1693 * max, not what it tells us to use.
1694 *
1695 * Note: This will still be broken if the eDP panel is not lit
1696 * up by the BIOS, and thus we can't get the mode at module
1697 * load.
1698 */
1699 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1700 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1701 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1702 }
045ac3b5
JB		 1703}
1704
34eb7579 1705static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1706{
34eb7579 1707 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1708}
1709
2b28bb1b
RV		 1710static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1711{
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713
18b5992c 1714 if (!HAS_PSR(dev))
2b28bb1b
RV		 1715 return false;
1716
18b5992c 1717 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1718}
1719
1720static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1721 struct edp_vsc_psr *vsc_psr)
1722{
1723 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1724 struct drm_device *dev = dig_port->base.base.dev;
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1727 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1728 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1729 uint32_t *data = (uint32_t *) vsc_psr;
1730 unsigned int i;
1731
1732 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1733 the video DIP being updated before program video DIP data buffer
1734 registers for DIP being updated. */
1735 I915_WRITE(ctl_reg, 0);
1736 POSTING_READ(ctl_reg);
1737
1738 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1739 if (i < sizeof(struct edp_vsc_psr))
1740 I915_WRITE(data_reg + i, *data++);
1741 else
1742 I915_WRITE(data_reg + i, 0);
1743 }
1744
1745 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1746 POSTING_READ(ctl_reg);
1747}
1748
1749static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1750{
1751 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 struct edp_vsc_psr psr_vsc;
1754
2b28bb1b
RV		 1755 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1756 memset(&psr_vsc, 0, sizeof(psr_vsc));
1757 psr_vsc.sdp_header.HB0 = 0;
1758 psr_vsc.sdp_header.HB1 = 0x7;
1759 psr_vsc.sdp_header.HB2 = 0x2;
1760 psr_vsc.sdp_header.HB3 = 0x8;
1761 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1762
1763 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1764 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1765 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1766}
1767
1768static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1769{
0e0ae652
RV		 1770 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1771 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1772 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1773 uint32_t aux_clock_divider;
2b28bb1b
RV		 1774 int precharge = 0x3;
1775 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1776 bool only_standby = false;
2b28bb1b 1777
ec5b01dd
DL		 1778 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1779
0e0ae652
RV		 1780 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1781 only_standby = true;
1782
2b28bb1b 1783 /* Enable PSR in sink */
0e0ae652 1784 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1785 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1786 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1787 else
9d1a1031
JN		 1788 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1789 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1790
1791 /* Setup AUX registers */
18b5992c
BW		 1792 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1793 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1794 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1795 DP_AUX_CH_CTL_TIME_OUT_400us |
1796 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1797 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1798 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1799}
1800
1801static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1802{
0e0ae652
RV		 1803 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1804 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 uint32_t max_sleep_time = 0x1f;
1807 uint32_t idle_frames = 1;
1808 uint32_t val = 0x0;
ed8546ac 1809 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1810 bool only_standby = false;
1811
1812 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1813 only_standby = true;
2b28bb1b 1814
0e0ae652 1815 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1816 val |= EDP_PSR_LINK_STANDBY;
1817 val |= EDP_PSR_TP2_TP3_TIME_0us;
1818 val |= EDP_PSR_TP1_TIME_0us;
1819 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1820 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1821 } else
1822 val |= EDP_PSR_LINK_DISABLE;
1823
18b5992c 1824 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1825 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1826 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1827 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1828 EDP_PSR_ENABLE);
1829}
1830
3f51e471
RV		 1831static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1832{
1833 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1834 struct drm_device *dev = dig_port->base.base.dev;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
1836 struct drm_crtc *crtc = dig_port->base.base.crtc;
1837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1838
f0355c4a 1839 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1840 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1841 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1842
a031d709
RV		 1843 dev_priv->psr.source_ok = false;
1844
9ca15301 1845 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1846 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1847 return false;
1848 }
1849
d330a953 1850 if (!i915.enable_psr) {
105b7c11 1851 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1852 return false;
1853 }
1854
4c8c7000
RV		 1855 /* Below limitations aren't valid for Broadwell */
1856 if (IS_BROADWELL(dev))
1857 goto out;
1858
3f51e471
RV		 1859 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1860 S3D_ENABLE) {
1861 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1862 return false;
1863 }
1864
ca73b4f0 1865 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1866 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1867 return false;
1868 }
1869
4c8c7000 1870 out:
a031d709 1871 dev_priv->psr.source_ok = true;
3f51e471
RV		 1872 return true;
1873}
1874
3d739d92 1875static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1876{
7c8f8a70
RV		 1877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1878 struct drm_device *dev = intel_dig_port->base.base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1880
3638379c
DV		 1881 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1882 WARN_ON(dev_priv->psr.active);
f0355c4a 1883 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1884
2b28bb1b
RV		 1885 /* Enable PSR on the panel */
1886 intel_edp_psr_enable_sink(intel_dp);
1887
1888 /* Enable PSR on the host */
1889 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1890
7c8f8a70 1891 dev_priv->psr.active = true;
2b28bb1b
RV		 1892}
1893
3d739d92
RV		 1894void intel_edp_psr_enable(struct intel_dp *intel_dp)
1895{
1896 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1897 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1898
4704c573
RV		 1899 if (!HAS_PSR(dev)) {
1900 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1901 return;
1902 }
1903
34eb7579
RV		 1904 if (!is_edp_psr(intel_dp)) {
1905 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1906 return;
1907 }
1908
f0355c4a 1909 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1910 if (dev_priv->psr.enabled) {
1911 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1912 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1913 return;
1914 }
1915
9ca15301
DV		 1916 dev_priv->psr.busy_frontbuffer_bits = 0;
1917
16487254
RV		 1918 /* Setup PSR once */
1919 intel_edp_psr_setup(intel_dp);
1920
7c8f8a70 1921 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1922 dev_priv->psr.enabled = intel_dp;
f0355c4a 1923 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1924}
1925
2b28bb1b
RV		 1926void intel_edp_psr_disable(struct intel_dp *intel_dp)
1927{
1928 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930
f0355c4a
DV		 1931 mutex_lock(&dev_priv->psr.lock);
1932 if (!dev_priv->psr.enabled) {
1933 mutex_unlock(&dev_priv->psr.lock);
1934 return;
1935 }
1936
3638379c
DV		 1937 if (dev_priv->psr.active) {
1938 I915_WRITE(EDP_PSR_CTL(dev),
1939 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1940
1941 /* Wait till PSR is idle */
1942 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1943 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1944 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1945
3638379c
DV		 1946 dev_priv->psr.active = false;
1947 } else {
1948 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1949 }
7c8f8a70 1950
2807cf69 1951 dev_priv->psr.enabled = NULL;
f0355c4a 1952 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1953
1954 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1955}
1956
f02a326e 1957static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1958{
1959 struct drm_i915_private *dev_priv =
1960 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1961 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1962
f0355c4a
DV		 1963 mutex_lock(&dev_priv->psr.lock);
1964 intel_dp = dev_priv->psr.enabled;
1965
2807cf69 1966 if (!intel_dp)
f0355c4a 1967 goto unlock;
2807cf69 1968
9ca15301
DV		 1969 /*
1970 * The delayed work can race with an invalidate hence we need to
1971 * recheck. Since psr_flush first clears this and then reschedules we
1972 * won't ever miss a flush when bailing out here.
1973 */
1974 if (dev_priv->psr.busy_frontbuffer_bits)
1975 goto unlock;
1976
1977 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1978unlock:
1979 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1980}
1981
9ca15301 1982static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1983{
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985
3638379c
DV		 1986 if (dev_priv->psr.active) {
1987 u32 val = I915_READ(EDP_PSR_CTL(dev));
1988
1989 WARN_ON(!(val & EDP_PSR_ENABLE));
1990
1991 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1992
1993 dev_priv->psr.active = false;
1994 }
7c8f8a70 1995
9ca15301
DV		 1996}
1997
1998void intel_edp_psr_invalidate(struct drm_device *dev,
1999 unsigned frontbuffer_bits)
2000{
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct drm_crtc *crtc;
2003 enum pipe pipe;
2004
9ca15301
DV		 2005 mutex_lock(&dev_priv->psr.lock);
2006 if (!dev_priv->psr.enabled) {
2007 mutex_unlock(&dev_priv->psr.lock);
2008 return;
2009 }
2010
2011 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2012 pipe = to_intel_crtc(crtc)->pipe;
2013
2014 intel_edp_psr_do_exit(dev);
2015
2016 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2017
2018 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2019 mutex_unlock(&dev_priv->psr.lock);
2020}
2021
2022void intel_edp_psr_flush(struct drm_device *dev,
2023 unsigned frontbuffer_bits)
2024{
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 struct drm_crtc *crtc;
2027 enum pipe pipe;
2028
9ca15301
DV		 2029 mutex_lock(&dev_priv->psr.lock);
2030 if (!dev_priv->psr.enabled) {
2031 mutex_unlock(&dev_priv->psr.lock);
2032 return;
2033 }
2034
2035 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2036 pipe = to_intel_crtc(crtc)->pipe;
2037 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2038
2039 /*
2040 * On Haswell sprite plane updates don't result in a psr invalidating
2041 * signal in the hardware. Which means we need to manually fake this in
2042 * software for all flushes, not just when we've seen a preceding
2043 * invalidation through frontbuffer rendering.
2044 */
2045 if (IS_HASWELL(dev) &&
2046 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2047 intel_edp_psr_do_exit(dev);
2048
2049 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2050 schedule_delayed_work(&dev_priv->psr.work,
2051 msecs_to_jiffies(100));
f0355c4a 2052 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2053}
2054
2055void intel_edp_psr_init(struct drm_device *dev)
2056{
2057 struct drm_i915_private *dev_priv = dev->dev_private;
2058
7c8f8a70 2059 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2060 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2061}
2062
e8cb4558 2063static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2064{
e8cb4558 2065 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2066 enum port port = dp_to_dig_port(intel_dp)->port;
2067 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2068
2069 /* Make sure the panel is off before trying to change the mode. But also
2070 * ensure that we have vdd while we switch off the panel. */
24f3e092 2071 intel_edp_panel_vdd_on(intel_dp);
4be73780 2072 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2073 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2074 intel_edp_panel_off(intel_dp);
3739850b
DV		 2075
2076 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2077 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2078 intel_dp_link_down(intel_dp);
d240f20f
JB		 2079}
2080
49277c31 2081static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2082{
2bd2ad64 2083 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2084 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2085
49277c31
VS		 2086 if (port != PORT_A)
2087 return;
2088
2089 intel_dp_link_down(intel_dp);
2090 ironlake_edp_pll_off(intel_dp);
2091}
2092
2093static void vlv_post_disable_dp(struct intel_encoder *encoder)
2094{
2095 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2096
2097 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2098}
2099
580d3811
VS		 2100static void chv_post_disable_dp(struct intel_encoder *encoder)
2101{
2102 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2103 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2104 struct drm_device *dev = encoder->base.dev;
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 struct intel_crtc *intel_crtc =
2107 to_intel_crtc(encoder->base.crtc);
2108 enum dpio_channel ch = vlv_dport_to_channel(dport);
2109 enum pipe pipe = intel_crtc->pipe;
2110 u32 val;
2111
2112 intel_dp_link_down(intel_dp);
2113
2114 mutex_lock(&dev_priv->dpio_lock);
2115
2116 /* Propagate soft reset to data lane reset */
97fd4d5c 2117 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2118 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2119 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2120
97fd4d5c
VS		 2121 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2122 val |= CHV_PCS_REQ_SOFTRESET_EN;
2123 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2124
2125 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2126 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2127 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2128
2129 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2130 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2131 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2132
2133 mutex_unlock(&dev_priv->dpio_lock);
2134}
2135
e8cb4558 2136static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2137{
e8cb4558
DV		 2138 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2139 struct drm_device *dev = encoder->base.dev;
2140 struct drm_i915_private *dev_priv = dev->dev_private;
2141 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2142
0c33d8d7
DV		 2143 if (WARN_ON(dp_reg & DP_PORT_EN))
2144 return;
5d613501 2145
24f3e092 2146 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2147 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2148 intel_dp_start_link_train(intel_dp);
4be73780 2149 intel_edp_panel_on(intel_dp);
1e0560e0 2150 intel_edp_panel_vdd_off(intel_dp, true);
33a34e4e 2151 intel_dp_complete_link_train(intel_dp);
3ab9c637 2152 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2153}
89b667f8 2154
ecff4f3b
JN		 2155static void g4x_enable_dp(struct intel_encoder *encoder)
2156{
828f5c6e
JN		 2157 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2158
ecff4f3b 2159 intel_enable_dp(encoder);
4be73780 2160 intel_edp_backlight_on(intel_dp);
ab1f90f9 2161}
89b667f8 2162
ab1f90f9
JN		 2163static void vlv_enable_dp(struct intel_encoder *encoder)
2164{
828f5c6e
JN		 2165 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2166
4be73780 2167 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2168}
2169
ecff4f3b 2170static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2171{
2172 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2173 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2174
8ac33ed3
DV		 2175 intel_dp_prepare(encoder);
2176
d41f1efb
DV		 2177 /* Only ilk+ has port A */
2178 if (dport->port == PORT_A) {
2179 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2180 ironlake_edp_pll_on(intel_dp);
d41f1efb 2181 }
ab1f90f9
JN		 2182}
2183
2184static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2185{
2bd2ad64 2186 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2187 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2188 struct drm_device *dev = encoder->base.dev;
89b667f8 2189 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2190 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2191 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2192 int pipe = intel_crtc->pipe;
bf13e81b 2193 struct edp_power_seq power_seq;
ab1f90f9 2194 u32 val;
a4fc5ed6 2195
ab1f90f9 2196 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2197
ab3c759a 2198 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2199 val = 0;
2200 if (pipe)
2201 val |= (1<<21);
2202 else
2203 val &= ~(1<<21);
2204 val |= 0x001000c4;
ab3c759a
CML		 2205 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2206 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2207 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2208
ab1f90f9
JN		 2209 mutex_unlock(&dev_priv->dpio_lock);
2210
2cac613b
ID		 2211 if (is_edp(intel_dp)) {
2212 /* init power sequencer on this pipe and port */
2213 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2214 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2215 &power_seq);
2216 }
bf13e81b 2217
ab1f90f9
JN		 2218 intel_enable_dp(encoder);
2219
e4607fcf 2220 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2221}
2222
ecff4f3b 2223static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2224{
2225 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2226 struct drm_device *dev = encoder->base.dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2228 struct intel_crtc *intel_crtc =
2229 to_intel_crtc(encoder->base.crtc);
e4607fcf 2230 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2231 int pipe = intel_crtc->pipe;
89b667f8 2232
8ac33ed3
DV		 2233 intel_dp_prepare(encoder);
2234
89b667f8 2235 /* Program Tx lane resets to default */
0980a60f 2236 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2237 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2238 DPIO_PCS_TX_LANE2_RESET |
2239 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2240 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2241 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2242 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2243 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2244 DPIO_PCS_CLK_SOFT_RESET);
2245
2246 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2247 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2248 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2249 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2250 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2251}
2252
e4a1d846
CML		 2253static void chv_pre_enable_dp(struct intel_encoder *encoder)
2254{
2255 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2256 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2257 struct drm_device *dev = encoder->base.dev;
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 struct edp_power_seq power_seq;
2260 struct intel_crtc *intel_crtc =
2261 to_intel_crtc(encoder->base.crtc);
2262 enum dpio_channel ch = vlv_dport_to_channel(dport);
2263 int pipe = intel_crtc->pipe;
2264 int data, i;
949c1d43 2265 u32 val;
e4a1d846 2266
e4a1d846 2267 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2268
2269 /* Deassert soft data lane reset*/
97fd4d5c 2270 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2271 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2272 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2273
2274 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2275 val |= CHV_PCS_REQ_SOFTRESET_EN;
2276 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2277
2278 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2279 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2280 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2281
97fd4d5c 2282 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2283 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2284 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2285
2286 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2287 for (i = 0; i < 4; i++) {
2288 /* Set the latency optimal bit */
2289 data = (i == 1) ? 0x0 : 0x6;
2290 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2291 data << DPIO_FRC_LATENCY_SHFIT);
2292
2293 /* Set the upar bit */
2294 data = (i == 1) ? 0x0 : 0x1;
2295 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2296 data << DPIO_UPAR_SHIFT);
2297 }
2298
2299 /* Data lane stagger programming */
2300 /* FIXME: Fix up value only after power analysis */
2301
2302 mutex_unlock(&dev_priv->dpio_lock);
2303
2304 if (is_edp(intel_dp)) {
2305 /* init power sequencer on this pipe and port */
2306 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2307 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2308 &power_seq);
2309 }
2310
2311 intel_enable_dp(encoder);
2312
2313 vlv_wait_port_ready(dev_priv, dport);
2314}
2315
9197c88b
VS		 2316static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2317{
2318 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2319 struct drm_device *dev = encoder->base.dev;
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2321 struct intel_crtc *intel_crtc =
2322 to_intel_crtc(encoder->base.crtc);
2323 enum dpio_channel ch = vlv_dport_to_channel(dport);
2324 enum pipe pipe = intel_crtc->pipe;
2325 u32 val;
2326
625695f8
VS		 2327 intel_dp_prepare(encoder);
2328
9197c88b
VS		 2329 mutex_lock(&dev_priv->dpio_lock);
2330
b9e5ac3c
VS		 2331 /* program left/right clock distribution */
2332 if (pipe != PIPE_B) {
2333 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2334 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2335 if (ch == DPIO_CH0)
2336 val |= CHV_BUFLEFTENA1_FORCE;
2337 if (ch == DPIO_CH1)
2338 val |= CHV_BUFRIGHTENA1_FORCE;
2339 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2340 } else {
2341 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2342 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2343 if (ch == DPIO_CH0)
2344 val |= CHV_BUFLEFTENA2_FORCE;
2345 if (ch == DPIO_CH1)
2346 val |= CHV_BUFRIGHTENA2_FORCE;
2347 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2348 }
2349
9197c88b
VS		 2350 /* program clock channel usage */
2351 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2352 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2353 if (pipe != PIPE_B)
2354 val &= ~CHV_PCS_USEDCLKCHANNEL;
2355 else
2356 val |= CHV_PCS_USEDCLKCHANNEL;
2357 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2358
2359 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2360 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2361 if (pipe != PIPE_B)
2362 val &= ~CHV_PCS_USEDCLKCHANNEL;
2363 else
2364 val |= CHV_PCS_USEDCLKCHANNEL;
2365 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2366
2367 /*
2368 * This a a bit weird since generally CL
2369 * matches the pipe, but here we need to
2370 * pick the CL based on the port.
2371 */
2372 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2373 if (pipe != PIPE_B)
2374 val &= ~CHV_CMN_USEDCLKCHANNEL;
2375 else
2376 val |= CHV_CMN_USEDCLKCHANNEL;
2377 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2378
2379 mutex_unlock(&dev_priv->dpio_lock);
2380}
2381
a4fc5ed6 2382/*
df0c237d
JB		 2383 * Native read with retry for link status and receiver capability reads for
2384 * cases where the sink may still be asleep.
9d1a1031
JN		 2385 *
2386 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2387 * supposed to retry 3 times per the spec.
a4fc5ed6 2388 */
9d1a1031
JN		 2389static ssize_t
2390intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2391 void *buffer, size_t size)
a4fc5ed6 2392{
9d1a1031
JN		 2393 ssize_t ret;
2394 int i;
61da5fab 2395
61da5fab 2396 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2397 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2398 if (ret == size)
2399 return ret;
61da5fab
JB		 2400 msleep(1);
2401 }
a4fc5ed6 2402
9d1a1031 2403 return ret;
a4fc5ed6
KP		 2404}
2405
2406/*
2407 * Fetch AUX CH registers 0x202 - 0x207 which contain
2408 * link status information
2409 */
2410static bool
93f62dad 2411intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2412{
9d1a1031
JN		 2413 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2414 DP_LANE0_1_STATUS,
2415 link_status,
2416 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2417}
2418
1100244e 2419/* These are source-specific values. */
a4fc5ed6 2420static uint8_t
1a2eb460 2421intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2422{
30add22d 2423 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2424 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2425
9576c27f 2426 if (IS_VALLEYVIEW(dev))
e2fa6fba 2427 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2428 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2429 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2430 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2431 return DP_TRAIN_VOLTAGE_SWING_1200;
2432 else
2433 return DP_TRAIN_VOLTAGE_SWING_800;
2434}
2435
2436static uint8_t
2437intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2438{
30add22d 2439 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2440 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2441
9576c27f 2442 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2443 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2444 case DP_TRAIN_VOLTAGE_SWING_400:
2445 return DP_TRAIN_PRE_EMPHASIS_9_5;
2446 case DP_TRAIN_VOLTAGE_SWING_600:
2447 return DP_TRAIN_PRE_EMPHASIS_6;
2448 case DP_TRAIN_VOLTAGE_SWING_800:
2449 return DP_TRAIN_PRE_EMPHASIS_3_5;
2450 case DP_TRAIN_VOLTAGE_SWING_1200:
2451 default:
2452 return DP_TRAIN_PRE_EMPHASIS_0;
2453 }
e2fa6fba
P		 2454 } else if (IS_VALLEYVIEW(dev)) {
2455 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2456 case DP_TRAIN_VOLTAGE_SWING_400:
2457 return DP_TRAIN_PRE_EMPHASIS_9_5;
2458 case DP_TRAIN_VOLTAGE_SWING_600:
2459 return DP_TRAIN_PRE_EMPHASIS_6;
2460 case DP_TRAIN_VOLTAGE_SWING_800:
2461 return DP_TRAIN_PRE_EMPHASIS_3_5;
2462 case DP_TRAIN_VOLTAGE_SWING_1200:
2463 default:
2464 return DP_TRAIN_PRE_EMPHASIS_0;
2465 }
bc7d38a4 2466 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2467 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2468 case DP_TRAIN_VOLTAGE_SWING_400:
2469 return DP_TRAIN_PRE_EMPHASIS_6;
2470 case DP_TRAIN_VOLTAGE_SWING_600:
2471 case DP_TRAIN_VOLTAGE_SWING_800:
2472 return DP_TRAIN_PRE_EMPHASIS_3_5;
2473 default:
2474 return DP_TRAIN_PRE_EMPHASIS_0;
2475 }
2476 } else {
2477 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2478 case DP_TRAIN_VOLTAGE_SWING_400:
2479 return DP_TRAIN_PRE_EMPHASIS_6;
2480 case DP_TRAIN_VOLTAGE_SWING_600:
2481 return DP_TRAIN_PRE_EMPHASIS_6;
2482 case DP_TRAIN_VOLTAGE_SWING_800:
2483 return DP_TRAIN_PRE_EMPHASIS_3_5;
2484 case DP_TRAIN_VOLTAGE_SWING_1200:
2485 default:
2486 return DP_TRAIN_PRE_EMPHASIS_0;
2487 }
a4fc5ed6
KP		 2488 }
2489}
2490
e2fa6fba
P		 2491static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2492{
2493 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2494 struct drm_i915_private *dev_priv = dev->dev_private;
2495 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2496 struct intel_crtc *intel_crtc =
2497 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2498 unsigned long demph_reg_value, preemph_reg_value,
2499 uniqtranscale_reg_value;
2500 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2501 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2502 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2503
2504 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2505 case DP_TRAIN_PRE_EMPHASIS_0:
2506 preemph_reg_value = 0x0004000;
2507 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2508 case DP_TRAIN_VOLTAGE_SWING_400:
2509 demph_reg_value = 0x2B405555;
2510 uniqtranscale_reg_value = 0x552AB83A;
2511 break;
2512 case DP_TRAIN_VOLTAGE_SWING_600:
2513 demph_reg_value = 0x2B404040;
2514 uniqtranscale_reg_value = 0x5548B83A;
2515 break;
2516 case DP_TRAIN_VOLTAGE_SWING_800:
2517 demph_reg_value = 0x2B245555;
2518 uniqtranscale_reg_value = 0x5560B83A;
2519 break;
2520 case DP_TRAIN_VOLTAGE_SWING_1200:
2521 demph_reg_value = 0x2B405555;
2522 uniqtranscale_reg_value = 0x5598DA3A;
2523 break;
2524 default:
2525 return 0;
2526 }
2527 break;
2528 case DP_TRAIN_PRE_EMPHASIS_3_5:
2529 preemph_reg_value = 0x0002000;
2530 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2531 case DP_TRAIN_VOLTAGE_SWING_400:
2532 demph_reg_value = 0x2B404040;
2533 uniqtranscale_reg_value = 0x5552B83A;
2534 break;
2535 case DP_TRAIN_VOLTAGE_SWING_600:
2536 demph_reg_value = 0x2B404848;
2537 uniqtranscale_reg_value = 0x5580B83A;
2538 break;
2539 case DP_TRAIN_VOLTAGE_SWING_800:
2540 demph_reg_value = 0x2B404040;
2541 uniqtranscale_reg_value = 0x55ADDA3A;
2542 break;
2543 default:
2544 return 0;
2545 }
2546 break;
2547 case DP_TRAIN_PRE_EMPHASIS_6:
2548 preemph_reg_value = 0x0000000;
2549 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2550 case DP_TRAIN_VOLTAGE_SWING_400:
2551 demph_reg_value = 0x2B305555;
2552 uniqtranscale_reg_value = 0x5570B83A;
2553 break;
2554 case DP_TRAIN_VOLTAGE_SWING_600:
2555 demph_reg_value = 0x2B2B4040;
2556 uniqtranscale_reg_value = 0x55ADDA3A;
2557 break;
2558 default:
2559 return 0;
2560 }
2561 break;
2562 case DP_TRAIN_PRE_EMPHASIS_9_5:
2563 preemph_reg_value = 0x0006000;
2564 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2565 case DP_TRAIN_VOLTAGE_SWING_400:
2566 demph_reg_value = 0x1B405555;
2567 uniqtranscale_reg_value = 0x55ADDA3A;
2568 break;
2569 default:
2570 return 0;
2571 }
2572 break;
2573 default:
2574 return 0;
2575 }
2576
0980a60f 2577 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2578 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2579 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2580 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2581 uniqtranscale_reg_value);
ab3c759a
CML		 2582 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2583 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2584 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2585 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2586 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2587
2588 return 0;
2589}
2590
e4a1d846
CML		 2591static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2592{
2593 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2596 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2597 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2598 uint8_t train_set = intel_dp->train_set[0];
2599 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2600 enum pipe pipe = intel_crtc->pipe;
2601 int i;
e4a1d846
CML		 2602
2603 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2604 case DP_TRAIN_PRE_EMPHASIS_0:
2605 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2606 case DP_TRAIN_VOLTAGE_SWING_400:
2607 deemph_reg_value = 128;
2608 margin_reg_value = 52;
2609 break;
2610 case DP_TRAIN_VOLTAGE_SWING_600:
2611 deemph_reg_value = 128;
2612 margin_reg_value = 77;
2613 break;
2614 case DP_TRAIN_VOLTAGE_SWING_800:
2615 deemph_reg_value = 128;
2616 margin_reg_value = 102;
2617 break;
2618 case DP_TRAIN_VOLTAGE_SWING_1200:
2619 deemph_reg_value = 128;
2620 margin_reg_value = 154;
2621 /* FIXME extra to set for 1200 */
2622 break;
2623 default:
2624 return 0;
2625 }
2626 break;
2627 case DP_TRAIN_PRE_EMPHASIS_3_5:
2628 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2629 case DP_TRAIN_VOLTAGE_SWING_400:
2630 deemph_reg_value = 85;
2631 margin_reg_value = 78;
2632 break;
2633 case DP_TRAIN_VOLTAGE_SWING_600:
2634 deemph_reg_value = 85;
2635 margin_reg_value = 116;
2636 break;
2637 case DP_TRAIN_VOLTAGE_SWING_800:
2638 deemph_reg_value = 85;
2639 margin_reg_value = 154;
2640 break;
2641 default:
2642 return 0;
2643 }
2644 break;
2645 case DP_TRAIN_PRE_EMPHASIS_6:
2646 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2647 case DP_TRAIN_VOLTAGE_SWING_400:
2648 deemph_reg_value = 64;
2649 margin_reg_value = 104;
2650 break;
2651 case DP_TRAIN_VOLTAGE_SWING_600:
2652 deemph_reg_value = 64;
2653 margin_reg_value = 154;
2654 break;
2655 default:
2656 return 0;
2657 }
2658 break;
2659 case DP_TRAIN_PRE_EMPHASIS_9_5:
2660 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2661 case DP_TRAIN_VOLTAGE_SWING_400:
2662 deemph_reg_value = 43;
2663 margin_reg_value = 154;
2664 break;
2665 default:
2666 return 0;
2667 }
2668 break;
2669 default:
2670 return 0;
2671 }
2672
2673 mutex_lock(&dev_priv->dpio_lock);
2674
2675 /* Clear calc init */
1966e59e
VS		 2676 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2677 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2678 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2679
2680 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2681 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2682 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2683
2684 /* Program swing deemph */
f72df8db
VS		 2685 for (i = 0; i < 4; i++) {
2686 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2687 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2688 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2689 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2690 }
e4a1d846
CML		 2691
2692 /* Program swing margin */
f72df8db
VS		 2693 for (i = 0; i < 4; i++) {
2694 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2695 val &= ~DPIO_SWING_MARGIN000_MASK;
2696 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2697 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2698 }
e4a1d846
CML		 2699
2700 /* Disable unique transition scale */
f72df8db
VS		 2701 for (i = 0; i < 4; i++) {
2702 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2703 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2704 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2705 }
e4a1d846
CML		 2706
2707 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2708 == DP_TRAIN_PRE_EMPHASIS_0) &&
2709 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2710 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2711
2712 /*
2713 * The document said it needs to set bit 27 for ch0 and bit 26
2714 * for ch1. Might be a typo in the doc.
2715 * For now, for this unique transition scale selection, set bit
2716 * 27 for ch0 and ch1.
2717 */
f72df8db
VS		 2718 for (i = 0; i < 4; i++) {
2719 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2720 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2721 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2722 }
e4a1d846 2723
f72df8db
VS		 2724 for (i = 0; i < 4; i++) {
2725 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2726 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2727 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2728 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2729 }
e4a1d846
CML		 2730 }
2731
2732 /* Start swing calculation */
1966e59e
VS		 2733 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2734 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2735 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2736
2737 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2738 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2739 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2740
2741 /* LRC Bypass */
2742 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2743 val |= DPIO_LRC_BYPASS;
2744 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2745
2746 mutex_unlock(&dev_priv->dpio_lock);
2747
2748 return 0;
2749}
2750
a4fc5ed6 2751static void
0301b3ac
JN		 2752intel_get_adjust_train(struct intel_dp *intel_dp,
2753 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2754{
2755 uint8_t v = 0;
2756 uint8_t p = 0;
2757 int lane;
1a2eb460
KP		 2758 uint8_t voltage_max;
2759 uint8_t preemph_max;
a4fc5ed6 2760
33a34e4e 2761 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2762 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2763 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2764
2765 if (this_v > v)
2766 v = this_v;
2767 if (this_p > p)
2768 p = this_p;
2769 }
2770
1a2eb460 2771 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2772 if (v >= voltage_max)
2773 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2774
1a2eb460
KP		 2775 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2776 if (p >= preemph_max)
2777 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2778
2779 for (lane = 0; lane < 4; lane++)
33a34e4e 2780 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2781}
2782
2783static uint32_t
f0a3424e 2784intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2785{
3cf2efb1 2786 uint32_t signal_levels = 0;
a4fc5ed6 2787
3cf2efb1 2788 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2789 case DP_TRAIN_VOLTAGE_SWING_400:
2790 default:
2791 signal_levels |= DP_VOLTAGE_0_4;
2792 break;
2793 case DP_TRAIN_VOLTAGE_SWING_600:
2794 signal_levels |= DP_VOLTAGE_0_6;
2795 break;
2796 case DP_TRAIN_VOLTAGE_SWING_800:
2797 signal_levels |= DP_VOLTAGE_0_8;
2798 break;
2799 case DP_TRAIN_VOLTAGE_SWING_1200:
2800 signal_levels |= DP_VOLTAGE_1_2;
2801 break;
2802 }
3cf2efb1 2803 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2804 case DP_TRAIN_PRE_EMPHASIS_0:
2805 default:
2806 signal_levels |= DP_PRE_EMPHASIS_0;
2807 break;
2808 case DP_TRAIN_PRE_EMPHASIS_3_5:
2809 signal_levels |= DP_PRE_EMPHASIS_3_5;
2810 break;
2811 case DP_TRAIN_PRE_EMPHASIS_6:
2812 signal_levels |= DP_PRE_EMPHASIS_6;
2813 break;
2814 case DP_TRAIN_PRE_EMPHASIS_9_5:
2815 signal_levels |= DP_PRE_EMPHASIS_9_5;
2816 break;
2817 }
2818 return signal_levels;
2819}
2820
e3421a18
ZW		 2821/* Gen6's DP voltage swing and pre-emphasis control */
2822static uint32_t
2823intel_gen6_edp_signal_levels(uint8_t train_set)
2824{
3c5a62b5
YL		 2825 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2826 DP_TRAIN_PRE_EMPHASIS_MASK);
2827 switch (signal_levels) {
e3421a18 2828 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2829 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2830 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2831 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2832 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2833 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2834 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2835 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2836 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2837 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2838 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2839 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2840 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2841 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2842 default:
3c5a62b5
YL		 2843 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2844 "0x%x\n", signal_levels);
2845 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2846 }
2847}
2848
1a2eb460
KP		 2849/* Gen7's DP voltage swing and pre-emphasis control */
2850static uint32_t
2851intel_gen7_edp_signal_levels(uint8_t train_set)
2852{
2853 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2854 DP_TRAIN_PRE_EMPHASIS_MASK);
2855 switch (signal_levels) {
2856 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2857 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2858 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2859 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2860 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2861 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2862
2863 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2864 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2865 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2866 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2867
2868 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2869 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2870 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2871 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2872
2873 default:
2874 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2875 "0x%x\n", signal_levels);
2876 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2877 }
2878}
2879
d6c0d722
PZ		 2880/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2881static uint32_t
f0a3424e 2882intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2883{
d6c0d722
PZ		 2884 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2885 DP_TRAIN_PRE_EMPHASIS_MASK);
2886 switch (signal_levels) {
2887 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2888 return DDI_BUF_EMP_400MV_0DB_HSW;
2889 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2890 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2891 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2892 return DDI_BUF_EMP_400MV_6DB_HSW;
2893 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2894 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2895
d6c0d722
PZ		 2896 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2897 return DDI_BUF_EMP_600MV_0DB_HSW;
2898 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2899 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2900 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2901 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2902
d6c0d722
PZ		 2903 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2904 return DDI_BUF_EMP_800MV_0DB_HSW;
2905 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2906 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2907 default:
2908 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2909 "0x%x\n", signal_levels);
2910 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2911 }
a4fc5ed6
KP		 2912}
2913
f0a3424e
PZ		 2914/* Properly updates "DP" with the correct signal levels. */
2915static void
2916intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2917{
2918 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2919 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2920 struct drm_device *dev = intel_dig_port->base.base.dev;
2921 uint32_t signal_levels, mask;
2922 uint8_t train_set = intel_dp->train_set[0];
2923
9576c27f 2924 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2925 signal_levels = intel_hsw_signal_levels(train_set);
2926 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2927 } else if (IS_CHERRYVIEW(dev)) {
2928 signal_levels = intel_chv_signal_levels(intel_dp);
2929 mask = 0;
e2fa6fba
P		 2930 } else if (IS_VALLEYVIEW(dev)) {
2931 signal_levels = intel_vlv_signal_levels(intel_dp);
2932 mask = 0;
bc7d38a4 2933 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2934 signal_levels = intel_gen7_edp_signal_levels(train_set);
2935 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2936 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2937 signal_levels = intel_gen6_edp_signal_levels(train_set);
2938 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2939 } else {
2940 signal_levels = intel_gen4_signal_levels(train_set);
2941 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2942 }
2943
2944 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2945
2946 *DP = (*DP & ~mask) | signal_levels;
2947}
2948
a4fc5ed6 2949static bool
ea5b213a 2950intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2951 uint32_t *DP,
58e10eb9 2952 uint8_t dp_train_pat)
a4fc5ed6 2953{
174edf1f
PZ		 2954 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2955 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2956 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2957 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2958 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2959 int ret, len;
a4fc5ed6 2960
22b8bf17 2961 if (HAS_DDI(dev)) {
3ab9c637 2962 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2963
2964 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2965 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2966 else
2967 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2968
2969 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2970 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2971 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2972 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2973
2974 break;
2975 case DP_TRAINING_PATTERN_1:
2976 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2977 break;
2978 case DP_TRAINING_PATTERN_2:
2979 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2980 break;
2981 case DP_TRAINING_PATTERN_3:
2982 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2983 break;
2984 }
174edf1f 2985 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2986
bc7d38a4 2987 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2988 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2989
2990 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2991 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2992 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2993 break;
2994 case DP_TRAINING_PATTERN_1:
70aff66c 2995 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2996 break;
2997 case DP_TRAINING_PATTERN_2:
70aff66c 2998 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2999 break;
3000 case DP_TRAINING_PATTERN_3:
3001 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 3002 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3003 break;
3004 }
3005
3006 } else {
aad3d14d
VS		 3007 if (IS_CHERRYVIEW(dev))
3008 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3009 else
3010 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 3011
3012 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3013 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3014 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 3015 break;
3016 case DP_TRAINING_PATTERN_1:
70aff66c 3017 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 3018 break;
3019 case DP_TRAINING_PATTERN_2:
70aff66c 3020 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 3021 break;
3022 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 3023 if (IS_CHERRYVIEW(dev)) {
3024 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3025 } else {
3026 DRM_ERROR("DP training pattern 3 not supported\n");
3027 *DP |= DP_LINK_TRAIN_PAT_2;
3028 }
47ea7542
PZ		 3029 break;
3030 }
3031 }
3032
70aff66c 3033 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3034 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3035
2cdfe6c8
JN		 3036 buf[0] = dp_train_pat;
3037 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3038 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3039 /* don't write DP_TRAINING_LANEx_SET on disable */
3040 len = 1;
3041 } else {
3042 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3043 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3044 len = intel_dp->lane_count + 1;
47ea7542 3045 }
a4fc5ed6 3046
9d1a1031
JN		 3047 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3048 buf, len);
2cdfe6c8
JN		 3049
3050 return ret == len;
a4fc5ed6
KP		 3051}
3052
70aff66c
JN		 3053static bool
3054intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3055 uint8_t dp_train_pat)
3056{
953d22e8 3057 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3058 intel_dp_set_signal_levels(intel_dp, DP);
3059 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3060}
3061
3062static bool
3063intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3064 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3065{
3066 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3067 struct drm_device *dev = intel_dig_port->base.base.dev;
3068 struct drm_i915_private *dev_priv = dev->dev_private;
3069 int ret;
3070
3071 intel_get_adjust_train(intel_dp, link_status);
3072 intel_dp_set_signal_levels(intel_dp, DP);
3073
3074 I915_WRITE(intel_dp->output_reg, *DP);
3075 POSTING_READ(intel_dp->output_reg);
3076
9d1a1031
JN		 3077 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3078 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3079
3080 return ret == intel_dp->lane_count;
3081}
3082
3ab9c637
ID		 3083static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3084{
3085 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3086 struct drm_device *dev = intel_dig_port->base.base.dev;
3087 struct drm_i915_private *dev_priv = dev->dev_private;
3088 enum port port = intel_dig_port->port;
3089 uint32_t val;
3090
3091 if (!HAS_DDI(dev))
3092 return;
3093
3094 val = I915_READ(DP_TP_CTL(port));
3095 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3096 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3097 I915_WRITE(DP_TP_CTL(port), val);
3098
3099 /*
3100 * On PORT_A we can have only eDP in SST mode. There the only reason
3101 * we need to set idle transmission mode is to work around a HW issue
3102 * where we enable the pipe while not in idle link-training mode.
3103 * In this case there is requirement to wait for a minimum number of
3104 * idle patterns to be sent.
3105 */
3106 if (port == PORT_A)
3107 return;
3108
3109 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3110 1))
3111 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3112}
3113
33a34e4e 3114/* Enable corresponding port and start training pattern 1 */
c19b0669 3115void
33a34e4e 3116intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3117{
da63a9f2 3118 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3119 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3120 int i;
3121 uint8_t voltage;
cdb0e95b 3122 int voltage_tries, loop_tries;
ea5b213a 3123 uint32_t DP = intel_dp->DP;
6aba5b6c 3124 uint8_t link_config[2];
a4fc5ed6 3125
affa9354 3126 if (HAS_DDI(dev))
c19b0669
PZ		 3127 intel_ddi_prepare_link_retrain(encoder);
3128
3cf2efb1 3129 /* Write the link configuration data */
6aba5b6c
JN		 3130 link_config[0] = intel_dp->link_bw;
3131 link_config[1] = intel_dp->lane_count;
3132 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3133 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3134 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3135
3136 link_config[0] = 0;
3137 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3138 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3139
3140 DP |= DP_PORT_EN;
1a2eb460 3141
70aff66c
JN		 3142 /* clock recovery */
3143 if (!intel_dp_reset_link_train(intel_dp, &DP,
3144 DP_TRAINING_PATTERN_1 |
3145 DP_LINK_SCRAMBLING_DISABLE)) {
3146 DRM_ERROR("failed to enable link training\n");
3147 return;
3148 }
3149
a4fc5ed6 3150 voltage = 0xff;
cdb0e95b
KP		 3151 voltage_tries = 0;
3152 loop_tries = 0;
a4fc5ed6 3153 for (;;) {
70aff66c 3154 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3155
a7c9655f 3156 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3157 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3158 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3159 break;
93f62dad 3160 }
a4fc5ed6 3161
01916270 3162 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3163 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3164 break;
3165 }
3166
3167 /* Check to see if we've tried the max voltage */
3168 for (i = 0; i < intel_dp->lane_count; i++)
3169 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3170 break;
3b4f819d 3171 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3172 ++loop_tries;
3173 if (loop_tries == 5) {
3def84b3 3174 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3175 break;
3176 }
70aff66c
JN		 3177 intel_dp_reset_link_train(intel_dp, &DP,
3178 DP_TRAINING_PATTERN_1 |
3179 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3180 voltage_tries = 0;
3181 continue;
3182 }
a4fc5ed6 3183
3cf2efb1 3184 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3185 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3186 ++voltage_tries;
b06fbda3 3187 if (voltage_tries == 5) {
3def84b3 3188 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3189 break;
3190 }
3191 } else
3192 voltage_tries = 0;
3193 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3194
70aff66c
JN		 3195 /* Update training set as requested by target */
3196 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3197 DRM_ERROR("failed to update link training\n");
3198 break;
3199 }
a4fc5ed6
KP		 3200 }
3201
33a34e4e
JB		 3202 intel_dp->DP = DP;
3203}
3204
c19b0669 3205void
33a34e4e
JB		 3206intel_dp_complete_link_train(struct intel_dp *intel_dp)
3207{
33a34e4e 3208 bool channel_eq = false;
37f80975 3209 int tries, cr_tries;
33a34e4e 3210 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3211 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3212
3213 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3214 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3215 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3216
a4fc5ed6 3217 /* channel equalization */
70aff66c 3218 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3219 training_pattern |
70aff66c
JN		 3220 DP_LINK_SCRAMBLING_DISABLE)) {
3221 DRM_ERROR("failed to start channel equalization\n");
3222 return;
3223 }
3224
a4fc5ed6 3225 tries = 0;
37f80975 3226 cr_tries = 0;
a4fc5ed6
KP		 3227 channel_eq = false;
3228 for (;;) {
70aff66c 3229 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3230
37f80975
JB		 3231 if (cr_tries > 5) {
3232 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3233 break;
3234 }
3235
a7c9655f 3236 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3237 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3238 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3239 break;
70aff66c 3240 }
a4fc5ed6 3241
37f80975 3242 /* Make sure clock is still ok */
01916270 3243 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3244 intel_dp_start_link_train(intel_dp);
70aff66c 3245 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3246 training_pattern |
70aff66c 3247 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3248 cr_tries++;
3249 continue;
3250 }
3251
1ffdff13 3252 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3253 channel_eq = true;
3254 break;
3255 }
a4fc5ed6 3256
37f80975
JB		 3257 /* Try 5 times, then try clock recovery if that fails */
3258 if (tries > 5) {
3259 intel_dp_link_down(intel_dp);
3260 intel_dp_start_link_train(intel_dp);
70aff66c 3261 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3262 training_pattern |
70aff66c 3263 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3264 tries = 0;
3265 cr_tries++;
3266 continue;
3267 }
a4fc5ed6 3268
70aff66c
JN		 3269 /* Update training set as requested by target */
3270 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3271 DRM_ERROR("failed to update link training\n");
3272 break;
3273 }
3cf2efb1 3274 ++tries;
869184a6 3275 }
3cf2efb1 3276
3ab9c637
ID		 3277 intel_dp_set_idle_link_train(intel_dp);
3278
3279 intel_dp->DP = DP;
3280
d6c0d722 3281 if (channel_eq)
07f42258 3282 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3283
3ab9c637
ID		 3284}
3285
3286void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3287{
70aff66c 3288 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3289 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3290}
3291
3292static void
ea5b213a 3293intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3294{
da63a9f2 3295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3296 enum port port = intel_dig_port->port;
da63a9f2 3297 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3298 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3299 struct intel_crtc *intel_crtc =
3300 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3301 uint32_t DP = intel_dp->DP;
a4fc5ed6 3302
bc76e320 3303 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3304 return;
3305
0c33d8d7 3306 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3307 return;
3308
28c97730 3309 DRM_DEBUG_KMS("\n");
32f9d658 3310
bc7d38a4 3311 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3312 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3313 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3314 } else {
aad3d14d
VS		 3315 if (IS_CHERRYVIEW(dev))
3316 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3317 else
3318 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3319 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3320 }
fe255d00 3321 POSTING_READ(intel_dp->output_reg);
5eb08b69 3322
493a7081 3323 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3324 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3325 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3326
5bddd17f
EA		 3327 /* Hardware workaround: leaving our transcoder select
3328 * set to transcoder B while it's off will prevent the
3329 * corresponding HDMI output on transcoder A.
3330 *
3331 * Combine this with another hardware workaround:
3332 * transcoder select bit can only be cleared while the
3333 * port is enabled.
3334 */
3335 DP &= ~DP_PIPEB_SELECT;
3336 I915_WRITE(intel_dp->output_reg, DP);
3337
3338 /* Changes to enable or select take place the vblank
3339 * after being written.
3340 */
ff50afe9
DV		 3341 if (WARN_ON(crtc == NULL)) {
3342 /* We should never try to disable a port without a crtc
3343 * attached. For paranoia keep the code around for a
3344 * bit. */
31acbcc4
CW		 3345 POSTING_READ(intel_dp->output_reg);
3346 msleep(50);
3347 } else
ab527efc 3348 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3349 }
3350
832afda6 3351 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3352 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3353 POSTING_READ(intel_dp->output_reg);
f01eca2e 3354 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3355}
3356
26d61aad
KP		 3357static bool
3358intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3359{
a031d709
RV		 3360 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3361 struct drm_device *dev = dig_port->base.base.dev;
3362 struct drm_i915_private *dev_priv = dev->dev_private;
3363
577c7a50
DL		 3364 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3365
9d1a1031
JN		 3366 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3367 sizeof(intel_dp->dpcd)) < 0)
edb39244 3368 return false; /* aux transfer failed */
92fd8fd1 3369
577c7a50
DL		 3370 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3371 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3372 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3373
edb39244
AJ		 3374 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3375 return false; /* DPCD not present */
3376
2293bb5c
SK		 3377 /* Check if the panel supports PSR */
3378 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3379 if (is_edp(intel_dp)) {
9d1a1031
JN		 3380 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3381 intel_dp->psr_dpcd,
3382 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3383 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3384 dev_priv->psr.sink_support = true;
50003939 3385 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3386 }
50003939
JN		 3387 }
3388
06ea66b6
TP		 3389 /* Training Pattern 3 support */
3390 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3391 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3392 intel_dp->use_tps3 = true;
3393 DRM_DEBUG_KMS("Displayport TPS3 supported");
3394 } else
3395 intel_dp->use_tps3 = false;
3396
edb39244
AJ		 3397 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3398 DP_DWN_STRM_PORT_PRESENT))
3399 return true; /* native DP sink */
3400
3401 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3402 return true; /* no per-port downstream info */
3403
9d1a1031
JN		 3404 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3405 intel_dp->downstream_ports,
3406 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3407 return false; /* downstream port status fetch failed */
3408
3409 return true;
92fd8fd1
KP		 3410}
3411
0d198328
AJ		 3412static void
3413intel_dp_probe_oui(struct intel_dp *intel_dp)
3414{
3415 u8 buf[3];
3416
3417 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3418 return;
3419
24f3e092 3420 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3421
9d1a1031 3422 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3423 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3424 buf[0], buf[1], buf[2]);
3425
9d1a1031 3426 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3427 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3428 buf[0], buf[1], buf[2]);
351cfc34 3429
1e0560e0 3430 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3431}
3432
0e32b39c
DA		 3433static bool
3434intel_dp_probe_mst(struct intel_dp *intel_dp)
3435{
3436 u8 buf[1];
3437
3438 if (!intel_dp->can_mst)
3439 return false;
3440
3441 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3442 return false;
3443
d337a341 3444 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3445 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3446 if (buf[0] & DP_MST_CAP) {
3447 DRM_DEBUG_KMS("Sink is MST capable\n");
3448 intel_dp->is_mst = true;
3449 } else {
3450 DRM_DEBUG_KMS("Sink is not MST capable\n");
3451 intel_dp->is_mst = false;
3452 }
3453 }
1e0560e0 3454 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3455
3456 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3457 return intel_dp->is_mst;
3458}
3459
d2e216d0
RV		 3460int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3461{
3462 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3463 struct drm_device *dev = intel_dig_port->base.base.dev;
3464 struct intel_crtc *intel_crtc =
3465 to_intel_crtc(intel_dig_port->base.base.crtc);
3466 u8 buf[1];
3467
9d1a1031 3468 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3469 return -EAGAIN;
3470
3471 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3472 return -ENOTTY;
3473
9d1a1031
JN		 3474 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3475 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3476 return -EAGAIN;
3477
3478 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3479 intel_wait_for_vblank(dev, intel_crtc->pipe);
3480 intel_wait_for_vblank(dev, intel_crtc->pipe);
3481
9d1a1031 3482 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3483 return -EAGAIN;
3484
9d1a1031 3485 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3486 return 0;
3487}
3488
a60f0e38
JB		 3489static bool
3490intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3491{
9d1a1031
JN		 3492 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3493 DP_DEVICE_SERVICE_IRQ_VECTOR,
3494 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3495}
3496
0e32b39c
DA		 3497static bool
3498intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3499{
3500 int ret;
3501
3502 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3503 DP_SINK_COUNT_ESI,
3504 sink_irq_vector, 14);
3505 if (ret != 14)
3506 return false;
3507
3508 return true;
3509}
3510
a60f0e38
JB		 3511static void
3512intel_dp_handle_test_request(struct intel_dp *intel_dp)
3513{
3514 /* NAK by default */
9d1a1031 3515 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3516}
3517
0e32b39c
DA		 3518static int
3519intel_dp_check_mst_status(struct intel_dp *intel_dp)
3520{
3521 bool bret;
3522
3523 if (intel_dp->is_mst) {
3524 u8 esi[16] = { 0 };
3525 int ret = 0;
3526 int retry;
3527 bool handled;
3528 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3529go_again:
3530 if (bret == true) {
3531
3532 /* check link status - esi[10] = 0x200c */
3533 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3534 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3535 intel_dp_start_link_train(intel_dp);
3536 intel_dp_complete_link_train(intel_dp);
3537 intel_dp_stop_link_train(intel_dp);
3538 }
3539
3540 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3541 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3542
3543 if (handled) {
3544 for (retry = 0; retry < 3; retry++) {
3545 int wret;
3546 wret = drm_dp_dpcd_write(&intel_dp->aux,
3547 DP_SINK_COUNT_ESI+1,
3548 &esi[1], 3);
3549 if (wret == 3) {
3550 break;
3551 }
3552 }
3553
3554 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3555 if (bret == true) {
3556 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3557 goto go_again;
3558 }
3559 } else
3560 ret = 0;
3561
3562 return ret;
3563 } else {
3564 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3565 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3566 intel_dp->is_mst = false;
3567 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3568 /* send a hotplug event */
3569 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3570 }
3571 }
3572 return -EINVAL;
3573}
3574
a4fc5ed6
KP		 3575/*
3576 * According to DP spec
3577 * 5.1.2:
3578 * 1. Read DPCD
3579 * 2. Configure link according to Receiver Capabilities
3580 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3581 * 4. Check link status on receipt of hot-plug interrupt
3582 */
00c09d70 3583void
ea5b213a 3584intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3585{
5b215bcf 3586 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3587 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3588 u8 sink_irq_vector;
93f62dad 3589 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3590
5b215bcf
DA		 3591 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3592
da63a9f2 3593 if (!intel_encoder->connectors_active)
d2b996ac 3594 return;
59cd09e1 3595
da63a9f2 3596 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3597 return;
3598
1a125d8a
ID		 3599 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3600 return;
3601
92fd8fd1 3602 /* Try to read receiver status if the link appears to be up */
93f62dad 3603 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3604 return;
3605 }
3606
92fd8fd1 3607 /* Now read the DPCD to see if it's actually running */
26d61aad 3608 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3609 return;
3610 }
3611
a60f0e38
JB		 3612 /* Try to read the source of the interrupt */
3613 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3614 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3615 /* Clear interrupt source */
9d1a1031
JN		 3616 drm_dp_dpcd_writeb(&intel_dp->aux,
3617 DP_DEVICE_SERVICE_IRQ_VECTOR,
3618 sink_irq_vector);
a60f0e38
JB		 3619
3620 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3621 intel_dp_handle_test_request(intel_dp);
3622 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3623 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3624 }
3625
1ffdff13 3626 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3627 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3628 intel_encoder->base.name);
33a34e4e
JB		 3629 intel_dp_start_link_train(intel_dp);
3630 intel_dp_complete_link_train(intel_dp);
3ab9c637 3631 intel_dp_stop_link_train(intel_dp);
33a34e4e 3632 }
a4fc5ed6 3633}
a4fc5ed6 3634
caf9ab24 3635/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3636static enum drm_connector_status
26d61aad 3637intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3638{
caf9ab24 3639 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3640 uint8_t type;
3641
3642 if (!intel_dp_get_dpcd(intel_dp))
3643 return connector_status_disconnected;
3644
3645 /* if there's no downstream port, we're done */
3646 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3647 return connector_status_connected;
caf9ab24
AJ		 3648
3649 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3650 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3651 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3652 uint8_t reg;
9d1a1031
JN		 3653
3654 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3655 &reg, 1) < 0)
caf9ab24 3656 return connector_status_unknown;
9d1a1031 3657
23235177
AJ		 3658 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3659 : connector_status_disconnected;
caf9ab24
AJ		 3660 }
3661
3662 /* If no HPD, poke DDC gently */
0b99836f 3663 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3664 return connector_status_connected;
caf9ab24
AJ		 3665
3666 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3667 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3668 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3669 if (type == DP_DS_PORT_TYPE_VGA ||
3670 type == DP_DS_PORT_TYPE_NON_EDID)
3671 return connector_status_unknown;
3672 } else {
3673 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3674 DP_DWN_STRM_PORT_TYPE_MASK;
3675 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3676 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3677 return connector_status_unknown;
3678 }
caf9ab24
AJ		 3679
3680 /* Anything else is out of spec, warn and ignore */
3681 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3682 return connector_status_disconnected;
71ba9000
AJ		 3683}
3684
5eb08b69 3685static enum drm_connector_status
a9756bb5 3686ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3687{
30add22d 3688 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3691 enum drm_connector_status status;
3692
fe16d949
CW		 3693 /* Can't disconnect eDP, but you can close the lid... */
3694 if (is_edp(intel_dp)) {
30add22d 3695 status = intel_panel_detect(dev);
fe16d949
CW		 3696 if (status == connector_status_unknown)
3697 status = connector_status_connected;
3698 return status;
3699 }
01cb9ea6 3700
1b469639
DL		 3701 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3702 return connector_status_disconnected;
3703
26d61aad 3704 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3705}
3706
a4fc5ed6 3707static enum drm_connector_status
a9756bb5 3708g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3709{
30add22d 3710 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3711 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3712 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3713 uint32_t bit;
5eb08b69 3714
35aad75f
JB		 3715 /* Can't disconnect eDP, but you can close the lid... */
3716 if (is_edp(intel_dp)) {
3717 enum drm_connector_status status;
3718
3719 status = intel_panel_detect(dev);
3720 if (status == connector_status_unknown)
3721 status = connector_status_connected;
3722 return status;
3723 }
3724
232a6ee9
TP		 3725 if (IS_VALLEYVIEW(dev)) {
3726 switch (intel_dig_port->port) {
3727 case PORT_B:
3728 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3729 break;
3730 case PORT_C:
3731 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3732 break;
3733 case PORT_D:
3734 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3735 break;
3736 default:
3737 return connector_status_unknown;
3738 }
3739 } else {
3740 switch (intel_dig_port->port) {
3741 case PORT_B:
3742 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3743 break;
3744 case PORT_C:
3745 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3746 break;
3747 case PORT_D:
3748 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3749 break;
3750 default:
3751 return connector_status_unknown;
3752 }
a4fc5ed6
KP		 3753 }
3754
10f76a38 3755 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3756 return connector_status_disconnected;
3757
26d61aad 3758 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3759}
3760
8c241fef
KP		 3761static struct edid *
3762intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3763{
9cd300e0 3764 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3765
9cd300e0
JN		 3766 /* use cached edid if we have one */
3767 if (intel_connector->edid) {
9cd300e0
JN		 3768 /* invalid edid */
3769 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3770 return NULL;
3771
55e9edeb 3772 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3773 }
8c241fef 3774
9cd300e0 3775 return drm_get_edid(connector, adapter);
8c241fef
KP		 3776}
3777
3778static int
3779intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3780{
9cd300e0 3781 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3782
9cd300e0
JN		 3783 /* use cached edid if we have one */
3784 if (intel_connector->edid) {
3785 /* invalid edid */
3786 if (IS_ERR(intel_connector->edid))
3787 return 0;
3788
3789 return intel_connector_update_modes(connector,
3790 intel_connector->edid);
d6f24d0f
JB		 3791 }
3792
9cd300e0 3793 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3794}
3795
a9756bb5
ZW		 3796static enum drm_connector_status
3797intel_dp_detect(struct drm_connector *connector, bool force)
3798{
3799 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3800 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3801 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3802 struct drm_device *dev = connector->dev;
c8c8fb33 3803 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3804 enum drm_connector_status status;
671dedd2 3805 enum intel_display_power_domain power_domain;
a9756bb5 3806 struct edid *edid = NULL;
0e32b39c 3807 bool ret;
a9756bb5 3808
671dedd2
ID		 3809 power_domain = intel_display_port_power_domain(intel_encoder);
3810 intel_display_power_get(dev_priv, power_domain);
3811
164c8598 3812 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3813 connector->base.id, connector->name);
164c8598 3814
0e32b39c
DA		 3815 if (intel_dp->is_mst) {
3816 /* MST devices are disconnected from a monitor POV */
3817 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3818 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3819 status = connector_status_disconnected;
3820 goto out;
3821 }
3822
a9756bb5
ZW		 3823 intel_dp->has_audio = false;
3824
3825 if (HAS_PCH_SPLIT(dev))
3826 status = ironlake_dp_detect(intel_dp);
3827 else
3828 status = g4x_dp_detect(intel_dp);
1b9be9d0 3829
a9756bb5 3830 if (status != connector_status_connected)
c8c8fb33 3831 goto out;
a9756bb5 3832
0d198328
AJ		 3833 intel_dp_probe_oui(intel_dp);
3834
0e32b39c
DA		 3835 ret = intel_dp_probe_mst(intel_dp);
3836 if (ret) {
3837 /* if we are in MST mode then this connector
3838 won't appear connected or have anything with EDID on it */
3839 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3840 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3841 status = connector_status_disconnected;
3842 goto out;
3843 }
3844
c3e5f67b
DV		 3845 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3846 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3847 } else {
0b99836f 3848 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3849 if (edid) {
3850 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3851 kfree(edid);
3852 }
a9756bb5
ZW		 3853 }
3854
d63885da
PZ		 3855 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3856 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3857 status = connector_status_connected;
3858
3859out:
671dedd2 3860 intel_display_power_put(dev_priv, power_domain);
c8c8fb33 3861 return status;
a4fc5ed6
KP		 3862}
3863
3864static int intel_dp_get_modes(struct drm_connector *connector)
3865{
df0e9248 3866 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3867 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3868 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3869 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3870 struct drm_device *dev = connector->dev;
671dedd2
ID		 3871 struct drm_i915_private *dev_priv = dev->dev_private;
3872 enum intel_display_power_domain power_domain;
32f9d658 3873 int ret;
a4fc5ed6
KP		 3874
3875 /* We should parse the EDID data and find out if it has an audio sink
3876 */
3877
671dedd2
ID		 3878 power_domain = intel_display_port_power_domain(intel_encoder);
3879 intel_display_power_get(dev_priv, power_domain);
3880
0b99836f 3881 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3882 intel_display_power_put(dev_priv, power_domain);
f8779fda 3883 if (ret)
32f9d658
ZW		 3884 return ret;
3885
f8779fda 3886 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3887 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3888 struct drm_display_mode *mode;
dd06f90e
JN		 3889 mode = drm_mode_duplicate(dev,
3890 intel_connector->panel.fixed_mode);
f8779fda 3891 if (mode) {
32f9d658
ZW		 3892 drm_mode_probed_add(connector, mode);
3893 return 1;
3894 }
3895 }
3896 return 0;
a4fc5ed6
KP		 3897}
3898
1aad7ac0
CW		 3899static bool
3900intel_dp_detect_audio(struct drm_connector *connector)
3901{
3902 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3903 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3904 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3905 struct drm_device *dev = connector->dev;
3906 struct drm_i915_private *dev_priv = dev->dev_private;
3907 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3908 struct edid *edid;
3909 bool has_audio = false;
3910
671dedd2
ID		 3911 power_domain = intel_display_port_power_domain(intel_encoder);
3912 intel_display_power_get(dev_priv, power_domain);
3913
0b99836f 3914 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3915 if (edid) {
3916 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3917 kfree(edid);
3918 }
3919
671dedd2
ID		 3920 intel_display_power_put(dev_priv, power_domain);
3921
1aad7ac0
CW		 3922 return has_audio;
3923}
3924
f684960e
CW		 3925static int
3926intel_dp_set_property(struct drm_connector *connector,
3927 struct drm_property *property,
3928 uint64_t val)
3929{
e953fd7b 3930 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3931 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3932 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3933 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3934 int ret;
3935
662595df 3936 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3937 if (ret)
3938 return ret;
3939
3f43c48d 3940 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3941 int i = val;
3942 bool has_audio;
3943
3944 if (i == intel_dp->force_audio)
f684960e
CW		 3945 return 0;
3946
1aad7ac0 3947 intel_dp->force_audio = i;
f684960e 3948
c3e5f67b 3949 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3950 has_audio = intel_dp_detect_audio(connector);
3951 else
c3e5f67b 3952 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3953
3954 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3955 return 0;
3956
1aad7ac0 3957 intel_dp->has_audio = has_audio;
f684960e
CW		 3958 goto done;
3959 }
3960
e953fd7b 3961 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3962 bool old_auto = intel_dp->color_range_auto;
3963 uint32_t old_range = intel_dp->color_range;
3964
55bc60db
VS		 3965 switch (val) {
3966 case INTEL_BROADCAST_RGB_AUTO:
3967 intel_dp->color_range_auto = true;
3968 break;
3969 case INTEL_BROADCAST_RGB_FULL:
3970 intel_dp->color_range_auto = false;
3971 intel_dp->color_range = 0;
3972 break;
3973 case INTEL_BROADCAST_RGB_LIMITED:
3974 intel_dp->color_range_auto = false;
3975 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3976 break;
3977 default:
3978 return -EINVAL;
3979 }
ae4edb80
DV		 3980
3981 if (old_auto == intel_dp->color_range_auto &&
3982 old_range == intel_dp->color_range)
3983 return 0;
3984
e953fd7b
CW		 3985 goto done;
3986 }
3987
53b41837
YN		 3988 if (is_edp(intel_dp) &&
3989 property == connector->dev->mode_config.scaling_mode_property) {
3990 if (val == DRM_MODE_SCALE_NONE) {
3991 DRM_DEBUG_KMS("no scaling not supported\n");
3992 return -EINVAL;
3993 }
3994
3995 if (intel_connector->panel.fitting_mode == val) {
3996 /* the eDP scaling property is not changed */
3997 return 0;
3998 }
3999 intel_connector->panel.fitting_mode = val;
4000
4001 goto done;
4002 }
4003
f684960e
CW		 4004 return -EINVAL;
4005
4006done:
c0c36b94
CW		 4007 if (intel_encoder->base.crtc)
4008 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4009
4010 return 0;
4011}
4012
a4fc5ed6 4013static void
73845adf 4014intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4015{
1d508706 4016 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4017
9cd300e0
JN		 4018 if (!IS_ERR_OR_NULL(intel_connector->edid))
4019 kfree(intel_connector->edid);
4020
acd8db10
PZ		 4021 /* Can't call is_edp() since the encoder may have been destroyed
4022 * already. */
4023 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4024 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4025
a4fc5ed6 4026 drm_connector_cleanup(connector);
55f78c43 4027 kfree(connector);
a4fc5ed6
KP		 4028}
4029
00c09d70 4030void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4031{
da63a9f2
PZ		 4032 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4033 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 4035
4f71d0cb 4036 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4037 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4038 drm_encoder_cleanup(encoder);
bd943159
KP		 4039 if (is_edp(intel_dp)) {
4040 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4041 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4042 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4043 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 4044 if (intel_dp->edp_notifier.notifier_call) {
4045 unregister_reboot_notifier(&intel_dp->edp_notifier);
4046 intel_dp->edp_notifier.notifier_call = NULL;
4047 }
bd943159 4048 }
da63a9f2 4049 kfree(intel_dig_port);
24d05927
DV		 4050}
4051
07f9cd0b
ID		 4052static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4053{
4054 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4055
4056 if (!is_edp(intel_dp))
4057 return;
4058
4059 edp_panel_vdd_off_sync(intel_dp);
4060}
4061
6d93c0c4
ID		 4062static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4063{
4064 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4065}
4066
a4fc5ed6 4067static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4068 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 4069 .detect = intel_dp_detect,
4070 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4071 .set_property = intel_dp_set_property,
73845adf 4072 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4073};
4074
4075static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4076 .get_modes = intel_dp_get_modes,
4077 .mode_valid = intel_dp_mode_valid,
df0e9248 4078 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4079};
4080
a4fc5ed6 4081static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4082 .reset = intel_dp_encoder_reset,
24d05927 4083 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4084};
4085
0e32b39c 4086void
21d40d37 4087intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4088{
0e32b39c 4089 return;
c8110e52 4090}
6207937d 4091
13cf5504
DA		 4092bool
4093intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4094{
4095 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4096 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4097 struct drm_device *dev = intel_dig_port->base.base.dev;
4098 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4099 enum intel_display_power_domain power_domain;
4100 bool ret = true;
4101
0e32b39c
DA		 4102 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4103 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4104
26fbb774
VS		 4105 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4106 port_name(intel_dig_port->port),
0e32b39c 4107 long_hpd ? "long" : "short");
13cf5504 4108
1c767b33
ID		 4109 power_domain = intel_display_port_power_domain(intel_encoder);
4110 intel_display_power_get(dev_priv, power_domain);
4111
0e32b39c
DA		 4112 if (long_hpd) {
4113 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4114 goto mst_fail;
4115
4116 if (!intel_dp_get_dpcd(intel_dp)) {
4117 goto mst_fail;
4118 }
4119
4120 intel_dp_probe_oui(intel_dp);
4121
4122 if (!intel_dp_probe_mst(intel_dp))
4123 goto mst_fail;
4124
4125 } else {
4126 if (intel_dp->is_mst) {
1c767b33 4127 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4128 goto mst_fail;
4129 }
4130
4131 if (!intel_dp->is_mst) {
4132 /*
4133 * we'll check the link status via the normal hot plug path later -
4134 * but for short hpds we should check it now
4135 */
5b215bcf 4136 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4137 intel_dp_check_link_status(intel_dp);
5b215bcf 4138 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4139 }
4140 }
1c767b33
ID		 4141 ret = false;
4142 goto put_power;
0e32b39c
DA		 4143mst_fail:
4144 /* if we were in MST mode, and device is not there get out of MST mode */
4145 if (intel_dp->is_mst) {
4146 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4147 intel_dp->is_mst = false;
4148 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4149 }
1c767b33
ID		 4150put_power:
4151 intel_display_power_put(dev_priv, power_domain);
4152
4153 return ret;
13cf5504
DA		 4154}
4155
e3421a18
ZW		 4156/* Return which DP Port should be selected for Transcoder DP control */
4157int
0206e353 4158intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4159{
4160 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4161 struct intel_encoder *intel_encoder;
4162 struct intel_dp *intel_dp;
e3421a18 4163
fa90ecef
PZ		 4164 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4165 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4166
fa90ecef
PZ		 4167 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4168 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4169 return intel_dp->output_reg;
e3421a18 4170 }
ea5b213a 4171
e3421a18
ZW		 4172 return -1;
4173}
4174
36e83a18 4175/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4176bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4177{
4178 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4179 union child_device_config *p_child;
36e83a18 4180 int i;
5d8a7752
VS		 4181 static const short port_mapping[] = {
4182 [PORT_B] = PORT_IDPB,
4183 [PORT_C] = PORT_IDPC,
4184 [PORT_D] = PORT_IDPD,
4185 };
36e83a18 4186
3b32a35b
VS		 4187 if (port == PORT_A)
4188 return true;
4189
41aa3448 4190 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4191 return false;
4192
41aa3448
RV		 4193 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4194 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4195
5d8a7752 4196 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4197 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4198 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4199 return true;
4200 }
4201 return false;
4202}
4203
0e32b39c 4204void
f684960e
CW		 4205intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4206{
53b41837
YN		 4207 struct intel_connector *intel_connector = to_intel_connector(connector);
4208
3f43c48d 4209 intel_attach_force_audio_property(connector);
e953fd7b 4210 intel_attach_broadcast_rgb_property(connector);
55bc60db 4211 intel_dp->color_range_auto = true;
53b41837
YN		 4212
4213 if (is_edp(intel_dp)) {
4214 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4215 drm_object_attach_property(
4216 &connector->base,
53b41837 4217 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4218 DRM_MODE_SCALE_ASPECT);
4219 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4220 }
f684960e
CW		 4221}
4222
dada1a9f
ID		 4223static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4224{
4225 intel_dp->last_power_cycle = jiffies;
4226 intel_dp->last_power_on = jiffies;
4227 intel_dp->last_backlight_off = jiffies;
4228}
4229
67a54566
DV		 4230static void
4231intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4232 struct intel_dp *intel_dp,
4233 struct edp_power_seq *out)
67a54566
DV		 4234{
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 struct edp_power_seq cur, vbt, spec, final;
4237 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4238 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4239
4240 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4241 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4242 pp_on_reg = PCH_PP_ON_DELAYS;
4243 pp_off_reg = PCH_PP_OFF_DELAYS;
4244 pp_div_reg = PCH_PP_DIVISOR;
4245 } else {
bf13e81b
JN		 4246 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4247
4248 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4249 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4250 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4251 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4252 }
67a54566
DV		 4253
4254 /* Workaround: Need to write PP_CONTROL with the unlock key as
4255 * the very first thing. */
453c5420 4256 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4257 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4258
453c5420
JB		 4259 pp_on = I915_READ(pp_on_reg);
4260 pp_off = I915_READ(pp_off_reg);
4261 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4262
4263 /* Pull timing values out of registers */
4264 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4265 PANEL_POWER_UP_DELAY_SHIFT;
4266
4267 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4268 PANEL_LIGHT_ON_DELAY_SHIFT;
4269
4270 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4271 PANEL_LIGHT_OFF_DELAY_SHIFT;
4272
4273 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4274 PANEL_POWER_DOWN_DELAY_SHIFT;
4275
4276 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4277 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4278
4279 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4280 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4281
41aa3448 4282 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4283
4284 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4285 * our hw here, which are all in 100usec. */
4286 spec.t1_t3 = 210 * 10;
4287 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4288 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4289 spec.t10 = 500 * 10;
4290 /* This one is special and actually in units of 100ms, but zero
4291 * based in the hw (so we need to add 100 ms). But the sw vbt
4292 * table multiplies it with 1000 to make it in units of 100usec,
4293 * too. */
4294 spec.t11_t12 = (510 + 100) * 10;
4295
4296 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4297 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4298
4299 /* Use the max of the register settings and vbt. If both are
4300 * unset, fall back to the spec limits. */
4301#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4302 spec.field : \
4303 max(cur.field, vbt.field))
4304 assign_final(t1_t3);
4305 assign_final(t8);
4306 assign_final(t9);
4307 assign_final(t10);
4308 assign_final(t11_t12);
4309#undef assign_final
4310
4311#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4312 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4313 intel_dp->backlight_on_delay = get_delay(t8);
4314 intel_dp->backlight_off_delay = get_delay(t9);
4315 intel_dp->panel_power_down_delay = get_delay(t10);
4316 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4317#undef get_delay
4318
f30d26e4
JN		 4319 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4320 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4321 intel_dp->panel_power_cycle_delay);
4322
4323 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4324 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4325
4326 if (out)
4327 *out = final;
4328}
4329
4330static void
4331intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4332 struct intel_dp *intel_dp,
4333 struct edp_power_seq *seq)
4334{
4335 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4336 u32 pp_on, pp_off, pp_div, port_sel = 0;
4337 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4338 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4339 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420
JB		 4340
4341 if (HAS_PCH_SPLIT(dev)) {
4342 pp_on_reg = PCH_PP_ON_DELAYS;
4343 pp_off_reg = PCH_PP_OFF_DELAYS;
4344 pp_div_reg = PCH_PP_DIVISOR;
4345 } else {
bf13e81b
JN		 4346 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4347
4348 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4349 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4350 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4351 }
4352
b2f19d1a
PZ		 4353 /*
4354 * And finally store the new values in the power sequencer. The
4355 * backlight delays are set to 1 because we do manual waits on them. For
4356 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4357 * we'll end up waiting for the backlight off delay twice: once when we
4358 * do the manual sleep, and once when we disable the panel and wait for
4359 * the PP_STATUS bit to become zero.
4360 */
f30d26e4 4361 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4362 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4363 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4364 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4365 /* Compute the divisor for the pp clock, simply match the Bspec
4366 * formula. */
453c5420 4367 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4368 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4369 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4370
4371 /* Haswell doesn't have any port selection bits for the panel
4372 * power sequencer any more. */
bc7d38a4 4373 if (IS_VALLEYVIEW(dev)) {
ad933b56 4374 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4375 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4376 if (port == PORT_A)
a24c144c 4377 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4378 else
a24c144c 4379 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4380 }
4381
453c5420
JB		 4382 pp_on |= port_sel;
4383
4384 I915_WRITE(pp_on_reg, pp_on);
4385 I915_WRITE(pp_off_reg, pp_off);
4386 I915_WRITE(pp_div_reg, pp_div);
67a54566 4387
67a54566 4388 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4389 I915_READ(pp_on_reg),
4390 I915_READ(pp_off_reg),
4391 I915_READ(pp_div_reg));
f684960e
CW		 4392}
4393
439d7ac0
PB		 4394void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4395{
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 struct intel_encoder *encoder;
4398 struct intel_dp *intel_dp = NULL;
4399 struct intel_crtc_config *config = NULL;
4400 struct intel_crtc *intel_crtc = NULL;
4401 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4402 u32 reg, val;
4403 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4404
4405 if (refresh_rate <= 0) {
4406 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4407 return;
4408 }
4409
4410 if (intel_connector == NULL) {
4411 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4412 return;
4413 }
4414
1fcc9d1c
DV		 4415 /*
4416 * FIXME: This needs proper synchronization with psr state. But really
4417 * hard to tell without seeing the user of this function of this code.
4418 * Check locking and ordering once that lands.
4419 */
439d7ac0
PB		 4420 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4421 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4422 return;
4423 }
4424
4425 encoder = intel_attached_encoder(&intel_connector->base);
4426 intel_dp = enc_to_intel_dp(&encoder->base);
4427 intel_crtc = encoder->new_crtc;
4428
4429 if (!intel_crtc) {
4430 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4431 return;
4432 }
4433
4434 config = &intel_crtc->config;
4435
4436 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4437 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4438 return;
4439 }
4440
4441 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4442 index = DRRS_LOW_RR;
4443
4444 if (index == intel_dp->drrs_state.refresh_rate_type) {
4445 DRM_DEBUG_KMS(
4446 "DRRS requested for previously set RR...ignoring\n");
4447 return;
4448 }
4449
4450 if (!intel_crtc->active) {
4451 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4452 return;
4453 }
4454
4455 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4456 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4457 val = I915_READ(reg);
4458 if (index > DRRS_HIGH_RR) {
4459 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4460 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4461 } else {
4462 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4463 }
4464 I915_WRITE(reg, val);
4465 }
4466
4467 /*
4468 * mutex taken to ensure that there is no race between differnt
4469 * drrs calls trying to update refresh rate. This scenario may occur
4470 * in future when idleness detection based DRRS in kernel and
4471 * possible calls from user space to set differnt RR are made.
4472 */
4473
4474 mutex_lock(&intel_dp->drrs_state.mutex);
4475
4476 intel_dp->drrs_state.refresh_rate_type = index;
4477
4478 mutex_unlock(&intel_dp->drrs_state.mutex);
4479
4480 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4481}
4482
4f9db5b5
PB		 4483static struct drm_display_mode *
4484intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4485 struct intel_connector *intel_connector,
4486 struct drm_display_mode *fixed_mode)
4487{
4488 struct drm_connector *connector = &intel_connector->base;
4489 struct intel_dp *intel_dp = &intel_dig_port->dp;
4490 struct drm_device *dev = intel_dig_port->base.base.dev;
4491 struct drm_i915_private *dev_priv = dev->dev_private;
4492 struct drm_display_mode *downclock_mode = NULL;
4493
4494 if (INTEL_INFO(dev)->gen <= 6) {
4495 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4496 return NULL;
4497 }
4498
4499 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4500 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4501 return NULL;
4502 }
4503
4504 downclock_mode = intel_find_panel_downclock
4505 (dev, fixed_mode, connector);
4506
4507 if (!downclock_mode) {
4079b8d1 4508 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4509 return NULL;
4510 }
4511
439d7ac0
PB		 4512 dev_priv->drrs.connector = intel_connector;
4513
4514 mutex_init(&intel_dp->drrs_state.mutex);
4515
4f9db5b5
PB		 4516 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4517
4518 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4519 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4520 return downclock_mode;
4521}
4522
aba86890
ID		 4523void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4524{
4525 struct drm_device *dev = intel_encoder->base.dev;
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527 struct intel_dp *intel_dp;
4528 enum intel_display_power_domain power_domain;
4529
4530 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4531 return;
4532
4533 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4534 if (!edp_have_panel_vdd(intel_dp))
4535 return;
4536 /*
4537 * The VDD bit needs a power domain reference, so if the bit is
4538 * already enabled when we boot or resume, grab this reference and
4539 * schedule a vdd off, so we don't hold on to the reference
4540 * indefinitely.
4541 */
4542 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4543 power_domain = intel_display_port_power_domain(intel_encoder);
4544 intel_display_power_get(dev_priv, power_domain);
4545
4546 edp_panel_vdd_schedule_off(intel_dp);
4547}
4548
ed92f0b2 4549static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4550 struct intel_connector *intel_connector,
4551 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4552{
4553 struct drm_connector *connector = &intel_connector->base;
4554 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4555 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4556 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4557 struct drm_i915_private *dev_priv = dev->dev_private;
4558 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4559 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4560 bool has_dpcd;
4561 struct drm_display_mode *scan;
4562 struct edid *edid;
4563
4f9db5b5
PB		 4564 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4565
ed92f0b2
PZ		 4566 if (!is_edp(intel_dp))
4567 return true;
4568
aba86890 4569 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4570
ed92f0b2 4571 /* Cache DPCD and EDID for edp. */
24f3e092 4572 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4573 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4574 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4575
4576 if (has_dpcd) {
4577 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4578 dev_priv->no_aux_handshake =
4579 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4580 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4581 } else {
4582 /* if this fails, presume the device is a ghost */
4583 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4584 return false;
4585 }
4586
4587 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4588 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4589
060c8778 4590 mutex_lock(&dev->mode_config.mutex);
0b99836f 4591 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4592 if (edid) {
4593 if (drm_add_edid_modes(connector, edid)) {
4594 drm_mode_connector_update_edid_property(connector,
4595 edid);
4596 drm_edid_to_eld(connector, edid);
4597 } else {
4598 kfree(edid);
4599 edid = ERR_PTR(-EINVAL);
4600 }
4601 } else {
4602 edid = ERR_PTR(-ENOENT);
4603 }
4604 intel_connector->edid = edid;
4605
4606 /* prefer fixed mode from EDID if available */
4607 list_for_each_entry(scan, &connector->probed_modes, head) {
4608 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4609 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4610 downclock_mode = intel_dp_drrs_init(
4611 intel_dig_port,
4612 intel_connector, fixed_mode);
ed92f0b2
PZ		 4613 break;
4614 }
4615 }
4616
4617 /* fallback to VBT if available for eDP */
4618 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4619 fixed_mode = drm_mode_duplicate(dev,
4620 dev_priv->vbt.lfp_lvds_vbt_mode);
4621 if (fixed_mode)
4622 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4623 }
060c8778 4624 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4625
01527b31
CT		 4626 if (IS_VALLEYVIEW(dev)) {
4627 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4628 register_reboot_notifier(&intel_dp->edp_notifier);
4629 }
4630
4f9db5b5 4631 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4632 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4633 intel_panel_setup_backlight(connector);
4634
4635 return true;
4636}
4637
16c25533 4638bool
f0fec3f2
PZ		 4639intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4640 struct intel_connector *intel_connector)
a4fc5ed6 4641{
f0fec3f2
PZ		 4642 struct drm_connector *connector = &intel_connector->base;
4643 struct intel_dp *intel_dp = &intel_dig_port->dp;
4644 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4645 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4646 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4647 enum port port = intel_dig_port->port;
0095e6dc 4648 struct edp_power_seq power_seq = { 0 };
0b99836f 4649 int type;
a4fc5ed6 4650
ec5b01dd
DL		 4651 /* intel_dp vfuncs */
4652 if (IS_VALLEYVIEW(dev))
4653 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4654 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4655 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4656 else if (HAS_PCH_SPLIT(dev))
4657 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4658 else
4659 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4660
153b1100
DL		 4661 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4662
0767935e
DV		 4663 /* Preserve the current hw state. */
4664 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4665 intel_dp->attached_connector = intel_connector;
3d3dc149 4666
3b32a35b 4667 if (intel_dp_is_edp(dev, port))
b329530c 4668 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4669 else
4670 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4671
f7d24902
ID		 4672 /*
4673 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4674 * for DP the encoder type can be set by the caller to
4675 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4676 */
4677 if (type == DRM_MODE_CONNECTOR_eDP)
4678 intel_encoder->type = INTEL_OUTPUT_EDP;
4679
e7281eab
ID		 4680 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4681 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4682 port_name(port));
4683
b329530c 4684 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4685 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4686
a4fc5ed6
KP		 4687 connector->interlace_allowed = true;
4688 connector->doublescan_allowed = 0;
4689
f0fec3f2 4690 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4691 edp_panel_vdd_work);
a4fc5ed6 4692
df0e9248 4693 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4694 drm_connector_register(connector);
a4fc5ed6 4695
affa9354 4696 if (HAS_DDI(dev))
bcbc889b
PZ		 4697 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4698 else
4699 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4700 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4701
0b99836f 4702 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4703 switch (port) {
4704 case PORT_A:
1d843f9d 4705 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4706 break;
4707 case PORT_B:
1d843f9d 4708 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4709 break;
4710 case PORT_C:
1d843f9d 4711 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4712 break;
4713 case PORT_D:
1d843f9d 4714 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4715 break;
4716 default:
ad1c0b19 4717 BUG();
5eb08b69
ZW		 4718 }
4719
dada1a9f
ID		 4720 if (is_edp(intel_dp)) {
4721 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4722 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4723 }
0095e6dc 4724
9d1a1031 4725 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4726
0e32b39c
DA		 4727 /* init MST on ports that can support it */
4728 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4729 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4730 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4731 }
4732 }
4733
0095e6dc 4734 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4735 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4736 if (is_edp(intel_dp)) {
4737 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4738 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4739 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4740 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4741 }
34ea3d38 4742 drm_connector_unregister(connector);
b2f246a8 4743 drm_connector_cleanup(connector);
16c25533 4744 return false;
b2f246a8 4745 }
32f9d658 4746
f684960e
CW		 4747 intel_dp_add_properties(intel_dp, connector);
4748
a4fc5ed6
KP		 4749 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4750 * 0xd. Failure to do so will result in spurious interrupts being
4751 * generated on the port when a cable is not attached.
4752 */
4753 if (IS_G4X(dev) && !IS_GM45(dev)) {
4754 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4755 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4756 }
16c25533
PZ		 4757
4758 return true;
a4fc5ed6 4759}
f0fec3f2
PZ		 4760
4761void
4762intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4763{
13cf5504 4764 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4765 struct intel_digital_port *intel_dig_port;
4766 struct intel_encoder *intel_encoder;
4767 struct drm_encoder *encoder;
4768 struct intel_connector *intel_connector;
4769
b14c5679 4770 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4771 if (!intel_dig_port)
4772 return;
4773
b14c5679 4774 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4775 if (!intel_connector) {
4776 kfree(intel_dig_port);
4777 return;
4778 }
4779
4780 intel_encoder = &intel_dig_port->base;
4781 encoder = &intel_encoder->base;
4782
4783 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4784 DRM_MODE_ENCODER_TMDS);
4785
5bfe2ac0 4786 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4787 intel_encoder->disable = intel_disable_dp;
00c09d70 4788 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4789 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 4790 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 4791 if (IS_CHERRYVIEW(dev)) {
9197c88b 4792 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4793 intel_encoder->pre_enable = chv_pre_enable_dp;
4794 intel_encoder->enable = vlv_enable_dp;
580d3811 4795 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4796 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4797 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4798 intel_encoder->pre_enable = vlv_pre_enable_dp;
4799 intel_encoder->enable = vlv_enable_dp;
49277c31 4800 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4801 } else {
ecff4f3b
JN		 4802 intel_encoder->pre_enable = g4x_pre_enable_dp;
4803 intel_encoder->enable = g4x_enable_dp;
49277c31 4804 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4805 }
f0fec3f2 4806
174edf1f 4807 intel_dig_port->port = port;
f0fec3f2
PZ		 4808 intel_dig_port->dp.output_reg = output_reg;
4809
00c09d70 4810 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4811 if (IS_CHERRYVIEW(dev)) {
4812 if (port == PORT_D)
4813 intel_encoder->crtc_mask = 1 << 2;
4814 else
4815 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4816 } else {
4817 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4818 }
bc079e8b 4819 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4820 intel_encoder->hot_plug = intel_dp_hot_plug;
4821
13cf5504
DA		 4822 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4823 dev_priv->hpd_irq_port[port] = intel_dig_port;
4824
15b1d171
PZ		 4825 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4826 drm_encoder_cleanup(encoder);
4827 kfree(intel_dig_port);
b2f246a8 4828 kfree(intel_connector);
15b1d171 4829 }
f0fec3f2 4830}
0e32b39c
DA		 4831
4832void intel_dp_mst_suspend(struct drm_device *dev)
4833{
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4835 int i;
4836
4837 /* disable MST */
4838 for (i = 0; i < I915_MAX_PORTS; i++) {
4839 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4840 if (!intel_dig_port)
4841 continue;
4842
4843 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4844 if (!intel_dig_port->dp.can_mst)
4845 continue;
4846 if (intel_dig_port->dp.is_mst)
4847 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4848 }
4849 }
4850}
4851
4852void intel_dp_mst_resume(struct drm_device *dev)
4853{
4854 struct drm_i915_private *dev_priv = dev->dev_private;
4855 int i;
4856
4857 for (i = 0; i < I915_MAX_PORTS; i++) {
4858 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4859 if (!intel_dig_port)
4860 continue;
4861 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4862 int ret;
4863
4864 if (!intel_dig_port->dp.can_mst)
4865 continue;
4866
4867 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4868 if (ret != 0) {
4869 intel_dp_check_mst_status(&intel_dig_port->dp);
4870 }
4871 }
4872 }
4873}
Linux kernel - Deliverables
This page took 0.807716 seconds and 5 git commands to generate.