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drm/i915/dp: Move port A pll setup to g4x_pre_enable_dp
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
a4fc5ed6 115static int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 126 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
128 max_link_bw = DP_LINK_BW_5_4;
129 else
130 max_link_bw = DP_LINK_BW_2_7;
d4eead50 131 break;
a4fc5ed6 132 default:
d4eead50
ID		 133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
134 max_link_bw);
a4fc5ed6
KP		 135 max_link_bw = DP_LINK_BW_1_62;
136 break;
137 }
138 return max_link_bw;
139}
140
cd9dde44
AJ		 141/*
142 * The units on the numbers in the next two are... bizarre. Examples will
143 * make it clearer; this one parallels an example in the eDP spec.
144 *
145 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
146 *
147 * 270000 * 1 * 8 / 10 == 216000
148 *
149 * The actual data capacity of that configuration is 2.16Gbit/s, so the
150 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
151 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
152 * 119000. At 18bpp that's 2142000 kilobits per second.
153 *
154 * Thus the strange-looking division by 10 in intel_dp_link_required, to
155 * get the result in decakilobits instead of kilobits.
156 */
157
a4fc5ed6 158static int
c898261c 159intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 160{
cd9dde44 161 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 162}
163
fe27d53e
DA		 164static int
165intel_dp_max_data_rate(int max_link_clock, int max_lanes)
166{
167 return (max_link_clock * max_lanes * 8) / 10;
168}
169
c19de8eb 170static enum drm_mode_status
a4fc5ed6
KP		 171intel_dp_mode_valid(struct drm_connector *connector,
172 struct drm_display_mode *mode)
173{
df0e9248 174 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 175 struct intel_connector *intel_connector = to_intel_connector(connector);
176 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 177 int target_clock = mode->clock;
178 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 179
dd06f90e
JN		 180 if (is_edp(intel_dp) && fixed_mode) {
181 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 182 return MODE_PANEL;
183
dd06f90e 184 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 185 return MODE_PANEL;
03afc4a2
DV		 186
187 target_clock = fixed_mode->clock;
7de56f43
ZY		 188 }
189
36008365
DV		 190 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
191 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
192
193 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
194 mode_rate = intel_dp_link_required(target_clock, 18);
195
196 if (mode_rate > max_rate)
c4867936 197 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 198
199 if (mode->clock < 10000)
200 return MODE_CLOCK_LOW;
201
0af78a2b
DV		 202 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
203 return MODE_H_ILLEGAL;
204
a4fc5ed6
KP		 205 return MODE_OK;
206}
207
208static uint32_t
209pack_aux(uint8_t *src, int src_bytes)
210{
211 int i;
212 uint32_t v = 0;
213
214 if (src_bytes > 4)
215 src_bytes = 4;
216 for (i = 0; i < src_bytes; i++)
217 v |= ((uint32_t) src[i]) << ((3-i) * 8);
218 return v;
219}
220
221static void
222unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
223{
224 int i;
225 if (dst_bytes > 4)
226 dst_bytes = 4;
227 for (i = 0; i < dst_bytes; i++)
228 dst[i] = src >> ((3-i) * 8);
229}
230
fb0f8fbf
KP		 231/* hrawclock is 1/4 the FSB frequency */
232static int
233intel_hrawclk(struct drm_device *dev)
234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 uint32_t clkcfg;
237
9473c8f4
VP		 238 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
239 if (IS_VALLEYVIEW(dev))
240 return 200;
241
fb0f8fbf
KP		 242 clkcfg = I915_READ(CLKCFG);
243 switch (clkcfg & CLKCFG_FSB_MASK) {
244 case CLKCFG_FSB_400:
245 return 100;
246 case CLKCFG_FSB_533:
247 return 133;
248 case CLKCFG_FSB_667:
249 return 166;
250 case CLKCFG_FSB_800:
251 return 200;
252 case CLKCFG_FSB_1067:
253 return 266;
254 case CLKCFG_FSB_1333:
255 return 333;
256 /* these two are just a guess; one of them might be right */
257 case CLKCFG_FSB_1600:
258 case CLKCFG_FSB_1600_ALT:
259 return 400;
260 default:
261 return 133;
262 }
263}
264
bf13e81b
JN		 265static void
266intel_dp_init_panel_power_sequencer(struct drm_device *dev,
267 struct intel_dp *intel_dp,
268 struct edp_power_seq *out);
269static void
270intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
271 struct intel_dp *intel_dp,
272 struct edp_power_seq *out);
273
274static enum pipe
275vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
276{
277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
278 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
279 struct drm_device *dev = intel_dig_port->base.base.dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 enum port port = intel_dig_port->port;
282 enum pipe pipe;
283
284 /* modeset should have pipe */
285 if (crtc)
286 return to_intel_crtc(crtc)->pipe;
287
288 /* init time, try to find a pipe with this port selected */
289 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
290 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
291 PANEL_PORT_SELECT_MASK;
292 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
293 return pipe;
294 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
295 return pipe;
296 }
297
298 /* shrug */
299 return PIPE_A;
300}
301
302static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
303{
304 struct drm_device *dev = intel_dp_to_dev(intel_dp);
305
306 if (HAS_PCH_SPLIT(dev))
307 return PCH_PP_CONTROL;
308 else
309 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
310}
311
312static u32 _pp_stat_reg(struct intel_dp *intel_dp)
313{
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315
316 if (HAS_PCH_SPLIT(dev))
317 return PCH_PP_STATUS;
318 else
319 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
320}
321
4be73780 322static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 325 struct drm_i915_private *dev_priv = dev->dev_private;
326
bf13e81b 327 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 328}
329
4be73780 330static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 331{
30add22d 332 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 333 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct intel_encoder *intel_encoder = &intel_dig_port->base;
336 enum intel_display_power_domain power_domain;
ebf33b18 337
bb4932c4
ID		 338 power_domain = intel_display_port_power_domain(intel_encoder);
339 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 340 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 341}
342
9b984dae
KP		 343static void
344intel_dp_check_edp(struct intel_dp *intel_dp)
345{
30add22d 346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 347 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 348
9b984dae
KP		 349 if (!is_edp(intel_dp))
350 return;
453c5420 351
4be73780 352 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 353 WARN(1, "eDP powered off while attempting aux channel communication.\n");
354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 355 I915_READ(_pp_stat_reg(intel_dp)),
356 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 357 }
358}
359
9ee32fea
DV		 360static uint32_t
361intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
362{
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 366 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 367 uint32_t status;
368 bool done;
369
ef04f00d 370#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 371 if (has_aux_irq)
b18ac466 372 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 373 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 374 else
375 done = wait_for_atomic(C, 10) == 0;
376 if (!done)
377 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
378 has_aux_irq);
379#undef C
380
381 return status;
382}
383
ec5b01dd 384static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 385{
174edf1f
PZ		 386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
387 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 388
ec5b01dd
DL		 389 /*
390 * The clock divider is based off the hrawclk, and would like to run at
391 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 392 */
ec5b01dd
DL		 393 return index ? 0 : intel_hrawclk(dev) / 2;
394}
395
396static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400
401 if (index)
402 return 0;
403
404 if (intel_dig_port->port == PORT_A) {
405 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 406 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 407 else
b84a1cf8 408 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 409 } else {
410 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
411 }
412}
413
414static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
417 struct drm_device *dev = intel_dig_port->base.base.dev;
418 struct drm_i915_private *dev_priv = dev->dev_private;
419
420 if (intel_dig_port->port == PORT_A) {
421 if (index)
422 return 0;
423 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 424 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
425 /* Workaround for non-ULT HSW */
bc86625a
CW		 426 switch (index) {
427 case 0: return 63;
428 case 1: return 72;
429 default: return 0;
430 }
ec5b01dd 431 } else {
bc86625a 432 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 433 }
b84a1cf8
RV		 434}
435
ec5b01dd
DL		 436static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
437{
438 return index ? 0 : 100;
439}
440
5ed12a19
DL		 441static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
442 bool has_aux_irq,
443 int send_bytes,
444 uint32_t aux_clock_divider)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448 uint32_t precharge, timeout;
449
450 if (IS_GEN6(dev))
451 precharge = 3;
452 else
453 precharge = 5;
454
455 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
456 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
457 else
458 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
459
460 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 461 DP_AUX_CH_CTL_DONE |
5ed12a19 462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 463 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 464 timeout |
788d4433 465 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 466 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
467 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 468 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 469}
470
b84a1cf8
RV		 471static int
472intel_dp_aux_ch(struct intel_dp *intel_dp,
473 uint8_t *send, int send_bytes,
474 uint8_t *recv, int recv_size)
475{
476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
477 struct drm_device *dev = intel_dig_port->base.base.dev;
478 struct drm_i915_private *dev_priv = dev->dev_private;
479 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
480 uint32_t ch_data = ch_ctl + 4;
bc86625a 481 uint32_t aux_clock_divider;
b84a1cf8
RV		 482 int i, ret, recv_bytes;
483 uint32_t status;
5ed12a19 484 int try, clock = 0;
4e6b788c 485 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 486 bool vdd;
487
488 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 489
490 /* dp aux is extremely sensitive to irq latency, hence request the
491 * lowest possible wakeup latency and so prevent the cpu from going into
492 * deep sleep states.
493 */
494 pm_qos_update_request(&dev_priv->pm_qos, 0);
495
496 intel_dp_check_edp(intel_dp);
5eb08b69 497
c67a470b
PZ		 498 intel_aux_display_runtime_get(dev_priv);
499
11bee43e
JB		 500 /* Try to wait for any previous AUX channel activity */
501 for (try = 0; try < 3; try++) {
ef04f00d 502 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 503 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
504 break;
505 msleep(1);
506 }
507
508 if (try == 3) {
509 WARN(1, "dp_aux_ch not started status 0x%08x\n",
510 I915_READ(ch_ctl));
9ee32fea
DV		 511 ret = -EBUSY;
512 goto out;
4f7f7b7e
CW		 513 }
514
46a5ae9f
PZ		 515 /* Only 5 data registers! */
516 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
517 ret = -E2BIG;
518 goto out;
519 }
520
ec5b01dd 521 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 522 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
523 has_aux_irq,
524 send_bytes,
525 aux_clock_divider);
5ed12a19 526
bc86625a
CW		 527 /* Must try at least 3 times according to DP spec */
528 for (try = 0; try < 5; try++) {
529 /* Load the send data into the aux channel data registers */
530 for (i = 0; i < send_bytes; i += 4)
531 I915_WRITE(ch_data + i,
532 pack_aux(send + i, send_bytes - i));
533
534 /* Send the command and wait for it to complete */
5ed12a19 535 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 536
537 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
538
539 /* Clear done status and any errors */
540 I915_WRITE(ch_ctl,
541 status |
542 DP_AUX_CH_CTL_DONE |
543 DP_AUX_CH_CTL_TIME_OUT_ERROR |
544 DP_AUX_CH_CTL_RECEIVE_ERROR);
545
546 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
547 DP_AUX_CH_CTL_RECEIVE_ERROR))
548 continue;
549 if (status & DP_AUX_CH_CTL_DONE)
550 break;
551 }
4f7f7b7e 552 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 553 break;
554 }
555
a4fc5ed6 556 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 557 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 558 ret = -EBUSY;
559 goto out;
a4fc5ed6
KP		 560 }
561
562 /* Check for timeout or receive error.
563 * Timeouts occur when the sink is not connected
564 */
a5b3da54 565 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 566 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 567 ret = -EIO;
568 goto out;
a5b3da54 569 }
1ae8c0a5
KP		 570
571 /* Timeouts occur when the device isn't connected, so they're
572 * "normal" -- don't fill the kernel log with these */
a5b3da54 573 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 574 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -ETIMEDOUT;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Unload any bytes sent back from the other side */
580 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
581 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 582 if (recv_bytes > recv_size)
583 recv_bytes = recv_size;
0206e353 584
4f7f7b7e
CW		 585 for (i = 0; i < recv_bytes; i += 4)
586 unpack_aux(I915_READ(ch_data + i),
587 recv + i, recv_bytes - i);
a4fc5ed6 588
9ee32fea
DV		 589 ret = recv_bytes;
590out:
591 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 592 intel_aux_display_runtime_put(dev_priv);
9ee32fea 593
884f19e9
JN		 594 if (vdd)
595 edp_panel_vdd_off(intel_dp, false);
596
9ee32fea 597 return ret;
a4fc5ed6
KP		 598}
599
a6c8aff0
JN		 600#define BARE_ADDRESS_SIZE 3
601#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 602static ssize_t
603intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 604{
9d1a1031
JN		 605 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
606 uint8_t txbuf[20], rxbuf[20];
607 size_t txsize, rxsize;
a4fc5ed6 608 int ret;
a4fc5ed6 609
9d1a1031
JN		 610 txbuf[0] = msg->request << 4;
611 txbuf[1] = msg->address >> 8;
612 txbuf[2] = msg->address & 0xff;
613 txbuf[3] = msg->size - 1;
46a5ae9f 614
9d1a1031
JN		 615 switch (msg->request & ~DP_AUX_I2C_MOT) {
616 case DP_AUX_NATIVE_WRITE:
617 case DP_AUX_I2C_WRITE:
a6c8aff0 618 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 619 rxsize = 1;
f51a44b9 620
9d1a1031
JN		 621 if (WARN_ON(txsize > 20))
622 return -E2BIG;
a4fc5ed6 623
9d1a1031 624 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 625
9d1a1031
JN		 626 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
627 if (ret > 0) {
628 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 629
9d1a1031
JN		 630 /* Return payload size. */
631 ret = msg->size;
632 }
633 break;
46a5ae9f 634
9d1a1031
JN		 635 case DP_AUX_NATIVE_READ:
636 case DP_AUX_I2C_READ:
a6c8aff0 637 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 638 rxsize = msg->size + 1;
a4fc5ed6 639
9d1a1031
JN		 640 if (WARN_ON(rxsize > 20))
641 return -E2BIG;
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
646 /*
647 * Assume happy day, and copy the data. The caller is
648 * expected to check msg->reply before touching it.
649 *
650 * Return payload size.
651 */
652 ret--;
653 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 654 }
9d1a1031
JN		 655 break;
656
657 default:
658 ret = -EINVAL;
659 break;
a4fc5ed6 660 }
f51a44b9 661
9d1a1031 662 return ret;
a4fc5ed6
KP		 663}
664
9d1a1031
JN		 665static void
666intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
667{
668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 enum port port = intel_dig_port->port;
0b99836f 671 const char *name = NULL;
ab2c0672
DA		 672 int ret;
673
33ad6626
JN		 674 switch (port) {
675 case PORT_A:
676 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 677 name = "DPDDC-A";
ab2c0672 678 break;
33ad6626
JN		 679 case PORT_B:
680 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 681 name = "DPDDC-B";
ab2c0672 682 break;
33ad6626
JN		 683 case PORT_C:
684 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 685 name = "DPDDC-C";
ab2c0672 686 break;
33ad6626
JN		 687 case PORT_D:
688 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 689 name = "DPDDC-D";
33ad6626
JN		 690 break;
691 default:
692 BUG();
ab2c0672
DA		 693 }
694
33ad6626
JN		 695 if (!HAS_DDI(dev))
696 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 697
0b99836f 698 intel_dp->aux.name = name;
9d1a1031
JN		 699 intel_dp->aux.dev = dev->dev;
700 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 701
0b99836f
JN		 702 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
703 connector->base.kdev->kobj.name);
8316f337 704
0b99836f
JN		 705 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
706 if (ret < 0) {
707 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
708 name, ret);
709 return;
ab2c0672 710 }
8a5e6aeb 711
0b99836f
JN		 712 ret = sysfs_create_link(&connector->base.kdev->kobj,
713 &intel_dp->aux.ddc.dev.kobj,
714 intel_dp->aux.ddc.dev.kobj.name);
715 if (ret < 0) {
716 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
717 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 718 }
a4fc5ed6
KP		 719}
720
80f65de3
ID		 721static void
722intel_dp_connector_unregister(struct intel_connector *intel_connector)
723{
724 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
725
726 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 727 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 728 intel_connector_unregister(intel_connector);
729}
730
c6bb3538
DV		 731static void
732intel_dp_set_clock(struct intel_encoder *encoder,
733 struct intel_crtc_config *pipe_config, int link_bw)
734{
735 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 736 const struct dp_link_dpll *divisor = NULL;
737 int i, count = 0;
c6bb3538
DV		 738
739 if (IS_G4X(dev)) {
9dd4ffdf
CML		 740 divisor = gen4_dpll;
741 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 742 } else if (IS_HASWELL(dev)) {
743 /* Haswell has special-purpose DP DDI clocks. */
744 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 745 divisor = pch_dpll;
746 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 747 } else if (IS_CHERRYVIEW(dev)) {
748 divisor = chv_dpll;
749 count = ARRAY_SIZE(chv_dpll);
c6bb3538 750 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 751 divisor = vlv_dpll;
752 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 753 }
9dd4ffdf
CML		 754
755 if (divisor && count) {
756 for (i = 0; i < count; i++) {
757 if (link_bw == divisor[i].link_bw) {
758 pipe_config->dpll = divisor[i].dpll;
759 pipe_config->clock_set = true;
760 break;
761 }
762 }
c6bb3538
DV		 763 }
764}
765
439d7ac0
PB		 766static void
767intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
768{
769 struct drm_device *dev = crtc->base.dev;
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 enum transcoder transcoder = crtc->config.cpu_transcoder;
772
773 I915_WRITE(PIPE_DATA_M2(transcoder),
774 TU_SIZE(m_n->tu) | m_n->gmch_m);
775 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
776 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
777 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
778}
779
00c09d70 780bool
5bfe2ac0
DV		 781intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
a4fc5ed6 783{
5bfe2ac0 784 struct drm_device *dev = encoder->base.dev;
36008365 785 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 788 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 789 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 790 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 791 int lane_count, clock;
397fe157 792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 793 /* Conveniently, the link BW constants become indices with a shift...*/
794 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 795 int bpp, mode_rate;
06ea66b6 796 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 797 int link_avail, link_clock;
a4fc5ed6 798
bc7d38a4 799 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 800 pipe_config->has_pch_encoder = true;
801
03afc4a2 802 pipe_config->has_dp_encoder = true;
9ed109a7 803 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 804
dd06f90e
JN		 805 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
806 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
807 adjusted_mode);
2dd24552
JB		 808 if (!HAS_PCH_SPLIT(dev))
809 intel_gmch_panel_fitting(intel_crtc, pipe_config,
810 intel_connector->panel.fitting_mode);
811 else
b074cec8
JB		 812 intel_pch_panel_fitting(intel_crtc, pipe_config,
813 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 814 }
815
cb1793ce 816 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 817 return false;
818
083f9560
DV		 819 DRM_DEBUG_KMS("DP link computation with max lane count %i "
820 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 821 max_lane_count, bws[max_clock],
822 adjusted_mode->crtc_clock);
083f9560 823
36008365
DV		 824 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
825 * bpc in between. */
3e7ca985 826 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 827 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
828 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 829 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
830 dev_priv->vbt.edp_bpp);
6da7f10d 831 bpp = dev_priv->vbt.edp_bpp;
7984211e 832 }
657445fe 833
36008365 834 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 835 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
836 bpp);
36008365 837
38aecea0
DV		 838 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
839 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 840 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
841 link_avail = intel_dp_max_data_rate(link_clock,
842 lane_count);
843
844 if (mode_rate <= link_avail) {
845 goto found;
846 }
847 }
848 }
849 }
c4867936 850
36008365 851 return false;
3685a8f3 852
36008365 853found:
55bc60db
VS		 854 if (intel_dp->color_range_auto) {
855 /*
856 * See:
857 * CEA-861-E - 5.1 Default Encoding Parameters
858 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
859 */
18316c8c 860 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 861 intel_dp->color_range = DP_COLOR_RANGE_16_235;
862 else
863 intel_dp->color_range = 0;
864 }
865
3685a8f3 866 if (intel_dp->color_range)
50f3b016 867 pipe_config->limited_color_range = true;
a4fc5ed6 868
36008365
DV		 869 intel_dp->link_bw = bws[clock];
870 intel_dp->lane_count = lane_count;
657445fe 871 pipe_config->pipe_bpp = bpp;
ff9a6750 872 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 873
36008365
DV		 874 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
875 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 876 pipe_config->port_clock, bpp);
36008365
DV		 877 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
878 mode_rate, link_avail);
a4fc5ed6 879
03afc4a2 880 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 881 adjusted_mode->crtc_clock,
882 pipe_config->port_clock,
03afc4a2 883 &pipe_config->dp_m_n);
9d1a455b 884
439d7ac0
PB		 885 if (intel_connector->panel.downclock_mode != NULL &&
886 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
887 intel_link_compute_m_n(bpp, lane_count,
888 intel_connector->panel.downclock_mode->clock,
889 pipe_config->port_clock,
890 &pipe_config->dp_m2_n2);
891 }
892
c6bb3538
DV		 893 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
894
03afc4a2 895 return true;
a4fc5ed6
KP		 896}
897
7c62a164 898static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 899{
7c62a164
DV		 900 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
901 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
902 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 903 struct drm_i915_private *dev_priv = dev->dev_private;
904 u32 dpa_ctl;
905
ff9a6750 906 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 907 dpa_ctl = I915_READ(DP_A);
908 dpa_ctl &= ~DP_PLL_FREQ_MASK;
909
ff9a6750 910 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 911 /* For a long time we've carried around a ILK-DevA w/a for the
912 * 160MHz clock. If we're really unlucky, it's still required.
913 */
914 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 915 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 916 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 917 } else {
918 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 919 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 920 }
1ce17038 921
ea9b6006
DV		 922 I915_WRITE(DP_A, dpa_ctl);
923
924 POSTING_READ(DP_A);
925 udelay(500);
926}
927
b934223d 928static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 929{
b934223d 930 struct drm_device *dev = encoder->base.dev;
417e822d 931 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 932 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 933 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 934 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
935 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 936
417e822d 937 /*
1a2eb460 938 * There are four kinds of DP registers:
417e822d
KP		 939 *
940 * IBX PCH
1a2eb460
KP		 941 * SNB CPU
942 * IVB CPU
417e822d
KP		 943 * CPT PCH
944 *
945 * IBX PCH and CPU are the same for almost everything,
946 * except that the CPU DP PLL is configured in this
947 * register
948 *
949 * CPT PCH is quite different, having many bits moved
950 * to the TRANS_DP_CTL register instead. That
951 * configuration happens (oddly) in ironlake_pch_enable
952 */
9c9e7927 953
417e822d
KP		 954 /* Preserve the BIOS-computed detected bit. This is
955 * supposed to be read-only.
956 */
957 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 958
417e822d 959 /* Handle DP bits in common between all three register formats */
417e822d 960 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 961 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 962
9ed109a7 963 if (crtc->config.has_audio) {
e0dac65e 964 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 965 pipe_name(crtc->pipe));
ea5b213a 966 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 967 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 968 }
247d89f6 969
417e822d 970 /* Split out the IBX/CPU vs CPT settings */
32f9d658 971
bc7d38a4 972 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 973 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
974 intel_dp->DP |= DP_SYNC_HS_HIGH;
975 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
976 intel_dp->DP |= DP_SYNC_VS_HIGH;
977 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
978
6aba5b6c 979 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 980 intel_dp->DP |= DP_ENHANCED_FRAMING;
981
7c62a164 982 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 983 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 984 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 985 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 986
987 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
988 intel_dp->DP |= DP_SYNC_HS_HIGH;
989 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
990 intel_dp->DP |= DP_SYNC_VS_HIGH;
991 intel_dp->DP |= DP_LINK_TRAIN_OFF;
992
6aba5b6c 993 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 994 intel_dp->DP |= DP_ENHANCED_FRAMING;
995
44f37d1f
CML		 996 if (!IS_CHERRYVIEW(dev)) {
997 if (crtc->pipe == 1)
998 intel_dp->DP |= DP_PIPEB_SELECT;
999 } else {
1000 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1001 }
417e822d
KP		 1002 } else {
1003 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1004 }
a4fc5ed6
KP		 1005}
1006
ffd6749d
PZ		 1007#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1009
1a5ef5b7
PZ		 1010#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1011#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1012
ffd6749d
PZ		 1013#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1014#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1015
4be73780 1016static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1017 u32 mask,
1018 u32 value)
bd943159 1019{
30add22d 1020 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1021 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1022 u32 pp_stat_reg, pp_ctrl_reg;
1023
bf13e81b
JN		 1024 pp_stat_reg = _pp_stat_reg(intel_dp);
1025 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1026
99ea7127 1027 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1028 mask, value,
1029 I915_READ(pp_stat_reg),
1030 I915_READ(pp_ctrl_reg));
32ce697c 1031
453c5420 1032 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1033 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1034 I915_READ(pp_stat_reg),
1035 I915_READ(pp_ctrl_reg));
32ce697c 1036 }
54c136d4
CW		 1037
1038 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1039}
32ce697c 1040
4be73780 1041static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1042{
1043 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1044 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1045}
1046
4be73780 1047static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1048{
1049 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1050 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1051}
1052
4be73780 1053static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1054{
1055 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1056
1057 /* When we disable the VDD override bit last we have to do the manual
1058 * wait. */
1059 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1060 intel_dp->panel_power_cycle_delay);
1061
4be73780 1062 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1063}
1064
4be73780 1065static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1066{
1067 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1068 intel_dp->backlight_on_delay);
1069}
1070
4be73780 1071static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1072{
1073 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1074 intel_dp->backlight_off_delay);
1075}
99ea7127 1076
832dd3c1
KP		 1077/* Read the current pp_control value, unlocking the register if it
1078 * is locked
1079 */
1080
453c5420 1081static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1082{
453c5420
JB		 1083 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1084 struct drm_i915_private *dev_priv = dev->dev_private;
1085 u32 control;
832dd3c1 1086
bf13e81b 1087 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1088 control &= ~PANEL_UNLOCK_MASK;
1089 control |= PANEL_UNLOCK_REGS;
1090 return control;
bd943159
KP		 1091}
1092
adddaaf4 1093static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1094{
30add22d 1095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1096 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1097 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1098 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1099 enum intel_display_power_domain power_domain;
5d613501 1100 u32 pp;
453c5420 1101 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1102 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1103
97af61f5 1104 if (!is_edp(intel_dp))
adddaaf4 1105 return false;
bd943159
KP		 1106
1107 intel_dp->want_panel_vdd = true;
99ea7127 1108
4be73780 1109 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1110 return need_to_disable;
b0665d57 1111
4e6e1a54
ID		 1112 power_domain = intel_display_port_power_domain(intel_encoder);
1113 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1114
b0665d57 1115 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1116
4be73780
DV		 1117 if (!edp_have_panel_power(intel_dp))
1118 wait_panel_power_cycle(intel_dp);
99ea7127 1119
453c5420 1120 pp = ironlake_get_pp_control(intel_dp);
5d613501 1121 pp |= EDP_FORCE_VDD;
ebf33b18 1122
bf13e81b
JN		 1123 pp_stat_reg = _pp_stat_reg(intel_dp);
1124 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1125
1126 I915_WRITE(pp_ctrl_reg, pp);
1127 POSTING_READ(pp_ctrl_reg);
1128 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1129 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1130 /*
1131 * If the panel wasn't on, delay before accessing aux channel
1132 */
4be73780 1133 if (!edp_have_panel_power(intel_dp)) {
bd943159 1134 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1135 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1136 }
adddaaf4
JN		 1137
1138 return need_to_disable;
1139}
1140
b80d6c78 1141void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1142{
1143 if (is_edp(intel_dp)) {
1144 bool vdd = _edp_panel_vdd_on(intel_dp);
1145
1146 WARN(!vdd, "eDP VDD already requested on\n");
1147 }
5d613501
JB		 1148}
1149
4be73780 1150static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1151{
30add22d 1152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 u32 pp;
453c5420 1155 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1156
a0e99e68
DV		 1157 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1158
4be73780 1159 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1160 struct intel_digital_port *intel_dig_port =
1161 dp_to_dig_port(intel_dp);
1162 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1163 enum intel_display_power_domain power_domain;
1164
b0665d57
PZ		 1165 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1166
453c5420 1167 pp = ironlake_get_pp_control(intel_dp);
bd943159 1168 pp &= ~EDP_FORCE_VDD;
bd943159 1169
9f08ef59
PZ		 1170 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1171 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1172
1173 I915_WRITE(pp_ctrl_reg, pp);
1174 POSTING_READ(pp_ctrl_reg);
99ea7127 1175
453c5420
JB		 1176 /* Make sure sequencer is idle before allowing subsequent activity */
1177 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1178 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1179
1180 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1181 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1182
4e6e1a54
ID		 1183 power_domain = intel_display_port_power_domain(intel_encoder);
1184 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1185 }
1186}
5d613501 1187
4be73780 1188static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1189{
1190 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1191 struct intel_dp, panel_vdd_work);
30add22d 1192 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1193
627f7675 1194 mutex_lock(&dev->mode_config.mutex);
4be73780 1195 edp_panel_vdd_off_sync(intel_dp);
627f7675 1196 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1197}
1198
4be73780 1199static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1200{
97af61f5
KP		 1201 if (!is_edp(intel_dp))
1202 return;
5d613501 1203
bd943159 1204 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1205
bd943159
KP		 1206 intel_dp->want_panel_vdd = false;
1207
1208 if (sync) {
4be73780 1209 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1210 } else {
1211 /*
1212 * Queue the timer to fire a long
1213 * time from now (relative to the power down delay)
1214 * to keep the panel power up across a sequence of operations
1215 */
1216 schedule_delayed_work(&intel_dp->panel_vdd_work,
1217 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1218 }
5d613501
JB		 1219}
1220
4be73780 1221void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1222{
30add22d 1223 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1224 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1225 u32 pp;
453c5420 1226 u32 pp_ctrl_reg;
9934c132 1227
97af61f5 1228 if (!is_edp(intel_dp))
bd943159 1229 return;
99ea7127
KP		 1230
1231 DRM_DEBUG_KMS("Turn eDP power on\n");
1232
4be73780 1233 if (edp_have_panel_power(intel_dp)) {
99ea7127 1234 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1235 return;
99ea7127 1236 }
9934c132 1237
4be73780 1238 wait_panel_power_cycle(intel_dp);
37c6c9b0 1239
bf13e81b 1240 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1241 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1242 if (IS_GEN5(dev)) {
1243 /* ILK workaround: disable reset around power sequence */
1244 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
05ce1a49 1247 }
37c6c9b0 1248
1c0ae80a 1249 pp |= POWER_TARGET_ON;
99ea7127
KP		 1250 if (!IS_GEN5(dev))
1251 pp |= PANEL_POWER_RESET;
1252
453c5420
JB		 1253 I915_WRITE(pp_ctrl_reg, pp);
1254 POSTING_READ(pp_ctrl_reg);
9934c132 1255
4be73780 1256 wait_panel_on(intel_dp);
dce56b3c 1257 intel_dp->last_power_on = jiffies;
9934c132 1258
05ce1a49
KP		 1259 if (IS_GEN5(dev)) {
1260 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1261 I915_WRITE(pp_ctrl_reg, pp);
1262 POSTING_READ(pp_ctrl_reg);
05ce1a49 1263 }
9934c132
JB		 1264}
1265
4be73780 1266void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1267{
4e6e1a54
ID		 1268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1269 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1270 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1271 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1272 enum intel_display_power_domain power_domain;
99ea7127 1273 u32 pp;
453c5420 1274 u32 pp_ctrl_reg;
9934c132 1275
97af61f5
KP		 1276 if (!is_edp(intel_dp))
1277 return;
37c6c9b0 1278
99ea7127 1279 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1280
4be73780 1281 edp_wait_backlight_off(intel_dp);
dce56b3c 1282
24f3e092
JN		 1283 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1284
453c5420 1285 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1286 /* We need to switch off panel power _and_ force vdd, for otherwise some
1287 * panels get very unhappy and cease to work. */
b3064154
PJ		 1288 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1289 EDP_BLC_ENABLE);
453c5420 1290
bf13e81b 1291 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1292
849e39f5
PZ		 1293 intel_dp->want_panel_vdd = false;
1294
453c5420
JB		 1295 I915_WRITE(pp_ctrl_reg, pp);
1296 POSTING_READ(pp_ctrl_reg);
9934c132 1297
dce56b3c 1298 intel_dp->last_power_cycle = jiffies;
4be73780 1299 wait_panel_off(intel_dp);
849e39f5
PZ		 1300
1301 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1302 power_domain = intel_display_port_power_domain(intel_encoder);
1303 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1304}
1305
4be73780 1306void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1307{
da63a9f2
PZ		 1308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 u32 pp;
453c5420 1312 u32 pp_ctrl_reg;
32f9d658 1313
f01eca2e
KP		 1314 if (!is_edp(intel_dp))
1315 return;
1316
28c97730 1317 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1318 /*
1319 * If we enable the backlight right away following a panel power
1320 * on, we may see slight flicker as the panel syncs with the eDP
1321 * link. So delay a bit to make sure the image is solid before
1322 * allowing it to appear.
1323 */
4be73780 1324 wait_backlight_on(intel_dp);
453c5420 1325 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1326 pp |= EDP_BLC_ENABLE;
453c5420 1327
bf13e81b 1328 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1329
1330 I915_WRITE(pp_ctrl_reg, pp);
1331 POSTING_READ(pp_ctrl_reg);
035aa3de 1332
752aa88a 1333 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1334}
1335
4be73780 1336void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1337{
30add22d 1338 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1339 struct drm_i915_private *dev_priv = dev->dev_private;
1340 u32 pp;
453c5420 1341 u32 pp_ctrl_reg;
32f9d658 1342
f01eca2e
KP		 1343 if (!is_edp(intel_dp))
1344 return;
1345
752aa88a 1346 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1347
28c97730 1348 DRM_DEBUG_KMS("\n");
453c5420 1349 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1350 pp &= ~EDP_BLC_ENABLE;
453c5420 1351
bf13e81b 1352 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1353
1354 I915_WRITE(pp_ctrl_reg, pp);
1355 POSTING_READ(pp_ctrl_reg);
dce56b3c 1356 intel_dp->last_backlight_off = jiffies;
32f9d658 1357}
a4fc5ed6 1358
2bd2ad64 1359static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1360{
da63a9f2
PZ		 1361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1362 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1363 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 u32 dpa_ctl;
1366
2bd2ad64
DV		 1367 assert_pipe_disabled(dev_priv,
1368 to_intel_crtc(crtc)->pipe);
1369
d240f20f
JB		 1370 DRM_DEBUG_KMS("\n");
1371 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1372 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1373 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1374
1375 /* We don't adjust intel_dp->DP while tearing down the link, to
1376 * facilitate link retraining (e.g. after hotplug). Hence clear all
1377 * enable bits here to ensure that we don't enable too much. */
1378 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1379 intel_dp->DP |= DP_PLL_ENABLE;
1380 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1381 POSTING_READ(DP_A);
1382 udelay(200);
d240f20f
JB		 1383}
1384
2bd2ad64 1385static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1386{
da63a9f2
PZ		 1387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1388 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1389 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 u32 dpa_ctl;
1392
2bd2ad64
DV		 1393 assert_pipe_disabled(dev_priv,
1394 to_intel_crtc(crtc)->pipe);
1395
d240f20f 1396 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1397 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1398 "dp pll off, should be on\n");
1399 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1400
1401 /* We can't rely on the value tracked for the DP register in
1402 * intel_dp->DP because link_down must not change that (otherwise link
1403 * re-training will fail. */
298b0b39 1404 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1405 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1406 POSTING_READ(DP_A);
d240f20f
JB		 1407 udelay(200);
1408}
1409
c7ad3810 1410/* If the sink supports it, try to set the power state appropriately */
c19b0669 1411void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1412{
1413 int ret, i;
1414
1415 /* Should have a valid DPCD by this point */
1416 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1417 return;
1418
1419 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1420 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1421 DP_SET_POWER_D3);
c7ad3810
JB		 1422 if (ret != 1)
1423 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1424 } else {
1425 /*
1426 * When turning on, we need to retry for 1ms to give the sink
1427 * time to wake up.
1428 */
1429 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1430 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1431 DP_SET_POWER_D0);
c7ad3810
JB		 1432 if (ret == 1)
1433 break;
1434 msleep(1);
1435 }
1436 }
1437}
1438
19d8fe15
DV		 1439static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1440 enum pipe *pipe)
d240f20f 1441{
19d8fe15 1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1443 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1446 enum intel_display_power_domain power_domain;
1447 u32 tmp;
1448
1449 power_domain = intel_display_port_power_domain(encoder);
1450 if (!intel_display_power_enabled(dev_priv, power_domain))
1451 return false;
1452
1453 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1454
1455 if (!(tmp & DP_PORT_EN))
1456 return false;
1457
bc7d38a4 1458 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1459 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1460 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1461 *pipe = PORT_TO_PIPE(tmp);
1462 } else {
1463 u32 trans_sel;
1464 u32 trans_dp;
1465 int i;
1466
1467 switch (intel_dp->output_reg) {
1468 case PCH_DP_B:
1469 trans_sel = TRANS_DP_PORT_SEL_B;
1470 break;
1471 case PCH_DP_C:
1472 trans_sel = TRANS_DP_PORT_SEL_C;
1473 break;
1474 case PCH_DP_D:
1475 trans_sel = TRANS_DP_PORT_SEL_D;
1476 break;
1477 default:
1478 return true;
1479 }
1480
1481 for_each_pipe(i) {
1482 trans_dp = I915_READ(TRANS_DP_CTL(i));
1483 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1484 *pipe = i;
1485 return true;
1486 }
1487 }
19d8fe15 1488
4a0833ec
DV		 1489 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1490 intel_dp->output_reg);
1491 }
d240f20f 1492
19d8fe15
DV		 1493 return true;
1494}
d240f20f 1495
045ac3b5
JB		 1496static void intel_dp_get_config(struct intel_encoder *encoder,
1497 struct intel_crtc_config *pipe_config)
1498{
1499 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1500 u32 tmp, flags = 0;
63000ef6
XZ		 1501 struct drm_device *dev = encoder->base.dev;
1502 struct drm_i915_private *dev_priv = dev->dev_private;
1503 enum port port = dp_to_dig_port(intel_dp)->port;
1504 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1505 int dotclock;
045ac3b5 1506
9ed109a7
DV		 1507 tmp = I915_READ(intel_dp->output_reg);
1508 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1509 pipe_config->has_audio = true;
1510
63000ef6 1511 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1512 if (tmp & DP_SYNC_HS_HIGH)
1513 flags |= DRM_MODE_FLAG_PHSYNC;
1514 else
1515 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1516
63000ef6
XZ		 1517 if (tmp & DP_SYNC_VS_HIGH)
1518 flags |= DRM_MODE_FLAG_PVSYNC;
1519 else
1520 flags |= DRM_MODE_FLAG_NVSYNC;
1521 } else {
1522 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1523 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1524 flags |= DRM_MODE_FLAG_PHSYNC;
1525 else
1526 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1527
63000ef6
XZ		 1528 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1529 flags |= DRM_MODE_FLAG_PVSYNC;
1530 else
1531 flags |= DRM_MODE_FLAG_NVSYNC;
1532 }
045ac3b5
JB		 1533
1534 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1535
eb14cb74
VS		 1536 pipe_config->has_dp_encoder = true;
1537
1538 intel_dp_get_m_n(crtc, pipe_config);
1539
18442d08 1540 if (port == PORT_A) {
f1f644dc
JB		 1541 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1542 pipe_config->port_clock = 162000;
1543 else
1544 pipe_config->port_clock = 270000;
1545 }
18442d08
VS		 1546
1547 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1548 &pipe_config->dp_m_n);
1549
1550 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1551 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1552
241bfc38 1553 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1554
c6cd2ee2
JN		 1555 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1556 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1557 /*
1558 * This is a big fat ugly hack.
1559 *
1560 * Some machines in UEFI boot mode provide us a VBT that has 18
1561 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1562 * unknown we fail to light up. Yet the same BIOS boots up with
1563 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1564 * max, not what it tells us to use.
1565 *
1566 * Note: This will still be broken if the eDP panel is not lit
1567 * up by the BIOS, and thus we can't get the mode at module
1568 * load.
1569 */
1570 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1571 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1572 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1573 }
045ac3b5
JB		 1574}
1575
a031d709 1576static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1577{
a031d709
RV		 1578 struct drm_i915_private *dev_priv = dev->dev_private;
1579
1580 return dev_priv->psr.sink_support;
2293bb5c
SK		 1581}
1582
2b28bb1b
RV		 1583static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1584{
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586
18b5992c 1587 if (!HAS_PSR(dev))
2b28bb1b
RV		 1588 return false;
1589
18b5992c 1590 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1591}
1592
1593static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1594 struct edp_vsc_psr *vsc_psr)
1595{
1596 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1597 struct drm_device *dev = dig_port->base.base.dev;
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1600 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1601 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1602 uint32_t *data = (uint32_t *) vsc_psr;
1603 unsigned int i;
1604
1605 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1606 the video DIP being updated before program video DIP data buffer
1607 registers for DIP being updated. */
1608 I915_WRITE(ctl_reg, 0);
1609 POSTING_READ(ctl_reg);
1610
1611 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1612 if (i < sizeof(struct edp_vsc_psr))
1613 I915_WRITE(data_reg + i, *data++);
1614 else
1615 I915_WRITE(data_reg + i, 0);
1616 }
1617
1618 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1619 POSTING_READ(ctl_reg);
1620}
1621
1622static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1623{
1624 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1625 struct drm_i915_private *dev_priv = dev->dev_private;
1626 struct edp_vsc_psr psr_vsc;
1627
1628 if (intel_dp->psr_setup_done)
1629 return;
1630
1631 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1632 memset(&psr_vsc, 0, sizeof(psr_vsc));
1633 psr_vsc.sdp_header.HB0 = 0;
1634 psr_vsc.sdp_header.HB1 = 0x7;
1635 psr_vsc.sdp_header.HB2 = 0x2;
1636 psr_vsc.sdp_header.HB3 = 0x8;
1637 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1638
1639 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1640 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1641 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1642
1643 intel_dp->psr_setup_done = true;
1644}
1645
1646static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1647{
1648 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1649 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1650 uint32_t aux_clock_divider;
2b28bb1b
RV		 1651 int precharge = 0x3;
1652 int msg_size = 5; /* Header(4) + Message(1) */
1653
ec5b01dd
DL		 1654 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1655
2b28bb1b
RV		 1656 /* Enable PSR in sink */
1657 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1658 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1659 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1660 else
9d1a1031
JN		 1661 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1662 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1663
1664 /* Setup AUX registers */
18b5992c
BW		 1665 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1666 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1667 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1668 DP_AUX_CH_CTL_TIME_OUT_400us |
1669 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1670 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1671 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1672}
1673
1674static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1675{
1676 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1677 struct drm_i915_private *dev_priv = dev->dev_private;
1678 uint32_t max_sleep_time = 0x1f;
1679 uint32_t idle_frames = 1;
1680 uint32_t val = 0x0;
ed8546ac 1681 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1682
1683 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1684 val |= EDP_PSR_LINK_STANDBY;
1685 val |= EDP_PSR_TP2_TP3_TIME_0us;
1686 val |= EDP_PSR_TP1_TIME_0us;
1687 val |= EDP_PSR_SKIP_AUX_EXIT;
1688 } else
1689 val |= EDP_PSR_LINK_DISABLE;
1690
18b5992c 1691 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1692 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1693 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1694 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1695 EDP_PSR_ENABLE);
1696}
1697
3f51e471
RV		 1698static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1699{
1700 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1701 struct drm_device *dev = dig_port->base.base.dev;
1702 struct drm_i915_private *dev_priv = dev->dev_private;
1703 struct drm_crtc *crtc = dig_port->base.base.crtc;
1704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1705 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1706 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1707
a031d709
RV		 1708 dev_priv->psr.source_ok = false;
1709
18b5992c 1710 if (!HAS_PSR(dev)) {
3f51e471 1711 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1712 return false;
1713 }
1714
1715 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1716 (dig_port->port != PORT_A)) {
1717 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1718 return false;
1719 }
1720
d330a953 1721 if (!i915.enable_psr) {
105b7c11 1722 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1723 return false;
1724 }
1725
cd234b0b
CW		 1726 crtc = dig_port->base.base.crtc;
1727 if (crtc == NULL) {
1728 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1729 return false;
1730 }
1731
1732 intel_crtc = to_intel_crtc(crtc);
20ddf665 1733 if (!intel_crtc_active(crtc)) {
3f51e471 1734 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1735 return false;
1736 }
1737
f4510a27 1738 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1739 if (obj->tiling_mode != I915_TILING_X ||
1740 obj->fence_reg == I915_FENCE_REG_NONE) {
1741 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1742 return false;
1743 }
1744
1745 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1746 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1747 return false;
1748 }
1749
1750 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1751 S3D_ENABLE) {
1752 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1753 return false;
1754 }
1755
ca73b4f0 1756 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1757 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1758 return false;
1759 }
1760
a031d709 1761 dev_priv->psr.source_ok = true;
3f51e471
RV		 1762 return true;
1763}
1764
3d739d92 1765static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1766{
1767 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1768
3f51e471
RV		 1769 if (!intel_edp_psr_match_conditions(intel_dp) ||
1770 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1771 return;
1772
1773 /* Setup PSR once */
1774 intel_edp_psr_setup(intel_dp);
1775
1776 /* Enable PSR on the panel */
1777 intel_edp_psr_enable_sink(intel_dp);
1778
1779 /* Enable PSR on the host */
1780 intel_edp_psr_enable_source(intel_dp);
1781}
1782
3d739d92
RV		 1783void intel_edp_psr_enable(struct intel_dp *intel_dp)
1784{
1785 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1786
1787 if (intel_edp_psr_match_conditions(intel_dp) &&
1788 !intel_edp_is_psr_enabled(dev))
1789 intel_edp_psr_do_enable(intel_dp);
1790}
1791
2b28bb1b
RV		 1792void intel_edp_psr_disable(struct intel_dp *intel_dp)
1793{
1794 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1795 struct drm_i915_private *dev_priv = dev->dev_private;
1796
1797 if (!intel_edp_is_psr_enabled(dev))
1798 return;
1799
18b5992c
BW		 1800 I915_WRITE(EDP_PSR_CTL(dev),
1801 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1802
1803 /* Wait till PSR is idle */
18b5992c 1804 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1805 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1806 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1807}
1808
3d739d92
RV		 1809void intel_edp_psr_update(struct drm_device *dev)
1810{
1811 struct intel_encoder *encoder;
1812 struct intel_dp *intel_dp = NULL;
1813
1814 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1815 if (encoder->type == INTEL_OUTPUT_EDP) {
1816 intel_dp = enc_to_intel_dp(&encoder->base);
1817
a031d709 1818 if (!is_edp_psr(dev))
3d739d92
RV		 1819 return;
1820
1821 if (!intel_edp_psr_match_conditions(intel_dp))
1822 intel_edp_psr_disable(intel_dp);
1823 else
1824 if (!intel_edp_is_psr_enabled(dev))
1825 intel_edp_psr_do_enable(intel_dp);
1826 }
1827}
1828
e8cb4558 1829static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1830{
e8cb4558 1831 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1832 enum port port = dp_to_dig_port(intel_dp)->port;
1833 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1834
1835 /* Make sure the panel is off before trying to change the mode. But also
1836 * ensure that we have vdd while we switch off the panel. */
24f3e092 1837 intel_edp_panel_vdd_on(intel_dp);
4be73780 1838 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1839 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1840 intel_edp_panel_off(intel_dp);
3739850b
DV		 1841
1842 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1843 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1844 intel_dp_link_down(intel_dp);
d240f20f
JB		 1845}
1846
49277c31 1847static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1848{
2bd2ad64 1849 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1850 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1851
49277c31
VS		 1852 if (port != PORT_A)
1853 return;
1854
1855 intel_dp_link_down(intel_dp);
1856 ironlake_edp_pll_off(intel_dp);
1857}
1858
1859static void vlv_post_disable_dp(struct intel_encoder *encoder)
1860{
1861 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1862
1863 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1864}
1865
e8cb4558 1866static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1867{
e8cb4558
DV		 1868 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1869 struct drm_device *dev = encoder->base.dev;
1870 struct drm_i915_private *dev_priv = dev->dev_private;
1871 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1872
0c33d8d7
DV		 1873 if (WARN_ON(dp_reg & DP_PORT_EN))
1874 return;
5d613501 1875
24f3e092 1876 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1877 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1878 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1879 intel_edp_panel_on(intel_dp);
1880 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1881 intel_dp_complete_link_train(intel_dp);
3ab9c637 1882 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1883}
89b667f8 1884
ecff4f3b
JN		 1885static void g4x_enable_dp(struct intel_encoder *encoder)
1886{
828f5c6e
JN		 1887 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1888
ecff4f3b 1889 intel_enable_dp(encoder);
4be73780 1890 intel_edp_backlight_on(intel_dp);
ab1f90f9 1891}
89b667f8 1892
ab1f90f9
JN		 1893static void vlv_enable_dp(struct intel_encoder *encoder)
1894{
828f5c6e
JN		 1895 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1896
4be73780 1897 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1898}
1899
ecff4f3b 1900static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1901{
1902 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1903 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1904
d41f1efb
DV		 1905 /* Only ilk+ has port A */
1906 if (dport->port == PORT_A) {
1907 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 1908 ironlake_edp_pll_on(intel_dp);
d41f1efb 1909 }
ab1f90f9
JN		 1910}
1911
1912static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1913{
2bd2ad64 1914 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1915 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1916 struct drm_device *dev = encoder->base.dev;
89b667f8 1917 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1918 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1919 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1920 int pipe = intel_crtc->pipe;
bf13e81b 1921 struct edp_power_seq power_seq;
ab1f90f9 1922 u32 val;
a4fc5ed6 1923
ab1f90f9 1924 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1925
ab3c759a 1926 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1927 val = 0;
1928 if (pipe)
1929 val |= (1<<21);
1930 else
1931 val &= ~(1<<21);
1932 val |= 0x001000c4;
ab3c759a
CML		 1933 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1934 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1935 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1936
ab1f90f9
JN		 1937 mutex_unlock(&dev_priv->dpio_lock);
1938
2cac613b
ID		 1939 if (is_edp(intel_dp)) {
1940 /* init power sequencer on this pipe and port */
1941 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1942 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1943 &power_seq);
1944 }
bf13e81b 1945
ab1f90f9
JN		 1946 intel_enable_dp(encoder);
1947
e4607fcf 1948 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1949}
1950
ecff4f3b 1951static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1952{
1953 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1954 struct drm_device *dev = encoder->base.dev;
1955 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1956 struct intel_crtc *intel_crtc =
1957 to_intel_crtc(encoder->base.crtc);
e4607fcf 1958 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1959 int pipe = intel_crtc->pipe;
89b667f8 1960
89b667f8 1961 /* Program Tx lane resets to default */
0980a60f 1962 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1963 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1964 DPIO_PCS_TX_LANE2_RESET |
1965 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1966 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1967 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1968 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1969 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1970 DPIO_PCS_CLK_SOFT_RESET);
1971
1972 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1973 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1974 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1975 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1976 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1977}
1978
e4a1d846
CML		 1979static void chv_pre_enable_dp(struct intel_encoder *encoder)
1980{
1981 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1982 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1983 struct drm_device *dev = encoder->base.dev;
1984 struct drm_i915_private *dev_priv = dev->dev_private;
1985 struct edp_power_seq power_seq;
1986 struct intel_crtc *intel_crtc =
1987 to_intel_crtc(encoder->base.crtc);
1988 enum dpio_channel ch = vlv_dport_to_channel(dport);
1989 int pipe = intel_crtc->pipe;
1990 int data, i;
1991
1992 /* Program Tx lane latency optimal setting*/
1993 mutex_lock(&dev_priv->dpio_lock);
1994 for (i = 0; i < 4; i++) {
1995 /* Set the latency optimal bit */
1996 data = (i == 1) ? 0x0 : 0x6;
1997 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
1998 data << DPIO_FRC_LATENCY_SHFIT);
1999
2000 /* Set the upar bit */
2001 data = (i == 1) ? 0x0 : 0x1;
2002 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2003 data << DPIO_UPAR_SHIFT);
2004 }
2005
2006 /* Data lane stagger programming */
2007 /* FIXME: Fix up value only after power analysis */
2008
2009 mutex_unlock(&dev_priv->dpio_lock);
2010
2011 if (is_edp(intel_dp)) {
2012 /* init power sequencer on this pipe and port */
2013 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2014 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2015 &power_seq);
2016 }
2017
2018 intel_enable_dp(encoder);
2019
2020 vlv_wait_port_ready(dev_priv, dport);
2021}
2022
a4fc5ed6 2023/*
df0c237d
JB		 2024 * Native read with retry for link status and receiver capability reads for
2025 * cases where the sink may still be asleep.
9d1a1031
JN		 2026 *
2027 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2028 * supposed to retry 3 times per the spec.
a4fc5ed6 2029 */
9d1a1031
JN		 2030static ssize_t
2031intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2032 void *buffer, size_t size)
a4fc5ed6 2033{
9d1a1031
JN		 2034 ssize_t ret;
2035 int i;
61da5fab 2036
61da5fab 2037 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2038 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2039 if (ret == size)
2040 return ret;
61da5fab
JB		 2041 msleep(1);
2042 }
a4fc5ed6 2043
9d1a1031 2044 return ret;
a4fc5ed6
KP		 2045}
2046
2047/*
2048 * Fetch AUX CH registers 0x202 - 0x207 which contain
2049 * link status information
2050 */
2051static bool
93f62dad 2052intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2053{
9d1a1031
JN		 2054 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2055 DP_LANE0_1_STATUS,
2056 link_status,
2057 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2058}
2059
a4fc5ed6
KP		 2060/*
2061 * These are source-specific values; current Intel hardware supports
2062 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2063 */
a4fc5ed6
KP		 2064
2065static uint8_t
1a2eb460 2066intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2067{
30add22d 2068 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2069 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2070
8f93f4f1 2071 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2072 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2073 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2074 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2075 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2076 return DP_TRAIN_VOLTAGE_SWING_1200;
2077 else
2078 return DP_TRAIN_VOLTAGE_SWING_800;
2079}
2080
2081static uint8_t
2082intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2083{
30add22d 2084 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2085 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2086
8f93f4f1
PZ		 2087 if (IS_BROADWELL(dev)) {
2088 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2089 case DP_TRAIN_VOLTAGE_SWING_400:
2090 case DP_TRAIN_VOLTAGE_SWING_600:
2091 return DP_TRAIN_PRE_EMPHASIS_6;
2092 case DP_TRAIN_VOLTAGE_SWING_800:
2093 return DP_TRAIN_PRE_EMPHASIS_3_5;
2094 case DP_TRAIN_VOLTAGE_SWING_1200:
2095 default:
2096 return DP_TRAIN_PRE_EMPHASIS_0;
2097 }
2098 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2099 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2100 case DP_TRAIN_VOLTAGE_SWING_400:
2101 return DP_TRAIN_PRE_EMPHASIS_9_5;
2102 case DP_TRAIN_VOLTAGE_SWING_600:
2103 return DP_TRAIN_PRE_EMPHASIS_6;
2104 case DP_TRAIN_VOLTAGE_SWING_800:
2105 return DP_TRAIN_PRE_EMPHASIS_3_5;
2106 case DP_TRAIN_VOLTAGE_SWING_1200:
2107 default:
2108 return DP_TRAIN_PRE_EMPHASIS_0;
2109 }
e2fa6fba
P		 2110 } else if (IS_VALLEYVIEW(dev)) {
2111 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2112 case DP_TRAIN_VOLTAGE_SWING_400:
2113 return DP_TRAIN_PRE_EMPHASIS_9_5;
2114 case DP_TRAIN_VOLTAGE_SWING_600:
2115 return DP_TRAIN_PRE_EMPHASIS_6;
2116 case DP_TRAIN_VOLTAGE_SWING_800:
2117 return DP_TRAIN_PRE_EMPHASIS_3_5;
2118 case DP_TRAIN_VOLTAGE_SWING_1200:
2119 default:
2120 return DP_TRAIN_PRE_EMPHASIS_0;
2121 }
bc7d38a4 2122 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2123 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2124 case DP_TRAIN_VOLTAGE_SWING_400:
2125 return DP_TRAIN_PRE_EMPHASIS_6;
2126 case DP_TRAIN_VOLTAGE_SWING_600:
2127 case DP_TRAIN_VOLTAGE_SWING_800:
2128 return DP_TRAIN_PRE_EMPHASIS_3_5;
2129 default:
2130 return DP_TRAIN_PRE_EMPHASIS_0;
2131 }
2132 } else {
2133 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2134 case DP_TRAIN_VOLTAGE_SWING_400:
2135 return DP_TRAIN_PRE_EMPHASIS_6;
2136 case DP_TRAIN_VOLTAGE_SWING_600:
2137 return DP_TRAIN_PRE_EMPHASIS_6;
2138 case DP_TRAIN_VOLTAGE_SWING_800:
2139 return DP_TRAIN_PRE_EMPHASIS_3_5;
2140 case DP_TRAIN_VOLTAGE_SWING_1200:
2141 default:
2142 return DP_TRAIN_PRE_EMPHASIS_0;
2143 }
a4fc5ed6
KP		 2144 }
2145}
2146
e2fa6fba
P		 2147static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2148{
2149 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2150 struct drm_i915_private *dev_priv = dev->dev_private;
2151 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2152 struct intel_crtc *intel_crtc =
2153 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2154 unsigned long demph_reg_value, preemph_reg_value,
2155 uniqtranscale_reg_value;
2156 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2157 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2158 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2159
2160 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2161 case DP_TRAIN_PRE_EMPHASIS_0:
2162 preemph_reg_value = 0x0004000;
2163 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2164 case DP_TRAIN_VOLTAGE_SWING_400:
2165 demph_reg_value = 0x2B405555;
2166 uniqtranscale_reg_value = 0x552AB83A;
2167 break;
2168 case DP_TRAIN_VOLTAGE_SWING_600:
2169 demph_reg_value = 0x2B404040;
2170 uniqtranscale_reg_value = 0x5548B83A;
2171 break;
2172 case DP_TRAIN_VOLTAGE_SWING_800:
2173 demph_reg_value = 0x2B245555;
2174 uniqtranscale_reg_value = 0x5560B83A;
2175 break;
2176 case DP_TRAIN_VOLTAGE_SWING_1200:
2177 demph_reg_value = 0x2B405555;
2178 uniqtranscale_reg_value = 0x5598DA3A;
2179 break;
2180 default:
2181 return 0;
2182 }
2183 break;
2184 case DP_TRAIN_PRE_EMPHASIS_3_5:
2185 preemph_reg_value = 0x0002000;
2186 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2187 case DP_TRAIN_VOLTAGE_SWING_400:
2188 demph_reg_value = 0x2B404040;
2189 uniqtranscale_reg_value = 0x5552B83A;
2190 break;
2191 case DP_TRAIN_VOLTAGE_SWING_600:
2192 demph_reg_value = 0x2B404848;
2193 uniqtranscale_reg_value = 0x5580B83A;
2194 break;
2195 case DP_TRAIN_VOLTAGE_SWING_800:
2196 demph_reg_value = 0x2B404040;
2197 uniqtranscale_reg_value = 0x55ADDA3A;
2198 break;
2199 default:
2200 return 0;
2201 }
2202 break;
2203 case DP_TRAIN_PRE_EMPHASIS_6:
2204 preemph_reg_value = 0x0000000;
2205 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2206 case DP_TRAIN_VOLTAGE_SWING_400:
2207 demph_reg_value = 0x2B305555;
2208 uniqtranscale_reg_value = 0x5570B83A;
2209 break;
2210 case DP_TRAIN_VOLTAGE_SWING_600:
2211 demph_reg_value = 0x2B2B4040;
2212 uniqtranscale_reg_value = 0x55ADDA3A;
2213 break;
2214 default:
2215 return 0;
2216 }
2217 break;
2218 case DP_TRAIN_PRE_EMPHASIS_9_5:
2219 preemph_reg_value = 0x0006000;
2220 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2221 case DP_TRAIN_VOLTAGE_SWING_400:
2222 demph_reg_value = 0x1B405555;
2223 uniqtranscale_reg_value = 0x55ADDA3A;
2224 break;
2225 default:
2226 return 0;
2227 }
2228 break;
2229 default:
2230 return 0;
2231 }
2232
0980a60f 2233 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2234 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2235 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2236 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2237 uniqtranscale_reg_value);
ab3c759a
CML		 2238 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2239 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2240 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2241 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2242 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2243
2244 return 0;
2245}
2246
e4a1d846
CML		 2247static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2248{
2249 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2252 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2253 u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
2254 uint8_t train_set = intel_dp->train_set[0];
2255 enum dpio_channel ch = vlv_dport_to_channel(dport);
2256 int pipe = intel_crtc->pipe;
2257
2258 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2259 case DP_TRAIN_PRE_EMPHASIS_0:
2260 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2261 case DP_TRAIN_VOLTAGE_SWING_400:
2262 deemph_reg_value = 128;
2263 margin_reg_value = 52;
2264 break;
2265 case DP_TRAIN_VOLTAGE_SWING_600:
2266 deemph_reg_value = 128;
2267 margin_reg_value = 77;
2268 break;
2269 case DP_TRAIN_VOLTAGE_SWING_800:
2270 deemph_reg_value = 128;
2271 margin_reg_value = 102;
2272 break;
2273 case DP_TRAIN_VOLTAGE_SWING_1200:
2274 deemph_reg_value = 128;
2275 margin_reg_value = 154;
2276 /* FIXME extra to set for 1200 */
2277 break;
2278 default:
2279 return 0;
2280 }
2281 break;
2282 case DP_TRAIN_PRE_EMPHASIS_3_5:
2283 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2284 case DP_TRAIN_VOLTAGE_SWING_400:
2285 deemph_reg_value = 85;
2286 margin_reg_value = 78;
2287 break;
2288 case DP_TRAIN_VOLTAGE_SWING_600:
2289 deemph_reg_value = 85;
2290 margin_reg_value = 116;
2291 break;
2292 case DP_TRAIN_VOLTAGE_SWING_800:
2293 deemph_reg_value = 85;
2294 margin_reg_value = 154;
2295 break;
2296 default:
2297 return 0;
2298 }
2299 break;
2300 case DP_TRAIN_PRE_EMPHASIS_6:
2301 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2302 case DP_TRAIN_VOLTAGE_SWING_400:
2303 deemph_reg_value = 64;
2304 margin_reg_value = 104;
2305 break;
2306 case DP_TRAIN_VOLTAGE_SWING_600:
2307 deemph_reg_value = 64;
2308 margin_reg_value = 154;
2309 break;
2310 default:
2311 return 0;
2312 }
2313 break;
2314 case DP_TRAIN_PRE_EMPHASIS_9_5:
2315 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2316 case DP_TRAIN_VOLTAGE_SWING_400:
2317 deemph_reg_value = 43;
2318 margin_reg_value = 154;
2319 break;
2320 default:
2321 return 0;
2322 }
2323 break;
2324 default:
2325 return 0;
2326 }
2327
2328 mutex_lock(&dev_priv->dpio_lock);
2329
2330 /* Clear calc init */
2331 vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
2332
2333 /* Program swing deemph */
2334 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
2335 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2336 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2337 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
2338
2339 /* Program swing margin */
2340 tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
2341 tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
2342 tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2343 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2344
2345 /* Disable unique transition scale */
2346 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2347 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2348 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2349
2350 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2351 == DP_TRAIN_PRE_EMPHASIS_0) &&
2352 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2353 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2354
2355 /*
2356 * The document said it needs to set bit 27 for ch0 and bit 26
2357 * for ch1. Might be a typo in the doc.
2358 * For now, for this unique transition scale selection, set bit
2359 * 27 for ch0 and ch1.
2360 */
2361 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2362 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2363 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2364
2365 tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2366 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2367 }
2368
2369 /* Start swing calculation */
2370 vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
2371 (DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
2372
2373 /* LRC Bypass */
2374 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2375 val |= DPIO_LRC_BYPASS;
2376 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2377
2378 mutex_unlock(&dev_priv->dpio_lock);
2379
2380 return 0;
2381}
2382
a4fc5ed6 2383static void
0301b3ac
JN		 2384intel_get_adjust_train(struct intel_dp *intel_dp,
2385 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2386{
2387 uint8_t v = 0;
2388 uint8_t p = 0;
2389 int lane;
1a2eb460
KP		 2390 uint8_t voltage_max;
2391 uint8_t preemph_max;
a4fc5ed6 2392
33a34e4e 2393 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2394 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2395 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2396
2397 if (this_v > v)
2398 v = this_v;
2399 if (this_p > p)
2400 p = this_p;
2401 }
2402
1a2eb460 2403 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2404 if (v >= voltage_max)
2405 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2406
1a2eb460
KP		 2407 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2408 if (p >= preemph_max)
2409 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2410
2411 for (lane = 0; lane < 4; lane++)
33a34e4e 2412 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2413}
2414
2415static uint32_t
f0a3424e 2416intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2417{
3cf2efb1 2418 uint32_t signal_levels = 0;
a4fc5ed6 2419
3cf2efb1 2420 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2421 case DP_TRAIN_VOLTAGE_SWING_400:
2422 default:
2423 signal_levels |= DP_VOLTAGE_0_4;
2424 break;
2425 case DP_TRAIN_VOLTAGE_SWING_600:
2426 signal_levels |= DP_VOLTAGE_0_6;
2427 break;
2428 case DP_TRAIN_VOLTAGE_SWING_800:
2429 signal_levels |= DP_VOLTAGE_0_8;
2430 break;
2431 case DP_TRAIN_VOLTAGE_SWING_1200:
2432 signal_levels |= DP_VOLTAGE_1_2;
2433 break;
2434 }
3cf2efb1 2435 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2436 case DP_TRAIN_PRE_EMPHASIS_0:
2437 default:
2438 signal_levels |= DP_PRE_EMPHASIS_0;
2439 break;
2440 case DP_TRAIN_PRE_EMPHASIS_3_5:
2441 signal_levels |= DP_PRE_EMPHASIS_3_5;
2442 break;
2443 case DP_TRAIN_PRE_EMPHASIS_6:
2444 signal_levels |= DP_PRE_EMPHASIS_6;
2445 break;
2446 case DP_TRAIN_PRE_EMPHASIS_9_5:
2447 signal_levels |= DP_PRE_EMPHASIS_9_5;
2448 break;
2449 }
2450 return signal_levels;
2451}
2452
e3421a18
ZW		 2453/* Gen6's DP voltage swing and pre-emphasis control */
2454static uint32_t
2455intel_gen6_edp_signal_levels(uint8_t train_set)
2456{
3c5a62b5
YL		 2457 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2458 DP_TRAIN_PRE_EMPHASIS_MASK);
2459 switch (signal_levels) {
e3421a18 2460 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2461 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2462 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2463 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2464 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2465 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2466 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2467 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2468 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2469 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2470 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2471 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2472 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2473 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2474 default:
3c5a62b5
YL		 2475 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2476 "0x%x\n", signal_levels);
2477 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2478 }
2479}
2480
1a2eb460
KP		 2481/* Gen7's DP voltage swing and pre-emphasis control */
2482static uint32_t
2483intel_gen7_edp_signal_levels(uint8_t train_set)
2484{
2485 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2486 DP_TRAIN_PRE_EMPHASIS_MASK);
2487 switch (signal_levels) {
2488 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2489 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2490 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2491 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2492 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2493 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2494
2495 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2496 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2497 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2498 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2499
2500 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2501 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2502 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2503 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2504
2505 default:
2506 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2507 "0x%x\n", signal_levels);
2508 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2509 }
2510}
2511
d6c0d722
PZ		 2512/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2513static uint32_t
f0a3424e 2514intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2515{
d6c0d722
PZ		 2516 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2517 DP_TRAIN_PRE_EMPHASIS_MASK);
2518 switch (signal_levels) {
2519 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2520 return DDI_BUF_EMP_400MV_0DB_HSW;
2521 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2522 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2523 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2524 return DDI_BUF_EMP_400MV_6DB_HSW;
2525 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2526 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2527
d6c0d722
PZ		 2528 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2529 return DDI_BUF_EMP_600MV_0DB_HSW;
2530 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2531 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2532 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2533 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2534
d6c0d722
PZ		 2535 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2536 return DDI_BUF_EMP_800MV_0DB_HSW;
2537 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2538 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2539 default:
2540 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2541 "0x%x\n", signal_levels);
2542 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2543 }
a4fc5ed6
KP		 2544}
2545
8f93f4f1
PZ		 2546static uint32_t
2547intel_bdw_signal_levels(uint8_t train_set)
2548{
2549 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2550 DP_TRAIN_PRE_EMPHASIS_MASK);
2551 switch (signal_levels) {
2552 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2553 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2554 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2555 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2556 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2557 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2558
2559 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2560 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2561 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2562 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2563 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2564 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2565
2566 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2567 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2568 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2569 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2570
2571 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2572 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2573
2574 default:
2575 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2576 "0x%x\n", signal_levels);
2577 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2578 }
2579}
2580
f0a3424e
PZ		 2581/* Properly updates "DP" with the correct signal levels. */
2582static void
2583intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2584{
2585 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2586 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2587 struct drm_device *dev = intel_dig_port->base.base.dev;
2588 uint32_t signal_levels, mask;
2589 uint8_t train_set = intel_dp->train_set[0];
2590
8f93f4f1
PZ		 2591 if (IS_BROADWELL(dev)) {
2592 signal_levels = intel_bdw_signal_levels(train_set);
2593 mask = DDI_BUF_EMP_MASK;
2594 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2595 signal_levels = intel_hsw_signal_levels(train_set);
2596 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2597 } else if (IS_CHERRYVIEW(dev)) {
2598 signal_levels = intel_chv_signal_levels(intel_dp);
2599 mask = 0;
e2fa6fba
P		 2600 } else if (IS_VALLEYVIEW(dev)) {
2601 signal_levels = intel_vlv_signal_levels(intel_dp);
2602 mask = 0;
bc7d38a4 2603 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2604 signal_levels = intel_gen7_edp_signal_levels(train_set);
2605 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2606 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2607 signal_levels = intel_gen6_edp_signal_levels(train_set);
2608 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2609 } else {
2610 signal_levels = intel_gen4_signal_levels(train_set);
2611 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2612 }
2613
2614 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2615
2616 *DP = (*DP & ~mask) | signal_levels;
2617}
2618
a4fc5ed6 2619static bool
ea5b213a 2620intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2621 uint32_t *DP,
58e10eb9 2622 uint8_t dp_train_pat)
a4fc5ed6 2623{
174edf1f
PZ		 2624 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2625 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2626 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2627 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2628 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2629 int ret, len;
a4fc5ed6 2630
22b8bf17 2631 if (HAS_DDI(dev)) {
3ab9c637 2632 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2633
2634 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2635 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2636 else
2637 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2638
2639 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2640 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2641 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2642 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2643
2644 break;
2645 case DP_TRAINING_PATTERN_1:
2646 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2647 break;
2648 case DP_TRAINING_PATTERN_2:
2649 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2650 break;
2651 case DP_TRAINING_PATTERN_3:
2652 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2653 break;
2654 }
174edf1f 2655 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2656
bc7d38a4 2657 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2658 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2659
2660 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2661 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2662 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2663 break;
2664 case DP_TRAINING_PATTERN_1:
70aff66c 2665 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2666 break;
2667 case DP_TRAINING_PATTERN_2:
70aff66c 2668 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2669 break;
2670 case DP_TRAINING_PATTERN_3:
2671 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2672 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2673 break;
2674 }
2675
2676 } else {
70aff66c 2677 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2678
2679 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2680 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2681 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2682 break;
2683 case DP_TRAINING_PATTERN_1:
70aff66c 2684 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2685 break;
2686 case DP_TRAINING_PATTERN_2:
70aff66c 2687 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2688 break;
2689 case DP_TRAINING_PATTERN_3:
2690 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2691 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2692 break;
2693 }
2694 }
2695
70aff66c 2696 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2697 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2698
2cdfe6c8
JN		 2699 buf[0] = dp_train_pat;
2700 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2701 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2702 /* don't write DP_TRAINING_LANEx_SET on disable */
2703 len = 1;
2704 } else {
2705 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2706 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2707 len = intel_dp->lane_count + 1;
47ea7542 2708 }
a4fc5ed6 2709
9d1a1031
JN		 2710 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2711 buf, len);
2cdfe6c8
JN		 2712
2713 return ret == len;
a4fc5ed6
KP		 2714}
2715
70aff66c
JN		 2716static bool
2717intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2718 uint8_t dp_train_pat)
2719{
953d22e8 2720 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2721 intel_dp_set_signal_levels(intel_dp, DP);
2722 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2723}
2724
2725static bool
2726intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2727 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2728{
2729 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2730 struct drm_device *dev = intel_dig_port->base.base.dev;
2731 struct drm_i915_private *dev_priv = dev->dev_private;
2732 int ret;
2733
2734 intel_get_adjust_train(intel_dp, link_status);
2735 intel_dp_set_signal_levels(intel_dp, DP);
2736
2737 I915_WRITE(intel_dp->output_reg, *DP);
2738 POSTING_READ(intel_dp->output_reg);
2739
9d1a1031
JN		 2740 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2741 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2742
2743 return ret == intel_dp->lane_count;
2744}
2745
3ab9c637
ID		 2746static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2747{
2748 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2749 struct drm_device *dev = intel_dig_port->base.base.dev;
2750 struct drm_i915_private *dev_priv = dev->dev_private;
2751 enum port port = intel_dig_port->port;
2752 uint32_t val;
2753
2754 if (!HAS_DDI(dev))
2755 return;
2756
2757 val = I915_READ(DP_TP_CTL(port));
2758 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2759 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2760 I915_WRITE(DP_TP_CTL(port), val);
2761
2762 /*
2763 * On PORT_A we can have only eDP in SST mode. There the only reason
2764 * we need to set idle transmission mode is to work around a HW issue
2765 * where we enable the pipe while not in idle link-training mode.
2766 * In this case there is requirement to wait for a minimum number of
2767 * idle patterns to be sent.
2768 */
2769 if (port == PORT_A)
2770 return;
2771
2772 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2773 1))
2774 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2775}
2776
33a34e4e 2777/* Enable corresponding port and start training pattern 1 */
c19b0669 2778void
33a34e4e 2779intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2780{
da63a9f2 2781 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2782 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2783 int i;
2784 uint8_t voltage;
cdb0e95b 2785 int voltage_tries, loop_tries;
ea5b213a 2786 uint32_t DP = intel_dp->DP;
6aba5b6c 2787 uint8_t link_config[2];
a4fc5ed6 2788
affa9354 2789 if (HAS_DDI(dev))
c19b0669
PZ		 2790 intel_ddi_prepare_link_retrain(encoder);
2791
3cf2efb1 2792 /* Write the link configuration data */
6aba5b6c
JN		 2793 link_config[0] = intel_dp->link_bw;
2794 link_config[1] = intel_dp->lane_count;
2795 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2796 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2797 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2798
2799 link_config[0] = 0;
2800 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2801 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2802
2803 DP |= DP_PORT_EN;
1a2eb460 2804
70aff66c
JN		 2805 /* clock recovery */
2806 if (!intel_dp_reset_link_train(intel_dp, &DP,
2807 DP_TRAINING_PATTERN_1 |
2808 DP_LINK_SCRAMBLING_DISABLE)) {
2809 DRM_ERROR("failed to enable link training\n");
2810 return;
2811 }
2812
a4fc5ed6 2813 voltage = 0xff;
cdb0e95b
KP		 2814 voltage_tries = 0;
2815 loop_tries = 0;
a4fc5ed6 2816 for (;;) {
70aff66c 2817 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2818
a7c9655f 2819 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2820 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2821 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2822 break;
93f62dad 2823 }
a4fc5ed6 2824
01916270 2825 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2826 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2827 break;
2828 }
2829
2830 /* Check to see if we've tried the max voltage */
2831 for (i = 0; i < intel_dp->lane_count; i++)
2832 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2833 break;
3b4f819d 2834 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2835 ++loop_tries;
2836 if (loop_tries == 5) {
3def84b3 2837 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2838 break;
2839 }
70aff66c
JN		 2840 intel_dp_reset_link_train(intel_dp, &DP,
2841 DP_TRAINING_PATTERN_1 |
2842 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2843 voltage_tries = 0;
2844 continue;
2845 }
a4fc5ed6 2846
3cf2efb1 2847 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2848 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2849 ++voltage_tries;
b06fbda3 2850 if (voltage_tries == 5) {
3def84b3 2851 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2852 break;
2853 }
2854 } else
2855 voltage_tries = 0;
2856 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2857
70aff66c
JN		 2858 /* Update training set as requested by target */
2859 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2860 DRM_ERROR("failed to update link training\n");
2861 break;
2862 }
a4fc5ed6
KP		 2863 }
2864
33a34e4e
JB		 2865 intel_dp->DP = DP;
2866}
2867
c19b0669 2868void
33a34e4e
JB		 2869intel_dp_complete_link_train(struct intel_dp *intel_dp)
2870{
33a34e4e 2871 bool channel_eq = false;
37f80975 2872 int tries, cr_tries;
33a34e4e 2873 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2874 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2875
2876 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2877 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2878 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2879
a4fc5ed6 2880 /* channel equalization */
70aff66c 2881 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2882 training_pattern |
70aff66c
JN		 2883 DP_LINK_SCRAMBLING_DISABLE)) {
2884 DRM_ERROR("failed to start channel equalization\n");
2885 return;
2886 }
2887
a4fc5ed6 2888 tries = 0;
37f80975 2889 cr_tries = 0;
a4fc5ed6
KP		 2890 channel_eq = false;
2891 for (;;) {
70aff66c 2892 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2893
37f80975
JB		 2894 if (cr_tries > 5) {
2895 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2896 break;
2897 }
2898
a7c9655f 2899 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2900 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2901 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2902 break;
70aff66c 2903 }
a4fc5ed6 2904
37f80975 2905 /* Make sure clock is still ok */
01916270 2906 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2907 intel_dp_start_link_train(intel_dp);
70aff66c 2908 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2909 training_pattern |
70aff66c 2910 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2911 cr_tries++;
2912 continue;
2913 }
2914
1ffdff13 2915 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2916 channel_eq = true;
2917 break;
2918 }
a4fc5ed6 2919
37f80975
JB		 2920 /* Try 5 times, then try clock recovery if that fails */
2921 if (tries > 5) {
2922 intel_dp_link_down(intel_dp);
2923 intel_dp_start_link_train(intel_dp);
70aff66c 2924 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2925 training_pattern |
70aff66c 2926 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2927 tries = 0;
2928 cr_tries++;
2929 continue;
2930 }
a4fc5ed6 2931
70aff66c
JN		 2932 /* Update training set as requested by target */
2933 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2934 DRM_ERROR("failed to update link training\n");
2935 break;
2936 }
3cf2efb1 2937 ++tries;
869184a6 2938 }
3cf2efb1 2939
3ab9c637
ID		 2940 intel_dp_set_idle_link_train(intel_dp);
2941
2942 intel_dp->DP = DP;
2943
d6c0d722 2944 if (channel_eq)
07f42258 2945 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2946
3ab9c637
ID		 2947}
2948
2949void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2950{
70aff66c 2951 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2952 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2953}
2954
2955static void
ea5b213a 2956intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2957{
da63a9f2 2958 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2959 enum port port = intel_dig_port->port;
da63a9f2 2960 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2961 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2962 struct intel_crtc *intel_crtc =
2963 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2964 uint32_t DP = intel_dp->DP;
a4fc5ed6 2965
c19b0669
PZ		 2966 /*
2967 * DDI code has a strict mode set sequence and we should try to respect
2968 * it, otherwise we might hang the machine in many different ways. So we
2969 * really should be disabling the port only on a complete crtc_disable
2970 * sequence. This function is just called under two conditions on DDI
2971 * code:
2972 * - Link train failed while doing crtc_enable, and on this case we
2973 * really should respect the mode set sequence and wait for a
2974 * crtc_disable.
2975 * - Someone turned the monitor off and intel_dp_check_link_status
2976 * called us. We don't need to disable the whole port on this case, so
2977 * when someone turns the monitor on again,
2978 * intel_ddi_prepare_link_retrain will take care of redoing the link
2979 * train.
2980 */
affa9354 2981 if (HAS_DDI(dev))
c19b0669
PZ		 2982 return;
2983
0c33d8d7 2984 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2985 return;
2986
28c97730 2987 DRM_DEBUG_KMS("\n");
32f9d658 2988
bc7d38a4 2989 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2990 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2991 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2992 } else {
2993 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2994 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2995 }
fe255d00 2996 POSTING_READ(intel_dp->output_reg);
5eb08b69 2997
493a7081 2998 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2999 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3000 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3001
5bddd17f
EA		 3002 /* Hardware workaround: leaving our transcoder select
3003 * set to transcoder B while it's off will prevent the
3004 * corresponding HDMI output on transcoder A.
3005 *
3006 * Combine this with another hardware workaround:
3007 * transcoder select bit can only be cleared while the
3008 * port is enabled.
3009 */
3010 DP &= ~DP_PIPEB_SELECT;
3011 I915_WRITE(intel_dp->output_reg, DP);
3012
3013 /* Changes to enable or select take place the vblank
3014 * after being written.
3015 */
ff50afe9
DV		 3016 if (WARN_ON(crtc == NULL)) {
3017 /* We should never try to disable a port without a crtc
3018 * attached. For paranoia keep the code around for a
3019 * bit. */
31acbcc4
CW		 3020 POSTING_READ(intel_dp->output_reg);
3021 msleep(50);
3022 } else
ab527efc 3023 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3024 }
3025
832afda6 3026 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3027 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3028 POSTING_READ(intel_dp->output_reg);
f01eca2e 3029 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3030}
3031
26d61aad
KP		 3032static bool
3033intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3034{
a031d709
RV		 3035 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3036 struct drm_device *dev = dig_port->base.base.dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038
577c7a50
DL		 3039 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3040
9d1a1031
JN		 3041 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3042 sizeof(intel_dp->dpcd)) < 0)
edb39244 3043 return false; /* aux transfer failed */
92fd8fd1 3044
577c7a50
DL		 3045 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3046 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3047 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3048
edb39244
AJ		 3049 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3050 return false; /* DPCD not present */
3051
2293bb5c
SK		 3052 /* Check if the panel supports PSR */
3053 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3054 if (is_edp(intel_dp)) {
9d1a1031
JN		 3055 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3056 intel_dp->psr_dpcd,
3057 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3058 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3059 dev_priv->psr.sink_support = true;
50003939 3060 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3061 }
50003939
JN		 3062 }
3063
06ea66b6
TP		 3064 /* Training Pattern 3 support */
3065 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3066 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3067 intel_dp->use_tps3 = true;
3068 DRM_DEBUG_KMS("Displayport TPS3 supported");
3069 } else
3070 intel_dp->use_tps3 = false;
3071
edb39244
AJ		 3072 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3073 DP_DWN_STRM_PORT_PRESENT))
3074 return true; /* native DP sink */
3075
3076 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3077 return true; /* no per-port downstream info */
3078
9d1a1031
JN		 3079 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3080 intel_dp->downstream_ports,
3081 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3082 return false; /* downstream port status fetch failed */
3083
3084 return true;
92fd8fd1
KP		 3085}
3086
0d198328
AJ		 3087static void
3088intel_dp_probe_oui(struct intel_dp *intel_dp)
3089{
3090 u8 buf[3];
3091
3092 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3093 return;
3094
24f3e092 3095 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3096
9d1a1031 3097 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3098 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3099 buf[0], buf[1], buf[2]);
3100
9d1a1031 3101 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3102 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3103 buf[0], buf[1], buf[2]);
351cfc34 3104
4be73780 3105 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3106}
3107
d2e216d0
RV		 3108int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3109{
3110 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3111 struct drm_device *dev = intel_dig_port->base.base.dev;
3112 struct intel_crtc *intel_crtc =
3113 to_intel_crtc(intel_dig_port->base.base.crtc);
3114 u8 buf[1];
3115
9d1a1031 3116 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3117 return -EAGAIN;
3118
3119 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3120 return -ENOTTY;
3121
9d1a1031
JN		 3122 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3123 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3124 return -EAGAIN;
3125
3126 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3127 intel_wait_for_vblank(dev, intel_crtc->pipe);
3128 intel_wait_for_vblank(dev, intel_crtc->pipe);
3129
9d1a1031 3130 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3131 return -EAGAIN;
3132
9d1a1031 3133 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3134 return 0;
3135}
3136
a60f0e38
JB		 3137static bool
3138intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3139{
9d1a1031
JN		 3140 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3141 DP_DEVICE_SERVICE_IRQ_VECTOR,
3142 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3143}
3144
3145static void
3146intel_dp_handle_test_request(struct intel_dp *intel_dp)
3147{
3148 /* NAK by default */
9d1a1031 3149 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3150}
3151
a4fc5ed6
KP		 3152/*
3153 * According to DP spec
3154 * 5.1.2:
3155 * 1. Read DPCD
3156 * 2. Configure link according to Receiver Capabilities
3157 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3158 * 4. Check link status on receipt of hot-plug interrupt
3159 */
3160
00c09d70 3161void
ea5b213a 3162intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3163{
da63a9f2 3164 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3165 u8 sink_irq_vector;
93f62dad 3166 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3167
da63a9f2 3168 if (!intel_encoder->connectors_active)
d2b996ac 3169 return;
59cd09e1 3170
da63a9f2 3171 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3172 return;
3173
92fd8fd1 3174 /* Try to read receiver status if the link appears to be up */
93f62dad 3175 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3176 return;
3177 }
3178
92fd8fd1 3179 /* Now read the DPCD to see if it's actually running */
26d61aad 3180 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3181 return;
3182 }
3183
a60f0e38
JB		 3184 /* Try to read the source of the interrupt */
3185 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3186 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3187 /* Clear interrupt source */
9d1a1031
JN		 3188 drm_dp_dpcd_writeb(&intel_dp->aux,
3189 DP_DEVICE_SERVICE_IRQ_VECTOR,
3190 sink_irq_vector);
a60f0e38
JB		 3191
3192 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3193 intel_dp_handle_test_request(intel_dp);
3194 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3195 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3196 }
3197
1ffdff13 3198 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3199 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3200 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3201 intel_dp_start_link_train(intel_dp);
3202 intel_dp_complete_link_train(intel_dp);
3ab9c637 3203 intel_dp_stop_link_train(intel_dp);
33a34e4e 3204 }
a4fc5ed6 3205}
a4fc5ed6 3206
caf9ab24 3207/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3208static enum drm_connector_status
26d61aad 3209intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3210{
caf9ab24 3211 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3212 uint8_t type;
3213
3214 if (!intel_dp_get_dpcd(intel_dp))
3215 return connector_status_disconnected;
3216
3217 /* if there's no downstream port, we're done */
3218 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3219 return connector_status_connected;
caf9ab24
AJ		 3220
3221 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3222 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3223 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3224 uint8_t reg;
9d1a1031
JN		 3225
3226 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3227 &reg, 1) < 0)
caf9ab24 3228 return connector_status_unknown;
9d1a1031 3229
23235177
AJ		 3230 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3231 : connector_status_disconnected;
caf9ab24
AJ		 3232 }
3233
3234 /* If no HPD, poke DDC gently */
0b99836f 3235 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3236 return connector_status_connected;
caf9ab24
AJ		 3237
3238 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3239 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3240 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3241 if (type == DP_DS_PORT_TYPE_VGA ||
3242 type == DP_DS_PORT_TYPE_NON_EDID)
3243 return connector_status_unknown;
3244 } else {
3245 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3246 DP_DWN_STRM_PORT_TYPE_MASK;
3247 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3248 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3249 return connector_status_unknown;
3250 }
caf9ab24
AJ		 3251
3252 /* Anything else is out of spec, warn and ignore */
3253 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3254 return connector_status_disconnected;
71ba9000
AJ		 3255}
3256
5eb08b69 3257static enum drm_connector_status
a9756bb5 3258ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3259{
30add22d 3260 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3263 enum drm_connector_status status;
3264
fe16d949
CW		 3265 /* Can't disconnect eDP, but you can close the lid... */
3266 if (is_edp(intel_dp)) {
30add22d 3267 status = intel_panel_detect(dev);
fe16d949
CW		 3268 if (status == connector_status_unknown)
3269 status = connector_status_connected;
3270 return status;
3271 }
01cb9ea6 3272
1b469639
DL		 3273 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3274 return connector_status_disconnected;
3275
26d61aad 3276 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3277}
3278
a4fc5ed6 3279static enum drm_connector_status
a9756bb5 3280g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3281{
30add22d 3282 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3283 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3284 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3285 uint32_t bit;
5eb08b69 3286
35aad75f
JB		 3287 /* Can't disconnect eDP, but you can close the lid... */
3288 if (is_edp(intel_dp)) {
3289 enum drm_connector_status status;
3290
3291 status = intel_panel_detect(dev);
3292 if (status == connector_status_unknown)
3293 status = connector_status_connected;
3294 return status;
3295 }
3296
232a6ee9
TP		 3297 if (IS_VALLEYVIEW(dev)) {
3298 switch (intel_dig_port->port) {
3299 case PORT_B:
3300 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3301 break;
3302 case PORT_C:
3303 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3304 break;
3305 case PORT_D:
3306 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3307 break;
3308 default:
3309 return connector_status_unknown;
3310 }
3311 } else {
3312 switch (intel_dig_port->port) {
3313 case PORT_B:
3314 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3315 break;
3316 case PORT_C:
3317 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3318 break;
3319 case PORT_D:
3320 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3321 break;
3322 default:
3323 return connector_status_unknown;
3324 }
a4fc5ed6
KP		 3325 }
3326
10f76a38 3327 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3328 return connector_status_disconnected;
3329
26d61aad 3330 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3331}
3332
8c241fef
KP		 3333static struct edid *
3334intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3335{
9cd300e0 3336 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3337
9cd300e0
JN		 3338 /* use cached edid if we have one */
3339 if (intel_connector->edid) {
9cd300e0
JN		 3340 /* invalid edid */
3341 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3342 return NULL;
3343
55e9edeb 3344 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3345 }
8c241fef 3346
9cd300e0 3347 return drm_get_edid(connector, adapter);
8c241fef
KP		 3348}
3349
3350static int
3351intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3352{
9cd300e0 3353 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3354
9cd300e0
JN		 3355 /* use cached edid if we have one */
3356 if (intel_connector->edid) {
3357 /* invalid edid */
3358 if (IS_ERR(intel_connector->edid))
3359 return 0;
3360
3361 return intel_connector_update_modes(connector,
3362 intel_connector->edid);
d6f24d0f
JB		 3363 }
3364
9cd300e0 3365 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3366}
3367
a9756bb5
ZW		 3368static enum drm_connector_status
3369intel_dp_detect(struct drm_connector *connector, bool force)
3370{
3371 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3372 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3373 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3374 struct drm_device *dev = connector->dev;
c8c8fb33 3375 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3376 enum drm_connector_status status;
671dedd2 3377 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3378 struct edid *edid = NULL;
3379
c8c8fb33
PZ		 3380 intel_runtime_pm_get(dev_priv);
3381
671dedd2
ID		 3382 power_domain = intel_display_port_power_domain(intel_encoder);
3383 intel_display_power_get(dev_priv, power_domain);
3384
164c8598
CW		 3385 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3386 connector->base.id, drm_get_connector_name(connector));
3387
a9756bb5
ZW		 3388 intel_dp->has_audio = false;
3389
3390 if (HAS_PCH_SPLIT(dev))
3391 status = ironlake_dp_detect(intel_dp);
3392 else
3393 status = g4x_dp_detect(intel_dp);
1b9be9d0 3394
a9756bb5 3395 if (status != connector_status_connected)
c8c8fb33 3396 goto out;
a9756bb5 3397
0d198328
AJ		 3398 intel_dp_probe_oui(intel_dp);
3399
c3e5f67b
DV		 3400 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3401 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3402 } else {
0b99836f 3403 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3404 if (edid) {
3405 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3406 kfree(edid);
3407 }
a9756bb5
ZW		 3408 }
3409
d63885da
PZ		 3410 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3411 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3412 status = connector_status_connected;
3413
3414out:
671dedd2
ID		 3415 intel_display_power_put(dev_priv, power_domain);
3416
c8c8fb33 3417 intel_runtime_pm_put(dev_priv);
671dedd2 3418
c8c8fb33 3419 return status;
a4fc5ed6
KP		 3420}
3421
3422static int intel_dp_get_modes(struct drm_connector *connector)
3423{
df0e9248 3424 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3426 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3427 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3428 struct drm_device *dev = connector->dev;
671dedd2
ID		 3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430 enum intel_display_power_domain power_domain;
32f9d658 3431 int ret;
a4fc5ed6
KP		 3432
3433 /* We should parse the EDID data and find out if it has an audio sink
3434 */
3435
671dedd2
ID		 3436 power_domain = intel_display_port_power_domain(intel_encoder);
3437 intel_display_power_get(dev_priv, power_domain);
3438
0b99836f 3439 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3440 intel_display_power_put(dev_priv, power_domain);
f8779fda 3441 if (ret)
32f9d658
ZW		 3442 return ret;
3443
f8779fda 3444 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3445 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3446 struct drm_display_mode *mode;
dd06f90e
JN		 3447 mode = drm_mode_duplicate(dev,
3448 intel_connector->panel.fixed_mode);
f8779fda 3449 if (mode) {
32f9d658
ZW		 3450 drm_mode_probed_add(connector, mode);
3451 return 1;
3452 }
3453 }
3454 return 0;
a4fc5ed6
KP		 3455}
3456
1aad7ac0
CW		 3457static bool
3458intel_dp_detect_audio(struct drm_connector *connector)
3459{
3460 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3462 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3463 struct drm_device *dev = connector->dev;
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3466 struct edid *edid;
3467 bool has_audio = false;
3468
671dedd2
ID		 3469 power_domain = intel_display_port_power_domain(intel_encoder);
3470 intel_display_power_get(dev_priv, power_domain);
3471
0b99836f 3472 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3473 if (edid) {
3474 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3475 kfree(edid);
3476 }
3477
671dedd2
ID		 3478 intel_display_power_put(dev_priv, power_domain);
3479
1aad7ac0
CW		 3480 return has_audio;
3481}
3482
f684960e
CW		 3483static int
3484intel_dp_set_property(struct drm_connector *connector,
3485 struct drm_property *property,
3486 uint64_t val)
3487{
e953fd7b 3488 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3489 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3490 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3491 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3492 int ret;
3493
662595df 3494 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3495 if (ret)
3496 return ret;
3497
3f43c48d 3498 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3499 int i = val;
3500 bool has_audio;
3501
3502 if (i == intel_dp->force_audio)
f684960e
CW		 3503 return 0;
3504
1aad7ac0 3505 intel_dp->force_audio = i;
f684960e 3506
c3e5f67b 3507 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3508 has_audio = intel_dp_detect_audio(connector);
3509 else
c3e5f67b 3510 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3511
3512 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3513 return 0;
3514
1aad7ac0 3515 intel_dp->has_audio = has_audio;
f684960e
CW		 3516 goto done;
3517 }
3518
e953fd7b 3519 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3520 bool old_auto = intel_dp->color_range_auto;
3521 uint32_t old_range = intel_dp->color_range;
3522
55bc60db
VS		 3523 switch (val) {
3524 case INTEL_BROADCAST_RGB_AUTO:
3525 intel_dp->color_range_auto = true;
3526 break;
3527 case INTEL_BROADCAST_RGB_FULL:
3528 intel_dp->color_range_auto = false;
3529 intel_dp->color_range = 0;
3530 break;
3531 case INTEL_BROADCAST_RGB_LIMITED:
3532 intel_dp->color_range_auto = false;
3533 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3534 break;
3535 default:
3536 return -EINVAL;
3537 }
ae4edb80
DV		 3538
3539 if (old_auto == intel_dp->color_range_auto &&
3540 old_range == intel_dp->color_range)
3541 return 0;
3542
e953fd7b
CW		 3543 goto done;
3544 }
3545
53b41837
YN		 3546 if (is_edp(intel_dp) &&
3547 property == connector->dev->mode_config.scaling_mode_property) {
3548 if (val == DRM_MODE_SCALE_NONE) {
3549 DRM_DEBUG_KMS("no scaling not supported\n");
3550 return -EINVAL;
3551 }
3552
3553 if (intel_connector->panel.fitting_mode == val) {
3554 /* the eDP scaling property is not changed */
3555 return 0;
3556 }
3557 intel_connector->panel.fitting_mode = val;
3558
3559 goto done;
3560 }
3561
f684960e
CW		 3562 return -EINVAL;
3563
3564done:
c0c36b94
CW		 3565 if (intel_encoder->base.crtc)
3566 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3567
3568 return 0;
3569}
3570
a4fc5ed6 3571static void
73845adf 3572intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3573{
1d508706 3574 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3575
9cd300e0
JN		 3576 if (!IS_ERR_OR_NULL(intel_connector->edid))
3577 kfree(intel_connector->edid);
3578
acd8db10
PZ		 3579 /* Can't call is_edp() since the encoder may have been destroyed
3580 * already. */
3581 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3582 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3583
a4fc5ed6 3584 drm_connector_cleanup(connector);
55f78c43 3585 kfree(connector);
a4fc5ed6
KP		 3586}
3587
00c09d70 3588void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3589{
da63a9f2
PZ		 3590 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3591 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3592 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3593
0b99836f 3594 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3595 drm_encoder_cleanup(encoder);
bd943159
KP		 3596 if (is_edp(intel_dp)) {
3597 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3598 mutex_lock(&dev->mode_config.mutex);
4be73780 3599 edp_panel_vdd_off_sync(intel_dp);
bd173813 3600 mutex_unlock(&dev->mode_config.mutex);
bd943159 3601 }
da63a9f2 3602 kfree(intel_dig_port);
24d05927
DV		 3603}
3604
a4fc5ed6 3605static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3606 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3607 .detect = intel_dp_detect,
3608 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3609 .set_property = intel_dp_set_property,
73845adf 3610 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3611};
3612
3613static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3614 .get_modes = intel_dp_get_modes,
3615 .mode_valid = intel_dp_mode_valid,
df0e9248 3616 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3617};
3618
a4fc5ed6 3619static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3620 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3621};
3622
995b6762 3623static void
21d40d37 3624intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3625{
fa90ecef 3626 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3627
885a5014 3628 intel_dp_check_link_status(intel_dp);
c8110e52 3629}
6207937d 3630
e3421a18
ZW		 3631/* Return which DP Port should be selected for Transcoder DP control */
3632int
0206e353 3633intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3634{
3635 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3636 struct intel_encoder *intel_encoder;
3637 struct intel_dp *intel_dp;
e3421a18 3638
fa90ecef
PZ		 3639 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3640 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3641
fa90ecef
PZ		 3642 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3643 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3644 return intel_dp->output_reg;
e3421a18 3645 }
ea5b213a 3646
e3421a18
ZW		 3647 return -1;
3648}
3649
36e83a18 3650/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3651bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3652{
3653 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3654 union child_device_config *p_child;
36e83a18 3655 int i;
5d8a7752
VS		 3656 static const short port_mapping[] = {
3657 [PORT_B] = PORT_IDPB,
3658 [PORT_C] = PORT_IDPC,
3659 [PORT_D] = PORT_IDPD,
3660 };
36e83a18 3661
3b32a35b
VS		 3662 if (port == PORT_A)
3663 return true;
3664
41aa3448 3665 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3666 return false;
3667
41aa3448
RV		 3668 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3669 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3670
5d8a7752 3671 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3672 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3673 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3674 return true;
3675 }
3676 return false;
3677}
3678
f684960e
CW		 3679static void
3680intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3681{
53b41837
YN		 3682 struct intel_connector *intel_connector = to_intel_connector(connector);
3683
3f43c48d 3684 intel_attach_force_audio_property(connector);
e953fd7b 3685 intel_attach_broadcast_rgb_property(connector);
55bc60db 3686 intel_dp->color_range_auto = true;
53b41837
YN		 3687
3688 if (is_edp(intel_dp)) {
3689 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3690 drm_object_attach_property(
3691 &connector->base,
53b41837 3692 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3693 DRM_MODE_SCALE_ASPECT);
3694 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3695 }
f684960e
CW		 3696}
3697
dada1a9f
ID		 3698static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3699{
3700 intel_dp->last_power_cycle = jiffies;
3701 intel_dp->last_power_on = jiffies;
3702 intel_dp->last_backlight_off = jiffies;
3703}
3704
67a54566
DV		 3705static void
3706intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3707 struct intel_dp *intel_dp,
3708 struct edp_power_seq *out)
67a54566
DV		 3709{
3710 struct drm_i915_private *dev_priv = dev->dev_private;
3711 struct edp_power_seq cur, vbt, spec, final;
3712 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3713 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3714
3715 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3716 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3717 pp_on_reg = PCH_PP_ON_DELAYS;
3718 pp_off_reg = PCH_PP_OFF_DELAYS;
3719 pp_div_reg = PCH_PP_DIVISOR;
3720 } else {
bf13e81b
JN		 3721 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3722
3723 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3724 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3725 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3726 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3727 }
67a54566
DV		 3728
3729 /* Workaround: Need to write PP_CONTROL with the unlock key as
3730 * the very first thing. */
453c5420 3731 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3732 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3733
453c5420
JB		 3734 pp_on = I915_READ(pp_on_reg);
3735 pp_off = I915_READ(pp_off_reg);
3736 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3737
3738 /* Pull timing values out of registers */
3739 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3740 PANEL_POWER_UP_DELAY_SHIFT;
3741
3742 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3743 PANEL_LIGHT_ON_DELAY_SHIFT;
3744
3745 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3746 PANEL_LIGHT_OFF_DELAY_SHIFT;
3747
3748 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3749 PANEL_POWER_DOWN_DELAY_SHIFT;
3750
3751 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3752 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3753
3754 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3755 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3756
41aa3448 3757 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3758
3759 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3760 * our hw here, which are all in 100usec. */
3761 spec.t1_t3 = 210 * 10;
3762 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3763 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3764 spec.t10 = 500 * 10;
3765 /* This one is special and actually in units of 100ms, but zero
3766 * based in the hw (so we need to add 100 ms). But the sw vbt
3767 * table multiplies it with 1000 to make it in units of 100usec,
3768 * too. */
3769 spec.t11_t12 = (510 + 100) * 10;
3770
3771 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3772 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3773
3774 /* Use the max of the register settings and vbt. If both are
3775 * unset, fall back to the spec limits. */
3776#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3777 spec.field : \
3778 max(cur.field, vbt.field))
3779 assign_final(t1_t3);
3780 assign_final(t8);
3781 assign_final(t9);
3782 assign_final(t10);
3783 assign_final(t11_t12);
3784#undef assign_final
3785
3786#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3787 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3788 intel_dp->backlight_on_delay = get_delay(t8);
3789 intel_dp->backlight_off_delay = get_delay(t9);
3790 intel_dp->panel_power_down_delay = get_delay(t10);
3791 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3792#undef get_delay
3793
f30d26e4
JN		 3794 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3795 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3796 intel_dp->panel_power_cycle_delay);
3797
3798 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3799 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3800
3801 if (out)
3802 *out = final;
3803}
3804
3805static void
3806intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3807 struct intel_dp *intel_dp,
3808 struct edp_power_seq *seq)
3809{
3810 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3811 u32 pp_on, pp_off, pp_div, port_sel = 0;
3812 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3813 int pp_on_reg, pp_off_reg, pp_div_reg;
3814
3815 if (HAS_PCH_SPLIT(dev)) {
3816 pp_on_reg = PCH_PP_ON_DELAYS;
3817 pp_off_reg = PCH_PP_OFF_DELAYS;
3818 pp_div_reg = PCH_PP_DIVISOR;
3819 } else {
bf13e81b
JN		 3820 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3821
3822 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3823 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3824 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3825 }
3826
b2f19d1a
PZ		 3827 /*
3828 * And finally store the new values in the power sequencer. The
3829 * backlight delays are set to 1 because we do manual waits on them. For
3830 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3831 * we'll end up waiting for the backlight off delay twice: once when we
3832 * do the manual sleep, and once when we disable the panel and wait for
3833 * the PP_STATUS bit to become zero.
3834 */
f30d26e4 3835 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3836 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3837 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3838 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3839 /* Compute the divisor for the pp clock, simply match the Bspec
3840 * formula. */
453c5420 3841 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3842 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3843 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3844
3845 /* Haswell doesn't have any port selection bits for the panel
3846 * power sequencer any more. */
bc7d38a4 3847 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3848 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3849 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3850 else
3851 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3852 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3853 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3854 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3855 else
a24c144c 3856 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3857 }
3858
453c5420
JB		 3859 pp_on |= port_sel;
3860
3861 I915_WRITE(pp_on_reg, pp_on);
3862 I915_WRITE(pp_off_reg, pp_off);
3863 I915_WRITE(pp_div_reg, pp_div);
67a54566 3864
67a54566 3865 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3866 I915_READ(pp_on_reg),
3867 I915_READ(pp_off_reg),
3868 I915_READ(pp_div_reg));
f684960e
CW		 3869}
3870
439d7ac0
PB		 3871void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3872{
3873 struct drm_i915_private *dev_priv = dev->dev_private;
3874 struct intel_encoder *encoder;
3875 struct intel_dp *intel_dp = NULL;
3876 struct intel_crtc_config *config = NULL;
3877 struct intel_crtc *intel_crtc = NULL;
3878 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3879 u32 reg, val;
3880 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3881
3882 if (refresh_rate <= 0) {
3883 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3884 return;
3885 }
3886
3887 if (intel_connector == NULL) {
3888 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3889 return;
3890 }
3891
3892 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3893 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3894 return;
3895 }
3896
3897 encoder = intel_attached_encoder(&intel_connector->base);
3898 intel_dp = enc_to_intel_dp(&encoder->base);
3899 intel_crtc = encoder->new_crtc;
3900
3901 if (!intel_crtc) {
3902 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3903 return;
3904 }
3905
3906 config = &intel_crtc->config;
3907
3908 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3909 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3910 return;
3911 }
3912
3913 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3914 index = DRRS_LOW_RR;
3915
3916 if (index == intel_dp->drrs_state.refresh_rate_type) {
3917 DRM_DEBUG_KMS(
3918 "DRRS requested for previously set RR...ignoring\n");
3919 return;
3920 }
3921
3922 if (!intel_crtc->active) {
3923 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3924 return;
3925 }
3926
3927 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3928 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3929 val = I915_READ(reg);
3930 if (index > DRRS_HIGH_RR) {
3931 val |= PIPECONF_EDP_RR_MODE_SWITCH;
3932 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3933 } else {
3934 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3935 }
3936 I915_WRITE(reg, val);
3937 }
3938
3939 /*
3940 * mutex taken to ensure that there is no race between differnt
3941 * drrs calls trying to update refresh rate. This scenario may occur
3942 * in future when idleness detection based DRRS in kernel and
3943 * possible calls from user space to set differnt RR are made.
3944 */
3945
3946 mutex_lock(&intel_dp->drrs_state.mutex);
3947
3948 intel_dp->drrs_state.refresh_rate_type = index;
3949
3950 mutex_unlock(&intel_dp->drrs_state.mutex);
3951
3952 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3953}
3954
4f9db5b5
PB		 3955static struct drm_display_mode *
3956intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
3957 struct intel_connector *intel_connector,
3958 struct drm_display_mode *fixed_mode)
3959{
3960 struct drm_connector *connector = &intel_connector->base;
3961 struct intel_dp *intel_dp = &intel_dig_port->dp;
3962 struct drm_device *dev = intel_dig_port->base.base.dev;
3963 struct drm_i915_private *dev_priv = dev->dev_private;
3964 struct drm_display_mode *downclock_mode = NULL;
3965
3966 if (INTEL_INFO(dev)->gen <= 6) {
3967 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3968 return NULL;
3969 }
3970
3971 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
3972 DRM_INFO("VBT doesn't support DRRS\n");
3973 return NULL;
3974 }
3975
3976 downclock_mode = intel_find_panel_downclock
3977 (dev, fixed_mode, connector);
3978
3979 if (!downclock_mode) {
3980 DRM_INFO("DRRS not supported\n");
3981 return NULL;
3982 }
3983
439d7ac0
PB		 3984 dev_priv->drrs.connector = intel_connector;
3985
3986 mutex_init(&intel_dp->drrs_state.mutex);
3987
4f9db5b5
PB		 3988 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
3989
3990 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
3991 DRM_INFO("seamless DRRS supported for eDP panel.\n");
3992 return downclock_mode;
3993}
3994
ed92f0b2 3995static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3996 struct intel_connector *intel_connector,
3997 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3998{
3999 struct drm_connector *connector = &intel_connector->base;
4000 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4001 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4002 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4003 struct drm_i915_private *dev_priv = dev->dev_private;
4004 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4005 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4006 bool has_dpcd;
4007 struct drm_display_mode *scan;
4008 struct edid *edid;
4009
4f9db5b5
PB		 4010 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4011
ed92f0b2
PZ		 4012 if (!is_edp(intel_dp))
4013 return true;
4014
63635217
PZ		 4015 /* The VDD bit needs a power domain reference, so if the bit is already
4016 * enabled when we boot, grab this reference. */
4017 if (edp_have_panel_vdd(intel_dp)) {
4018 enum intel_display_power_domain power_domain;
4019 power_domain = intel_display_port_power_domain(intel_encoder);
4020 intel_display_power_get(dev_priv, power_domain);
4021 }
4022
ed92f0b2 4023 /* Cache DPCD and EDID for edp. */
24f3e092 4024 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4025 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4026 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4027
4028 if (has_dpcd) {
4029 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4030 dev_priv->no_aux_handshake =
4031 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4032 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4033 } else {
4034 /* if this fails, presume the device is a ghost */
4035 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4036 return false;
4037 }
4038
4039 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4040 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4041
060c8778 4042 mutex_lock(&dev->mode_config.mutex);
0b99836f 4043 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4044 if (edid) {
4045 if (drm_add_edid_modes(connector, edid)) {
4046 drm_mode_connector_update_edid_property(connector,
4047 edid);
4048 drm_edid_to_eld(connector, edid);
4049 } else {
4050 kfree(edid);
4051 edid = ERR_PTR(-EINVAL);
4052 }
4053 } else {
4054 edid = ERR_PTR(-ENOENT);
4055 }
4056 intel_connector->edid = edid;
4057
4058 /* prefer fixed mode from EDID if available */
4059 list_for_each_entry(scan, &connector->probed_modes, head) {
4060 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4061 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4062 downclock_mode = intel_dp_drrs_init(
4063 intel_dig_port,
4064 intel_connector, fixed_mode);
ed92f0b2
PZ		 4065 break;
4066 }
4067 }
4068
4069 /* fallback to VBT if available for eDP */
4070 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4071 fixed_mode = drm_mode_duplicate(dev,
4072 dev_priv->vbt.lfp_lvds_vbt_mode);
4073 if (fixed_mode)
4074 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4075 }
060c8778 4076 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4077
4f9db5b5 4078 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4079 intel_panel_setup_backlight(connector);
4080
4081 return true;
4082}
4083
16c25533 4084bool
f0fec3f2
PZ		 4085intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4086 struct intel_connector *intel_connector)
a4fc5ed6 4087{
f0fec3f2
PZ		 4088 struct drm_connector *connector = &intel_connector->base;
4089 struct intel_dp *intel_dp = &intel_dig_port->dp;
4090 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4091 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4092 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4093 enum port port = intel_dig_port->port;
0095e6dc 4094 struct edp_power_seq power_seq = { 0 };
0b99836f 4095 int type;
a4fc5ed6 4096
ec5b01dd
DL		 4097 /* intel_dp vfuncs */
4098 if (IS_VALLEYVIEW(dev))
4099 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4100 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4101 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4102 else if (HAS_PCH_SPLIT(dev))
4103 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4104 else
4105 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4106
153b1100
DL		 4107 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4108
0767935e
DV		 4109 /* Preserve the current hw state. */
4110 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4111 intel_dp->attached_connector = intel_connector;
3d3dc149 4112
3b32a35b 4113 if (intel_dp_is_edp(dev, port))
b329530c 4114 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4115 else
4116 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4117
f7d24902
ID		 4118 /*
4119 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4120 * for DP the encoder type can be set by the caller to
4121 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4122 */
4123 if (type == DRM_MODE_CONNECTOR_eDP)
4124 intel_encoder->type = INTEL_OUTPUT_EDP;
4125
e7281eab
ID		 4126 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4127 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4128 port_name(port));
4129
b329530c 4130 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4131 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4132
a4fc5ed6
KP		 4133 connector->interlace_allowed = true;
4134 connector->doublescan_allowed = 0;
4135
f0fec3f2 4136 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4137 edp_panel_vdd_work);
a4fc5ed6 4138
df0e9248 4139 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 4140 drm_sysfs_connector_add(connector);
4141
affa9354 4142 if (HAS_DDI(dev))
bcbc889b
PZ		 4143 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4144 else
4145 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4146 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4147
0b99836f 4148 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4149 switch (port) {
4150 case PORT_A:
1d843f9d 4151 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4152 break;
4153 case PORT_B:
1d843f9d 4154 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4155 break;
4156 case PORT_C:
1d843f9d 4157 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4158 break;
4159 case PORT_D:
1d843f9d 4160 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4161 break;
4162 default:
ad1c0b19 4163 BUG();
5eb08b69
ZW		 4164 }
4165
dada1a9f
ID		 4166 if (is_edp(intel_dp)) {
4167 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4168 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4169 }
0095e6dc 4170
9d1a1031 4171 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4172
2b28bb1b
RV		 4173 intel_dp->psr_setup_done = false;
4174
0095e6dc 4175 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 4176 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 4177 if (is_edp(intel_dp)) {
4178 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4179 mutex_lock(&dev->mode_config.mutex);
4be73780 4180 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 4181 mutex_unlock(&dev->mode_config.mutex);
4182 }
b2f246a8
PZ		 4183 drm_sysfs_connector_remove(connector);
4184 drm_connector_cleanup(connector);
16c25533 4185 return false;
b2f246a8 4186 }
32f9d658 4187
f684960e
CW		 4188 intel_dp_add_properties(intel_dp, connector);
4189
a4fc5ed6
KP		 4190 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4191 * 0xd. Failure to do so will result in spurious interrupts being
4192 * generated on the port when a cable is not attached.
4193 */
4194 if (IS_G4X(dev) && !IS_GM45(dev)) {
4195 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4196 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4197 }
16c25533
PZ		 4198
4199 return true;
a4fc5ed6 4200}
f0fec3f2
PZ		 4201
4202void
4203intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4204{
4205 struct intel_digital_port *intel_dig_port;
4206 struct intel_encoder *intel_encoder;
4207 struct drm_encoder *encoder;
4208 struct intel_connector *intel_connector;
4209
b14c5679 4210 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4211 if (!intel_dig_port)
4212 return;
4213
b14c5679 4214 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4215 if (!intel_connector) {
4216 kfree(intel_dig_port);
4217 return;
4218 }
4219
4220 intel_encoder = &intel_dig_port->base;
4221 encoder = &intel_encoder->base;
4222
4223 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4224 DRM_MODE_ENCODER_TMDS);
4225
5bfe2ac0 4226 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 4227 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70 4228 intel_encoder->disable = intel_disable_dp;
00c09d70 4229 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4230 intel_encoder->get_config = intel_dp_get_config;
e4a1d846
CML		 4231 if (IS_CHERRYVIEW(dev)) {
4232 intel_encoder->pre_enable = chv_pre_enable_dp;
4233 intel_encoder->enable = vlv_enable_dp;
4234 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4235 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4236 intel_encoder->pre_enable = vlv_pre_enable_dp;
4237 intel_encoder->enable = vlv_enable_dp;
49277c31 4238 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4239 } else {
ecff4f3b
JN		 4240 intel_encoder->pre_enable = g4x_pre_enable_dp;
4241 intel_encoder->enable = g4x_enable_dp;
49277c31 4242 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4243 }
f0fec3f2 4244
174edf1f 4245 intel_dig_port->port = port;
f0fec3f2
PZ		 4246 intel_dig_port->dp.output_reg = output_reg;
4247
00c09d70 4248 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 4249 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 4250 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4251 intel_encoder->hot_plug = intel_dp_hot_plug;
4252
15b1d171
PZ		 4253 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4254 drm_encoder_cleanup(encoder);
4255 kfree(intel_dig_port);
b2f246a8 4256 kfree(intel_connector);
15b1d171 4257 }
f0fec3f2 4258}
Linux kernel - Deliverables
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