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drm/i915: Make the sprite formats const
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf
CML		 50struct dp_link_dpll {
51 int link_bw;
52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
63 { DP_LINK_BW_1_62,
64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
65 { DP_LINK_BW_2_7,
66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5
CML		 69static const struct dp_link_dpll vlv_dpll[] = {
70 { DP_LINK_BW_1_62,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 72 { DP_LINK_BW_2_7,
73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
86 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
88 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
90 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63
SJ		 93
94static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15 95 324000, 432000, 540000 };
fe51bfb9
VS		 96static const int chv_rates[] = { 162000, 202500, 210000, 216000,
97 243000, 270000, 324000, 405000,
98 420000, 432000, 540000 };
f4896f15 99static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 100
cfcb0fc9
JB		 101/**
102 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
103 * @intel_dp: DP struct
104 *
105 * If a CPU or PCH DP output is attached to an eDP panel, this function
106 * will return true, and false otherwise.
107 */
108static bool is_edp(struct intel_dp *intel_dp)
109{
da63a9f2
PZ		 110 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
111
112 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 113}
114
68b4d824 115static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 116{
68b4d824
ID		 117 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
118
119 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 120}
121
df0e9248
CW		 122static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
123{
fa90ecef 124 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 125}
126
ea5b213a 127static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 128static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 129static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 130static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 131static void vlv_steal_power_sequencer(struct drm_device *dev,
132 enum pipe pipe);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
156 struct drm_device *dev = intel_dig_port->base.base.dev;
157 u8 source_max, sink_max;
158
159 source_max = 4;
160 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
161 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
162 source_max = 2;
163
164 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
165
166 return min(source_max, sink_max);
167}
168
cd9dde44
AJ		 169/*
170 * The units on the numbers in the next two are... bizarre. Examples will
171 * make it clearer; this one parallels an example in the eDP spec.
172 *
173 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
174 *
175 * 270000 * 1 * 8 / 10 == 216000
176 *
177 * The actual data capacity of that configuration is 2.16Gbit/s, so the
178 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
179 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
180 * 119000. At 18bpp that's 2142000 kilobits per second.
181 *
182 * Thus the strange-looking division by 10 in intel_dp_link_required, to
183 * get the result in decakilobits instead of kilobits.
184 */
185
a4fc5ed6 186static int
c898261c 187intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 188{
cd9dde44 189 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 190}
191
fe27d53e
DA		 192static int
193intel_dp_max_data_rate(int max_link_clock, int max_lanes)
194{
195 return (max_link_clock * max_lanes * 8) / 10;
196}
197
c19de8eb 198static enum drm_mode_status
a4fc5ed6
KP		 199intel_dp_mode_valid(struct drm_connector *connector,
200 struct drm_display_mode *mode)
201{
df0e9248 202 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 203 struct intel_connector *intel_connector = to_intel_connector(connector);
204 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 205 int target_clock = mode->clock;
206 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 207
dd06f90e
JN		 208 if (is_edp(intel_dp) && fixed_mode) {
209 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 210 return MODE_PANEL;
211
dd06f90e 212 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 213 return MODE_PANEL;
03afc4a2
DV		 214
215 target_clock = fixed_mode->clock;
7de56f43
ZY		 216 }
217
50fec21a 218 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 219 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 220
221 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
222 mode_rate = intel_dp_link_required(target_clock, 18);
223
224 if (mode_rate > max_rate)
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
a4f1289e 236uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 237{
238 int i;
239 uint32_t v = 0;
240
241 if (src_bytes > 4)
242 src_bytes = 4;
243 for (i = 0; i < src_bytes; i++)
244 v |= ((uint32_t) src[i]) << ((3-i) * 8);
245 return v;
246}
247
c2af70e2 248static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 249{
250 int i;
251 if (dst_bytes > 4)
252 dst_bytes = 4;
253 for (i = 0; i < dst_bytes; i++)
254 dst[i] = src >> ((3-i) * 8);
255}
256
fb0f8fbf
KP		 257/* hrawclock is 1/4 the FSB frequency */
258static int
259intel_hrawclk(struct drm_device *dev)
260{
261 struct drm_i915_private *dev_priv = dev->dev_private;
262 uint32_t clkcfg;
263
9473c8f4
VP		 264 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
265 if (IS_VALLEYVIEW(dev))
266 return 200;
267
fb0f8fbf
KP		 268 clkcfg = I915_READ(CLKCFG);
269 switch (clkcfg & CLKCFG_FSB_MASK) {
270 case CLKCFG_FSB_400:
271 return 100;
272 case CLKCFG_FSB_533:
273 return 133;
274 case CLKCFG_FSB_667:
275 return 166;
276 case CLKCFG_FSB_800:
277 return 200;
278 case CLKCFG_FSB_1067:
279 return 266;
280 case CLKCFG_FSB_1333:
281 return 333;
282 /* these two are just a guess; one of them might be right */
283 case CLKCFG_FSB_1600:
284 case CLKCFG_FSB_1600_ALT:
285 return 400;
286 default:
287 return 133;
288 }
289}
290
bf13e81b
JN		 291static void
292intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 293 struct intel_dp *intel_dp);
bf13e81b
JN		 294static void
295intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 296 struct intel_dp *intel_dp);
bf13e81b 297
773538e8
VS		 298static void pps_lock(struct intel_dp *intel_dp)
299{
300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
301 struct intel_encoder *encoder = &intel_dig_port->base;
302 struct drm_device *dev = encoder->base.dev;
303 struct drm_i915_private *dev_priv = dev->dev_private;
304 enum intel_display_power_domain power_domain;
305
306 /*
307 * See vlv_power_sequencer_reset() why we need
308 * a power domain reference here.
309 */
310 power_domain = intel_display_port_power_domain(encoder);
311 intel_display_power_get(dev_priv, power_domain);
312
313 mutex_lock(&dev_priv->pps_mutex);
314}
315
316static void pps_unlock(struct intel_dp *intel_dp)
317{
318 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
319 struct intel_encoder *encoder = &intel_dig_port->base;
320 struct drm_device *dev = encoder->base.dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
322 enum intel_display_power_domain power_domain;
323
324 mutex_unlock(&dev_priv->pps_mutex);
325
326 power_domain = intel_display_port_power_domain(encoder);
327 intel_display_power_put(dev_priv, power_domain);
328}
329
961a0db0
VS		 330static void
331vlv_power_sequencer_kick(struct intel_dp *intel_dp)
332{
333 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
334 struct drm_device *dev = intel_dig_port->base.base.dev;
335 struct drm_i915_private *dev_priv = dev->dev_private;
336 enum pipe pipe = intel_dp->pps_pipe;
d288f65f 337 bool pll_enabled;
961a0db0
VS		 338 uint32_t DP;
339
340 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
341 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
342 pipe_name(pipe), port_name(intel_dig_port->port)))
343 return;
344
345 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
346 pipe_name(pipe), port_name(intel_dig_port->port));
347
348 /* Preserve the BIOS-computed detected bit. This is
349 * supposed to be read-only.
350 */
351 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
352 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
353 DP |= DP_PORT_WIDTH(1);
354 DP |= DP_LINK_TRAIN_PAT_1;
355
356 if (IS_CHERRYVIEW(dev))
357 DP |= DP_PIPE_SELECT_CHV(pipe);
358 else if (pipe == PIPE_B)
359 DP |= DP_PIPEB_SELECT;
360
d288f65f
VS		 361 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
362
363 /*
364 * The DPLL for the pipe must be enabled for this to work.
365 * So enable temporarily it if it's not already enabled.
366 */
367 if (!pll_enabled)
368 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
369 &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
370
961a0db0
VS		 371 /*
372 * Similar magic as in intel_dp_enable_port().
373 * We _must_ do this port enable + disable trick
374 * to make this power seqeuencer lock onto the port.
375 * Otherwise even VDD force bit won't work.
376 */
377 I915_WRITE(intel_dp->output_reg, DP);
378 POSTING_READ(intel_dp->output_reg);
379
380 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
381 POSTING_READ(intel_dp->output_reg);
382
383 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
384 POSTING_READ(intel_dp->output_reg);
d288f65f
VS		 385
386 if (!pll_enabled)
387 vlv_force_pll_off(dev, pipe);
961a0db0
VS		 388}
389
bf13e81b
JN		 390static enum pipe
391vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
392{
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 394 struct drm_device *dev = intel_dig_port->base.base.dev;
395 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 396 struct intel_encoder *encoder;
397 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 398 enum pipe pipe;
bf13e81b 399
e39b999a 400 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 401
a8c3344e
VS		 402 /* We should never land here with regular DP ports */
403 WARN_ON(!is_edp(intel_dp));
404
a4a5d2f8
VS		 405 if (intel_dp->pps_pipe != INVALID_PIPE)
406 return intel_dp->pps_pipe;
407
408 /*
409 * We don't have power sequencer currently.
410 * Pick one that's not used by other ports.
411 */
412 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
413 base.head) {
414 struct intel_dp *tmp;
415
416 if (encoder->type != INTEL_OUTPUT_EDP)
417 continue;
418
419 tmp = enc_to_intel_dp(&encoder->base);
420
421 if (tmp->pps_pipe != INVALID_PIPE)
422 pipes &= ~(1 << tmp->pps_pipe);
423 }
424
425 /*
426 * Didn't find one. This should not happen since there
427 * are two power sequencers and up to two eDP ports.
428 */
429 if (WARN_ON(pipes == 0))
a8c3344e
VS		 430 pipe = PIPE_A;
431 else
432 pipe = ffs(pipes) - 1;
a4a5d2f8 433
a8c3344e
VS		 434 vlv_steal_power_sequencer(dev, pipe);
435 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 436
437 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
438 pipe_name(intel_dp->pps_pipe),
439 port_name(intel_dig_port->port));
440
441 /* init power sequencer on this pipe and port */
36b5f425
VS		 442 intel_dp_init_panel_power_sequencer(dev, intel_dp);
443 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 444
961a0db0
VS		 445 /*
446 * Even vdd force doesn't work until we've made
447 * the power sequencer lock in on the port.
448 */
449 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 450
451 return intel_dp->pps_pipe;
452}
453
6491ab27
VS		 454typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
455 enum pipe pipe);
456
457static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
458 enum pipe pipe)
459{
460 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
461}
462
463static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
464 enum pipe pipe)
465{
466 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
467}
468
469static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
470 enum pipe pipe)
471{
472 return true;
473}
bf13e81b 474
a4a5d2f8 475static enum pipe
6491ab27
VS		 476vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
477 enum port port,
478 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 479{
480 enum pipe pipe;
bf13e81b 481
bf13e81b
JN		 482 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
483 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
484 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 485
486 if (port_sel != PANEL_PORT_SELECT_VLV(port))
487 continue;
488
6491ab27
VS		 489 if (!pipe_check(dev_priv, pipe))
490 continue;
491
a4a5d2f8 492 return pipe;
bf13e81b
JN		 493 }
494
a4a5d2f8
VS		 495 return INVALID_PIPE;
496}
497
498static void
499vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
500{
501 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
502 struct drm_device *dev = intel_dig_port->base.base.dev;
503 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 504 enum port port = intel_dig_port->port;
505
506 lockdep_assert_held(&dev_priv->pps_mutex);
507
508 /* try to find a pipe with this port selected */
6491ab27
VS		 509 /* first pick one where the panel is on */
510 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
511 vlv_pipe_has_pp_on);
512 /* didn't find one? pick one where vdd is on */
513 if (intel_dp->pps_pipe == INVALID_PIPE)
514 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
515 vlv_pipe_has_vdd_on);
516 /* didn't find one? pick one with just the correct port */
517 if (intel_dp->pps_pipe == INVALID_PIPE)
518 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
519 vlv_pipe_any);
a4a5d2f8
VS		 520
521 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
522 if (intel_dp->pps_pipe == INVALID_PIPE) {
523 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
524 port_name(port));
525 return;
bf13e81b
JN		 526 }
527
a4a5d2f8
VS		 528 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
529 port_name(port), pipe_name(intel_dp->pps_pipe));
530
36b5f425
VS		 531 intel_dp_init_panel_power_sequencer(dev, intel_dp);
532 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 533}
534
773538e8
VS		 535void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
536{
537 struct drm_device *dev = dev_priv->dev;
538 struct intel_encoder *encoder;
539
540 if (WARN_ON(!IS_VALLEYVIEW(dev)))
541 return;
542
543 /*
544 * We can't grab pps_mutex here due to deadlock with power_domain
545 * mutex when power_domain functions are called while holding pps_mutex.
546 * That also means that in order to use pps_pipe the code needs to
547 * hold both a power domain reference and pps_mutex, and the power domain
548 * reference get/put must be done while _not_ holding pps_mutex.
549 * pps_{lock,unlock}() do these steps in the correct order, so one
550 * should use them always.
551 */
552
553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
554 struct intel_dp *intel_dp;
555
556 if (encoder->type != INTEL_OUTPUT_EDP)
557 continue;
558
559 intel_dp = enc_to_intel_dp(&encoder->base);
560 intel_dp->pps_pipe = INVALID_PIPE;
561 }
bf13e81b
JN		 562}
563
564static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
565{
566 struct drm_device *dev = intel_dp_to_dev(intel_dp);
567
568 if (HAS_PCH_SPLIT(dev))
569 return PCH_PP_CONTROL;
570 else
571 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
572}
573
574static u32 _pp_stat_reg(struct intel_dp *intel_dp)
575{
576 struct drm_device *dev = intel_dp_to_dev(intel_dp);
577
578 if (HAS_PCH_SPLIT(dev))
579 return PCH_PP_STATUS;
580 else
581 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
582}
583
01527b31
CT		 584/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
585 This function only applicable when panel PM state is not to be tracked */
586static int edp_notify_handler(struct notifier_block *this, unsigned long code,
587 void *unused)
588{
589 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
590 edp_notifier);
591 struct drm_device *dev = intel_dp_to_dev(intel_dp);
592 struct drm_i915_private *dev_priv = dev->dev_private;
593 u32 pp_div;
594 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 595
596 if (!is_edp(intel_dp) || code != SYS_RESTART)
597 return 0;
598
773538e8 599 pps_lock(intel_dp);
e39b999a 600
01527b31 601 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 602 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
603
01527b31
CT		 604 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
605 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
606 pp_div = I915_READ(pp_div_reg);
607 pp_div &= PP_REFERENCE_DIVIDER_MASK;
608
609 /* 0x1F write to PP_DIV_REG sets max cycle delay */
610 I915_WRITE(pp_div_reg, pp_div | 0x1F);
611 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
612 msleep(intel_dp->panel_power_cycle_delay);
613 }
614
773538e8 615 pps_unlock(intel_dp);
e39b999a 616
01527b31
CT		 617 return 0;
618}
619
4be73780 620static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 621{
30add22d 622 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 623 struct drm_i915_private *dev_priv = dev->dev_private;
624
e39b999a
VS		 625 lockdep_assert_held(&dev_priv->pps_mutex);
626
9a42356b
VS		 627 if (IS_VALLEYVIEW(dev) &&
628 intel_dp->pps_pipe == INVALID_PIPE)
629 return false;
630
bf13e81b 631 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 632}
633
4be73780 634static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 635{
30add22d 636 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 637 struct drm_i915_private *dev_priv = dev->dev_private;
638
e39b999a
VS		 639 lockdep_assert_held(&dev_priv->pps_mutex);
640
9a42356b
VS		 641 if (IS_VALLEYVIEW(dev) &&
642 intel_dp->pps_pipe == INVALID_PIPE)
643 return false;
644
773538e8 645 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 646}
647
9b984dae
KP		 648static void
649intel_dp_check_edp(struct intel_dp *intel_dp)
650{
30add22d 651 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 652 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 653
9b984dae
KP		 654 if (!is_edp(intel_dp))
655 return;
453c5420 656
4be73780 657 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 658 WARN(1, "eDP powered off while attempting aux channel communication.\n");
659 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 660 I915_READ(_pp_stat_reg(intel_dp)),
661 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 662 }
663}
664
9ee32fea
DV		 665static uint32_t
666intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
667{
668 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
669 struct drm_device *dev = intel_dig_port->base.base.dev;
670 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 671 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 672 uint32_t status;
673 bool done;
674
ef04f00d 675#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 676 if (has_aux_irq)
b18ac466 677 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 678 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 679 else
680 done = wait_for_atomic(C, 10) == 0;
681 if (!done)
682 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
683 has_aux_irq);
684#undef C
685
686 return status;
687}
688
ec5b01dd 689static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 690{
174edf1f
PZ		 691 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
692 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 693
ec5b01dd
DL		 694 /*
695 * The clock divider is based off the hrawclk, and would like to run at
696 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 697 */
ec5b01dd
DL		 698 return index ? 0 : intel_hrawclk(dev) / 2;
699}
700
701static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
702{
703 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
704 struct drm_device *dev = intel_dig_port->base.base.dev;
469d4b2a 705 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd
DL		 706
707 if (index)
708 return 0;
709
710 if (intel_dig_port->port == PORT_A) {
469d4b2a 711 return DIV_ROUND_UP(dev_priv->display.get_display_clock_speed(dev), 2000);
ec5b01dd
DL		 712 } else {
713 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
714 }
715}
716
717static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
718{
719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
720 struct drm_device *dev = intel_dig_port->base.base.dev;
721 struct drm_i915_private *dev_priv = dev->dev_private;
722
723 if (intel_dig_port->port == PORT_A) {
724 if (index)
725 return 0;
1652d19e 726 return DIV_ROUND_CLOSEST(dev_priv->display.get_display_clock_speed(dev), 2000);
2c55c336
JN		 727 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
728 /* Workaround for non-ULT HSW */
bc86625a
CW		 729 switch (index) {
730 case 0: return 63;
731 case 1: return 72;
732 default: return 0;
733 }
ec5b01dd 734 } else {
bc86625a 735 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 736 }
b84a1cf8
RV		 737}
738
ec5b01dd
DL		 739static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
740{
741 return index ? 0 : 100;
742}
743
b6b5e383
DL		 744static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
745{
746 /*
747 * SKL doesn't need us to program the AUX clock divider (Hardware will
748 * derive the clock from CDCLK automatically). We still implement the
749 * get_aux_clock_divider vfunc to plug-in into the existing code.
750 */
751 return index ? 0 : 1;
752}
753
5ed12a19
DL		 754static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
755 bool has_aux_irq,
756 int send_bytes,
757 uint32_t aux_clock_divider)
758{
759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
760 struct drm_device *dev = intel_dig_port->base.base.dev;
761 uint32_t precharge, timeout;
762
763 if (IS_GEN6(dev))
764 precharge = 3;
765 else
766 precharge = 5;
767
768 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
769 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
770 else
771 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
772
773 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 774 DP_AUX_CH_CTL_DONE |
5ed12a19 775 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 776 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 777 timeout |
788d4433 778 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 779 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
780 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 781 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 782}
783
b9ca5fad
DL		 784static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
785 bool has_aux_irq,
786 int send_bytes,
787 uint32_t unused)
788{
789 return DP_AUX_CH_CTL_SEND_BUSY |
790 DP_AUX_CH_CTL_DONE |
791 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
792 DP_AUX_CH_CTL_TIME_OUT_ERROR |
793 DP_AUX_CH_CTL_TIME_OUT_1600us |
794 DP_AUX_CH_CTL_RECEIVE_ERROR |
795 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
796 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
797}
798
b84a1cf8
RV		 799static int
800intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 801 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 802 uint8_t *recv, int recv_size)
803{
804 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
805 struct drm_device *dev = intel_dig_port->base.base.dev;
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
808 uint32_t ch_data = ch_ctl + 4;
bc86625a 809 uint32_t aux_clock_divider;
b84a1cf8
RV		 810 int i, ret, recv_bytes;
811 uint32_t status;
5ed12a19 812 int try, clock = 0;
4e6b788c 813 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 814 bool vdd;
815
773538e8 816 pps_lock(intel_dp);
e39b999a 817
72c3500a
VS		 818 /*
819 * We will be called with VDD already enabled for dpcd/edid/oui reads.
820 * In such cases we want to leave VDD enabled and it's up to upper layers
821 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
822 * ourselves.
823 */
1e0560e0 824 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 825
826 /* dp aux is extremely sensitive to irq latency, hence request the
827 * lowest possible wakeup latency and so prevent the cpu from going into
828 * deep sleep states.
829 */
830 pm_qos_update_request(&dev_priv->pm_qos, 0);
831
832 intel_dp_check_edp(intel_dp);
5eb08b69 833
c67a470b
PZ		 834 intel_aux_display_runtime_get(dev_priv);
835
11bee43e
JB		 836 /* Try to wait for any previous AUX channel activity */
837 for (try = 0; try < 3; try++) {
ef04f00d 838 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 839 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
840 break;
841 msleep(1);
842 }
843
844 if (try == 3) {
845 WARN(1, "dp_aux_ch not started status 0x%08x\n",
846 I915_READ(ch_ctl));
9ee32fea
DV		 847 ret = -EBUSY;
848 goto out;
4f7f7b7e
CW		 849 }
850
46a5ae9f
PZ		 851 /* Only 5 data registers! */
852 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
853 ret = -E2BIG;
854 goto out;
855 }
856
ec5b01dd 857 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 858 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
859 has_aux_irq,
860 send_bytes,
861 aux_clock_divider);
5ed12a19 862
bc86625a
CW		 863 /* Must try at least 3 times according to DP spec */
864 for (try = 0; try < 5; try++) {
865 /* Load the send data into the aux channel data registers */
866 for (i = 0; i < send_bytes; i += 4)
867 I915_WRITE(ch_data + i,
a4f1289e
RV		 868 intel_dp_pack_aux(send + i,
869 send_bytes - i));
bc86625a
CW		 870
871 /* Send the command and wait for it to complete */
5ed12a19 872 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 873
874 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
875
876 /* Clear done status and any errors */
877 I915_WRITE(ch_ctl,
878 status |
879 DP_AUX_CH_CTL_DONE |
880 DP_AUX_CH_CTL_TIME_OUT_ERROR |
881 DP_AUX_CH_CTL_RECEIVE_ERROR);
882
74ebf294 883 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 884 continue;
74ebf294
TP		 885
886 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
887 * 400us delay required for errors and timeouts
888 * Timeout errors from the HW already meet this
889 * requirement so skip to next iteration
890 */
891 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
892 usleep_range(400, 500);
bc86625a 893 continue;
74ebf294 894 }
bc86625a
CW		 895 if (status & DP_AUX_CH_CTL_DONE)
896 break;
897 }
4f7f7b7e 898 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 899 break;
900 }
901
a4fc5ed6 902 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 903 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 904 ret = -EBUSY;
905 goto out;
a4fc5ed6
KP		 906 }
907
908 /* Check for timeout or receive error.
909 * Timeouts occur when the sink is not connected
910 */
a5b3da54 911 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 912 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 913 ret = -EIO;
914 goto out;
a5b3da54 915 }
1ae8c0a5
KP		 916
917 /* Timeouts occur when the device isn't connected, so they're
918 * "normal" -- don't fill the kernel log with these */
a5b3da54 919 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 920 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 921 ret = -ETIMEDOUT;
922 goto out;
a4fc5ed6
KP		 923 }
924
925 /* Unload any bytes sent back from the other side */
926 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
927 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 928 if (recv_bytes > recv_size)
929 recv_bytes = recv_size;
0206e353 930
4f7f7b7e 931 for (i = 0; i < recv_bytes; i += 4)
a4f1289e
RV		 932 intel_dp_unpack_aux(I915_READ(ch_data + i),
933 recv + i, recv_bytes - i);
a4fc5ed6 934
9ee32fea
DV		 935 ret = recv_bytes;
936out:
937 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 938 intel_aux_display_runtime_put(dev_priv);
9ee32fea 939
884f19e9
JN		 940 if (vdd)
941 edp_panel_vdd_off(intel_dp, false);
942
773538e8 943 pps_unlock(intel_dp);
e39b999a 944
9ee32fea 945 return ret;
a4fc5ed6
KP		 946}
947
a6c8aff0
JN		 948#define BARE_ADDRESS_SIZE 3
949#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 950static ssize_t
951intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 952{
9d1a1031
JN		 953 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
954 uint8_t txbuf[20], rxbuf[20];
955 size_t txsize, rxsize;
a4fc5ed6 956 int ret;
a4fc5ed6 957
d2d9cbbd
VS		 958 txbuf[0] = (msg->request << 4) |
959 ((msg->address >> 16) & 0xf);
960 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 961 txbuf[2] = msg->address & 0xff;
962 txbuf[3] = msg->size - 1;
46a5ae9f 963
9d1a1031
JN		 964 switch (msg->request & ~DP_AUX_I2C_MOT) {
965 case DP_AUX_NATIVE_WRITE:
966 case DP_AUX_I2C_WRITE:
a6c8aff0 967 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 968 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 969
9d1a1031
JN		 970 if (WARN_ON(txsize > 20))
971 return -E2BIG;
a4fc5ed6 972
9d1a1031 973 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 974
9d1a1031
JN		 975 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
976 if (ret > 0) {
977 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 978
a1ddefd8
JN		 979 if (ret > 1) {
980 /* Number of bytes written in a short write. */
981 ret = clamp_t(int, rxbuf[1], 0, msg->size);
982 } else {
983 /* Return payload size. */
984 ret = msg->size;
985 }
9d1a1031
JN		 986 }
987 break;
46a5ae9f 988
9d1a1031
JN		 989 case DP_AUX_NATIVE_READ:
990 case DP_AUX_I2C_READ:
a6c8aff0 991 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 992 rxsize = msg->size + 1;
a4fc5ed6 993
9d1a1031
JN		 994 if (WARN_ON(rxsize > 20))
995 return -E2BIG;
a4fc5ed6 996
9d1a1031
JN		 997 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
998 if (ret > 0) {
999 msg->reply = rxbuf[0] >> 4;
1000 /*
1001 * Assume happy day, and copy the data. The caller is
1002 * expected to check msg->reply before touching it.
1003 *
1004 * Return payload size.
1005 */
1006 ret--;
1007 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1008 }
9d1a1031
JN		 1009 break;
1010
1011 default:
1012 ret = -EINVAL;
1013 break;
a4fc5ed6 1014 }
f51a44b9 1015
9d1a1031 1016 return ret;
a4fc5ed6
KP		 1017}
1018
9d1a1031
JN		 1019static void
1020intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1021{
1022 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 1023 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1024 enum port port = intel_dig_port->port;
0b99836f 1025 const char *name = NULL;
ab2c0672
DA		 1026 int ret;
1027
33ad6626
JN		 1028 switch (port) {
1029 case PORT_A:
1030 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 1031 name = "DPDDC-A";
ab2c0672 1032 break;
33ad6626
JN		 1033 case PORT_B:
1034 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 1035 name = "DPDDC-B";
ab2c0672 1036 break;
33ad6626
JN		 1037 case PORT_C:
1038 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 1039 name = "DPDDC-C";
ab2c0672 1040 break;
33ad6626
JN		 1041 case PORT_D:
1042 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 1043 name = "DPDDC-D";
33ad6626
JN		 1044 break;
1045 default:
1046 BUG();
ab2c0672
DA		 1047 }
1048
1b1aad75
DL		 1049 /*
1050 * The AUX_CTL register is usually DP_CTL + 0x10.
1051 *
1052 * On Haswell and Broadwell though:
1053 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
1054 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
1055 *
1056 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
1057 */
1058 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 1059 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 1060
0b99836f 1061 intel_dp->aux.name = name;
9d1a1031
JN		 1062 intel_dp->aux.dev = dev->dev;
1063 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1064
0b99836f
JN		 1065 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
1066 connector->base.kdev->kobj.name);
8316f337 1067
4f71d0cb 1068 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1069 if (ret < 0) {
4f71d0cb 1070 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 1071 name, ret);
1072 return;
ab2c0672 1073 }
8a5e6aeb 1074
0b99836f
JN		 1075 ret = sysfs_create_link(&connector->base.kdev->kobj,
1076 &intel_dp->aux.ddc.dev.kobj,
1077 intel_dp->aux.ddc.dev.kobj.name);
1078 if (ret < 0) {
1079 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 1080 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 1081 }
a4fc5ed6
KP		 1082}
1083
80f65de3
ID		 1084static void
1085intel_dp_connector_unregister(struct intel_connector *intel_connector)
1086{
1087 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1088
0e32b39c
DA		 1089 if (!intel_connector->mst_port)
1090 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1091 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 1092 intel_connector_unregister(intel_connector);
1093}
1094
5416d871 1095static void
c3346ef6 1096skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
5416d871
DL		 1097{
1098 u32 ctrl1;
1099
1100 pipe_config->ddi_pll_sel = SKL_DPLL0;
1101 pipe_config->dpll_hw_state.cfgcr1 = 0;
1102 pipe_config->dpll_hw_state.cfgcr2 = 0;
1103
1104 ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
c3346ef6
SJ		 1105 switch (link_clock / 2) {
1106 case 81000:
71cd8423 1107 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5416d871
DL		 1108 SKL_DPLL0);
1109 break;
c3346ef6 1110 case 135000:
71cd8423 1111 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
5416d871
DL		 1112 SKL_DPLL0);
1113 break;
c3346ef6 1114 case 270000:
71cd8423 1115 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
5416d871
DL		 1116 SKL_DPLL0);
1117 break;
c3346ef6 1118 case 162000:
71cd8423 1119 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
c3346ef6
SJ		 1120 SKL_DPLL0);
1121 break;
1122 /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1123 results in CDCLK change. Need to handle the change of CDCLK by
1124 disabling pipes and re-enabling them */
1125 case 108000:
71cd8423 1126 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
c3346ef6
SJ		 1127 SKL_DPLL0);
1128 break;
1129 case 216000:
71cd8423 1130 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
c3346ef6
SJ		 1131 SKL_DPLL0);
1132 break;
1133
5416d871
DL		 1134 }
1135 pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1136}
1137
0e50338c 1138static void
5cec258b 1139hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
0e50338c
DV		 1140{
1141 switch (link_bw) {
1142 case DP_LINK_BW_1_62:
1143 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1144 break;
1145 case DP_LINK_BW_2_7:
1146 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1147 break;
1148 case DP_LINK_BW_5_4:
1149 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1150 break;
1151 }
1152}
1153
fc0f8e25 1154static int
12f6a2e2 1155intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1156{
94ca719e
VS		 1157 if (intel_dp->num_sink_rates) {
1158 *sink_rates = intel_dp->sink_rates;
1159 return intel_dp->num_sink_rates;
fc0f8e25 1160 }
12f6a2e2
VS		 1161
1162 *sink_rates = default_rates;
1163
1164 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1165}
1166
a8f3ef61 1167static int
1db10e28 1168intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
a8f3ef61 1169{
637a9c63
SJ		 1170 if (IS_SKYLAKE(dev)) {
1171 *source_rates = skl_rates;
1172 return ARRAY_SIZE(skl_rates);
fe51bfb9
VS		 1173 } else if (IS_CHERRYVIEW(dev)) {
1174 *source_rates = chv_rates;
1175 return ARRAY_SIZE(chv_rates);
a8f3ef61 1176 }
636280ba
VS		 1177
1178 *source_rates = default_rates;
1179
1db10e28
VS		 1180 if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
1181 /* WaDisableHBR2:skl */
1182 return (DP_LINK_BW_2_7 >> 3) + 1;
1183 else if (INTEL_INFO(dev)->gen >= 8 ||
1184 (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
1185 return (DP_LINK_BW_5_4 >> 3) + 1;
1186 else
1187 return (DP_LINK_BW_2_7 >> 3) + 1;
a8f3ef61
SJ		 1188}
1189
c6bb3538
DV		 1190static void
1191intel_dp_set_clock(struct intel_encoder *encoder,
5cec258b 1192 struct intel_crtc_state *pipe_config, int link_bw)
c6bb3538
DV		 1193{
1194 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1195 const struct dp_link_dpll *divisor = NULL;
1196 int i, count = 0;
c6bb3538
DV		 1197
1198 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1199 divisor = gen4_dpll;
1200 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1201 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1202 divisor = pch_dpll;
1203 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1204 } else if (IS_CHERRYVIEW(dev)) {
1205 divisor = chv_dpll;
1206 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1207 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1208 divisor = vlv_dpll;
1209 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1210 }
9dd4ffdf
CML		 1211
1212 if (divisor && count) {
1213 for (i = 0; i < count; i++) {
1214 if (link_bw == divisor[i].link_bw) {
1215 pipe_config->dpll = divisor[i].dpll;
1216 pipe_config->clock_set = true;
1217 break;
1218 }
1219 }
c6bb3538
DV		 1220 }
1221}
1222
2ecae76a
VS		 1223static int intersect_rates(const int *source_rates, int source_len,
1224 const int *sink_rates, int sink_len,
94ca719e 1225 int *common_rates)
a8f3ef61
SJ		 1226{
1227 int i = 0, j = 0, k = 0;
1228
a8f3ef61
SJ		 1229 while (i < source_len && j < sink_len) {
1230 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1231 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1232 return k;
94ca719e 1233 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1234 ++k;
1235 ++i;
1236 ++j;
1237 } else if (source_rates[i] < sink_rates[j]) {
1238 ++i;
1239 } else {
1240 ++j;
1241 }
1242 }
1243 return k;
1244}
1245
94ca719e
VS		 1246static int intel_dp_common_rates(struct intel_dp *intel_dp,
1247 int *common_rates)
2ecae76a
VS		 1248{
1249 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1250 const int *source_rates, *sink_rates;
1251 int source_len, sink_len;
1252
1253 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1254 source_len = intel_dp_source_rates(dev, &source_rates);
1255
1256 return intersect_rates(source_rates, source_len,
1257 sink_rates, sink_len,
94ca719e 1258 common_rates);
2ecae76a
VS		 1259}
1260
0336400e
VS		 1261static void snprintf_int_array(char *str, size_t len,
1262 const int *array, int nelem)
1263{
1264 int i;
1265
1266 str[0] = '\0';
1267
1268 for (i = 0; i < nelem; i++) {
1269 int r = snprintf(str, len, "%d,", array[i]);
1270 if (r >= len)
1271 return;
1272 str += r;
1273 len -= r;
1274 }
1275}
1276
1277static void intel_dp_print_rates(struct intel_dp *intel_dp)
1278{
1279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1280 const int *source_rates, *sink_rates;
94ca719e
VS		 1281 int source_len, sink_len, common_len;
1282 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1283 char str[128]; /* FIXME: too big for stack? */
1284
1285 if ((drm_debug & DRM_UT_KMS) == 0)
1286 return;
1287
1288 source_len = intel_dp_source_rates(dev, &source_rates);
1289 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1290 DRM_DEBUG_KMS("source rates: %s\n", str);
1291
1292 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1293 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1294 DRM_DEBUG_KMS("sink rates: %s\n", str);
1295
94ca719e
VS		 1296 common_len = intel_dp_common_rates(intel_dp, common_rates);
1297 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1298 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1299}
1300
f4896f15 1301static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1302{
1303 int i = 0;
1304
1305 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1306 if (find == rates[i])
1307 break;
1308
1309 return i;
1310}
1311
50fec21a
VS		 1312int
1313intel_dp_max_link_rate(struct intel_dp *intel_dp)
1314{
1315 int rates[DP_MAX_SUPPORTED_RATES] = {};
1316 int len;
1317
94ca719e 1318 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1319 if (WARN_ON(len <= 0))
1320 return 162000;
1321
1322 return rates[rate_to_index(0, rates) - 1];
1323}
1324
ed4e9c1d
VS		 1325int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1326{
94ca719e 1327 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1328}
1329
00c09d70 1330bool
5bfe2ac0 1331intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1332 struct intel_crtc_state *pipe_config)
a4fc5ed6 1333{
5bfe2ac0 1334 struct drm_device *dev = encoder->base.dev;
36008365 1335 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1336 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1338 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1339 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1340 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1341 int lane_count, clock;
56071a20 1342 int min_lane_count = 1;
eeb6324d 1343 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1344 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1345 int min_clock = 0;
a8f3ef61 1346 int max_clock;
083f9560 1347 int bpp, mode_rate;
ff9a6750 1348 int link_avail, link_clock;
94ca719e
VS		 1349 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1350 int common_len;
a8f3ef61 1351
94ca719e 1352 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1353
1354 /* No common link rates between source and sink */
94ca719e 1355 WARN_ON(common_len <= 0);
a8f3ef61 1356
94ca719e 1357 max_clock = common_len - 1;
a4fc5ed6 1358
bc7d38a4 1359 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1360 pipe_config->has_pch_encoder = true;
1361
03afc4a2 1362 pipe_config->has_dp_encoder = true;
f769cd24 1363 pipe_config->has_drrs = false;
9fcb1704 1364 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1365
dd06f90e
JN		 1366 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1367 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1368 adjusted_mode);
a1b2278e
CK		 1369
1370 if (INTEL_INFO(dev)->gen >= 9) {
1371 int ret;
1372 ret = skl_update_scaler_users(intel_crtc, pipe_config, NULL, NULL, 0);
1373 if (ret)
1374 return ret;
1375 }
1376
2dd24552
JB		 1377 if (!HAS_PCH_SPLIT(dev))
1378 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1379 intel_connector->panel.fitting_mode);
1380 else
b074cec8
JB		 1381 intel_pch_panel_fitting(intel_crtc, pipe_config,
1382 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1383 }
1384
cb1793ce 1385 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1386 return false;
1387
083f9560 1388 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1389 "max bw %d pixel clock %iKHz\n",
94ca719e 1390 max_lane_count, common_rates[max_clock],
241bfc38 1391 adjusted_mode->crtc_clock);
083f9560 1392
36008365
DV		 1393 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1394 * bpc in between. */
3e7ca985 1395 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1396 if (is_edp(intel_dp)) {
1397 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1398 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1399 dev_priv->vbt.edp_bpp);
1400 bpp = dev_priv->vbt.edp_bpp;
1401 }
1402
344c5bbc
JN		 1403 /*
1404 * Use the maximum clock and number of lanes the eDP panel
1405 * advertizes being capable of. The panels are generally
1406 * designed to support only a single clock and lane
1407 * configuration, and typically these values correspond to the
1408 * native resolution of the panel.
1409 */
1410 min_lane_count = max_lane_count;
1411 min_clock = max_clock;
7984211e 1412 }
657445fe 1413
36008365 1414 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1415 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1416 bpp);
36008365 1417
c6930992 1418 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1419 for (lane_count = min_lane_count;
1420 lane_count <= max_lane_count;
1421 lane_count <<= 1) {
1422
94ca719e 1423 link_clock = common_rates[clock];
36008365
DV		 1424 link_avail = intel_dp_max_data_rate(link_clock,
1425 lane_count);
1426
1427 if (mode_rate <= link_avail) {
1428 goto found;
1429 }
1430 }
1431 }
1432 }
c4867936 1433
36008365 1434 return false;
3685a8f3 1435
36008365 1436found:
55bc60db
VS		 1437 if (intel_dp->color_range_auto) {
1438 /*
1439 * See:
1440 * CEA-861-E - 5.1 Default Encoding Parameters
1441 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1442 */
18316c8c 1443 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1444 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1445 else
1446 intel_dp->color_range = 0;
1447 }
1448
3685a8f3 1449 if (intel_dp->color_range)
50f3b016 1450 pipe_config->limited_color_range = true;
a4fc5ed6 1451
36008365 1452 intel_dp->lane_count = lane_count;
a8f3ef61 1453
94ca719e 1454 if (intel_dp->num_sink_rates) {
bc27b7d3 1455 intel_dp->link_bw = 0;
a8f3ef61 1456 intel_dp->rate_select =
94ca719e 1457 intel_dp_rate_select(intel_dp, common_rates[clock]);
bc27b7d3
VS		 1458 } else {
1459 intel_dp->link_bw =
94ca719e 1460 drm_dp_link_rate_to_bw_code(common_rates[clock]);
bc27b7d3 1461 intel_dp->rate_select = 0;
a8f3ef61
SJ		 1462 }
1463
657445fe 1464 pipe_config->pipe_bpp = bpp;
94ca719e 1465 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1466
36008365
DV		 1467 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1468 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1469 pipe_config->port_clock, bpp);
36008365
DV		 1470 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1471 mode_rate, link_avail);
a4fc5ed6 1472
03afc4a2 1473 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1474 adjusted_mode->crtc_clock,
1475 pipe_config->port_clock,
03afc4a2 1476 &pipe_config->dp_m_n);
9d1a455b 1477
439d7ac0 1478 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1479 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1480 pipe_config->has_drrs = true;
439d7ac0
PB		 1481 intel_link_compute_m_n(bpp, lane_count,
1482 intel_connector->panel.downclock_mode->clock,
1483 pipe_config->port_clock,
1484 &pipe_config->dp_m2_n2);
1485 }
1486
5416d871 1487 if (IS_SKYLAKE(dev) && is_edp(intel_dp))
94ca719e 1488 skl_edp_set_pll_config(pipe_config, common_rates[clock]);
977bb38d
S		 1489 else if (IS_BROXTON(dev))
1490 /* handled in ddi */;
5416d871 1491 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1492 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1493 else
1494 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1495
03afc4a2 1496 return true;
a4fc5ed6
KP		 1497}
1498
7c62a164 1499static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1500{
7c62a164
DV		 1501 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1502 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1503 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 u32 dpa_ctl;
1506
6e3c9717
ACO		 1507 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n",
1508 crtc->config->port_clock);
ea9b6006
DV		 1509 dpa_ctl = I915_READ(DP_A);
1510 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1511
6e3c9717 1512 if (crtc->config->port_clock == 162000) {
1ce17038
DV		 1513 /* For a long time we've carried around a ILK-DevA w/a for the
1514 * 160MHz clock. If we're really unlucky, it's still required.
1515 */
1516 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1517 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1518 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1519 } else {
1520 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1521 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1522 }
1ce17038 1523
ea9b6006
DV		 1524 I915_WRITE(DP_A, dpa_ctl);
1525
1526 POSTING_READ(DP_A);
1527 udelay(500);
1528}
1529
8ac33ed3 1530static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1531{
b934223d 1532 struct drm_device *dev = encoder->base.dev;
417e822d 1533 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1534 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1535 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1536 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717 1537 struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1538
417e822d 1539 /*
1a2eb460 1540 * There are four kinds of DP registers:
417e822d
KP		 1541 *
1542 * IBX PCH
1a2eb460
KP		 1543 * SNB CPU
1544 * IVB CPU
417e822d
KP		 1545 * CPT PCH
1546 *
1547 * IBX PCH and CPU are the same for almost everything,
1548 * except that the CPU DP PLL is configured in this
1549 * register
1550 *
1551 * CPT PCH is quite different, having many bits moved
1552 * to the TRANS_DP_CTL register instead. That
1553 * configuration happens (oddly) in ironlake_pch_enable
1554 */
9c9e7927 1555
417e822d
KP		 1556 /* Preserve the BIOS-computed detected bit. This is
1557 * supposed to be read-only.
1558 */
1559 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1560
417e822d 1561 /* Handle DP bits in common between all three register formats */
417e822d 1562 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1563 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1564
6e3c9717 1565 if (crtc->config->has_audio)
ea5b213a 1566 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
247d89f6 1567
417e822d 1568 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1569
bc7d38a4 1570 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1571 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1572 intel_dp->DP |= DP_SYNC_HS_HIGH;
1573 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1574 intel_dp->DP |= DP_SYNC_VS_HIGH;
1575 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1576
6aba5b6c 1577 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1578 intel_dp->DP |= DP_ENHANCED_FRAMING;
1579
7c62a164 1580 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1581 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1582 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1583 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1584
1585 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1586 intel_dp->DP |= DP_SYNC_HS_HIGH;
1587 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1588 intel_dp->DP |= DP_SYNC_VS_HIGH;
1589 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1590
6aba5b6c 1591 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1592 intel_dp->DP |= DP_ENHANCED_FRAMING;
1593
44f37d1f
CML		 1594 if (!IS_CHERRYVIEW(dev)) {
1595 if (crtc->pipe == 1)
1596 intel_dp->DP |= DP_PIPEB_SELECT;
1597 } else {
1598 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1599 }
417e822d
KP		 1600 } else {
1601 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1602 }
a4fc5ed6
KP		 1603}
1604
ffd6749d
PZ		 1605#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1606#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1607
1a5ef5b7
PZ		 1608#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1609#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1610
ffd6749d
PZ		 1611#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1612#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1613
4be73780 1614static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1615 u32 mask,
1616 u32 value)
bd943159 1617{
30add22d 1618 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1619 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1620 u32 pp_stat_reg, pp_ctrl_reg;
1621
e39b999a
VS		 1622 lockdep_assert_held(&dev_priv->pps_mutex);
1623
bf13e81b
JN		 1624 pp_stat_reg = _pp_stat_reg(intel_dp);
1625 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1626
99ea7127 1627 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1628 mask, value,
1629 I915_READ(pp_stat_reg),
1630 I915_READ(pp_ctrl_reg));
32ce697c 1631
453c5420 1632 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1633 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1634 I915_READ(pp_stat_reg),
1635 I915_READ(pp_ctrl_reg));
32ce697c 1636 }
54c136d4
CW		 1637
1638 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1639}
32ce697c 1640
4be73780 1641static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1642{
1643 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1644 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1645}
1646
4be73780 1647static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1648{
1649 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1650 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1651}
1652
4be73780 1653static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1654{
1655 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1656
1657 /* When we disable the VDD override bit last we have to do the manual
1658 * wait. */
1659 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1660 intel_dp->panel_power_cycle_delay);
1661
4be73780 1662 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1663}
1664
4be73780 1665static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1666{
1667 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1668 intel_dp->backlight_on_delay);
1669}
1670
4be73780 1671static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1672{
1673 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1674 intel_dp->backlight_off_delay);
1675}
99ea7127 1676
832dd3c1
KP		 1677/* Read the current pp_control value, unlocking the register if it
1678 * is locked
1679 */
1680
453c5420 1681static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1682{
453c5420
JB		 1683 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 u32 control;
832dd3c1 1686
e39b999a
VS		 1687 lockdep_assert_held(&dev_priv->pps_mutex);
1688
bf13e81b 1689 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1690 control &= ~PANEL_UNLOCK_MASK;
1691 control |= PANEL_UNLOCK_REGS;
1692 return control;
bd943159
KP		 1693}
1694
951468f3
VS		 1695/*
1696 * Must be paired with edp_panel_vdd_off().
1697 * Must hold pps_mutex around the whole on/off sequence.
1698 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1699 */
1e0560e0 1700static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1701{
30add22d 1702 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1703 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1704 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1705 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1706 enum intel_display_power_domain power_domain;
5d613501 1707 u32 pp;
453c5420 1708 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1709 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1710
e39b999a
VS		 1711 lockdep_assert_held(&dev_priv->pps_mutex);
1712
97af61f5 1713 if (!is_edp(intel_dp))
adddaaf4 1714 return false;
bd943159 1715
2c623c11 1716 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1717 intel_dp->want_panel_vdd = true;
99ea7127 1718
4be73780 1719 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1720 return need_to_disable;
b0665d57 1721
4e6e1a54
ID		 1722 power_domain = intel_display_port_power_domain(intel_encoder);
1723 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1724
3936fcf4
VS		 1725 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1726 port_name(intel_dig_port->port));
bd943159 1727
4be73780
DV		 1728 if (!edp_have_panel_power(intel_dp))
1729 wait_panel_power_cycle(intel_dp);
99ea7127 1730
453c5420 1731 pp = ironlake_get_pp_control(intel_dp);
5d613501 1732 pp |= EDP_FORCE_VDD;
ebf33b18 1733
bf13e81b
JN		 1734 pp_stat_reg = _pp_stat_reg(intel_dp);
1735 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1736
1737 I915_WRITE(pp_ctrl_reg, pp);
1738 POSTING_READ(pp_ctrl_reg);
1739 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1740 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1741 /*
1742 * If the panel wasn't on, delay before accessing aux channel
1743 */
4be73780 1744 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1745 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1746 port_name(intel_dig_port->port));
f01eca2e 1747 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1748 }
adddaaf4
JN		 1749
1750 return need_to_disable;
1751}
1752
951468f3
VS		 1753/*
1754 * Must be paired with intel_edp_panel_vdd_off() or
1755 * intel_edp_panel_off().
1756 * Nested calls to these functions are not allowed since
1757 * we drop the lock. Caller must use some higher level
1758 * locking to prevent nested calls from other threads.
1759 */
b80d6c78 1760void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1761{
c695b6b6 1762 bool vdd;
adddaaf4 1763
c695b6b6
VS		 1764 if (!is_edp(intel_dp))
1765 return;
1766
773538e8 1767 pps_lock(intel_dp);
c695b6b6 1768 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1769 pps_unlock(intel_dp);
c695b6b6 1770
e2c719b7 1771 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1772 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1773}
1774
4be73780 1775static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1776{
30add22d 1777 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1778 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1779 struct intel_digital_port *intel_dig_port =
1780 dp_to_dig_port(intel_dp);
1781 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1782 enum intel_display_power_domain power_domain;
5d613501 1783 u32 pp;
453c5420 1784 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1785
e39b999a 1786 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1787
15e899a0 1788 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1789
15e899a0 1790 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1791 return;
b0665d57 1792
3936fcf4
VS		 1793 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1794 port_name(intel_dig_port->port));
bd943159 1795
be2c9196
VS		 1796 pp = ironlake_get_pp_control(intel_dp);
1797 pp &= ~EDP_FORCE_VDD;
453c5420 1798
be2c9196
VS		 1799 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1800 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1801
be2c9196
VS		 1802 I915_WRITE(pp_ctrl_reg, pp);
1803 POSTING_READ(pp_ctrl_reg);
90791a5c 1804
be2c9196
VS		 1805 /* Make sure sequencer is idle before allowing subsequent activity */
1806 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1807 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1808
be2c9196
VS		 1809 if ((pp & POWER_TARGET_ON) == 0)
1810 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1811
be2c9196
VS		 1812 power_domain = intel_display_port_power_domain(intel_encoder);
1813 intel_display_power_put(dev_priv, power_domain);
bd943159 1814}
5d613501 1815
4be73780 1816static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1817{
1818 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1819 struct intel_dp, panel_vdd_work);
bd943159 1820
773538e8 1821 pps_lock(intel_dp);
15e899a0
VS		 1822 if (!intel_dp->want_panel_vdd)
1823 edp_panel_vdd_off_sync(intel_dp);
773538e8 1824 pps_unlock(intel_dp);
bd943159
KP		 1825}
1826
aba86890
ID		 1827static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1828{
1829 unsigned long delay;
1830
1831 /*
1832 * Queue the timer to fire a long time from now (relative to the power
1833 * down delay) to keep the panel power up across a sequence of
1834 * operations.
1835 */
1836 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1837 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1838}
1839
951468f3
VS		 1840/*
1841 * Must be paired with edp_panel_vdd_on().
1842 * Must hold pps_mutex around the whole on/off sequence.
1843 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1844 */
4be73780 1845static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1846{
e39b999a
VS		 1847 struct drm_i915_private *dev_priv =
1848 intel_dp_to_dev(intel_dp)->dev_private;
1849
1850 lockdep_assert_held(&dev_priv->pps_mutex);
1851
97af61f5
KP		 1852 if (!is_edp(intel_dp))
1853 return;
5d613501 1854
e2c719b7 1855 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1856 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1857
bd943159
KP		 1858 intel_dp->want_panel_vdd = false;
1859
aba86890 1860 if (sync)
4be73780 1861 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1862 else
1863 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1864}
1865
9f0fb5be 1866static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1867{
30add22d 1868 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1869 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1870 u32 pp;
453c5420 1871 u32 pp_ctrl_reg;
9934c132 1872
9f0fb5be
VS		 1873 lockdep_assert_held(&dev_priv->pps_mutex);
1874
97af61f5 1875 if (!is_edp(intel_dp))
bd943159 1876 return;
99ea7127 1877
3936fcf4
VS		 1878 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1879 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1880
e7a89ace
VS		 1881 if (WARN(edp_have_panel_power(intel_dp),
1882 "eDP port %c panel power already on\n",
1883 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1884 return;
9934c132 1885
4be73780 1886 wait_panel_power_cycle(intel_dp);
37c6c9b0 1887
bf13e81b 1888 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1889 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1890 if (IS_GEN5(dev)) {
1891 /* ILK workaround: disable reset around power sequence */
1892 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1893 I915_WRITE(pp_ctrl_reg, pp);
1894 POSTING_READ(pp_ctrl_reg);
05ce1a49 1895 }
37c6c9b0 1896
1c0ae80a 1897 pp |= POWER_TARGET_ON;
99ea7127
KP		 1898 if (!IS_GEN5(dev))
1899 pp |= PANEL_POWER_RESET;
1900
453c5420
JB		 1901 I915_WRITE(pp_ctrl_reg, pp);
1902 POSTING_READ(pp_ctrl_reg);
9934c132 1903
4be73780 1904 wait_panel_on(intel_dp);
dce56b3c 1905 intel_dp->last_power_on = jiffies;
9934c132 1906
05ce1a49
KP		 1907 if (IS_GEN5(dev)) {
1908 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1909 I915_WRITE(pp_ctrl_reg, pp);
1910 POSTING_READ(pp_ctrl_reg);
05ce1a49 1911 }
9f0fb5be 1912}
e39b999a 1913
9f0fb5be
VS		 1914void intel_edp_panel_on(struct intel_dp *intel_dp)
1915{
1916 if (!is_edp(intel_dp))
1917 return;
1918
1919 pps_lock(intel_dp);
1920 edp_panel_on(intel_dp);
773538e8 1921 pps_unlock(intel_dp);
9934c132
JB		 1922}
1923
9f0fb5be
VS		 1924
1925static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1926{
4e6e1a54
ID		 1927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1928 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1930 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1931 enum intel_display_power_domain power_domain;
99ea7127 1932 u32 pp;
453c5420 1933 u32 pp_ctrl_reg;
9934c132 1934
9f0fb5be
VS		 1935 lockdep_assert_held(&dev_priv->pps_mutex);
1936
97af61f5
KP		 1937 if (!is_edp(intel_dp))
1938 return;
37c6c9b0 1939
3936fcf4
VS		 1940 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
1941 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 1942
3936fcf4
VS		 1943 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
1944 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 1945
453c5420 1946 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1947 /* We need to switch off panel power _and_ force vdd, for otherwise some
1948 * panels get very unhappy and cease to work. */
b3064154
PJ		 1949 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1950 EDP_BLC_ENABLE);
453c5420 1951
bf13e81b 1952 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1953
849e39f5
PZ		 1954 intel_dp->want_panel_vdd = false;
1955
453c5420
JB		 1956 I915_WRITE(pp_ctrl_reg, pp);
1957 POSTING_READ(pp_ctrl_reg);
9934c132 1958
dce56b3c 1959 intel_dp->last_power_cycle = jiffies;
4be73780 1960 wait_panel_off(intel_dp);
849e39f5
PZ		 1961
1962 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1963 power_domain = intel_display_port_power_domain(intel_encoder);
1964 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1965}
e39b999a 1966
9f0fb5be
VS		 1967void intel_edp_panel_off(struct intel_dp *intel_dp)
1968{
1969 if (!is_edp(intel_dp))
1970 return;
e39b999a 1971
9f0fb5be
VS		 1972 pps_lock(intel_dp);
1973 edp_panel_off(intel_dp);
773538e8 1974 pps_unlock(intel_dp);
9934c132
JB		 1975}
1976
1250d107
JN		 1977/* Enable backlight in the panel power control. */
1978static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1979{
da63a9f2
PZ		 1980 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1981 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 u32 pp;
453c5420 1984 u32 pp_ctrl_reg;
32f9d658 1985
01cb9ea6
JB		 1986 /*
1987 * If we enable the backlight right away following a panel power
1988 * on, we may see slight flicker as the panel syncs with the eDP
1989 * link. So delay a bit to make sure the image is solid before
1990 * allowing it to appear.
1991 */
4be73780 1992 wait_backlight_on(intel_dp);
e39b999a 1993
773538e8 1994 pps_lock(intel_dp);
e39b999a 1995
453c5420 1996 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1997 pp |= EDP_BLC_ENABLE;
453c5420 1998
bf13e81b 1999 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2000
2001 I915_WRITE(pp_ctrl_reg, pp);
2002 POSTING_READ(pp_ctrl_reg);
e39b999a 2003
773538e8 2004 pps_unlock(intel_dp);
32f9d658
ZW		 2005}
2006
1250d107
JN		 2007/* Enable backlight PWM and backlight PP control. */
2008void intel_edp_backlight_on(struct intel_dp *intel_dp)
2009{
2010 if (!is_edp(intel_dp))
2011 return;
2012
2013 DRM_DEBUG_KMS("\n");
2014
2015 intel_panel_enable_backlight(intel_dp->attached_connector);
2016 _intel_edp_backlight_on(intel_dp);
2017}
2018
2019/* Disable backlight in the panel power control. */
2020static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2021{
30add22d 2022 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 u32 pp;
453c5420 2025 u32 pp_ctrl_reg;
32f9d658 2026
f01eca2e
KP		 2027 if (!is_edp(intel_dp))
2028 return;
2029
773538e8 2030 pps_lock(intel_dp);
e39b999a 2031
453c5420 2032 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2033 pp &= ~EDP_BLC_ENABLE;
453c5420 2034
bf13e81b 2035 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2036
2037 I915_WRITE(pp_ctrl_reg, pp);
2038 POSTING_READ(pp_ctrl_reg);
f7d2323c 2039
773538e8 2040 pps_unlock(intel_dp);
e39b999a
VS		 2041
2042 intel_dp->last_backlight_off = jiffies;
f7d2323c 2043 edp_wait_backlight_off(intel_dp);
1250d107 2044}
f7d2323c 2045
1250d107
JN		 2046/* Disable backlight PP control and backlight PWM. */
2047void intel_edp_backlight_off(struct intel_dp *intel_dp)
2048{
2049 if (!is_edp(intel_dp))
2050 return;
2051
2052 DRM_DEBUG_KMS("\n");
f7d2323c 2053
1250d107 2054 _intel_edp_backlight_off(intel_dp);
f7d2323c 2055 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2056}
a4fc5ed6 2057
73580fb7
JN		 2058/*
2059 * Hook for controlling the panel power control backlight through the bl_power
2060 * sysfs attribute. Take care to handle multiple calls.
2061 */
2062static void intel_edp_backlight_power(struct intel_connector *connector,
2063 bool enable)
2064{
2065 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2066 bool is_enabled;
2067
773538e8 2068 pps_lock(intel_dp);
e39b999a 2069 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2070 pps_unlock(intel_dp);
73580fb7
JN		 2071
2072 if (is_enabled == enable)
2073 return;
2074
23ba9373
JN		 2075 DRM_DEBUG_KMS("panel power control backlight %s\n",
2076 enable ? "enable" : "disable");
73580fb7
JN		 2077
2078 if (enable)
2079 _intel_edp_backlight_on(intel_dp);
2080 else
2081 _intel_edp_backlight_off(intel_dp);
2082}
2083
2bd2ad64 2084static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2085{
da63a9f2
PZ		 2086 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2087 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2088 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2089 struct drm_i915_private *dev_priv = dev->dev_private;
2090 u32 dpa_ctl;
2091
2bd2ad64
DV		 2092 assert_pipe_disabled(dev_priv,
2093 to_intel_crtc(crtc)->pipe);
2094
d240f20f
JB		 2095 DRM_DEBUG_KMS("\n");
2096 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2097 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
2098 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2099
2100 /* We don't adjust intel_dp->DP while tearing down the link, to
2101 * facilitate link retraining (e.g. after hotplug). Hence clear all
2102 * enable bits here to ensure that we don't enable too much. */
2103 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
2104 intel_dp->DP |= DP_PLL_ENABLE;
2105 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2106 POSTING_READ(DP_A);
2107 udelay(200);
d240f20f
JB		 2108}
2109
2bd2ad64 2110static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2111{
da63a9f2
PZ		 2112 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2113 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2114 struct drm_device *dev = crtc->dev;
d240f20f
JB		 2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116 u32 dpa_ctl;
2117
2bd2ad64
DV		 2118 assert_pipe_disabled(dev_priv,
2119 to_intel_crtc(crtc)->pipe);
2120
d240f20f 2121 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 2122 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
2123 "dp pll off, should be on\n");
2124 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
2125
2126 /* We can't rely on the value tracked for the DP register in
2127 * intel_dp->DP because link_down must not change that (otherwise link
2128 * re-training will fail. */
298b0b39 2129 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 2130 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 2131 POSTING_READ(DP_A);
d240f20f
JB		 2132 udelay(200);
2133}
2134
c7ad3810 2135/* If the sink supports it, try to set the power state appropriately */
c19b0669 2136void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2137{
2138 int ret, i;
2139
2140 /* Should have a valid DPCD by this point */
2141 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2142 return;
2143
2144 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2145 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2146 DP_SET_POWER_D3);
c7ad3810
JB		 2147 } else {
2148 /*
2149 * When turning on, we need to retry for 1ms to give the sink
2150 * time to wake up.
2151 */
2152 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2153 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2154 DP_SET_POWER_D0);
c7ad3810
JB		 2155 if (ret == 1)
2156 break;
2157 msleep(1);
2158 }
2159 }
f9cac721
JN		 2160
2161 if (ret != 1)
2162 DRM_DEBUG_KMS("failed to %s sink power state\n",
2163 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2164}
2165
19d8fe15
DV		 2166static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2167 enum pipe *pipe)
d240f20f 2168{
19d8fe15 2169 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2170 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2171 struct drm_device *dev = encoder->base.dev;
2172 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2173 enum intel_display_power_domain power_domain;
2174 u32 tmp;
2175
2176 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 2177 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 2178 return false;
2179
2180 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2181
2182 if (!(tmp & DP_PORT_EN))
2183 return false;
2184
bc7d38a4 2185 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 2186 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 2187 } else if (IS_CHERRYVIEW(dev)) {
2188 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 2189 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 2190 *pipe = PORT_TO_PIPE(tmp);
2191 } else {
2192 u32 trans_sel;
2193 u32 trans_dp;
2194 int i;
2195
2196 switch (intel_dp->output_reg) {
2197 case PCH_DP_B:
2198 trans_sel = TRANS_DP_PORT_SEL_B;
2199 break;
2200 case PCH_DP_C:
2201 trans_sel = TRANS_DP_PORT_SEL_C;
2202 break;
2203 case PCH_DP_D:
2204 trans_sel = TRANS_DP_PORT_SEL_D;
2205 break;
2206 default:
2207 return true;
2208 }
2209
055e393f 2210 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 2211 trans_dp = I915_READ(TRANS_DP_CTL(i));
2212 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
2213 *pipe = i;
2214 return true;
2215 }
2216 }
19d8fe15 2217
4a0833ec
DV		 2218 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2219 intel_dp->output_reg);
2220 }
d240f20f 2221
19d8fe15
DV		 2222 return true;
2223}
d240f20f 2224
045ac3b5 2225static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2226 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2227{
2228 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2229 u32 tmp, flags = 0;
63000ef6
XZ		 2230 struct drm_device *dev = encoder->base.dev;
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 enum port port = dp_to_dig_port(intel_dp)->port;
2233 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 2234 int dotclock;
045ac3b5 2235
9ed109a7 2236 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2237
2238 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2239
63000ef6 2240 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 2241 if (tmp & DP_SYNC_HS_HIGH)
2242 flags |= DRM_MODE_FLAG_PHSYNC;
2243 else
2244 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2245
63000ef6
XZ		 2246 if (tmp & DP_SYNC_VS_HIGH)
2247 flags |= DRM_MODE_FLAG_PVSYNC;
2248 else
2249 flags |= DRM_MODE_FLAG_NVSYNC;
2250 } else {
2251 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2252 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2253 flags |= DRM_MODE_FLAG_PHSYNC;
2254 else
2255 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2256
63000ef6
XZ		 2257 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2258 flags |= DRM_MODE_FLAG_PVSYNC;
2259 else
2260 flags |= DRM_MODE_FLAG_NVSYNC;
2261 }
045ac3b5 2262
2d112de7 2263 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2264
8c875fca
VS		 2265 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2266 tmp & DP_COLOR_RANGE_16_235)
2267 pipe_config->limited_color_range = true;
2268
eb14cb74
VS		 2269 pipe_config->has_dp_encoder = true;
2270
2271 intel_dp_get_m_n(crtc, pipe_config);
2272
18442d08 2273 if (port == PORT_A) {
f1f644dc
JB		 2274 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
2275 pipe_config->port_clock = 162000;
2276 else
2277 pipe_config->port_clock = 270000;
2278 }
18442d08
VS		 2279
2280 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2281 &pipe_config->dp_m_n);
2282
2283 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2284 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2285
2d112de7 2286 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
7f16e5c1 2287
c6cd2ee2
JN		 2288 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2289 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2290 /*
2291 * This is a big fat ugly hack.
2292 *
2293 * Some machines in UEFI boot mode provide us a VBT that has 18
2294 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2295 * unknown we fail to light up. Yet the same BIOS boots up with
2296 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2297 * max, not what it tells us to use.
2298 *
2299 * Note: This will still be broken if the eDP panel is not lit
2300 * up by the BIOS, and thus we can't get the mode at module
2301 * load.
2302 */
2303 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2304 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2305 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2306 }
045ac3b5
JB		 2307}
2308
e8cb4558 2309static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2310{
e8cb4558 2311 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2312 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2313 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2314
6e3c9717 2315 if (crtc->config->has_audio)
495a5bb8 2316 intel_audio_codec_disable(encoder);
6cb49835 2317
b32c6f48
RV		 2318 if (HAS_PSR(dev) && !HAS_DDI(dev))
2319 intel_psr_disable(intel_dp);
2320
6cb49835
DV		 2321 /* Make sure the panel is off before trying to change the mode. But also
2322 * ensure that we have vdd while we switch off the panel. */
24f3e092 2323 intel_edp_panel_vdd_on(intel_dp);
4be73780 2324 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2325 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2326 intel_edp_panel_off(intel_dp);
3739850b 2327
08aff3fe
VS		 2328 /* disable the port before the pipe on g4x */
2329 if (INTEL_INFO(dev)->gen < 5)
3739850b 2330 intel_dp_link_down(intel_dp);
d240f20f
JB		 2331}
2332
08aff3fe 2333static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2334{
2bd2ad64 2335 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2336 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2337
49277c31 2338 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2339 if (port == PORT_A)
2340 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2341}
2342
2343static void vlv_post_disable_dp(struct intel_encoder *encoder)
2344{
2345 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2346
2347 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2348}
2349
580d3811
VS		 2350static void chv_post_disable_dp(struct intel_encoder *encoder)
2351{
2352 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2353 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2354 struct drm_device *dev = encoder->base.dev;
2355 struct drm_i915_private *dev_priv = dev->dev_private;
2356 struct intel_crtc *intel_crtc =
2357 to_intel_crtc(encoder->base.crtc);
2358 enum dpio_channel ch = vlv_dport_to_channel(dport);
2359 enum pipe pipe = intel_crtc->pipe;
2360 u32 val;
2361
2362 intel_dp_link_down(intel_dp);
2363
2364 mutex_lock(&dev_priv->dpio_lock);
2365
2366 /* Propagate soft reset to data lane reset */
97fd4d5c 2367 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2368 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2369 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2370
97fd4d5c
VS		 2371 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2372 val |= CHV_PCS_REQ_SOFTRESET_EN;
2373 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2374
2375 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2376 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2377 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2378
2379 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2380 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2381 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2382
2383 mutex_unlock(&dev_priv->dpio_lock);
2384}
2385
7b13b58a
VS		 2386static void
2387_intel_dp_set_link_train(struct intel_dp *intel_dp,
2388 uint32_t *DP,
2389 uint8_t dp_train_pat)
2390{
2391 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2392 struct drm_device *dev = intel_dig_port->base.base.dev;
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2394 enum port port = intel_dig_port->port;
2395
2396 if (HAS_DDI(dev)) {
2397 uint32_t temp = I915_READ(DP_TP_CTL(port));
2398
2399 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2400 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2401 else
2402 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2403
2404 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2405 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2406 case DP_TRAINING_PATTERN_DISABLE:
2407 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2408
2409 break;
2410 case DP_TRAINING_PATTERN_1:
2411 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2412 break;
2413 case DP_TRAINING_PATTERN_2:
2414 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2415 break;
2416 case DP_TRAINING_PATTERN_3:
2417 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2418 break;
2419 }
2420 I915_WRITE(DP_TP_CTL(port), temp);
2421
2422 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2423 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2424
2425 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2426 case DP_TRAINING_PATTERN_DISABLE:
2427 *DP |= DP_LINK_TRAIN_OFF_CPT;
2428 break;
2429 case DP_TRAINING_PATTERN_1:
2430 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2431 break;
2432 case DP_TRAINING_PATTERN_2:
2433 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2434 break;
2435 case DP_TRAINING_PATTERN_3:
2436 DRM_ERROR("DP training pattern 3 not supported\n");
2437 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2438 break;
2439 }
2440
2441 } else {
2442 if (IS_CHERRYVIEW(dev))
2443 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2444 else
2445 *DP &= ~DP_LINK_TRAIN_MASK;
2446
2447 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2448 case DP_TRAINING_PATTERN_DISABLE:
2449 *DP |= DP_LINK_TRAIN_OFF;
2450 break;
2451 case DP_TRAINING_PATTERN_1:
2452 *DP |= DP_LINK_TRAIN_PAT_1;
2453 break;
2454 case DP_TRAINING_PATTERN_2:
2455 *DP |= DP_LINK_TRAIN_PAT_2;
2456 break;
2457 case DP_TRAINING_PATTERN_3:
2458 if (IS_CHERRYVIEW(dev)) {
2459 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2460 } else {
2461 DRM_ERROR("DP training pattern 3 not supported\n");
2462 *DP |= DP_LINK_TRAIN_PAT_2;
2463 }
2464 break;
2465 }
2466 }
2467}
2468
2469static void intel_dp_enable_port(struct intel_dp *intel_dp)
2470{
2471 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2472 struct drm_i915_private *dev_priv = dev->dev_private;
2473
7b13b58a
VS		 2474 /* enable with pattern 1 (as per spec) */
2475 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2476 DP_TRAINING_PATTERN_1);
2477
2478 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2479 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2480
2481 /*
2482 * Magic for VLV/CHV. We _must_ first set up the register
2483 * without actually enabling the port, and then do another
2484 * write to enable the port. Otherwise link training will
2485 * fail when the power sequencer is freshly used for this port.
2486 */
2487 intel_dp->DP |= DP_PORT_EN;
2488
2489 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2490 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2491}
2492
e8cb4558 2493static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2494{
e8cb4558
DV		 2495 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2496 struct drm_device *dev = encoder->base.dev;
2497 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2498 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2499 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
9b6de0a1 2500 unsigned int lane_mask = 0x0;
5d613501 2501
0c33d8d7
DV		 2502 if (WARN_ON(dp_reg & DP_PORT_EN))
2503 return;
5d613501 2504
093e3f13
VS		 2505 pps_lock(intel_dp);
2506
2507 if (IS_VALLEYVIEW(dev))
2508 vlv_init_panel_power_sequencer(intel_dp);
2509
7b13b58a 2510 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2511
2512 edp_panel_vdd_on(intel_dp);
2513 edp_panel_on(intel_dp);
2514 edp_panel_vdd_off(intel_dp, true);
2515
2516 pps_unlock(intel_dp);
2517
61234fa5 2518 if (IS_VALLEYVIEW(dev))
9b6de0a1
VS		 2519 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2520 lane_mask);
61234fa5 2521
f01eca2e 2522 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2523 intel_dp_start_link_train(intel_dp);
33a34e4e 2524 intel_dp_complete_link_train(intel_dp);
3ab9c637 2525 intel_dp_stop_link_train(intel_dp);
c1dec79a 2526
6e3c9717 2527 if (crtc->config->has_audio) {
c1dec79a
JN		 2528 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2529 pipe_name(crtc->pipe));
2530 intel_audio_codec_enable(encoder);
2531 }
ab1f90f9 2532}
89b667f8 2533
ecff4f3b
JN		 2534static void g4x_enable_dp(struct intel_encoder *encoder)
2535{
828f5c6e
JN		 2536 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2537
ecff4f3b 2538 intel_enable_dp(encoder);
4be73780 2539 intel_edp_backlight_on(intel_dp);
ab1f90f9 2540}
89b667f8 2541
ab1f90f9
JN		 2542static void vlv_enable_dp(struct intel_encoder *encoder)
2543{
828f5c6e
JN		 2544 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2545
4be73780 2546 intel_edp_backlight_on(intel_dp);
b32c6f48 2547 intel_psr_enable(intel_dp);
d240f20f
JB		 2548}
2549
ecff4f3b 2550static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2551{
2552 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2553 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2554
8ac33ed3
DV		 2555 intel_dp_prepare(encoder);
2556
d41f1efb
DV		 2557 /* Only ilk+ has port A */
2558 if (dport->port == PORT_A) {
2559 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2560 ironlake_edp_pll_on(intel_dp);
d41f1efb 2561 }
ab1f90f9
JN		 2562}
2563
83b84597
VS		 2564static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2565{
2566 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2567 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2568 enum pipe pipe = intel_dp->pps_pipe;
2569 int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2570
2571 edp_panel_vdd_off_sync(intel_dp);
2572
2573 /*
2574 * VLV seems to get confused when multiple power seqeuencers
2575 * have the same port selected (even if only one has power/vdd
2576 * enabled). The failure manifests as vlv_wait_port_ready() failing
2577 * CHV on the other hand doesn't seem to mind having the same port
2578 * selected in multiple power seqeuencers, but let's clear the
2579 * port select always when logically disconnecting a power sequencer
2580 * from a port.
2581 */
2582 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2583 pipe_name(pipe), port_name(intel_dig_port->port));
2584 I915_WRITE(pp_on_reg, 0);
2585 POSTING_READ(pp_on_reg);
2586
2587 intel_dp->pps_pipe = INVALID_PIPE;
2588}
2589
a4a5d2f8
VS		 2590static void vlv_steal_power_sequencer(struct drm_device *dev,
2591 enum pipe pipe)
2592{
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2594 struct intel_encoder *encoder;
2595
2596 lockdep_assert_held(&dev_priv->pps_mutex);
2597
ac3c12e4
VS		 2598 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2599 return;
2600
a4a5d2f8
VS		 2601 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2602 base.head) {
2603 struct intel_dp *intel_dp;
773538e8 2604 enum port port;
a4a5d2f8
VS		 2605
2606 if (encoder->type != INTEL_OUTPUT_EDP)
2607 continue;
2608
2609 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2610 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2611
2612 if (intel_dp->pps_pipe != pipe)
2613 continue;
2614
2615 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2616 pipe_name(pipe), port_name(port));
a4a5d2f8 2617
034e43c6
VS		 2618 WARN(encoder->connectors_active,
2619 "stealing pipe %c power sequencer from active eDP port %c\n",
2620 pipe_name(pipe), port_name(port));
a4a5d2f8 2621
a4a5d2f8 2622 /* make sure vdd is off before we steal it */
83b84597 2623 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2624 }
2625}
2626
2627static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2628{
2629 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2630 struct intel_encoder *encoder = &intel_dig_port->base;
2631 struct drm_device *dev = encoder->base.dev;
2632 struct drm_i915_private *dev_priv = dev->dev_private;
2633 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2634
2635 lockdep_assert_held(&dev_priv->pps_mutex);
2636
093e3f13
VS		 2637 if (!is_edp(intel_dp))
2638 return;
2639
a4a5d2f8
VS		 2640 if (intel_dp->pps_pipe == crtc->pipe)
2641 return;
2642
2643 /*
2644 * If another power sequencer was being used on this
2645 * port previously make sure to turn off vdd there while
2646 * we still have control of it.
2647 */
2648 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2649 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2650
2651 /*
2652 * We may be stealing the power
2653 * sequencer from another port.
2654 */
2655 vlv_steal_power_sequencer(dev, crtc->pipe);
2656
2657 /* now it's all ours */
2658 intel_dp->pps_pipe = crtc->pipe;
2659
2660 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2661 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2662
2663 /* init power sequencer on this pipe and port */
36b5f425
VS		 2664 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2665 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2666}
2667
ab1f90f9 2668static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2669{
2bd2ad64 2670 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2671 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2672 struct drm_device *dev = encoder->base.dev;
89b667f8 2673 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2674 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2675 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2676 int pipe = intel_crtc->pipe;
2677 u32 val;
a4fc5ed6 2678
ab1f90f9 2679 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2680
ab3c759a 2681 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2682 val = 0;
2683 if (pipe)
2684 val |= (1<<21);
2685 else
2686 val &= ~(1<<21);
2687 val |= 0x001000c4;
ab3c759a
CML		 2688 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2689 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2690 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2691
ab1f90f9
JN		 2692 mutex_unlock(&dev_priv->dpio_lock);
2693
2694 intel_enable_dp(encoder);
89b667f8
JB		 2695}
2696
ecff4f3b 2697static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2698{
2699 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2700 struct drm_device *dev = encoder->base.dev;
2701 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2702 struct intel_crtc *intel_crtc =
2703 to_intel_crtc(encoder->base.crtc);
e4607fcf 2704 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2705 int pipe = intel_crtc->pipe;
89b667f8 2706
8ac33ed3
DV		 2707 intel_dp_prepare(encoder);
2708
89b667f8 2709 /* Program Tx lane resets to default */
0980a60f 2710 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2711 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2712 DPIO_PCS_TX_LANE2_RESET |
2713 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2714 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2715 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2716 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2717 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2718 DPIO_PCS_CLK_SOFT_RESET);
2719
2720 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2721 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2722 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2723 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2724 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2725}
2726
e4a1d846
CML		 2727static void chv_pre_enable_dp(struct intel_encoder *encoder)
2728{
2729 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2730 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2731 struct drm_device *dev = encoder->base.dev;
2732 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2733 struct intel_crtc *intel_crtc =
2734 to_intel_crtc(encoder->base.crtc);
2735 enum dpio_channel ch = vlv_dport_to_channel(dport);
2736 int pipe = intel_crtc->pipe;
2e523e98 2737 int data, i, stagger;
949c1d43 2738 u32 val;
e4a1d846 2739
e4a1d846 2740 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2741
570e2a74
VS		 2742 /* allow hardware to manage TX FIFO reset source */
2743 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2744 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2746
2747 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2748 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2749 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2750
949c1d43 2751 /* Deassert soft data lane reset*/
97fd4d5c 2752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2753 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2754 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2755
2756 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2757 val |= CHV_PCS_REQ_SOFTRESET_EN;
2758 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2759
2760 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2761 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2762 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2763
97fd4d5c 2764 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2765 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2766 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2767
2768 /* Program Tx lane latency optimal setting*/
e4a1d846 2769 for (i = 0; i < 4; i++) {
e4a1d846
CML		 2770 /* Set the upar bit */
2771 data = (i == 1) ? 0x0 : 0x1;
2772 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2773 data << DPIO_UPAR_SHIFT);
2774 }
2775
2776 /* Data lane stagger programming */
2e523e98
VS		 2777 if (intel_crtc->config->port_clock > 270000)
2778 stagger = 0x18;
2779 else if (intel_crtc->config->port_clock > 135000)
2780 stagger = 0xd;
2781 else if (intel_crtc->config->port_clock > 67500)
2782 stagger = 0x7;
2783 else if (intel_crtc->config->port_clock > 33750)
2784 stagger = 0x4;
2785 else
2786 stagger = 0x2;
2787
2788 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2789 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2790 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2791
2792 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2793 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2794 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2795
2796 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2797 DPIO_LANESTAGGER_STRAP(stagger) |
2798 DPIO_LANESTAGGER_STRAP_OVRD |
2799 DPIO_TX1_STAGGER_MASK(0x1f) |
2800 DPIO_TX1_STAGGER_MULT(6) |
2801 DPIO_TX2_STAGGER_MULT(0));
2802
2803 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2804 DPIO_LANESTAGGER_STRAP(stagger) |
2805 DPIO_LANESTAGGER_STRAP_OVRD |
2806 DPIO_TX1_STAGGER_MASK(0x1f) |
2807 DPIO_TX1_STAGGER_MULT(7) |
2808 DPIO_TX2_STAGGER_MULT(5));
e4a1d846
CML		 2809
2810 mutex_unlock(&dev_priv->dpio_lock);
2811
e4a1d846 2812 intel_enable_dp(encoder);
e4a1d846
CML		 2813}
2814
9197c88b
VS		 2815static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2816{
2817 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2818 struct drm_device *dev = encoder->base.dev;
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820 struct intel_crtc *intel_crtc =
2821 to_intel_crtc(encoder->base.crtc);
2822 enum dpio_channel ch = vlv_dport_to_channel(dport);
2823 enum pipe pipe = intel_crtc->pipe;
2824 u32 val;
2825
625695f8
VS		 2826 intel_dp_prepare(encoder);
2827
9197c88b
VS		 2828 mutex_lock(&dev_priv->dpio_lock);
2829
b9e5ac3c
VS		 2830 /* program left/right clock distribution */
2831 if (pipe != PIPE_B) {
2832 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2833 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2834 if (ch == DPIO_CH0)
2835 val |= CHV_BUFLEFTENA1_FORCE;
2836 if (ch == DPIO_CH1)
2837 val |= CHV_BUFRIGHTENA1_FORCE;
2838 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2839 } else {
2840 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2841 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2842 if (ch == DPIO_CH0)
2843 val |= CHV_BUFLEFTENA2_FORCE;
2844 if (ch == DPIO_CH1)
2845 val |= CHV_BUFRIGHTENA2_FORCE;
2846 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2847 }
2848
9197c88b
VS		 2849 /* program clock channel usage */
2850 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2851 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2852 if (pipe != PIPE_B)
2853 val &= ~CHV_PCS_USEDCLKCHANNEL;
2854 else
2855 val |= CHV_PCS_USEDCLKCHANNEL;
2856 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2857
2858 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2859 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2860 if (pipe != PIPE_B)
2861 val &= ~CHV_PCS_USEDCLKCHANNEL;
2862 else
2863 val |= CHV_PCS_USEDCLKCHANNEL;
2864 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2865
2866 /*
2867 * This a a bit weird since generally CL
2868 * matches the pipe, but here we need to
2869 * pick the CL based on the port.
2870 */
2871 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2872 if (pipe != PIPE_B)
2873 val &= ~CHV_CMN_USEDCLKCHANNEL;
2874 else
2875 val |= CHV_CMN_USEDCLKCHANNEL;
2876 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2877
2878 mutex_unlock(&dev_priv->dpio_lock);
2879}
2880
a4fc5ed6 2881/*
df0c237d
JB		 2882 * Native read with retry for link status and receiver capability reads for
2883 * cases where the sink may still be asleep.
9d1a1031
JN		 2884 *
2885 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2886 * supposed to retry 3 times per the spec.
a4fc5ed6 2887 */
9d1a1031
JN		 2888static ssize_t
2889intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2890 void *buffer, size_t size)
a4fc5ed6 2891{
9d1a1031
JN		 2892 ssize_t ret;
2893 int i;
61da5fab 2894
f6a19066
VS		 2895 /*
2896 * Sometime we just get the same incorrect byte repeated
2897 * over the entire buffer. Doing just one throw away read
2898 * initially seems to "solve" it.
2899 */
2900 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
2901
61da5fab 2902 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2903 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2904 if (ret == size)
2905 return ret;
61da5fab
JB		 2906 msleep(1);
2907 }
a4fc5ed6 2908
9d1a1031 2909 return ret;
a4fc5ed6
KP		 2910}
2911
2912/*
2913 * Fetch AUX CH registers 0x202 - 0x207 which contain
2914 * link status information
2915 */
2916static bool
93f62dad 2917intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2918{
9d1a1031
JN		 2919 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2920 DP_LANE0_1_STATUS,
2921 link_status,
2922 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2923}
2924
1100244e 2925/* These are source-specific values. */
a4fc5ed6 2926static uint8_t
1a2eb460 2927intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2928{
30add22d 2929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 2930 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 2931 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2932
9314726b
VK		 2933 if (IS_BROXTON(dev))
2934 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2935 else if (INTEL_INFO(dev)->gen >= 9) {
9e458034 2936 if (dev_priv->edp_low_vswing && port == PORT_A)
7ad14a29 2937 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2938 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
7ad14a29 2939 } else if (IS_VALLEYVIEW(dev))
bd60018a 2940 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2941 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2942 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2943 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2944 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2945 else
bd60018a 2946 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2947}
2948
2949static uint8_t
2950intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2951{
30add22d 2952 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2953 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2954
5a9d1f1a
DL		 2955 if (INTEL_INFO(dev)->gen >= 9) {
2956 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2957 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2958 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2960 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2961 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2962 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 2963 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
2964 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 2965 default:
2966 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2967 }
2968 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2969 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2971 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2972 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2973 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2975 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2977 default:
bd60018a 2978 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2979 }
e2fa6fba
P		 2980 } else if (IS_VALLEYVIEW(dev)) {
2981 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2982 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2983 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2984 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2985 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2986 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2987 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2988 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2989 default:
bd60018a 2990 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2991 }
bc7d38a4 2992 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2993 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2994 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2995 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2996 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2997 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2998 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2999 default:
bd60018a 3000 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3001 }
3002 } else {
3003 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3005 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3006 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3007 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3008 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3009 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3010 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3011 default:
bd60018a 3012 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3013 }
a4fc5ed6
KP		 3014 }
3015}
3016
5829975c 3017static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3018{
3019 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3020 struct drm_i915_private *dev_priv = dev->dev_private;
3021 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3022 struct intel_crtc *intel_crtc =
3023 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3024 unsigned long demph_reg_value, preemph_reg_value,
3025 uniqtranscale_reg_value;
3026 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3027 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3028 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3029
3030 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3031 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3032 preemph_reg_value = 0x0004000;
3033 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3035 demph_reg_value = 0x2B405555;
3036 uniqtranscale_reg_value = 0x552AB83A;
3037 break;
bd60018a 3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3039 demph_reg_value = 0x2B404040;
3040 uniqtranscale_reg_value = 0x5548B83A;
3041 break;
bd60018a 3042 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3043 demph_reg_value = 0x2B245555;
3044 uniqtranscale_reg_value = 0x5560B83A;
3045 break;
bd60018a 3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3047 demph_reg_value = 0x2B405555;
3048 uniqtranscale_reg_value = 0x5598DA3A;
3049 break;
3050 default:
3051 return 0;
3052 }
3053 break;
bd60018a 3054 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3055 preemph_reg_value = 0x0002000;
3056 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3058 demph_reg_value = 0x2B404040;
3059 uniqtranscale_reg_value = 0x5552B83A;
3060 break;
bd60018a 3061 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3062 demph_reg_value = 0x2B404848;
3063 uniqtranscale_reg_value = 0x5580B83A;
3064 break;
bd60018a 3065 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3066 demph_reg_value = 0x2B404040;
3067 uniqtranscale_reg_value = 0x55ADDA3A;
3068 break;
3069 default:
3070 return 0;
3071 }
3072 break;
bd60018a 3073 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3074 preemph_reg_value = 0x0000000;
3075 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3077 demph_reg_value = 0x2B305555;
3078 uniqtranscale_reg_value = 0x5570B83A;
3079 break;
bd60018a 3080 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3081 demph_reg_value = 0x2B2B4040;
3082 uniqtranscale_reg_value = 0x55ADDA3A;
3083 break;
3084 default:
3085 return 0;
3086 }
3087 break;
bd60018a 3088 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3089 preemph_reg_value = 0x0006000;
3090 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3091 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3092 demph_reg_value = 0x1B405555;
3093 uniqtranscale_reg_value = 0x55ADDA3A;
3094 break;
3095 default:
3096 return 0;
3097 }
3098 break;
3099 default:
3100 return 0;
3101 }
3102
0980a60f 3103 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3104 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3105 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3106 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3107 uniqtranscale_reg_value);
ab3c759a
CML		 3108 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3109 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3110 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3111 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3112 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3113
3114 return 0;
3115}
3116
5829975c 3117static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3118{
3119 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3120 struct drm_i915_private *dev_priv = dev->dev_private;
3121 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3122 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3123 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3124 uint8_t train_set = intel_dp->train_set[0];
3125 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3126 enum pipe pipe = intel_crtc->pipe;
3127 int i;
e4a1d846
CML		 3128
3129 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3130 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3131 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3132 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3133 deemph_reg_value = 128;
3134 margin_reg_value = 52;
3135 break;
bd60018a 3136 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3137 deemph_reg_value = 128;
3138 margin_reg_value = 77;
3139 break;
bd60018a 3140 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3141 deemph_reg_value = 128;
3142 margin_reg_value = 102;
3143 break;
bd60018a 3144 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3145 deemph_reg_value = 128;
3146 margin_reg_value = 154;
3147 /* FIXME extra to set for 1200 */
3148 break;
3149 default:
3150 return 0;
3151 }
3152 break;
bd60018a 3153 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3154 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3155 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3156 deemph_reg_value = 85;
3157 margin_reg_value = 78;
3158 break;
bd60018a 3159 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3160 deemph_reg_value = 85;
3161 margin_reg_value = 116;
3162 break;
bd60018a 3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3164 deemph_reg_value = 85;
3165 margin_reg_value = 154;
3166 break;
3167 default:
3168 return 0;
3169 }
3170 break;
bd60018a 3171 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3172 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3173 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3174 deemph_reg_value = 64;
3175 margin_reg_value = 104;
3176 break;
bd60018a 3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3178 deemph_reg_value = 64;
3179 margin_reg_value = 154;
3180 break;
3181 default:
3182 return 0;
3183 }
3184 break;
bd60018a 3185 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3186 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3187 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3188 deemph_reg_value = 43;
3189 margin_reg_value = 154;
3190 break;
3191 default:
3192 return 0;
3193 }
3194 break;
3195 default:
3196 return 0;
3197 }
3198
3199 mutex_lock(&dev_priv->dpio_lock);
3200
3201 /* Clear calc init */
1966e59e
VS		 3202 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3203 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3204 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3205 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3206 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3207
3208 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3209 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3210 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3211 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3212 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3213
a02ef3c7
VS		 3214 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3215 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3216 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3217 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3218
3219 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3220 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3221 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3222 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3223
e4a1d846 3224 /* Program swing deemph */
f72df8db
VS		 3225 for (i = 0; i < 4; i++) {
3226 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3227 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3228 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3229 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3230 }
e4a1d846
CML		 3231
3232 /* Program swing margin */
f72df8db
VS		 3233 for (i = 0; i < 4; i++) {
3234 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3235 val &= ~DPIO_SWING_MARGIN000_MASK;
3236 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3237 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3238 }
e4a1d846
CML		 3239
3240 /* Disable unique transition scale */
f72df8db
VS		 3241 for (i = 0; i < 4; i++) {
3242 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3243 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3244 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3245 }
e4a1d846
CML		 3246
3247 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3248 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3249 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3250 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3251
3252 /*
3253 * The document said it needs to set bit 27 for ch0 and bit 26
3254 * for ch1. Might be a typo in the doc.
3255 * For now, for this unique transition scale selection, set bit
3256 * 27 for ch0 and ch1.
3257 */
f72df8db
VS		 3258 for (i = 0; i < 4; i++) {
3259 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3260 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3261 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3262 }
e4a1d846 3263
f72df8db
VS		 3264 for (i = 0; i < 4; i++) {
3265 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3266 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3267 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3268 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3269 }
e4a1d846
CML		 3270 }
3271
3272 /* Start swing calculation */
1966e59e
VS		 3273 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3274 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3275 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3276
3277 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3278 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3279 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3280
3281 /* LRC Bypass */
3282 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3283 val |= DPIO_LRC_BYPASS;
3284 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3285
3286 mutex_unlock(&dev_priv->dpio_lock);
3287
3288 return 0;
3289}
3290
a4fc5ed6 3291static void
0301b3ac
JN		 3292intel_get_adjust_train(struct intel_dp *intel_dp,
3293 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3294{
3295 uint8_t v = 0;
3296 uint8_t p = 0;
3297 int lane;
1a2eb460
KP		 3298 uint8_t voltage_max;
3299 uint8_t preemph_max;
a4fc5ed6 3300
33a34e4e 3301 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3302 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3303 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3304
3305 if (this_v > v)
3306 v = this_v;
3307 if (this_p > p)
3308 p = this_p;
3309 }
3310
1a2eb460 3311 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3312 if (v >= voltage_max)
3313 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3314
1a2eb460
KP		 3315 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3316 if (p >= preemph_max)
3317 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3318
3319 for (lane = 0; lane < 4; lane++)
33a34e4e 3320 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3321}
3322
3323static uint32_t
5829975c 3324gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3325{
3cf2efb1 3326 uint32_t signal_levels = 0;
a4fc5ed6 3327
3cf2efb1 3328 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3330 default:
3331 signal_levels |= DP_VOLTAGE_0_4;
3332 break;
bd60018a 3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3334 signal_levels |= DP_VOLTAGE_0_6;
3335 break;
bd60018a 3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3337 signal_levels |= DP_VOLTAGE_0_8;
3338 break;
bd60018a 3339 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3340 signal_levels |= DP_VOLTAGE_1_2;
3341 break;
3342 }
3cf2efb1 3343 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3344 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3345 default:
3346 signal_levels |= DP_PRE_EMPHASIS_0;
3347 break;
bd60018a 3348 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3349 signal_levels |= DP_PRE_EMPHASIS_3_5;
3350 break;
bd60018a 3351 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3352 signal_levels |= DP_PRE_EMPHASIS_6;
3353 break;
bd60018a 3354 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3355 signal_levels |= DP_PRE_EMPHASIS_9_5;
3356 break;
3357 }
3358 return signal_levels;
3359}
3360
e3421a18
ZW		 3361/* Gen6's DP voltage swing and pre-emphasis control */
3362static uint32_t
5829975c 3363gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3364{
3c5a62b5
YL		 3365 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3366 DP_TRAIN_PRE_EMPHASIS_MASK);
3367 switch (signal_levels) {
bd60018a
SJ		 3368 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3369 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3370 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3371 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3372 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3373 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3375 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3376 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3377 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3378 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3379 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3380 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3381 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3382 default:
3c5a62b5
YL		 3383 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3384 "0x%x\n", signal_levels);
3385 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3386 }
3387}
3388
1a2eb460
KP		 3389/* Gen7's DP voltage swing and pre-emphasis control */
3390static uint32_t
5829975c 3391gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3392{
3393 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3394 DP_TRAIN_PRE_EMPHASIS_MASK);
3395 switch (signal_levels) {
bd60018a 3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3397 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3398 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3399 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3400 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3401 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3402
bd60018a 3403 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3404 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3405 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3406 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3407
bd60018a 3408 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3409 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3410 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3411 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3412
3413 default:
3414 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3415 "0x%x\n", signal_levels);
3416 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3417 }
3418}
3419
d6c0d722
PZ		 3420/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3421static uint32_t
5829975c 3422hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3423{
d6c0d722
PZ		 3424 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3425 DP_TRAIN_PRE_EMPHASIS_MASK);
3426 switch (signal_levels) {
bd60018a 3427 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3428 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3429 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3430 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3431 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3432 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3433 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3434 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3435
bd60018a 3436 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3437 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3438 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3439 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3440 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3441 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3442
bd60018a 3443 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3444 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3445 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3446 return DDI_BUF_TRANS_SELECT(8);
7ad14a29
SJ		 3447
3448 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3449 return DDI_BUF_TRANS_SELECT(9);
d6c0d722
PZ		 3450 default:
3451 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3452 "0x%x\n", signal_levels);
c5fe6a06 3453 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3454 }
a4fc5ed6
KP		 3455}
3456
5829975c 3457static void bxt_signal_levels(struct intel_dp *intel_dp)
96fb9f9b
VK		 3458{
3459 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3460 enum port port = dport->port;
3461 struct drm_device *dev = dport->base.base.dev;
3462 struct intel_encoder *encoder = &dport->base;
3463 uint8_t train_set = intel_dp->train_set[0];
3464 uint32_t level = 0;
3465
3466 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3467 DP_TRAIN_PRE_EMPHASIS_MASK);
3468 switch (signal_levels) {
3469 default:
3470 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emph level\n");
3471 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3472 level = 0;
3473 break;
3474 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3475 level = 1;
3476 break;
3477 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3478 level = 2;
3479 break;
3480 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3481 level = 3;
3482 break;
3483 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3484 level = 4;
3485 break;
3486 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3487 level = 5;
3488 break;
3489 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3490 level = 6;
3491 break;
3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3493 level = 7;
3494 break;
3495 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3496 level = 8;
3497 break;
3498 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3499 level = 9;
3500 break;
3501 }
3502
3503 bxt_ddi_vswing_sequence(dev, level, port, encoder->type);
3504}
3505
f0a3424e
PZ		 3506/* Properly updates "DP" with the correct signal levels. */
3507static void
3508intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3509{
3510 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3511 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3512 struct drm_device *dev = intel_dig_port->base.base.dev;
3513 uint32_t signal_levels, mask;
3514 uint8_t train_set = intel_dp->train_set[0];
3515
96fb9f9b
VK		 3516 if (IS_BROXTON(dev)) {
3517 signal_levels = 0;
5829975c 3518 bxt_signal_levels(intel_dp);
96fb9f9b
VK		 3519 mask = 0;
3520 } else if (HAS_DDI(dev)) {
5829975c 3521 signal_levels = hsw_signal_levels(train_set);
f0a3424e 3522 mask = DDI_BUF_EMP_MASK;
e4a1d846 3523 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3524 signal_levels = chv_signal_levels(intel_dp);
e4a1d846 3525 mask = 0;
e2fa6fba 3526 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3527 signal_levels = vlv_signal_levels(intel_dp);
e2fa6fba 3528 mask = 0;
bc7d38a4 3529 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3530 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3531 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3532 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3533 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3534 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3535 } else {
5829975c 3536 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3537 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3538 }
3539
96fb9f9b
VK		 3540 if (mask)
3541 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3542
3543 DRM_DEBUG_KMS("Using vswing level %d\n",
3544 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3545 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3546 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3547 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e
PZ		 3548
3549 *DP = (*DP & ~mask) | signal_levels;
3550}
3551
a4fc5ed6 3552static bool
ea5b213a 3553intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3554 uint32_t *DP,
58e10eb9 3555 uint8_t dp_train_pat)
a4fc5ed6 3556{
174edf1f
PZ		 3557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3558 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3559 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3560 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3561 int ret, len;
a4fc5ed6 3562
7b13b58a 3563 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3564
70aff66c 3565 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3566 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3567
2cdfe6c8
JN		 3568 buf[0] = dp_train_pat;
3569 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3570 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3571 /* don't write DP_TRAINING_LANEx_SET on disable */
3572 len = 1;
3573 } else {
3574 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3575 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3576 len = intel_dp->lane_count + 1;
47ea7542 3577 }
a4fc5ed6 3578
9d1a1031
JN		 3579 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3580 buf, len);
2cdfe6c8
JN		 3581
3582 return ret == len;
a4fc5ed6
KP		 3583}
3584
70aff66c
JN		 3585static bool
3586intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3587 uint8_t dp_train_pat)
3588{
4e96c977
MK		 3589 if (!intel_dp->train_set_valid)
3590 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3591 intel_dp_set_signal_levels(intel_dp, DP);
3592 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3593}
3594
3595static bool
3596intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3597 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3598{
3599 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3600 struct drm_device *dev = intel_dig_port->base.base.dev;
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 int ret;
3603
3604 intel_get_adjust_train(intel_dp, link_status);
3605 intel_dp_set_signal_levels(intel_dp, DP);
3606
3607 I915_WRITE(intel_dp->output_reg, *DP);
3608 POSTING_READ(intel_dp->output_reg);
3609
9d1a1031
JN		 3610 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3611 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3612
3613 return ret == intel_dp->lane_count;
3614}
3615
3ab9c637
ID		 3616static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3617{
3618 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3619 struct drm_device *dev = intel_dig_port->base.base.dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 enum port port = intel_dig_port->port;
3622 uint32_t val;
3623
3624 if (!HAS_DDI(dev))
3625 return;
3626
3627 val = I915_READ(DP_TP_CTL(port));
3628 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3629 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3630 I915_WRITE(DP_TP_CTL(port), val);
3631
3632 /*
3633 * On PORT_A we can have only eDP in SST mode. There the only reason
3634 * we need to set idle transmission mode is to work around a HW issue
3635 * where we enable the pipe while not in idle link-training mode.
3636 * In this case there is requirement to wait for a minimum number of
3637 * idle patterns to be sent.
3638 */
3639 if (port == PORT_A)
3640 return;
3641
3642 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3643 1))
3644 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3645}
3646
33a34e4e 3647/* Enable corresponding port and start training pattern 1 */
c19b0669 3648void
33a34e4e 3649intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3650{
da63a9f2 3651 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3652 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3653 int i;
3654 uint8_t voltage;
cdb0e95b 3655 int voltage_tries, loop_tries;
ea5b213a 3656 uint32_t DP = intel_dp->DP;
6aba5b6c 3657 uint8_t link_config[2];
a4fc5ed6 3658
affa9354 3659 if (HAS_DDI(dev))
c19b0669
PZ		 3660 intel_ddi_prepare_link_retrain(encoder);
3661
3cf2efb1 3662 /* Write the link configuration data */
6aba5b6c
JN		 3663 link_config[0] = intel_dp->link_bw;
3664 link_config[1] = intel_dp->lane_count;
3665 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3666 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3667 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
94ca719e 3668 if (intel_dp->num_sink_rates)
a8f3ef61
SJ		 3669 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
3670 &intel_dp->rate_select, 1);
6aba5b6c
JN		 3671
3672 link_config[0] = 0;
3673 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3674 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3675
3676 DP |= DP_PORT_EN;
1a2eb460 3677
70aff66c
JN		 3678 /* clock recovery */
3679 if (!intel_dp_reset_link_train(intel_dp, &DP,
3680 DP_TRAINING_PATTERN_1 |
3681 DP_LINK_SCRAMBLING_DISABLE)) {
3682 DRM_ERROR("failed to enable link training\n");
3683 return;
3684 }
3685
a4fc5ed6 3686 voltage = 0xff;
cdb0e95b
KP		 3687 voltage_tries = 0;
3688 loop_tries = 0;
a4fc5ed6 3689 for (;;) {
70aff66c 3690 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3691
a7c9655f 3692 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3693 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3694 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3695 break;
93f62dad 3696 }
a4fc5ed6 3697
01916270 3698 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3699 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3700 break;
3701 }
3702
4e96c977
MK		 3703 /*
3704 * if we used previously trained voltage and pre-emphasis values
3705 * and we don't get clock recovery, reset link training values
3706 */
3707 if (intel_dp->train_set_valid) {
3708 DRM_DEBUG_KMS("clock recovery not ok, reset");
3709 /* clear the flag as we are not reusing train set */
3710 intel_dp->train_set_valid = false;
3711 if (!intel_dp_reset_link_train(intel_dp, &DP,
3712 DP_TRAINING_PATTERN_1 |
3713 DP_LINK_SCRAMBLING_DISABLE)) {
3714 DRM_ERROR("failed to enable link training\n");
3715 return;
3716 }
3717 continue;
3718 }
3719
3cf2efb1
CW		 3720 /* Check to see if we've tried the max voltage */
3721 for (i = 0; i < intel_dp->lane_count; i++)
3722 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3723 break;
3b4f819d 3724 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3725 ++loop_tries;
3726 if (loop_tries == 5) {
3def84b3 3727 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3728 break;
3729 }
70aff66c
JN		 3730 intel_dp_reset_link_train(intel_dp, &DP,
3731 DP_TRAINING_PATTERN_1 |
3732 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3733 voltage_tries = 0;
3734 continue;
3735 }
a4fc5ed6 3736
3cf2efb1 3737 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3738 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3739 ++voltage_tries;
b06fbda3 3740 if (voltage_tries == 5) {
3def84b3 3741 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3742 break;
3743 }
3744 } else
3745 voltage_tries = 0;
3746 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3747
70aff66c
JN		 3748 /* Update training set as requested by target */
3749 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3750 DRM_ERROR("failed to update link training\n");
3751 break;
3752 }
a4fc5ed6
KP		 3753 }
3754
33a34e4e
JB		 3755 intel_dp->DP = DP;
3756}
3757
c19b0669 3758void
33a34e4e
JB		 3759intel_dp_complete_link_train(struct intel_dp *intel_dp)
3760{
33a34e4e 3761 bool channel_eq = false;
37f80975 3762 int tries, cr_tries;
33a34e4e 3763 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3764 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3765
3766 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3767 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3768 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3769
a4fc5ed6 3770 /* channel equalization */
70aff66c 3771 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3772 training_pattern |
70aff66c
JN		 3773 DP_LINK_SCRAMBLING_DISABLE)) {
3774 DRM_ERROR("failed to start channel equalization\n");
3775 return;
3776 }
3777
a4fc5ed6 3778 tries = 0;
37f80975 3779 cr_tries = 0;
a4fc5ed6
KP		 3780 channel_eq = false;
3781 for (;;) {
70aff66c 3782 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3783
37f80975
JB		 3784 if (cr_tries > 5) {
3785 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3786 break;
3787 }
3788
a7c9655f 3789 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3790 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3791 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3792 break;
70aff66c 3793 }
a4fc5ed6 3794
37f80975 3795 /* Make sure clock is still ok */
01916270 3796 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
4e96c977 3797 intel_dp->train_set_valid = false;
37f80975 3798 intel_dp_start_link_train(intel_dp);
70aff66c 3799 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3800 training_pattern |
70aff66c 3801 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3802 cr_tries++;
3803 continue;
3804 }
3805
1ffdff13 3806 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3807 channel_eq = true;
3808 break;
3809 }
a4fc5ed6 3810
37f80975
JB		 3811 /* Try 5 times, then try clock recovery if that fails */
3812 if (tries > 5) {
4e96c977 3813 intel_dp->train_set_valid = false;
37f80975 3814 intel_dp_start_link_train(intel_dp);
70aff66c 3815 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3816 training_pattern |
70aff66c 3817 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3818 tries = 0;
3819 cr_tries++;
3820 continue;
3821 }
a4fc5ed6 3822
70aff66c
JN		 3823 /* Update training set as requested by target */
3824 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3825 DRM_ERROR("failed to update link training\n");
3826 break;
3827 }
3cf2efb1 3828 ++tries;
869184a6 3829 }
3cf2efb1 3830
3ab9c637
ID		 3831 intel_dp_set_idle_link_train(intel_dp);
3832
3833 intel_dp->DP = DP;
3834
4e96c977 3835 if (channel_eq) {
5fa836a9 3836 intel_dp->train_set_valid = true;
07f42258 3837 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
4e96c977 3838 }
3ab9c637
ID		 3839}
3840
3841void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3842{
70aff66c 3843 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3844 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3845}
3846
3847static void
ea5b213a 3848intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3849{
da63a9f2 3850 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3851 enum port port = intel_dig_port->port;
da63a9f2 3852 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3853 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3854 uint32_t DP = intel_dp->DP;
a4fc5ed6 3855
bc76e320 3856 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3857 return;
3858
0c33d8d7 3859 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3860 return;
3861
28c97730 3862 DRM_DEBUG_KMS("\n");
32f9d658 3863
bc7d38a4 3864 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3865 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3866 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3867 } else {
aad3d14d
VS		 3868 if (IS_CHERRYVIEW(dev))
3869 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3870 else
3871 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3872 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3873 }
fe255d00 3874 POSTING_READ(intel_dp->output_reg);
5eb08b69 3875
493a7081 3876 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3877 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
5bddd17f
EA		 3878 /* Hardware workaround: leaving our transcoder select
3879 * set to transcoder B while it's off will prevent the
3880 * corresponding HDMI output on transcoder A.
3881 *
3882 * Combine this with another hardware workaround:
3883 * transcoder select bit can only be cleared while the
3884 * port is enabled.
3885 */
3886 DP &= ~DP_PIPEB_SELECT;
3887 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3888 POSTING_READ(intel_dp->output_reg);
5bddd17f
EA		 3889 }
3890
832afda6 3891 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3892 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3893 POSTING_READ(intel_dp->output_reg);
f01eca2e 3894 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3895}
3896
26d61aad
KP		 3897static bool
3898intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3899{
a031d709
RV		 3900 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3901 struct drm_device *dev = dig_port->base.base.dev;
3902 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3903 uint8_t rev;
a031d709 3904
9d1a1031
JN		 3905 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3906 sizeof(intel_dp->dpcd)) < 0)
edb39244 3907 return false; /* aux transfer failed */
92fd8fd1 3908
a8e98153 3909 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3910
edb39244
AJ		 3911 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3912 return false; /* DPCD not present */
3913
2293bb5c
SK		 3914 /* Check if the panel supports PSR */
3915 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3916 if (is_edp(intel_dp)) {
9d1a1031
JN		 3917 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3918 intel_dp->psr_dpcd,
3919 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3920 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3921 dev_priv->psr.sink_support = true;
50003939 3922 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3923 }
474d1ec4
SJ		 3924
3925 if (INTEL_INFO(dev)->gen >= 9 &&
3926 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3927 uint8_t frame_sync_cap;
3928
3929 dev_priv->psr.sink_support = true;
3930 intel_dp_dpcd_read_wake(&intel_dp->aux,
3931 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3932 &frame_sync_cap, 1);
3933 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3934 /* PSR2 needs frame sync as well */
3935 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3936 DRM_DEBUG_KMS("PSR2 %s on sink",
3937 dev_priv->psr.psr2_support ? "supported" : "not supported");
3938 }
50003939
JN		 3939 }
3940
7809a611 3941 /* Training Pattern 3 support, both source and sink */
06ea66b6 3942 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
7809a611
JN		 3943 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED &&
3944 (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)) {
06ea66b6 3945 intel_dp->use_tps3 = true;
f8d8a672 3946 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3947 } else
3948 intel_dp->use_tps3 = false;
3949
fc0f8e25
SJ		 3950 /* Intermediate frequency support */
3951 if (is_edp(intel_dp) &&
3952 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3953 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3954 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3955 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3956 int i;
3957
fc0f8e25
SJ		 3958 intel_dp_dpcd_read_wake(&intel_dp->aux,
3959 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3960 sink_rates,
3961 sizeof(sink_rates));
ea2d8a42 3962
94ca719e
VS		 3963 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3964 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3965
3966 if (val == 0)
3967 break;
3968
af77b974
SJ		 3969 /* Value read is in kHz while drm clock is saved in deca-kHz */
3970 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3971 }
94ca719e 3972 intel_dp->num_sink_rates = i;
fc0f8e25 3973 }
0336400e
VS		 3974
3975 intel_dp_print_rates(intel_dp);
3976
edb39244
AJ		 3977 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3978 DP_DWN_STRM_PORT_PRESENT))
3979 return true; /* native DP sink */
3980
3981 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3982 return true; /* no per-port downstream info */
3983
9d1a1031
JN		 3984 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3985 intel_dp->downstream_ports,
3986 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3987 return false; /* downstream port status fetch failed */
3988
3989 return true;
92fd8fd1
KP		 3990}
3991
0d198328
AJ		 3992static void
3993intel_dp_probe_oui(struct intel_dp *intel_dp)
3994{
3995 u8 buf[3];
3996
3997 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3998 return;
3999
9d1a1031 4000 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 4001 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
4002 buf[0], buf[1], buf[2]);
4003
9d1a1031 4004 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 4005 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
4006 buf[0], buf[1], buf[2]);
4007}
4008
0e32b39c
DA		 4009static bool
4010intel_dp_probe_mst(struct intel_dp *intel_dp)
4011{
4012 u8 buf[1];
4013
4014 if (!intel_dp->can_mst)
4015 return false;
4016
4017 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
4018 return false;
4019
0e32b39c
DA		 4020 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
4021 if (buf[0] & DP_MST_CAP) {
4022 DRM_DEBUG_KMS("Sink is MST capable\n");
4023 intel_dp->is_mst = true;
4024 } else {
4025 DRM_DEBUG_KMS("Sink is not MST capable\n");
4026 intel_dp->is_mst = false;
4027 }
4028 }
0e32b39c
DA		 4029
4030 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4031 return intel_dp->is_mst;
4032}
4033
d2e216d0
RV		 4034int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4035{
4036 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4037 struct drm_device *dev = intel_dig_port->base.base.dev;
4038 struct intel_crtc *intel_crtc =
4039 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 4040 u8 buf;
4041 int test_crc_count;
4042 int attempts = 6;
d2e216d0 4043
ad9dc91b 4044 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 4045 return -EIO;
d2e216d0 4046
ad9dc91b 4047 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 4048 return -ENOTTY;
4049
1dda5f93
RV		 4050 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4051 return -EIO;
4052
9d1a1031 4053 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 4054 buf | DP_TEST_SINK_START) < 0)
bda0381e 4055 return -EIO;
d2e216d0 4056
1dda5f93 4057 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 4058 return -EIO;
ad9dc91b 4059 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 4060
ad9dc91b 4061 do {
1dda5f93
RV		 4062 if (drm_dp_dpcd_readb(&intel_dp->aux,
4063 DP_TEST_SINK_MISC, &buf) < 0)
4064 return -EIO;
ad9dc91b
RV		 4065 intel_wait_for_vblank(dev, intel_crtc->pipe);
4066 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
4067
4068 if (attempts == 0) {
90bd1f46
DV		 4069 DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
4070 return -ETIMEDOUT;
ad9dc91b 4071 }
d2e216d0 4072
9d1a1031 4073 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 4074 return -EIO;
d2e216d0 4075
1dda5f93
RV		 4076 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4077 return -EIO;
4078 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4079 buf & ~DP_TEST_SINK_START) < 0)
4080 return -EIO;
ce31d9f4 4081
d2e216d0
RV		 4082 return 0;
4083}
4084
a60f0e38
JB		 4085static bool
4086intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4087{
9d1a1031
JN		 4088 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4089 DP_DEVICE_SERVICE_IRQ_VECTOR,
4090 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4091}
4092
0e32b39c
DA		 4093static bool
4094intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4095{
4096 int ret;
4097
4098 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4099 DP_SINK_COUNT_ESI,
4100 sink_irq_vector, 14);
4101 if (ret != 14)
4102 return false;
4103
4104 return true;
4105}
4106
c5d5ab7a
TP		 4107static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4108{
4109 uint8_t test_result = DP_TEST_ACK;
4110 return test_result;
4111}
4112
4113static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4114{
4115 uint8_t test_result = DP_TEST_NAK;
4116 return test_result;
4117}
4118
4119static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4120{
c5d5ab7a 4121 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4122 struct intel_connector *intel_connector = intel_dp->attached_connector;
4123 struct drm_connector *connector = &intel_connector->base;
4124
4125 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4126 connector->edid_corrupt ||
559be30c
TP		 4127 intel_dp->aux.i2c_defer_count > 6) {
4128 /* Check EDID read for NACKs, DEFERs and corruption
4129 * (DP CTS 1.2 Core r1.1)
4130 * 4.2.2.4 : Failed EDID read, I2C_NAK
4131 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4132 * 4.2.2.6 : EDID corruption detected
4133 * Use failsafe mode for all cases
4134 */
4135 if (intel_dp->aux.i2c_nack_count > 0 ||
4136 intel_dp->aux.i2c_defer_count > 0)
4137 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4138 intel_dp->aux.i2c_nack_count,
4139 intel_dp->aux.i2c_defer_count);
4140 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4141 } else {
4142 if (!drm_dp_dpcd_write(&intel_dp->aux,
4143 DP_TEST_EDID_CHECKSUM,
4144 &intel_connector->detect_edid->checksum,
4145 1));
4146 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4147
4148 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4149 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4150 }
4151
4152 /* Set test active flag here so userspace doesn't interrupt things */
4153 intel_dp->compliance_test_active = 1;
4154
c5d5ab7a
TP		 4155 return test_result;
4156}
4157
4158static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4159{
c5d5ab7a
TP		 4160 uint8_t test_result = DP_TEST_NAK;
4161 return test_result;
4162}
4163
4164static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4165{
4166 uint8_t response = DP_TEST_NAK;
4167 uint8_t rxdata = 0;
4168 int status = 0;
4169
559be30c 4170 intel_dp->compliance_test_active = 0;
c5d5ab7a 4171 intel_dp->compliance_test_type = 0;
559be30c
TP		 4172 intel_dp->compliance_test_data = 0;
4173
c5d5ab7a
TP		 4174 intel_dp->aux.i2c_nack_count = 0;
4175 intel_dp->aux.i2c_defer_count = 0;
4176
4177 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4178 if (status <= 0) {
4179 DRM_DEBUG_KMS("Could not read test request from sink\n");
4180 goto update_status;
4181 }
4182
4183 switch (rxdata) {
4184 case DP_TEST_LINK_TRAINING:
4185 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4186 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4187 response = intel_dp_autotest_link_training(intel_dp);
4188 break;
4189 case DP_TEST_LINK_VIDEO_PATTERN:
4190 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4191 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4192 response = intel_dp_autotest_video_pattern(intel_dp);
4193 break;
4194 case DP_TEST_LINK_EDID_READ:
4195 DRM_DEBUG_KMS("EDID test requested\n");
4196 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4197 response = intel_dp_autotest_edid(intel_dp);
4198 break;
4199 case DP_TEST_LINK_PHY_TEST_PATTERN:
4200 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4201 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4202 response = intel_dp_autotest_phy_pattern(intel_dp);
4203 break;
4204 default:
4205 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4206 break;
4207 }
4208
4209update_status:
4210 status = drm_dp_dpcd_write(&intel_dp->aux,
4211 DP_TEST_RESPONSE,
4212 &response, 1);
4213 if (status <= 0)
4214 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4215}
4216
0e32b39c
DA		 4217static int
4218intel_dp_check_mst_status(struct intel_dp *intel_dp)
4219{
4220 bool bret;
4221
4222 if (intel_dp->is_mst) {
4223 u8 esi[16] = { 0 };
4224 int ret = 0;
4225 int retry;
4226 bool handled;
4227 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4228go_again:
4229 if (bret == true) {
4230
4231 /* check link status - esi[10] = 0x200c */
4232 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4233 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4234 intel_dp_start_link_train(intel_dp);
4235 intel_dp_complete_link_train(intel_dp);
4236 intel_dp_stop_link_train(intel_dp);
4237 }
4238
6f34cc39 4239 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4240 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4241
4242 if (handled) {
4243 for (retry = 0; retry < 3; retry++) {
4244 int wret;
4245 wret = drm_dp_dpcd_write(&intel_dp->aux,
4246 DP_SINK_COUNT_ESI+1,
4247 &esi[1], 3);
4248 if (wret == 3) {
4249 break;
4250 }
4251 }
4252
4253 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4254 if (bret == true) {
6f34cc39 4255 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4256 goto go_again;
4257 }
4258 } else
4259 ret = 0;
4260
4261 return ret;
4262 } else {
4263 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4264 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4265 intel_dp->is_mst = false;
4266 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4267 /* send a hotplug event */
4268 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4269 }
4270 }
4271 return -EINVAL;
4272}
4273
a4fc5ed6
KP		 4274/*
4275 * According to DP spec
4276 * 5.1.2:
4277 * 1. Read DPCD
4278 * 2. Configure link according to Receiver Capabilities
4279 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4280 * 4. Check link status on receipt of hot-plug interrupt
4281 */
a5146200 4282static void
ea5b213a 4283intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4284{
5b215bcf 4285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4286 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4287 u8 sink_irq_vector;
93f62dad 4288 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4289
5b215bcf
DA		 4290 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4291
da63a9f2 4292 if (!intel_encoder->connectors_active)
d2b996ac 4293 return;
59cd09e1 4294
da63a9f2 4295 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4296 return;
4297
1a125d8a
ID		 4298 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4299 return;
4300
92fd8fd1 4301 /* Try to read receiver status if the link appears to be up */
93f62dad 4302 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4303 return;
4304 }
4305
92fd8fd1 4306 /* Now read the DPCD to see if it's actually running */
26d61aad 4307 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4308 return;
4309 }
4310
a60f0e38
JB		 4311 /* Try to read the source of the interrupt */
4312 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4313 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4314 /* Clear interrupt source */
9d1a1031
JN		 4315 drm_dp_dpcd_writeb(&intel_dp->aux,
4316 DP_DEVICE_SERVICE_IRQ_VECTOR,
4317 sink_irq_vector);
a60f0e38
JB		 4318
4319 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4320 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4321 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4322 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4323 }
4324
1ffdff13 4325 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4326 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4327 intel_encoder->base.name);
33a34e4e
JB		 4328 intel_dp_start_link_train(intel_dp);
4329 intel_dp_complete_link_train(intel_dp);
3ab9c637 4330 intel_dp_stop_link_train(intel_dp);
33a34e4e 4331 }
a4fc5ed6 4332}
a4fc5ed6 4333
caf9ab24 4334/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4335static enum drm_connector_status
26d61aad 4336intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4337{
caf9ab24 4338 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4339 uint8_t type;
4340
4341 if (!intel_dp_get_dpcd(intel_dp))
4342 return connector_status_disconnected;
4343
4344 /* if there's no downstream port, we're done */
4345 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4346 return connector_status_connected;
caf9ab24
AJ		 4347
4348 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4349 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4350 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4351 uint8_t reg;
9d1a1031
JN		 4352
4353 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4354 &reg, 1) < 0)
caf9ab24 4355 return connector_status_unknown;
9d1a1031 4356
23235177
AJ		 4357 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4358 : connector_status_disconnected;
caf9ab24
AJ		 4359 }
4360
4361 /* If no HPD, poke DDC gently */
0b99836f 4362 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4363 return connector_status_connected;
caf9ab24
AJ		 4364
4365 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4366 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4367 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4368 if (type == DP_DS_PORT_TYPE_VGA ||
4369 type == DP_DS_PORT_TYPE_NON_EDID)
4370 return connector_status_unknown;
4371 } else {
4372 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4373 DP_DWN_STRM_PORT_TYPE_MASK;
4374 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4375 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4376 return connector_status_unknown;
4377 }
caf9ab24
AJ		 4378
4379 /* Anything else is out of spec, warn and ignore */
4380 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4381 return connector_status_disconnected;
71ba9000
AJ		 4382}
4383
d410b56d
CW		 4384static enum drm_connector_status
4385edp_detect(struct intel_dp *intel_dp)
4386{
4387 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4388 enum drm_connector_status status;
4389
4390 status = intel_panel_detect(dev);
4391 if (status == connector_status_unknown)
4392 status = connector_status_connected;
4393
4394 return status;
4395}
4396
5eb08b69 4397static enum drm_connector_status
a9756bb5 4398ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4399{
30add22d 4400 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4401 struct drm_i915_private *dev_priv = dev->dev_private;
4402 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4403
1b469639
DL		 4404 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4405 return connector_status_disconnected;
4406
26d61aad 4407 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4408}
4409
2a592bec
DA		 4410static int g4x_digital_port_connected(struct drm_device *dev,
4411 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4412{
a4fc5ed6 4413 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4414 uint32_t bit;
5eb08b69 4415
232a6ee9
TP		 4416 if (IS_VALLEYVIEW(dev)) {
4417 switch (intel_dig_port->port) {
4418 case PORT_B:
4419 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4420 break;
4421 case PORT_C:
4422 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4423 break;
4424 case PORT_D:
4425 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4426 break;
4427 default:
2a592bec 4428 return -EINVAL;
232a6ee9
TP		 4429 }
4430 } else {
4431 switch (intel_dig_port->port) {
4432 case PORT_B:
4433 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4434 break;
4435 case PORT_C:
4436 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4437 break;
4438 case PORT_D:
4439 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4440 break;
4441 default:
2a592bec 4442 return -EINVAL;
232a6ee9 4443 }
a4fc5ed6
KP		 4444 }
4445
10f76a38 4446 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4447 return 0;
4448 return 1;
4449}
4450
4451static enum drm_connector_status
4452g4x_dp_detect(struct intel_dp *intel_dp)
4453{
4454 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4455 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4456 int ret;
4457
4458 /* Can't disconnect eDP, but you can close the lid... */
4459 if (is_edp(intel_dp)) {
4460 enum drm_connector_status status;
4461
4462 status = intel_panel_detect(dev);
4463 if (status == connector_status_unknown)
4464 status = connector_status_connected;
4465 return status;
4466 }
4467
4468 ret = g4x_digital_port_connected(dev, intel_dig_port);
4469 if (ret == -EINVAL)
4470 return connector_status_unknown;
4471 else if (ret == 0)
a4fc5ed6
KP		 4472 return connector_status_disconnected;
4473
26d61aad 4474 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4475}
4476
8c241fef 4477static struct edid *
beb60608 4478intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4479{
beb60608 4480 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4481
9cd300e0
JN		 4482 /* use cached edid if we have one */
4483 if (intel_connector->edid) {
9cd300e0
JN		 4484 /* invalid edid */
4485 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4486 return NULL;
4487
55e9edeb 4488 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4489 } else
4490 return drm_get_edid(&intel_connector->base,
4491 &intel_dp->aux.ddc);
4492}
8c241fef 4493
beb60608
CW		 4494static void
4495intel_dp_set_edid(struct intel_dp *intel_dp)
4496{
4497 struct intel_connector *intel_connector = intel_dp->attached_connector;
4498 struct edid *edid;
8c241fef 4499
beb60608
CW		 4500 edid = intel_dp_get_edid(intel_dp);
4501 intel_connector->detect_edid = edid;
4502
4503 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4504 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4505 else
4506 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4507}
4508
beb60608
CW		 4509static void
4510intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4511{
beb60608 4512 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4513
beb60608
CW		 4514 kfree(intel_connector->detect_edid);
4515 intel_connector->detect_edid = NULL;
9cd300e0 4516
beb60608
CW		 4517 intel_dp->has_audio = false;
4518}
d6f24d0f 4519
beb60608
CW		 4520static enum intel_display_power_domain
4521intel_dp_power_get(struct intel_dp *dp)
4522{
4523 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4524 enum intel_display_power_domain power_domain;
4525
4526 power_domain = intel_display_port_power_domain(encoder);
4527 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4528
4529 return power_domain;
4530}
d6f24d0f 4531
beb60608
CW		 4532static void
4533intel_dp_power_put(struct intel_dp *dp,
4534 enum intel_display_power_domain power_domain)
4535{
4536 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4537 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4538}
4539
a9756bb5
ZW		 4540static enum drm_connector_status
4541intel_dp_detect(struct drm_connector *connector, bool force)
4542{
4543 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4544 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4545 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4546 struct drm_device *dev = connector->dev;
a9756bb5 4547 enum drm_connector_status status;
671dedd2 4548 enum intel_display_power_domain power_domain;
0e32b39c 4549 bool ret;
09b1eb13 4550 u8 sink_irq_vector;
a9756bb5 4551
164c8598 4552 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4553 connector->base.id, connector->name);
beb60608 4554 intel_dp_unset_edid(intel_dp);
164c8598 4555
0e32b39c
DA		 4556 if (intel_dp->is_mst) {
4557 /* MST devices are disconnected from a monitor POV */
4558 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4559 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4560 return connector_status_disconnected;
0e32b39c
DA		 4561 }
4562
beb60608 4563 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4564
d410b56d
CW		 4565 /* Can't disconnect eDP, but you can close the lid... */
4566 if (is_edp(intel_dp))
4567 status = edp_detect(intel_dp);
4568 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4569 status = ironlake_dp_detect(intel_dp);
4570 else
4571 status = g4x_dp_detect(intel_dp);
4572 if (status != connector_status_connected)
c8c8fb33 4573 goto out;
a9756bb5 4574
0d198328
AJ		 4575 intel_dp_probe_oui(intel_dp);
4576
0e32b39c
DA		 4577 ret = intel_dp_probe_mst(intel_dp);
4578 if (ret) {
4579 /* if we are in MST mode then this connector
4580 won't appear connected or have anything with EDID on it */
4581 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4582 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4583 status = connector_status_disconnected;
4584 goto out;
4585 }
4586
beb60608 4587 intel_dp_set_edid(intel_dp);
a9756bb5 4588
d63885da
PZ		 4589 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4590 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4591 status = connector_status_connected;
4592
09b1eb13
TP		 4593 /* Try to read the source of the interrupt */
4594 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4595 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4596 /* Clear interrupt source */
4597 drm_dp_dpcd_writeb(&intel_dp->aux,
4598 DP_DEVICE_SERVICE_IRQ_VECTOR,
4599 sink_irq_vector);
4600
4601 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4602 intel_dp_handle_test_request(intel_dp);
4603 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4604 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4605 }
4606
c8c8fb33 4607out:
beb60608 4608 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4609 return status;
a4fc5ed6
KP		 4610}
4611
beb60608
CW		 4612static void
4613intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4614{
df0e9248 4615 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4616 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4617 enum intel_display_power_domain power_domain;
a4fc5ed6 4618
beb60608
CW		 4619 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4620 connector->base.id, connector->name);
4621 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4622
beb60608
CW		 4623 if (connector->status != connector_status_connected)
4624 return;
671dedd2 4625
beb60608
CW		 4626 power_domain = intel_dp_power_get(intel_dp);
4627
4628 intel_dp_set_edid(intel_dp);
4629
4630 intel_dp_power_put(intel_dp, power_domain);
4631
4632 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4633 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4634}
4635
4636static int intel_dp_get_modes(struct drm_connector *connector)
4637{
4638 struct intel_connector *intel_connector = to_intel_connector(connector);
4639 struct edid *edid;
4640
4641 edid = intel_connector->detect_edid;
4642 if (edid) {
4643 int ret = intel_connector_update_modes(connector, edid);
4644 if (ret)
4645 return ret;
4646 }
32f9d658 4647
f8779fda 4648 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4649 if (is_edp(intel_attached_dp(connector)) &&
4650 intel_connector->panel.fixed_mode) {
f8779fda 4651 struct drm_display_mode *mode;
beb60608
CW		 4652
4653 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4654 intel_connector->panel.fixed_mode);
f8779fda 4655 if (mode) {
32f9d658
ZW		 4656 drm_mode_probed_add(connector, mode);
4657 return 1;
4658 }
4659 }
beb60608 4660
32f9d658 4661 return 0;
a4fc5ed6
KP		 4662}
4663
1aad7ac0
CW		 4664static bool
4665intel_dp_detect_audio(struct drm_connector *connector)
4666{
1aad7ac0 4667 bool has_audio = false;
beb60608 4668 struct edid *edid;
1aad7ac0 4669
beb60608
CW		 4670 edid = to_intel_connector(connector)->detect_edid;
4671 if (edid)
1aad7ac0 4672 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4673
1aad7ac0
CW		 4674 return has_audio;
4675}
4676
f684960e
CW		 4677static int
4678intel_dp_set_property(struct drm_connector *connector,
4679 struct drm_property *property,
4680 uint64_t val)
4681{
e953fd7b 4682 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4683 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4684 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4685 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4686 int ret;
4687
662595df 4688 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4689 if (ret)
4690 return ret;
4691
3f43c48d 4692 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4693 int i = val;
4694 bool has_audio;
4695
4696 if (i == intel_dp->force_audio)
f684960e
CW		 4697 return 0;
4698
1aad7ac0 4699 intel_dp->force_audio = i;
f684960e 4700
c3e5f67b 4701 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4702 has_audio = intel_dp_detect_audio(connector);
4703 else
c3e5f67b 4704 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4705
4706 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4707 return 0;
4708
1aad7ac0 4709 intel_dp->has_audio = has_audio;
f684960e
CW		 4710 goto done;
4711 }
4712
e953fd7b 4713 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4714 bool old_auto = intel_dp->color_range_auto;
4715 uint32_t old_range = intel_dp->color_range;
4716
55bc60db
VS		 4717 switch (val) {
4718 case INTEL_BROADCAST_RGB_AUTO:
4719 intel_dp->color_range_auto = true;
4720 break;
4721 case INTEL_BROADCAST_RGB_FULL:
4722 intel_dp->color_range_auto = false;
4723 intel_dp->color_range = 0;
4724 break;
4725 case INTEL_BROADCAST_RGB_LIMITED:
4726 intel_dp->color_range_auto = false;
4727 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4728 break;
4729 default:
4730 return -EINVAL;
4731 }
ae4edb80
DV		 4732
4733 if (old_auto == intel_dp->color_range_auto &&
4734 old_range == intel_dp->color_range)
4735 return 0;
4736
e953fd7b
CW		 4737 goto done;
4738 }
4739
53b41837
YN		 4740 if (is_edp(intel_dp) &&
4741 property == connector->dev->mode_config.scaling_mode_property) {
4742 if (val == DRM_MODE_SCALE_NONE) {
4743 DRM_DEBUG_KMS("no scaling not supported\n");
4744 return -EINVAL;
4745 }
4746
4747 if (intel_connector->panel.fitting_mode == val) {
4748 /* the eDP scaling property is not changed */
4749 return 0;
4750 }
4751 intel_connector->panel.fitting_mode = val;
4752
4753 goto done;
4754 }
4755
f684960e
CW		 4756 return -EINVAL;
4757
4758done:
c0c36b94
CW		 4759 if (intel_encoder->base.crtc)
4760 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4761
4762 return 0;
4763}
4764
a4fc5ed6 4765static void
73845adf 4766intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4767{
1d508706 4768 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4769
10e972d3 4770 kfree(intel_connector->detect_edid);
beb60608 4771
9cd300e0
JN		 4772 if (!IS_ERR_OR_NULL(intel_connector->edid))
4773 kfree(intel_connector->edid);
4774
acd8db10
PZ		 4775 /* Can't call is_edp() since the encoder may have been destroyed
4776 * already. */
4777 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4778 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4779
a4fc5ed6 4780 drm_connector_cleanup(connector);
55f78c43 4781 kfree(connector);
a4fc5ed6
KP		 4782}
4783
00c09d70 4784void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4785{
da63a9f2
PZ		 4786 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4787 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4788
4f71d0cb 4789 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4790 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4791 if (is_edp(intel_dp)) {
4792 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4793 /*
4794 * vdd might still be enabled do to the delayed vdd off.
4795 * Make sure vdd is actually turned off here.
4796 */
773538e8 4797 pps_lock(intel_dp);
4be73780 4798 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4799 pps_unlock(intel_dp);
4800
01527b31
CT		 4801 if (intel_dp->edp_notifier.notifier_call) {
4802 unregister_reboot_notifier(&intel_dp->edp_notifier);
4803 intel_dp->edp_notifier.notifier_call = NULL;
4804 }
bd943159 4805 }
c8bd0e49 4806 drm_encoder_cleanup(encoder);
da63a9f2 4807 kfree(intel_dig_port);
24d05927
DV		 4808}
4809
07f9cd0b
ID		 4810static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4811{
4812 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4813
4814 if (!is_edp(intel_dp))
4815 return;
4816
951468f3
VS		 4817 /*
4818 * vdd might still be enabled do to the delayed vdd off.
4819 * Make sure vdd is actually turned off here.
4820 */
afa4e53a 4821 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4822 pps_lock(intel_dp);
07f9cd0b 4823 edp_panel_vdd_off_sync(intel_dp);
773538e8 4824 pps_unlock(intel_dp);
07f9cd0b
ID		 4825}
4826
49e6bc51
VS		 4827static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4828{
4829 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4830 struct drm_device *dev = intel_dig_port->base.base.dev;
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832 enum intel_display_power_domain power_domain;
4833
4834 lockdep_assert_held(&dev_priv->pps_mutex);
4835
4836 if (!edp_have_panel_vdd(intel_dp))
4837 return;
4838
4839 /*
4840 * The VDD bit needs a power domain reference, so if the bit is
4841 * already enabled when we boot or resume, grab this reference and
4842 * schedule a vdd off, so we don't hold on to the reference
4843 * indefinitely.
4844 */
4845 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4846 power_domain = intel_display_port_power_domain(&intel_dig_port->base);
4847 intel_display_power_get(dev_priv, power_domain);
4848
4849 edp_panel_vdd_schedule_off(intel_dp);
4850}
4851
6d93c0c4
ID		 4852static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4853{
49e6bc51
VS		 4854 struct intel_dp *intel_dp;
4855
4856 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4857 return;
4858
4859 intel_dp = enc_to_intel_dp(encoder);
4860
4861 pps_lock(intel_dp);
4862
4863 /*
4864 * Read out the current power sequencer assignment,
4865 * in case the BIOS did something with it.
4866 */
4867 if (IS_VALLEYVIEW(encoder->dev))
4868 vlv_initial_power_sequencer_setup(intel_dp);
4869
4870 intel_edp_panel_vdd_sanitize(intel_dp);
4871
4872 pps_unlock(intel_dp);
6d93c0c4
ID		 4873}
4874
a4fc5ed6 4875static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4876 .dpms = intel_connector_dpms,
a4fc5ed6 4877 .detect = intel_dp_detect,
beb60608 4878 .force = intel_dp_force,
a4fc5ed6 4879 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4880 .set_property = intel_dp_set_property,
2545e4a6 4881 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4882 .destroy = intel_dp_connector_destroy,
c6f95f27 4883 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4884 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4885};
4886
4887static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4888 .get_modes = intel_dp_get_modes,
4889 .mode_valid = intel_dp_mode_valid,
df0e9248 4890 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4891};
4892
a4fc5ed6 4893static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4894 .reset = intel_dp_encoder_reset,
24d05927 4895 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4896};
4897
0e32b39c 4898void
21d40d37 4899intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4900{
0e32b39c 4901 return;
c8110e52 4902}
6207937d 4903
b2c5c181 4904enum irqreturn
13cf5504
DA		 4905intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4906{
4907 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4908 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4909 struct drm_device *dev = intel_dig_port->base.base.dev;
4910 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4911 enum intel_display_power_domain power_domain;
b2c5c181 4912 enum irqreturn ret = IRQ_NONE;
1c767b33 4913
0e32b39c
DA		 4914 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4915 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4916
7a7f84cc
VS		 4917 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4918 /*
4919 * vdd off can generate a long pulse on eDP which
4920 * would require vdd on to handle it, and thus we
4921 * would end up in an endless cycle of
4922 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4923 */
4924 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4925 port_name(intel_dig_port->port));
a8b3d52f 4926 return IRQ_HANDLED;
7a7f84cc
VS		 4927 }
4928
26fbb774
VS		 4929 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4930 port_name(intel_dig_port->port),
0e32b39c 4931 long_hpd ? "long" : "short");
13cf5504 4932
1c767b33
ID		 4933 power_domain = intel_display_port_power_domain(intel_encoder);
4934 intel_display_power_get(dev_priv, power_domain);
4935
0e32b39c 4936 if (long_hpd) {
5fa836a9
MK		 4937 /* indicate that we need to restart link training */
4938 intel_dp->train_set_valid = false;
2a592bec
DA		 4939
4940 if (HAS_PCH_SPLIT(dev)) {
4941 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4942 goto mst_fail;
4943 } else {
4944 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4945 goto mst_fail;
4946 }
0e32b39c
DA		 4947
4948 if (!intel_dp_get_dpcd(intel_dp)) {
4949 goto mst_fail;
4950 }
4951
4952 intel_dp_probe_oui(intel_dp);
4953
4954 if (!intel_dp_probe_mst(intel_dp))
4955 goto mst_fail;
4956
4957 } else {
4958 if (intel_dp->is_mst) {
1c767b33 4959 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4960 goto mst_fail;
4961 }
4962
4963 if (!intel_dp->is_mst) {
4964 /*
4965 * we'll check the link status via the normal hot plug path later -
4966 * but for short hpds we should check it now
4967 */
5b215bcf 4968 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4969 intel_dp_check_link_status(intel_dp);
5b215bcf 4970 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4971 }
4972 }
b2c5c181
DV		 4973
4974 ret = IRQ_HANDLED;
4975
1c767b33 4976 goto put_power;
0e32b39c
DA		 4977mst_fail:
4978 /* if we were in MST mode, and device is not there get out of MST mode */
4979 if (intel_dp->is_mst) {
4980 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4981 intel_dp->is_mst = false;
4982 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4983 }
1c767b33
ID		 4984put_power:
4985 intel_display_power_put(dev_priv, power_domain);
4986
4987 return ret;
13cf5504
DA		 4988}
4989
e3421a18
ZW		 4990/* Return which DP Port should be selected for Transcoder DP control */
4991int
0206e353 4992intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4993{
4994 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4995 struct intel_encoder *intel_encoder;
4996 struct intel_dp *intel_dp;
e3421a18 4997
fa90ecef
PZ		 4998 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4999 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 5000
fa90ecef
PZ		 5001 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
5002 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 5003 return intel_dp->output_reg;
e3421a18 5004 }
ea5b213a 5005
e3421a18
ZW		 5006 return -1;
5007}
5008
36e83a18 5009/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 5010bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 5011{
5012 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 5013 union child_device_config *p_child;
36e83a18 5014 int i;
5d8a7752
VS		 5015 static const short port_mapping[] = {
5016 [PORT_B] = PORT_IDPB,
5017 [PORT_C] = PORT_IDPC,
5018 [PORT_D] = PORT_IDPD,
5019 };
36e83a18 5020
3b32a35b
VS		 5021 if (port == PORT_A)
5022 return true;
5023
41aa3448 5024 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 5025 return false;
5026
41aa3448
RV		 5027 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5028 p_child = dev_priv->vbt.child_dev + i;
36e83a18 5029
5d8a7752 5030 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 5031 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5032 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 5033 return true;
5034 }
5035 return false;
5036}
5037
0e32b39c 5038void
f684960e
CW		 5039intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5040{
53b41837
YN		 5041 struct intel_connector *intel_connector = to_intel_connector(connector);
5042
3f43c48d 5043 intel_attach_force_audio_property(connector);
e953fd7b 5044 intel_attach_broadcast_rgb_property(connector);
55bc60db 5045 intel_dp->color_range_auto = true;
53b41837
YN		 5046
5047 if (is_edp(intel_dp)) {
5048 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 5049 drm_object_attach_property(
5050 &connector->base,
53b41837 5051 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 5052 DRM_MODE_SCALE_ASPECT);
5053 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5054 }
f684960e
CW		 5055}
5056
dada1a9f
ID		 5057static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5058{
5059 intel_dp->last_power_cycle = jiffies;
5060 intel_dp->last_power_on = jiffies;
5061 intel_dp->last_backlight_off = jiffies;
5062}
5063
67a54566
DV		 5064static void
5065intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5066 struct intel_dp *intel_dp)
67a54566
DV		 5067{
5068 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5069 struct edp_power_seq cur, vbt, spec,
5070 *final = &intel_dp->pps_delays;
67a54566 5071 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 5072 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 5073
e39b999a
VS		 5074 lockdep_assert_held(&dev_priv->pps_mutex);
5075
81ddbc69
VS		 5076 /* already initialized? */
5077 if (final->t11_t12 != 0)
5078 return;
5079
453c5420 5080 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5081 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5082 pp_on_reg = PCH_PP_ON_DELAYS;
5083 pp_off_reg = PCH_PP_OFF_DELAYS;
5084 pp_div_reg = PCH_PP_DIVISOR;
5085 } else {
bf13e81b
JN		 5086 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5087
5088 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5089 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5090 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5091 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5092 }
67a54566
DV		 5093
5094 /* Workaround: Need to write PP_CONTROL with the unlock key as
5095 * the very first thing. */
453c5420 5096 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 5097 I915_WRITE(pp_ctrl_reg, pp);
67a54566 5098
453c5420
JB		 5099 pp_on = I915_READ(pp_on_reg);
5100 pp_off = I915_READ(pp_off_reg);
5101 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 5102
5103 /* Pull timing values out of registers */
5104 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5105 PANEL_POWER_UP_DELAY_SHIFT;
5106
5107 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5108 PANEL_LIGHT_ON_DELAY_SHIFT;
5109
5110 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5111 PANEL_LIGHT_OFF_DELAY_SHIFT;
5112
5113 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5114 PANEL_POWER_DOWN_DELAY_SHIFT;
5115
5116 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5117 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5118
5119 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5120 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5121
41aa3448 5122 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 5123
5124 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5125 * our hw here, which are all in 100usec. */
5126 spec.t1_t3 = 210 * 10;
5127 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5128 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5129 spec.t10 = 500 * 10;
5130 /* This one is special and actually in units of 100ms, but zero
5131 * based in the hw (so we need to add 100 ms). But the sw vbt
5132 * table multiplies it with 1000 to make it in units of 100usec,
5133 * too. */
5134 spec.t11_t12 = (510 + 100) * 10;
5135
5136 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5137 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5138
5139 /* Use the max of the register settings and vbt. If both are
5140 * unset, fall back to the spec limits. */
36b5f425 5141#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5142 spec.field : \
5143 max(cur.field, vbt.field))
5144 assign_final(t1_t3);
5145 assign_final(t8);
5146 assign_final(t9);
5147 assign_final(t10);
5148 assign_final(t11_t12);
5149#undef assign_final
5150
36b5f425 5151#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5152 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5153 intel_dp->backlight_on_delay = get_delay(t8);
5154 intel_dp->backlight_off_delay = get_delay(t9);
5155 intel_dp->panel_power_down_delay = get_delay(t10);
5156 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5157#undef get_delay
5158
f30d26e4
JN		 5159 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5160 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5161 intel_dp->panel_power_cycle_delay);
5162
5163 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5164 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5165}
5166
5167static void
5168intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5169 struct intel_dp *intel_dp)
f30d26e4
JN		 5170{
5171 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 5172 u32 pp_on, pp_off, pp_div, port_sel = 0;
5173 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5174 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 5175 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5176 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5177
e39b999a 5178 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 5179
5180 if (HAS_PCH_SPLIT(dev)) {
5181 pp_on_reg = PCH_PP_ON_DELAYS;
5182 pp_off_reg = PCH_PP_OFF_DELAYS;
5183 pp_div_reg = PCH_PP_DIVISOR;
5184 } else {
bf13e81b
JN		 5185 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5186
5187 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5188 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5189 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5190 }
5191
b2f19d1a
PZ		 5192 /*
5193 * And finally store the new values in the power sequencer. The
5194 * backlight delays are set to 1 because we do manual waits on them. For
5195 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5196 * we'll end up waiting for the backlight off delay twice: once when we
5197 * do the manual sleep, and once when we disable the panel and wait for
5198 * the PP_STATUS bit to become zero.
5199 */
f30d26e4 5200 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5201 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5202 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5203 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5204 /* Compute the divisor for the pp clock, simply match the Bspec
5205 * formula. */
453c5420 5206 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 5207 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 5208 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5209
5210 /* Haswell doesn't have any port selection bits for the panel
5211 * power sequencer any more. */
bc7d38a4 5212 if (IS_VALLEYVIEW(dev)) {
ad933b56 5213 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5214 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5215 if (port == PORT_A)
a24c144c 5216 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5217 else
a24c144c 5218 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5219 }
5220
453c5420
JB		 5221 pp_on |= port_sel;
5222
5223 I915_WRITE(pp_on_reg, pp_on);
5224 I915_WRITE(pp_off_reg, pp_off);
5225 I915_WRITE(pp_div_reg, pp_div);
67a54566 5226
67a54566 5227 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5228 I915_READ(pp_on_reg),
5229 I915_READ(pp_off_reg),
5230 I915_READ(pp_div_reg));
f684960e
CW		 5231}
5232
b33a2815
VK		 5233/**
5234 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5235 * @dev: DRM device
5236 * @refresh_rate: RR to be programmed
5237 *
5238 * This function gets called when refresh rate (RR) has to be changed from
5239 * one frequency to another. Switches can be between high and low RR
5240 * supported by the panel or to any other RR based on media playback (in
5241 * this case, RR value needs to be passed from user space).
5242 *
5243 * The caller of this function needs to take a lock on dev_priv->drrs.
5244 */
96178eeb 5245static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5246{
5247 struct drm_i915_private *dev_priv = dev->dev_private;
5248 struct intel_encoder *encoder;
96178eeb
VK		 5249 struct intel_digital_port *dig_port = NULL;
5250 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5251 struct intel_crtc_state *config = NULL;
439d7ac0 5252 struct intel_crtc *intel_crtc = NULL;
439d7ac0 5253 u32 reg, val;
96178eeb 5254 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5255
5256 if (refresh_rate <= 0) {
5257 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5258 return;
5259 }
5260
96178eeb
VK		 5261 if (intel_dp == NULL) {
5262 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5263 return;
5264 }
5265
1fcc9d1c 5266 /*
e4d59f6b
RV		 5267 * FIXME: This needs proper synchronization with psr state for some
5268 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5269 */
439d7ac0 5270
96178eeb
VK		 5271 dig_port = dp_to_dig_port(intel_dp);
5272 encoder = &dig_port->base;
723f9aab 5273 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5274
5275 if (!intel_crtc) {
5276 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5277 return;
5278 }
5279
6e3c9717 5280 config = intel_crtc->config;
439d7ac0 5281
96178eeb 5282 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5283 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5284 return;
5285 }
5286
96178eeb
VK		 5287 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5288 refresh_rate)
439d7ac0
PB		 5289 index = DRRS_LOW_RR;
5290
96178eeb 5291 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5292 DRM_DEBUG_KMS(
5293 "DRRS requested for previously set RR...ignoring\n");
5294 return;
5295 }
5296
5297 if (!intel_crtc->active) {
5298 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5299 return;
5300 }
5301
44395bfe 5302 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5303 switch (index) {
5304 case DRRS_HIGH_RR:
5305 intel_dp_set_m_n(intel_crtc, M1_N1);
5306 break;
5307 case DRRS_LOW_RR:
5308 intel_dp_set_m_n(intel_crtc, M2_N2);
5309 break;
5310 case DRRS_MAX_RR:
5311 default:
5312 DRM_ERROR("Unsupported refreshrate type\n");
5313 }
5314 } else if (INTEL_INFO(dev)->gen > 6) {
6e3c9717 5315 reg = PIPECONF(intel_crtc->config->cpu_transcoder);
439d7ac0 5316 val = I915_READ(reg);
a4c30b1d 5317
439d7ac0 5318 if (index > DRRS_HIGH_RR) {
6fa7aec1
VK		 5319 if (IS_VALLEYVIEW(dev))
5320 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5321 else
5322 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5323 } else {
6fa7aec1
VK		 5324 if (IS_VALLEYVIEW(dev))
5325 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5326 else
5327 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5328 }
5329 I915_WRITE(reg, val);
5330 }
5331
4e9ac947
VK		 5332 dev_priv->drrs.refresh_rate_type = index;
5333
5334 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5335}
5336
b33a2815
VK		 5337/**
5338 * intel_edp_drrs_enable - init drrs struct if supported
5339 * @intel_dp: DP struct
5340 *
5341 * Initializes frontbuffer_bits and drrs.dp
5342 */
c395578e
VK		 5343void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5344{
5345 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5346 struct drm_i915_private *dev_priv = dev->dev_private;
5347 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5348 struct drm_crtc *crtc = dig_port->base.base.crtc;
5349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5350
5351 if (!intel_crtc->config->has_drrs) {
5352 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5353 return;
5354 }
5355
5356 mutex_lock(&dev_priv->drrs.mutex);
5357 if (WARN_ON(dev_priv->drrs.dp)) {
5358 DRM_ERROR("DRRS already enabled\n");
5359 goto unlock;
5360 }
5361
5362 dev_priv->drrs.busy_frontbuffer_bits = 0;
5363
5364 dev_priv->drrs.dp = intel_dp;
5365
5366unlock:
5367 mutex_unlock(&dev_priv->drrs.mutex);
5368}
5369
b33a2815
VK		 5370/**
5371 * intel_edp_drrs_disable - Disable DRRS
5372 * @intel_dp: DP struct
5373 *
5374 */
c395578e
VK		 5375void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5376{
5377 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5378 struct drm_i915_private *dev_priv = dev->dev_private;
5379 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5380 struct drm_crtc *crtc = dig_port->base.base.crtc;
5381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5382
5383 if (!intel_crtc->config->has_drrs)
5384 return;
5385
5386 mutex_lock(&dev_priv->drrs.mutex);
5387 if (!dev_priv->drrs.dp) {
5388 mutex_unlock(&dev_priv->drrs.mutex);
5389 return;
5390 }
5391
5392 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5393 intel_dp_set_drrs_state(dev_priv->dev,
5394 intel_dp->attached_connector->panel.
5395 fixed_mode->vrefresh);
5396
5397 dev_priv->drrs.dp = NULL;
5398 mutex_unlock(&dev_priv->drrs.mutex);
5399
5400 cancel_delayed_work_sync(&dev_priv->drrs.work);
5401}
5402
4e9ac947
VK		 5403static void intel_edp_drrs_downclock_work(struct work_struct *work)
5404{
5405 struct drm_i915_private *dev_priv =
5406 container_of(work, typeof(*dev_priv), drrs.work.work);
5407 struct intel_dp *intel_dp;
5408
5409 mutex_lock(&dev_priv->drrs.mutex);
5410
5411 intel_dp = dev_priv->drrs.dp;
5412
5413 if (!intel_dp)
5414 goto unlock;
5415
439d7ac0 5416 /*
4e9ac947
VK		 5417 * The delayed work can race with an invalidate hence we need to
5418 * recheck.
439d7ac0
PB		 5419 */
5420
4e9ac947
VK		 5421 if (dev_priv->drrs.busy_frontbuffer_bits)
5422 goto unlock;
439d7ac0 5423
4e9ac947
VK		 5424 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5425 intel_dp_set_drrs_state(dev_priv->dev,
5426 intel_dp->attached_connector->panel.
5427 downclock_mode->vrefresh);
439d7ac0 5428
4e9ac947 5429unlock:
4e9ac947 5430 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5431}
5432
b33a2815
VK		 5433/**
5434 * intel_edp_drrs_invalidate - Invalidate DRRS
5435 * @dev: DRM device
5436 * @frontbuffer_bits: frontbuffer plane tracking bits
5437 *
5438 * When there is a disturbance on screen (due to cursor movement/time
5439 * update etc), DRRS needs to be invalidated, i.e. need to switch to
5440 * high RR.
5441 *
5442 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5443 */
a93fad0f
VK		 5444void intel_edp_drrs_invalidate(struct drm_device *dev,
5445 unsigned frontbuffer_bits)
5446{
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448 struct drm_crtc *crtc;
5449 enum pipe pipe;
5450
9da7d693 5451 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5452 return;
5453
88f933a8 5454 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5455
a93fad0f 5456 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5457 if (!dev_priv->drrs.dp) {
5458 mutex_unlock(&dev_priv->drrs.mutex);
5459 return;
5460 }
5461
a93fad0f
VK		 5462 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5463 pipe = to_intel_crtc(crtc)->pipe;
5464
5465 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
a93fad0f
VK		 5466 intel_dp_set_drrs_state(dev_priv->dev,
5467 dev_priv->drrs.dp->attached_connector->panel.
5468 fixed_mode->vrefresh);
5469 }
5470
5471 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5472
5473 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5474 mutex_unlock(&dev_priv->drrs.mutex);
5475}
5476
b33a2815
VK		 5477/**
5478 * intel_edp_drrs_flush - Flush DRRS
5479 * @dev: DRM device
5480 * @frontbuffer_bits: frontbuffer plane tracking bits
5481 *
5482 * When there is no movement on screen, DRRS work can be scheduled.
5483 * This DRRS work is responsible for setting relevant registers after a
5484 * timeout of 1 second.
5485 *
5486 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5487 */
a93fad0f
VK		 5488void intel_edp_drrs_flush(struct drm_device *dev,
5489 unsigned frontbuffer_bits)
5490{
5491 struct drm_i915_private *dev_priv = dev->dev_private;
5492 struct drm_crtc *crtc;
5493 enum pipe pipe;
5494
9da7d693 5495 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5496 return;
5497
88f933a8 5498 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5499
a93fad0f 5500 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5501 if (!dev_priv->drrs.dp) {
5502 mutex_unlock(&dev_priv->drrs.mutex);
5503 return;
5504 }
5505
a93fad0f
VK		 5506 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5507 pipe = to_intel_crtc(crtc)->pipe;
5508 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5509
a93fad0f
VK		 5510 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&
5511 !dev_priv->drrs.busy_frontbuffer_bits)
5512 schedule_delayed_work(&dev_priv->drrs.work,
5513 msecs_to_jiffies(1000));
5514 mutex_unlock(&dev_priv->drrs.mutex);
5515}
5516
b33a2815
VK		 5517/**
5518 * DOC: Display Refresh Rate Switching (DRRS)
5519 *
5520 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5521 * which enables swtching between low and high refresh rates,
5522 * dynamically, based on the usage scenario. This feature is applicable
5523 * for internal panels.
5524 *
5525 * Indication that the panel supports DRRS is given by the panel EDID, which
5526 * would list multiple refresh rates for one resolution.
5527 *
5528 * DRRS is of 2 types - static and seamless.
5529 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5530 * (may appear as a blink on screen) and is used in dock-undock scenario.
5531 * Seamless DRRS involves changing RR without any visual effect to the user
5532 * and can be used during normal system usage. This is done by programming
5533 * certain registers.
5534 *
5535 * Support for static/seamless DRRS may be indicated in the VBT based on
5536 * inputs from the panel spec.
5537 *
5538 * DRRS saves power by switching to low RR based on usage scenarios.
5539 *
5540 * eDP DRRS:-
5541 * The implementation is based on frontbuffer tracking implementation.
5542 * When there is a disturbance on the screen triggered by user activity or a
5543 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5544 * When there is no movement on screen, after a timeout of 1 second, a switch
5545 * to low RR is made.
5546 * For integration with frontbuffer tracking code,
5547 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5548 *
5549 * DRRS can be further extended to support other internal panels and also
5550 * the scenario of video playback wherein RR is set based on the rate
5551 * requested by userspace.
5552 */
5553
5554/**
5555 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5556 * @intel_connector: eDP connector
5557 * @fixed_mode: preferred mode of panel
5558 *
5559 * This function is called only once at driver load to initialize basic
5560 * DRRS stuff.
5561 *
5562 * Returns:
5563 * Downclock mode if panel supports it, else return NULL.
5564 * DRRS support is determined by the presence of downclock mode (apart
5565 * from VBT setting).
5566 */
4f9db5b5 5567static struct drm_display_mode *
96178eeb
VK		 5568intel_dp_drrs_init(struct intel_connector *intel_connector,
5569 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5570{
5571 struct drm_connector *connector = &intel_connector->base;
96178eeb 5572 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5573 struct drm_i915_private *dev_priv = dev->dev_private;
5574 struct drm_display_mode *downclock_mode = NULL;
5575
9da7d693
DV		 5576 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5577 mutex_init(&dev_priv->drrs.mutex);
5578
4f9db5b5
PB		 5579 if (INTEL_INFO(dev)->gen <= 6) {
5580 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5581 return NULL;
5582 }
5583
5584 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5585 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5586 return NULL;
5587 }
5588
5589 downclock_mode = intel_find_panel_downclock
5590 (dev, fixed_mode, connector);
5591
5592 if (!downclock_mode) {
a1d26342 5593 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5594 return NULL;
5595 }
5596
96178eeb 5597 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5598
96178eeb 5599 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5600 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5601 return downclock_mode;
5602}
5603
ed92f0b2 5604static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5605 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5606{
5607 struct drm_connector *connector = &intel_connector->base;
5608 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5609 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5610 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5611 struct drm_i915_private *dev_priv = dev->dev_private;
5612 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5613 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5614 bool has_dpcd;
5615 struct drm_display_mode *scan;
5616 struct edid *edid;
6517d273 5617 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5618
5619 if (!is_edp(intel_dp))
5620 return true;
5621
49e6bc51
VS		 5622 pps_lock(intel_dp);
5623 intel_edp_panel_vdd_sanitize(intel_dp);
5624 pps_unlock(intel_dp);
63635217 5625
ed92f0b2 5626 /* Cache DPCD and EDID for edp. */
ed92f0b2 5627 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5628
5629 if (has_dpcd) {
5630 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5631 dev_priv->no_aux_handshake =
5632 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5633 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5634 } else {
5635 /* if this fails, presume the device is a ghost */
5636 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5637 return false;
5638 }
5639
5640 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5641 pps_lock(intel_dp);
36b5f425 5642 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5643 pps_unlock(intel_dp);
ed92f0b2 5644
060c8778 5645 mutex_lock(&dev->mode_config.mutex);
0b99836f 5646 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5647 if (edid) {
5648 if (drm_add_edid_modes(connector, edid)) {
5649 drm_mode_connector_update_edid_property(connector,
5650 edid);
5651 drm_edid_to_eld(connector, edid);
5652 } else {
5653 kfree(edid);
5654 edid = ERR_PTR(-EINVAL);
5655 }
5656 } else {
5657 edid = ERR_PTR(-ENOENT);
5658 }
5659 intel_connector->edid = edid;
5660
5661 /* prefer fixed mode from EDID if available */
5662 list_for_each_entry(scan, &connector->probed_modes, head) {
5663 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5664 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5665 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5666 intel_connector, fixed_mode);
ed92f0b2
PZ		 5667 break;
5668 }
5669 }
5670
5671 /* fallback to VBT if available for eDP */
5672 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5673 fixed_mode = drm_mode_duplicate(dev,
5674 dev_priv->vbt.lfp_lvds_vbt_mode);
5675 if (fixed_mode)
5676 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5677 }
060c8778 5678 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5679
01527b31
CT		 5680 if (IS_VALLEYVIEW(dev)) {
5681 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5682 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5683
5684 /*
5685 * Figure out the current pipe for the initial backlight setup.
5686 * If the current pipe isn't valid, try the PPS pipe, and if that
5687 * fails just assume pipe A.
5688 */
5689 if (IS_CHERRYVIEW(dev))
5690 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5691 else
5692 pipe = PORT_TO_PIPE(intel_dp->DP);
5693
5694 if (pipe != PIPE_A && pipe != PIPE_B)
5695 pipe = intel_dp->pps_pipe;
5696
5697 if (pipe != PIPE_A && pipe != PIPE_B)
5698 pipe = PIPE_A;
5699
5700 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5701 pipe_name(pipe));
01527b31
CT		 5702 }
5703
4f9db5b5 5704 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5705 intel_connector->panel.backlight_power = intel_edp_backlight_power;
6517d273 5706 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5707
5708 return true;
5709}
5710
16c25533 5711bool
f0fec3f2
PZ		 5712intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5713 struct intel_connector *intel_connector)
a4fc5ed6 5714{
f0fec3f2
PZ		 5715 struct drm_connector *connector = &intel_connector->base;
5716 struct intel_dp *intel_dp = &intel_dig_port->dp;
5717 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5718 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5719 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5720 enum port port = intel_dig_port->port;
0b99836f 5721 int type;
a4fc5ed6 5722
a4a5d2f8
VS		 5723 intel_dp->pps_pipe = INVALID_PIPE;
5724
ec5b01dd 5725 /* intel_dp vfuncs */
b6b5e383
DL		 5726 if (INTEL_INFO(dev)->gen >= 9)
5727 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5728 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5729 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5730 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5731 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5732 else if (HAS_PCH_SPLIT(dev))
5733 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5734 else
5735 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5736
b9ca5fad
DL		 5737 if (INTEL_INFO(dev)->gen >= 9)
5738 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5739 else
5740 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5741
0767935e
DV		 5742 /* Preserve the current hw state. */
5743 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5744 intel_dp->attached_connector = intel_connector;
3d3dc149 5745
3b32a35b 5746 if (intel_dp_is_edp(dev, port))
b329530c 5747 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5748 else
5749 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5750
f7d24902
ID		 5751 /*
5752 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5753 * for DP the encoder type can be set by the caller to
5754 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5755 */
5756 if (type == DRM_MODE_CONNECTOR_eDP)
5757 intel_encoder->type = INTEL_OUTPUT_EDP;
5758
c17ed5b5
VS		 5759 /* eDP only on port B and/or C on vlv/chv */
5760 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5761 port != PORT_B && port != PORT_C))
5762 return false;
5763
e7281eab
ID		 5764 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5765 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5766 port_name(port));
5767
b329530c 5768 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5769 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5770
a4fc5ed6
KP		 5771 connector->interlace_allowed = true;
5772 connector->doublescan_allowed = 0;
5773
f0fec3f2 5774 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5775 edp_panel_vdd_work);
a4fc5ed6 5776
df0e9248 5777 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5778 drm_connector_register(connector);
a4fc5ed6 5779
affa9354 5780 if (HAS_DDI(dev))
bcbc889b
PZ		 5781 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5782 else
5783 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5784 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5785
0b99836f 5786 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5787 switch (port) {
5788 case PORT_A:
1d843f9d 5789 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5790 break;
5791 case PORT_B:
1d843f9d 5792 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5793 break;
5794 case PORT_C:
1d843f9d 5795 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5796 break;
5797 case PORT_D:
1d843f9d 5798 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5799 break;
5800 default:
ad1c0b19 5801 BUG();
5eb08b69
ZW		 5802 }
5803
dada1a9f 5804 if (is_edp(intel_dp)) {
773538e8 5805 pps_lock(intel_dp);
1e74a324
VS		 5806 intel_dp_init_panel_power_timestamps(intel_dp);
5807 if (IS_VALLEYVIEW(dev))
a4a5d2f8 5808 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5809 else
36b5f425 5810 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5811 pps_unlock(intel_dp);
dada1a9f 5812 }
0095e6dc 5813
9d1a1031 5814 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5815
0e32b39c 5816 /* init MST on ports that can support it */
c86ea3d0 5817 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
0e32b39c 5818 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5819 intel_dp_mst_encoder_init(intel_dig_port,
5820 intel_connector->base.base.id);
0e32b39c
DA		 5821 }
5822 }
5823
36b5f425 5824 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5825 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5826 if (is_edp(intel_dp)) {
5827 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5828 /*
5829 * vdd might still be enabled do to the delayed vdd off.
5830 * Make sure vdd is actually turned off here.
5831 */
773538e8 5832 pps_lock(intel_dp);
4be73780 5833 edp_panel_vdd_off_sync(intel_dp);
773538e8 5834 pps_unlock(intel_dp);
15b1d171 5835 }
34ea3d38 5836 drm_connector_unregister(connector);
b2f246a8 5837 drm_connector_cleanup(connector);
16c25533 5838 return false;
b2f246a8 5839 }
32f9d658 5840
f684960e
CW		 5841 intel_dp_add_properties(intel_dp, connector);
5842
a4fc5ed6
KP		 5843 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5844 * 0xd. Failure to do so will result in spurious interrupts being
5845 * generated on the port when a cable is not attached.
5846 */
5847 if (IS_G4X(dev) && !IS_GM45(dev)) {
5848 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5849 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5850 }
16c25533 5851
aa7471d2
JN		 5852 i915_debugfs_connector_add(connector);
5853
16c25533 5854 return true;
a4fc5ed6 5855}
f0fec3f2
PZ		 5856
5857void
5858intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5859{
13cf5504 5860 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5861 struct intel_digital_port *intel_dig_port;
5862 struct intel_encoder *intel_encoder;
5863 struct drm_encoder *encoder;
5864 struct intel_connector *intel_connector;
5865
b14c5679 5866 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5867 if (!intel_dig_port)
5868 return;
5869
08d9bc92 5870 intel_connector = intel_connector_alloc();
f0fec3f2
PZ		 5871 if (!intel_connector) {
5872 kfree(intel_dig_port);
5873 return;
5874 }
5875
5876 intel_encoder = &intel_dig_port->base;
5877 encoder = &intel_encoder->base;
5878
5879 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5880 DRM_MODE_ENCODER_TMDS);
5881
5bfe2ac0 5882 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5883 intel_encoder->disable = intel_disable_dp;
00c09d70 5884 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5885 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5886 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5887 if (IS_CHERRYVIEW(dev)) {
9197c88b 5888 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5889 intel_encoder->pre_enable = chv_pre_enable_dp;
5890 intel_encoder->enable = vlv_enable_dp;
580d3811 5891 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5892 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5893 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5894 intel_encoder->pre_enable = vlv_pre_enable_dp;
5895 intel_encoder->enable = vlv_enable_dp;
49277c31 5896 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5897 } else {
ecff4f3b
JN		 5898 intel_encoder->pre_enable = g4x_pre_enable_dp;
5899 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5900 if (INTEL_INFO(dev)->gen >= 5)
5901 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5902 }
f0fec3f2 5903
174edf1f 5904 intel_dig_port->port = port;
f0fec3f2
PZ		 5905 intel_dig_port->dp.output_reg = output_reg;
5906
00c09d70 5907 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5908 if (IS_CHERRYVIEW(dev)) {
5909 if (port == PORT_D)
5910 intel_encoder->crtc_mask = 1 << 2;
5911 else
5912 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5913 } else {
5914 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5915 }
bc079e8b 5916 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5917 intel_encoder->hot_plug = intel_dp_hot_plug;
5918
13cf5504
DA		 5919 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5920 dev_priv->hpd_irq_port[port] = intel_dig_port;
5921
15b1d171
PZ		 5922 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5923 drm_encoder_cleanup(encoder);
5924 kfree(intel_dig_port);
b2f246a8 5925 kfree(intel_connector);
15b1d171 5926 }
f0fec3f2 5927}
0e32b39c
DA		 5928
5929void intel_dp_mst_suspend(struct drm_device *dev)
5930{
5931 struct drm_i915_private *dev_priv = dev->dev_private;
5932 int i;
5933
5934 /* disable MST */
5935 for (i = 0; i < I915_MAX_PORTS; i++) {
5936 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5937 if (!intel_dig_port)
5938 continue;
5939
5940 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5941 if (!intel_dig_port->dp.can_mst)
5942 continue;
5943 if (intel_dig_port->dp.is_mst)
5944 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5945 }
5946 }
5947}
5948
5949void intel_dp_mst_resume(struct drm_device *dev)
5950{
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 int i;
5953
5954 for (i = 0; i < I915_MAX_PORTS; i++) {
5955 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5956 if (!intel_dig_port)
5957 continue;
5958 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5959 int ret;
5960
5961 if (!intel_dig_port->dp.can_mst)
5962 continue;
5963
5964 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5965 if (ret != 0) {
5966 intel_dp_check_mst_status(&intel_dig_port->dp);
5967 }
5968 }
5969 }
5970}
Linux kernel - Deliverables
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