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drm/i915: fix wait_remaining_ms_from_jiffies
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
4be73780
DV		 94static void edp_panel_vdd_on(struct intel_dp *intel_dp);
95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 315 struct drm_i915_private *dev_priv = dev->dev_private;
316
bf13e81b 317 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 318}
319
9b984dae
KP		 320static void
321intel_dp_check_edp(struct intel_dp *intel_dp)
322{
30add22d 323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 324 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 325
9b984dae
KP		 326 if (!is_edp(intel_dp))
327 return;
453c5420 328
4be73780 329 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 332 I915_READ(_pp_stat_reg(intel_dp)),
333 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 334 }
335}
336
9ee32fea
DV		 337static uint32_t
338intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
339{
340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
341 struct drm_device *dev = intel_dig_port->base.base.dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 343 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 344 uint32_t status;
345 bool done;
346
ef04f00d 347#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 348 if (has_aux_irq)
b18ac466 349 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 350 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 351 else
352 done = wait_for_atomic(C, 10) == 0;
353 if (!done)
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
355 has_aux_irq);
356#undef C
357
358 return status;
359}
360
ec5b01dd 361static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 362{
174edf1f
PZ		 363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 365
ec5b01dd
DL		 366 /*
367 * The clock divider is based off the hrawclk, and would like to run at
368 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 369 */
ec5b01dd
DL		 370 return index ? 0 : intel_hrawclk(dev) / 2;
371}
372
373static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
374{
375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
376 struct drm_device *dev = intel_dig_port->base.base.dev;
377
378 if (index)
379 return 0;
380
381 if (intel_dig_port->port == PORT_A) {
382 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 384 else
b84a1cf8 385 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 386 } else {
387 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
388 }
389}
390
391static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
392{
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct drm_device *dev = intel_dig_port->base.base.dev;
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (intel_dig_port->port == PORT_A) {
398 if (index)
399 return 0;
400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 401 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
402 /* Workaround for non-ULT HSW */
bc86625a
CW		 403 switch (index) {
404 case 0: return 63;
405 case 1: return 72;
406 default: return 0;
407 }
ec5b01dd 408 } else {
bc86625a 409 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 410 }
b84a1cf8
RV		 411}
412
ec5b01dd
DL		 413static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 return index ? 0 : 100;
416}
417
5ed12a19
DL		 418static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
419 bool has_aux_irq,
420 int send_bytes,
421 uint32_t aux_clock_divider)
422{
423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
424 struct drm_device *dev = intel_dig_port->base.base.dev;
425 uint32_t precharge, timeout;
426
427 if (IS_GEN6(dev))
428 precharge = 3;
429 else
430 precharge = 5;
431
432 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
433 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
434 else
435 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
436
437 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 438 DP_AUX_CH_CTL_DONE |
5ed12a19 439 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 440 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 441 timeout |
788d4433 442 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 443 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
444 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 445 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 446}
447
b84a1cf8
RV		 448static int
449intel_dp_aux_ch(struct intel_dp *intel_dp,
450 uint8_t *send, int send_bytes,
451 uint8_t *recv, int recv_size)
452{
453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
454 struct drm_device *dev = intel_dig_port->base.base.dev;
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
457 uint32_t ch_data = ch_ctl + 4;
bc86625a 458 uint32_t aux_clock_divider;
b84a1cf8
RV		 459 int i, ret, recv_bytes;
460 uint32_t status;
5ed12a19 461 int try, clock = 0;
4aeebd74 462 bool has_aux_irq = true;
b84a1cf8
RV		 463
464 /* dp aux is extremely sensitive to irq latency, hence request the
465 * lowest possible wakeup latency and so prevent the cpu from going into
466 * deep sleep states.
467 */
468 pm_qos_update_request(&dev_priv->pm_qos, 0);
469
470 intel_dp_check_edp(intel_dp);
5eb08b69 471
c67a470b
PZ		 472 intel_aux_display_runtime_get(dev_priv);
473
11bee43e
JB		 474 /* Try to wait for any previous AUX channel activity */
475 for (try = 0; try < 3; try++) {
ef04f00d 476 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 477 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
478 break;
479 msleep(1);
480 }
481
482 if (try == 3) {
483 WARN(1, "dp_aux_ch not started status 0x%08x\n",
484 I915_READ(ch_ctl));
9ee32fea
DV		 485 ret = -EBUSY;
486 goto out;
4f7f7b7e
CW		 487 }
488
46a5ae9f
PZ		 489 /* Only 5 data registers! */
490 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
491 ret = -E2BIG;
492 goto out;
493 }
494
ec5b01dd 495 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 496 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
497 has_aux_irq,
498 send_bytes,
499 aux_clock_divider);
5ed12a19 500
bc86625a
CW		 501 /* Must try at least 3 times according to DP spec */
502 for (try = 0; try < 5; try++) {
503 /* Load the send data into the aux channel data registers */
504 for (i = 0; i < send_bytes; i += 4)
505 I915_WRITE(ch_data + i,
506 pack_aux(send + i, send_bytes - i));
507
508 /* Send the command and wait for it to complete */
5ed12a19 509 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 510
511 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
512
513 /* Clear done status and any errors */
514 I915_WRITE(ch_ctl,
515 status |
516 DP_AUX_CH_CTL_DONE |
517 DP_AUX_CH_CTL_TIME_OUT_ERROR |
518 DP_AUX_CH_CTL_RECEIVE_ERROR);
519
520 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
521 DP_AUX_CH_CTL_RECEIVE_ERROR))
522 continue;
523 if (status & DP_AUX_CH_CTL_DONE)
524 break;
525 }
4f7f7b7e 526 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 527 break;
528 }
529
a4fc5ed6 530 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 531 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 532 ret = -EBUSY;
533 goto out;
a4fc5ed6
KP		 534 }
535
536 /* Check for timeout or receive error.
537 * Timeouts occur when the sink is not connected
538 */
a5b3da54 539 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 540 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 541 ret = -EIO;
542 goto out;
a5b3da54 543 }
1ae8c0a5
KP		 544
545 /* Timeouts occur when the device isn't connected, so they're
546 * "normal" -- don't fill the kernel log with these */
a5b3da54 547 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 548 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 549 ret = -ETIMEDOUT;
550 goto out;
a4fc5ed6
KP		 551 }
552
553 /* Unload any bytes sent back from the other side */
554 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
555 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 556 if (recv_bytes > recv_size)
557 recv_bytes = recv_size;
0206e353 558
4f7f7b7e
CW		 559 for (i = 0; i < recv_bytes; i += 4)
560 unpack_aux(I915_READ(ch_data + i),
561 recv + i, recv_bytes - i);
a4fc5ed6 562
9ee32fea
DV		 563 ret = recv_bytes;
564out:
565 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 566 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 567
568 return ret;
a4fc5ed6
KP		 569}
570
571/* Write data to the aux channel in native mode */
572static int
ea5b213a 573intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 574 uint16_t address, uint8_t *send, int send_bytes)
575{
576 int ret;
577 uint8_t msg[20];
578 int msg_bytes;
579 uint8_t ack;
580
46a5ae9f
PZ		 581 if (WARN_ON(send_bytes > 16))
582 return -E2BIG;
583
9b984dae 584 intel_dp_check_edp(intel_dp);
6b27f7f0 585 msg[0] = DP_AUX_NATIVE_WRITE << 4;
a4fc5ed6 586 msg[1] = address >> 8;
eebc863e 587 msg[2] = address & 0xff;
a4fc5ed6
KP		 588 msg[3] = send_bytes - 1;
589 memcpy(&msg[4], send, send_bytes);
590 msg_bytes = send_bytes + 4;
591 for (;;) {
ea5b213a 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 593 if (ret < 0)
594 return ret;
6b27f7f0
TR		 595 ack >>= 4;
596 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
a4fc5ed6 597 break;
6b27f7f0 598 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 599 udelay(100);
600 else
a5b3da54 601 return -EIO;
a4fc5ed6
KP		 602 }
603 return send_bytes;
604}
605
606/* Write a single byte to the aux channel in native mode */
607static int
ea5b213a 608intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 609 uint16_t address, uint8_t byte)
610{
ea5b213a 611 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 612}
613
614/* read bytes from a native aux channel */
615static int
ea5b213a 616intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 617 uint16_t address, uint8_t *recv, int recv_bytes)
618{
619 uint8_t msg[4];
620 int msg_bytes;
621 uint8_t reply[20];
622 int reply_bytes;
623 uint8_t ack;
624 int ret;
625
46a5ae9f
PZ		 626 if (WARN_ON(recv_bytes > 19))
627 return -E2BIG;
628
9b984dae 629 intel_dp_check_edp(intel_dp);
6b27f7f0 630 msg[0] = DP_AUX_NATIVE_READ << 4;
a4fc5ed6
KP		 631 msg[1] = address >> 8;
632 msg[2] = address & 0xff;
633 msg[3] = recv_bytes - 1;
634
635 msg_bytes = 4;
636 reply_bytes = recv_bytes + 1;
637
638 for (;;) {
ea5b213a 639 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 640 reply, reply_bytes);
a5b3da54
KP		 641 if (ret == 0)
642 return -EPROTO;
643 if (ret < 0)
a4fc5ed6 644 return ret;
6b27f7f0
TR		 645 ack = reply[0] >> 4;
646 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
a4fc5ed6
KP		 647 memcpy(recv, reply + 1, ret - 1);
648 return ret - 1;
649 }
6b27f7f0 650 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 651 udelay(100);
652 else
a5b3da54 653 return -EIO;
a4fc5ed6
KP		 654 }
655}
656
657static int
ab2c0672
DA		 658intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
659 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 660{
ab2c0672 661 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 662 struct intel_dp *intel_dp = container_of(adapter,
663 struct intel_dp,
664 adapter);
ab2c0672
DA		 665 uint16_t address = algo_data->address;
666 uint8_t msg[5];
667 uint8_t reply[2];
8316f337 668 unsigned retry;
ab2c0672
DA		 669 int msg_bytes;
670 int reply_bytes;
671 int ret;
672
4be73780 673 edp_panel_vdd_on(intel_dp);
9b984dae 674 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 675 /* Set up the command byte */
676 if (mode & MODE_I2C_READ)
6b27f7f0 677 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 678 else
6b27f7f0 679 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 680
681 if (!(mode & MODE_I2C_STOP))
6b27f7f0 682 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 683
ab2c0672
DA		 684 msg[1] = address >> 8;
685 msg[2] = address;
686
687 switch (mode) {
688 case MODE_I2C_WRITE:
689 msg[3] = 0;
690 msg[4] = write_byte;
691 msg_bytes = 5;
692 reply_bytes = 1;
693 break;
694 case MODE_I2C_READ:
695 msg[3] = 0;
696 msg_bytes = 4;
697 reply_bytes = 2;
698 break;
699 default:
700 msg_bytes = 3;
701 reply_bytes = 1;
702 break;
703 }
704
58c67ce9
JN		 705 /*
706 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
707 * required to retry at least seven times upon receiving AUX_DEFER
708 * before giving up the AUX transaction.
709 */
710 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 711 ret = intel_dp_aux_ch(intel_dp,
712 msg, msg_bytes,
713 reply, reply_bytes);
ab2c0672 714 if (ret < 0) {
3ff99164 715 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 716 goto out;
ab2c0672 717 }
8316f337 718
6b27f7f0
TR		 719 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
720 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 721 /* I2C-over-AUX Reply field is only valid
722 * when paired with AUX ACK.
723 */
724 break;
6b27f7f0 725 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 726 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 727 ret = -EREMOTEIO;
728 goto out;
6b27f7f0 729 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 730 /*
731 * For now, just give more slack to branch devices. We
732 * could check the DPCD for I2C bit rate capabilities,
733 * and if available, adjust the interval. We could also
734 * be more careful with DP-to-Legacy adapters where a
735 * long legacy cable may force very low I2C bit rates.
736 */
737 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
738 DP_DWN_STRM_PORT_PRESENT)
739 usleep_range(500, 600);
740 else
741 usleep_range(300, 400);
8316f337
DF		 742 continue;
743 default:
744 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
745 reply[0]);
8a5e6aeb
PZ		 746 ret = -EREMOTEIO;
747 goto out;
8316f337
DF		 748 }
749
6b27f7f0
TR		 750 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
751 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 752 if (mode == MODE_I2C_READ) {
753 *read_byte = reply[1];
754 }
8a5e6aeb
PZ		 755 ret = reply_bytes - 1;
756 goto out;
6b27f7f0 757 case DP_AUX_I2C_REPLY_NACK:
8316f337 758 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 759 ret = -EREMOTEIO;
760 goto out;
6b27f7f0 761 case DP_AUX_I2C_REPLY_DEFER:
8316f337 762 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 763 udelay(100);
764 break;
765 default:
8316f337 766 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 767 ret = -EREMOTEIO;
768 goto out;
ab2c0672
DA		 769 }
770 }
8316f337
DF		 771
772 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 773 ret = -EREMOTEIO;
774
775out:
4be73780 776 edp_panel_vdd_off(intel_dp, false);
8a5e6aeb 777 return ret;
a4fc5ed6
KP		 778}
779
780static int
ea5b213a 781intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 782 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 783{
0b5c541b
KP		 784 int ret;
785
d54e9d28 786 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 787 intel_dp->algo.running = false;
788 intel_dp->algo.address = 0;
789 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
790
0206e353 791 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 792 intel_dp->adapter.owner = THIS_MODULE;
793 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 794 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 795 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
796 intel_dp->adapter.algo_data = &intel_dp->algo;
5bdebb18 797 intel_dp->adapter.dev.parent = intel_connector->base.kdev;
ea5b213a 798
0b5c541b 799 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
0b5c541b 800 return ret;
a4fc5ed6
KP		 801}
802
c6bb3538
DV		 803static void
804intel_dp_set_clock(struct intel_encoder *encoder,
805 struct intel_crtc_config *pipe_config, int link_bw)
806{
807 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 808 const struct dp_link_dpll *divisor = NULL;
809 int i, count = 0;
c6bb3538
DV		 810
811 if (IS_G4X(dev)) {
9dd4ffdf
CML		 812 divisor = gen4_dpll;
813 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 814 } else if (IS_HASWELL(dev)) {
815 /* Haswell has special-purpose DP DDI clocks. */
816 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 817 divisor = pch_dpll;
818 count = ARRAY_SIZE(pch_dpll);
c6bb3538 819 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 820 divisor = vlv_dpll;
821 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 822 }
9dd4ffdf
CML		 823
824 if (divisor && count) {
825 for (i = 0; i < count; i++) {
826 if (link_bw == divisor[i].link_bw) {
827 pipe_config->dpll = divisor[i].dpll;
828 pipe_config->clock_set = true;
829 break;
830 }
831 }
c6bb3538
DV		 832 }
833}
834
00c09d70 835bool
5bfe2ac0
DV		 836intel_dp_compute_config(struct intel_encoder *encoder,
837 struct intel_crtc_config *pipe_config)
a4fc5ed6 838{
5bfe2ac0 839 struct drm_device *dev = encoder->base.dev;
36008365 840 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 841 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 843 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 844 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 845 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 846 int lane_count, clock;
397fe157 847 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 848 /* Conveniently, the link BW constants become indices with a shift...*/
849 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 850 int bpp, mode_rate;
06ea66b6 851 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 852 int link_avail, link_clock;
a4fc5ed6 853
bc7d38a4 854 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 855 pipe_config->has_pch_encoder = true;
856
03afc4a2 857 pipe_config->has_dp_encoder = true;
a4fc5ed6 858
dd06f90e
JN		 859 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
860 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
861 adjusted_mode);
2dd24552
JB		 862 if (!HAS_PCH_SPLIT(dev))
863 intel_gmch_panel_fitting(intel_crtc, pipe_config,
864 intel_connector->panel.fitting_mode);
865 else
b074cec8
JB		 866 intel_pch_panel_fitting(intel_crtc, pipe_config,
867 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 868 }
869
cb1793ce 870 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 871 return false;
872
083f9560
DV		 873 DRM_DEBUG_KMS("DP link computation with max lane count %i "
874 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 875 max_lane_count, bws[max_clock],
876 adjusted_mode->crtc_clock);
083f9560 877
36008365
DV		 878 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
879 * bpc in between. */
3e7ca985 880 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 881 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
882 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 883 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
884 dev_priv->vbt.edp_bpp);
6da7f10d 885 bpp = dev_priv->vbt.edp_bpp;
7984211e 886 }
657445fe 887
36008365 888 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 889 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
890 bpp);
36008365
DV		 891
892 for (clock = 0; clock <= max_clock; clock++) {
893 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
894 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
895 link_avail = intel_dp_max_data_rate(link_clock,
896 lane_count);
897
898 if (mode_rate <= link_avail) {
899 goto found;
900 }
901 }
902 }
903 }
c4867936 904
36008365 905 return false;
3685a8f3 906
36008365 907found:
55bc60db
VS		 908 if (intel_dp->color_range_auto) {
909 /*
910 * See:
911 * CEA-861-E - 5.1 Default Encoding Parameters
912 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
913 */
18316c8c 914 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 915 intel_dp->color_range = DP_COLOR_RANGE_16_235;
916 else
917 intel_dp->color_range = 0;
918 }
919
3685a8f3 920 if (intel_dp->color_range)
50f3b016 921 pipe_config->limited_color_range = true;
a4fc5ed6 922
36008365
DV		 923 intel_dp->link_bw = bws[clock];
924 intel_dp->lane_count = lane_count;
657445fe 925 pipe_config->pipe_bpp = bpp;
ff9a6750 926 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 927
36008365
DV		 928 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
929 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 930 pipe_config->port_clock, bpp);
36008365
DV		 931 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
932 mode_rate, link_avail);
a4fc5ed6 933
03afc4a2 934 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 935 adjusted_mode->crtc_clock,
936 pipe_config->port_clock,
03afc4a2 937 &pipe_config->dp_m_n);
9d1a455b 938
c6bb3538
DV		 939 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
940
03afc4a2 941 return true;
a4fc5ed6
KP		 942}
943
7c62a164 944static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 945{
7c62a164
DV		 946 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
947 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
948 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 949 struct drm_i915_private *dev_priv = dev->dev_private;
950 u32 dpa_ctl;
951
ff9a6750 952 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 953 dpa_ctl = I915_READ(DP_A);
954 dpa_ctl &= ~DP_PLL_FREQ_MASK;
955
ff9a6750 956 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 957 /* For a long time we've carried around a ILK-DevA w/a for the
958 * 160MHz clock. If we're really unlucky, it's still required.
959 */
960 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 961 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 962 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 963 } else {
964 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 965 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 966 }
1ce17038 967
ea9b6006
DV		 968 I915_WRITE(DP_A, dpa_ctl);
969
970 POSTING_READ(DP_A);
971 udelay(500);
972}
973
b934223d 974static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 975{
b934223d 976 struct drm_device *dev = encoder->base.dev;
417e822d 977 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 978 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 979 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 980 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
981 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 982
417e822d 983 /*
1a2eb460 984 * There are four kinds of DP registers:
417e822d
KP		 985 *
986 * IBX PCH
1a2eb460
KP		 987 * SNB CPU
988 * IVB CPU
417e822d
KP		 989 * CPT PCH
990 *
991 * IBX PCH and CPU are the same for almost everything,
992 * except that the CPU DP PLL is configured in this
993 * register
994 *
995 * CPT PCH is quite different, having many bits moved
996 * to the TRANS_DP_CTL register instead. That
997 * configuration happens (oddly) in ironlake_pch_enable
998 */
9c9e7927 999
417e822d
KP		 1000 /* Preserve the BIOS-computed detected bit. This is
1001 * supposed to be read-only.
1002 */
1003 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1004
417e822d 1005 /* Handle DP bits in common between all three register formats */
417e822d 1006 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1007 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1008
e0dac65e
WF		 1009 if (intel_dp->has_audio) {
1010 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1011 pipe_name(crtc->pipe));
ea5b213a 1012 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1013 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1014 }
247d89f6 1015
417e822d 1016 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1017
bc7d38a4 1018 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1019 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1020 intel_dp->DP |= DP_SYNC_HS_HIGH;
1021 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1022 intel_dp->DP |= DP_SYNC_VS_HIGH;
1023 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1024
6aba5b6c 1025 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1026 intel_dp->DP |= DP_ENHANCED_FRAMING;
1027
7c62a164 1028 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1029 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1030 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1031 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1032
1033 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1034 intel_dp->DP |= DP_SYNC_HS_HIGH;
1035 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1036 intel_dp->DP |= DP_SYNC_VS_HIGH;
1037 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1038
6aba5b6c 1039 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1040 intel_dp->DP |= DP_ENHANCED_FRAMING;
1041
7c62a164 1042 if (crtc->pipe == 1)
417e822d 1043 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1044 } else {
1045 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1046 }
ea9b6006 1047
bc7d38a4 1048 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1049 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1050}
1051
ffd6749d
PZ		 1052#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1053#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1054
1a5ef5b7
PZ		 1055#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1056#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1057
ffd6749d
PZ		 1058#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1059#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1060
4be73780 1061static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1062 u32 mask,
1063 u32 value)
bd943159 1064{
30add22d 1065 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1066 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1067 u32 pp_stat_reg, pp_ctrl_reg;
1068
bf13e81b
JN		 1069 pp_stat_reg = _pp_stat_reg(intel_dp);
1070 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1071
99ea7127 1072 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1073 mask, value,
1074 I915_READ(pp_stat_reg),
1075 I915_READ(pp_ctrl_reg));
32ce697c 1076
453c5420 1077 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1078 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1079 I915_READ(pp_stat_reg),
1080 I915_READ(pp_ctrl_reg));
32ce697c 1081 }
54c136d4
CW		 1082
1083 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1084}
32ce697c 1085
4be73780 1086static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1087{
1088 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1089 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1090}
1091
4be73780 1092static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1093{
1094 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1095 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1096}
1097
4be73780 1098static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1099{
1100 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1101
1102 /* When we disable the VDD override bit last we have to do the manual
1103 * wait. */
1104 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1105 intel_dp->panel_power_cycle_delay);
1106
4be73780 1107 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1108}
1109
4be73780 1110static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1111{
1112 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1113 intel_dp->backlight_on_delay);
1114}
1115
4be73780 1116static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1117{
1118 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1119 intel_dp->backlight_off_delay);
1120}
99ea7127 1121
832dd3c1
KP		 1122/* Read the current pp_control value, unlocking the register if it
1123 * is locked
1124 */
1125
453c5420 1126static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1127{
453c5420
JB		 1128 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1129 struct drm_i915_private *dev_priv = dev->dev_private;
1130 u32 control;
832dd3c1 1131
bf13e81b 1132 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1133 control &= ~PANEL_UNLOCK_MASK;
1134 control |= PANEL_UNLOCK_REGS;
1135 return control;
bd943159
KP		 1136}
1137
4be73780 1138static void edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1139{
30add22d 1140 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1141 struct drm_i915_private *dev_priv = dev->dev_private;
1142 u32 pp;
453c5420 1143 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1144
97af61f5
KP		 1145 if (!is_edp(intel_dp))
1146 return;
5d613501 1147
bd943159
KP		 1148 WARN(intel_dp->want_panel_vdd,
1149 "eDP VDD already requested on\n");
1150
1151 intel_dp->want_panel_vdd = true;
99ea7127 1152
4be73780 1153 if (edp_have_panel_vdd(intel_dp))
bd943159 1154 return;
b0665d57 1155
e9cb81a2
PZ		 1156 intel_runtime_pm_get(dev_priv);
1157
b0665d57 1158 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1159
4be73780
DV		 1160 if (!edp_have_panel_power(intel_dp))
1161 wait_panel_power_cycle(intel_dp);
99ea7127 1162
453c5420 1163 pp = ironlake_get_pp_control(intel_dp);
5d613501 1164 pp |= EDP_FORCE_VDD;
ebf33b18 1165
bf13e81b
JN		 1166 pp_stat_reg = _pp_stat_reg(intel_dp);
1167 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1168
1169 I915_WRITE(pp_ctrl_reg, pp);
1170 POSTING_READ(pp_ctrl_reg);
1171 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1172 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1173 /*
1174 * If the panel wasn't on, delay before accessing aux channel
1175 */
4be73780 1176 if (!edp_have_panel_power(intel_dp)) {
bd943159 1177 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1178 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1179 }
5d613501
JB		 1180}
1181
4be73780 1182static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1183{
30add22d 1184 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1185 struct drm_i915_private *dev_priv = dev->dev_private;
1186 u32 pp;
453c5420 1187 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1188
a0e99e68
DV		 1189 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1190
4be73780 1191 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1192 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1193
453c5420 1194 pp = ironlake_get_pp_control(intel_dp);
bd943159 1195 pp &= ~EDP_FORCE_VDD;
bd943159 1196
9f08ef59
PZ		 1197 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1198 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1199
1200 I915_WRITE(pp_ctrl_reg, pp);
1201 POSTING_READ(pp_ctrl_reg);
99ea7127 1202
453c5420
JB		 1203 /* Make sure sequencer is idle before allowing subsequent activity */
1204 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1205 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1206
1207 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1208 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1209
1210 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1211 }
1212}
5d613501 1213
4be73780 1214static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1215{
1216 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1217 struct intel_dp, panel_vdd_work);
30add22d 1218 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1219
627f7675 1220 mutex_lock(&dev->mode_config.mutex);
4be73780 1221 edp_panel_vdd_off_sync(intel_dp);
627f7675 1222 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1223}
1224
4be73780 1225static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1226{
97af61f5
KP		 1227 if (!is_edp(intel_dp))
1228 return;
5d613501 1229
bd943159 1230 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1231
bd943159
KP		 1232 intel_dp->want_panel_vdd = false;
1233
1234 if (sync) {
4be73780 1235 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1236 } else {
1237 /*
1238 * Queue the timer to fire a long
1239 * time from now (relative to the power down delay)
1240 * to keep the panel power up across a sequence of operations
1241 */
1242 schedule_delayed_work(&intel_dp->panel_vdd_work,
1243 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1244 }
5d613501
JB		 1245}
1246
4be73780 1247void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1248{
30add22d 1249 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1250 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1251 u32 pp;
453c5420 1252 u32 pp_ctrl_reg;
9934c132 1253
97af61f5 1254 if (!is_edp(intel_dp))
bd943159 1255 return;
99ea7127
KP		 1256
1257 DRM_DEBUG_KMS("Turn eDP power on\n");
1258
4be73780 1259 if (edp_have_panel_power(intel_dp)) {
99ea7127 1260 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1261 return;
99ea7127 1262 }
9934c132 1263
4be73780 1264 wait_panel_power_cycle(intel_dp);
37c6c9b0 1265
bf13e81b 1266 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1267 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1268 if (IS_GEN5(dev)) {
1269 /* ILK workaround: disable reset around power sequence */
1270 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1271 I915_WRITE(pp_ctrl_reg, pp);
1272 POSTING_READ(pp_ctrl_reg);
05ce1a49 1273 }
37c6c9b0 1274
1c0ae80a 1275 pp |= POWER_TARGET_ON;
99ea7127
KP		 1276 if (!IS_GEN5(dev))
1277 pp |= PANEL_POWER_RESET;
1278
453c5420
JB		 1279 I915_WRITE(pp_ctrl_reg, pp);
1280 POSTING_READ(pp_ctrl_reg);
9934c132 1281
4be73780 1282 wait_panel_on(intel_dp);
dce56b3c 1283 intel_dp->last_power_on = jiffies;
9934c132 1284
05ce1a49
KP		 1285 if (IS_GEN5(dev)) {
1286 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1287 I915_WRITE(pp_ctrl_reg, pp);
1288 POSTING_READ(pp_ctrl_reg);
05ce1a49 1289 }
9934c132
JB		 1290}
1291
4be73780 1292void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1293{
30add22d 1294 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1295 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1296 u32 pp;
453c5420 1297 u32 pp_ctrl_reg;
9934c132 1298
97af61f5
KP		 1299 if (!is_edp(intel_dp))
1300 return;
37c6c9b0 1301
99ea7127 1302 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1303
4be73780 1304 edp_wait_backlight_off(intel_dp);
dce56b3c 1305
453c5420 1306 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1307 /* We need to switch off panel power _and_ force vdd, for otherwise some
1308 * panels get very unhappy and cease to work. */
dff392db 1309 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420 1310
bf13e81b 1311 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1312
1313 I915_WRITE(pp_ctrl_reg, pp);
1314 POSTING_READ(pp_ctrl_reg);
9934c132 1315
dce56b3c 1316 intel_dp->last_power_cycle = jiffies;
4be73780 1317 wait_panel_off(intel_dp);
9934c132
JB		 1318}
1319
4be73780 1320void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1321{
da63a9f2
PZ		 1322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1323 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1324 struct drm_i915_private *dev_priv = dev->dev_private;
1325 u32 pp;
453c5420 1326 u32 pp_ctrl_reg;
32f9d658 1327
f01eca2e
KP		 1328 if (!is_edp(intel_dp))
1329 return;
1330
28c97730 1331 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1332 /*
1333 * If we enable the backlight right away following a panel power
1334 * on, we may see slight flicker as the panel syncs with the eDP
1335 * link. So delay a bit to make sure the image is solid before
1336 * allowing it to appear.
1337 */
4be73780 1338 wait_backlight_on(intel_dp);
453c5420 1339 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1340 pp |= EDP_BLC_ENABLE;
453c5420 1341
bf13e81b 1342 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1343
1344 I915_WRITE(pp_ctrl_reg, pp);
1345 POSTING_READ(pp_ctrl_reg);
035aa3de 1346
752aa88a 1347 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1348}
1349
4be73780 1350void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1351{
30add22d 1352 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1353 struct drm_i915_private *dev_priv = dev->dev_private;
1354 u32 pp;
453c5420 1355 u32 pp_ctrl_reg;
32f9d658 1356
f01eca2e
KP		 1357 if (!is_edp(intel_dp))
1358 return;
1359
752aa88a 1360 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1361
28c97730 1362 DRM_DEBUG_KMS("\n");
453c5420 1363 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1364 pp &= ~EDP_BLC_ENABLE;
453c5420 1365
bf13e81b 1366 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1367
1368 I915_WRITE(pp_ctrl_reg, pp);
1369 POSTING_READ(pp_ctrl_reg);
dce56b3c 1370 intel_dp->last_backlight_off = jiffies;
32f9d658 1371}
a4fc5ed6 1372
2bd2ad64 1373static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1374{
da63a9f2
PZ		 1375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1376 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1377 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1378 struct drm_i915_private *dev_priv = dev->dev_private;
1379 u32 dpa_ctl;
1380
2bd2ad64
DV		 1381 assert_pipe_disabled(dev_priv,
1382 to_intel_crtc(crtc)->pipe);
1383
d240f20f
JB		 1384 DRM_DEBUG_KMS("\n");
1385 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1386 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1387 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1388
1389 /* We don't adjust intel_dp->DP while tearing down the link, to
1390 * facilitate link retraining (e.g. after hotplug). Hence clear all
1391 * enable bits here to ensure that we don't enable too much. */
1392 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1393 intel_dp->DP |= DP_PLL_ENABLE;
1394 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1395 POSTING_READ(DP_A);
1396 udelay(200);
d240f20f
JB		 1397}
1398
2bd2ad64 1399static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1400{
da63a9f2
PZ		 1401 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1402 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1403 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 u32 dpa_ctl;
1406
2bd2ad64
DV		 1407 assert_pipe_disabled(dev_priv,
1408 to_intel_crtc(crtc)->pipe);
1409
d240f20f 1410 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1411 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1412 "dp pll off, should be on\n");
1413 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1414
1415 /* We can't rely on the value tracked for the DP register in
1416 * intel_dp->DP because link_down must not change that (otherwise link
1417 * re-training will fail. */
298b0b39 1418 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1419 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1420 POSTING_READ(DP_A);
d240f20f
JB		 1421 udelay(200);
1422}
1423
c7ad3810 1424/* If the sink supports it, try to set the power state appropriately */
c19b0669 1425void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1426{
1427 int ret, i;
1428
1429 /* Should have a valid DPCD by this point */
1430 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1431 return;
1432
1433 if (mode != DRM_MODE_DPMS_ON) {
1434 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1435 DP_SET_POWER_D3);
1436 if (ret != 1)
1437 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1438 } else {
1439 /*
1440 * When turning on, we need to retry for 1ms to give the sink
1441 * time to wake up.
1442 */
1443 for (i = 0; i < 3; i++) {
1444 ret = intel_dp_aux_native_write_1(intel_dp,
1445 DP_SET_POWER,
1446 DP_SET_POWER_D0);
1447 if (ret == 1)
1448 break;
1449 msleep(1);
1450 }
1451 }
1452}
1453
19d8fe15
DV		 1454static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1455 enum pipe *pipe)
d240f20f 1456{
19d8fe15 1457 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1458 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1459 struct drm_device *dev = encoder->base.dev;
1460 struct drm_i915_private *dev_priv = dev->dev_private;
1461 u32 tmp = I915_READ(intel_dp->output_reg);
1462
1463 if (!(tmp & DP_PORT_EN))
1464 return false;
1465
bc7d38a4 1466 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1467 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1468 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1469 *pipe = PORT_TO_PIPE(tmp);
1470 } else {
1471 u32 trans_sel;
1472 u32 trans_dp;
1473 int i;
1474
1475 switch (intel_dp->output_reg) {
1476 case PCH_DP_B:
1477 trans_sel = TRANS_DP_PORT_SEL_B;
1478 break;
1479 case PCH_DP_C:
1480 trans_sel = TRANS_DP_PORT_SEL_C;
1481 break;
1482 case PCH_DP_D:
1483 trans_sel = TRANS_DP_PORT_SEL_D;
1484 break;
1485 default:
1486 return true;
1487 }
1488
1489 for_each_pipe(i) {
1490 trans_dp = I915_READ(TRANS_DP_CTL(i));
1491 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1492 *pipe = i;
1493 return true;
1494 }
1495 }
19d8fe15 1496
4a0833ec
DV		 1497 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1498 intel_dp->output_reg);
1499 }
d240f20f 1500
19d8fe15
DV		 1501 return true;
1502}
d240f20f 1503
045ac3b5
JB		 1504static void intel_dp_get_config(struct intel_encoder *encoder,
1505 struct intel_crtc_config *pipe_config)
1506{
1507 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1508 u32 tmp, flags = 0;
63000ef6
XZ		 1509 struct drm_device *dev = encoder->base.dev;
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511 enum port port = dp_to_dig_port(intel_dp)->port;
1512 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1513 int dotclock;
045ac3b5 1514
63000ef6
XZ		 1515 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1516 tmp = I915_READ(intel_dp->output_reg);
1517 if (tmp & DP_SYNC_HS_HIGH)
1518 flags |= DRM_MODE_FLAG_PHSYNC;
1519 else
1520 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1521
63000ef6
XZ		 1522 if (tmp & DP_SYNC_VS_HIGH)
1523 flags |= DRM_MODE_FLAG_PVSYNC;
1524 else
1525 flags |= DRM_MODE_FLAG_NVSYNC;
1526 } else {
1527 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1528 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1529 flags |= DRM_MODE_FLAG_PHSYNC;
1530 else
1531 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1532
63000ef6
XZ		 1533 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1534 flags |= DRM_MODE_FLAG_PVSYNC;
1535 else
1536 flags |= DRM_MODE_FLAG_NVSYNC;
1537 }
045ac3b5
JB		 1538
1539 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1540
eb14cb74
VS		 1541 pipe_config->has_dp_encoder = true;
1542
1543 intel_dp_get_m_n(crtc, pipe_config);
1544
18442d08 1545 if (port == PORT_A) {
f1f644dc
JB		 1546 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1547 pipe_config->port_clock = 162000;
1548 else
1549 pipe_config->port_clock = 270000;
1550 }
18442d08
VS		 1551
1552 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1553 &pipe_config->dp_m_n);
1554
1555 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1556 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1557
241bfc38 1558 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1559
c6cd2ee2
JN		 1560 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1561 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1562 /*
1563 * This is a big fat ugly hack.
1564 *
1565 * Some machines in UEFI boot mode provide us a VBT that has 18
1566 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1567 * unknown we fail to light up. Yet the same BIOS boots up with
1568 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1569 * max, not what it tells us to use.
1570 *
1571 * Note: This will still be broken if the eDP panel is not lit
1572 * up by the BIOS, and thus we can't get the mode at module
1573 * load.
1574 */
1575 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1576 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1577 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1578 }
045ac3b5
JB		 1579}
1580
a031d709 1581static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1582{
a031d709
RV		 1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585 return dev_priv->psr.sink_support;
2293bb5c
SK		 1586}
1587
2b28bb1b
RV		 1588static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1589{
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
18b5992c 1592 if (!HAS_PSR(dev))
2b28bb1b
RV		 1593 return false;
1594
18b5992c 1595 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1596}
1597
1598static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1599 struct edp_vsc_psr *vsc_psr)
1600{
1601 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1602 struct drm_device *dev = dig_port->base.base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1605 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1606 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1607 uint32_t *data = (uint32_t *) vsc_psr;
1608 unsigned int i;
1609
1610 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1611 the video DIP being updated before program video DIP data buffer
1612 registers for DIP being updated. */
1613 I915_WRITE(ctl_reg, 0);
1614 POSTING_READ(ctl_reg);
1615
1616 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1617 if (i < sizeof(struct edp_vsc_psr))
1618 I915_WRITE(data_reg + i, *data++);
1619 else
1620 I915_WRITE(data_reg + i, 0);
1621 }
1622
1623 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1624 POSTING_READ(ctl_reg);
1625}
1626
1627static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1628{
1629 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 struct edp_vsc_psr psr_vsc;
1632
1633 if (intel_dp->psr_setup_done)
1634 return;
1635
1636 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1637 memset(&psr_vsc, 0, sizeof(psr_vsc));
1638 psr_vsc.sdp_header.HB0 = 0;
1639 psr_vsc.sdp_header.HB1 = 0x7;
1640 psr_vsc.sdp_header.HB2 = 0x2;
1641 psr_vsc.sdp_header.HB3 = 0x8;
1642 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1643
1644 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1645 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1646 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1647
1648 intel_dp->psr_setup_done = true;
1649}
1650
1651static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1652{
1653 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1654 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1655 uint32_t aux_clock_divider;
2b28bb1b
RV		 1656 int precharge = 0x3;
1657 int msg_size = 5; /* Header(4) + Message(1) */
1658
ec5b01dd
DL		 1659 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1660
2b28bb1b
RV		 1661 /* Enable PSR in sink */
1662 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1663 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1664 DP_PSR_ENABLE &
1665 ~DP_PSR_MAIN_LINK_ACTIVE);
1666 else
1667 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1668 DP_PSR_ENABLE |
1669 DP_PSR_MAIN_LINK_ACTIVE);
1670
1671 /* Setup AUX registers */
18b5992c
BW		 1672 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1673 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1674 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1675 DP_AUX_CH_CTL_TIME_OUT_400us |
1676 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1677 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1678 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1679}
1680
1681static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1682{
1683 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 uint32_t max_sleep_time = 0x1f;
1686 uint32_t idle_frames = 1;
1687 uint32_t val = 0x0;
ed8546ac 1688 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1689
1690 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1691 val |= EDP_PSR_LINK_STANDBY;
1692 val |= EDP_PSR_TP2_TP3_TIME_0us;
1693 val |= EDP_PSR_TP1_TIME_0us;
1694 val |= EDP_PSR_SKIP_AUX_EXIT;
1695 } else
1696 val |= EDP_PSR_LINK_DISABLE;
1697
18b5992c 1698 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1699 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1700 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1701 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1702 EDP_PSR_ENABLE);
1703}
1704
3f51e471
RV		 1705static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1706{
1707 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1708 struct drm_device *dev = dig_port->base.base.dev;
1709 struct drm_i915_private *dev_priv = dev->dev_private;
1710 struct drm_crtc *crtc = dig_port->base.base.crtc;
1711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1712 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1713 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1714
a031d709
RV		 1715 dev_priv->psr.source_ok = false;
1716
18b5992c 1717 if (!HAS_PSR(dev)) {
3f51e471 1718 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1719 return false;
1720 }
1721
1722 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1723 (dig_port->port != PORT_A)) {
1724 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1725 return false;
1726 }
1727
d330a953 1728 if (!i915.enable_psr) {
105b7c11 1729 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1730 return false;
1731 }
1732
cd234b0b
CW		 1733 crtc = dig_port->base.base.crtc;
1734 if (crtc == NULL) {
1735 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1736 return false;
1737 }
1738
1739 intel_crtc = to_intel_crtc(crtc);
20ddf665 1740 if (!intel_crtc_active(crtc)) {
3f51e471 1741 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1742 return false;
1743 }
1744
cd234b0b 1745 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1746 if (obj->tiling_mode != I915_TILING_X ||
1747 obj->fence_reg == I915_FENCE_REG_NONE) {
1748 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1749 return false;
1750 }
1751
1752 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1753 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1754 return false;
1755 }
1756
1757 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1758 S3D_ENABLE) {
1759 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1760 return false;
1761 }
1762
ca73b4f0 1763 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1764 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1765 return false;
1766 }
1767
a031d709 1768 dev_priv->psr.source_ok = true;
3f51e471
RV		 1769 return true;
1770}
1771
3d739d92 1772static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1773{
1774 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1775
3f51e471
RV		 1776 if (!intel_edp_psr_match_conditions(intel_dp) ||
1777 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1778 return;
1779
1780 /* Setup PSR once */
1781 intel_edp_psr_setup(intel_dp);
1782
1783 /* Enable PSR on the panel */
1784 intel_edp_psr_enable_sink(intel_dp);
1785
1786 /* Enable PSR on the host */
1787 intel_edp_psr_enable_source(intel_dp);
1788}
1789
3d739d92
RV		 1790void intel_edp_psr_enable(struct intel_dp *intel_dp)
1791{
1792 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1793
1794 if (intel_edp_psr_match_conditions(intel_dp) &&
1795 !intel_edp_is_psr_enabled(dev))
1796 intel_edp_psr_do_enable(intel_dp);
1797}
1798
2b28bb1b
RV		 1799void intel_edp_psr_disable(struct intel_dp *intel_dp)
1800{
1801 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803
1804 if (!intel_edp_is_psr_enabled(dev))
1805 return;
1806
18b5992c
BW		 1807 I915_WRITE(EDP_PSR_CTL(dev),
1808 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1809
1810 /* Wait till PSR is idle */
18b5992c 1811 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1812 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1813 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1814}
1815
3d739d92
RV		 1816void intel_edp_psr_update(struct drm_device *dev)
1817{
1818 struct intel_encoder *encoder;
1819 struct intel_dp *intel_dp = NULL;
1820
1821 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1822 if (encoder->type == INTEL_OUTPUT_EDP) {
1823 intel_dp = enc_to_intel_dp(&encoder->base);
1824
a031d709 1825 if (!is_edp_psr(dev))
3d739d92
RV		 1826 return;
1827
1828 if (!intel_edp_psr_match_conditions(intel_dp))
1829 intel_edp_psr_disable(intel_dp);
1830 else
1831 if (!intel_edp_is_psr_enabled(dev))
1832 intel_edp_psr_do_enable(intel_dp);
1833 }
1834}
1835
e8cb4558 1836static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1837{
e8cb4558 1838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1839 enum port port = dp_to_dig_port(intel_dp)->port;
1840 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1841
1842 /* Make sure the panel is off before trying to change the mode. But also
1843 * ensure that we have vdd while we switch off the panel. */
4be73780 1844 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1845 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1846 intel_edp_panel_off(intel_dp);
3739850b
DV		 1847
1848 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1849 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1850 intel_dp_link_down(intel_dp);
d240f20f
JB		 1851}
1852
2bd2ad64 1853static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1854{
2bd2ad64 1855 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1856 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1857 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1858
982a3866 1859 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1860 intel_dp_link_down(intel_dp);
b2634017
JB		 1861 if (!IS_VALLEYVIEW(dev))
1862 ironlake_edp_pll_off(intel_dp);
3739850b 1863 }
2bd2ad64
DV		 1864}
1865
e8cb4558 1866static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1867{
e8cb4558
DV		 1868 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1869 struct drm_device *dev = encoder->base.dev;
1870 struct drm_i915_private *dev_priv = dev->dev_private;
1871 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1872
0c33d8d7
DV		 1873 if (WARN_ON(dp_reg & DP_PORT_EN))
1874 return;
5d613501 1875
4be73780 1876 edp_panel_vdd_on(intel_dp);
f01eca2e 1877 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1878 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1879 intel_edp_panel_on(intel_dp);
1880 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1881 intel_dp_complete_link_train(intel_dp);
3ab9c637 1882 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1883}
89b667f8 1884
ecff4f3b
JN		 1885static void g4x_enable_dp(struct intel_encoder *encoder)
1886{
828f5c6e
JN		 1887 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1888
ecff4f3b 1889 intel_enable_dp(encoder);
4be73780 1890 intel_edp_backlight_on(intel_dp);
ab1f90f9 1891}
89b667f8 1892
ab1f90f9
JN		 1893static void vlv_enable_dp(struct intel_encoder *encoder)
1894{
828f5c6e
JN		 1895 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1896
4be73780 1897 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1898}
1899
ecff4f3b 1900static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1901{
1902 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1903 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1904
1905 if (dport->port == PORT_A)
1906 ironlake_edp_pll_on(intel_dp);
1907}
1908
1909static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1910{
2bd2ad64 1911 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1912 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1913 struct drm_device *dev = encoder->base.dev;
89b667f8 1914 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1915 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1916 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1917 int pipe = intel_crtc->pipe;
bf13e81b 1918 struct edp_power_seq power_seq;
ab1f90f9 1919 u32 val;
a4fc5ed6 1920
ab1f90f9 1921 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1922
ab3c759a 1923 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1924 val = 0;
1925 if (pipe)
1926 val |= (1<<21);
1927 else
1928 val &= ~(1<<21);
1929 val |= 0x001000c4;
ab3c759a
CML		 1930 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1931 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1932 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1933
ab1f90f9
JN		 1934 mutex_unlock(&dev_priv->dpio_lock);
1935
bf13e81b
JN		 1936 /* init power sequencer on this pipe and port */
1937 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1938 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1939 &power_seq);
1940
ab1f90f9
JN		 1941 intel_enable_dp(encoder);
1942
e4607fcf 1943 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1944}
1945
ecff4f3b 1946static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1947{
1948 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1949 struct drm_device *dev = encoder->base.dev;
1950 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1951 struct intel_crtc *intel_crtc =
1952 to_intel_crtc(encoder->base.crtc);
e4607fcf 1953 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1954 int pipe = intel_crtc->pipe;
89b667f8 1955
89b667f8 1956 /* Program Tx lane resets to default */
0980a60f 1957 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1958 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1959 DPIO_PCS_TX_LANE2_RESET |
1960 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1961 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1962 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1963 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1964 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1965 DPIO_PCS_CLK_SOFT_RESET);
1966
1967 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1968 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1969 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1970 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1971 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1972}
1973
1974/*
df0c237d
JB		 1975 * Native read with retry for link status and receiver capability reads for
1976 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1977 */
1978static bool
df0c237d
JB		 1979intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1980 uint8_t *recv, int recv_bytes)
a4fc5ed6 1981{
61da5fab
JB		 1982 int ret, i;
1983
df0c237d
JB		 1984 /*
1985 * Sinks are *supposed* to come up within 1ms from an off state,
1986 * but we're also supposed to retry 3 times per the spec.
1987 */
61da5fab 1988 for (i = 0; i < 3; i++) {
df0c237d
JB		 1989 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1990 recv_bytes);
1991 if (ret == recv_bytes)
61da5fab
JB		 1992 return true;
1993 msleep(1);
1994 }
a4fc5ed6 1995
61da5fab 1996 return false;
a4fc5ed6
KP		 1997}
1998
1999/*
2000 * Fetch AUX CH registers 0x202 - 0x207 which contain
2001 * link status information
2002 */
2003static bool
93f62dad 2004intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2005{
df0c237d
JB		 2006 return intel_dp_aux_native_read_retry(intel_dp,
2007 DP_LANE0_1_STATUS,
93f62dad 2008 link_status,
df0c237d 2009 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 2010}
2011
a4fc5ed6
KP		 2012/*
2013 * These are source-specific values; current Intel hardware supports
2014 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2015 */
a4fc5ed6
KP		 2016
2017static uint8_t
1a2eb460 2018intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2019{
30add22d 2020 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2021 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2022
8f93f4f1 2023 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2024 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2025 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2026 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2027 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2028 return DP_TRAIN_VOLTAGE_SWING_1200;
2029 else
2030 return DP_TRAIN_VOLTAGE_SWING_800;
2031}
2032
2033static uint8_t
2034intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2035{
30add22d 2036 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2037 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2038
8f93f4f1
PZ		 2039 if (IS_BROADWELL(dev)) {
2040 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2041 case DP_TRAIN_VOLTAGE_SWING_400:
2042 case DP_TRAIN_VOLTAGE_SWING_600:
2043 return DP_TRAIN_PRE_EMPHASIS_6;
2044 case DP_TRAIN_VOLTAGE_SWING_800:
2045 return DP_TRAIN_PRE_EMPHASIS_3_5;
2046 case DP_TRAIN_VOLTAGE_SWING_1200:
2047 default:
2048 return DP_TRAIN_PRE_EMPHASIS_0;
2049 }
2050 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2051 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2052 case DP_TRAIN_VOLTAGE_SWING_400:
2053 return DP_TRAIN_PRE_EMPHASIS_9_5;
2054 case DP_TRAIN_VOLTAGE_SWING_600:
2055 return DP_TRAIN_PRE_EMPHASIS_6;
2056 case DP_TRAIN_VOLTAGE_SWING_800:
2057 return DP_TRAIN_PRE_EMPHASIS_3_5;
2058 case DP_TRAIN_VOLTAGE_SWING_1200:
2059 default:
2060 return DP_TRAIN_PRE_EMPHASIS_0;
2061 }
e2fa6fba
P		 2062 } else if (IS_VALLEYVIEW(dev)) {
2063 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2064 case DP_TRAIN_VOLTAGE_SWING_400:
2065 return DP_TRAIN_PRE_EMPHASIS_9_5;
2066 case DP_TRAIN_VOLTAGE_SWING_600:
2067 return DP_TRAIN_PRE_EMPHASIS_6;
2068 case DP_TRAIN_VOLTAGE_SWING_800:
2069 return DP_TRAIN_PRE_EMPHASIS_3_5;
2070 case DP_TRAIN_VOLTAGE_SWING_1200:
2071 default:
2072 return DP_TRAIN_PRE_EMPHASIS_0;
2073 }
bc7d38a4 2074 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2075 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2076 case DP_TRAIN_VOLTAGE_SWING_400:
2077 return DP_TRAIN_PRE_EMPHASIS_6;
2078 case DP_TRAIN_VOLTAGE_SWING_600:
2079 case DP_TRAIN_VOLTAGE_SWING_800:
2080 return DP_TRAIN_PRE_EMPHASIS_3_5;
2081 default:
2082 return DP_TRAIN_PRE_EMPHASIS_0;
2083 }
2084 } else {
2085 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2086 case DP_TRAIN_VOLTAGE_SWING_400:
2087 return DP_TRAIN_PRE_EMPHASIS_6;
2088 case DP_TRAIN_VOLTAGE_SWING_600:
2089 return DP_TRAIN_PRE_EMPHASIS_6;
2090 case DP_TRAIN_VOLTAGE_SWING_800:
2091 return DP_TRAIN_PRE_EMPHASIS_3_5;
2092 case DP_TRAIN_VOLTAGE_SWING_1200:
2093 default:
2094 return DP_TRAIN_PRE_EMPHASIS_0;
2095 }
a4fc5ed6
KP		 2096 }
2097}
2098
e2fa6fba
P		 2099static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2100{
2101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2102 struct drm_i915_private *dev_priv = dev->dev_private;
2103 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2104 struct intel_crtc *intel_crtc =
2105 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2106 unsigned long demph_reg_value, preemph_reg_value,
2107 uniqtranscale_reg_value;
2108 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2109 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2110 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2111
2112 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2113 case DP_TRAIN_PRE_EMPHASIS_0:
2114 preemph_reg_value = 0x0004000;
2115 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2116 case DP_TRAIN_VOLTAGE_SWING_400:
2117 demph_reg_value = 0x2B405555;
2118 uniqtranscale_reg_value = 0x552AB83A;
2119 break;
2120 case DP_TRAIN_VOLTAGE_SWING_600:
2121 demph_reg_value = 0x2B404040;
2122 uniqtranscale_reg_value = 0x5548B83A;
2123 break;
2124 case DP_TRAIN_VOLTAGE_SWING_800:
2125 demph_reg_value = 0x2B245555;
2126 uniqtranscale_reg_value = 0x5560B83A;
2127 break;
2128 case DP_TRAIN_VOLTAGE_SWING_1200:
2129 demph_reg_value = 0x2B405555;
2130 uniqtranscale_reg_value = 0x5598DA3A;
2131 break;
2132 default:
2133 return 0;
2134 }
2135 break;
2136 case DP_TRAIN_PRE_EMPHASIS_3_5:
2137 preemph_reg_value = 0x0002000;
2138 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2139 case DP_TRAIN_VOLTAGE_SWING_400:
2140 demph_reg_value = 0x2B404040;
2141 uniqtranscale_reg_value = 0x5552B83A;
2142 break;
2143 case DP_TRAIN_VOLTAGE_SWING_600:
2144 demph_reg_value = 0x2B404848;
2145 uniqtranscale_reg_value = 0x5580B83A;
2146 break;
2147 case DP_TRAIN_VOLTAGE_SWING_800:
2148 demph_reg_value = 0x2B404040;
2149 uniqtranscale_reg_value = 0x55ADDA3A;
2150 break;
2151 default:
2152 return 0;
2153 }
2154 break;
2155 case DP_TRAIN_PRE_EMPHASIS_6:
2156 preemph_reg_value = 0x0000000;
2157 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2158 case DP_TRAIN_VOLTAGE_SWING_400:
2159 demph_reg_value = 0x2B305555;
2160 uniqtranscale_reg_value = 0x5570B83A;
2161 break;
2162 case DP_TRAIN_VOLTAGE_SWING_600:
2163 demph_reg_value = 0x2B2B4040;
2164 uniqtranscale_reg_value = 0x55ADDA3A;
2165 break;
2166 default:
2167 return 0;
2168 }
2169 break;
2170 case DP_TRAIN_PRE_EMPHASIS_9_5:
2171 preemph_reg_value = 0x0006000;
2172 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2173 case DP_TRAIN_VOLTAGE_SWING_400:
2174 demph_reg_value = 0x1B405555;
2175 uniqtranscale_reg_value = 0x55ADDA3A;
2176 break;
2177 default:
2178 return 0;
2179 }
2180 break;
2181 default:
2182 return 0;
2183 }
2184
0980a60f 2185 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2186 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2187 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2188 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2189 uniqtranscale_reg_value);
ab3c759a
CML		 2190 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2191 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2192 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2193 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2194 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2195
2196 return 0;
2197}
2198
a4fc5ed6 2199static void
0301b3ac
JN		 2200intel_get_adjust_train(struct intel_dp *intel_dp,
2201 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2202{
2203 uint8_t v = 0;
2204 uint8_t p = 0;
2205 int lane;
1a2eb460
KP		 2206 uint8_t voltage_max;
2207 uint8_t preemph_max;
a4fc5ed6 2208
33a34e4e 2209 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2210 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2211 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2212
2213 if (this_v > v)
2214 v = this_v;
2215 if (this_p > p)
2216 p = this_p;
2217 }
2218
1a2eb460 2219 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2220 if (v >= voltage_max)
2221 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2222
1a2eb460
KP		 2223 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2224 if (p >= preemph_max)
2225 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2226
2227 for (lane = 0; lane < 4; lane++)
33a34e4e 2228 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2229}
2230
2231static uint32_t
f0a3424e 2232intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2233{
3cf2efb1 2234 uint32_t signal_levels = 0;
a4fc5ed6 2235
3cf2efb1 2236 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2237 case DP_TRAIN_VOLTAGE_SWING_400:
2238 default:
2239 signal_levels |= DP_VOLTAGE_0_4;
2240 break;
2241 case DP_TRAIN_VOLTAGE_SWING_600:
2242 signal_levels |= DP_VOLTAGE_0_6;
2243 break;
2244 case DP_TRAIN_VOLTAGE_SWING_800:
2245 signal_levels |= DP_VOLTAGE_0_8;
2246 break;
2247 case DP_TRAIN_VOLTAGE_SWING_1200:
2248 signal_levels |= DP_VOLTAGE_1_2;
2249 break;
2250 }
3cf2efb1 2251 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2252 case DP_TRAIN_PRE_EMPHASIS_0:
2253 default:
2254 signal_levels |= DP_PRE_EMPHASIS_0;
2255 break;
2256 case DP_TRAIN_PRE_EMPHASIS_3_5:
2257 signal_levels |= DP_PRE_EMPHASIS_3_5;
2258 break;
2259 case DP_TRAIN_PRE_EMPHASIS_6:
2260 signal_levels |= DP_PRE_EMPHASIS_6;
2261 break;
2262 case DP_TRAIN_PRE_EMPHASIS_9_5:
2263 signal_levels |= DP_PRE_EMPHASIS_9_5;
2264 break;
2265 }
2266 return signal_levels;
2267}
2268
e3421a18
ZW		 2269/* Gen6's DP voltage swing and pre-emphasis control */
2270static uint32_t
2271intel_gen6_edp_signal_levels(uint8_t train_set)
2272{
3c5a62b5
YL		 2273 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2274 DP_TRAIN_PRE_EMPHASIS_MASK);
2275 switch (signal_levels) {
e3421a18 2276 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2277 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2278 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2279 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2280 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2281 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2282 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2283 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2284 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2285 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2286 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2287 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2288 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2289 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2290 default:
3c5a62b5
YL		 2291 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2292 "0x%x\n", signal_levels);
2293 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2294 }
2295}
2296
1a2eb460
KP		 2297/* Gen7's DP voltage swing and pre-emphasis control */
2298static uint32_t
2299intel_gen7_edp_signal_levels(uint8_t train_set)
2300{
2301 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2302 DP_TRAIN_PRE_EMPHASIS_MASK);
2303 switch (signal_levels) {
2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2305 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2306 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2307 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2308 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2309 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2310
2311 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2312 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2313 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2314 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2315
2316 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2317 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2318 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2319 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2320
2321 default:
2322 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2323 "0x%x\n", signal_levels);
2324 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2325 }
2326}
2327
d6c0d722
PZ		 2328/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2329static uint32_t
f0a3424e 2330intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2331{
d6c0d722
PZ		 2332 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2333 DP_TRAIN_PRE_EMPHASIS_MASK);
2334 switch (signal_levels) {
2335 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2336 return DDI_BUF_EMP_400MV_0DB_HSW;
2337 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2338 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2339 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2340 return DDI_BUF_EMP_400MV_6DB_HSW;
2341 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2342 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2343
d6c0d722
PZ		 2344 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2345 return DDI_BUF_EMP_600MV_0DB_HSW;
2346 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2347 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2348 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2349 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2350
d6c0d722
PZ		 2351 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2352 return DDI_BUF_EMP_800MV_0DB_HSW;
2353 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2354 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2355 default:
2356 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2357 "0x%x\n", signal_levels);
2358 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2359 }
a4fc5ed6
KP		 2360}
2361
8f93f4f1
PZ		 2362static uint32_t
2363intel_bdw_signal_levels(uint8_t train_set)
2364{
2365 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2366 DP_TRAIN_PRE_EMPHASIS_MASK);
2367 switch (signal_levels) {
2368 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2369 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2370 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2371 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2372 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2373 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2374
2375 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2376 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2377 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2378 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2379 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2380 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2381
2382 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2383 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2384 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2385 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2386
2387 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2388 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2389
2390 default:
2391 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2392 "0x%x\n", signal_levels);
2393 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2394 }
2395}
2396
f0a3424e
PZ		 2397/* Properly updates "DP" with the correct signal levels. */
2398static void
2399intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2400{
2401 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2402 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2403 struct drm_device *dev = intel_dig_port->base.base.dev;
2404 uint32_t signal_levels, mask;
2405 uint8_t train_set = intel_dp->train_set[0];
2406
8f93f4f1
PZ		 2407 if (IS_BROADWELL(dev)) {
2408 signal_levels = intel_bdw_signal_levels(train_set);
2409 mask = DDI_BUF_EMP_MASK;
2410 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2411 signal_levels = intel_hsw_signal_levels(train_set);
2412 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2413 } else if (IS_VALLEYVIEW(dev)) {
2414 signal_levels = intel_vlv_signal_levels(intel_dp);
2415 mask = 0;
bc7d38a4 2416 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2417 signal_levels = intel_gen7_edp_signal_levels(train_set);
2418 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2419 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2420 signal_levels = intel_gen6_edp_signal_levels(train_set);
2421 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2422 } else {
2423 signal_levels = intel_gen4_signal_levels(train_set);
2424 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2425 }
2426
2427 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2428
2429 *DP = (*DP & ~mask) | signal_levels;
2430}
2431
a4fc5ed6 2432static bool
ea5b213a 2433intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2434 uint32_t *DP,
58e10eb9 2435 uint8_t dp_train_pat)
a4fc5ed6 2436{
174edf1f
PZ		 2437 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2438 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2439 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2440 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2441 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2442 int ret, len;
a4fc5ed6 2443
22b8bf17 2444 if (HAS_DDI(dev)) {
3ab9c637 2445 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2446
2447 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2448 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2449 else
2450 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2451
2452 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2453 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2454 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2455 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2456
2457 break;
2458 case DP_TRAINING_PATTERN_1:
2459 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2460 break;
2461 case DP_TRAINING_PATTERN_2:
2462 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2463 break;
2464 case DP_TRAINING_PATTERN_3:
2465 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2466 break;
2467 }
174edf1f 2468 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2469
bc7d38a4 2470 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2471 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2472
2473 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2474 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2475 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2476 break;
2477 case DP_TRAINING_PATTERN_1:
70aff66c 2478 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2479 break;
2480 case DP_TRAINING_PATTERN_2:
70aff66c 2481 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2482 break;
2483 case DP_TRAINING_PATTERN_3:
2484 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2485 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2486 break;
2487 }
2488
2489 } else {
70aff66c 2490 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2491
2492 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2493 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2494 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2495 break;
2496 case DP_TRAINING_PATTERN_1:
70aff66c 2497 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2498 break;
2499 case DP_TRAINING_PATTERN_2:
70aff66c 2500 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2501 break;
2502 case DP_TRAINING_PATTERN_3:
2503 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2504 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2505 break;
2506 }
2507 }
2508
70aff66c 2509 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2510 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2511
2cdfe6c8
JN		 2512 buf[0] = dp_train_pat;
2513 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2514 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2515 /* don't write DP_TRAINING_LANEx_SET on disable */
2516 len = 1;
2517 } else {
2518 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2519 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2520 len = intel_dp->lane_count + 1;
47ea7542 2521 }
a4fc5ed6 2522
2cdfe6c8
JN		 2523 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2524 buf, len);
2525
2526 return ret == len;
a4fc5ed6
KP		 2527}
2528
70aff66c
JN		 2529static bool
2530intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2531 uint8_t dp_train_pat)
2532{
953d22e8 2533 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2534 intel_dp_set_signal_levels(intel_dp, DP);
2535 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2536}
2537
2538static bool
2539intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2540 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2541{
2542 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2543 struct drm_device *dev = intel_dig_port->base.base.dev;
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 int ret;
2546
2547 intel_get_adjust_train(intel_dp, link_status);
2548 intel_dp_set_signal_levels(intel_dp, DP);
2549
2550 I915_WRITE(intel_dp->output_reg, *DP);
2551 POSTING_READ(intel_dp->output_reg);
2552
2553 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2554 intel_dp->train_set,
2555 intel_dp->lane_count);
2556
2557 return ret == intel_dp->lane_count;
2558}
2559
3ab9c637
ID		 2560static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2561{
2562 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2563 struct drm_device *dev = intel_dig_port->base.base.dev;
2564 struct drm_i915_private *dev_priv = dev->dev_private;
2565 enum port port = intel_dig_port->port;
2566 uint32_t val;
2567
2568 if (!HAS_DDI(dev))
2569 return;
2570
2571 val = I915_READ(DP_TP_CTL(port));
2572 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2573 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2574 I915_WRITE(DP_TP_CTL(port), val);
2575
2576 /*
2577 * On PORT_A we can have only eDP in SST mode. There the only reason
2578 * we need to set idle transmission mode is to work around a HW issue
2579 * where we enable the pipe while not in idle link-training mode.
2580 * In this case there is requirement to wait for a minimum number of
2581 * idle patterns to be sent.
2582 */
2583 if (port == PORT_A)
2584 return;
2585
2586 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2587 1))
2588 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2589}
2590
33a34e4e 2591/* Enable corresponding port and start training pattern 1 */
c19b0669 2592void
33a34e4e 2593intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2594{
da63a9f2 2595 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2596 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2597 int i;
2598 uint8_t voltage;
cdb0e95b 2599 int voltage_tries, loop_tries;
ea5b213a 2600 uint32_t DP = intel_dp->DP;
6aba5b6c 2601 uint8_t link_config[2];
a4fc5ed6 2602
affa9354 2603 if (HAS_DDI(dev))
c19b0669
PZ		 2604 intel_ddi_prepare_link_retrain(encoder);
2605
3cf2efb1 2606 /* Write the link configuration data */
6aba5b6c
JN		 2607 link_config[0] = intel_dp->link_bw;
2608 link_config[1] = intel_dp->lane_count;
2609 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2610 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2611 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2612
2613 link_config[0] = 0;
2614 link_config[1] = DP_SET_ANSI_8B10B;
2615 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2616
2617 DP |= DP_PORT_EN;
1a2eb460 2618
70aff66c
JN		 2619 /* clock recovery */
2620 if (!intel_dp_reset_link_train(intel_dp, &DP,
2621 DP_TRAINING_PATTERN_1 |
2622 DP_LINK_SCRAMBLING_DISABLE)) {
2623 DRM_ERROR("failed to enable link training\n");
2624 return;
2625 }
2626
a4fc5ed6 2627 voltage = 0xff;
cdb0e95b
KP		 2628 voltage_tries = 0;
2629 loop_tries = 0;
a4fc5ed6 2630 for (;;) {
70aff66c 2631 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2632
a7c9655f 2633 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2634 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2635 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2636 break;
93f62dad 2637 }
a4fc5ed6 2638
01916270 2639 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2640 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2641 break;
2642 }
2643
2644 /* Check to see if we've tried the max voltage */
2645 for (i = 0; i < intel_dp->lane_count; i++)
2646 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2647 break;
3b4f819d 2648 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2649 ++loop_tries;
2650 if (loop_tries == 5) {
3def84b3 2651 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2652 break;
2653 }
70aff66c
JN		 2654 intel_dp_reset_link_train(intel_dp, &DP,
2655 DP_TRAINING_PATTERN_1 |
2656 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2657 voltage_tries = 0;
2658 continue;
2659 }
a4fc5ed6 2660
3cf2efb1 2661 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2662 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2663 ++voltage_tries;
b06fbda3 2664 if (voltage_tries == 5) {
3def84b3 2665 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2666 break;
2667 }
2668 } else
2669 voltage_tries = 0;
2670 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2671
70aff66c
JN		 2672 /* Update training set as requested by target */
2673 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2674 DRM_ERROR("failed to update link training\n");
2675 break;
2676 }
a4fc5ed6
KP		 2677 }
2678
33a34e4e
JB		 2679 intel_dp->DP = DP;
2680}
2681
c19b0669 2682void
33a34e4e
JB		 2683intel_dp_complete_link_train(struct intel_dp *intel_dp)
2684{
33a34e4e 2685 bool channel_eq = false;
37f80975 2686 int tries, cr_tries;
33a34e4e 2687 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2688 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2689
2690 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2691 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2692 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2693
a4fc5ed6 2694 /* channel equalization */
70aff66c 2695 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2696 training_pattern |
70aff66c
JN		 2697 DP_LINK_SCRAMBLING_DISABLE)) {
2698 DRM_ERROR("failed to start channel equalization\n");
2699 return;
2700 }
2701
a4fc5ed6 2702 tries = 0;
37f80975 2703 cr_tries = 0;
a4fc5ed6
KP		 2704 channel_eq = false;
2705 for (;;) {
70aff66c 2706 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2707
37f80975
JB		 2708 if (cr_tries > 5) {
2709 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2710 break;
2711 }
2712
a7c9655f 2713 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2714 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2715 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2716 break;
70aff66c 2717 }
a4fc5ed6 2718
37f80975 2719 /* Make sure clock is still ok */
01916270 2720 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2721 intel_dp_start_link_train(intel_dp);
70aff66c 2722 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2723 training_pattern |
70aff66c 2724 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2725 cr_tries++;
2726 continue;
2727 }
2728
1ffdff13 2729 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2730 channel_eq = true;
2731 break;
2732 }
a4fc5ed6 2733
37f80975
JB		 2734 /* Try 5 times, then try clock recovery if that fails */
2735 if (tries > 5) {
2736 intel_dp_link_down(intel_dp);
2737 intel_dp_start_link_train(intel_dp);
70aff66c 2738 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2739 training_pattern |
70aff66c 2740 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2741 tries = 0;
2742 cr_tries++;
2743 continue;
2744 }
a4fc5ed6 2745
70aff66c
JN		 2746 /* Update training set as requested by target */
2747 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2748 DRM_ERROR("failed to update link training\n");
2749 break;
2750 }
3cf2efb1 2751 ++tries;
869184a6 2752 }
3cf2efb1 2753
3ab9c637
ID		 2754 intel_dp_set_idle_link_train(intel_dp);
2755
2756 intel_dp->DP = DP;
2757
d6c0d722 2758 if (channel_eq)
07f42258 2759 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2760
3ab9c637
ID		 2761}
2762
2763void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2764{
70aff66c 2765 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2766 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2767}
2768
2769static void
ea5b213a 2770intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2771{
da63a9f2 2772 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2773 enum port port = intel_dig_port->port;
da63a9f2 2774 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2775 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2776 struct intel_crtc *intel_crtc =
2777 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2778 uint32_t DP = intel_dp->DP;
a4fc5ed6 2779
c19b0669
PZ		 2780 /*
2781 * DDI code has a strict mode set sequence and we should try to respect
2782 * it, otherwise we might hang the machine in many different ways. So we
2783 * really should be disabling the port only on a complete crtc_disable
2784 * sequence. This function is just called under two conditions on DDI
2785 * code:
2786 * - Link train failed while doing crtc_enable, and on this case we
2787 * really should respect the mode set sequence and wait for a
2788 * crtc_disable.
2789 * - Someone turned the monitor off and intel_dp_check_link_status
2790 * called us. We don't need to disable the whole port on this case, so
2791 * when someone turns the monitor on again,
2792 * intel_ddi_prepare_link_retrain will take care of redoing the link
2793 * train.
2794 */
affa9354 2795 if (HAS_DDI(dev))
c19b0669
PZ		 2796 return;
2797
0c33d8d7 2798 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2799 return;
2800
28c97730 2801 DRM_DEBUG_KMS("\n");
32f9d658 2802
bc7d38a4 2803 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2804 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2805 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2806 } else {
2807 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2808 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2809 }
fe255d00 2810 POSTING_READ(intel_dp->output_reg);
5eb08b69 2811
ab527efc
DV		 2812 /* We don't really know why we're doing this */
2813 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2814
493a7081 2815 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2816 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2817 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2818
5bddd17f
EA		 2819 /* Hardware workaround: leaving our transcoder select
2820 * set to transcoder B while it's off will prevent the
2821 * corresponding HDMI output on transcoder A.
2822 *
2823 * Combine this with another hardware workaround:
2824 * transcoder select bit can only be cleared while the
2825 * port is enabled.
2826 */
2827 DP &= ~DP_PIPEB_SELECT;
2828 I915_WRITE(intel_dp->output_reg, DP);
2829
2830 /* Changes to enable or select take place the vblank
2831 * after being written.
2832 */
ff50afe9
DV		 2833 if (WARN_ON(crtc == NULL)) {
2834 /* We should never try to disable a port without a crtc
2835 * attached. For paranoia keep the code around for a
2836 * bit. */
31acbcc4
CW		 2837 POSTING_READ(intel_dp->output_reg);
2838 msleep(50);
2839 } else
ab527efc 2840 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2841 }
2842
832afda6 2843 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2844 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2845 POSTING_READ(intel_dp->output_reg);
f01eca2e 2846 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2847}
2848
26d61aad
KP		 2849static bool
2850intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2851{
a031d709
RV		 2852 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2853 struct drm_device *dev = dig_port->base.base.dev;
2854 struct drm_i915_private *dev_priv = dev->dev_private;
2855
577c7a50
DL		 2856 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2857
92fd8fd1 2858 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2859 sizeof(intel_dp->dpcd)) == 0)
2860 return false; /* aux transfer failed */
92fd8fd1 2861
577c7a50
DL		 2862 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2863 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2864 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2865
edb39244
AJ		 2866 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2867 return false; /* DPCD not present */
2868
2293bb5c
SK		 2869 /* Check if the panel supports PSR */
2870 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2871 if (is_edp(intel_dp)) {
2872 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2873 intel_dp->psr_dpcd,
2874 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2875 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2876 dev_priv->psr.sink_support = true;
50003939 2877 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2878 }
50003939
JN		 2879 }
2880
06ea66b6
TP		 2881 /* Training Pattern 3 support */
2882 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2883 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2884 intel_dp->use_tps3 = true;
2885 DRM_DEBUG_KMS("Displayport TPS3 supported");
2886 } else
2887 intel_dp->use_tps3 = false;
2888
edb39244
AJ		 2889 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2890 DP_DWN_STRM_PORT_PRESENT))
2891 return true; /* native DP sink */
2892
2893 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2894 return true; /* no per-port downstream info */
2895
2896 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2897 intel_dp->downstream_ports,
2898 DP_MAX_DOWNSTREAM_PORTS) == 0)
2899 return false; /* downstream port status fetch failed */
2900
2901 return true;
92fd8fd1
KP		 2902}
2903
0d198328
AJ		 2904static void
2905intel_dp_probe_oui(struct intel_dp *intel_dp)
2906{
2907 u8 buf[3];
2908
2909 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2910 return;
2911
4be73780 2912 edp_panel_vdd_on(intel_dp);
351cfc34 2913
0d198328
AJ		 2914 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2915 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2916 buf[0], buf[1], buf[2]);
2917
2918 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2919 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2920 buf[0], buf[1], buf[2]);
351cfc34 2921
4be73780 2922 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2923}
2924
d2e216d0
RV		 2925int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2926{
2927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2928 struct drm_device *dev = intel_dig_port->base.base.dev;
2929 struct intel_crtc *intel_crtc =
2930 to_intel_crtc(intel_dig_port->base.base.crtc);
2931 u8 buf[1];
2932
2933 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2934 return -EAGAIN;
2935
2936 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2937 return -ENOTTY;
2938
2939 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2940 DP_TEST_SINK_START))
2941 return -EAGAIN;
2942
2943 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2944 intel_wait_for_vblank(dev, intel_crtc->pipe);
2945 intel_wait_for_vblank(dev, intel_crtc->pipe);
2946
2947 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2948 return -EAGAIN;
2949
2950 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
2951 return 0;
2952}
2953
a60f0e38
JB		 2954static bool
2955intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2956{
2957 int ret;
2958
2959 ret = intel_dp_aux_native_read_retry(intel_dp,
2960 DP_DEVICE_SERVICE_IRQ_VECTOR,
2961 sink_irq_vector, 1);
2962 if (!ret)
2963 return false;
2964
2965 return true;
2966}
2967
2968static void
2969intel_dp_handle_test_request(struct intel_dp *intel_dp)
2970{
2971 /* NAK by default */
9324cf7f 2972 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2973}
2974
a4fc5ed6
KP		 2975/*
2976 * According to DP spec
2977 * 5.1.2:
2978 * 1. Read DPCD
2979 * 2. Configure link according to Receiver Capabilities
2980 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2981 * 4. Check link status on receipt of hot-plug interrupt
2982 */
2983
00c09d70 2984void
ea5b213a 2985intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2986{
da63a9f2 2987 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2988 u8 sink_irq_vector;
93f62dad 2989 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2990
da63a9f2 2991 if (!intel_encoder->connectors_active)
d2b996ac 2992 return;
59cd09e1 2993
da63a9f2 2994 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2995 return;
2996
92fd8fd1 2997 /* Try to read receiver status if the link appears to be up */
93f62dad 2998 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2999 return;
3000 }
3001
92fd8fd1 3002 /* Now read the DPCD to see if it's actually running */
26d61aad 3003 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3004 return;
3005 }
3006
a60f0e38
JB		 3007 /* Try to read the source of the interrupt */
3008 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3009 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3010 /* Clear interrupt source */
3011 intel_dp_aux_native_write_1(intel_dp,
3012 DP_DEVICE_SERVICE_IRQ_VECTOR,
3013 sink_irq_vector);
3014
3015 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3016 intel_dp_handle_test_request(intel_dp);
3017 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3018 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3019 }
3020
1ffdff13 3021 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3022 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3023 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3024 intel_dp_start_link_train(intel_dp);
3025 intel_dp_complete_link_train(intel_dp);
3ab9c637 3026 intel_dp_stop_link_train(intel_dp);
33a34e4e 3027 }
a4fc5ed6 3028}
a4fc5ed6 3029
caf9ab24 3030/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3031static enum drm_connector_status
26d61aad 3032intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3033{
caf9ab24 3034 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3035 uint8_t type;
3036
3037 if (!intel_dp_get_dpcd(intel_dp))
3038 return connector_status_disconnected;
3039
3040 /* if there's no downstream port, we're done */
3041 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3042 return connector_status_connected;
caf9ab24
AJ		 3043
3044 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3045 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3046 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3047 uint8_t reg;
caf9ab24 3048 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 3049 &reg, 1))
caf9ab24 3050 return connector_status_unknown;
23235177
AJ		 3051 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3052 : connector_status_disconnected;
caf9ab24
AJ		 3053 }
3054
3055 /* If no HPD, poke DDC gently */
3056 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 3057 return connector_status_connected;
caf9ab24
AJ		 3058
3059 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3060 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3061 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3062 if (type == DP_DS_PORT_TYPE_VGA ||
3063 type == DP_DS_PORT_TYPE_NON_EDID)
3064 return connector_status_unknown;
3065 } else {
3066 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3067 DP_DWN_STRM_PORT_TYPE_MASK;
3068 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3069 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3070 return connector_status_unknown;
3071 }
caf9ab24
AJ		 3072
3073 /* Anything else is out of spec, warn and ignore */
3074 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3075 return connector_status_disconnected;
71ba9000
AJ		 3076}
3077
5eb08b69 3078static enum drm_connector_status
a9756bb5 3079ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3080{
30add22d 3081 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3082 struct drm_i915_private *dev_priv = dev->dev_private;
3083 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3084 enum drm_connector_status status;
3085
fe16d949
CW		 3086 /* Can't disconnect eDP, but you can close the lid... */
3087 if (is_edp(intel_dp)) {
30add22d 3088 status = intel_panel_detect(dev);
fe16d949
CW		 3089 if (status == connector_status_unknown)
3090 status = connector_status_connected;
3091 return status;
3092 }
01cb9ea6 3093
1b469639
DL		 3094 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3095 return connector_status_disconnected;
3096
26d61aad 3097 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3098}
3099
a4fc5ed6 3100static enum drm_connector_status
a9756bb5 3101g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3102{
30add22d 3103 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3104 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3105 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3106 uint32_t bit;
5eb08b69 3107
35aad75f
JB		 3108 /* Can't disconnect eDP, but you can close the lid... */
3109 if (is_edp(intel_dp)) {
3110 enum drm_connector_status status;
3111
3112 status = intel_panel_detect(dev);
3113 if (status == connector_status_unknown)
3114 status = connector_status_connected;
3115 return status;
3116 }
3117
232a6ee9
TP		 3118 if (IS_VALLEYVIEW(dev)) {
3119 switch (intel_dig_port->port) {
3120 case PORT_B:
3121 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3122 break;
3123 case PORT_C:
3124 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3125 break;
3126 case PORT_D:
3127 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3128 break;
3129 default:
3130 return connector_status_unknown;
3131 }
3132 } else {
3133 switch (intel_dig_port->port) {
3134 case PORT_B:
3135 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3136 break;
3137 case PORT_C:
3138 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3139 break;
3140 case PORT_D:
3141 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3142 break;
3143 default:
3144 return connector_status_unknown;
3145 }
a4fc5ed6
KP		 3146 }
3147
10f76a38 3148 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3149 return connector_status_disconnected;
3150
26d61aad 3151 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3152}
3153
8c241fef
KP		 3154static struct edid *
3155intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3156{
9cd300e0 3157 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3158
9cd300e0
JN		 3159 /* use cached edid if we have one */
3160 if (intel_connector->edid) {
9cd300e0
JN		 3161 /* invalid edid */
3162 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3163 return NULL;
3164
55e9edeb 3165 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3166 }
8c241fef 3167
9cd300e0 3168 return drm_get_edid(connector, adapter);
8c241fef
KP		 3169}
3170
3171static int
3172intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3173{
9cd300e0 3174 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3175
9cd300e0
JN		 3176 /* use cached edid if we have one */
3177 if (intel_connector->edid) {
3178 /* invalid edid */
3179 if (IS_ERR(intel_connector->edid))
3180 return 0;
3181
3182 return intel_connector_update_modes(connector,
3183 intel_connector->edid);
d6f24d0f
JB		 3184 }
3185
9cd300e0 3186 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3187}
3188
a9756bb5
ZW		 3189static enum drm_connector_status
3190intel_dp_detect(struct drm_connector *connector, bool force)
3191{
3192 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3193 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3194 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3195 struct drm_device *dev = connector->dev;
c8c8fb33 3196 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5
ZW		 3197 enum drm_connector_status status;
3198 struct edid *edid = NULL;
3199
c8c8fb33
PZ		 3200 intel_runtime_pm_get(dev_priv);
3201
164c8598
CW		 3202 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3203 connector->base.id, drm_get_connector_name(connector));
3204
a9756bb5
ZW		 3205 intel_dp->has_audio = false;
3206
3207 if (HAS_PCH_SPLIT(dev))
3208 status = ironlake_dp_detect(intel_dp);
3209 else
3210 status = g4x_dp_detect(intel_dp);
1b9be9d0 3211
a9756bb5 3212 if (status != connector_status_connected)
c8c8fb33 3213 goto out;
a9756bb5 3214
0d198328
AJ		 3215 intel_dp_probe_oui(intel_dp);
3216
c3e5f67b
DV		 3217 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3218 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3219 } else {
8c241fef 3220 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3221 if (edid) {
3222 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3223 kfree(edid);
3224 }
a9756bb5
ZW		 3225 }
3226
d63885da
PZ		 3227 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3228 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3229 status = connector_status_connected;
3230
3231out:
3232 intel_runtime_pm_put(dev_priv);
3233 return status;
a4fc5ed6
KP		 3234}
3235
3236static int intel_dp_get_modes(struct drm_connector *connector)
3237{
df0e9248 3238 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 3239 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3240 struct drm_device *dev = connector->dev;
32f9d658 3241 int ret;
a4fc5ed6
KP		 3242
3243 /* We should parse the EDID data and find out if it has an audio sink
3244 */
3245
8c241fef 3246 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 3247 if (ret)
32f9d658
ZW		 3248 return ret;
3249
f8779fda 3250 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3251 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3252 struct drm_display_mode *mode;
dd06f90e
JN		 3253 mode = drm_mode_duplicate(dev,
3254 intel_connector->panel.fixed_mode);
f8779fda 3255 if (mode) {
32f9d658
ZW		 3256 drm_mode_probed_add(connector, mode);
3257 return 1;
3258 }
3259 }
3260 return 0;
a4fc5ed6
KP		 3261}
3262
1aad7ac0
CW		 3263static bool
3264intel_dp_detect_audio(struct drm_connector *connector)
3265{
3266 struct intel_dp *intel_dp = intel_attached_dp(connector);
3267 struct edid *edid;
3268 bool has_audio = false;
3269
8c241fef 3270 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3271 if (edid) {
3272 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3273 kfree(edid);
3274 }
3275
3276 return has_audio;
3277}
3278
f684960e
CW		 3279static int
3280intel_dp_set_property(struct drm_connector *connector,
3281 struct drm_property *property,
3282 uint64_t val)
3283{
e953fd7b 3284 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3285 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3286 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3287 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3288 int ret;
3289
662595df 3290 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3291 if (ret)
3292 return ret;
3293
3f43c48d 3294 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3295 int i = val;
3296 bool has_audio;
3297
3298 if (i == intel_dp->force_audio)
f684960e
CW		 3299 return 0;
3300
1aad7ac0 3301 intel_dp->force_audio = i;
f684960e 3302
c3e5f67b 3303 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3304 has_audio = intel_dp_detect_audio(connector);
3305 else
c3e5f67b 3306 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3307
3308 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3309 return 0;
3310
1aad7ac0 3311 intel_dp->has_audio = has_audio;
f684960e
CW		 3312 goto done;
3313 }
3314
e953fd7b 3315 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3316 bool old_auto = intel_dp->color_range_auto;
3317 uint32_t old_range = intel_dp->color_range;
3318
55bc60db
VS		 3319 switch (val) {
3320 case INTEL_BROADCAST_RGB_AUTO:
3321 intel_dp->color_range_auto = true;
3322 break;
3323 case INTEL_BROADCAST_RGB_FULL:
3324 intel_dp->color_range_auto = false;
3325 intel_dp->color_range = 0;
3326 break;
3327 case INTEL_BROADCAST_RGB_LIMITED:
3328 intel_dp->color_range_auto = false;
3329 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3330 break;
3331 default:
3332 return -EINVAL;
3333 }
ae4edb80
DV		 3334
3335 if (old_auto == intel_dp->color_range_auto &&
3336 old_range == intel_dp->color_range)
3337 return 0;
3338
e953fd7b
CW		 3339 goto done;
3340 }
3341
53b41837
YN		 3342 if (is_edp(intel_dp) &&
3343 property == connector->dev->mode_config.scaling_mode_property) {
3344 if (val == DRM_MODE_SCALE_NONE) {
3345 DRM_DEBUG_KMS("no scaling not supported\n");
3346 return -EINVAL;
3347 }
3348
3349 if (intel_connector->panel.fitting_mode == val) {
3350 /* the eDP scaling property is not changed */
3351 return 0;
3352 }
3353 intel_connector->panel.fitting_mode = val;
3354
3355 goto done;
3356 }
3357
f684960e
CW		 3358 return -EINVAL;
3359
3360done:
c0c36b94
CW		 3361 if (intel_encoder->base.crtc)
3362 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3363
3364 return 0;
3365}
3366
a4fc5ed6 3367static void
73845adf 3368intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3369{
1d508706 3370 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3371
9cd300e0
JN		 3372 if (!IS_ERR_OR_NULL(intel_connector->edid))
3373 kfree(intel_connector->edid);
3374
acd8db10
PZ		 3375 /* Can't call is_edp() since the encoder may have been destroyed
3376 * already. */
3377 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3378 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3379
a4fc5ed6 3380 drm_connector_cleanup(connector);
55f78c43 3381 kfree(connector);
a4fc5ed6
KP		 3382}
3383
00c09d70 3384void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3385{
da63a9f2
PZ		 3386 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3387 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3388 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3389
3390 i2c_del_adapter(&intel_dp->adapter);
3391 drm_encoder_cleanup(encoder);
bd943159
KP		 3392 if (is_edp(intel_dp)) {
3393 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3394 mutex_lock(&dev->mode_config.mutex);
4be73780 3395 edp_panel_vdd_off_sync(intel_dp);
bd173813 3396 mutex_unlock(&dev->mode_config.mutex);
bd943159 3397 }
da63a9f2 3398 kfree(intel_dig_port);
24d05927
DV		 3399}
3400
a4fc5ed6 3401static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3402 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3403 .detect = intel_dp_detect,
3404 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3405 .set_property = intel_dp_set_property,
73845adf 3406 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3407};
3408
3409static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3410 .get_modes = intel_dp_get_modes,
3411 .mode_valid = intel_dp_mode_valid,
df0e9248 3412 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3413};
3414
a4fc5ed6 3415static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3416 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3417};
3418
995b6762 3419static void
21d40d37 3420intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3421{
fa90ecef 3422 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3423
885a5014 3424 intel_dp_check_link_status(intel_dp);
c8110e52 3425}
6207937d 3426
e3421a18
ZW		 3427/* Return which DP Port should be selected for Transcoder DP control */
3428int
0206e353 3429intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3430{
3431 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3432 struct intel_encoder *intel_encoder;
3433 struct intel_dp *intel_dp;
e3421a18 3434
fa90ecef
PZ		 3435 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3436 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3437
fa90ecef
PZ		 3438 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3439 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3440 return intel_dp->output_reg;
e3421a18 3441 }
ea5b213a 3442
e3421a18
ZW		 3443 return -1;
3444}
3445
36e83a18 3446/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3447bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3448{
3449 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3450 union child_device_config *p_child;
36e83a18 3451 int i;
5d8a7752
VS		 3452 static const short port_mapping[] = {
3453 [PORT_B] = PORT_IDPB,
3454 [PORT_C] = PORT_IDPC,
3455 [PORT_D] = PORT_IDPD,
3456 };
36e83a18 3457
3b32a35b
VS		 3458 if (port == PORT_A)
3459 return true;
3460
41aa3448 3461 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3462 return false;
3463
41aa3448
RV		 3464 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3465 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3466
5d8a7752 3467 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3468 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3469 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3470 return true;
3471 }
3472 return false;
3473}
3474
f684960e
CW		 3475static void
3476intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3477{
53b41837
YN		 3478 struct intel_connector *intel_connector = to_intel_connector(connector);
3479
3f43c48d 3480 intel_attach_force_audio_property(connector);
e953fd7b 3481 intel_attach_broadcast_rgb_property(connector);
55bc60db 3482 intel_dp->color_range_auto = true;
53b41837
YN		 3483
3484 if (is_edp(intel_dp)) {
3485 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3486 drm_object_attach_property(
3487 &connector->base,
53b41837 3488 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3489 DRM_MODE_SCALE_ASPECT);
3490 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3491 }
f684960e
CW		 3492}
3493
67a54566
DV		 3494static void
3495intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3496 struct intel_dp *intel_dp,
3497 struct edp_power_seq *out)
67a54566
DV		 3498{
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500 struct edp_power_seq cur, vbt, spec, final;
3501 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3502 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3503
3504 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3505 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3506 pp_on_reg = PCH_PP_ON_DELAYS;
3507 pp_off_reg = PCH_PP_OFF_DELAYS;
3508 pp_div_reg = PCH_PP_DIVISOR;
3509 } else {
bf13e81b
JN		 3510 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3511
3512 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3513 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3514 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3515 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3516 }
67a54566
DV		 3517
3518 /* Workaround: Need to write PP_CONTROL with the unlock key as
3519 * the very first thing. */
453c5420 3520 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3521 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3522
453c5420
JB		 3523 pp_on = I915_READ(pp_on_reg);
3524 pp_off = I915_READ(pp_off_reg);
3525 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3526
3527 /* Pull timing values out of registers */
3528 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3529 PANEL_POWER_UP_DELAY_SHIFT;
3530
3531 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3532 PANEL_LIGHT_ON_DELAY_SHIFT;
3533
3534 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3535 PANEL_LIGHT_OFF_DELAY_SHIFT;
3536
3537 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3538 PANEL_POWER_DOWN_DELAY_SHIFT;
3539
3540 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3541 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3542
3543 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3544 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3545
41aa3448 3546 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3547
3548 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3549 * our hw here, which are all in 100usec. */
3550 spec.t1_t3 = 210 * 10;
3551 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3552 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3553 spec.t10 = 500 * 10;
3554 /* This one is special and actually in units of 100ms, but zero
3555 * based in the hw (so we need to add 100 ms). But the sw vbt
3556 * table multiplies it with 1000 to make it in units of 100usec,
3557 * too. */
3558 spec.t11_t12 = (510 + 100) * 10;
3559
3560 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3561 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3562
3563 /* Use the max of the register settings and vbt. If both are
3564 * unset, fall back to the spec limits. */
3565#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3566 spec.field : \
3567 max(cur.field, vbt.field))
3568 assign_final(t1_t3);
3569 assign_final(t8);
3570 assign_final(t9);
3571 assign_final(t10);
3572 assign_final(t11_t12);
3573#undef assign_final
3574
3575#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3576 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3577 intel_dp->backlight_on_delay = get_delay(t8);
3578 intel_dp->backlight_off_delay = get_delay(t9);
3579 intel_dp->panel_power_down_delay = get_delay(t10);
3580 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3581#undef get_delay
3582
f30d26e4
JN		 3583 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3584 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3585 intel_dp->panel_power_cycle_delay);
3586
3587 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3588 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3589
3590 if (out)
3591 *out = final;
3592}
3593
3594static void
3595intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3596 struct intel_dp *intel_dp,
3597 struct edp_power_seq *seq)
3598{
3599 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3600 u32 pp_on, pp_off, pp_div, port_sel = 0;
3601 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3602 int pp_on_reg, pp_off_reg, pp_div_reg;
3603
3604 if (HAS_PCH_SPLIT(dev)) {
3605 pp_on_reg = PCH_PP_ON_DELAYS;
3606 pp_off_reg = PCH_PP_OFF_DELAYS;
3607 pp_div_reg = PCH_PP_DIVISOR;
3608 } else {
bf13e81b
JN		 3609 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3610
3611 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3612 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3613 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3614 }
3615
b2f19d1a
PZ		 3616 /*
3617 * And finally store the new values in the power sequencer. The
3618 * backlight delays are set to 1 because we do manual waits on them. For
3619 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3620 * we'll end up waiting for the backlight off delay twice: once when we
3621 * do the manual sleep, and once when we disable the panel and wait for
3622 * the PP_STATUS bit to become zero.
3623 */
f30d26e4 3624 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3625 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3626 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3627 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3628 /* Compute the divisor for the pp clock, simply match the Bspec
3629 * formula. */
453c5420 3630 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3631 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3632 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3633
3634 /* Haswell doesn't have any port selection bits for the panel
3635 * power sequencer any more. */
bc7d38a4 3636 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3637 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3638 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3639 else
3640 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3641 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3642 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3643 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3644 else
a24c144c 3645 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3646 }
3647
453c5420
JB		 3648 pp_on |= port_sel;
3649
3650 I915_WRITE(pp_on_reg, pp_on);
3651 I915_WRITE(pp_off_reg, pp_off);
3652 I915_WRITE(pp_div_reg, pp_div);
67a54566 3653
67a54566 3654 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3655 I915_READ(pp_on_reg),
3656 I915_READ(pp_off_reg),
3657 I915_READ(pp_div_reg));
f684960e
CW		 3658}
3659
ed92f0b2 3660static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3661 struct intel_connector *intel_connector,
3662 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3663{
3664 struct drm_connector *connector = &intel_connector->base;
3665 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3666 struct drm_device *dev = intel_dig_port->base.base.dev;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3669 bool has_dpcd;
3670 struct drm_display_mode *scan;
3671 struct edid *edid;
3672
3673 if (!is_edp(intel_dp))
3674 return true;
3675
ed92f0b2 3676 /* Cache DPCD and EDID for edp. */
4be73780 3677 edp_panel_vdd_on(intel_dp);
ed92f0b2 3678 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3679 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3680
3681 if (has_dpcd) {
3682 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3683 dev_priv->no_aux_handshake =
3684 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3685 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3686 } else {
3687 /* if this fails, presume the device is a ghost */
3688 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3689 return false;
3690 }
3691
3692 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3693 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3694
ed92f0b2
PZ		 3695 edid = drm_get_edid(connector, &intel_dp->adapter);
3696 if (edid) {
3697 if (drm_add_edid_modes(connector, edid)) {
3698 drm_mode_connector_update_edid_property(connector,
3699 edid);
3700 drm_edid_to_eld(connector, edid);
3701 } else {
3702 kfree(edid);
3703 edid = ERR_PTR(-EINVAL);
3704 }
3705 } else {
3706 edid = ERR_PTR(-ENOENT);
3707 }
3708 intel_connector->edid = edid;
3709
3710 /* prefer fixed mode from EDID if available */
3711 list_for_each_entry(scan, &connector->probed_modes, head) {
3712 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3713 fixed_mode = drm_mode_duplicate(dev, scan);
3714 break;
3715 }
3716 }
3717
3718 /* fallback to VBT if available for eDP */
3719 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3720 fixed_mode = drm_mode_duplicate(dev,
3721 dev_priv->vbt.lfp_lvds_vbt_mode);
3722 if (fixed_mode)
3723 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3724 }
3725
ed92f0b2
PZ		 3726 intel_panel_init(&intel_connector->panel, fixed_mode);
3727 intel_panel_setup_backlight(connector);
3728
3729 return true;
3730}
3731
16c25533 3732bool
f0fec3f2
PZ		 3733intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3734 struct intel_connector *intel_connector)
a4fc5ed6 3735{
f0fec3f2
PZ		 3736 struct drm_connector *connector = &intel_connector->base;
3737 struct intel_dp *intel_dp = &intel_dig_port->dp;
3738 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3739 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3740 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3741 enum port port = intel_dig_port->port;
0095e6dc 3742 struct edp_power_seq power_seq = { 0 };
5eb08b69 3743 const char *name = NULL;
b2a14755 3744 int type, error;
a4fc5ed6 3745
ec5b01dd
DL		 3746 /* intel_dp vfuncs */
3747 if (IS_VALLEYVIEW(dev))
3748 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3749 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3750 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3751 else if (HAS_PCH_SPLIT(dev))
3752 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3753 else
3754 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3755
153b1100
DL		 3756 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3757
0767935e
DV		 3758 /* Preserve the current hw state. */
3759 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3760 intel_dp->attached_connector = intel_connector;
3d3dc149 3761
3b32a35b 3762 if (intel_dp_is_edp(dev, port))
b329530c 3763 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3764 else
3765 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3766
f7d24902
ID		 3767 /*
3768 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3769 * for DP the encoder type can be set by the caller to
3770 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3771 */
3772 if (type == DRM_MODE_CONNECTOR_eDP)
3773 intel_encoder->type = INTEL_OUTPUT_EDP;
3774
e7281eab
ID		 3775 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3776 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3777 port_name(port));
3778
b329530c 3779 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3780 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3781
a4fc5ed6
KP		 3782 connector->interlace_allowed = true;
3783 connector->doublescan_allowed = 0;
3784
f0fec3f2 3785 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3786 edp_panel_vdd_work);
a4fc5ed6 3787
df0e9248 3788 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3789 drm_sysfs_connector_add(connector);
3790
affa9354 3791 if (HAS_DDI(dev))
bcbc889b
PZ		 3792 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3793 else
3794 intel_connector->get_hw_state = intel_connector_get_hw_state;
3795
9ed35ab1
PZ		 3796 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3797 if (HAS_DDI(dev)) {
3798 switch (intel_dig_port->port) {
3799 case PORT_A:
3800 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3801 break;
3802 case PORT_B:
3803 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3804 break;
3805 case PORT_C:
3806 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3807 break;
3808 case PORT_D:
3809 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3810 break;
3811 default:
3812 BUG();
3813 }
3814 }
e8cb4558 3815
a4fc5ed6 3816 /* Set up the DDC bus. */
ab9d7c30
PZ		 3817 switch (port) {
3818 case PORT_A:
1d843f9d 3819 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3820 name = "DPDDC-A";
3821 break;
3822 case PORT_B:
1d843f9d 3823 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3824 name = "DPDDC-B";
3825 break;
3826 case PORT_C:
1d843f9d 3827 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3828 name = "DPDDC-C";
3829 break;
3830 case PORT_D:
1d843f9d 3831 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3832 name = "DPDDC-D";
3833 break;
3834 default:
ad1c0b19 3835 BUG();
5eb08b69
ZW		 3836 }
3837
0095e6dc
PZ		 3838 if (is_edp(intel_dp))
3839 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3840
b2a14755
PZ		 3841 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3842 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3843 error, port_name(port));
c1f05264 3844
2b28bb1b
RV		 3845 intel_dp->psr_setup_done = false;
3846
0095e6dc 3847 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3848 i2c_del_adapter(&intel_dp->adapter);
3849 if (is_edp(intel_dp)) {
3850 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3851 mutex_lock(&dev->mode_config.mutex);
4be73780 3852 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3853 mutex_unlock(&dev->mode_config.mutex);
3854 }
b2f246a8
PZ		 3855 drm_sysfs_connector_remove(connector);
3856 drm_connector_cleanup(connector);
16c25533 3857 return false;
b2f246a8 3858 }
32f9d658 3859
f684960e
CW		 3860 intel_dp_add_properties(intel_dp, connector);
3861
a4fc5ed6
KP		 3862 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3863 * 0xd. Failure to do so will result in spurious interrupts being
3864 * generated on the port when a cable is not attached.
3865 */
3866 if (IS_G4X(dev) && !IS_GM45(dev)) {
3867 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3868 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3869 }
16c25533
PZ		 3870
3871 return true;
a4fc5ed6 3872}
f0fec3f2
PZ		 3873
3874void
3875intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3876{
3877 struct intel_digital_port *intel_dig_port;
3878 struct intel_encoder *intel_encoder;
3879 struct drm_encoder *encoder;
3880 struct intel_connector *intel_connector;
3881
b14c5679 3882 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3883 if (!intel_dig_port)
3884 return;
3885
b14c5679 3886 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3887 if (!intel_connector) {
3888 kfree(intel_dig_port);
3889 return;
3890 }
3891
3892 intel_encoder = &intel_dig_port->base;
3893 encoder = &intel_encoder->base;
3894
3895 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3896 DRM_MODE_ENCODER_TMDS);
3897
5bfe2ac0 3898 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3899 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3900 intel_encoder->disable = intel_disable_dp;
3901 intel_encoder->post_disable = intel_post_disable_dp;
3902 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3903 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3904 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3905 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3906 intel_encoder->pre_enable = vlv_pre_enable_dp;
3907 intel_encoder->enable = vlv_enable_dp;
3908 } else {
ecff4f3b
JN		 3909 intel_encoder->pre_enable = g4x_pre_enable_dp;
3910 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3911 }
f0fec3f2 3912
174edf1f 3913 intel_dig_port->port = port;
f0fec3f2
PZ		 3914 intel_dig_port->dp.output_reg = output_reg;
3915
00c09d70 3916 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3917 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3918 intel_encoder->cloneable = false;
3919 intel_encoder->hot_plug = intel_dp_hot_plug;
3920
15b1d171
PZ		 3921 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3922 drm_encoder_cleanup(encoder);
3923 kfree(intel_dig_port);
b2f246a8 3924 kfree(intel_connector);
15b1d171 3925 }
f0fec3f2 3926}
Linux kernel - Deliverables
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