projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/skl: gen9 uses the same bind_vma() vfuncs as gen6+
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
5ed12a19
DL		 664static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
665 bool has_aux_irq,
666 int send_bytes,
667 uint32_t aux_clock_divider)
668{
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
672
673 if (IS_GEN6(dev))
674 precharge = 3;
675 else
676 precharge = 5;
677
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
680 else
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
682
683 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 684 DP_AUX_CH_CTL_DONE |
5ed12a19 685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 687 timeout |
788d4433 688 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 692}
693
b84a1cf8
RV		 694static int
695intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
bc86625a 704 uint32_t aux_clock_divider;
b84a1cf8
RV		 705 int i, ret, recv_bytes;
706 uint32_t status;
5ed12a19 707 int try, clock = 0;
4e6b788c 708 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 709 bool vdd;
710
773538e8 711 pps_lock(intel_dp);
e39b999a 712
72c3500a
VS		 713 /*
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
717 * ourselves.
718 */
1e0560e0 719 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 720
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
723 * deep sleep states.
724 */
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
726
727 intel_dp_check_edp(intel_dp);
5eb08b69 728
c67a470b
PZ		 729 intel_aux_display_runtime_get(dev_priv);
730
11bee43e
JB		 731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
ef04f00d 733 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
735 break;
736 msleep(1);
737 }
738
739 if (try == 3) {
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
741 I915_READ(ch_ctl));
9ee32fea
DV		 742 ret = -EBUSY;
743 goto out;
4f7f7b7e
CW		 744 }
745
46a5ae9f
PZ		 746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
748 ret = -E2BIG;
749 goto out;
750 }
751
ec5b01dd 752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
754 has_aux_irq,
755 send_bytes,
756 aux_clock_divider);
5ed12a19 757
bc86625a
CW		 758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
764
765 /* Send the command and wait for it to complete */
5ed12a19 766 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 767
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
769
770 /* Clear done status and any errors */
771 I915_WRITE(ch_ctl,
772 status |
773 DP_AUX_CH_CTL_DONE |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
776
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
779 continue;
780 if (status & DP_AUX_CH_CTL_DONE)
781 break;
782 }
4f7f7b7e 783 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 784 break;
785 }
786
a4fc5ed6 787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 789 ret = -EBUSY;
790 goto out;
a4fc5ed6
KP		 791 }
792
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
795 */
a5b3da54 796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 798 ret = -EIO;
799 goto out;
a5b3da54 800 }
1ae8c0a5
KP		 801
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
a5b3da54 804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 806 ret = -ETIMEDOUT;
807 goto out;
a4fc5ed6
KP		 808 }
809
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
0206e353 815
4f7f7b7e
CW		 816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
a4fc5ed6 819
9ee32fea
DV		 820 ret = recv_bytes;
821out:
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 823 intel_aux_display_runtime_put(dev_priv);
9ee32fea 824
884f19e9
JN		 825 if (vdd)
826 edp_panel_vdd_off(intel_dp, false);
827
773538e8 828 pps_unlock(intel_dp);
e39b999a 829
9ee32fea 830 return ret;
a4fc5ed6
KP		 831}
832
a6c8aff0
JN		 833#define BARE_ADDRESS_SIZE 3
834#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 835static ssize_t
836intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 837{
9d1a1031
JN		 838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
a4fc5ed6 841 int ret;
a4fc5ed6 842
9d1a1031
JN		 843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
46a5ae9f 847
9d1a1031
JN		 848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
a6c8aff0 851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 852 rxsize = 1;
f51a44b9 853
9d1a1031
JN		 854 if (WARN_ON(txsize > 20))
855 return -E2BIG;
a4fc5ed6 856
9d1a1031 857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 858
9d1a1031
JN		 859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
860 if (ret > 0) {
861 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 862
9d1a1031
JN		 863 /* Return payload size. */
864 ret = msg->size;
865 }
866 break;
46a5ae9f 867
9d1a1031
JN		 868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = msg->size + 1;
a4fc5ed6 872
9d1a1031
JN		 873 if (WARN_ON(rxsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031
JN		 876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
877 if (ret > 0) {
878 msg->reply = rxbuf[0] >> 4;
879 /*
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
882 *
883 * Return payload size.
884 */
885 ret--;
886 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 887 }
9d1a1031
JN		 888 break;
889
890 default:
891 ret = -EINVAL;
892 break;
a4fc5ed6 893 }
f51a44b9 894
9d1a1031 895 return ret;
a4fc5ed6
KP		 896}
897
9d1a1031
JN		 898static void
899intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
900{
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 enum port port = intel_dig_port->port;
0b99836f 904 const char *name = NULL;
ab2c0672
DA		 905 int ret;
906
33ad6626
JN		 907 switch (port) {
908 case PORT_A:
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 910 name = "DPDDC-A";
ab2c0672 911 break;
33ad6626
JN		 912 case PORT_B:
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 914 name = "DPDDC-B";
ab2c0672 915 break;
33ad6626
JN		 916 case PORT_C:
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 918 name = "DPDDC-C";
ab2c0672 919 break;
33ad6626
JN		 920 case PORT_D:
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 922 name = "DPDDC-D";
33ad6626
JN		 923 break;
924 default:
925 BUG();
ab2c0672
DA		 926 }
927
1b1aad75
DL		 928 /*
929 * The AUX_CTL register is usually DP_CTL + 0x10.
930 *
931 * On Haswell and Broadwell though:
932 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
933 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
934 *
935 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
936 */
937 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 938 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 939
0b99836f 940 intel_dp->aux.name = name;
9d1a1031
JN		 941 intel_dp->aux.dev = dev->dev;
942 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 943
0b99836f
JN		 944 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
945 connector->base.kdev->kobj.name);
8316f337 946
4f71d0cb 947 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 948 if (ret < 0) {
4f71d0cb 949 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 950 name, ret);
951 return;
ab2c0672 952 }
8a5e6aeb 953
0b99836f
JN		 954 ret = sysfs_create_link(&connector->base.kdev->kobj,
955 &intel_dp->aux.ddc.dev.kobj,
956 intel_dp->aux.ddc.dev.kobj.name);
957 if (ret < 0) {
958 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 959 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 960 }
a4fc5ed6
KP		 961}
962
80f65de3
ID		 963static void
964intel_dp_connector_unregister(struct intel_connector *intel_connector)
965{
966 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
967
0e32b39c
DA		 968 if (!intel_connector->mst_port)
969 sysfs_remove_link(&intel_connector->base.kdev->kobj,
970 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 971 intel_connector_unregister(intel_connector);
972}
973
0e50338c
DV		 974static void
975hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
976{
977 switch (link_bw) {
978 case DP_LINK_BW_1_62:
979 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
980 break;
981 case DP_LINK_BW_2_7:
982 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
983 break;
984 case DP_LINK_BW_5_4:
985 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
986 break;
987 }
988}
989
c6bb3538
DV		 990static void
991intel_dp_set_clock(struct intel_encoder *encoder,
992 struct intel_crtc_config *pipe_config, int link_bw)
993{
994 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 995 const struct dp_link_dpll *divisor = NULL;
996 int i, count = 0;
c6bb3538
DV		 997
998 if (IS_G4X(dev)) {
9dd4ffdf
CML		 999 divisor = gen4_dpll;
1000 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1001 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1002 divisor = pch_dpll;
1003 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1004 } else if (IS_CHERRYVIEW(dev)) {
1005 divisor = chv_dpll;
1006 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1007 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1008 divisor = vlv_dpll;
1009 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1010 }
9dd4ffdf
CML		 1011
1012 if (divisor && count) {
1013 for (i = 0; i < count; i++) {
1014 if (link_bw == divisor[i].link_bw) {
1015 pipe_config->dpll = divisor[i].dpll;
1016 pipe_config->clock_set = true;
1017 break;
1018 }
1019 }
c6bb3538
DV		 1020 }
1021}
1022
00c09d70 1023bool
5bfe2ac0
DV		 1024intel_dp_compute_config(struct intel_encoder *encoder,
1025 struct intel_crtc_config *pipe_config)
a4fc5ed6 1026{
5bfe2ac0 1027 struct drm_device *dev = encoder->base.dev;
36008365 1028 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1029 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1030 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1031 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1032 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1033 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1034 int lane_count, clock;
56071a20 1035 int min_lane_count = 1;
eeb6324d 1036 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1037 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1038 int min_clock = 0;
06ea66b6 1039 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1040 int bpp, mode_rate;
06ea66b6 1041 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1042 int link_avail, link_clock;
a4fc5ed6 1043
bc7d38a4 1044 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1045 pipe_config->has_pch_encoder = true;
1046
03afc4a2 1047 pipe_config->has_dp_encoder = true;
f769cd24 1048 pipe_config->has_drrs = false;
9ed109a7 1049 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1050
dd06f90e
JN		 1051 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1052 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1053 adjusted_mode);
2dd24552
JB		 1054 if (!HAS_PCH_SPLIT(dev))
1055 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1056 intel_connector->panel.fitting_mode);
1057 else
b074cec8
JB		 1058 intel_pch_panel_fitting(intel_crtc, pipe_config,
1059 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1060 }
1061
cb1793ce 1062 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1063 return false;
1064
083f9560
DV		 1065 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1066 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1067 max_lane_count, bws[max_clock],
1068 adjusted_mode->crtc_clock);
083f9560 1069
36008365
DV		 1070 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1071 * bpc in between. */
3e7ca985 1072 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1073 if (is_edp(intel_dp)) {
1074 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1075 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1076 dev_priv->vbt.edp_bpp);
1077 bpp = dev_priv->vbt.edp_bpp;
1078 }
1079
f4cdbc21
JN		 1080 if (IS_BROADWELL(dev)) {
1081 /* Yes, it's an ugly hack. */
1082 min_lane_count = max_lane_count;
1083 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
1084 min_lane_count);
1085 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 1086 min_lane_count = min(dev_priv->vbt.edp_lanes,
1087 max_lane_count);
1088 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
1089 min_lane_count);
1090 }
1091
1092 if (dev_priv->vbt.edp_rate) {
1093 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
1094 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
1095 bws[min_clock]);
1096 }
7984211e 1097 }
657445fe 1098
36008365 1099 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1100 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1101 bpp);
36008365 1102
c6930992
DA		 1103 for (clock = min_clock; clock <= max_clock; clock++) {
1104 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1105 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1106 link_avail = intel_dp_max_data_rate(link_clock,
1107 lane_count);
1108
1109 if (mode_rate <= link_avail) {
1110 goto found;
1111 }
1112 }
1113 }
1114 }
c4867936 1115
36008365 1116 return false;
3685a8f3 1117
36008365 1118found:
55bc60db
VS		 1119 if (intel_dp->color_range_auto) {
1120 /*
1121 * See:
1122 * CEA-861-E - 5.1 Default Encoding Parameters
1123 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1124 */
18316c8c 1125 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1126 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1127 else
1128 intel_dp->color_range = 0;
1129 }
1130
3685a8f3 1131 if (intel_dp->color_range)
50f3b016 1132 pipe_config->limited_color_range = true;
a4fc5ed6 1133
36008365
DV		 1134 intel_dp->link_bw = bws[clock];
1135 intel_dp->lane_count = lane_count;
657445fe 1136 pipe_config->pipe_bpp = bpp;
ff9a6750 1137 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1138
36008365
DV		 1139 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1140 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1141 pipe_config->port_clock, bpp);
36008365
DV		 1142 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1143 mode_rate, link_avail);
a4fc5ed6 1144
03afc4a2 1145 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1146 adjusted_mode->crtc_clock,
1147 pipe_config->port_clock,
03afc4a2 1148 &pipe_config->dp_m_n);
9d1a455b 1149
439d7ac0
PB		 1150 if (intel_connector->panel.downclock_mode != NULL &&
1151 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1152 pipe_config->has_drrs = true;
439d7ac0
PB		 1153 intel_link_compute_m_n(bpp, lane_count,
1154 intel_connector->panel.downclock_mode->clock,
1155 pipe_config->port_clock,
1156 &pipe_config->dp_m2_n2);
1157 }
1158
ea155f32 1159 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1160 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1161 else
1162 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1163
03afc4a2 1164 return true;
a4fc5ed6
KP		 1165}
1166
7c62a164 1167static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1168{
7c62a164
DV		 1169 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1170 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1171 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 dpa_ctl;
1174
ff9a6750 1175 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1176 dpa_ctl = I915_READ(DP_A);
1177 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1178
ff9a6750 1179 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1180 /* For a long time we've carried around a ILK-DevA w/a for the
1181 * 160MHz clock. If we're really unlucky, it's still required.
1182 */
1183 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1184 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1185 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1186 } else {
1187 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1188 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1189 }
1ce17038 1190
ea9b6006
DV		 1191 I915_WRITE(DP_A, dpa_ctl);
1192
1193 POSTING_READ(DP_A);
1194 udelay(500);
1195}
1196
8ac33ed3 1197static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1198{
b934223d 1199 struct drm_device *dev = encoder->base.dev;
417e822d 1200 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1201 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1202 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1203 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1204 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1205
417e822d 1206 /*
1a2eb460 1207 * There are four kinds of DP registers:
417e822d
KP		 1208 *
1209 * IBX PCH
1a2eb460
KP		 1210 * SNB CPU
1211 * IVB CPU
417e822d
KP		 1212 * CPT PCH
1213 *
1214 * IBX PCH and CPU are the same for almost everything,
1215 * except that the CPU DP PLL is configured in this
1216 * register
1217 *
1218 * CPT PCH is quite different, having many bits moved
1219 * to the TRANS_DP_CTL register instead. That
1220 * configuration happens (oddly) in ironlake_pch_enable
1221 */
9c9e7927 1222
417e822d
KP		 1223 /* Preserve the BIOS-computed detected bit. This is
1224 * supposed to be read-only.
1225 */
1226 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1227
417e822d 1228 /* Handle DP bits in common between all three register formats */
417e822d 1229 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1230 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1231
9ed109a7 1232 if (crtc->config.has_audio) {
e0dac65e 1233 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1234 pipe_name(crtc->pipe));
ea5b213a 1235 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1236 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1237 }
247d89f6 1238
417e822d 1239 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1240
bc7d38a4 1241 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1242 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1243 intel_dp->DP |= DP_SYNC_HS_HIGH;
1244 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1245 intel_dp->DP |= DP_SYNC_VS_HIGH;
1246 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1247
6aba5b6c 1248 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1249 intel_dp->DP |= DP_ENHANCED_FRAMING;
1250
7c62a164 1251 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1252 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1253 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1254 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1255
1256 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1257 intel_dp->DP |= DP_SYNC_HS_HIGH;
1258 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1259 intel_dp->DP |= DP_SYNC_VS_HIGH;
1260 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1261
6aba5b6c 1262 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1263 intel_dp->DP |= DP_ENHANCED_FRAMING;
1264
44f37d1f
CML		 1265 if (!IS_CHERRYVIEW(dev)) {
1266 if (crtc->pipe == 1)
1267 intel_dp->DP |= DP_PIPEB_SELECT;
1268 } else {
1269 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1270 }
417e822d
KP		 1271 } else {
1272 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1273 }
a4fc5ed6
KP		 1274}
1275
ffd6749d
PZ		 1276#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1277#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1278
1a5ef5b7
PZ		 1279#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1280#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1281
ffd6749d
PZ		 1282#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1283#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1284
4be73780 1285static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1286 u32 mask,
1287 u32 value)
bd943159 1288{
30add22d 1289 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1290 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1291 u32 pp_stat_reg, pp_ctrl_reg;
1292
e39b999a
VS		 1293 lockdep_assert_held(&dev_priv->pps_mutex);
1294
bf13e81b
JN		 1295 pp_stat_reg = _pp_stat_reg(intel_dp);
1296 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1297
99ea7127 1298 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1299 mask, value,
1300 I915_READ(pp_stat_reg),
1301 I915_READ(pp_ctrl_reg));
32ce697c 1302
453c5420 1303 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1304 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1305 I915_READ(pp_stat_reg),
1306 I915_READ(pp_ctrl_reg));
32ce697c 1307 }
54c136d4
CW		 1308
1309 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1310}
32ce697c 1311
4be73780 1312static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1313{
1314 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1315 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1316}
1317
4be73780 1318static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1319{
1320 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1321 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1322}
1323
4be73780 1324static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1325{
1326 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1327
1328 /* When we disable the VDD override bit last we have to do the manual
1329 * wait. */
1330 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1331 intel_dp->panel_power_cycle_delay);
1332
4be73780 1333 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1334}
1335
4be73780 1336static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1337{
1338 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1339 intel_dp->backlight_on_delay);
1340}
1341
4be73780 1342static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1343{
1344 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1345 intel_dp->backlight_off_delay);
1346}
99ea7127 1347
832dd3c1
KP		 1348/* Read the current pp_control value, unlocking the register if it
1349 * is locked
1350 */
1351
453c5420 1352static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1353{
453c5420
JB		 1354 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 u32 control;
832dd3c1 1357
e39b999a
VS		 1358 lockdep_assert_held(&dev_priv->pps_mutex);
1359
bf13e81b 1360 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1361 control &= ~PANEL_UNLOCK_MASK;
1362 control |= PANEL_UNLOCK_REGS;
1363 return control;
bd943159
KP		 1364}
1365
951468f3
VS		 1366/*
1367 * Must be paired with edp_panel_vdd_off().
1368 * Must hold pps_mutex around the whole on/off sequence.
1369 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1370 */
1e0560e0 1371static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1372{
30add22d 1373 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1375 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1376 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1377 enum intel_display_power_domain power_domain;
5d613501 1378 u32 pp;
453c5420 1379 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1380 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1381
e39b999a
VS		 1382 lockdep_assert_held(&dev_priv->pps_mutex);
1383
97af61f5 1384 if (!is_edp(intel_dp))
adddaaf4 1385 return false;
bd943159
KP		 1386
1387 intel_dp->want_panel_vdd = true;
99ea7127 1388
4be73780 1389 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1390 return need_to_disable;
b0665d57 1391
4e6e1a54
ID		 1392 power_domain = intel_display_port_power_domain(intel_encoder);
1393 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1394
b0665d57 1395 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1396
4be73780
DV		 1397 if (!edp_have_panel_power(intel_dp))
1398 wait_panel_power_cycle(intel_dp);
99ea7127 1399
453c5420 1400 pp = ironlake_get_pp_control(intel_dp);
5d613501 1401 pp |= EDP_FORCE_VDD;
ebf33b18 1402
bf13e81b
JN		 1403 pp_stat_reg = _pp_stat_reg(intel_dp);
1404 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1405
1406 I915_WRITE(pp_ctrl_reg, pp);
1407 POSTING_READ(pp_ctrl_reg);
1408 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1409 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1410 /*
1411 * If the panel wasn't on, delay before accessing aux channel
1412 */
4be73780 1413 if (!edp_have_panel_power(intel_dp)) {
bd943159 1414 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1415 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1416 }
adddaaf4
JN		 1417
1418 return need_to_disable;
1419}
1420
951468f3
VS		 1421/*
1422 * Must be paired with intel_edp_panel_vdd_off() or
1423 * intel_edp_panel_off().
1424 * Nested calls to these functions are not allowed since
1425 * we drop the lock. Caller must use some higher level
1426 * locking to prevent nested calls from other threads.
1427 */
b80d6c78 1428void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1429{
c695b6b6 1430 bool vdd;
adddaaf4 1431
c695b6b6
VS		 1432 if (!is_edp(intel_dp))
1433 return;
1434
773538e8 1435 pps_lock(intel_dp);
c695b6b6 1436 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1437 pps_unlock(intel_dp);
c695b6b6
VS		 1438
1439 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1440}
1441
4be73780 1442static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1443{
30add22d 1444 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1445 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1446 struct intel_digital_port *intel_dig_port =
1447 dp_to_dig_port(intel_dp);
1448 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1449 enum intel_display_power_domain power_domain;
5d613501 1450 u32 pp;
453c5420 1451 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1452
e39b999a 1453 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1454
15e899a0 1455 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1456
15e899a0 1457 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1458 return;
b0665d57 1459
be2c9196 1460 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1461
be2c9196
VS		 1462 pp = ironlake_get_pp_control(intel_dp);
1463 pp &= ~EDP_FORCE_VDD;
453c5420 1464
be2c9196
VS		 1465 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1466 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1467
be2c9196
VS		 1468 I915_WRITE(pp_ctrl_reg, pp);
1469 POSTING_READ(pp_ctrl_reg);
99ea7127 1470
be2c9196
VS		 1471 /* Make sure sequencer is idle before allowing subsequent activity */
1472 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1473 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1474
be2c9196
VS		 1475 if ((pp & POWER_TARGET_ON) == 0)
1476 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1477
be2c9196
VS		 1478 power_domain = intel_display_port_power_domain(intel_encoder);
1479 intel_display_power_put(dev_priv, power_domain);
bd943159 1480}
5d613501 1481
4be73780 1482static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1483{
1484 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1485 struct intel_dp, panel_vdd_work);
bd943159 1486
773538e8 1487 pps_lock(intel_dp);
15e899a0
VS		 1488 if (!intel_dp->want_panel_vdd)
1489 edp_panel_vdd_off_sync(intel_dp);
773538e8 1490 pps_unlock(intel_dp);
bd943159
KP		 1491}
1492
aba86890
ID		 1493static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1494{
1495 unsigned long delay;
1496
1497 /*
1498 * Queue the timer to fire a long time from now (relative to the power
1499 * down delay) to keep the panel power up across a sequence of
1500 * operations.
1501 */
1502 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1503 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1504}
1505
951468f3
VS		 1506/*
1507 * Must be paired with edp_panel_vdd_on().
1508 * Must hold pps_mutex around the whole on/off sequence.
1509 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1510 */
4be73780 1511static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1512{
e39b999a
VS		 1513 struct drm_i915_private *dev_priv =
1514 intel_dp_to_dev(intel_dp)->dev_private;
1515
1516 lockdep_assert_held(&dev_priv->pps_mutex);
1517
97af61f5
KP		 1518 if (!is_edp(intel_dp))
1519 return;
5d613501 1520
bd943159 1521 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1522
bd943159
KP		 1523 intel_dp->want_panel_vdd = false;
1524
aba86890 1525 if (sync)
4be73780 1526 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1527 else
1528 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1529}
1530
951468f3
VS		 1531/*
1532 * Must be paired with intel_edp_panel_vdd_on().
1533 * Nested calls to these functions are not allowed since
1534 * we drop the lock. Caller must use some higher level
1535 * locking to prevent nested calls from other threads.
1536 */
1e0560e0
VS		 1537static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1538{
e39b999a
VS		 1539 if (!is_edp(intel_dp))
1540 return;
1541
773538e8 1542 pps_lock(intel_dp);
1e0560e0 1543 edp_panel_vdd_off(intel_dp, sync);
773538e8 1544 pps_unlock(intel_dp);
1e0560e0
VS		 1545}
1546
4be73780 1547void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1548{
30add22d 1549 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1550 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1551 u32 pp;
453c5420 1552 u32 pp_ctrl_reg;
9934c132 1553
97af61f5 1554 if (!is_edp(intel_dp))
bd943159 1555 return;
99ea7127
KP		 1556
1557 DRM_DEBUG_KMS("Turn eDP power on\n");
1558
773538e8 1559 pps_lock(intel_dp);
e39b999a 1560
4be73780 1561 if (edp_have_panel_power(intel_dp)) {
99ea7127 1562 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1563 goto out;
99ea7127 1564 }
9934c132 1565
4be73780 1566 wait_panel_power_cycle(intel_dp);
37c6c9b0 1567
bf13e81b 1568 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1569 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1570 if (IS_GEN5(dev)) {
1571 /* ILK workaround: disable reset around power sequence */
1572 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1573 I915_WRITE(pp_ctrl_reg, pp);
1574 POSTING_READ(pp_ctrl_reg);
05ce1a49 1575 }
37c6c9b0 1576
1c0ae80a 1577 pp |= POWER_TARGET_ON;
99ea7127
KP		 1578 if (!IS_GEN5(dev))
1579 pp |= PANEL_POWER_RESET;
1580
453c5420
JB		 1581 I915_WRITE(pp_ctrl_reg, pp);
1582 POSTING_READ(pp_ctrl_reg);
9934c132 1583
4be73780 1584 wait_panel_on(intel_dp);
dce56b3c 1585 intel_dp->last_power_on = jiffies;
9934c132 1586
05ce1a49
KP		 1587 if (IS_GEN5(dev)) {
1588 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1589 I915_WRITE(pp_ctrl_reg, pp);
1590 POSTING_READ(pp_ctrl_reg);
05ce1a49 1591 }
e39b999a
VS		 1592
1593 out:
773538e8 1594 pps_unlock(intel_dp);
9934c132
JB		 1595}
1596
4be73780 1597void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1598{
4e6e1a54
ID		 1599 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1600 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1601 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1602 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1603 enum intel_display_power_domain power_domain;
99ea7127 1604 u32 pp;
453c5420 1605 u32 pp_ctrl_reg;
9934c132 1606
97af61f5
KP		 1607 if (!is_edp(intel_dp))
1608 return;
37c6c9b0 1609
99ea7127 1610 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1611
773538e8 1612 pps_lock(intel_dp);
e39b999a 1613
24f3e092
JN		 1614 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1615
453c5420 1616 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1617 /* We need to switch off panel power _and_ force vdd, for otherwise some
1618 * panels get very unhappy and cease to work. */
b3064154
PJ		 1619 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1620 EDP_BLC_ENABLE);
453c5420 1621
bf13e81b 1622 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1623
849e39f5
PZ		 1624 intel_dp->want_panel_vdd = false;
1625
453c5420
JB		 1626 I915_WRITE(pp_ctrl_reg, pp);
1627 POSTING_READ(pp_ctrl_reg);
9934c132 1628
dce56b3c 1629 intel_dp->last_power_cycle = jiffies;
4be73780 1630 wait_panel_off(intel_dp);
849e39f5
PZ		 1631
1632 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1633 power_domain = intel_display_port_power_domain(intel_encoder);
1634 intel_display_power_put(dev_priv, power_domain);
e39b999a 1635
773538e8 1636 pps_unlock(intel_dp);
9934c132
JB		 1637}
1638
1250d107
JN		 1639/* Enable backlight in the panel power control. */
1640static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1641{
da63a9f2
PZ		 1642 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1643 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1644 struct drm_i915_private *dev_priv = dev->dev_private;
1645 u32 pp;
453c5420 1646 u32 pp_ctrl_reg;
32f9d658 1647
01cb9ea6
JB		 1648 /*
1649 * If we enable the backlight right away following a panel power
1650 * on, we may see slight flicker as the panel syncs with the eDP
1651 * link. So delay a bit to make sure the image is solid before
1652 * allowing it to appear.
1653 */
4be73780 1654 wait_backlight_on(intel_dp);
e39b999a 1655
773538e8 1656 pps_lock(intel_dp);
e39b999a 1657
453c5420 1658 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1659 pp |= EDP_BLC_ENABLE;
453c5420 1660
bf13e81b 1661 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1662
1663 I915_WRITE(pp_ctrl_reg, pp);
1664 POSTING_READ(pp_ctrl_reg);
e39b999a 1665
773538e8 1666 pps_unlock(intel_dp);
32f9d658
ZW		 1667}
1668
1250d107
JN		 1669/* Enable backlight PWM and backlight PP control. */
1670void intel_edp_backlight_on(struct intel_dp *intel_dp)
1671{
1672 if (!is_edp(intel_dp))
1673 return;
1674
1675 DRM_DEBUG_KMS("\n");
1676
1677 intel_panel_enable_backlight(intel_dp->attached_connector);
1678 _intel_edp_backlight_on(intel_dp);
1679}
1680
1681/* Disable backlight in the panel power control. */
1682static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1683{
30add22d 1684 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1685 struct drm_i915_private *dev_priv = dev->dev_private;
1686 u32 pp;
453c5420 1687 u32 pp_ctrl_reg;
32f9d658 1688
f01eca2e
KP		 1689 if (!is_edp(intel_dp))
1690 return;
1691
773538e8 1692 pps_lock(intel_dp);
e39b999a 1693
453c5420 1694 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1695 pp &= ~EDP_BLC_ENABLE;
453c5420 1696
bf13e81b 1697 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1698
1699 I915_WRITE(pp_ctrl_reg, pp);
1700 POSTING_READ(pp_ctrl_reg);
f7d2323c 1701
773538e8 1702 pps_unlock(intel_dp);
e39b999a
VS		 1703
1704 intel_dp->last_backlight_off = jiffies;
f7d2323c 1705 edp_wait_backlight_off(intel_dp);
1250d107 1706}
f7d2323c 1707
1250d107
JN		 1708/* Disable backlight PP control and backlight PWM. */
1709void intel_edp_backlight_off(struct intel_dp *intel_dp)
1710{
1711 if (!is_edp(intel_dp))
1712 return;
1713
1714 DRM_DEBUG_KMS("\n");
f7d2323c 1715
1250d107 1716 _intel_edp_backlight_off(intel_dp);
f7d2323c 1717 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1718}
a4fc5ed6 1719
73580fb7
JN		 1720/*
1721 * Hook for controlling the panel power control backlight through the bl_power
1722 * sysfs attribute. Take care to handle multiple calls.
1723 */
1724static void intel_edp_backlight_power(struct intel_connector *connector,
1725 bool enable)
1726{
1727 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1728 bool is_enabled;
1729
773538e8 1730 pps_lock(intel_dp);
e39b999a 1731 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1732 pps_unlock(intel_dp);
73580fb7
JN		 1733
1734 if (is_enabled == enable)
1735 return;
1736
23ba9373
JN		 1737 DRM_DEBUG_KMS("panel power control backlight %s\n",
1738 enable ? "enable" : "disable");
73580fb7
JN		 1739
1740 if (enable)
1741 _intel_edp_backlight_on(intel_dp);
1742 else
1743 _intel_edp_backlight_off(intel_dp);
1744}
1745
2bd2ad64 1746static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1747{
da63a9f2
PZ		 1748 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1749 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1750 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1751 struct drm_i915_private *dev_priv = dev->dev_private;
1752 u32 dpa_ctl;
1753
2bd2ad64
DV		 1754 assert_pipe_disabled(dev_priv,
1755 to_intel_crtc(crtc)->pipe);
1756
d240f20f
JB		 1757 DRM_DEBUG_KMS("\n");
1758 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1759 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1760 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1761
1762 /* We don't adjust intel_dp->DP while tearing down the link, to
1763 * facilitate link retraining (e.g. after hotplug). Hence clear all
1764 * enable bits here to ensure that we don't enable too much. */
1765 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1766 intel_dp->DP |= DP_PLL_ENABLE;
1767 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1768 POSTING_READ(DP_A);
1769 udelay(200);
d240f20f
JB		 1770}
1771
2bd2ad64 1772static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1773{
da63a9f2
PZ		 1774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1775 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1776 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1777 struct drm_i915_private *dev_priv = dev->dev_private;
1778 u32 dpa_ctl;
1779
2bd2ad64
DV		 1780 assert_pipe_disabled(dev_priv,
1781 to_intel_crtc(crtc)->pipe);
1782
d240f20f 1783 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1784 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1785 "dp pll off, should be on\n");
1786 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1787
1788 /* We can't rely on the value tracked for the DP register in
1789 * intel_dp->DP because link_down must not change that (otherwise link
1790 * re-training will fail. */
298b0b39 1791 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1792 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1793 POSTING_READ(DP_A);
d240f20f
JB		 1794 udelay(200);
1795}
1796
c7ad3810 1797/* If the sink supports it, try to set the power state appropriately */
c19b0669 1798void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1799{
1800 int ret, i;
1801
1802 /* Should have a valid DPCD by this point */
1803 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1804 return;
1805
1806 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1807 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1808 DP_SET_POWER_D3);
c7ad3810
JB		 1809 } else {
1810 /*
1811 * When turning on, we need to retry for 1ms to give the sink
1812 * time to wake up.
1813 */
1814 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1815 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1816 DP_SET_POWER_D0);
c7ad3810
JB		 1817 if (ret == 1)
1818 break;
1819 msleep(1);
1820 }
1821 }
f9cac721
JN		 1822
1823 if (ret != 1)
1824 DRM_DEBUG_KMS("failed to %s sink power state\n",
1825 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1826}
1827
19d8fe15
DV		 1828static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1829 enum pipe *pipe)
d240f20f 1830{
19d8fe15 1831 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1832 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1833 struct drm_device *dev = encoder->base.dev;
1834 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1835 enum intel_display_power_domain power_domain;
1836 u32 tmp;
1837
1838 power_domain = intel_display_port_power_domain(encoder);
1839 if (!intel_display_power_enabled(dev_priv, power_domain))
1840 return false;
1841
1842 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1843
1844 if (!(tmp & DP_PORT_EN))
1845 return false;
1846
bc7d38a4 1847 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1848 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1849 } else if (IS_CHERRYVIEW(dev)) {
1850 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1851 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1852 *pipe = PORT_TO_PIPE(tmp);
1853 } else {
1854 u32 trans_sel;
1855 u32 trans_dp;
1856 int i;
1857
1858 switch (intel_dp->output_reg) {
1859 case PCH_DP_B:
1860 trans_sel = TRANS_DP_PORT_SEL_B;
1861 break;
1862 case PCH_DP_C:
1863 trans_sel = TRANS_DP_PORT_SEL_C;
1864 break;
1865 case PCH_DP_D:
1866 trans_sel = TRANS_DP_PORT_SEL_D;
1867 break;
1868 default:
1869 return true;
1870 }
1871
055e393f 1872 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1873 trans_dp = I915_READ(TRANS_DP_CTL(i));
1874 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1875 *pipe = i;
1876 return true;
1877 }
1878 }
19d8fe15 1879
4a0833ec
DV		 1880 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1881 intel_dp->output_reg);
1882 }
d240f20f 1883
19d8fe15
DV		 1884 return true;
1885}
d240f20f 1886
045ac3b5
JB		 1887static void intel_dp_get_config(struct intel_encoder *encoder,
1888 struct intel_crtc_config *pipe_config)
1889{
1890 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1891 u32 tmp, flags = 0;
63000ef6
XZ		 1892 struct drm_device *dev = encoder->base.dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 enum port port = dp_to_dig_port(intel_dp)->port;
1895 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1896 int dotclock;
045ac3b5 1897
9ed109a7
DV		 1898 tmp = I915_READ(intel_dp->output_reg);
1899 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1900 pipe_config->has_audio = true;
1901
63000ef6 1902 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1903 if (tmp & DP_SYNC_HS_HIGH)
1904 flags |= DRM_MODE_FLAG_PHSYNC;
1905 else
1906 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1907
63000ef6
XZ		 1908 if (tmp & DP_SYNC_VS_HIGH)
1909 flags |= DRM_MODE_FLAG_PVSYNC;
1910 else
1911 flags |= DRM_MODE_FLAG_NVSYNC;
1912 } else {
1913 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1914 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1915 flags |= DRM_MODE_FLAG_PHSYNC;
1916 else
1917 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1918
63000ef6
XZ		 1919 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1920 flags |= DRM_MODE_FLAG_PVSYNC;
1921 else
1922 flags |= DRM_MODE_FLAG_NVSYNC;
1923 }
045ac3b5
JB		 1924
1925 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1926
eb14cb74
VS		 1927 pipe_config->has_dp_encoder = true;
1928
1929 intel_dp_get_m_n(crtc, pipe_config);
1930
18442d08 1931 if (port == PORT_A) {
f1f644dc
JB		 1932 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1933 pipe_config->port_clock = 162000;
1934 else
1935 pipe_config->port_clock = 270000;
1936 }
18442d08
VS		 1937
1938 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1939 &pipe_config->dp_m_n);
1940
1941 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1942 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1943
241bfc38 1944 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1945
c6cd2ee2
JN		 1946 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1947 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1948 /*
1949 * This is a big fat ugly hack.
1950 *
1951 * Some machines in UEFI boot mode provide us a VBT that has 18
1952 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1953 * unknown we fail to light up. Yet the same BIOS boots up with
1954 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1955 * max, not what it tells us to use.
1956 *
1957 * Note: This will still be broken if the eDP panel is not lit
1958 * up by the BIOS, and thus we can't get the mode at module
1959 * load.
1960 */
1961 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1962 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1963 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1964 }
045ac3b5
JB		 1965}
1966
34eb7579 1967static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1968{
34eb7579 1969 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1970}
1971
2b28bb1b
RV		 1972static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1973{
1974 struct drm_i915_private *dev_priv = dev->dev_private;
1975
18b5992c 1976 if (!HAS_PSR(dev))
2b28bb1b
RV		 1977 return false;
1978
18b5992c 1979 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1980}
1981
1982static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1983 struct edp_vsc_psr *vsc_psr)
1984{
1985 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1986 struct drm_device *dev = dig_port->base.base.dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1989 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1990 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1991 uint32_t *data = (uint32_t *) vsc_psr;
1992 unsigned int i;
1993
1994 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1995 the video DIP being updated before program video DIP data buffer
1996 registers for DIP being updated. */
1997 I915_WRITE(ctl_reg, 0);
1998 POSTING_READ(ctl_reg);
1999
2000 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2001 if (i < sizeof(struct edp_vsc_psr))
2002 I915_WRITE(data_reg + i, *data++);
2003 else
2004 I915_WRITE(data_reg + i, 0);
2005 }
2006
2007 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2008 POSTING_READ(ctl_reg);
2009}
2010
2011static void intel_edp_psr_setup(struct intel_dp *intel_dp)
2012{
2013 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 struct edp_vsc_psr psr_vsc;
2016
2b28bb1b
RV		 2017 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2018 memset(&psr_vsc, 0, sizeof(psr_vsc));
2019 psr_vsc.sdp_header.HB0 = 0;
2020 psr_vsc.sdp_header.HB1 = 0x7;
2021 psr_vsc.sdp_header.HB2 = 0x2;
2022 psr_vsc.sdp_header.HB3 = 0x8;
2023 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2024
2025 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 2026 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 2027 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 2028}
2029
2030static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2031{
0e0ae652
RV		 2032 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2033 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2034 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2035 uint32_t aux_clock_divider;
2b28bb1b
RV		 2036 int precharge = 0x3;
2037 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2038 bool only_standby = false;
2b28bb1b 2039
ec5b01dd
DL		 2040 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2041
0e0ae652
RV		 2042 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2043 only_standby = true;
2044
2b28bb1b 2045 /* Enable PSR in sink */
0e0ae652 2046 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2047 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2048 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2049 else
9d1a1031
JN		 2050 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2051 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2052
2053 /* Setup AUX registers */
18b5992c
BW		 2054 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2055 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2056 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2057 DP_AUX_CH_CTL_TIME_OUT_400us |
2058 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2059 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2060 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2061}
2062
2063static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2064{
0e0ae652
RV		 2065 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2066 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 uint32_t max_sleep_time = 0x1f;
2069 uint32_t idle_frames = 1;
2070 uint32_t val = 0x0;
ed8546ac 2071 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2072 bool only_standby = false;
2073
2074 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2075 only_standby = true;
2b28bb1b 2076
0e0ae652 2077 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2078 val |= EDP_PSR_LINK_STANDBY;
2079 val |= EDP_PSR_TP2_TP3_TIME_0us;
2080 val |= EDP_PSR_TP1_TIME_0us;
2081 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2082 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2083 } else
2084 val |= EDP_PSR_LINK_DISABLE;
2085
18b5992c 2086 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2087 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2088 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2089 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2090 EDP_PSR_ENABLE);
2091}
2092
3f51e471
RV		 2093static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2094{
2095 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2096 struct drm_device *dev = dig_port->base.base.dev;
2097 struct drm_i915_private *dev_priv = dev->dev_private;
2098 struct drm_crtc *crtc = dig_port->base.base.crtc;
2099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2100
f0355c4a 2101 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2102 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2103 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2104
a031d709
RV		 2105 dev_priv->psr.source_ok = false;
2106
9ca15301 2107 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2108 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2109 return false;
2110 }
2111
d330a953 2112 if (!i915.enable_psr) {
105b7c11 2113 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2114 return false;
2115 }
2116
4c8c7000
RV		 2117 /* Below limitations aren't valid for Broadwell */
2118 if (IS_BROADWELL(dev))
2119 goto out;
2120
3f51e471
RV		 2121 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2122 S3D_ENABLE) {
2123 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2124 return false;
2125 }
2126
ca73b4f0 2127 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2128 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2129 return false;
2130 }
2131
4c8c7000 2132 out:
a031d709 2133 dev_priv->psr.source_ok = true;
3f51e471
RV		 2134 return true;
2135}
2136
3d739d92 2137static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2138{
7c8f8a70
RV		 2139 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2140 struct drm_device *dev = intel_dig_port->base.base.dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2142
3638379c
DV		 2143 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2144 WARN_ON(dev_priv->psr.active);
f0355c4a 2145 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2146
2b28bb1b
RV		 2147 /* Enable PSR on the panel */
2148 intel_edp_psr_enable_sink(intel_dp);
2149
2150 /* Enable PSR on the host */
2151 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2152
7c8f8a70 2153 dev_priv->psr.active = true;
2b28bb1b
RV		 2154}
2155
3d739d92
RV		 2156void intel_edp_psr_enable(struct intel_dp *intel_dp)
2157{
2158 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2159 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2160
4704c573
RV		 2161 if (!HAS_PSR(dev)) {
2162 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2163 return;
2164 }
2165
34eb7579
RV		 2166 if (!is_edp_psr(intel_dp)) {
2167 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2168 return;
2169 }
2170
f0355c4a 2171 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2172 if (dev_priv->psr.enabled) {
2173 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 2174 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 2175 return;
2176 }
2177
9ca15301
DV		 2178 dev_priv->psr.busy_frontbuffer_bits = 0;
2179
16487254
RV		 2180 /* Setup PSR once */
2181 intel_edp_psr_setup(intel_dp);
2182
7c8f8a70 2183 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 2184 dev_priv->psr.enabled = intel_dp;
f0355c4a 2185 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2186}
2187
2b28bb1b
RV		 2188void intel_edp_psr_disable(struct intel_dp *intel_dp)
2189{
2190 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2191 struct drm_i915_private *dev_priv = dev->dev_private;
2192
f0355c4a
DV		 2193 mutex_lock(&dev_priv->psr.lock);
2194 if (!dev_priv->psr.enabled) {
2195 mutex_unlock(&dev_priv->psr.lock);
2196 return;
2197 }
2198
3638379c
DV		 2199 if (dev_priv->psr.active) {
2200 I915_WRITE(EDP_PSR_CTL(dev),
2201 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2202
2203 /* Wait till PSR is idle */
2204 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2205 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2206 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2207
3638379c
DV		 2208 dev_priv->psr.active = false;
2209 } else {
2210 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2211 }
7c8f8a70 2212
2807cf69 2213 dev_priv->psr.enabled = NULL;
f0355c4a 2214 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2215
2216 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2217}
2218
f02a326e 2219static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2220{
2221 struct drm_i915_private *dev_priv =
2222 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2223 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2224
f0355c4a
DV		 2225 mutex_lock(&dev_priv->psr.lock);
2226 intel_dp = dev_priv->psr.enabled;
2227
2807cf69 2228 if (!intel_dp)
f0355c4a 2229 goto unlock;
2807cf69 2230
9ca15301
DV		 2231 /*
2232 * The delayed work can race with an invalidate hence we need to
2233 * recheck. Since psr_flush first clears this and then reschedules we
2234 * won't ever miss a flush when bailing out here.
2235 */
2236 if (dev_priv->psr.busy_frontbuffer_bits)
2237 goto unlock;
2238
2239 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2240unlock:
2241 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2242}
2243
9ca15301 2244static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2245{
2246 struct drm_i915_private *dev_priv = dev->dev_private;
2247
3638379c
DV		 2248 if (dev_priv->psr.active) {
2249 u32 val = I915_READ(EDP_PSR_CTL(dev));
2250
2251 WARN_ON(!(val & EDP_PSR_ENABLE));
2252
2253 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2254
2255 dev_priv->psr.active = false;
2256 }
7c8f8a70 2257
9ca15301
DV		 2258}
2259
2260void intel_edp_psr_invalidate(struct drm_device *dev,
2261 unsigned frontbuffer_bits)
2262{
2263 struct drm_i915_private *dev_priv = dev->dev_private;
2264 struct drm_crtc *crtc;
2265 enum pipe pipe;
2266
9ca15301
DV		 2267 mutex_lock(&dev_priv->psr.lock);
2268 if (!dev_priv->psr.enabled) {
2269 mutex_unlock(&dev_priv->psr.lock);
2270 return;
2271 }
2272
2273 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2274 pipe = to_intel_crtc(crtc)->pipe;
2275
2276 intel_edp_psr_do_exit(dev);
2277
2278 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2279
2280 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2281 mutex_unlock(&dev_priv->psr.lock);
2282}
2283
2284void intel_edp_psr_flush(struct drm_device *dev,
2285 unsigned frontbuffer_bits)
2286{
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288 struct drm_crtc *crtc;
2289 enum pipe pipe;
2290
9ca15301
DV		 2291 mutex_lock(&dev_priv->psr.lock);
2292 if (!dev_priv->psr.enabled) {
2293 mutex_unlock(&dev_priv->psr.lock);
2294 return;
2295 }
2296
2297 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2298 pipe = to_intel_crtc(crtc)->pipe;
2299 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2300
2301 /*
2302 * On Haswell sprite plane updates don't result in a psr invalidating
2303 * signal in the hardware. Which means we need to manually fake this in
2304 * software for all flushes, not just when we've seen a preceding
2305 * invalidation through frontbuffer rendering.
2306 */
2307 if (IS_HASWELL(dev) &&
2308 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2309 intel_edp_psr_do_exit(dev);
2310
2311 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2312 schedule_delayed_work(&dev_priv->psr.work,
2313 msecs_to_jiffies(100));
f0355c4a 2314 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2315}
2316
2317void intel_edp_psr_init(struct drm_device *dev)
2318{
2319 struct drm_i915_private *dev_priv = dev->dev_private;
2320
7c8f8a70 2321 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2322 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2323}
2324
e8cb4558 2325static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2326{
e8cb4558 2327 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2328 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2329
2330 /* Make sure the panel is off before trying to change the mode. But also
2331 * ensure that we have vdd while we switch off the panel. */
24f3e092 2332 intel_edp_panel_vdd_on(intel_dp);
4be73780 2333 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2334 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2335 intel_edp_panel_off(intel_dp);
3739850b 2336
08aff3fe
VS		 2337 /* disable the port before the pipe on g4x */
2338 if (INTEL_INFO(dev)->gen < 5)
3739850b 2339 intel_dp_link_down(intel_dp);
d240f20f
JB		 2340}
2341
08aff3fe 2342static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2343{
2bd2ad64 2344 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2345 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2346
49277c31 2347 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2348 if (port == PORT_A)
2349 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2350}
2351
2352static void vlv_post_disable_dp(struct intel_encoder *encoder)
2353{
2354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2355
2356 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2357}
2358
580d3811
VS		 2359static void chv_post_disable_dp(struct intel_encoder *encoder)
2360{
2361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2362 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2363 struct drm_device *dev = encoder->base.dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365 struct intel_crtc *intel_crtc =
2366 to_intel_crtc(encoder->base.crtc);
2367 enum dpio_channel ch = vlv_dport_to_channel(dport);
2368 enum pipe pipe = intel_crtc->pipe;
2369 u32 val;
2370
2371 intel_dp_link_down(intel_dp);
2372
2373 mutex_lock(&dev_priv->dpio_lock);
2374
2375 /* Propagate soft reset to data lane reset */
97fd4d5c 2376 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2377 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2378 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2379
97fd4d5c
VS		 2380 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2381 val |= CHV_PCS_REQ_SOFTRESET_EN;
2382 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2383
2384 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2385 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2386 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2387
2388 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2389 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2390 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2391
2392 mutex_unlock(&dev_priv->dpio_lock);
2393}
2394
7b13b58a
VS		 2395static void
2396_intel_dp_set_link_train(struct intel_dp *intel_dp,
2397 uint32_t *DP,
2398 uint8_t dp_train_pat)
2399{
2400 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2401 struct drm_device *dev = intel_dig_port->base.base.dev;
2402 struct drm_i915_private *dev_priv = dev->dev_private;
2403 enum port port = intel_dig_port->port;
2404
2405 if (HAS_DDI(dev)) {
2406 uint32_t temp = I915_READ(DP_TP_CTL(port));
2407
2408 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2409 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2410 else
2411 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2412
2413 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2414 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2415 case DP_TRAINING_PATTERN_DISABLE:
2416 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2417
2418 break;
2419 case DP_TRAINING_PATTERN_1:
2420 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2421 break;
2422 case DP_TRAINING_PATTERN_2:
2423 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2424 break;
2425 case DP_TRAINING_PATTERN_3:
2426 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2427 break;
2428 }
2429 I915_WRITE(DP_TP_CTL(port), temp);
2430
2431 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2432 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2433
2434 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2435 case DP_TRAINING_PATTERN_DISABLE:
2436 *DP |= DP_LINK_TRAIN_OFF_CPT;
2437 break;
2438 case DP_TRAINING_PATTERN_1:
2439 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2440 break;
2441 case DP_TRAINING_PATTERN_2:
2442 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2443 break;
2444 case DP_TRAINING_PATTERN_3:
2445 DRM_ERROR("DP training pattern 3 not supported\n");
2446 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2447 break;
2448 }
2449
2450 } else {
2451 if (IS_CHERRYVIEW(dev))
2452 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2453 else
2454 *DP &= ~DP_LINK_TRAIN_MASK;
2455
2456 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2457 case DP_TRAINING_PATTERN_DISABLE:
2458 *DP |= DP_LINK_TRAIN_OFF;
2459 break;
2460 case DP_TRAINING_PATTERN_1:
2461 *DP |= DP_LINK_TRAIN_PAT_1;
2462 break;
2463 case DP_TRAINING_PATTERN_2:
2464 *DP |= DP_LINK_TRAIN_PAT_2;
2465 break;
2466 case DP_TRAINING_PATTERN_3:
2467 if (IS_CHERRYVIEW(dev)) {
2468 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2469 } else {
2470 DRM_ERROR("DP training pattern 3 not supported\n");
2471 *DP |= DP_LINK_TRAIN_PAT_2;
2472 }
2473 break;
2474 }
2475 }
2476}
2477
2478static void intel_dp_enable_port(struct intel_dp *intel_dp)
2479{
2480 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2481 struct drm_i915_private *dev_priv = dev->dev_private;
2482
2483 intel_dp->DP |= DP_PORT_EN;
2484
2485 /* enable with pattern 1 (as per spec) */
2486 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2487 DP_TRAINING_PATTERN_1);
2488
2489 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2490 POSTING_READ(intel_dp->output_reg);
2491}
2492
e8cb4558 2493static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2494{
e8cb4558
DV		 2495 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2496 struct drm_device *dev = encoder->base.dev;
2497 struct drm_i915_private *dev_priv = dev->dev_private;
2498 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2499
0c33d8d7
DV		 2500 if (WARN_ON(dp_reg & DP_PORT_EN))
2501 return;
5d613501 2502
7b13b58a 2503 intel_dp_enable_port(intel_dp);
24f3e092 2504 intel_edp_panel_vdd_on(intel_dp);
4be73780 2505 intel_edp_panel_on(intel_dp);
1e0560e0 2506 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2507 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2508 intel_dp_start_link_train(intel_dp);
33a34e4e 2509 intel_dp_complete_link_train(intel_dp);
3ab9c637 2510 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2511}
89b667f8 2512
ecff4f3b
JN		 2513static void g4x_enable_dp(struct intel_encoder *encoder)
2514{
828f5c6e
JN		 2515 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2516
ecff4f3b 2517 intel_enable_dp(encoder);
4be73780 2518 intel_edp_backlight_on(intel_dp);
ab1f90f9 2519}
89b667f8 2520
ab1f90f9
JN		 2521static void vlv_enable_dp(struct intel_encoder *encoder)
2522{
828f5c6e
JN		 2523 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2524
4be73780 2525 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2526}
2527
ecff4f3b 2528static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2529{
2530 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2531 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2532
8ac33ed3
DV		 2533 intel_dp_prepare(encoder);
2534
d41f1efb
DV		 2535 /* Only ilk+ has port A */
2536 if (dport->port == PORT_A) {
2537 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2538 ironlake_edp_pll_on(intel_dp);
d41f1efb 2539 }
ab1f90f9
JN		 2540}
2541
a4a5d2f8
VS		 2542static void vlv_steal_power_sequencer(struct drm_device *dev,
2543 enum pipe pipe)
2544{
2545 struct drm_i915_private *dev_priv = dev->dev_private;
2546 struct intel_encoder *encoder;
2547
2548 lockdep_assert_held(&dev_priv->pps_mutex);
2549
2550 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2551 base.head) {
2552 struct intel_dp *intel_dp;
773538e8 2553 enum port port;
a4a5d2f8
VS		 2554
2555 if (encoder->type != INTEL_OUTPUT_EDP)
2556 continue;
2557
2558 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2559 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2560
2561 if (intel_dp->pps_pipe != pipe)
2562 continue;
2563
2564 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2565 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2566
2567 /* make sure vdd is off before we steal it */
2568 edp_panel_vdd_off_sync(intel_dp);
2569
2570 intel_dp->pps_pipe = INVALID_PIPE;
2571 }
2572}
2573
2574static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2575{
2576 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2577 struct intel_encoder *encoder = &intel_dig_port->base;
2578 struct drm_device *dev = encoder->base.dev;
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2581 struct edp_power_seq power_seq;
2582
2583 lockdep_assert_held(&dev_priv->pps_mutex);
2584
2585 if (intel_dp->pps_pipe == crtc->pipe)
2586 return;
2587
2588 /*
2589 * If another power sequencer was being used on this
2590 * port previously make sure to turn off vdd there while
2591 * we still have control of it.
2592 */
2593 if (intel_dp->pps_pipe != INVALID_PIPE)
2594 edp_panel_vdd_off_sync(intel_dp);
2595
2596 /*
2597 * We may be stealing the power
2598 * sequencer from another port.
2599 */
2600 vlv_steal_power_sequencer(dev, crtc->pipe);
2601
2602 /* now it's all ours */
2603 intel_dp->pps_pipe = crtc->pipe;
2604
2605 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2606 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2607
2608 /* init power sequencer on this pipe and port */
2609 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2610 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2611 &power_seq);
2612}
2613
ab1f90f9 2614static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2615{
2bd2ad64 2616 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2617 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2618 struct drm_device *dev = encoder->base.dev;
89b667f8 2619 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2620 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2621 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2622 int pipe = intel_crtc->pipe;
2623 u32 val;
a4fc5ed6 2624
ab1f90f9 2625 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2626
ab3c759a 2627 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2628 val = 0;
2629 if (pipe)
2630 val |= (1<<21);
2631 else
2632 val &= ~(1<<21);
2633 val |= 0x001000c4;
ab3c759a
CML		 2634 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2635 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2636 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2637
ab1f90f9
JN		 2638 mutex_unlock(&dev_priv->dpio_lock);
2639
2cac613b 2640 if (is_edp(intel_dp)) {
773538e8 2641 pps_lock(intel_dp);
a4a5d2f8 2642 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2643 pps_unlock(intel_dp);
2cac613b 2644 }
bf13e81b 2645
ab1f90f9
JN		 2646 intel_enable_dp(encoder);
2647
e4607fcf 2648 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2649}
2650
ecff4f3b 2651static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2652{
2653 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2654 struct drm_device *dev = encoder->base.dev;
2655 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2656 struct intel_crtc *intel_crtc =
2657 to_intel_crtc(encoder->base.crtc);
e4607fcf 2658 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2659 int pipe = intel_crtc->pipe;
89b667f8 2660
8ac33ed3
DV		 2661 intel_dp_prepare(encoder);
2662
89b667f8 2663 /* Program Tx lane resets to default */
0980a60f 2664 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2665 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2666 DPIO_PCS_TX_LANE2_RESET |
2667 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2668 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2669 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2670 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2671 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2672 DPIO_PCS_CLK_SOFT_RESET);
2673
2674 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2675 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2676 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2677 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2678 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2679}
2680
e4a1d846
CML		 2681static void chv_pre_enable_dp(struct intel_encoder *encoder)
2682{
2683 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2684 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2685 struct drm_device *dev = encoder->base.dev;
2686 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2687 struct intel_crtc *intel_crtc =
2688 to_intel_crtc(encoder->base.crtc);
2689 enum dpio_channel ch = vlv_dport_to_channel(dport);
2690 int pipe = intel_crtc->pipe;
2691 int data, i;
949c1d43 2692 u32 val;
e4a1d846 2693
e4a1d846 2694 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2695
2696 /* Deassert soft data lane reset*/
97fd4d5c 2697 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2698 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2699 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2700
2701 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2702 val |= CHV_PCS_REQ_SOFTRESET_EN;
2703 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2704
2705 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2706 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2707 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2708
97fd4d5c 2709 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2710 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2711 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2712
2713 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2714 for (i = 0; i < 4; i++) {
2715 /* Set the latency optimal bit */
2716 data = (i == 1) ? 0x0 : 0x6;
2717 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2718 data << DPIO_FRC_LATENCY_SHFIT);
2719
2720 /* Set the upar bit */
2721 data = (i == 1) ? 0x0 : 0x1;
2722 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2723 data << DPIO_UPAR_SHIFT);
2724 }
2725
2726 /* Data lane stagger programming */
2727 /* FIXME: Fix up value only after power analysis */
2728
2729 mutex_unlock(&dev_priv->dpio_lock);
2730
2731 if (is_edp(intel_dp)) {
773538e8 2732 pps_lock(intel_dp);
a4a5d2f8 2733 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2734 pps_unlock(intel_dp);
e4a1d846
CML		 2735 }
2736
2737 intel_enable_dp(encoder);
2738
2739 vlv_wait_port_ready(dev_priv, dport);
2740}
2741
9197c88b
VS		 2742static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2743{
2744 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2745 struct drm_device *dev = encoder->base.dev;
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct intel_crtc *intel_crtc =
2748 to_intel_crtc(encoder->base.crtc);
2749 enum dpio_channel ch = vlv_dport_to_channel(dport);
2750 enum pipe pipe = intel_crtc->pipe;
2751 u32 val;
2752
625695f8
VS		 2753 intel_dp_prepare(encoder);
2754
9197c88b
VS		 2755 mutex_lock(&dev_priv->dpio_lock);
2756
b9e5ac3c
VS		 2757 /* program left/right clock distribution */
2758 if (pipe != PIPE_B) {
2759 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2760 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2761 if (ch == DPIO_CH0)
2762 val |= CHV_BUFLEFTENA1_FORCE;
2763 if (ch == DPIO_CH1)
2764 val |= CHV_BUFRIGHTENA1_FORCE;
2765 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2766 } else {
2767 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2768 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2769 if (ch == DPIO_CH0)
2770 val |= CHV_BUFLEFTENA2_FORCE;
2771 if (ch == DPIO_CH1)
2772 val |= CHV_BUFRIGHTENA2_FORCE;
2773 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2774 }
2775
9197c88b
VS		 2776 /* program clock channel usage */
2777 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2778 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2779 if (pipe != PIPE_B)
2780 val &= ~CHV_PCS_USEDCLKCHANNEL;
2781 else
2782 val |= CHV_PCS_USEDCLKCHANNEL;
2783 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2784
2785 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2786 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2787 if (pipe != PIPE_B)
2788 val &= ~CHV_PCS_USEDCLKCHANNEL;
2789 else
2790 val |= CHV_PCS_USEDCLKCHANNEL;
2791 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2792
2793 /*
2794 * This a a bit weird since generally CL
2795 * matches the pipe, but here we need to
2796 * pick the CL based on the port.
2797 */
2798 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2799 if (pipe != PIPE_B)
2800 val &= ~CHV_CMN_USEDCLKCHANNEL;
2801 else
2802 val |= CHV_CMN_USEDCLKCHANNEL;
2803 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2804
2805 mutex_unlock(&dev_priv->dpio_lock);
2806}
2807
a4fc5ed6 2808/*
df0c237d
JB		 2809 * Native read with retry for link status and receiver capability reads for
2810 * cases where the sink may still be asleep.
9d1a1031
JN		 2811 *
2812 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2813 * supposed to retry 3 times per the spec.
a4fc5ed6 2814 */
9d1a1031
JN		 2815static ssize_t
2816intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2817 void *buffer, size_t size)
a4fc5ed6 2818{
9d1a1031
JN		 2819 ssize_t ret;
2820 int i;
61da5fab 2821
61da5fab 2822 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2823 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2824 if (ret == size)
2825 return ret;
61da5fab
JB		 2826 msleep(1);
2827 }
a4fc5ed6 2828
9d1a1031 2829 return ret;
a4fc5ed6
KP		 2830}
2831
2832/*
2833 * Fetch AUX CH registers 0x202 - 0x207 which contain
2834 * link status information
2835 */
2836static bool
93f62dad 2837intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2838{
9d1a1031
JN		 2839 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2840 DP_LANE0_1_STATUS,
2841 link_status,
2842 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2843}
2844
1100244e 2845/* These are source-specific values. */
a4fc5ed6 2846static uint8_t
1a2eb460 2847intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2848{
30add22d 2849 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2850 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2851
5a9d1f1a
DL		 2852 if (INTEL_INFO(dev)->gen >= 9)
2853 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2854 else if (IS_VALLEYVIEW(dev))
bd60018a 2855 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2856 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2857 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2858 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2859 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2860 else
bd60018a 2861 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2862}
2863
2864static uint8_t
2865intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2866{
30add22d 2867 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2868 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2869
5a9d1f1a
DL		 2870 if (INTEL_INFO(dev)->gen >= 9) {
2871 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2872 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2873 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2874 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2875 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2876 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2877 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2878 default:
2879 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2880 }
2881 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2882 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2883 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2884 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2885 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2886 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2887 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2888 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2889 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2890 default:
bd60018a 2891 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2892 }
e2fa6fba
P		 2893 } else if (IS_VALLEYVIEW(dev)) {
2894 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2895 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2896 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2897 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2898 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2899 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2900 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2901 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2902 default:
bd60018a 2903 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2904 }
bc7d38a4 2905 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2906 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2908 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2909 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2910 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2911 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2912 default:
bd60018a 2913 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2914 }
2915 } else {
2916 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2918 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2919 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2920 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2921 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2922 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2923 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2924 default:
bd60018a 2925 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2926 }
a4fc5ed6
KP		 2927 }
2928}
2929
e2fa6fba
P		 2930static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2931{
2932 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2935 struct intel_crtc *intel_crtc =
2936 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2937 unsigned long demph_reg_value, preemph_reg_value,
2938 uniqtranscale_reg_value;
2939 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2940 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2941 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2942
2943 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2944 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2945 preemph_reg_value = 0x0004000;
2946 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2948 demph_reg_value = 0x2B405555;
2949 uniqtranscale_reg_value = 0x552AB83A;
2950 break;
bd60018a 2951 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2952 demph_reg_value = 0x2B404040;
2953 uniqtranscale_reg_value = 0x5548B83A;
2954 break;
bd60018a 2955 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2956 demph_reg_value = 0x2B245555;
2957 uniqtranscale_reg_value = 0x5560B83A;
2958 break;
bd60018a 2959 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2960 demph_reg_value = 0x2B405555;
2961 uniqtranscale_reg_value = 0x5598DA3A;
2962 break;
2963 default:
2964 return 0;
2965 }
2966 break;
bd60018a 2967 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2968 preemph_reg_value = 0x0002000;
2969 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2970 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2971 demph_reg_value = 0x2B404040;
2972 uniqtranscale_reg_value = 0x5552B83A;
2973 break;
bd60018a 2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2975 demph_reg_value = 0x2B404848;
2976 uniqtranscale_reg_value = 0x5580B83A;
2977 break;
bd60018a 2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2979 demph_reg_value = 0x2B404040;
2980 uniqtranscale_reg_value = 0x55ADDA3A;
2981 break;
2982 default:
2983 return 0;
2984 }
2985 break;
bd60018a 2986 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2987 preemph_reg_value = 0x0000000;
2988 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2989 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2990 demph_reg_value = 0x2B305555;
2991 uniqtranscale_reg_value = 0x5570B83A;
2992 break;
bd60018a 2993 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2994 demph_reg_value = 0x2B2B4040;
2995 uniqtranscale_reg_value = 0x55ADDA3A;
2996 break;
2997 default:
2998 return 0;
2999 }
3000 break;
bd60018a 3001 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3002 preemph_reg_value = 0x0006000;
3003 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3004 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3005 demph_reg_value = 0x1B405555;
3006 uniqtranscale_reg_value = 0x55ADDA3A;
3007 break;
3008 default:
3009 return 0;
3010 }
3011 break;
3012 default:
3013 return 0;
3014 }
3015
0980a60f 3016 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3017 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3018 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3019 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3020 uniqtranscale_reg_value);
ab3c759a
CML		 3021 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3022 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3023 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3024 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3025 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3026
3027 return 0;
3028}
3029
e4a1d846
CML		 3030static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3031{
3032 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3035 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3036 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3037 uint8_t train_set = intel_dp->train_set[0];
3038 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3039 enum pipe pipe = intel_crtc->pipe;
3040 int i;
e4a1d846
CML		 3041
3042 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3043 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3044 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3046 deemph_reg_value = 128;
3047 margin_reg_value = 52;
3048 break;
bd60018a 3049 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3050 deemph_reg_value = 128;
3051 margin_reg_value = 77;
3052 break;
bd60018a 3053 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3054 deemph_reg_value = 128;
3055 margin_reg_value = 102;
3056 break;
bd60018a 3057 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3058 deemph_reg_value = 128;
3059 margin_reg_value = 154;
3060 /* FIXME extra to set for 1200 */
3061 break;
3062 default:
3063 return 0;
3064 }
3065 break;
bd60018a 3066 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3067 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3068 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3069 deemph_reg_value = 85;
3070 margin_reg_value = 78;
3071 break;
bd60018a 3072 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3073 deemph_reg_value = 85;
3074 margin_reg_value = 116;
3075 break;
bd60018a 3076 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3077 deemph_reg_value = 85;
3078 margin_reg_value = 154;
3079 break;
3080 default:
3081 return 0;
3082 }
3083 break;
bd60018a 3084 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3085 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3087 deemph_reg_value = 64;
3088 margin_reg_value = 104;
3089 break;
bd60018a 3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3091 deemph_reg_value = 64;
3092 margin_reg_value = 154;
3093 break;
3094 default:
3095 return 0;
3096 }
3097 break;
bd60018a 3098 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3099 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3101 deemph_reg_value = 43;
3102 margin_reg_value = 154;
3103 break;
3104 default:
3105 return 0;
3106 }
3107 break;
3108 default:
3109 return 0;
3110 }
3111
3112 mutex_lock(&dev_priv->dpio_lock);
3113
3114 /* Clear calc init */
1966e59e
VS		 3115 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3116 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3117 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3118
3119 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3120 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3121 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3122
3123 /* Program swing deemph */
f72df8db
VS		 3124 for (i = 0; i < 4; i++) {
3125 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3126 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3127 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3128 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3129 }
e4a1d846
CML		 3130
3131 /* Program swing margin */
f72df8db
VS		 3132 for (i = 0; i < 4; i++) {
3133 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3134 val &= ~DPIO_SWING_MARGIN000_MASK;
3135 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3136 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3137 }
e4a1d846
CML		 3138
3139 /* Disable unique transition scale */
f72df8db
VS		 3140 for (i = 0; i < 4; i++) {
3141 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3142 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3143 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3144 }
e4a1d846
CML		 3145
3146 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3147 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3148 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3149 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3150
3151 /*
3152 * The document said it needs to set bit 27 for ch0 and bit 26
3153 * for ch1. Might be a typo in the doc.
3154 * For now, for this unique transition scale selection, set bit
3155 * 27 for ch0 and ch1.
3156 */
f72df8db
VS		 3157 for (i = 0; i < 4; i++) {
3158 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3159 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3160 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3161 }
e4a1d846 3162
f72df8db
VS		 3163 for (i = 0; i < 4; i++) {
3164 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3165 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3166 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3167 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3168 }
e4a1d846
CML		 3169 }
3170
3171 /* Start swing calculation */
1966e59e
VS		 3172 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3173 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3174 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3175
3176 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3177 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3178 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3179
3180 /* LRC Bypass */
3181 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3182 val |= DPIO_LRC_BYPASS;
3183 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3184
3185 mutex_unlock(&dev_priv->dpio_lock);
3186
3187 return 0;
3188}
3189
a4fc5ed6 3190static void
0301b3ac
JN		 3191intel_get_adjust_train(struct intel_dp *intel_dp,
3192 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3193{
3194 uint8_t v = 0;
3195 uint8_t p = 0;
3196 int lane;
1a2eb460
KP		 3197 uint8_t voltage_max;
3198 uint8_t preemph_max;
a4fc5ed6 3199
33a34e4e 3200 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3201 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3202 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3203
3204 if (this_v > v)
3205 v = this_v;
3206 if (this_p > p)
3207 p = this_p;
3208 }
3209
1a2eb460 3210 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3211 if (v >= voltage_max)
3212 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3213
1a2eb460
KP		 3214 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3215 if (p >= preemph_max)
3216 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3217
3218 for (lane = 0; lane < 4; lane++)
33a34e4e 3219 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3220}
3221
3222static uint32_t
f0a3424e 3223intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3224{
3cf2efb1 3225 uint32_t signal_levels = 0;
a4fc5ed6 3226
3cf2efb1 3227 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3228 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3229 default:
3230 signal_levels |= DP_VOLTAGE_0_4;
3231 break;
bd60018a 3232 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3233 signal_levels |= DP_VOLTAGE_0_6;
3234 break;
bd60018a 3235 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3236 signal_levels |= DP_VOLTAGE_0_8;
3237 break;
bd60018a 3238 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3239 signal_levels |= DP_VOLTAGE_1_2;
3240 break;
3241 }
3cf2efb1 3242 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3243 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3244 default:
3245 signal_levels |= DP_PRE_EMPHASIS_0;
3246 break;
bd60018a 3247 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3248 signal_levels |= DP_PRE_EMPHASIS_3_5;
3249 break;
bd60018a 3250 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3251 signal_levels |= DP_PRE_EMPHASIS_6;
3252 break;
bd60018a 3253 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3254 signal_levels |= DP_PRE_EMPHASIS_9_5;
3255 break;
3256 }
3257 return signal_levels;
3258}
3259
e3421a18
ZW		 3260/* Gen6's DP voltage swing and pre-emphasis control */
3261static uint32_t
3262intel_gen6_edp_signal_levels(uint8_t train_set)
3263{
3c5a62b5
YL		 3264 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3265 DP_TRAIN_PRE_EMPHASIS_MASK);
3266 switch (signal_levels) {
bd60018a
SJ		 3267 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3268 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3269 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3270 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3271 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3272 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3274 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3277 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3279 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3280 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3281 default:
3c5a62b5
YL		 3282 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3283 "0x%x\n", signal_levels);
3284 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3285 }
3286}
3287
1a2eb460
KP		 3288/* Gen7's DP voltage swing and pre-emphasis control */
3289static uint32_t
3290intel_gen7_edp_signal_levels(uint8_t train_set)
3291{
3292 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3293 DP_TRAIN_PRE_EMPHASIS_MASK);
3294 switch (signal_levels) {
bd60018a 3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3296 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3298 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3300 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3301
bd60018a 3302 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3303 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3305 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3306
bd60018a 3307 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3308 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3310 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3311
3312 default:
3313 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3314 "0x%x\n", signal_levels);
3315 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3316 }
3317}
3318
d6c0d722
PZ		 3319/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3320static uint32_t
f0a3424e 3321intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3322{
d6c0d722
PZ		 3323 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3324 DP_TRAIN_PRE_EMPHASIS_MASK);
3325 switch (signal_levels) {
bd60018a 3326 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3327 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3328 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3329 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3331 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3333 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3334
bd60018a 3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3336 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3338 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3339 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3340 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3341
bd60018a 3342 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3343 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3344 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3345 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3346 default:
3347 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3348 "0x%x\n", signal_levels);
c5fe6a06 3349 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3350 }
a4fc5ed6
KP		 3351}
3352
f0a3424e
PZ		 3353/* Properly updates "DP" with the correct signal levels. */
3354static void
3355intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3356{
3357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3358 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3359 struct drm_device *dev = intel_dig_port->base.base.dev;
3360 uint32_t signal_levels, mask;
3361 uint8_t train_set = intel_dp->train_set[0];
3362
5a9d1f1a 3363 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3364 signal_levels = intel_hsw_signal_levels(train_set);
3365 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3366 } else if (IS_CHERRYVIEW(dev)) {
3367 signal_levels = intel_chv_signal_levels(intel_dp);
3368 mask = 0;
e2fa6fba
P		 3369 } else if (IS_VALLEYVIEW(dev)) {
3370 signal_levels = intel_vlv_signal_levels(intel_dp);
3371 mask = 0;
bc7d38a4 3372 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3373 signal_levels = intel_gen7_edp_signal_levels(train_set);
3374 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3375 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3376 signal_levels = intel_gen6_edp_signal_levels(train_set);
3377 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3378 } else {
3379 signal_levels = intel_gen4_signal_levels(train_set);
3380 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3381 }
3382
3383 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3384
3385 *DP = (*DP & ~mask) | signal_levels;
3386}
3387
a4fc5ed6 3388static bool
ea5b213a 3389intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3390 uint32_t *DP,
58e10eb9 3391 uint8_t dp_train_pat)
a4fc5ed6 3392{
174edf1f
PZ		 3393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3394 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3395 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3396 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3397 int ret, len;
a4fc5ed6 3398
7b13b58a 3399 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3400
70aff66c 3401 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3402 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3403
2cdfe6c8
JN		 3404 buf[0] = dp_train_pat;
3405 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3406 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3407 /* don't write DP_TRAINING_LANEx_SET on disable */
3408 len = 1;
3409 } else {
3410 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3411 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3412 len = intel_dp->lane_count + 1;
47ea7542 3413 }
a4fc5ed6 3414
9d1a1031
JN		 3415 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3416 buf, len);
2cdfe6c8
JN		 3417
3418 return ret == len;
a4fc5ed6
KP		 3419}
3420
70aff66c
JN		 3421static bool
3422intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3423 uint8_t dp_train_pat)
3424{
953d22e8 3425 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3426 intel_dp_set_signal_levels(intel_dp, DP);
3427 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3428}
3429
3430static bool
3431intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3432 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3433{
3434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3435 struct drm_device *dev = intel_dig_port->base.base.dev;
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 int ret;
3438
3439 intel_get_adjust_train(intel_dp, link_status);
3440 intel_dp_set_signal_levels(intel_dp, DP);
3441
3442 I915_WRITE(intel_dp->output_reg, *DP);
3443 POSTING_READ(intel_dp->output_reg);
3444
9d1a1031
JN		 3445 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3446 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3447
3448 return ret == intel_dp->lane_count;
3449}
3450
3ab9c637
ID		 3451static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3452{
3453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3454 struct drm_device *dev = intel_dig_port->base.base.dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
3456 enum port port = intel_dig_port->port;
3457 uint32_t val;
3458
3459 if (!HAS_DDI(dev))
3460 return;
3461
3462 val = I915_READ(DP_TP_CTL(port));
3463 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3464 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3465 I915_WRITE(DP_TP_CTL(port), val);
3466
3467 /*
3468 * On PORT_A we can have only eDP in SST mode. There the only reason
3469 * we need to set idle transmission mode is to work around a HW issue
3470 * where we enable the pipe while not in idle link-training mode.
3471 * In this case there is requirement to wait for a minimum number of
3472 * idle patterns to be sent.
3473 */
3474 if (port == PORT_A)
3475 return;
3476
3477 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3478 1))
3479 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3480}
3481
33a34e4e 3482/* Enable corresponding port and start training pattern 1 */
c19b0669 3483void
33a34e4e 3484intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3485{
da63a9f2 3486 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3487 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3488 int i;
3489 uint8_t voltage;
cdb0e95b 3490 int voltage_tries, loop_tries;
ea5b213a 3491 uint32_t DP = intel_dp->DP;
6aba5b6c 3492 uint8_t link_config[2];
a4fc5ed6 3493
affa9354 3494 if (HAS_DDI(dev))
c19b0669
PZ		 3495 intel_ddi_prepare_link_retrain(encoder);
3496
3cf2efb1 3497 /* Write the link configuration data */
6aba5b6c
JN		 3498 link_config[0] = intel_dp->link_bw;
3499 link_config[1] = intel_dp->lane_count;
3500 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3501 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3502 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3503
3504 link_config[0] = 0;
3505 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3506 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3507
3508 DP |= DP_PORT_EN;
1a2eb460 3509
70aff66c
JN		 3510 /* clock recovery */
3511 if (!intel_dp_reset_link_train(intel_dp, &DP,
3512 DP_TRAINING_PATTERN_1 |
3513 DP_LINK_SCRAMBLING_DISABLE)) {
3514 DRM_ERROR("failed to enable link training\n");
3515 return;
3516 }
3517
a4fc5ed6 3518 voltage = 0xff;
cdb0e95b
KP		 3519 voltage_tries = 0;
3520 loop_tries = 0;
a4fc5ed6 3521 for (;;) {
70aff66c 3522 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3523
a7c9655f 3524 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3525 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3526 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3527 break;
93f62dad 3528 }
a4fc5ed6 3529
01916270 3530 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3531 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3532 break;
3533 }
3534
3535 /* Check to see if we've tried the max voltage */
3536 for (i = 0; i < intel_dp->lane_count; i++)
3537 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3538 break;
3b4f819d 3539 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3540 ++loop_tries;
3541 if (loop_tries == 5) {
3def84b3 3542 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3543 break;
3544 }
70aff66c
JN		 3545 intel_dp_reset_link_train(intel_dp, &DP,
3546 DP_TRAINING_PATTERN_1 |
3547 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3548 voltage_tries = 0;
3549 continue;
3550 }
a4fc5ed6 3551
3cf2efb1 3552 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3553 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3554 ++voltage_tries;
b06fbda3 3555 if (voltage_tries == 5) {
3def84b3 3556 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3557 break;
3558 }
3559 } else
3560 voltage_tries = 0;
3561 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3562
70aff66c
JN		 3563 /* Update training set as requested by target */
3564 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3565 DRM_ERROR("failed to update link training\n");
3566 break;
3567 }
a4fc5ed6
KP		 3568 }
3569
33a34e4e
JB		 3570 intel_dp->DP = DP;
3571}
3572
c19b0669 3573void
33a34e4e
JB		 3574intel_dp_complete_link_train(struct intel_dp *intel_dp)
3575{
33a34e4e 3576 bool channel_eq = false;
37f80975 3577 int tries, cr_tries;
33a34e4e 3578 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3579 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3580
3581 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3582 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3583 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3584
a4fc5ed6 3585 /* channel equalization */
70aff66c 3586 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3587 training_pattern |
70aff66c
JN		 3588 DP_LINK_SCRAMBLING_DISABLE)) {
3589 DRM_ERROR("failed to start channel equalization\n");
3590 return;
3591 }
3592
a4fc5ed6 3593 tries = 0;
37f80975 3594 cr_tries = 0;
a4fc5ed6
KP		 3595 channel_eq = false;
3596 for (;;) {
70aff66c 3597 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3598
37f80975
JB		 3599 if (cr_tries > 5) {
3600 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3601 break;
3602 }
3603
a7c9655f 3604 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3605 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3606 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3607 break;
70aff66c 3608 }
a4fc5ed6 3609
37f80975 3610 /* Make sure clock is still ok */
01916270 3611 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3612 intel_dp_start_link_train(intel_dp);
70aff66c 3613 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3614 training_pattern |
70aff66c 3615 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3616 cr_tries++;
3617 continue;
3618 }
3619
1ffdff13 3620 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3621 channel_eq = true;
3622 break;
3623 }
a4fc5ed6 3624
37f80975
JB		 3625 /* Try 5 times, then try clock recovery if that fails */
3626 if (tries > 5) {
3627 intel_dp_link_down(intel_dp);
3628 intel_dp_start_link_train(intel_dp);
70aff66c 3629 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3630 training_pattern |
70aff66c 3631 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3632 tries = 0;
3633 cr_tries++;
3634 continue;
3635 }
a4fc5ed6 3636
70aff66c
JN		 3637 /* Update training set as requested by target */
3638 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3639 DRM_ERROR("failed to update link training\n");
3640 break;
3641 }
3cf2efb1 3642 ++tries;
869184a6 3643 }
3cf2efb1 3644
3ab9c637
ID		 3645 intel_dp_set_idle_link_train(intel_dp);
3646
3647 intel_dp->DP = DP;
3648
d6c0d722 3649 if (channel_eq)
07f42258 3650 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3651
3ab9c637
ID		 3652}
3653
3654void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3655{
70aff66c 3656 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3657 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3658}
3659
3660static void
ea5b213a 3661intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3662{
da63a9f2 3663 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3664 enum port port = intel_dig_port->port;
da63a9f2 3665 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3666 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3667 struct intel_crtc *intel_crtc =
3668 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3669 uint32_t DP = intel_dp->DP;
a4fc5ed6 3670
bc76e320 3671 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3672 return;
3673
0c33d8d7 3674 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3675 return;
3676
28c97730 3677 DRM_DEBUG_KMS("\n");
32f9d658 3678
bc7d38a4 3679 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3680 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3681 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3682 } else {
aad3d14d
VS		 3683 if (IS_CHERRYVIEW(dev))
3684 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3685 else
3686 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3687 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3688 }
fe255d00 3689 POSTING_READ(intel_dp->output_reg);
5eb08b69 3690
493a7081 3691 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3692 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3693 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3694
5bddd17f
EA		 3695 /* Hardware workaround: leaving our transcoder select
3696 * set to transcoder B while it's off will prevent the
3697 * corresponding HDMI output on transcoder A.
3698 *
3699 * Combine this with another hardware workaround:
3700 * transcoder select bit can only be cleared while the
3701 * port is enabled.
3702 */
3703 DP &= ~DP_PIPEB_SELECT;
3704 I915_WRITE(intel_dp->output_reg, DP);
3705
3706 /* Changes to enable or select take place the vblank
3707 * after being written.
3708 */
ff50afe9
DV		 3709 if (WARN_ON(crtc == NULL)) {
3710 /* We should never try to disable a port without a crtc
3711 * attached. For paranoia keep the code around for a
3712 * bit. */
31acbcc4
CW		 3713 POSTING_READ(intel_dp->output_reg);
3714 msleep(50);
3715 } else
ab527efc 3716 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3717 }
3718
832afda6 3719 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3720 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3721 POSTING_READ(intel_dp->output_reg);
f01eca2e 3722 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3723}
3724
26d61aad
KP		 3725static bool
3726intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3727{
a031d709
RV		 3728 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3729 struct drm_device *dev = dig_port->base.base.dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
3731
9d1a1031
JN		 3732 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3733 sizeof(intel_dp->dpcd)) < 0)
edb39244 3734 return false; /* aux transfer failed */
92fd8fd1 3735
a8e98153 3736 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3737
edb39244
AJ		 3738 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3739 return false; /* DPCD not present */
3740
2293bb5c
SK		 3741 /* Check if the panel supports PSR */
3742 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3743 if (is_edp(intel_dp)) {
9d1a1031
JN		 3744 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3745 intel_dp->psr_dpcd,
3746 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3747 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3748 dev_priv->psr.sink_support = true;
50003939 3749 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3750 }
50003939
JN		 3751 }
3752
06ea66b6
TP		 3753 /* Training Pattern 3 support */
3754 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3755 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3756 intel_dp->use_tps3 = true;
3757 DRM_DEBUG_KMS("Displayport TPS3 supported");
3758 } else
3759 intel_dp->use_tps3 = false;
3760
edb39244
AJ		 3761 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3762 DP_DWN_STRM_PORT_PRESENT))
3763 return true; /* native DP sink */
3764
3765 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3766 return true; /* no per-port downstream info */
3767
9d1a1031
JN		 3768 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3769 intel_dp->downstream_ports,
3770 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3771 return false; /* downstream port status fetch failed */
3772
3773 return true;
92fd8fd1
KP		 3774}
3775
0d198328
AJ		 3776static void
3777intel_dp_probe_oui(struct intel_dp *intel_dp)
3778{
3779 u8 buf[3];
3780
3781 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3782 return;
3783
24f3e092 3784 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3785
9d1a1031 3786 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3787 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3788 buf[0], buf[1], buf[2]);
3789
9d1a1031 3790 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3791 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3792 buf[0], buf[1], buf[2]);
351cfc34 3793
1e0560e0 3794 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3795}
3796
0e32b39c
DA		 3797static bool
3798intel_dp_probe_mst(struct intel_dp *intel_dp)
3799{
3800 u8 buf[1];
3801
3802 if (!intel_dp->can_mst)
3803 return false;
3804
3805 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3806 return false;
3807
d337a341 3808 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3809 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3810 if (buf[0] & DP_MST_CAP) {
3811 DRM_DEBUG_KMS("Sink is MST capable\n");
3812 intel_dp->is_mst = true;
3813 } else {
3814 DRM_DEBUG_KMS("Sink is not MST capable\n");
3815 intel_dp->is_mst = false;
3816 }
3817 }
1e0560e0 3818 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3819
3820 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3821 return intel_dp->is_mst;
3822}
3823
d2e216d0
RV		 3824int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3825{
3826 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3827 struct drm_device *dev = intel_dig_port->base.base.dev;
3828 struct intel_crtc *intel_crtc =
3829 to_intel_crtc(intel_dig_port->base.base.crtc);
3830 u8 buf[1];
3831
9d1a1031 3832 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3833 return -EAGAIN;
3834
3835 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3836 return -ENOTTY;
3837
9d1a1031
JN		 3838 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3839 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3840 return -EAGAIN;
3841
3842 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3843 intel_wait_for_vblank(dev, intel_crtc->pipe);
3844 intel_wait_for_vblank(dev, intel_crtc->pipe);
3845
9d1a1031 3846 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3847 return -EAGAIN;
3848
9d1a1031 3849 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3850 return 0;
3851}
3852
a60f0e38
JB		 3853static bool
3854intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3855{
9d1a1031
JN		 3856 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3857 DP_DEVICE_SERVICE_IRQ_VECTOR,
3858 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3859}
3860
0e32b39c
DA		 3861static bool
3862intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3863{
3864 int ret;
3865
3866 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3867 DP_SINK_COUNT_ESI,
3868 sink_irq_vector, 14);
3869 if (ret != 14)
3870 return false;
3871
3872 return true;
3873}
3874
a60f0e38
JB		 3875static void
3876intel_dp_handle_test_request(struct intel_dp *intel_dp)
3877{
3878 /* NAK by default */
9d1a1031 3879 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3880}
3881
0e32b39c
DA		 3882static int
3883intel_dp_check_mst_status(struct intel_dp *intel_dp)
3884{
3885 bool bret;
3886
3887 if (intel_dp->is_mst) {
3888 u8 esi[16] = { 0 };
3889 int ret = 0;
3890 int retry;
3891 bool handled;
3892 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3893go_again:
3894 if (bret == true) {
3895
3896 /* check link status - esi[10] = 0x200c */
3897 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3898 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3899 intel_dp_start_link_train(intel_dp);
3900 intel_dp_complete_link_train(intel_dp);
3901 intel_dp_stop_link_train(intel_dp);
3902 }
3903
3904 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3905 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3906
3907 if (handled) {
3908 for (retry = 0; retry < 3; retry++) {
3909 int wret;
3910 wret = drm_dp_dpcd_write(&intel_dp->aux,
3911 DP_SINK_COUNT_ESI+1,
3912 &esi[1], 3);
3913 if (wret == 3) {
3914 break;
3915 }
3916 }
3917
3918 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3919 if (bret == true) {
3920 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3921 goto go_again;
3922 }
3923 } else
3924 ret = 0;
3925
3926 return ret;
3927 } else {
3928 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3929 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3930 intel_dp->is_mst = false;
3931 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3932 /* send a hotplug event */
3933 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3934 }
3935 }
3936 return -EINVAL;
3937}
3938
a4fc5ed6
KP		 3939/*
3940 * According to DP spec
3941 * 5.1.2:
3942 * 1. Read DPCD
3943 * 2. Configure link according to Receiver Capabilities
3944 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3945 * 4. Check link status on receipt of hot-plug interrupt
3946 */
00c09d70 3947void
ea5b213a 3948intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3949{
5b215bcf 3950 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3951 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3952 u8 sink_irq_vector;
93f62dad 3953 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3954
5b215bcf
DA		 3955 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3956
da63a9f2 3957 if (!intel_encoder->connectors_active)
d2b996ac 3958 return;
59cd09e1 3959
da63a9f2 3960 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3961 return;
3962
1a125d8a
ID		 3963 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3964 return;
3965
92fd8fd1 3966 /* Try to read receiver status if the link appears to be up */
93f62dad 3967 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3968 return;
3969 }
3970
92fd8fd1 3971 /* Now read the DPCD to see if it's actually running */
26d61aad 3972 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3973 return;
3974 }
3975
a60f0e38
JB		 3976 /* Try to read the source of the interrupt */
3977 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3978 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3979 /* Clear interrupt source */
9d1a1031
JN		 3980 drm_dp_dpcd_writeb(&intel_dp->aux,
3981 DP_DEVICE_SERVICE_IRQ_VECTOR,
3982 sink_irq_vector);
a60f0e38
JB		 3983
3984 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3985 intel_dp_handle_test_request(intel_dp);
3986 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3987 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3988 }
3989
1ffdff13 3990 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3991 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3992 intel_encoder->base.name);
33a34e4e
JB		 3993 intel_dp_start_link_train(intel_dp);
3994 intel_dp_complete_link_train(intel_dp);
3ab9c637 3995 intel_dp_stop_link_train(intel_dp);
33a34e4e 3996 }
a4fc5ed6 3997}
a4fc5ed6 3998
caf9ab24 3999/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4000static enum drm_connector_status
26d61aad 4001intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4002{
caf9ab24 4003 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4004 uint8_t type;
4005
4006 if (!intel_dp_get_dpcd(intel_dp))
4007 return connector_status_disconnected;
4008
4009 /* if there's no downstream port, we're done */
4010 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4011 return connector_status_connected;
caf9ab24
AJ		 4012
4013 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4014 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4015 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4016 uint8_t reg;
9d1a1031
JN		 4017
4018 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4019 &reg, 1) < 0)
caf9ab24 4020 return connector_status_unknown;
9d1a1031 4021
23235177
AJ		 4022 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4023 : connector_status_disconnected;
caf9ab24
AJ		 4024 }
4025
4026 /* If no HPD, poke DDC gently */
0b99836f 4027 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4028 return connector_status_connected;
caf9ab24
AJ		 4029
4030 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4031 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4032 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4033 if (type == DP_DS_PORT_TYPE_VGA ||
4034 type == DP_DS_PORT_TYPE_NON_EDID)
4035 return connector_status_unknown;
4036 } else {
4037 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4038 DP_DWN_STRM_PORT_TYPE_MASK;
4039 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4040 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4041 return connector_status_unknown;
4042 }
caf9ab24
AJ		 4043
4044 /* Anything else is out of spec, warn and ignore */
4045 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4046 return connector_status_disconnected;
71ba9000
AJ		 4047}
4048
d410b56d
CW		 4049static enum drm_connector_status
4050edp_detect(struct intel_dp *intel_dp)
4051{
4052 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4053 enum drm_connector_status status;
4054
4055 status = intel_panel_detect(dev);
4056 if (status == connector_status_unknown)
4057 status = connector_status_connected;
4058
4059 return status;
4060}
4061
5eb08b69 4062static enum drm_connector_status
a9756bb5 4063ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4064{
30add22d 4065 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4066 struct drm_i915_private *dev_priv = dev->dev_private;
4067 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4068
1b469639
DL		 4069 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4070 return connector_status_disconnected;
4071
26d61aad 4072 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4073}
4074
2a592bec
DA		 4075static int g4x_digital_port_connected(struct drm_device *dev,
4076 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4077{
a4fc5ed6 4078 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4079 uint32_t bit;
5eb08b69 4080
232a6ee9
TP		 4081 if (IS_VALLEYVIEW(dev)) {
4082 switch (intel_dig_port->port) {
4083 case PORT_B:
4084 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4085 break;
4086 case PORT_C:
4087 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4088 break;
4089 case PORT_D:
4090 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4091 break;
4092 default:
2a592bec 4093 return -EINVAL;
232a6ee9
TP		 4094 }
4095 } else {
4096 switch (intel_dig_port->port) {
4097 case PORT_B:
4098 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4099 break;
4100 case PORT_C:
4101 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4102 break;
4103 case PORT_D:
4104 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4105 break;
4106 default:
2a592bec 4107 return -EINVAL;
232a6ee9 4108 }
a4fc5ed6
KP		 4109 }
4110
10f76a38 4111 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4112 return 0;
4113 return 1;
4114}
4115
4116static enum drm_connector_status
4117g4x_dp_detect(struct intel_dp *intel_dp)
4118{
4119 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4120 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4121 int ret;
4122
4123 /* Can't disconnect eDP, but you can close the lid... */
4124 if (is_edp(intel_dp)) {
4125 enum drm_connector_status status;
4126
4127 status = intel_panel_detect(dev);
4128 if (status == connector_status_unknown)
4129 status = connector_status_connected;
4130 return status;
4131 }
4132
4133 ret = g4x_digital_port_connected(dev, intel_dig_port);
4134 if (ret == -EINVAL)
4135 return connector_status_unknown;
4136 else if (ret == 0)
a4fc5ed6
KP		 4137 return connector_status_disconnected;
4138
26d61aad 4139 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4140}
4141
8c241fef 4142static struct edid *
beb60608 4143intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4144{
beb60608 4145 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4146
9cd300e0
JN		 4147 /* use cached edid if we have one */
4148 if (intel_connector->edid) {
9cd300e0
JN		 4149 /* invalid edid */
4150 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4151 return NULL;
4152
55e9edeb 4153 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4154 } else
4155 return drm_get_edid(&intel_connector->base,
4156 &intel_dp->aux.ddc);
4157}
8c241fef 4158
beb60608
CW		 4159static void
4160intel_dp_set_edid(struct intel_dp *intel_dp)
4161{
4162 struct intel_connector *intel_connector = intel_dp->attached_connector;
4163 struct edid *edid;
8c241fef 4164
beb60608
CW		 4165 edid = intel_dp_get_edid(intel_dp);
4166 intel_connector->detect_edid = edid;
4167
4168 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4169 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4170 else
4171 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4172}
4173
beb60608
CW		 4174static void
4175intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4176{
beb60608 4177 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4178
beb60608
CW		 4179 kfree(intel_connector->detect_edid);
4180 intel_connector->detect_edid = NULL;
9cd300e0 4181
beb60608
CW		 4182 intel_dp->has_audio = false;
4183}
d6f24d0f 4184
beb60608
CW		 4185static enum intel_display_power_domain
4186intel_dp_power_get(struct intel_dp *dp)
4187{
4188 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4189 enum intel_display_power_domain power_domain;
4190
4191 power_domain = intel_display_port_power_domain(encoder);
4192 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4193
4194 return power_domain;
4195}
d6f24d0f 4196
beb60608
CW		 4197static void
4198intel_dp_power_put(struct intel_dp *dp,
4199 enum intel_display_power_domain power_domain)
4200{
4201 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4202 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4203}
4204
a9756bb5
ZW		 4205static enum drm_connector_status
4206intel_dp_detect(struct drm_connector *connector, bool force)
4207{
4208 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4209 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4210 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4211 struct drm_device *dev = connector->dev;
a9756bb5 4212 enum drm_connector_status status;
671dedd2 4213 enum intel_display_power_domain power_domain;
0e32b39c 4214 bool ret;
a9756bb5 4215
164c8598 4216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4217 connector->base.id, connector->name);
beb60608 4218 intel_dp_unset_edid(intel_dp);
164c8598 4219
0e32b39c
DA		 4220 if (intel_dp->is_mst) {
4221 /* MST devices are disconnected from a monitor POV */
4222 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4223 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4224 return connector_status_disconnected;
0e32b39c
DA		 4225 }
4226
beb60608 4227 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4228
d410b56d
CW		 4229 /* Can't disconnect eDP, but you can close the lid... */
4230 if (is_edp(intel_dp))
4231 status = edp_detect(intel_dp);
4232 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4233 status = ironlake_dp_detect(intel_dp);
4234 else
4235 status = g4x_dp_detect(intel_dp);
4236 if (status != connector_status_connected)
c8c8fb33 4237 goto out;
a9756bb5 4238
0d198328
AJ		 4239 intel_dp_probe_oui(intel_dp);
4240
0e32b39c
DA		 4241 ret = intel_dp_probe_mst(intel_dp);
4242 if (ret) {
4243 /* if we are in MST mode then this connector
4244 won't appear connected or have anything with EDID on it */
4245 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4246 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4247 status = connector_status_disconnected;
4248 goto out;
4249 }
4250
beb60608 4251 intel_dp_set_edid(intel_dp);
a9756bb5 4252
d63885da
PZ		 4253 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4254 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4255 status = connector_status_connected;
4256
4257out:
beb60608 4258 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4259 return status;
a4fc5ed6
KP		 4260}
4261
beb60608
CW		 4262static void
4263intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4264{
df0e9248 4265 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4266 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4267 enum intel_display_power_domain power_domain;
a4fc5ed6 4268
beb60608
CW		 4269 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4270 connector->base.id, connector->name);
4271 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4272
beb60608
CW		 4273 if (connector->status != connector_status_connected)
4274 return;
671dedd2 4275
beb60608
CW		 4276 power_domain = intel_dp_power_get(intel_dp);
4277
4278 intel_dp_set_edid(intel_dp);
4279
4280 intel_dp_power_put(intel_dp, power_domain);
4281
4282 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4283 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4284}
4285
4286static int intel_dp_get_modes(struct drm_connector *connector)
4287{
4288 struct intel_connector *intel_connector = to_intel_connector(connector);
4289 struct edid *edid;
4290
4291 edid = intel_connector->detect_edid;
4292 if (edid) {
4293 int ret = intel_connector_update_modes(connector, edid);
4294 if (ret)
4295 return ret;
4296 }
32f9d658 4297
f8779fda 4298 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4299 if (is_edp(intel_attached_dp(connector)) &&
4300 intel_connector->panel.fixed_mode) {
f8779fda 4301 struct drm_display_mode *mode;
beb60608
CW		 4302
4303 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4304 intel_connector->panel.fixed_mode);
f8779fda 4305 if (mode) {
32f9d658
ZW		 4306 drm_mode_probed_add(connector, mode);
4307 return 1;
4308 }
4309 }
beb60608 4310
32f9d658 4311 return 0;
a4fc5ed6
KP		 4312}
4313
1aad7ac0
CW		 4314static bool
4315intel_dp_detect_audio(struct drm_connector *connector)
4316{
1aad7ac0 4317 bool has_audio = false;
beb60608 4318 struct edid *edid;
1aad7ac0 4319
beb60608
CW		 4320 edid = to_intel_connector(connector)->detect_edid;
4321 if (edid)
1aad7ac0 4322 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4323
1aad7ac0
CW		 4324 return has_audio;
4325}
4326
f684960e
CW		 4327static int
4328intel_dp_set_property(struct drm_connector *connector,
4329 struct drm_property *property,
4330 uint64_t val)
4331{
e953fd7b 4332 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4333 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4334 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4335 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4336 int ret;
4337
662595df 4338 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4339 if (ret)
4340 return ret;
4341
3f43c48d 4342 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4343 int i = val;
4344 bool has_audio;
4345
4346 if (i == intel_dp->force_audio)
f684960e
CW		 4347 return 0;
4348
1aad7ac0 4349 intel_dp->force_audio = i;
f684960e 4350
c3e5f67b 4351 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4352 has_audio = intel_dp_detect_audio(connector);
4353 else
c3e5f67b 4354 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4355
4356 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4357 return 0;
4358
1aad7ac0 4359 intel_dp->has_audio = has_audio;
f684960e
CW		 4360 goto done;
4361 }
4362
e953fd7b 4363 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4364 bool old_auto = intel_dp->color_range_auto;
4365 uint32_t old_range = intel_dp->color_range;
4366
55bc60db
VS		 4367 switch (val) {
4368 case INTEL_BROADCAST_RGB_AUTO:
4369 intel_dp->color_range_auto = true;
4370 break;
4371 case INTEL_BROADCAST_RGB_FULL:
4372 intel_dp->color_range_auto = false;
4373 intel_dp->color_range = 0;
4374 break;
4375 case INTEL_BROADCAST_RGB_LIMITED:
4376 intel_dp->color_range_auto = false;
4377 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4378 break;
4379 default:
4380 return -EINVAL;
4381 }
ae4edb80
DV		 4382
4383 if (old_auto == intel_dp->color_range_auto &&
4384 old_range == intel_dp->color_range)
4385 return 0;
4386
e953fd7b
CW		 4387 goto done;
4388 }
4389
53b41837
YN		 4390 if (is_edp(intel_dp) &&
4391 property == connector->dev->mode_config.scaling_mode_property) {
4392 if (val == DRM_MODE_SCALE_NONE) {
4393 DRM_DEBUG_KMS("no scaling not supported\n");
4394 return -EINVAL;
4395 }
4396
4397 if (intel_connector->panel.fitting_mode == val) {
4398 /* the eDP scaling property is not changed */
4399 return 0;
4400 }
4401 intel_connector->panel.fitting_mode = val;
4402
4403 goto done;
4404 }
4405
f684960e
CW		 4406 return -EINVAL;
4407
4408done:
c0c36b94
CW		 4409 if (intel_encoder->base.crtc)
4410 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4411
4412 return 0;
4413}
4414
a4fc5ed6 4415static void
73845adf 4416intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4417{
1d508706 4418 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4419
beb60608
CW		 4420 intel_dp_unset_edid(intel_attached_dp(connector));
4421
9cd300e0
JN		 4422 if (!IS_ERR_OR_NULL(intel_connector->edid))
4423 kfree(intel_connector->edid);
4424
acd8db10
PZ		 4425 /* Can't call is_edp() since the encoder may have been destroyed
4426 * already. */
4427 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4428 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4429
a4fc5ed6 4430 drm_connector_cleanup(connector);
55f78c43 4431 kfree(connector);
a4fc5ed6
KP		 4432}
4433
00c09d70 4434void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4435{
da63a9f2
PZ		 4436 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4437 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4438
4f71d0cb 4439 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4440 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4441 drm_encoder_cleanup(encoder);
bd943159
KP		 4442 if (is_edp(intel_dp)) {
4443 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4444 /*
4445 * vdd might still be enabled do to the delayed vdd off.
4446 * Make sure vdd is actually turned off here.
4447 */
773538e8 4448 pps_lock(intel_dp);
4be73780 4449 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4450 pps_unlock(intel_dp);
4451
01527b31
CT		 4452 if (intel_dp->edp_notifier.notifier_call) {
4453 unregister_reboot_notifier(&intel_dp->edp_notifier);
4454 intel_dp->edp_notifier.notifier_call = NULL;
4455 }
bd943159 4456 }
da63a9f2 4457 kfree(intel_dig_port);
24d05927
DV		 4458}
4459
07f9cd0b
ID		 4460static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4461{
4462 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4463
4464 if (!is_edp(intel_dp))
4465 return;
4466
951468f3
VS		 4467 /*
4468 * vdd might still be enabled do to the delayed vdd off.
4469 * Make sure vdd is actually turned off here.
4470 */
773538e8 4471 pps_lock(intel_dp);
07f9cd0b 4472 edp_panel_vdd_off_sync(intel_dp);
773538e8 4473 pps_unlock(intel_dp);
07f9cd0b
ID		 4474}
4475
6d93c0c4
ID		 4476static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4477{
4478 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4479}
4480
a4fc5ed6 4481static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4482 .dpms = intel_connector_dpms,
a4fc5ed6 4483 .detect = intel_dp_detect,
beb60608 4484 .force = intel_dp_force,
a4fc5ed6 4485 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4486 .set_property = intel_dp_set_property,
73845adf 4487 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4488};
4489
4490static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4491 .get_modes = intel_dp_get_modes,
4492 .mode_valid = intel_dp_mode_valid,
df0e9248 4493 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4494};
4495
a4fc5ed6 4496static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4497 .reset = intel_dp_encoder_reset,
24d05927 4498 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4499};
4500
0e32b39c 4501void
21d40d37 4502intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4503{
0e32b39c 4504 return;
c8110e52 4505}
6207937d 4506
13cf5504
DA		 4507bool
4508intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4509{
4510 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4511 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4512 struct drm_device *dev = intel_dig_port->base.base.dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4514 enum intel_display_power_domain power_domain;
4515 bool ret = true;
4516
0e32b39c
DA		 4517 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4518 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4519
26fbb774
VS		 4520 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4521 port_name(intel_dig_port->port),
0e32b39c 4522 long_hpd ? "long" : "short");
13cf5504 4523
1c767b33
ID		 4524 power_domain = intel_display_port_power_domain(intel_encoder);
4525 intel_display_power_get(dev_priv, power_domain);
4526
0e32b39c 4527 if (long_hpd) {
2a592bec
DA		 4528
4529 if (HAS_PCH_SPLIT(dev)) {
4530 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4531 goto mst_fail;
4532 } else {
4533 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4534 goto mst_fail;
4535 }
0e32b39c
DA		 4536
4537 if (!intel_dp_get_dpcd(intel_dp)) {
4538 goto mst_fail;
4539 }
4540
4541 intel_dp_probe_oui(intel_dp);
4542
4543 if (!intel_dp_probe_mst(intel_dp))
4544 goto mst_fail;
4545
4546 } else {
4547 if (intel_dp->is_mst) {
1c767b33 4548 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4549 goto mst_fail;
4550 }
4551
4552 if (!intel_dp->is_mst) {
4553 /*
4554 * we'll check the link status via the normal hot plug path later -
4555 * but for short hpds we should check it now
4556 */
5b215bcf 4557 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4558 intel_dp_check_link_status(intel_dp);
5b215bcf 4559 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4560 }
4561 }
1c767b33
ID		 4562 ret = false;
4563 goto put_power;
0e32b39c
DA		 4564mst_fail:
4565 /* if we were in MST mode, and device is not there get out of MST mode */
4566 if (intel_dp->is_mst) {
4567 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4568 intel_dp->is_mst = false;
4569 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4570 }
1c767b33
ID		 4571put_power:
4572 intel_display_power_put(dev_priv, power_domain);
4573
4574 return ret;
13cf5504
DA		 4575}
4576
e3421a18
ZW		 4577/* Return which DP Port should be selected for Transcoder DP control */
4578int
0206e353 4579intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4580{
4581 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4582 struct intel_encoder *intel_encoder;
4583 struct intel_dp *intel_dp;
e3421a18 4584
fa90ecef
PZ		 4585 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4586 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4587
fa90ecef
PZ		 4588 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4589 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4590 return intel_dp->output_reg;
e3421a18 4591 }
ea5b213a 4592
e3421a18
ZW		 4593 return -1;
4594}
4595
36e83a18 4596/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4597bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4598{
4599 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4600 union child_device_config *p_child;
36e83a18 4601 int i;
5d8a7752
VS		 4602 static const short port_mapping[] = {
4603 [PORT_B] = PORT_IDPB,
4604 [PORT_C] = PORT_IDPC,
4605 [PORT_D] = PORT_IDPD,
4606 };
36e83a18 4607
3b32a35b
VS		 4608 if (port == PORT_A)
4609 return true;
4610
41aa3448 4611 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4612 return false;
4613
41aa3448
RV		 4614 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4615 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4616
5d8a7752 4617 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4618 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4619 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4620 return true;
4621 }
4622 return false;
4623}
4624
0e32b39c 4625void
f684960e
CW		 4626intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4627{
53b41837
YN		 4628 struct intel_connector *intel_connector = to_intel_connector(connector);
4629
3f43c48d 4630 intel_attach_force_audio_property(connector);
e953fd7b 4631 intel_attach_broadcast_rgb_property(connector);
55bc60db 4632 intel_dp->color_range_auto = true;
53b41837
YN		 4633
4634 if (is_edp(intel_dp)) {
4635 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4636 drm_object_attach_property(
4637 &connector->base,
53b41837 4638 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4639 DRM_MODE_SCALE_ASPECT);
4640 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4641 }
f684960e
CW		 4642}
4643
dada1a9f
ID		 4644static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4645{
4646 intel_dp->last_power_cycle = jiffies;
4647 intel_dp->last_power_on = jiffies;
4648 intel_dp->last_backlight_off = jiffies;
4649}
4650
67a54566
DV		 4651static void
4652intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4653 struct intel_dp *intel_dp,
4654 struct edp_power_seq *out)
67a54566
DV		 4655{
4656 struct drm_i915_private *dev_priv = dev->dev_private;
4657 struct edp_power_seq cur, vbt, spec, final;
4658 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4659 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4660
e39b999a
VS		 4661 lockdep_assert_held(&dev_priv->pps_mutex);
4662
453c5420 4663 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4664 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4665 pp_on_reg = PCH_PP_ON_DELAYS;
4666 pp_off_reg = PCH_PP_OFF_DELAYS;
4667 pp_div_reg = PCH_PP_DIVISOR;
4668 } else {
bf13e81b
JN		 4669 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4670
4671 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4672 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4673 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4674 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4675 }
67a54566
DV		 4676
4677 /* Workaround: Need to write PP_CONTROL with the unlock key as
4678 * the very first thing. */
453c5420 4679 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4680 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4681
453c5420
JB		 4682 pp_on = I915_READ(pp_on_reg);
4683 pp_off = I915_READ(pp_off_reg);
4684 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4685
4686 /* Pull timing values out of registers */
4687 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4688 PANEL_POWER_UP_DELAY_SHIFT;
4689
4690 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4691 PANEL_LIGHT_ON_DELAY_SHIFT;
4692
4693 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4694 PANEL_LIGHT_OFF_DELAY_SHIFT;
4695
4696 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4697 PANEL_POWER_DOWN_DELAY_SHIFT;
4698
4699 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4700 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4701
4702 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4703 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4704
41aa3448 4705 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4706
4707 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4708 * our hw here, which are all in 100usec. */
4709 spec.t1_t3 = 210 * 10;
4710 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4711 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4712 spec.t10 = 500 * 10;
4713 /* This one is special and actually in units of 100ms, but zero
4714 * based in the hw (so we need to add 100 ms). But the sw vbt
4715 * table multiplies it with 1000 to make it in units of 100usec,
4716 * too. */
4717 spec.t11_t12 = (510 + 100) * 10;
4718
4719 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4720 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4721
4722 /* Use the max of the register settings and vbt. If both are
4723 * unset, fall back to the spec limits. */
4724#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4725 spec.field : \
4726 max(cur.field, vbt.field))
4727 assign_final(t1_t3);
4728 assign_final(t8);
4729 assign_final(t9);
4730 assign_final(t10);
4731 assign_final(t11_t12);
4732#undef assign_final
4733
4734#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4735 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4736 intel_dp->backlight_on_delay = get_delay(t8);
4737 intel_dp->backlight_off_delay = get_delay(t9);
4738 intel_dp->panel_power_down_delay = get_delay(t10);
4739 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4740#undef get_delay
4741
f30d26e4
JN		 4742 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4743 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4744 intel_dp->panel_power_cycle_delay);
4745
4746 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4747 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4748
4749 if (out)
4750 *out = final;
4751}
4752
4753static void
4754intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4755 struct intel_dp *intel_dp,
4756 struct edp_power_seq *seq)
4757{
4758 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4759 u32 pp_on, pp_off, pp_div, port_sel = 0;
4760 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4761 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4762 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4763
e39b999a 4764 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4765
4766 if (HAS_PCH_SPLIT(dev)) {
4767 pp_on_reg = PCH_PP_ON_DELAYS;
4768 pp_off_reg = PCH_PP_OFF_DELAYS;
4769 pp_div_reg = PCH_PP_DIVISOR;
4770 } else {
bf13e81b
JN		 4771 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4772
4773 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4774 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4775 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4776 }
4777
b2f19d1a
PZ		 4778 /*
4779 * And finally store the new values in the power sequencer. The
4780 * backlight delays are set to 1 because we do manual waits on them. For
4781 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4782 * we'll end up waiting for the backlight off delay twice: once when we
4783 * do the manual sleep, and once when we disable the panel and wait for
4784 * the PP_STATUS bit to become zero.
4785 */
f30d26e4 4786 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4787 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4788 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4789 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4790 /* Compute the divisor for the pp clock, simply match the Bspec
4791 * formula. */
453c5420 4792 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4793 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4794 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4795
4796 /* Haswell doesn't have any port selection bits for the panel
4797 * power sequencer any more. */
bc7d38a4 4798 if (IS_VALLEYVIEW(dev)) {
ad933b56 4799 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4800 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4801 if (port == PORT_A)
a24c144c 4802 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4803 else
a24c144c 4804 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4805 }
4806
453c5420
JB		 4807 pp_on |= port_sel;
4808
4809 I915_WRITE(pp_on_reg, pp_on);
4810 I915_WRITE(pp_off_reg, pp_off);
4811 I915_WRITE(pp_div_reg, pp_div);
67a54566 4812
67a54566 4813 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4814 I915_READ(pp_on_reg),
4815 I915_READ(pp_off_reg),
4816 I915_READ(pp_div_reg));
f684960e
CW		 4817}
4818
439d7ac0
PB		 4819void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4820{
4821 struct drm_i915_private *dev_priv = dev->dev_private;
4822 struct intel_encoder *encoder;
4823 struct intel_dp *intel_dp = NULL;
4824 struct intel_crtc_config *config = NULL;
4825 struct intel_crtc *intel_crtc = NULL;
4826 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4827 u32 reg, val;
4828 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4829
4830 if (refresh_rate <= 0) {
4831 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4832 return;
4833 }
4834
4835 if (intel_connector == NULL) {
4836 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4837 return;
4838 }
4839
1fcc9d1c
DV		 4840 /*
4841 * FIXME: This needs proper synchronization with psr state. But really
4842 * hard to tell without seeing the user of this function of this code.
4843 * Check locking and ordering once that lands.
4844 */
439d7ac0
PB		 4845 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4846 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4847 return;
4848 }
4849
4850 encoder = intel_attached_encoder(&intel_connector->base);
4851 intel_dp = enc_to_intel_dp(&encoder->base);
4852 intel_crtc = encoder->new_crtc;
4853
4854 if (!intel_crtc) {
4855 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4856 return;
4857 }
4858
4859 config = &intel_crtc->config;
4860
4861 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4862 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4863 return;
4864 }
4865
4866 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4867 index = DRRS_LOW_RR;
4868
4869 if (index == intel_dp->drrs_state.refresh_rate_type) {
4870 DRM_DEBUG_KMS(
4871 "DRRS requested for previously set RR...ignoring\n");
4872 return;
4873 }
4874
4875 if (!intel_crtc->active) {
4876 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4877 return;
4878 }
4879
4880 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4881 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4882 val = I915_READ(reg);
4883 if (index > DRRS_HIGH_RR) {
4884 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4885 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4886 } else {
4887 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4888 }
4889 I915_WRITE(reg, val);
4890 }
4891
4892 /*
4893 * mutex taken to ensure that there is no race between differnt
4894 * drrs calls trying to update refresh rate. This scenario may occur
4895 * in future when idleness detection based DRRS in kernel and
4896 * possible calls from user space to set differnt RR are made.
4897 */
4898
4899 mutex_lock(&intel_dp->drrs_state.mutex);
4900
4901 intel_dp->drrs_state.refresh_rate_type = index;
4902
4903 mutex_unlock(&intel_dp->drrs_state.mutex);
4904
4905 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4906}
4907
4f9db5b5
PB		 4908static struct drm_display_mode *
4909intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4910 struct intel_connector *intel_connector,
4911 struct drm_display_mode *fixed_mode)
4912{
4913 struct drm_connector *connector = &intel_connector->base;
4914 struct intel_dp *intel_dp = &intel_dig_port->dp;
4915 struct drm_device *dev = intel_dig_port->base.base.dev;
4916 struct drm_i915_private *dev_priv = dev->dev_private;
4917 struct drm_display_mode *downclock_mode = NULL;
4918
4919 if (INTEL_INFO(dev)->gen <= 6) {
4920 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4921 return NULL;
4922 }
4923
4924 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4925 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4926 return NULL;
4927 }
4928
4929 downclock_mode = intel_find_panel_downclock
4930 (dev, fixed_mode, connector);
4931
4932 if (!downclock_mode) {
4079b8d1 4933 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4934 return NULL;
4935 }
4936
439d7ac0
PB		 4937 dev_priv->drrs.connector = intel_connector;
4938
4939 mutex_init(&intel_dp->drrs_state.mutex);
4940
4f9db5b5
PB		 4941 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4942
4943 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4944 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4945 return downclock_mode;
4946}
4947
aba86890
ID		 4948void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4949{
4950 struct drm_device *dev = intel_encoder->base.dev;
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952 struct intel_dp *intel_dp;
4953 enum intel_display_power_domain power_domain;
4954
4955 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4956 return;
4957
4958 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 4959
4960 pps_lock(intel_dp);
4961
aba86890 4962 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4963 goto out;
aba86890
ID		 4964 /*
4965 * The VDD bit needs a power domain reference, so if the bit is
4966 * already enabled when we boot or resume, grab this reference and
4967 * schedule a vdd off, so we don't hold on to the reference
4968 * indefinitely.
4969 */
4970 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4971 power_domain = intel_display_port_power_domain(intel_encoder);
4972 intel_display_power_get(dev_priv, power_domain);
4973
4974 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 4975 out:
773538e8 4976 pps_unlock(intel_dp);
aba86890
ID		 4977}
4978
ed92f0b2 4979static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4980 struct intel_connector *intel_connector,
4981 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4982{
4983 struct drm_connector *connector = &intel_connector->base;
4984 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4985 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4986 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4989 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4990 bool has_dpcd;
4991 struct drm_display_mode *scan;
4992 struct edid *edid;
4993
4f9db5b5
PB		 4994 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4995
ed92f0b2
PZ		 4996 if (!is_edp(intel_dp))
4997 return true;
4998
aba86890 4999 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5000
ed92f0b2 5001 /* Cache DPCD and EDID for edp. */
24f3e092 5002 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 5003 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 5004 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 5005
5006 if (has_dpcd) {
5007 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5008 dev_priv->no_aux_handshake =
5009 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5010 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5011 } else {
5012 /* if this fails, presume the device is a ghost */
5013 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5014 return false;
5015 }
5016
5017 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5018 pps_lock(intel_dp);
0095e6dc 5019 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 5020 pps_unlock(intel_dp);
ed92f0b2 5021
060c8778 5022 mutex_lock(&dev->mode_config.mutex);
0b99836f 5023 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5024 if (edid) {
5025 if (drm_add_edid_modes(connector, edid)) {
5026 drm_mode_connector_update_edid_property(connector,
5027 edid);
5028 drm_edid_to_eld(connector, edid);
5029 } else {
5030 kfree(edid);
5031 edid = ERR_PTR(-EINVAL);
5032 }
5033 } else {
5034 edid = ERR_PTR(-ENOENT);
5035 }
5036 intel_connector->edid = edid;
5037
5038 /* prefer fixed mode from EDID if available */
5039 list_for_each_entry(scan, &connector->probed_modes, head) {
5040 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5041 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5042 downclock_mode = intel_dp_drrs_init(
5043 intel_dig_port,
5044 intel_connector, fixed_mode);
ed92f0b2
PZ		 5045 break;
5046 }
5047 }
5048
5049 /* fallback to VBT if available for eDP */
5050 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5051 fixed_mode = drm_mode_duplicate(dev,
5052 dev_priv->vbt.lfp_lvds_vbt_mode);
5053 if (fixed_mode)
5054 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5055 }
060c8778 5056 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5057
01527b31
CT		 5058 if (IS_VALLEYVIEW(dev)) {
5059 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5060 register_reboot_notifier(&intel_dp->edp_notifier);
5061 }
5062
4f9db5b5 5063 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5064 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5065 intel_panel_setup_backlight(connector);
5066
5067 return true;
5068}
5069
16c25533 5070bool
f0fec3f2
PZ		 5071intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5072 struct intel_connector *intel_connector)
a4fc5ed6 5073{
f0fec3f2
PZ		 5074 struct drm_connector *connector = &intel_connector->base;
5075 struct intel_dp *intel_dp = &intel_dig_port->dp;
5076 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5077 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5078 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5079 enum port port = intel_dig_port->port;
0095e6dc 5080 struct edp_power_seq power_seq = { 0 };
0b99836f 5081 int type;
a4fc5ed6 5082
a4a5d2f8
VS		 5083 intel_dp->pps_pipe = INVALID_PIPE;
5084
ec5b01dd
DL		 5085 /* intel_dp vfuncs */
5086 if (IS_VALLEYVIEW(dev))
5087 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5088 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5089 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5090 else if (HAS_PCH_SPLIT(dev))
5091 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5092 else
5093 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5094
153b1100
DL		 5095 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5096
0767935e
DV		 5097 /* Preserve the current hw state. */
5098 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5099 intel_dp->attached_connector = intel_connector;
3d3dc149 5100
3b32a35b 5101 if (intel_dp_is_edp(dev, port))
b329530c 5102 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5103 else
5104 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5105
f7d24902
ID		 5106 /*
5107 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5108 * for DP the encoder type can be set by the caller to
5109 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5110 */
5111 if (type == DRM_MODE_CONNECTOR_eDP)
5112 intel_encoder->type = INTEL_OUTPUT_EDP;
5113
e7281eab
ID		 5114 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5115 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5116 port_name(port));
5117
b329530c 5118 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5119 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5120
a4fc5ed6
KP		 5121 connector->interlace_allowed = true;
5122 connector->doublescan_allowed = 0;
5123
f0fec3f2 5124 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5125 edp_panel_vdd_work);
a4fc5ed6 5126
df0e9248 5127 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5128 drm_connector_register(connector);
a4fc5ed6 5129
affa9354 5130 if (HAS_DDI(dev))
bcbc889b
PZ		 5131 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5132 else
5133 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5134 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5135
0b99836f 5136 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5137 switch (port) {
5138 case PORT_A:
1d843f9d 5139 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5140 break;
5141 case PORT_B:
1d843f9d 5142 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5143 break;
5144 case PORT_C:
1d843f9d 5145 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5146 break;
5147 case PORT_D:
1d843f9d 5148 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5149 break;
5150 default:
ad1c0b19 5151 BUG();
5eb08b69
ZW		 5152 }
5153
dada1a9f 5154 if (is_edp(intel_dp)) {
773538e8 5155 pps_lock(intel_dp);
a4a5d2f8
VS		 5156 if (IS_VALLEYVIEW(dev)) {
5157 vlv_initial_power_sequencer_setup(intel_dp);
5158 } else {
5159 intel_dp_init_panel_power_timestamps(intel_dp);
5160 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5161 &power_seq);
5162 }
773538e8 5163 pps_unlock(intel_dp);
dada1a9f 5164 }
0095e6dc 5165
9d1a1031 5166 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5167
0e32b39c
DA		 5168 /* init MST on ports that can support it */
5169 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5170 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5171 intel_dp_mst_encoder_init(intel_dig_port,
5172 intel_connector->base.base.id);
0e32b39c
DA		 5173 }
5174 }
5175
0095e6dc 5176 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5177 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5178 if (is_edp(intel_dp)) {
5179 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5180 /*
5181 * vdd might still be enabled do to the delayed vdd off.
5182 * Make sure vdd is actually turned off here.
5183 */
773538e8 5184 pps_lock(intel_dp);
4be73780 5185 edp_panel_vdd_off_sync(intel_dp);
773538e8 5186 pps_unlock(intel_dp);
15b1d171 5187 }
34ea3d38 5188 drm_connector_unregister(connector);
b2f246a8 5189 drm_connector_cleanup(connector);
16c25533 5190 return false;
b2f246a8 5191 }
32f9d658 5192
f684960e
CW		 5193 intel_dp_add_properties(intel_dp, connector);
5194
a4fc5ed6
KP		 5195 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5196 * 0xd. Failure to do so will result in spurious interrupts being
5197 * generated on the port when a cable is not attached.
5198 */
5199 if (IS_G4X(dev) && !IS_GM45(dev)) {
5200 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5201 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5202 }
16c25533
PZ		 5203
5204 return true;
a4fc5ed6 5205}
f0fec3f2
PZ		 5206
5207void
5208intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5209{
13cf5504 5210 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5211 struct intel_digital_port *intel_dig_port;
5212 struct intel_encoder *intel_encoder;
5213 struct drm_encoder *encoder;
5214 struct intel_connector *intel_connector;
5215
b14c5679 5216 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5217 if (!intel_dig_port)
5218 return;
5219
b14c5679 5220 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5221 if (!intel_connector) {
5222 kfree(intel_dig_port);
5223 return;
5224 }
5225
5226 intel_encoder = &intel_dig_port->base;
5227 encoder = &intel_encoder->base;
5228
5229 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5230 DRM_MODE_ENCODER_TMDS);
5231
5bfe2ac0 5232 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5233 intel_encoder->disable = intel_disable_dp;
00c09d70 5234 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5235 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5236 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5237 if (IS_CHERRYVIEW(dev)) {
9197c88b 5238 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5239 intel_encoder->pre_enable = chv_pre_enable_dp;
5240 intel_encoder->enable = vlv_enable_dp;
580d3811 5241 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5242 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5243 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5244 intel_encoder->pre_enable = vlv_pre_enable_dp;
5245 intel_encoder->enable = vlv_enable_dp;
49277c31 5246 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5247 } else {
ecff4f3b
JN		 5248 intel_encoder->pre_enable = g4x_pre_enable_dp;
5249 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5250 if (INTEL_INFO(dev)->gen >= 5)
5251 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5252 }
f0fec3f2 5253
174edf1f 5254 intel_dig_port->port = port;
f0fec3f2
PZ		 5255 intel_dig_port->dp.output_reg = output_reg;
5256
00c09d70 5257 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5258 if (IS_CHERRYVIEW(dev)) {
5259 if (port == PORT_D)
5260 intel_encoder->crtc_mask = 1 << 2;
5261 else
5262 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5263 } else {
5264 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5265 }
bc079e8b 5266 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5267 intel_encoder->hot_plug = intel_dp_hot_plug;
5268
13cf5504
DA		 5269 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5270 dev_priv->hpd_irq_port[port] = intel_dig_port;
5271
15b1d171
PZ		 5272 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5273 drm_encoder_cleanup(encoder);
5274 kfree(intel_dig_port);
b2f246a8 5275 kfree(intel_connector);
15b1d171 5276 }
f0fec3f2 5277}
0e32b39c
DA		 5278
5279void intel_dp_mst_suspend(struct drm_device *dev)
5280{
5281 struct drm_i915_private *dev_priv = dev->dev_private;
5282 int i;
5283
5284 /* disable MST */
5285 for (i = 0; i < I915_MAX_PORTS; i++) {
5286 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5287 if (!intel_dig_port)
5288 continue;
5289
5290 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5291 if (!intel_dig_port->dp.can_mst)
5292 continue;
5293 if (intel_dig_port->dp.is_mst)
5294 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5295 }
5296 }
5297}
5298
5299void intel_dp_mst_resume(struct drm_device *dev)
5300{
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302 int i;
5303
5304 for (i = 0; i < I915_MAX_PORTS; i++) {
5305 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5306 if (!intel_dig_port)
5307 continue;
5308 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5309 int ret;
5310
5311 if (!intel_dig_port->dp.can_mst)
5312 continue;
5313
5314 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5315 if (ret != 0) {
5316 intel_dp_check_mst_status(&intel_dig_port->dp);
5317 }
5318 }
5319 }
5320}
Linux kernel - Deliverables
This page took 0.827854 seconds and 5 git commands to generate.