[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp_link_training.c

/*
 * Copyright © 2008-2015 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#include "intel_drv.h"

static void
intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
{

	DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
		      link_status[0], link_status[1], link_status[2],
		      link_status[3], link_status[4], link_status[5]);
}

static void
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
	uint8_t voltage_max;
	uint8_t preemph_max;

	for (lane = 0; lane < intel_dp->lane_count; lane++) {
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

	voltage_max = intel_dp_voltage_max(intel_dp);
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;

	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

	for (lane = 0; lane < 4; lane++)
		intel_dp->train_set[lane] = v | p;
}

static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
			uint8_t dp_train_pat)
{
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;

	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);

	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
	    DP_TRAINING_PATTERN_DISABLE) {
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
	}

	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);

	return ret == len;
}

static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp,
			uint8_t dp_train_pat)
{
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
	intel_dp_set_signal_levels(intel_dp);
	return intel_dp_set_link_train(intel_dp, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp)
{
	int ret;

	intel_dp_set_signal_levels(intel_dp);

	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
				intel_dp->train_set, intel_dp->lane_count);

	return ret == intel_dp->lane_count;
}

static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
{
	int lane;

	for (lane = 0; lane < intel_dp->lane_count; lane++)
		if ((intel_dp->train_set[lane] &
		     DP_TRAIN_MAX_SWING_REACHED) == 0)
			return false;

	return true;
}

/* Enable corresponding port and start training pattern 1 */
static bool
intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
{
	uint8_t voltage;
	int voltage_tries, max_vswing_tries;
	uint8_t link_config[2];
	uint8_t link_bw, rate_select;

	if (intel_dp->prepare_link_retrain)
		intel_dp->prepare_link_retrain(intel_dp);

	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
			      &link_bw, &rate_select);

	/* Write the link configuration data */
	link_config[0] = link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);

	if (intel_dp->num_sink_rates)
		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
				  &rate_select, 1);

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

	intel_dp->DP |= DP_PORT_EN;

	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return false;
	}

	voltage_tries = 1;
	max_vswing_tries = 0;
	for (;;) {
		uint8_t link_status[DP_LINK_STATUS_SIZE];

		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);

		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
			return false;
		}

		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
			DRM_DEBUG_KMS("clock recovery OK\n");
			return true;
		}

		if (voltage_tries == 5) {
			DRM_DEBUG_KMS("Same voltage tried 5 times\n");
			return false;
		}

		if (max_vswing_tries == 1) {
			DRM_DEBUG_KMS("Max Voltage Swing reached\n");
			return false;
		}

		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;

		/* Update training set as requested by target */
		intel_get_adjust_train(intel_dp, link_status);
		if (!intel_dp_update_link_train(intel_dp)) {
			DRM_ERROR("failed to update link training\n");
			return false;
		}

		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
		    voltage)
			++voltage_tries;
		else
			voltage_tries = 1;

		if (intel_dp_link_max_vswing_reached(intel_dp))
			++max_vswing_tries;

	}
}

/*
 * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
 * or 1.2 devices that support it, Training Pattern 2 otherwise.
 */
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
{
	u32 training_pattern = DP_TRAINING_PATTERN_2;
	bool source_tps3, sink_tps3;

	/*
	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
	 * also mandatory for downstream devices that support HBR2. However, not
	 * all sinks follow the spec.
	 *
	 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
	 * supported in source but still not enabled.
	 */
	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);

	if (source_tps3 && sink_tps3) {
		training_pattern = DP_TRAINING_PATTERN_3;
	} else if (intel_dp->link_rate == 540000) {
		if (!source_tps3)
			DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
		if (!sink_tps3)
			DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
	}

	return training_pattern;
}

static bool
intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
{
	int tries;
	u32 training_pattern;
	uint8_t link_status[DP_LINK_STATUS_SIZE];

	training_pattern = intel_dp_training_pattern(intel_dp);

	/* channel equalization */
	if (!intel_dp_set_link_train(intel_dp,
				     training_pattern |
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return false;
	}

	intel_dp->channel_eq_status = false;
	for (tries = 0; tries < 5; tries++) {

		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
			break;
		}

		/* Make sure clock is still ok */
		if (!drm_dp_clock_recovery_ok(link_status,
					      intel_dp->lane_count)) {
			intel_dp_dump_link_status(link_status);
			DRM_DEBUG_KMS("Clock recovery check failed, cannot "
				      "continue channel equalization\n");
			break;
		}

		if (drm_dp_channel_eq_ok(link_status,
					 intel_dp->lane_count)) {
			intel_dp->channel_eq_status = true;
			DRM_DEBUG_KMS("Channel EQ done. DP Training "
				      "successful\n");
			break;
		}

		/* Update training set as requested by target */
		intel_get_adjust_train(intel_dp, link_status);
		if (!intel_dp_update_link_train(intel_dp)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
	}

	/* Try 5 times, else fail and try at lower BW */
	if (tries == 5) {
		intel_dp_dump_link_status(link_status);
		DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
	}

	intel_dp_set_idle_link_train(intel_dp);

	return intel_dp->channel_eq_status;

}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
	intel_dp_set_link_train(intel_dp,
				DP_TRAINING_PATTERN_DISABLE);
}

void
intel_dp_start_link_train(struct intel_dp *intel_dp)
{
	intel_dp_link_training_clock_recovery(intel_dp);
	intel_dp_link_training_channel_equalization(intel_dp);
}
Commit	Line	Data
94223d04 ACO	1	/*
	2	* Copyright © 2008-2015 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*/
	23
	24	#include "intel_drv.h"
	25
8ab5de2e PD	26	static void
	27	intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
	28	{
	29
	30	DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
	31	link_status[0], link_status[1], link_status[2],
	32	link_status[3], link_status[4], link_status[5]);
	33	}
	34
94223d04 ACO	35	static void
	36	intel_get_adjust_train(struct intel_dp *intel_dp,
	37	const uint8_t link_status[DP_LINK_STATUS_SIZE])
	38	{
	39	uint8_t v = 0;
	40	uint8_t p = 0;
	41	int lane;
	42	uint8_t voltage_max;
	43	uint8_t preemph_max;
	44
	45	for (lane = 0; lane < intel_dp->lane_count; lane++) {
	46	uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
	47	uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
	48
	49	if (this_v > v)
	50	v = this_v;
	51	if (this_p > p)
	52	p = this_p;
	53	}
	54
	55	voltage_max = intel_dp_voltage_max(intel_dp);
	56	if (v >= voltage_max)
	57	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
	58
	59	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	60	if (p >= preemph_max)
	61	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
	62
	63	for (lane = 0; lane < 4; lane++)
	64	intel_dp->train_set[lane] = v \| p;
	65	}
	66
	67	static bool
	68	intel_dp_set_link_train(struct intel_dp *intel_dp,
	69	uint8_t dp_train_pat)
	70	{
	71	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	72	int ret, len;
	73
	74	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
	75
	76	buf[0] = dp_train_pat;
	77	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
	78	DP_TRAINING_PATTERN_DISABLE) {
	79	/* don't write DP_TRAINING_LANEx_SET on disable */
	80	len = 1;
	81	} else {
	82	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
	83	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
	84	len = intel_dp->lane_count + 1;
	85	}
	86
	87	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
	88	buf, len);
	89
	90	return ret == len;
	91	}
	92
	93	static bool
	94	intel_dp_reset_link_train(struct intel_dp *intel_dp,
	95	uint8_t dp_train_pat)
	96	{
91df09d9	97	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
94223d04 ACO	98	intel_dp_set_signal_levels(intel_dp);
	99	return intel_dp_set_link_train(intel_dp, dp_train_pat);
	100	}
	101
	102	static bool
	103	intel_dp_update_link_train(struct intel_dp *intel_dp)
	104	{
	105	int ret;
	106
	107	intel_dp_set_signal_levels(intel_dp);
	108
	109	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
	110	intel_dp->train_set, intel_dp->lane_count);
	111
	112	return ret == intel_dp->lane_count;
	113	}
	114
7bfaddf0 DP	115	static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
	116	{
	117	int lane;
	118
	119	for (lane = 0; lane < intel_dp->lane_count; lane++)
	120	if ((intel_dp->train_set[lane] &
	121	DP_TRAIN_MAX_SWING_REACHED) == 0)
	122	return false;
	123
	124	return true;
	125	}
	126
94223d04	127	/* Enable corresponding port and start training pattern 1 */
13b1996e	128	static bool
94223d04 ACO	129	intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
94223d04 ACO	130	{
94223d04	131	uint8_t voltage;
13b1996e	132	int voltage_tries, max_vswing_tries;
94223d04 ACO	133	uint8_t link_config[2];
	134	uint8_t link_bw, rate_select;
	135
ad64217b ACO	136	if (intel_dp->prepare_link_retrain)
ad64217b ACO	137	intel_dp->prepare_link_retrain(intel_dp);
94223d04 ACO	138
	139	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
	140	&link_bw, &rate_select);
	141
	142	/* Write the link configuration data */
	143	link_config[0] = link_bw;
	144	link_config[1] = intel_dp->lane_count;
	145	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
	146	link_config[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	147	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
13b1996e	148
94223d04 ACO	149	if (intel_dp->num_sink_rates)
	150	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
	151	&rate_select, 1);
	152
	153	link_config[0] = 0;
	154	link_config[1] = DP_SET_ANSI_8B10B;
	155	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
	156
	157	intel_dp->DP \|= DP_PORT_EN;
	158
	159	/* clock recovery */
	160	if (!intel_dp_reset_link_train(intel_dp,
	161	DP_TRAINING_PATTERN_1 \|
	162	DP_LINK_SCRAMBLING_DISABLE)) {
	163	DRM_ERROR("failed to enable link training\n");
13b1996e	164	return false;
94223d04 ACO	165	}
94223d04 ACO	166
13b1996e DP	167	voltage_tries = 1;
13b1996e DP	168	max_vswing_tries = 0;
94223d04 ACO	169	for (;;) {
	170	uint8_t link_status[DP_LINK_STATUS_SIZE];
	171
	172	drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
13b1996e	173
94223d04 ACO	174	if (!intel_dp_get_link_status(intel_dp, link_status)) {
94223d04 ACO	175	DRM_ERROR("failed to get link status\n");
13b1996e	176	return false;
94223d04 ACO	177	}
	178
	179	if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
	180	DRM_DEBUG_KMS("clock recovery OK\n");
13b1996e	181	return true;
94223d04 ACO	182	}
94223d04 ACO	183
13b1996e DP	184	if (voltage_tries == 5) {
	185	DRM_DEBUG_KMS("Same voltage tried 5 times\n");
	186	return false;
	187	}
	188
	189	if (max_vswing_tries == 1) {
	190	DRM_DEBUG_KMS("Max Voltage Swing reached\n");
	191	return false;
94223d04 ACO	192	}
94223d04 ACO	193
94223d04 ACO	194	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	195
	196	/* Update training set as requested by target */
	197	intel_get_adjust_train(intel_dp, link_status);
	198	if (!intel_dp_update_link_train(intel_dp)) {
	199	DRM_ERROR("failed to update link training\n");
13b1996e	200	return false;
94223d04	201	}
13b1996e DP	202
	203	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
	204	voltage)
	205	++voltage_tries;
	206	else
	207	voltage_tries = 1;
	208
	209	if (intel_dp_link_max_vswing_reached(intel_dp))
	210	++max_vswing_tries;
	211
94223d04 ACO	212	}
	213	}
	214
23a5110d JN	215	/*
	216	* Pick training pattern for channel equalization. Training Pattern 3 for HBR2
	217	* or 1.2 devices that support it, Training Pattern 2 otherwise.
	218	*/
	219	static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
94223d04	220	{
23a5110d	221	u32 training_pattern = DP_TRAINING_PATTERN_2;
bfcef5d2	222	bool source_tps3, sink_tps3;
94223d04 ACO	223
94223d04 ACO	224	/*
94223d04	225	* Intel platforms that support HBR2 also support TPS3. TPS3 support is
bfcef5d2 JN	226	* also mandatory for downstream devices that support HBR2. However, not
bfcef5d2 JN	227	* all sinks follow the spec.
94223d04 ACO	228	*
94223d04 ACO	229	* Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
bfcef5d2	230	* supported in source but still not enabled.
94223d04	231	*/
bfcef5d2 JN	232	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
	233	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
	234
	235	if (source_tps3 && sink_tps3) {
94223d04	236	training_pattern = DP_TRAINING_PATTERN_3;
bfcef5d2 JN	237	} else if (intel_dp->link_rate == 540000) {
	238	if (!source_tps3)
	239	DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
	240	if (!sink_tps3)
	241	DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
	242	}
94223d04	243
23a5110d JN	244	return training_pattern;
	245	}
	246
c92bd2fa	247	static bool
23a5110d JN	248	intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
23a5110d JN	249	{
c92bd2fa	250	int tries;
23a5110d	251	u32 training_pattern;
c92bd2fa	252	uint8_t link_status[DP_LINK_STATUS_SIZE];
23a5110d JN	253
	254	training_pattern = intel_dp_training_pattern(intel_dp);
	255
94223d04 ACO	256	/* channel equalization */
	257	if (!intel_dp_set_link_train(intel_dp,
	258	training_pattern \|
	259	DP_LINK_SCRAMBLING_DISABLE)) {
	260	DRM_ERROR("failed to start channel equalization\n");
c92bd2fa	261	return false;
94223d04 ACO	262	}
94223d04 ACO	263
c92bd2fa NM	264	intel_dp->channel_eq_status = false;
c92bd2fa NM	265	for (tries = 0; tries < 5; tries++) {
94223d04 ACO	266
	267	drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
	268	if (!intel_dp_get_link_status(intel_dp, link_status)) {
	269	DRM_ERROR("failed to get link status\n");
	270	break;
	271	}
	272
	273	/* Make sure clock is still ok */
	274	if (!drm_dp_clock_recovery_ok(link_status,
	275	intel_dp->lane_count)) {
c92bd2fa NM	276	intel_dp_dump_link_status(link_status);
	277	DRM_DEBUG_KMS("Clock recovery check failed, cannot "
	278	"continue channel equalization\n");
	279	break;
94223d04 ACO	280	}
	281
	282	if (drm_dp_channel_eq_ok(link_status,
	283	intel_dp->lane_count)) {
c92bd2fa NM	284	intel_dp->channel_eq_status = true;
	285	DRM_DEBUG_KMS("Channel EQ done. DP Training "
	286	"successful\n");
94223d04 ACO	287	break;
	288	}
	289
94223d04 ACO	290	/* Update training set as requested by target */
	291	intel_get_adjust_train(intel_dp, link_status);
	292	if (!intel_dp_update_link_train(intel_dp)) {
	293	DRM_ERROR("failed to update link training\n");
	294	break;
	295	}
c92bd2fa NM	296	}
	297
	298	/* Try 5 times, else fail and try at lower BW */
	299	if (tries == 5) {
	300	intel_dp_dump_link_status(link_status);
	301	DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
94223d04 ACO	302	}
	303
	304	intel_dp_set_idle_link_train(intel_dp);
	305
c92bd2fa NM	306	return intel_dp->channel_eq_status;
c92bd2fa NM	307
94223d04 ACO	308	}
	309
	310	void intel_dp_stop_link_train(struct intel_dp *intel_dp)
	311	{
	312	intel_dp_set_link_train(intel_dp,
	313	DP_TRAINING_PATTERN_DISABLE);
	314	}
	315
	316	void
	317	intel_dp_start_link_train(struct intel_dp *intel_dp)
	318	{
	319	intel_dp_link_training_clock_recovery(intel_dp);
	320	intel_dp_link_training_channel_equalization(intel_dp);
	321	}