Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_dp_link_training.c
CommitLineData
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1/*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "intel_drv.h"
25
8ab5de2e
PD
26static void
27intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
28{
29
30 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
31 link_status[0], link_status[1], link_status[2],
32 link_status[3], link_status[4], link_status[5]);
33}
34
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35static void
36intel_get_adjust_train(struct intel_dp *intel_dp,
37 const uint8_t link_status[DP_LINK_STATUS_SIZE])
38{
39 uint8_t v = 0;
40 uint8_t p = 0;
41 int lane;
42 uint8_t voltage_max;
43 uint8_t preemph_max;
44
45 for (lane = 0; lane < intel_dp->lane_count; lane++) {
46 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
47 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
48
49 if (this_v > v)
50 v = this_v;
51 if (this_p > p)
52 p = this_p;
53 }
54
55 voltage_max = intel_dp_voltage_max(intel_dp);
56 if (v >= voltage_max)
57 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
58
59 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
60 if (p >= preemph_max)
61 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
62
63 for (lane = 0; lane < 4; lane++)
64 intel_dp->train_set[lane] = v | p;
65}
66
67static bool
68intel_dp_set_link_train(struct intel_dp *intel_dp,
69 uint8_t dp_train_pat)
70{
71 uint8_t buf[sizeof(intel_dp->train_set) + 1];
72 int ret, len;
73
74 intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
75
76 buf[0] = dp_train_pat;
77 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
78 DP_TRAINING_PATTERN_DISABLE) {
79 /* don't write DP_TRAINING_LANEx_SET on disable */
80 len = 1;
81 } else {
82 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
83 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
84 len = intel_dp->lane_count + 1;
85 }
86
87 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
88 buf, len);
89
90 return ret == len;
91}
92
93static bool
94intel_dp_reset_link_train(struct intel_dp *intel_dp,
95 uint8_t dp_train_pat)
96{
91df09d9 97 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
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98 intel_dp_set_signal_levels(intel_dp);
99 return intel_dp_set_link_train(intel_dp, dp_train_pat);
100}
101
102static bool
103intel_dp_update_link_train(struct intel_dp *intel_dp)
104{
105 int ret;
106
107 intel_dp_set_signal_levels(intel_dp);
108
109 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
110 intel_dp->train_set, intel_dp->lane_count);
111
112 return ret == intel_dp->lane_count;
113}
114
7bfaddf0
DP
115static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
116{
117 int lane;
118
119 for (lane = 0; lane < intel_dp->lane_count; lane++)
120 if ((intel_dp->train_set[lane] &
121 DP_TRAIN_MAX_SWING_REACHED) == 0)
122 return false;
123
124 return true;
125}
126
94223d04 127/* Enable corresponding port and start training pattern 1 */
13b1996e 128static bool
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129intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
130{
94223d04 131 uint8_t voltage;
13b1996e 132 int voltage_tries, max_vswing_tries;
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133 uint8_t link_config[2];
134 uint8_t link_bw, rate_select;
135
ad64217b
ACO
136 if (intel_dp->prepare_link_retrain)
137 intel_dp->prepare_link_retrain(intel_dp);
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138
139 intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
140 &link_bw, &rate_select);
141
142 /* Write the link configuration data */
143 link_config[0] = link_bw;
144 link_config[1] = intel_dp->lane_count;
145 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
146 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
147 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
13b1996e 148
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149 if (intel_dp->num_sink_rates)
150 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
151 &rate_select, 1);
152
153 link_config[0] = 0;
154 link_config[1] = DP_SET_ANSI_8B10B;
155 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
156
157 intel_dp->DP |= DP_PORT_EN;
158
159 /* clock recovery */
160 if (!intel_dp_reset_link_train(intel_dp,
161 DP_TRAINING_PATTERN_1 |
162 DP_LINK_SCRAMBLING_DISABLE)) {
163 DRM_ERROR("failed to enable link training\n");
13b1996e 164 return false;
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165 }
166
13b1996e
DP
167 voltage_tries = 1;
168 max_vswing_tries = 0;
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169 for (;;) {
170 uint8_t link_status[DP_LINK_STATUS_SIZE];
171
172 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
13b1996e 173
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174 if (!intel_dp_get_link_status(intel_dp, link_status)) {
175 DRM_ERROR("failed to get link status\n");
13b1996e 176 return false;
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177 }
178
179 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
180 DRM_DEBUG_KMS("clock recovery OK\n");
13b1996e 181 return true;
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182 }
183
13b1996e
DP
184 if (voltage_tries == 5) {
185 DRM_DEBUG_KMS("Same voltage tried 5 times\n");
186 return false;
187 }
188
189 if (max_vswing_tries == 1) {
190 DRM_DEBUG_KMS("Max Voltage Swing reached\n");
191 return false;
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192 }
193
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194 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
195
196 /* Update training set as requested by target */
197 intel_get_adjust_train(intel_dp, link_status);
198 if (!intel_dp_update_link_train(intel_dp)) {
199 DRM_ERROR("failed to update link training\n");
13b1996e 200 return false;
94223d04 201 }
13b1996e
DP
202
203 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
204 voltage)
205 ++voltage_tries;
206 else
207 voltage_tries = 1;
208
209 if (intel_dp_link_max_vswing_reached(intel_dp))
210 ++max_vswing_tries;
211
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212 }
213}
214
23a5110d
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215/*
216 * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
217 * or 1.2 devices that support it, Training Pattern 2 otherwise.
218 */
219static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
94223d04 220{
23a5110d 221 u32 training_pattern = DP_TRAINING_PATTERN_2;
bfcef5d2 222 bool source_tps3, sink_tps3;
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223
224 /*
94223d04 225 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
bfcef5d2
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226 * also mandatory for downstream devices that support HBR2. However, not
227 * all sinks follow the spec.
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228 *
229 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
bfcef5d2 230 * supported in source but still not enabled.
94223d04 231 */
bfcef5d2
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232 source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
233 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
234
235 if (source_tps3 && sink_tps3) {
94223d04 236 training_pattern = DP_TRAINING_PATTERN_3;
bfcef5d2
JN
237 } else if (intel_dp->link_rate == 540000) {
238 if (!source_tps3)
239 DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
240 if (!sink_tps3)
241 DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
242 }
94223d04 243
23a5110d
JN
244 return training_pattern;
245}
246
c92bd2fa 247static bool
23a5110d
JN
248intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
249{
c92bd2fa 250 int tries;
23a5110d 251 u32 training_pattern;
c92bd2fa 252 uint8_t link_status[DP_LINK_STATUS_SIZE];
23a5110d
JN
253
254 training_pattern = intel_dp_training_pattern(intel_dp);
255
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256 /* channel equalization */
257 if (!intel_dp_set_link_train(intel_dp,
258 training_pattern |
259 DP_LINK_SCRAMBLING_DISABLE)) {
260 DRM_ERROR("failed to start channel equalization\n");
c92bd2fa 261 return false;
94223d04
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262 }
263
c92bd2fa
NM
264 intel_dp->channel_eq_status = false;
265 for (tries = 0; tries < 5; tries++) {
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266
267 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
268 if (!intel_dp_get_link_status(intel_dp, link_status)) {
269 DRM_ERROR("failed to get link status\n");
270 break;
271 }
272
273 /* Make sure clock is still ok */
274 if (!drm_dp_clock_recovery_ok(link_status,
275 intel_dp->lane_count)) {
c92bd2fa
NM
276 intel_dp_dump_link_status(link_status);
277 DRM_DEBUG_KMS("Clock recovery check failed, cannot "
278 "continue channel equalization\n");
279 break;
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280 }
281
282 if (drm_dp_channel_eq_ok(link_status,
283 intel_dp->lane_count)) {
c92bd2fa
NM
284 intel_dp->channel_eq_status = true;
285 DRM_DEBUG_KMS("Channel EQ done. DP Training "
286 "successful\n");
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287 break;
288 }
289
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290 /* Update training set as requested by target */
291 intel_get_adjust_train(intel_dp, link_status);
292 if (!intel_dp_update_link_train(intel_dp)) {
293 DRM_ERROR("failed to update link training\n");
294 break;
295 }
c92bd2fa
NM
296 }
297
298 /* Try 5 times, else fail and try at lower BW */
299 if (tries == 5) {
300 intel_dp_dump_link_status(link_status);
301 DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
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302 }
303
304 intel_dp_set_idle_link_train(intel_dp);
305
c92bd2fa
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306 return intel_dp->channel_eq_status;
307
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308}
309
310void intel_dp_stop_link_train(struct intel_dp *intel_dp)
311{
312 intel_dp_set_link_train(intel_dp,
313 DP_TRAINING_PATTERN_DISABLE);
314}
315
316void
317intel_dp_start_link_train(struct intel_dp *intel_dp)
318{
319 intel_dp_link_training_clock_recovery(intel_dp);
320 intel_dp_link_training_channel_equalization(intel_dp);
321}
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