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4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
c6f95f27 | 27 | #include <drm/drm_atomic_helper.h> |
4e646495 JN |
28 | #include <drm/drm_crtc.h> |
29 | #include <drm/drm_edid.h> | |
30 | #include <drm/i915_drm.h> | |
593e0622 | 31 | #include <drm/drm_panel.h> |
7e9804fd | 32 | #include <drm/drm_mipi_dsi.h> |
4e646495 | 33 | #include <linux/slab.h> |
fc45e821 | 34 | #include <linux/gpio/consumer.h> |
4e646495 JN |
35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" | |
37 | #include "intel_dsi.h" | |
4e646495 | 38 | |
593e0622 JN |
39 | static const struct { |
40 | u16 panel_id; | |
41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); | |
42 | } intel_dsi_drivers[] = { | |
2ab8b458 SK |
43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
593e0622 | 45 | .init = vbt_panel_init, |
2ab8b458 | 46 | }, |
4e646495 JN |
47 | }; |
48 | ||
042ab0c3 R |
49 | /* return pixels in terms of txbyteclkhs */ |
50 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, | |
51 | u16 burst_mode_ratio) | |
52 | { | |
53 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, | |
54 | 8 * 100), lane_count); | |
55 | } | |
56 | ||
cefc4e18 R |
57 | /* return pixels equvalent to txbyteclkhs */ |
58 | static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, | |
59 | u16 burst_mode_ratio) | |
60 | { | |
61 | return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), | |
62 | (bpp * burst_mode_ratio)); | |
63 | } | |
64 | ||
43367ec9 R |
65 | enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt) |
66 | { | |
67 | /* It just so happens the VBT matches register contents. */ | |
68 | switch (fmt) { | |
69 | case VID_MODE_FORMAT_RGB888: | |
70 | return MIPI_DSI_FMT_RGB888; | |
71 | case VID_MODE_FORMAT_RGB666: | |
72 | return MIPI_DSI_FMT_RGB666; | |
73 | case VID_MODE_FORMAT_RGB666_PACKED: | |
74 | return MIPI_DSI_FMT_RGB666_PACKED; | |
75 | case VID_MODE_FORMAT_RGB565: | |
76 | return MIPI_DSI_FMT_RGB565; | |
77 | default: | |
78 | MISSING_CASE(fmt); | |
79 | return MIPI_DSI_FMT_RGB666; | |
80 | } | |
81 | } | |
82 | ||
7f6a6a4a | 83 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
3b1808bf JN |
84 | { |
85 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
86 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 87 | struct drm_i915_private *dev_priv = to_i915(dev); |
3b1808bf JN |
88 | u32 mask; |
89 | ||
90 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | | |
91 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; | |
92 | ||
9b6a2d72 CW |
93 | if (intel_wait_for_register(dev_priv, |
94 | MIPI_GEN_FIFO_STAT(port), mask, mask, | |
95 | 100)) | |
3b1808bf JN |
96 | DRM_ERROR("DPI FIFOs are not empty\n"); |
97 | } | |
98 | ||
f0f59a00 VS |
99 | static void write_data(struct drm_i915_private *dev_priv, |
100 | i915_reg_t reg, | |
7e9804fd JN |
101 | const u8 *data, u32 len) |
102 | { | |
103 | u32 i, j; | |
104 | ||
105 | for (i = 0; i < len; i += 4) { | |
106 | u32 val = 0; | |
107 | ||
108 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
109 | val |= *data++ << 8 * j; | |
110 | ||
111 | I915_WRITE(reg, val); | |
112 | } | |
113 | } | |
114 | ||
f0f59a00 VS |
115 | static void read_data(struct drm_i915_private *dev_priv, |
116 | i915_reg_t reg, | |
7e9804fd JN |
117 | u8 *data, u32 len) |
118 | { | |
119 | u32 i, j; | |
120 | ||
121 | for (i = 0; i < len; i += 4) { | |
122 | u32 val = I915_READ(reg); | |
123 | ||
124 | for (j = 0; j < min_t(u32, len - i, 4); j++) | |
125 | *data++ = val >> 8 * j; | |
126 | } | |
127 | } | |
128 | ||
129 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, | |
130 | const struct mipi_dsi_msg *msg) | |
131 | { | |
132 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); | |
133 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; | |
fac5e23e | 134 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e9804fd JN |
135 | enum port port = intel_dsi_host->port; |
136 | struct mipi_dsi_packet packet; | |
137 | ssize_t ret; | |
138 | const u8 *header, *data; | |
f0f59a00 VS |
139 | i915_reg_t data_reg, ctrl_reg; |
140 | u32 data_mask, ctrl_mask; | |
7e9804fd JN |
141 | |
142 | ret = mipi_dsi_create_packet(&packet, msg); | |
143 | if (ret < 0) | |
144 | return ret; | |
145 | ||
146 | header = packet.header; | |
147 | data = packet.payload; | |
148 | ||
149 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { | |
150 | data_reg = MIPI_LP_GEN_DATA(port); | |
151 | data_mask = LP_DATA_FIFO_FULL; | |
152 | ctrl_reg = MIPI_LP_GEN_CTRL(port); | |
153 | ctrl_mask = LP_CTRL_FIFO_FULL; | |
154 | } else { | |
155 | data_reg = MIPI_HS_GEN_DATA(port); | |
156 | data_mask = HS_DATA_FIFO_FULL; | |
157 | ctrl_reg = MIPI_HS_GEN_CTRL(port); | |
158 | ctrl_mask = HS_CTRL_FIFO_FULL; | |
159 | } | |
160 | ||
161 | /* note: this is never true for reads */ | |
162 | if (packet.payload_length) { | |
8c6cea0b CW |
163 | if (intel_wait_for_register(dev_priv, |
164 | MIPI_GEN_FIFO_STAT(port), | |
165 | data_mask, 0, | |
166 | 50)) | |
7e9804fd JN |
167 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
168 | ||
169 | write_data(dev_priv, data_reg, packet.payload, | |
170 | packet.payload_length); | |
171 | } | |
172 | ||
173 | if (msg->rx_len) { | |
174 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); | |
175 | } | |
176 | ||
84c2aa90 CW |
177 | if (intel_wait_for_register(dev_priv, |
178 | MIPI_GEN_FIFO_STAT(port), | |
179 | ctrl_mask, 0, | |
180 | 50)) { | |
7e9804fd JN |
181 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
182 | } | |
183 | ||
184 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); | |
185 | ||
186 | /* ->rx_len is set only for reads */ | |
187 | if (msg->rx_len) { | |
188 | data_mask = GEN_READ_DATA_AVAIL; | |
e7615b37 CW |
189 | if (intel_wait_for_register(dev_priv, |
190 | MIPI_INTR_STAT(port), | |
191 | data_mask, data_mask, | |
192 | 50)) | |
7e9804fd JN |
193 | DRM_ERROR("Timeout waiting for read data.\n"); |
194 | ||
195 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); | |
196 | } | |
197 | ||
198 | /* XXX: fix for reads and writes */ | |
199 | return 4 + packet.payload_length; | |
200 | } | |
201 | ||
202 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, | |
203 | struct mipi_dsi_device *dsi) | |
204 | { | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, | |
209 | struct mipi_dsi_device *dsi) | |
210 | { | |
211 | return 0; | |
212 | } | |
213 | ||
214 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { | |
215 | .attach = intel_dsi_host_attach, | |
216 | .detach = intel_dsi_host_detach, | |
217 | .transfer = intel_dsi_host_transfer, | |
218 | }; | |
219 | ||
220 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, | |
221 | enum port port) | |
222 | { | |
223 | struct intel_dsi_host *host; | |
224 | struct mipi_dsi_device *device; | |
225 | ||
226 | host = kzalloc(sizeof(*host), GFP_KERNEL); | |
227 | if (!host) | |
228 | return NULL; | |
229 | ||
230 | host->base.ops = &intel_dsi_host_ops; | |
231 | host->intel_dsi = intel_dsi; | |
232 | host->port = port; | |
233 | ||
234 | /* | |
235 | * We should call mipi_dsi_host_register(&host->base) here, but we don't | |
236 | * have a host->dev, and we don't have OF stuff either. So just use the | |
237 | * dsi framework as a library and hope for the best. Create the dsi | |
238 | * devices by ourselves here too. Need to be careful though, because we | |
239 | * don't initialize any of the driver model devices here. | |
240 | */ | |
241 | device = kzalloc(sizeof(*device), GFP_KERNEL); | |
242 | if (!device) { | |
243 | kfree(host); | |
244 | return NULL; | |
245 | } | |
246 | ||
247 | device->host = &host->base; | |
248 | host->device = device; | |
249 | ||
250 | return host; | |
251 | } | |
252 | ||
a2581a9e JN |
253 | /* |
254 | * send a video mode command | |
255 | * | |
256 | * XXX: commands with data in MIPI_DPI_DATA? | |
257 | */ | |
258 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, | |
259 | enum port port) | |
260 | { | |
261 | struct drm_encoder *encoder = &intel_dsi->base.base; | |
262 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 263 | struct drm_i915_private *dev_priv = to_i915(dev); |
a2581a9e JN |
264 | u32 mask; |
265 | ||
266 | /* XXX: pipe, hs */ | |
267 | if (hs) | |
268 | cmd &= ~DPI_LP_MODE; | |
269 | else | |
270 | cmd |= DPI_LP_MODE; | |
271 | ||
272 | /* clear bit */ | |
273 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); | |
274 | ||
275 | /* XXX: old code skips write if control unchanged */ | |
276 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) | |
277 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); | |
278 | ||
279 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); | |
280 | ||
281 | mask = SPL_PKT_SENT_INTERRUPT; | |
2af05078 CW |
282 | if (intel_wait_for_register(dev_priv, |
283 | MIPI_INTR_STAT(port), mask, mask, | |
284 | 100)) | |
a2581a9e JN |
285 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
e9fe51c6 | 290 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 | 291 | { |
a580516d | 292 | mutex_lock(&dev_priv->sb_lock); |
4ce8c9a7 | 293 | |
e9fe51c6 SK |
294 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
295 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
296 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
297 | udelay(150); | |
298 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
299 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 | 300 | |
a580516d | 301 | mutex_unlock(&dev_priv->sb_lock); |
4ce8c9a7 SK |
302 | } |
303 | ||
4e646495 JN |
304 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
305 | { | |
dfba2e2d | 306 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
307 | } |
308 | ||
309 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
310 | { | |
dfba2e2d | 311 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
312 | } |
313 | ||
4e646495 | 314 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
315 | struct intel_crtc_state *pipe_config, |
316 | struct drm_connector_state *conn_state) | |
4e646495 | 317 | { |
fac5e23e | 318 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
4e646495 JN |
319 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
320 | base); | |
321 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
f4ee265f VS |
322 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
323 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
a65347ba | 324 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
47eacbab | 325 | int ret; |
4e646495 JN |
326 | |
327 | DRM_DEBUG_KMS("\n"); | |
328 | ||
f4ee265f | 329 | if (fixed_mode) { |
4e646495 JN |
330 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
331 | ||
f4ee265f VS |
332 | if (HAS_GMCH_DISPLAY(dev_priv)) |
333 | intel_gmch_panel_fitting(crtc, pipe_config, | |
334 | intel_connector->panel.fitting_mode); | |
335 | else | |
336 | intel_pch_panel_fitting(crtc, pipe_config, | |
337 | intel_connector->panel.fitting_mode); | |
338 | } | |
339 | ||
f573de5a SK |
340 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
341 | adjusted_mode->flags = 0; | |
342 | ||
4d1de975 JN |
343 | if (IS_BROXTON(dev_priv)) { |
344 | /* Dual link goes to DSI transcoder A. */ | |
345 | if (intel_dsi->ports == BIT(PORT_C)) | |
346 | pipe_config->cpu_transcoder = TRANSCODER_DSI_C; | |
347 | else | |
348 | pipe_config->cpu_transcoder = TRANSCODER_DSI_A; | |
349 | } | |
350 | ||
47eacbab VS |
351 | ret = intel_compute_dsi_pll(encoder, pipe_config); |
352 | if (ret) | |
353 | return false; | |
354 | ||
cd2d34d9 VS |
355 | pipe_config->clock_set = true; |
356 | ||
4e646495 JN |
357 | return true; |
358 | } | |
359 | ||
37ab0810 | 360 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
5505a244 | 361 | { |
fac5e23e | 362 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5505a244 | 363 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
369602d3 | 364 | enum port port; |
37ab0810 | 365 | u32 val; |
5505a244 | 366 | |
37ab0810 | 367 | DRM_DEBUG_KMS("\n"); |
a9da9bce | 368 | |
37ab0810 | 369 | /* Exit Low power state in 4 steps*/ |
369602d3 | 370 | for_each_dsi_port(port, intel_dsi->ports) { |
5505a244 | 371 | |
37ab0810 SS |
372 | /* 1. Enable MIPI PHY transparent latch */ |
373 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
374 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); | |
375 | usleep_range(2000, 2500); | |
376 | ||
377 | /* 2. Enter ULPS */ | |
378 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
379 | val &= ~ULPS_STATE_MASK; | |
380 | val |= (ULPS_STATE_ENTER | DEVICE_READY); | |
381 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
382 | usleep_range(2, 3); | |
383 | ||
384 | /* 3. Exit ULPS */ | |
385 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
386 | val &= ~ULPS_STATE_MASK; | |
387 | val |= (ULPS_STATE_EXIT | DEVICE_READY); | |
388 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
389 | usleep_range(1000, 1500); | |
5505a244 | 390 | |
37ab0810 SS |
391 | /* Clear ULPS and set device ready */ |
392 | val = I915_READ(MIPI_DEVICE_READY(port)); | |
393 | val &= ~ULPS_STATE_MASK; | |
394 | val |= DEVICE_READY; | |
395 | I915_WRITE(MIPI_DEVICE_READY(port), val); | |
369602d3 | 396 | } |
5505a244 GS |
397 | } |
398 | ||
37ab0810 | 399 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 400 | { |
fac5e23e | 401 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
24ee0e64 GS |
402 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
403 | enum port port; | |
1dbd7cb2 SK |
404 | u32 val; |
405 | ||
4e646495 | 406 | DRM_DEBUG_KMS("\n"); |
4e646495 | 407 | |
a580516d | 408 | mutex_lock(&dev_priv->sb_lock); |
2095f9fc SK |
409 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
410 | * needed everytime after power gate */ | |
411 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
a580516d | 412 | mutex_unlock(&dev_priv->sb_lock); |
2095f9fc SK |
413 | |
414 | /* bandgap reset is needed after everytime we do power gate */ | |
415 | band_gap_reset(dev_priv); | |
416 | ||
24ee0e64 | 417 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 418 | |
24ee0e64 GS |
419 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
420 | usleep_range(2500, 3000); | |
aceb365c | 421 | |
bf344e80 GS |
422 | /* Enable MIPI PHY transparent latch |
423 | * Common bit for both MIPI Port A & MIPI Port C | |
424 | * No similar bit in MIPI Port C reg | |
425 | */ | |
4ba7d93a | 426 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
bf344e80 | 427 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
24ee0e64 | 428 | usleep_range(1000, 1500); |
aceb365c | 429 | |
24ee0e64 GS |
430 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
431 | usleep_range(2500, 3000); | |
432 | ||
433 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
434 | usleep_range(2500, 3000); | |
435 | } | |
1dbd7cb2 | 436 | } |
1dbd7cb2 | 437 | |
37ab0810 SS |
438 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
439 | { | |
440 | struct drm_device *dev = encoder->base.dev; | |
441 | ||
666a4537 | 442 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
37ab0810 SS |
443 | vlv_dsi_device_ready(encoder); |
444 | else if (IS_BROXTON(dev)) | |
445 | bxt_dsi_device_ready(encoder); | |
446 | } | |
447 | ||
448 | static void intel_dsi_port_enable(struct intel_encoder *encoder) | |
449 | { | |
450 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 451 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
452 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
453 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
454 | enum port port; | |
37ab0810 SS |
455 | |
456 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { | |
f0f59a00 VS |
457 | u32 temp; |
458 | ||
37ab0810 SS |
459 | temp = I915_READ(VLV_CHICKEN_3); |
460 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
461 | intel_dsi->pixel_overlap << | |
462 | PIXEL_OVERLAP_CNT_SHIFT; | |
463 | I915_WRITE(VLV_CHICKEN_3, temp); | |
464 | } | |
465 | ||
466 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
467 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
468 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
469 | u32 temp; | |
37ab0810 SS |
470 | |
471 | temp = I915_READ(port_ctrl); | |
472 | ||
473 | temp &= ~LANE_CONFIGURATION_MASK; | |
474 | temp &= ~DUAL_LINK_MODE_MASK; | |
475 | ||
701d25b4 | 476 | if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { |
37ab0810 SS |
477 | temp |= (intel_dsi->dual_link - 1) |
478 | << DUAL_LINK_MODE_SHIFT; | |
479 | temp |= intel_crtc->pipe ? | |
480 | LANE_CONFIGURATION_DUAL_LINK_B : | |
481 | LANE_CONFIGURATION_DUAL_LINK_A; | |
482 | } | |
483 | /* assert ip_tg_enable signal */ | |
484 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); | |
485 | POSTING_READ(port_ctrl); | |
486 | } | |
487 | } | |
488 | ||
489 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
490 | { | |
491 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 492 | struct drm_i915_private *dev_priv = to_i915(dev); |
37ab0810 SS |
493 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
494 | enum port port; | |
37ab0810 SS |
495 | |
496 | for_each_dsi_port(port, intel_dsi->ports) { | |
f0f59a00 VS |
497 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
498 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
499 | u32 temp; | |
500 | ||
37ab0810 | 501 | /* de-assert ip_tg_enable signal */ |
b389a45c SS |
502 | temp = I915_READ(port_ctrl); |
503 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); | |
504 | POSTING_READ(port_ctrl); | |
37ab0810 SS |
505 | } |
506 | } | |
507 | ||
1dbd7cb2 SK |
508 | static void intel_dsi_enable(struct intel_encoder *encoder) |
509 | { | |
510 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 511 | struct drm_i915_private *dev_priv = to_i915(dev); |
1dbd7cb2 | 512 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
4934b656 | 513 | enum port port; |
1dbd7cb2 SK |
514 | |
515 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 516 | |
4934b656 JN |
517 | if (is_cmd_mode(intel_dsi)) { |
518 | for_each_dsi_port(port, intel_dsi->ports) | |
519 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); | |
520 | } else { | |
4e646495 | 521 | msleep(20); /* XXX */ |
f03e4179 | 522 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 523 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
4e646495 JN |
524 | msleep(100); |
525 | ||
593e0622 | 526 | drm_panel_enable(intel_dsi->panel); |
2634fd7f | 527 | |
7f6a6a4a JN |
528 | for_each_dsi_port(port, intel_dsi->ports) |
529 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 530 | |
5505a244 | 531 | intel_dsi_port_enable(encoder); |
4e646495 | 532 | } |
b029e66f SK |
533 | |
534 | intel_panel_enable_backlight(intel_dsi->attached_connector); | |
2634fd7f SK |
535 | } |
536 | ||
5eff0edf ML |
537 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
538 | struct intel_crtc_state *pipe_config); | |
e3488e75 | 539 | |
fd6bbda9 ML |
540 | static void intel_dsi_pre_enable(struct intel_encoder *encoder, |
541 | struct intel_crtc_state *pipe_config, | |
542 | struct drm_connector_state *conn_state) | |
2634fd7f | 543 | { |
5eff0edf | 544 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2634fd7f | 545 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
7f6a6a4a | 546 | enum port port; |
2634fd7f SK |
547 | |
548 | DRM_DEBUG_KMS("\n"); | |
549 | ||
f00b5689 VS |
550 | /* |
551 | * The BIOS may leave the PLL in a wonky state where it doesn't | |
552 | * lock. It needs to be fully powered down to fix it. | |
553 | */ | |
554 | intel_disable_dsi_pll(encoder); | |
5eff0edf | 555 | intel_enable_dsi_pll(encoder, pipe_config); |
f00b5689 | 556 | |
5eff0edf | 557 | intel_dsi_prepare(encoder, pipe_config); |
e3488e75 | 558 | |
fc45e821 SK |
559 | /* Panel Enable over CRC PMIC */ |
560 | if (intel_dsi->gpio_panel) | |
561 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); | |
562 | ||
563 | msleep(intel_dsi->panel_on_delay); | |
564 | ||
d1877c0f VS |
565 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
566 | u32 val; | |
567 | ||
cd2d34d9 | 568 | /* Disable DPOunit clock gating, can stall pipe */ |
d1877c0f VS |
569 | val = I915_READ(DSPCLK_GATE_D); |
570 | val |= DPOUNIT_CLOCK_GATE_DISABLE; | |
571 | I915_WRITE(DSPCLK_GATE_D, val); | |
37ab0810 | 572 | } |
2634fd7f SK |
573 | |
574 | /* put device in ready state */ | |
575 | intel_dsi_device_ready(encoder); | |
4e646495 | 576 | |
593e0622 | 577 | drm_panel_prepare(intel_dsi->panel); |
20e5bf66 | 578 | |
7f6a6a4a JN |
579 | for_each_dsi_port(port, intel_dsi->ports) |
580 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 581 | |
2634fd7f SK |
582 | /* Enable port in pre-enable phase itself because as per hw team |
583 | * recommendation, port should be enabled befor plane & pipe */ | |
584 | intel_dsi_enable(encoder); | |
585 | } | |
586 | ||
fd6bbda9 ML |
587 | static void intel_dsi_enable_nop(struct intel_encoder *encoder, |
588 | struct intel_crtc_state *pipe_config, | |
589 | struct drm_connector_state *conn_state) | |
2634fd7f SK |
590 | { |
591 | DRM_DEBUG_KMS("\n"); | |
592 | ||
593 | /* for DSI port enable has to be done before pipe | |
594 | * and plane enable, so port enable is done in | |
595 | * pre_enable phase itself unlike other encoders | |
596 | */ | |
4e646495 JN |
597 | } |
598 | ||
fd6bbda9 ML |
599 | static void intel_dsi_pre_disable(struct intel_encoder *encoder, |
600 | struct intel_crtc_state *old_crtc_state, | |
601 | struct drm_connector_state *old_conn_state) | |
c315faf8 ID |
602 | { |
603 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
f03e4179 | 604 | enum port port; |
c315faf8 ID |
605 | |
606 | DRM_DEBUG_KMS("\n"); | |
607 | ||
b029e66f SK |
608 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
609 | ||
c315faf8 ID |
610 | if (is_vid_mode(intel_dsi)) { |
611 | /* Send Shutdown command to the panel in LP mode */ | |
f03e4179 | 612 | for_each_dsi_port(port, intel_dsi->ports) |
a2581a9e | 613 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
c315faf8 ID |
614 | msleep(10); |
615 | } | |
616 | } | |
617 | ||
4e646495 JN |
618 | static void intel_dsi_disable(struct intel_encoder *encoder) |
619 | { | |
1dbd7cb2 | 620 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 621 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e646495 | 622 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 623 | enum port port; |
4e646495 JN |
624 | u32 temp; |
625 | ||
626 | DRM_DEBUG_KMS("\n"); | |
627 | ||
4e646495 | 628 | if (is_vid_mode(intel_dsi)) { |
7f6a6a4a JN |
629 | for_each_dsi_port(port, intel_dsi->ports) |
630 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
1381308b | 631 | |
5505a244 | 632 | intel_dsi_port_disable(encoder); |
4e646495 JN |
633 | msleep(2); |
634 | } | |
635 | ||
384f02a2 GS |
636 | for_each_dsi_port(port, intel_dsi->ports) { |
637 | /* Panel commands can be sent when clock is in LP11 */ | |
638 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 639 | |
b389a45c | 640 | intel_dsi_reset_clocks(encoder, port); |
384f02a2 | 641 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 642 | |
384f02a2 GS |
643 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
644 | temp &= ~VID_MODE_FORMAT_MASK; | |
645 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 646 | |
384f02a2 GS |
647 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
648 | } | |
1dbd7cb2 SK |
649 | /* if disable packets are sent before sending shutdown packet then in |
650 | * some next enable sequence send turn on packet error is observed */ | |
593e0622 | 651 | drm_panel_disable(intel_dsi->panel); |
1381308b | 652 | |
7f6a6a4a JN |
653 | for_each_dsi_port(port, intel_dsi->ports) |
654 | wait_for_dsi_fifo_empty(intel_dsi, port); | |
4e646495 JN |
655 | } |
656 | ||
1dbd7cb2 | 657 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 658 | { |
b389a45c | 659 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 660 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
384f02a2 GS |
661 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
662 | enum port port; | |
1dbd7cb2 | 663 | |
4e646495 | 664 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 665 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
666 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
667 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? | |
668 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); | |
669 | u32 val; | |
be4fc046 | 670 | |
384f02a2 GS |
671 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
672 | ULPS_STATE_ENTER); | |
673 | usleep_range(2000, 2500); | |
674 | ||
675 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
676 | ULPS_STATE_EXIT); | |
677 | usleep_range(2000, 2500); | |
678 | ||
679 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
680 | ULPS_STATE_ENTER); | |
681 | usleep_range(2000, 2500); | |
682 | ||
683 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
684 | * only. MIPI Port C has no similar bit for checking | |
685 | */ | |
0698cf60 CW |
686 | if (intel_wait_for_register(dev_priv, |
687 | port_ctrl, AFE_LATCHOUT, 0, | |
688 | 30)) | |
384f02a2 GS |
689 | DRM_ERROR("DSI LP not going Low\n"); |
690 | ||
b389a45c SS |
691 | /* Disable MIPI PHY transparent latch */ |
692 | val = I915_READ(port_ctrl); | |
693 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); | |
384f02a2 GS |
694 | usleep_range(1000, 1500); |
695 | ||
696 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
697 | usleep_range(2000, 2500); | |
698 | } | |
1dbd7cb2 | 699 | |
fe88fc68 | 700 | intel_disable_dsi_pll(encoder); |
4e646495 | 701 | } |
20e5bf66 | 702 | |
fd6bbda9 ML |
703 | static void intel_dsi_post_disable(struct intel_encoder *encoder, |
704 | struct intel_crtc_state *pipe_config, | |
705 | struct drm_connector_state *conn_state) | |
1dbd7cb2 | 706 | { |
fac5e23e | 707 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1dbd7cb2 SK |
708 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
709 | ||
710 | DRM_DEBUG_KMS("\n"); | |
711 | ||
c315faf8 ID |
712 | intel_dsi_disable(encoder); |
713 | ||
1dbd7cb2 SK |
714 | intel_dsi_clear_device_ready(encoder); |
715 | ||
d1877c0f | 716 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
d6e3af54 US |
717 | u32 val; |
718 | ||
719 | val = I915_READ(DSPCLK_GATE_D); | |
720 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
721 | I915_WRITE(DSPCLK_GATE_D, val); | |
722 | } | |
20e5bf66 | 723 | |
593e0622 | 724 | drm_panel_unprepare(intel_dsi->panel); |
df38e655 SK |
725 | |
726 | msleep(intel_dsi->panel_off_delay); | |
fc45e821 SK |
727 | |
728 | /* Panel Disable over CRC PMIC */ | |
729 | if (intel_dsi->gpio_panel) | |
730 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); | |
1d5c65ed VS |
731 | |
732 | /* | |
733 | * FIXME As we do with eDP, just make a note of the time here | |
734 | * and perform the wait before the next panel power on. | |
735 | */ | |
736 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 737 | } |
4e646495 JN |
738 | |
739 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
740 | enum pipe *pipe) | |
741 | { | |
fac5e23e | 742 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
c0beefd2 GS |
743 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
744 | struct drm_device *dev = encoder->base.dev; | |
6d129bea | 745 | enum intel_display_power_domain power_domain; |
e7d7cad0 | 746 | enum port port; |
1dcec2f3 | 747 | bool active = false; |
4e646495 JN |
748 | |
749 | DRM_DEBUG_KMS("\n"); | |
750 | ||
6d129bea | 751 | power_domain = intel_display_port_power_domain(encoder); |
3f3f42b8 | 752 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
753 | return false; |
754 | ||
db18b6a6 ID |
755 | /* |
756 | * On Broxton the PLL needs to be enabled with a valid divider | |
757 | * configuration, otherwise accessing DSI registers will hang the | |
758 | * machine. See BSpec North Display Engine registers/MIPI[BXT]. | |
759 | */ | |
760 | if (IS_BROXTON(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv)) | |
761 | goto out_put_power; | |
762 | ||
4e646495 | 763 | /* XXX: this only works for one DSI output */ |
c0beefd2 | 764 | for_each_dsi_port(port, intel_dsi->ports) { |
f0f59a00 VS |
765 | i915_reg_t ctrl_reg = IS_BROXTON(dev) ? |
766 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); | |
1dcec2f3 | 767 | bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
c0beefd2 | 768 | |
e6f57789 JN |
769 | /* |
770 | * Due to some hardware limitations on VLV/CHV, the DPI enable | |
771 | * bit in port C control register does not get set. As a | |
772 | * workaround, check pipe B conf instead. | |
c0beefd2 | 773 | */ |
e6f57789 | 774 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && port == PORT_C) |
1dcec2f3 | 775 | enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; |
4e646495 | 776 | |
1dcec2f3 JN |
777 | /* Try command mode if video mode not enabled */ |
778 | if (!enabled) { | |
779 | u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
780 | enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; | |
4e646495 | 781 | } |
1dcec2f3 JN |
782 | |
783 | if (!enabled) | |
784 | continue; | |
785 | ||
786 | if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) | |
787 | continue; | |
788 | ||
6b93e9c8 JN |
789 | if (IS_BROXTON(dev_priv)) { |
790 | u32 tmp = I915_READ(MIPI_CTRL(port)); | |
791 | tmp &= BXT_PIPE_SELECT_MASK; | |
792 | tmp >>= BXT_PIPE_SELECT_SHIFT; | |
793 | ||
794 | if (WARN_ON(tmp > PIPE_C)) | |
795 | continue; | |
796 | ||
797 | *pipe = tmp; | |
798 | } else { | |
799 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; | |
800 | } | |
801 | ||
1dcec2f3 JN |
802 | active = true; |
803 | break; | |
4e646495 | 804 | } |
1dcec2f3 | 805 | |
db18b6a6 | 806 | out_put_power: |
3f3f42b8 | 807 | intel_display_power_put(dev_priv, power_domain); |
4e646495 | 808 | |
1dcec2f3 | 809 | return active; |
4e646495 JN |
810 | } |
811 | ||
6f0e7535 R |
812 | static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, |
813 | struct intel_crtc_state *pipe_config) | |
814 | { | |
815 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 816 | struct drm_i915_private *dev_priv = to_i915(dev); |
6f0e7535 R |
817 | struct drm_display_mode *adjusted_mode = |
818 | &pipe_config->base.adjusted_mode; | |
042ab0c3 R |
819 | struct drm_display_mode *adjusted_mode_sw; |
820 | struct intel_crtc *intel_crtc; | |
6f0e7535 | 821 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
cefc4e18 | 822 | unsigned int lane_count = intel_dsi->lane_count; |
6f0e7535 R |
823 | unsigned int bpp, fmt; |
824 | enum port port; | |
cefc4e18 | 825 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
042ab0c3 R |
826 | u16 hfp_sw, hsync_sw, hbp_sw; |
827 | u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw, | |
828 | crtc_hblank_start_sw, crtc_hblank_end_sw; | |
829 | ||
5eff0edf | 830 | /* FIXME: hw readout should not depend on SW state */ |
042ab0c3 R |
831 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
832 | adjusted_mode_sw = &intel_crtc->config->base.adjusted_mode; | |
6f0e7535 R |
833 | |
834 | /* | |
835 | * Atleast one port is active as encoder->get_config called only if | |
836 | * encoder->get_hw_state() returns true. | |
837 | */ | |
838 | for_each_dsi_port(port, intel_dsi->ports) { | |
839 | if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) | |
840 | break; | |
841 | } | |
842 | ||
843 | fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; | |
844 | pipe_config->pipe_bpp = | |
845 | mipi_dsi_pixel_format_to_bpp( | |
846 | pixel_format_from_register_bits(fmt)); | |
847 | bpp = pipe_config->pipe_bpp; | |
848 | ||
849 | /* In terms of pixels */ | |
850 | adjusted_mode->crtc_hdisplay = | |
851 | I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); | |
852 | adjusted_mode->crtc_vdisplay = | |
853 | I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); | |
854 | adjusted_mode->crtc_vtotal = | |
855 | I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); | |
856 | ||
cefc4e18 R |
857 | hactive = adjusted_mode->crtc_hdisplay; |
858 | hfp = I915_READ(MIPI_HFP_COUNT(port)); | |
859 | ||
6f0e7535 | 860 | /* |
cefc4e18 R |
861 | * Meaningful for video mode non-burst sync pulse mode only, |
862 | * can be zero for non-burst sync events and burst modes | |
6f0e7535 | 863 | */ |
cefc4e18 R |
864 | hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); |
865 | hbp = I915_READ(MIPI_HBP_COUNT(port)); | |
866 | ||
867 | /* harizontal values are in terms of high speed byte clock */ | |
868 | hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, | |
869 | intel_dsi->burst_mode_ratio); | |
870 | hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, | |
871 | intel_dsi->burst_mode_ratio); | |
872 | hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, | |
873 | intel_dsi->burst_mode_ratio); | |
874 | ||
875 | if (intel_dsi->dual_link) { | |
876 | hfp *= 2; | |
877 | hsync *= 2; | |
878 | hbp *= 2; | |
879 | } | |
6f0e7535 R |
880 | |
881 | /* vertical values are in terms of lines */ | |
882 | vfp = I915_READ(MIPI_VFP_COUNT(port)); | |
883 | vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); | |
884 | vbp = I915_READ(MIPI_VBP_COUNT(port)); | |
885 | ||
cefc4e18 R |
886 | adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; |
887 | adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; | |
888 | adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; | |
6f0e7535 | 889 | adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; |
cefc4e18 | 890 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; |
6f0e7535 | 891 | |
cefc4e18 R |
892 | adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; |
893 | adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; | |
6f0e7535 R |
894 | adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; |
895 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; | |
6f0e7535 | 896 | |
042ab0c3 R |
897 | /* |
898 | * In BXT DSI there is no regs programmed with few horizontal timings | |
899 | * in Pixels but txbyteclkhs.. So retrieval process adds some | |
900 | * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs. | |
901 | * Actually here for the given adjusted_mode, we are calculating the | |
902 | * value programmed to the port and then back to the horizontal timing | |
903 | * param in pixels. This is the expected value, including roundup errors | |
904 | * And if that is same as retrieved value from port, then | |
905 | * (HW state) adjusted_mode's horizontal timings are corrected to | |
906 | * match with SW state to nullify the errors. | |
907 | */ | |
908 | /* Calculating the value programmed to the Port register */ | |
909 | hfp_sw = adjusted_mode_sw->crtc_hsync_start - | |
910 | adjusted_mode_sw->crtc_hdisplay; | |
911 | hsync_sw = adjusted_mode_sw->crtc_hsync_end - | |
912 | adjusted_mode_sw->crtc_hsync_start; | |
913 | hbp_sw = adjusted_mode_sw->crtc_htotal - | |
914 | adjusted_mode_sw->crtc_hsync_end; | |
915 | ||
916 | if (intel_dsi->dual_link) { | |
917 | hfp_sw /= 2; | |
918 | hsync_sw /= 2; | |
919 | hbp_sw /= 2; | |
920 | } | |
921 | ||
922 | hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, | |
923 | intel_dsi->burst_mode_ratio); | |
924 | hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, | |
925 | intel_dsi->burst_mode_ratio); | |
926 | hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, | |
927 | intel_dsi->burst_mode_ratio); | |
928 | ||
929 | /* Reverse calculating the adjusted mode parameters from port reg vals*/ | |
930 | hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, | |
931 | intel_dsi->burst_mode_ratio); | |
932 | hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, | |
933 | intel_dsi->burst_mode_ratio); | |
934 | hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, | |
935 | intel_dsi->burst_mode_ratio); | |
936 | ||
937 | if (intel_dsi->dual_link) { | |
938 | hfp_sw *= 2; | |
939 | hsync_sw *= 2; | |
940 | hbp_sw *= 2; | |
941 | } | |
942 | ||
943 | crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + | |
944 | hsync_sw + hbp_sw; | |
945 | crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; | |
946 | crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw; | |
947 | crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; | |
948 | crtc_hblank_end_sw = crtc_htotal_sw; | |
949 | ||
950 | if (adjusted_mode->crtc_htotal == crtc_htotal_sw) | |
951 | adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; | |
952 | ||
953 | if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) | |
954 | adjusted_mode->crtc_hsync_start = | |
955 | adjusted_mode_sw->crtc_hsync_start; | |
956 | ||
957 | if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) | |
958 | adjusted_mode->crtc_hsync_end = | |
959 | adjusted_mode_sw->crtc_hsync_end; | |
960 | ||
961 | if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) | |
962 | adjusted_mode->crtc_hblank_start = | |
963 | adjusted_mode_sw->crtc_hblank_start; | |
964 | ||
965 | if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) | |
966 | adjusted_mode->crtc_hblank_end = | |
967 | adjusted_mode_sw->crtc_hblank_end; | |
968 | } | |
6f0e7535 | 969 | |
4e646495 | 970 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
5cec258b | 971 | struct intel_crtc_state *pipe_config) |
4e646495 | 972 | { |
6f0e7535 | 973 | struct drm_device *dev = encoder->base.dev; |
d7d85d85 | 974 | u32 pclk; |
4e646495 JN |
975 | DRM_DEBUG_KMS("\n"); |
976 | ||
6f0e7535 R |
977 | if (IS_BROXTON(dev)) |
978 | bxt_dsi_get_pipe_config(encoder, pipe_config); | |
979 | ||
47eacbab VS |
980 | pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp, |
981 | pipe_config); | |
f573de5a SK |
982 | if (!pclk) |
983 | return; | |
984 | ||
2d112de7 | 985 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
f573de5a | 986 | pipe_config->port_clock = pclk; |
4e646495 JN |
987 | } |
988 | ||
c19de8eb DL |
989 | static enum drm_mode_status |
990 | intel_dsi_mode_valid(struct drm_connector *connector, | |
991 | struct drm_display_mode *mode) | |
4e646495 JN |
992 | { |
993 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
f4ee265f | 994 | const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
759a1e98 | 995 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4e646495 JN |
996 | |
997 | DRM_DEBUG_KMS("\n"); | |
998 | ||
999 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
1000 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
1001 | return MODE_NO_DBLESCAN; | |
1002 | } | |
1003 | ||
1004 | if (fixed_mode) { | |
1005 | if (mode->hdisplay > fixed_mode->hdisplay) | |
1006 | return MODE_PANEL; | |
1007 | if (mode->vdisplay > fixed_mode->vdisplay) | |
1008 | return MODE_PANEL; | |
759a1e98 MK |
1009 | if (fixed_mode->clock > max_dotclk) |
1010 | return MODE_CLOCK_HIGH; | |
4e646495 JN |
1011 | } |
1012 | ||
36d21f4c | 1013 | return MODE_OK; |
4e646495 JN |
1014 | } |
1015 | ||
1016 | /* return txclkesc cycles in terms of divider and duration in us */ | |
1017 | static u16 txclkesc(u32 divider, unsigned int us) | |
1018 | { | |
1019 | switch (divider) { | |
1020 | case ESCAPE_CLOCK_DIVIDER_1: | |
1021 | default: | |
1022 | return 20 * us; | |
1023 | case ESCAPE_CLOCK_DIVIDER_2: | |
1024 | return 10 * us; | |
1025 | case ESCAPE_CLOCK_DIVIDER_4: | |
1026 | return 5 * us; | |
1027 | } | |
1028 | } | |
1029 | ||
4e646495 | 1030 | static void set_dsi_timings(struct drm_encoder *encoder, |
5e7234c9 | 1031 | const struct drm_display_mode *adjusted_mode) |
4e646495 JN |
1032 | { |
1033 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1034 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e646495 | 1035 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
aa102d28 | 1036 | enum port port; |
1e78aa01 | 1037 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 JN |
1038 | unsigned int lane_count = intel_dsi->lane_count; |
1039 | ||
1040 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
1041 | ||
aad941d5 VS |
1042 | hactive = adjusted_mode->crtc_hdisplay; |
1043 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; | |
1044 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; | |
1045 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; | |
4e646495 | 1046 | |
aa102d28 GS |
1047 | if (intel_dsi->dual_link) { |
1048 | hactive /= 2; | |
1049 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1050 | hactive += intel_dsi->pixel_overlap; | |
1051 | hfp /= 2; | |
1052 | hsync /= 2; | |
1053 | hbp /= 2; | |
1054 | } | |
1055 | ||
aad941d5 VS |
1056 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
1057 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; | |
1058 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; | |
4e646495 JN |
1059 | |
1060 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 1061 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 1062 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
1063 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
1064 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 1065 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 1066 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 1067 | |
aa102d28 | 1068 | for_each_dsi_port(port, intel_dsi->ports) { |
d2e08c0f SS |
1069 | if (IS_BROXTON(dev)) { |
1070 | /* | |
1071 | * Program hdisplay and vdisplay on MIPI transcoder. | |
1072 | * This is different from calculated hactive and | |
1073 | * vactive, as they are calculated per channel basis, | |
1074 | * whereas these values should be based on resolution. | |
1075 | */ | |
1076 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), | |
aad941d5 | 1077 | adjusted_mode->crtc_hdisplay); |
d2e08c0f | 1078 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
aad941d5 | 1079 | adjusted_mode->crtc_vdisplay); |
d2e08c0f | 1080 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
aad941d5 | 1081 | adjusted_mode->crtc_vtotal); |
d2e08c0f SS |
1082 | } |
1083 | ||
aa102d28 GS |
1084 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
1085 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
1086 | ||
1087 | /* meaningful for video mode non-burst sync pulse mode only, | |
1088 | * can be zero for non-burst sync events and burst modes */ | |
1089 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
1090 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
1091 | ||
1092 | /* vertical values are in terms of lines */ | |
1093 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
1094 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
1095 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
1096 | } | |
4e646495 JN |
1097 | } |
1098 | ||
1e78aa01 JN |
1099 | static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt) |
1100 | { | |
1101 | switch (fmt) { | |
1102 | case MIPI_DSI_FMT_RGB888: | |
1103 | return VID_MODE_FORMAT_RGB888; | |
1104 | case MIPI_DSI_FMT_RGB666: | |
1105 | return VID_MODE_FORMAT_RGB666; | |
1106 | case MIPI_DSI_FMT_RGB666_PACKED: | |
1107 | return VID_MODE_FORMAT_RGB666_PACKED; | |
1108 | case MIPI_DSI_FMT_RGB565: | |
1109 | return VID_MODE_FORMAT_RGB565; | |
1110 | default: | |
1111 | MISSING_CASE(fmt); | |
1112 | return VID_MODE_FORMAT_RGB666; | |
1113 | } | |
1114 | } | |
1115 | ||
5eff0edf ML |
1116 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder, |
1117 | struct intel_crtc_state *pipe_config) | |
4e646495 JN |
1118 | { |
1119 | struct drm_encoder *encoder = &intel_encoder->base; | |
1120 | struct drm_device *dev = encoder->dev; | |
fac5e23e | 1121 | struct drm_i915_private *dev_priv = to_i915(dev); |
5eff0edf | 1122 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e646495 | 1123 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
5eff0edf | 1124 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
24ee0e64 | 1125 | enum port port; |
1e78aa01 | 1126 | unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); |
4e646495 | 1127 | u32 val, tmp; |
24ee0e64 | 1128 | u16 mode_hdisplay; |
4e646495 | 1129 | |
e7d7cad0 | 1130 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 1131 | |
aad941d5 | 1132 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4e646495 | 1133 | |
24ee0e64 GS |
1134 | if (intel_dsi->dual_link) { |
1135 | mode_hdisplay /= 2; | |
1136 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
1137 | mode_hdisplay += intel_dsi->pixel_overlap; | |
1138 | } | |
4e646495 | 1139 | |
24ee0e64 | 1140 | for_each_dsi_port(port, intel_dsi->ports) { |
666a4537 | 1141 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
d2e08c0f SS |
1142 | /* |
1143 | * escape clock divider, 20MHz, shared for A and C. | |
1144 | * device ready must be off when doing this! txclkesc? | |
1145 | */ | |
1146 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
1147 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
1148 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | | |
1149 | ESCAPE_CLOCK_DIVIDER_1); | |
1150 | ||
1151 | /* read request priority is per pipe */ | |
1152 | tmp = I915_READ(MIPI_CTRL(port)); | |
1153 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
1154 | I915_WRITE(MIPI_CTRL(port), tmp | | |
1155 | READ_REQUEST_PRIORITY_HIGH); | |
1156 | } else if (IS_BROXTON(dev)) { | |
56c48978 D |
1157 | enum pipe pipe = intel_crtc->pipe; |
1158 | ||
d2e08c0f SS |
1159 | tmp = I915_READ(MIPI_CTRL(port)); |
1160 | tmp &= ~BXT_PIPE_SELECT_MASK; | |
1161 | ||
56c48978 | 1162 | tmp |= BXT_PIPE_SELECT(pipe); |
d2e08c0f SS |
1163 | I915_WRITE(MIPI_CTRL(port), tmp); |
1164 | } | |
24ee0e64 GS |
1165 | |
1166 | /* XXX: why here, why like this? handling in irq handler?! */ | |
1167 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
1168 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
1169 | ||
1170 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
1171 | ||
1172 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
aad941d5 | 1173 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
24ee0e64 GS |
1174 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
1175 | } | |
4e646495 JN |
1176 | |
1177 | set_dsi_timings(encoder, adjusted_mode); | |
1178 | ||
1179 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
1180 | if (is_cmd_mode(intel_dsi)) { | |
1181 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
1182 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
1183 | } else { | |
1184 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
1e78aa01 | 1185 | val |= pixel_format_to_reg(intel_dsi->pixel_format); |
4e646495 | 1186 | } |
4e646495 | 1187 | |
24ee0e64 GS |
1188 | tmp = 0; |
1189 | if (intel_dsi->eotp_pkt == 0) | |
1190 | tmp |= EOT_DISABLE; | |
1191 | if (intel_dsi->clock_stop) | |
1192 | tmp |= CLOCKSTOP; | |
4e646495 | 1193 | |
f90e8c36 JN |
1194 | if (IS_BROXTON(dev_priv)) { |
1195 | tmp |= BXT_DPHY_DEFEATURE_EN; | |
1196 | if (!is_cmd_mode(intel_dsi)) | |
1197 | tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; | |
1198 | } | |
1199 | ||
24ee0e64 GS |
1200 | for_each_dsi_port(port, intel_dsi->ports) { |
1201 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
1202 | ||
1203 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
1204 | * EOT and stop state. */ | |
1205 | ||
1206 | /* | |
1207 | * In burst mode, value greater than one DPI line Time in byte | |
1208 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
1209 | * said value is recommended. | |
1210 | * | |
1211 | * In non-burst mode, Value greater than one DPI frame time in | |
1212 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1213 | * said value is recommended. | |
1214 | * | |
1215 | * In DBI only mode, value greater than one DBI frame time in | |
1216 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
1217 | * said value is recommended. | |
1218 | */ | |
4e646495 | 1219 | |
24ee0e64 GS |
1220 | if (is_vid_mode(intel_dsi) && |
1221 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
1222 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 | 1223 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
124abe07 VS |
1224 | intel_dsi->lane_count, |
1225 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1226 | } else { |
1227 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
aad941d5 VS |
1228 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
1229 | adjusted_mode->crtc_htotal, | |
124abe07 VS |
1230 | bpp, intel_dsi->lane_count, |
1231 | intel_dsi->burst_mode_ratio) + 1); | |
24ee0e64 GS |
1232 | } |
1233 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
1234 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
1235 | intel_dsi->turn_arnd_val); | |
1236 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
1237 | intel_dsi->rst_timer_val); | |
f1c79f16 | 1238 | |
24ee0e64 | 1239 | /* dphy stuff */ |
f1c79f16 | 1240 | |
24ee0e64 GS |
1241 | /* in terms of low power clock */ |
1242 | I915_WRITE(MIPI_INIT_COUNT(port), | |
1243 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 1244 | |
d2e08c0f SS |
1245 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
1246 | /* | |
1247 | * BXT spec says write MIPI_INIT_COUNT for | |
1248 | * both the ports, even if only one is | |
1249 | * getting used. So write the other port | |
1250 | * if not in dual link mode. | |
1251 | */ | |
1252 | I915_WRITE(MIPI_INIT_COUNT(port == | |
1253 | PORT_A ? PORT_C : PORT_A), | |
1254 | intel_dsi->init_count); | |
1255 | } | |
4e646495 | 1256 | |
24ee0e64 | 1257 | /* recovery disables */ |
87c54d0e | 1258 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
cf4dbd2e | 1259 | |
24ee0e64 GS |
1260 | /* in terms of low power clock */ |
1261 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 1262 | |
24ee0e64 GS |
1263 | /* in terms of txbyteclkhs. actual high to low switch + |
1264 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
1265 | * | |
1266 | * XXX: write MIPI_STOP_STATE_STALL? | |
1267 | */ | |
1268 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
1269 | intel_dsi->hs_to_lp_count); | |
1270 | ||
1271 | /* XXX: low power clock equivalence in terms of byte clock. | |
1272 | * the number of byte clocks occupied in one low power clock. | |
1273 | * based on txbyteclkhs and txclkesc. | |
1274 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
1275 | * ) / 105.??? | |
1276 | */ | |
1277 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
1278 | ||
1279 | /* the bw essential for transmitting 16 long packets containing | |
1280 | * 252 bytes meant for dcs write memory command is programmed in | |
1281 | * this register in terms of byte clocks. based on dsi transfer | |
1282 | * rate and the number of lanes configured the time taken to | |
1283 | * transmit 16 long packets in a dsi stream varies. */ | |
1284 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
1285 | ||
1286 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
1287 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
1288 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
1289 | ||
1290 | if (is_vid_mode(intel_dsi)) | |
1291 | /* Some panels might have resolution which is not a | |
1292 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
1293 | * resolution support for such panels by default */ | |
1294 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
1295 | intel_dsi->video_frmt_cfg_bits | | |
1296 | intel_dsi->video_mode_format | | |
1297 | IP_TG_CONFIG | | |
1298 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
1299 | } | |
4e646495 JN |
1300 | } |
1301 | ||
1302 | static enum drm_connector_status | |
1303 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
1304 | { | |
36d21f4c | 1305 | return connector_status_connected; |
4e646495 JN |
1306 | } |
1307 | ||
1308 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
1309 | { | |
1310 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1311 | struct drm_display_mode *mode; | |
1312 | ||
1313 | DRM_DEBUG_KMS("\n"); | |
1314 | ||
1315 | if (!intel_connector->panel.fixed_mode) { | |
1316 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1317 | return 0; | |
1318 | } | |
1319 | ||
1320 | mode = drm_mode_duplicate(connector->dev, | |
1321 | intel_connector->panel.fixed_mode); | |
1322 | if (!mode) { | |
1323 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | drm_mode_probed_add(connector, mode); | |
1328 | return 1; | |
1329 | } | |
1330 | ||
f4ee265f VS |
1331 | static int intel_dsi_set_property(struct drm_connector *connector, |
1332 | struct drm_property *property, | |
1333 | uint64_t val) | |
1334 | { | |
1335 | struct drm_device *dev = connector->dev; | |
1336 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1337 | struct drm_crtc *crtc; | |
1338 | int ret; | |
1339 | ||
1340 | ret = drm_object_property_set_value(&connector->base, property, val); | |
1341 | if (ret) | |
1342 | return ret; | |
1343 | ||
1344 | if (property == dev->mode_config.scaling_mode_property) { | |
1345 | if (val == DRM_MODE_SCALE_NONE) { | |
1346 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
1347 | return -EINVAL; | |
1348 | } | |
234126c6 VS |
1349 | if (HAS_GMCH_DISPLAY(dev) && |
1350 | val == DRM_MODE_SCALE_CENTER) { | |
1351 | DRM_DEBUG_KMS("centering not supported\n"); | |
1352 | return -EINVAL; | |
1353 | } | |
f4ee265f VS |
1354 | |
1355 | if (intel_connector->panel.fitting_mode == val) | |
1356 | return 0; | |
1357 | ||
1358 | intel_connector->panel.fitting_mode = val; | |
1359 | } | |
1360 | ||
5eff0edf | 1361 | crtc = connector->state->crtc; |
f4ee265f VS |
1362 | if (crtc && crtc->state->enable) { |
1363 | /* | |
1364 | * If the CRTC is enabled, the display will be changed | |
1365 | * according to the new panel fitting mode. | |
1366 | */ | |
1367 | intel_crtc_restore_mode(crtc); | |
1368 | } | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
593e0622 | 1373 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4e646495 JN |
1374 | { |
1375 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
1376 | ||
1377 | DRM_DEBUG_KMS("\n"); | |
1378 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
1379 | drm_connector_cleanup(connector); |
1380 | kfree(connector); | |
1381 | } | |
1382 | ||
593e0622 JN |
1383 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1384 | { | |
1385 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
1386 | ||
1387 | if (intel_dsi->panel) { | |
1388 | drm_panel_detach(intel_dsi->panel); | |
1389 | /* XXX: Logically this call belongs in the panel driver. */ | |
1390 | drm_panel_remove(intel_dsi->panel); | |
1391 | } | |
fc45e821 SK |
1392 | |
1393 | /* dispose of the gpios */ | |
1394 | if (intel_dsi->gpio_panel) | |
1395 | gpiod_put(intel_dsi->gpio_panel); | |
1396 | ||
593e0622 JN |
1397 | intel_encoder_destroy(encoder); |
1398 | } | |
1399 | ||
4e646495 | 1400 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
593e0622 | 1401 | .destroy = intel_dsi_encoder_destroy, |
4e646495 JN |
1402 | }; |
1403 | ||
1404 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
1405 | .get_modes = intel_dsi_get_modes, | |
1406 | .mode_valid = intel_dsi_mode_valid, | |
4e646495 JN |
1407 | }; |
1408 | ||
1409 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
4d688a2a | 1410 | .dpms = drm_atomic_helper_connector_dpms, |
4e646495 | 1411 | .detect = intel_dsi_detect, |
1ebaa0b9 | 1412 | .late_register = intel_connector_register, |
c191eca1 | 1413 | .early_unregister = intel_connector_unregister, |
593e0622 | 1414 | .destroy = intel_dsi_connector_destroy, |
4e646495 | 1415 | .fill_modes = drm_helper_probe_single_connector_modes, |
f4ee265f | 1416 | .set_property = intel_dsi_set_property, |
2545e4a6 | 1417 | .atomic_get_property = intel_connector_atomic_get_property, |
c6f95f27 | 1418 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 1419 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
4e646495 JN |
1420 | }; |
1421 | ||
f4ee265f VS |
1422 | static void intel_dsi_add_properties(struct intel_connector *connector) |
1423 | { | |
1424 | struct drm_device *dev = connector->base.dev; | |
1425 | ||
1426 | if (connector->panel.fixed_mode) { | |
1427 | drm_mode_create_scaling_mode_property(dev); | |
1428 | drm_object_attach_property(&connector->base.base, | |
1429 | dev->mode_config.scaling_mode_property, | |
1430 | DRM_MODE_SCALE_ASPECT); | |
1431 | connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
1432 | } | |
1433 | } | |
1434 | ||
4328633d | 1435 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
1436 | { |
1437 | struct intel_dsi *intel_dsi; | |
1438 | struct intel_encoder *intel_encoder; | |
1439 | struct drm_encoder *encoder; | |
1440 | struct intel_connector *intel_connector; | |
1441 | struct drm_connector *connector; | |
593e0622 | 1442 | struct drm_display_mode *scan, *fixed_mode = NULL; |
fac5e23e | 1443 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e9804fd | 1444 | enum port port; |
4e646495 JN |
1445 | unsigned int i; |
1446 | ||
1447 | DRM_DEBUG_KMS("\n"); | |
1448 | ||
3e6bd011 | 1449 | /* There is no detection method for MIPI so rely on VBT */ |
7137aec1 | 1450 | if (!intel_bios_is_dsi_present(dev_priv, &port)) |
4328633d | 1451 | return; |
3e6bd011 | 1452 | |
666a4537 | 1453 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
868d665b | 1454 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
c6c794a2 SS |
1455 | } else if (IS_BROXTON(dev)) { |
1456 | dev_priv->mipi_mmio_base = BXT_MIPI_BASE; | |
868d665b CJ |
1457 | } else { |
1458 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
1459 | return; | |
1460 | } | |
3e6bd011 | 1461 | |
4e646495 JN |
1462 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1463 | if (!intel_dsi) | |
4328633d | 1464 | return; |
4e646495 | 1465 | |
08d9bc92 | 1466 | intel_connector = intel_connector_alloc(); |
4e646495 JN |
1467 | if (!intel_connector) { |
1468 | kfree(intel_dsi); | |
4328633d | 1469 | return; |
4e646495 JN |
1470 | } |
1471 | ||
1472 | intel_encoder = &intel_dsi->base; | |
1473 | encoder = &intel_encoder->base; | |
1474 | intel_dsi->attached_connector = intel_connector; | |
1475 | ||
1476 | connector = &intel_connector->base; | |
1477 | ||
13a3d91f | 1478 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
580d8ed5 | 1479 | "DSI %c", port_name(port)); |
4e646495 | 1480 | |
4e646495 | 1481 | intel_encoder->compute_config = intel_dsi_compute_config; |
4e646495 | 1482 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
2634fd7f | 1483 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 1484 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
1485 | intel_encoder->post_disable = intel_dsi_post_disable; |
1486 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
1487 | intel_encoder->get_config = intel_dsi_get_config; | |
1488 | ||
1489 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
1490 | ||
2e85ab4f JN |
1491 | /* |
1492 | * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI | |
1493 | * port C. BXT isn't limited like this. | |
1494 | */ | |
1495 | if (IS_BROXTON(dev_priv)) | |
1496 | intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); | |
1497 | else if (port == PORT_A) | |
701d25b4 | 1498 | intel_encoder->crtc_mask = BIT(PIPE_A); |
7137aec1 | 1499 | else |
701d25b4 | 1500 | intel_encoder->crtc_mask = BIT(PIPE_B); |
e7d7cad0 | 1501 | |
90198355 | 1502 | if (dev_priv->vbt.dsi.config->dual_link) { |
701d25b4 | 1503 | intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); |
90198355 JN |
1504 | |
1505 | switch (dev_priv->vbt.dsi.config->dl_dcs_backlight_ports) { | |
1506 | case DL_DCS_PORT_A: | |
1507 | intel_dsi->dcs_backlight_ports = BIT(PORT_A); | |
1508 | break; | |
1509 | case DL_DCS_PORT_C: | |
1510 | intel_dsi->dcs_backlight_ports = BIT(PORT_C); | |
1511 | break; | |
1512 | default: | |
1513 | case DL_DCS_PORT_A_AND_C: | |
1514 | intel_dsi->dcs_backlight_ports = BIT(PORT_A) | BIT(PORT_C); | |
1515 | break; | |
1516 | } | |
1ecc1c6c D |
1517 | |
1518 | switch (dev_priv->vbt.dsi.config->dl_dcs_cabc_ports) { | |
1519 | case DL_DCS_PORT_A: | |
1520 | intel_dsi->dcs_cabc_ports = BIT(PORT_A); | |
1521 | break; | |
1522 | case DL_DCS_PORT_C: | |
1523 | intel_dsi->dcs_cabc_ports = BIT(PORT_C); | |
1524 | break; | |
1525 | default: | |
1526 | case DL_DCS_PORT_A_AND_C: | |
1527 | intel_dsi->dcs_cabc_ports = BIT(PORT_A) | BIT(PORT_C); | |
1528 | break; | |
1529 | } | |
90198355 | 1530 | } else { |
701d25b4 | 1531 | intel_dsi->ports = BIT(port); |
90198355 | 1532 | intel_dsi->dcs_backlight_ports = BIT(port); |
1ecc1c6c | 1533 | intel_dsi->dcs_cabc_ports = BIT(port); |
90198355 | 1534 | } |
82425785 | 1535 | |
1ecc1c6c D |
1536 | if (!dev_priv->vbt.dsi.config->cabc_supported) |
1537 | intel_dsi->dcs_cabc_ports = 0; | |
1538 | ||
7e9804fd JN |
1539 | /* Create a DSI host (and a device) for each port. */ |
1540 | for_each_dsi_port(port, intel_dsi->ports) { | |
1541 | struct intel_dsi_host *host; | |
1542 | ||
1543 | host = intel_dsi_host_init(intel_dsi, port); | |
1544 | if (!host) | |
1545 | goto err; | |
1546 | ||
1547 | intel_dsi->dsi_hosts[port] = host; | |
1548 | } | |
1549 | ||
593e0622 JN |
1550 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
1551 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, | |
1552 | intel_dsi_drivers[i].panel_id); | |
1553 | if (intel_dsi->panel) | |
4e646495 JN |
1554 | break; |
1555 | } | |
1556 | ||
593e0622 | 1557 | if (!intel_dsi->panel) { |
4e646495 JN |
1558 | DRM_DEBUG_KMS("no device found\n"); |
1559 | goto err; | |
1560 | } | |
1561 | ||
fc45e821 SK |
1562 | /* |
1563 | * In case of BYT with CRC PMIC, we need to use GPIO for | |
1564 | * Panel control. | |
1565 | */ | |
1566 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { | |
1567 | intel_dsi->gpio_panel = | |
1568 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); | |
1569 | ||
1570 | if (IS_ERR(intel_dsi->gpio_panel)) { | |
1571 | DRM_ERROR("Failed to own gpio for panel control\n"); | |
1572 | intel_dsi->gpio_panel = NULL; | |
1573 | } | |
1574 | } | |
1575 | ||
4e646495 | 1576 | intel_encoder->type = INTEL_OUTPUT_DSI; |
bc079e8b | 1577 | intel_encoder->cloneable = 0; |
4e646495 JN |
1578 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1579 | DRM_MODE_CONNECTOR_DSI); | |
1580 | ||
1581 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
1582 | ||
1583 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
1584 | connector->interlace_allowed = false; | |
1585 | connector->doublescan_allowed = false; | |
1586 | ||
1587 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1588 | ||
593e0622 JN |
1589 | drm_panel_attach(intel_dsi->panel, connector); |
1590 | ||
1591 | mutex_lock(&dev->mode_config.mutex); | |
1592 | drm_panel_get_modes(intel_dsi->panel); | |
1593 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
1594 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
1595 | fixed_mode = drm_mode_duplicate(dev, scan); | |
1596 | break; | |
1597 | } | |
1598 | } | |
1599 | mutex_unlock(&dev->mode_config.mutex); | |
1600 | ||
4e646495 JN |
1601 | if (!fixed_mode) { |
1602 | DRM_DEBUG_KMS("no fixed mode\n"); | |
1603 | goto err; | |
1604 | } | |
1605 | ||
df457245 VS |
1606 | connector->display_info.width_mm = fixed_mode->width_mm; |
1607 | connector->display_info.height_mm = fixed_mode->height_mm; | |
1608 | ||
4b6ed685 | 1609 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
fda9ee98 | 1610 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
f4ee265f VS |
1611 | |
1612 | intel_dsi_add_properties(intel_connector); | |
1613 | ||
4328633d | 1614 | return; |
4e646495 JN |
1615 | |
1616 | err: | |
1617 | drm_encoder_cleanup(&intel_encoder->base); | |
1618 | kfree(intel_dsi); | |
1619 | kfree(intel_connector); | |
4e646495 | 1620 | } |