Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
ea5b213a CW |
40 | struct intel_hdmi { |
41 | struct intel_encoder base; | |
7d57382e | 42 | u32 sdvox_reg; |
f899fc64 | 43 | int ddc_bus; |
e953fd7b | 44 | uint32_t color_range; |
9dff6af8 | 45 | bool has_hdmi_sink; |
2e3d6006 | 46 | bool has_audio; |
b1d7e4b4 | 47 | enum hdmi_force_audio force_audio; |
45187ace JB |
48 | void (*write_infoframe)(struct drm_encoder *encoder, |
49 | struct dip_infoframe *frame); | |
7d57382e EA |
50 | }; |
51 | ||
ea5b213a CW |
52 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
53 | { | |
4ef69c7a | 54 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
55 | } |
56 | ||
df0e9248 CW |
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
58 | { | |
59 | return container_of(intel_attached_encoder(connector), | |
60 | struct intel_hdmi, base); | |
61 | } | |
62 | ||
45187ace | 63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 64 | { |
45187ace | 65 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
66 | uint8_t sum = 0; |
67 | unsigned i; | |
68 | ||
45187ace JB |
69 | frame->checksum = 0; |
70 | frame->ecc = 0; | |
3c17fe4b | 71 | |
64a8fc01 | 72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
73 | sum += data[i]; |
74 | ||
45187ace | 75 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
76 | } |
77 | ||
45187ace | 78 | static u32 intel_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 79 | { |
45187ace JB |
80 | u32 flags = 0; |
81 | ||
82 | switch (frame->type) { | |
83 | case DIP_TYPE_AVI: | |
84 | flags |= VIDEO_DIP_SELECT_AVI; | |
85 | break; | |
86 | case DIP_TYPE_SPD: | |
87 | flags |= VIDEO_DIP_SELECT_SPD; | |
88 | break; | |
89 | default: | |
90 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
91 | break; | |
92 | } | |
93 | ||
94 | return flags; | |
95 | } | |
96 | ||
fa193ff7 | 97 | static u32 intel_infoframe_enable(struct dip_infoframe *frame) |
45187ace JB |
98 | { |
99 | u32 flags = 0; | |
100 | ||
101 | switch (frame->type) { | |
102 | case DIP_TYPE_AVI: | |
fa193ff7 | 103 | flags |= VIDEO_DIP_ENABLE_AVI; |
45187ace JB |
104 | break; |
105 | case DIP_TYPE_SPD: | |
fa193ff7 PZ |
106 | flags |= VIDEO_DIP_ENABLE_SPD; |
107 | break; | |
108 | default: | |
109 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
110 | break; | |
111 | } | |
112 | ||
113 | return flags; | |
114 | } | |
115 | ||
116 | static u32 intel_infoframe_frequency(struct dip_infoframe *frame) | |
117 | { | |
118 | u32 flags = 0; | |
119 | ||
120 | switch (frame->type) { | |
121 | case DIP_TYPE_AVI: | |
122 | case DIP_TYPE_SPD: | |
123 | flags |= VIDEO_DIP_FREQ_VSYNC; | |
45187ace JB |
124 | break; |
125 | default: | |
126 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
127 | break; | |
128 | } | |
129 | ||
130 | return flags; | |
131 | } | |
132 | ||
133 | static void i9xx_write_infoframe(struct drm_encoder *encoder, | |
134 | struct dip_infoframe *frame) | |
135 | { | |
136 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
139 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
22509ec8 | 140 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 141 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 142 | |
3c17fe4b DH |
143 | |
144 | /* XXX first guess at handling video port, is this corrent? */ | |
3e6e6395 | 145 | val &= ~VIDEO_DIP_PORT_MASK; |
3c17fe4b | 146 | if (intel_hdmi->sdvox_reg == SDVOB) |
22509ec8 | 147 | val |= VIDEO_DIP_PORT_B; |
3c17fe4b | 148 | else if (intel_hdmi->sdvox_reg == SDVOC) |
22509ec8 | 149 | val |= VIDEO_DIP_PORT_C; |
3c17fe4b DH |
150 | else |
151 | return; | |
152 | ||
1d4f85ac | 153 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 PZ |
154 | val |= intel_infoframe_index(frame); |
155 | ||
ecb97851 | 156 | val &= ~intel_infoframe_enable(frame); |
22509ec8 | 157 | val |= VIDEO_DIP_ENABLE; |
45187ace | 158 | |
22509ec8 | 159 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 160 | |
45187ace | 161 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
162 | I915_WRITE(VIDEO_DIP_DATA, *data); |
163 | data++; | |
164 | } | |
165 | ||
fa193ff7 | 166 | val |= intel_infoframe_enable(frame); |
60c5ea2d | 167 | val &= ~VIDEO_DIP_FREQ_MASK; |
fa193ff7 | 168 | val |= intel_infoframe_frequency(frame); |
45187ace | 169 | |
22509ec8 | 170 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
171 | } |
172 | ||
fdf1250a PZ |
173 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
174 | struct dip_infoframe *frame) | |
175 | { | |
176 | uint32_t *data = (uint32_t *)frame; | |
177 | struct drm_device *dev = encoder->dev; | |
178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
179 | struct drm_crtc *crtc = encoder->crtc; | |
180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4e89ee17 | 181 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
fdf1250a PZ |
182 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
183 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
184 | u32 val = I915_READ(reg); | |
185 | ||
4e89ee17 PZ |
186 | val &= ~VIDEO_DIP_PORT_MASK; |
187 | switch (intel_hdmi->sdvox_reg) { | |
188 | case HDMIB: | |
189 | val |= VIDEO_DIP_PORT_B; | |
190 | break; | |
191 | case HDMIC: | |
192 | val |= VIDEO_DIP_PORT_C; | |
193 | break; | |
194 | case HDMID: | |
195 | val |= VIDEO_DIP_PORT_D; | |
196 | break; | |
197 | default: | |
198 | return; | |
199 | } | |
200 | ||
fdf1250a PZ |
201 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
202 | ||
203 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
204 | val |= intel_infoframe_index(frame); | |
205 | ||
4dc20c0d | 206 | val &= ~intel_infoframe_enable(frame); |
fdf1250a PZ |
207 | val |= VIDEO_DIP_ENABLE; |
208 | ||
209 | I915_WRITE(reg, val); | |
210 | ||
211 | for (i = 0; i < len; i += 4) { | |
212 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
213 | data++; | |
214 | } | |
215 | ||
216 | val |= intel_infoframe_enable(frame); | |
217 | val &= ~VIDEO_DIP_FREQ_MASK; | |
218 | val |= intel_infoframe_frequency(frame); | |
219 | ||
220 | I915_WRITE(reg, val); | |
221 | } | |
222 | ||
223 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
224 | struct dip_infoframe *frame) | |
b055c8f3 | 225 | { |
45187ace | 226 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
227 | struct drm_device *dev = encoder->dev; |
228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b055c8f3 JB |
229 | struct drm_crtc *crtc = encoder->crtc; |
230 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
231 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
45187ace | 232 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 233 | u32 val = I915_READ(reg); |
b055c8f3 JB |
234 | |
235 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
236 | ||
64a8fc01 | 237 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 | 238 | val |= intel_infoframe_index(frame); |
45187ace | 239 | |
ecb97851 PZ |
240 | /* The DIP control register spec says that we need to update the AVI |
241 | * infoframe without clearing its enable bit */ | |
242 | if (frame->type == DIP_TYPE_AVI) | |
243 | val |= VIDEO_DIP_ENABLE_AVI; | |
244 | else | |
245 | val &= ~intel_infoframe_enable(frame); | |
246 | ||
22509ec8 PZ |
247 | val |= VIDEO_DIP_ENABLE; |
248 | ||
249 | I915_WRITE(reg, val); | |
45187ace JB |
250 | |
251 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
252 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
253 | data++; | |
254 | } | |
255 | ||
fa193ff7 | 256 | val |= intel_infoframe_enable(frame); |
60c5ea2d | 257 | val &= ~VIDEO_DIP_FREQ_MASK; |
fa193ff7 | 258 | val |= intel_infoframe_frequency(frame); |
45187ace | 259 | |
22509ec8 | 260 | I915_WRITE(reg, val); |
45187ace | 261 | } |
90b107c8 SK |
262 | |
263 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
264 | struct dip_infoframe *frame) | |
265 | { | |
266 | uint32_t *data = (uint32_t *)frame; | |
267 | struct drm_device *dev = encoder->dev; | |
268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
269 | struct drm_crtc *crtc = encoder->crtc; | |
270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
271 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
272 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 273 | u32 val = I915_READ(reg); |
90b107c8 SK |
274 | |
275 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
276 | ||
90b107c8 | 277 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 PZ |
278 | val |= intel_infoframe_index(frame); |
279 | ||
ecb97851 | 280 | val &= ~intel_infoframe_enable(frame); |
22509ec8 | 281 | val |= VIDEO_DIP_ENABLE; |
90b107c8 | 282 | |
22509ec8 | 283 | I915_WRITE(reg, val); |
90b107c8 SK |
284 | |
285 | for (i = 0; i < len; i += 4) { | |
286 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
287 | data++; | |
288 | } | |
289 | ||
fa193ff7 | 290 | val |= intel_infoframe_enable(frame); |
60c5ea2d | 291 | val &= ~VIDEO_DIP_FREQ_MASK; |
fa193ff7 | 292 | val |= intel_infoframe_frequency(frame); |
90b107c8 | 293 | |
22509ec8 | 294 | I915_WRITE(reg, val); |
90b107c8 SK |
295 | } |
296 | ||
45187ace JB |
297 | static void intel_set_infoframe(struct drm_encoder *encoder, |
298 | struct dip_infoframe *frame) | |
299 | { | |
300 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
301 | ||
302 | if (!intel_hdmi->has_hdmi_sink) | |
303 | return; | |
304 | ||
305 | intel_dip_infoframe_csum(frame); | |
306 | intel_hdmi->write_infoframe(encoder, frame); | |
307 | } | |
308 | ||
c846b619 PZ |
309 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
310 | struct drm_display_mode *adjusted_mode) | |
45187ace JB |
311 | { |
312 | struct dip_infoframe avi_if = { | |
313 | .type = DIP_TYPE_AVI, | |
314 | .ver = DIP_VERSION_AVI, | |
315 | .len = DIP_LEN_AVI, | |
316 | }; | |
317 | ||
c846b619 PZ |
318 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
319 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
320 | ||
45187ace | 321 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
322 | } |
323 | ||
c0864cb3 JB |
324 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
325 | { | |
326 | struct dip_infoframe spd_if; | |
327 | ||
328 | memset(&spd_if, 0, sizeof(spd_if)); | |
329 | spd_if.type = DIP_TYPE_SPD; | |
330 | spd_if.ver = DIP_VERSION_SPD; | |
331 | spd_if.len = DIP_LEN_SPD; | |
332 | strcpy(spd_if.body.spd.vn, "Intel"); | |
333 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
334 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
335 | ||
336 | intel_set_infoframe(encoder, &spd_if); | |
337 | } | |
338 | ||
7d57382e EA |
339 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
340 | struct drm_display_mode *mode, | |
341 | struct drm_display_mode *adjusted_mode) | |
342 | { | |
343 | struct drm_device *dev = encoder->dev; | |
344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
345 | struct drm_crtc *crtc = encoder->crtc; | |
346 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 347 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
348 | u32 sdvox; |
349 | ||
b599c0bc | 350 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
351 | if (!HAS_PCH_SPLIT(dev)) |
352 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
353 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
354 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
355 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
356 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 357 | |
020f6704 JB |
358 | if (intel_crtc->bpp > 24) |
359 | sdvox |= COLOR_FORMAT_12bpc; | |
360 | else | |
361 | sdvox |= COLOR_FORMAT_8bpc; | |
362 | ||
2e3d6006 ZW |
363 | /* Required on CPT */ |
364 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
365 | sdvox |= HDMI_MODE_SELECT; | |
366 | ||
3c17fe4b | 367 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
368 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
369 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 370 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 371 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 372 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 373 | } |
7d57382e | 374 | |
75770564 JB |
375 | if (HAS_PCH_CPT(dev)) |
376 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
377 | else if (intel_crtc->pipe == 1) | |
378 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 379 | |
ea5b213a CW |
380 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
381 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 382 | |
c846b619 | 383 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
c0864cb3 | 384 | intel_hdmi_set_spd_infoframe(encoder); |
7d57382e EA |
385 | } |
386 | ||
387 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
388 | { | |
389 | struct drm_device *dev = encoder->dev; | |
390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 391 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 392 | u32 temp; |
2deed761 WF |
393 | u32 enable_bits = SDVO_ENABLE; |
394 | ||
395 | if (intel_hdmi->has_audio) | |
396 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 397 | |
ea5b213a | 398 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
399 | |
400 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
401 | * we do this anyway which shows more stable in testing. | |
402 | */ | |
c619eed4 | 403 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
404 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
405 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
406 | } |
407 | ||
408 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 409 | temp &= ~enable_bits; |
7d57382e | 410 | } else { |
2deed761 | 411 | temp |= enable_bits; |
7d57382e | 412 | } |
d8a2d0e0 | 413 | |
ea5b213a CW |
414 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
415 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
416 | |
417 | /* HW workaround, need to write this twice for issue that may result | |
418 | * in first write getting masked. | |
419 | */ | |
c619eed4 | 420 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
421 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
422 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 423 | } |
7d57382e EA |
424 | } |
425 | ||
7d57382e EA |
426 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
427 | struct drm_display_mode *mode) | |
428 | { | |
429 | if (mode->clock > 165000) | |
430 | return MODE_CLOCK_HIGH; | |
431 | if (mode->clock < 20000) | |
5cbba41d | 432 | return MODE_CLOCK_LOW; |
7d57382e EA |
433 | |
434 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
435 | return MODE_NO_DBLESCAN; | |
436 | ||
437 | return MODE_OK; | |
438 | } | |
439 | ||
440 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
441 | struct drm_display_mode *mode, | |
442 | struct drm_display_mode *adjusted_mode) | |
443 | { | |
444 | return true; | |
445 | } | |
446 | ||
aa93d632 | 447 | static enum drm_connector_status |
930a9e28 | 448 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 449 | { |
df0e9248 | 450 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
451 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
452 | struct edid *edid; | |
aa93d632 | 453 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 454 | |
ea5b213a | 455 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 456 | intel_hdmi->has_audio = false; |
f899fc64 | 457 | edid = drm_get_edid(connector, |
3bd7d909 DK |
458 | intel_gmbus_get_adapter(dev_priv, |
459 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 460 | |
aa93d632 | 461 | if (edid) { |
be9f1c4f | 462 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 463 | status = connector_status_connected; |
b1d7e4b4 WF |
464 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
465 | intel_hdmi->has_hdmi_sink = | |
466 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 467 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 468 | } |
674e2d08 | 469 | connector->display_info.raw_edid = NULL; |
aa93d632 | 470 | kfree(edid); |
9dff6af8 | 471 | } |
30ad48b7 | 472 | |
55b7d6e8 | 473 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
474 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
475 | intel_hdmi->has_audio = | |
476 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
477 | } |
478 | ||
2ded9e27 | 479 | return status; |
7d57382e EA |
480 | } |
481 | ||
482 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
483 | { | |
df0e9248 | 484 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 485 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
486 | |
487 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
488 | * we can send audio to it. | |
489 | */ | |
490 | ||
f899fc64 | 491 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
492 | intel_gmbus_get_adapter(dev_priv, |
493 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
494 | } |
495 | ||
1aad7ac0 CW |
496 | static bool |
497 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
498 | { | |
499 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
500 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
501 | struct edid *edid; | |
502 | bool has_audio = false; | |
503 | ||
504 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
505 | intel_gmbus_get_adapter(dev_priv, |
506 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
507 | if (edid) { |
508 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
509 | has_audio = drm_detect_monitor_audio(edid); | |
510 | ||
511 | connector->display_info.raw_edid = NULL; | |
512 | kfree(edid); | |
513 | } | |
514 | ||
515 | return has_audio; | |
516 | } | |
517 | ||
55b7d6e8 CW |
518 | static int |
519 | intel_hdmi_set_property(struct drm_connector *connector, | |
520 | struct drm_property *property, | |
521 | uint64_t val) | |
522 | { | |
523 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 524 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
525 | int ret; |
526 | ||
527 | ret = drm_connector_property_set_value(connector, property, val); | |
528 | if (ret) | |
529 | return ret; | |
530 | ||
3f43c48d | 531 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 532 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
533 | bool has_audio; |
534 | ||
535 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
536 | return 0; |
537 | ||
1aad7ac0 | 538 | intel_hdmi->force_audio = i; |
55b7d6e8 | 539 | |
b1d7e4b4 | 540 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
541 | has_audio = intel_hdmi_detect_audio(connector); |
542 | else | |
b1d7e4b4 | 543 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 544 | |
b1d7e4b4 WF |
545 | if (i == HDMI_AUDIO_OFF_DVI) |
546 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 547 | |
1aad7ac0 | 548 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
549 | goto done; |
550 | } | |
551 | ||
e953fd7b CW |
552 | if (property == dev_priv->broadcast_rgb_property) { |
553 | if (val == !!intel_hdmi->color_range) | |
554 | return 0; | |
555 | ||
556 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
557 | goto done; | |
558 | } | |
559 | ||
55b7d6e8 CW |
560 | return -EINVAL; |
561 | ||
562 | done: | |
563 | if (intel_hdmi->base.base.crtc) { | |
564 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
565 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
566 | crtc->x, crtc->y, | |
567 | crtc->fb); | |
568 | } | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
7d57382e EA |
573 | static void intel_hdmi_destroy(struct drm_connector *connector) |
574 | { | |
7d57382e EA |
575 | drm_sysfs_connector_remove(connector); |
576 | drm_connector_cleanup(connector); | |
674e2d08 | 577 | kfree(connector); |
7d57382e EA |
578 | } |
579 | ||
580 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
581 | .dpms = intel_hdmi_dpms, | |
582 | .mode_fixup = intel_hdmi_mode_fixup, | |
583 | .prepare = intel_encoder_prepare, | |
584 | .mode_set = intel_hdmi_mode_set, | |
585 | .commit = intel_encoder_commit, | |
586 | }; | |
587 | ||
588 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 589 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
590 | .detect = intel_hdmi_detect, |
591 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 592 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
593 | .destroy = intel_hdmi_destroy, |
594 | }; | |
595 | ||
596 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
597 | .get_modes = intel_hdmi_get_modes, | |
598 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 599 | .best_encoder = intel_best_encoder, |
7d57382e EA |
600 | }; |
601 | ||
7d57382e | 602 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 603 | .destroy = intel_encoder_destroy, |
7d57382e EA |
604 | }; |
605 | ||
55b7d6e8 CW |
606 | static void |
607 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
608 | { | |
3f43c48d | 609 | intel_attach_force_audio_property(connector); |
e953fd7b | 610 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
611 | } |
612 | ||
7d57382e EA |
613 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
614 | { | |
615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
616 | struct drm_connector *connector; | |
21d40d37 | 617 | struct intel_encoder *intel_encoder; |
674e2d08 | 618 | struct intel_connector *intel_connector; |
ea5b213a | 619 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 620 | int i; |
7d57382e | 621 | |
ea5b213a CW |
622 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
623 | if (!intel_hdmi) | |
7d57382e | 624 | return; |
674e2d08 ZW |
625 | |
626 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
627 | if (!intel_connector) { | |
ea5b213a | 628 | kfree(intel_hdmi); |
674e2d08 ZW |
629 | return; |
630 | } | |
631 | ||
ea5b213a | 632 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
633 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
634 | DRM_MODE_ENCODER_TMDS); | |
635 | ||
674e2d08 | 636 | connector = &intel_connector->base; |
7d57382e | 637 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 638 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
639 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
640 | ||
21d40d37 | 641 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 642 | |
eb1f8e4f | 643 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 644 | connector->interlace_allowed = 1; |
7d57382e | 645 | connector->doublescan_allowed = 0; |
27f8227b | 646 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
647 | |
648 | /* Set up the DDC bus. */ | |
f8aed700 | 649 | if (sdvox_reg == SDVOB) { |
21d40d37 | 650 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 651 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 652 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 653 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 654 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 655 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 656 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 657 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 658 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 659 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 660 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 661 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 662 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 663 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 664 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 665 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 666 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 667 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 668 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 669 | } |
7d57382e | 670 | |
ea5b213a | 671 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 672 | |
64a8fc01 | 673 | if (!HAS_PCH_SPLIT(dev)) { |
45187ace | 674 | intel_hdmi->write_infoframe = i9xx_write_infoframe; |
64a8fc01 | 675 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
676 | } else if (IS_VALLEYVIEW(dev)) { |
677 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
678 | for_each_pipe(i) | |
679 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
fdf1250a PZ |
680 | } else if (HAS_PCH_IBX(dev)) { |
681 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
682 | for_each_pipe(i) | |
683 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
684 | } else { | |
685 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
64a8fc01 JB |
686 | for_each_pipe(i) |
687 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
688 | } | |
45187ace | 689 | |
4ef69c7a | 690 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
7d57382e | 691 | |
55b7d6e8 CW |
692 | intel_hdmi_add_properties(intel_hdmi, connector); |
693 | ||
df0e9248 | 694 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
695 | drm_sysfs_connector_add(connector); |
696 | ||
697 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
698 | * 0xd. Failure to do so will result in spurious interrupts being | |
699 | * generated on the port when a cable is not attached. | |
700 | */ | |
701 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
702 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
703 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
704 | } | |
7d57382e | 705 | } |