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79e53945 JB |
1 | /* |
2 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
f899fc64 | 3 | * Copyright © 2006-2008,2010 Intel Corporation |
79e53945 JB |
4 | * Jesse Barnes <jesse.barnes@intel.com> |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
f899fc64 | 27 | * Chris Wilson <chris@chris-wilson.co.uk> |
79e53945 JB |
28 | */ |
29 | #include <linux/i2c.h> | |
79e53945 | 30 | #include <linux/i2c-algo-bit.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 | 32 | #include <drm/drmP.h> |
79e53945 | 33 | #include "intel_drv.h" |
760285e7 | 34 | #include <drm/i915_drm.h> |
79e53945 JB |
35 | #include "i915_drv.h" |
36 | ||
5ea6e5e3 | 37 | struct gmbus_pin { |
2ed06c93 | 38 | const char *name; |
f0f59a00 | 39 | i915_reg_t reg; |
2ed06c93 DK |
40 | }; |
41 | ||
5ea6e5e3 JN |
42 | /* Map gmbus pin pairs to names and registers. */ |
43 | static const struct gmbus_pin gmbus_pins[] = { | |
44 | [GMBUS_PIN_SSC] = { "ssc", GPIOB }, | |
45 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, | |
46 | [GMBUS_PIN_PANEL] = { "panel", GPIOC }, | |
47 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
48 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
49 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
2ed06c93 DK |
50 | }; |
51 | ||
c1bad5b6 JN |
52 | static const struct gmbus_pin gmbus_pins_bdw[] = { |
53 | [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, | |
54 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
55 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
56 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
57 | }; | |
58 | ||
6364e67e JN |
59 | static const struct gmbus_pin gmbus_pins_skl[] = { |
60 | [GMBUS_PIN_DPC] = { "dpc", GPIOD }, | |
61 | [GMBUS_PIN_DPB] = { "dpb", GPIOE }, | |
62 | [GMBUS_PIN_DPD] = { "dpd", GPIOF }, | |
63 | }; | |
64 | ||
4c272834 | 65 | static const struct gmbus_pin gmbus_pins_bxt[] = { |
b2e8c6cd VS |
66 | [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, |
67 | [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, | |
68 | [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, | |
4c272834 JN |
69 | }; |
70 | ||
71 | /* pin is expected to be valid */ | |
72 | static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, | |
73 | unsigned int pin) | |
74 | { | |
75 | if (IS_BROXTON(dev_priv)) | |
76 | return &gmbus_pins_bxt[pin]; | |
ef11bdb3 | 77 | else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
6364e67e | 78 | return &gmbus_pins_skl[pin]; |
c1bad5b6 JN |
79 | else if (IS_BROADWELL(dev_priv)) |
80 | return &gmbus_pins_bdw[pin]; | |
4c272834 JN |
81 | else |
82 | return &gmbus_pins[pin]; | |
83 | } | |
84 | ||
88ac7939 JN |
85 | bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
86 | unsigned int pin) | |
87 | { | |
4c272834 JN |
88 | unsigned int size; |
89 | ||
90 | if (IS_BROXTON(dev_priv)) | |
91 | size = ARRAY_SIZE(gmbus_pins_bxt); | |
ef11bdb3 | 92 | else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
6364e67e | 93 | size = ARRAY_SIZE(gmbus_pins_skl); |
c1bad5b6 JN |
94 | else if (IS_BROADWELL(dev_priv)) |
95 | size = ARRAY_SIZE(gmbus_pins_bdw); | |
4c272834 JN |
96 | else |
97 | size = ARRAY_SIZE(gmbus_pins); | |
98 | ||
f0f59a00 VS |
99 | return pin < size && |
100 | i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg); | |
88ac7939 JN |
101 | } |
102 | ||
f899fc64 CW |
103 | /* Intel GPIO access functions */ |
104 | ||
1849ecb2 | 105 | #define I2C_RISEFALL_TIME 10 |
f899fc64 | 106 | |
e957d772 CW |
107 | static inline struct intel_gmbus * |
108 | to_intel_gmbus(struct i2c_adapter *i2c) | |
109 | { | |
110 | return container_of(i2c, struct intel_gmbus, adapter); | |
111 | } | |
112 | ||
f899fc64 CW |
113 | void |
114 | intel_i2c_reset(struct drm_device *dev) | |
0ba0e9e1 | 115 | { |
fac5e23e | 116 | struct drm_i915_private *dev_priv = to_i915(dev); |
24eb2d59 | 117 | |
699fc401 VS |
118 | I915_WRITE(GMBUS0, 0); |
119 | I915_WRITE(GMBUS4, 0); | |
f899fc64 CW |
120 | } |
121 | ||
122 | static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) | |
123 | { | |
b222f267 | 124 | u32 val; |
0ba0e9e1 SL |
125 | |
126 | /* When using bit bashing for I2C, this bit needs to be set to 1 */ | |
2d1fe073 | 127 | if (!IS_PINEVIEW(dev_priv)) |
0ba0e9e1 | 128 | return; |
b222f267 CW |
129 | |
130 | val = I915_READ(DSPCLK_GATE_D); | |
0ba0e9e1 | 131 | if (enable) |
b222f267 | 132 | val |= DPCUNIT_CLOCK_GATE_DISABLE; |
0ba0e9e1 | 133 | else |
b222f267 CW |
134 | val &= ~DPCUNIT_CLOCK_GATE_DISABLE; |
135 | I915_WRITE(DSPCLK_GATE_D, val); | |
0ba0e9e1 SL |
136 | } |
137 | ||
36c785f0 | 138 | static u32 get_reserved(struct intel_gmbus *bus) |
e957d772 | 139 | { |
36c785f0 | 140 | struct drm_i915_private *dev_priv = bus->dev_priv; |
91c8a326 | 141 | struct drm_device *dev = &dev_priv->drm; |
e957d772 CW |
142 | u32 reserved = 0; |
143 | ||
144 | /* On most chips, these bits must be preserved in software. */ | |
145 | if (!IS_I830(dev) && !IS_845G(dev)) | |
36c785f0 | 146 | reserved = I915_READ_NOTRACE(bus->gpio_reg) & |
db5e4172 YL |
147 | (GPIO_DATA_PULLUP_DISABLE | |
148 | GPIO_CLOCK_PULLUP_DISABLE); | |
e957d772 CW |
149 | |
150 | return reserved; | |
151 | } | |
152 | ||
79e53945 JB |
153 | static int get_clock(void *data) |
154 | { | |
36c785f0 DV |
155 | struct intel_gmbus *bus = data; |
156 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
157 | u32 reserved = get_reserved(bus); | |
158 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); | |
159 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
160 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; | |
79e53945 JB |
161 | } |
162 | ||
163 | static int get_data(void *data) | |
164 | { | |
36c785f0 DV |
165 | struct intel_gmbus *bus = data; |
166 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
167 | u32 reserved = get_reserved(bus); | |
168 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); | |
169 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved); | |
170 | return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; | |
79e53945 JB |
171 | } |
172 | ||
173 | static void set_clock(void *data, int state_high) | |
174 | { | |
36c785f0 DV |
175 | struct intel_gmbus *bus = data; |
176 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
177 | u32 reserved = get_reserved(bus); | |
e957d772 | 178 | u32 clock_bits; |
79e53945 JB |
179 | |
180 | if (state_high) | |
181 | clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; | |
182 | else | |
183 | clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | | |
184 | GPIO_CLOCK_VAL_MASK; | |
f899fc64 | 185 | |
36c785f0 DV |
186 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits); |
187 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
188 | } |
189 | ||
190 | static void set_data(void *data, int state_high) | |
191 | { | |
36c785f0 DV |
192 | struct intel_gmbus *bus = data; |
193 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
194 | u32 reserved = get_reserved(bus); | |
e957d772 | 195 | u32 data_bits; |
79e53945 JB |
196 | |
197 | if (state_high) | |
198 | data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; | |
199 | else | |
200 | data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | | |
201 | GPIO_DATA_VAL_MASK; | |
202 | ||
36c785f0 DV |
203 | I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits); |
204 | POSTING_READ(bus->gpio_reg); | |
79e53945 JB |
205 | } |
206 | ||
489fbc10 DK |
207 | static int |
208 | intel_gpio_pre_xfer(struct i2c_adapter *adapter) | |
209 | { | |
210 | struct intel_gmbus *bus = container_of(adapter, | |
211 | struct intel_gmbus, | |
212 | adapter); | |
213 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
214 | ||
91c8a326 | 215 | intel_i2c_reset(&dev_priv->drm); |
489fbc10 DK |
216 | intel_i2c_quirk_set(dev_priv, true); |
217 | set_data(bus, 1); | |
218 | set_clock(bus, 1); | |
219 | udelay(I2C_RISEFALL_TIME); | |
220 | return 0; | |
221 | } | |
222 | ||
223 | static void | |
224 | intel_gpio_post_xfer(struct i2c_adapter *adapter) | |
225 | { | |
226 | struct intel_gmbus *bus = container_of(adapter, | |
227 | struct intel_gmbus, | |
228 | adapter); | |
229 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
230 | ||
231 | set_data(bus, 1); | |
232 | set_clock(bus, 1); | |
233 | intel_i2c_quirk_set(dev_priv, false); | |
234 | } | |
235 | ||
2ed06c93 | 236 | static void |
5ea6e5e3 | 237 | intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) |
f0217c42 | 238 | { |
36c785f0 | 239 | struct drm_i915_private *dev_priv = bus->dev_priv; |
36c785f0 | 240 | struct i2c_algo_bit_data *algo; |
f0217c42 | 241 | |
c167a6fc | 242 | algo = &bus->bit_algo; |
36c785f0 | 243 | |
f0f59a00 VS |
244 | bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base + |
245 | i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg)); | |
c167a6fc | 246 | bus->adapter.algo_data = algo; |
36c785f0 DV |
247 | algo->setsda = set_data; |
248 | algo->setscl = set_clock; | |
249 | algo->getsda = get_data; | |
250 | algo->getscl = get_clock; | |
489fbc10 DK |
251 | algo->pre_xfer = intel_gpio_pre_xfer; |
252 | algo->post_xfer = intel_gpio_post_xfer; | |
36c785f0 DV |
253 | algo->udelay = I2C_RISEFALL_TIME; |
254 | algo->timeout = usecs_to_jiffies(2200); | |
255 | algo->data = bus; | |
79e53945 JB |
256 | } |
257 | ||
4e6c2d58 | 258 | static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) |
61168c53 | 259 | { |
28c70f16 | 260 | DEFINE_WAIT(wait); |
4e6c2d58 CW |
261 | u32 gmbus2; |
262 | int ret; | |
c12aba5a | 263 | |
28c70f16 DV |
264 | /* Important: The hw handles only the first bit, so set only one! Since |
265 | * we also need to check for NAKs besides the hw ready/idle signal, we | |
4e6c2d58 CW |
266 | * need to wake up periodically and check that ourselves. |
267 | */ | |
268 | if (!HAS_GMBUS_IRQ(dev_priv)) | |
269 | irq_en = 0; | |
28c70f16 | 270 | |
4e6c2d58 CW |
271 | add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); |
272 | I915_WRITE_FW(GMBUS4, irq_en); | |
61168c53 | 273 | |
4e6c2d58 CW |
274 | status |= GMBUS_SATOER; |
275 | ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); | |
276 | if (ret) | |
277 | ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); | |
28c70f16 | 278 | |
4e6c2d58 CW |
279 | I915_WRITE_FW(GMBUS4, 0); |
280 | remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); | |
61168c53 DV |
281 | |
282 | if (gmbus2 & GMBUS_SATOER) | |
283 | return -ENXIO; | |
4e6c2d58 CW |
284 | |
285 | return ret; | |
61168c53 DV |
286 | } |
287 | ||
2c438c02 DV |
288 | static int |
289 | gmbus_wait_idle(struct drm_i915_private *dev_priv) | |
290 | { | |
4e6c2d58 CW |
291 | DEFINE_WAIT(wait); |
292 | u32 irq_enable; | |
2c438c02 | 293 | int ret; |
2c438c02 | 294 | |
2c438c02 | 295 | /* Important: The hw handles only the first bit, so set only one! */ |
4e6c2d58 CW |
296 | irq_enable = 0; |
297 | if (HAS_GMBUS_IRQ(dev_priv)) | |
298 | irq_enable = GMBUS_IDLE_EN; | |
2c438c02 | 299 | |
4e6c2d58 CW |
300 | add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); |
301 | I915_WRITE_FW(GMBUS4, irq_enable); | |
2c438c02 | 302 | |
4e6c2d58 CW |
303 | ret = intel_wait_for_register_fw(dev_priv, |
304 | GMBUS2, GMBUS_ACTIVE, 0, | |
305 | 10); | |
2c438c02 | 306 | |
4e6c2d58 CW |
307 | I915_WRITE_FW(GMBUS4, 0); |
308 | remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); | |
309 | ||
310 | return ret; | |
2c438c02 DV |
311 | } |
312 | ||
924a93ed | 313 | static int |
9535c475 DT |
314 | gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, |
315 | unsigned short addr, u8 *buf, unsigned int len, | |
316 | u32 gmbus1_index) | |
924a93ed | 317 | { |
4e6c2d58 CW |
318 | I915_WRITE_FW(GMBUS1, |
319 | gmbus1_index | | |
320 | GMBUS_CYCLE_WAIT | | |
321 | (len << GMBUS_BYTE_COUNT_SHIFT) | | |
322 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
323 | GMBUS_SLAVE_READ | GMBUS_SW_RDY); | |
79985eee | 324 | while (len) { |
90e6b26d | 325 | int ret; |
924a93ed DK |
326 | u32 val, loop = 0; |
327 | ||
4e6c2d58 | 328 | ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); |
90e6b26d | 329 | if (ret) |
61168c53 | 330 | return ret; |
924a93ed | 331 | |
4e6c2d58 | 332 | val = I915_READ_FW(GMBUS3); |
924a93ed DK |
333 | do { |
334 | *buf++ = val & 0xff; | |
335 | val >>= 8; | |
336 | } while (--len && ++loop < 4); | |
79985eee | 337 | } |
924a93ed DK |
338 | |
339 | return 0; | |
340 | } | |
341 | ||
342 | static int | |
9535c475 DT |
343 | gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, |
344 | u32 gmbus1_index) | |
924a93ed | 345 | { |
924a93ed | 346 | u8 *buf = msg->buf; |
9535c475 DT |
347 | unsigned int rx_size = msg->len; |
348 | unsigned int len; | |
349 | int ret; | |
350 | ||
351 | do { | |
352 | len = min(rx_size, GMBUS_BYTE_COUNT_MAX); | |
353 | ||
354 | ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, | |
355 | buf, len, gmbus1_index); | |
356 | if (ret) | |
357 | return ret; | |
358 | ||
359 | rx_size -= len; | |
360 | buf += len; | |
361 | } while (rx_size != 0); | |
362 | ||
363 | return 0; | |
364 | } | |
365 | ||
366 | static int | |
367 | gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, | |
368 | unsigned short addr, u8 *buf, unsigned int len) | |
369 | { | |
9535c475 | 370 | unsigned int chunk_size = len; |
924a93ed DK |
371 | u32 val, loop; |
372 | ||
373 | val = loop = 0; | |
26883c31 DK |
374 | while (len && loop < 4) { |
375 | val |= *buf++ << (8 * loop++); | |
376 | len -= 1; | |
377 | } | |
924a93ed | 378 | |
4e6c2d58 CW |
379 | I915_WRITE_FW(GMBUS3, val); |
380 | I915_WRITE_FW(GMBUS1, | |
381 | GMBUS_CYCLE_WAIT | | |
382 | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | | |
383 | (addr << GMBUS_SLAVE_ADDR_SHIFT) | | |
384 | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); | |
924a93ed | 385 | while (len) { |
90e6b26d | 386 | int ret; |
90e6b26d | 387 | |
924a93ed DK |
388 | val = loop = 0; |
389 | do { | |
390 | val |= *buf++ << (8 * loop); | |
391 | } while (--len && ++loop < 4); | |
392 | ||
4e6c2d58 | 393 | I915_WRITE_FW(GMBUS3, val); |
7a39a9d4 | 394 | |
4e6c2d58 | 395 | ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); |
90e6b26d | 396 | if (ret) |
61168c53 | 397 | return ret; |
924a93ed | 398 | } |
9535c475 DT |
399 | |
400 | return 0; | |
401 | } | |
402 | ||
403 | static int | |
404 | gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg) | |
405 | { | |
406 | u8 *buf = msg->buf; | |
407 | unsigned int tx_size = msg->len; | |
408 | unsigned int len; | |
409 | int ret; | |
410 | ||
411 | do { | |
412 | len = min(tx_size, GMBUS_BYTE_COUNT_MAX); | |
413 | ||
414 | ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len); | |
415 | if (ret) | |
416 | return ret; | |
417 | ||
418 | buf += len; | |
419 | tx_size -= len; | |
420 | } while (tx_size != 0); | |
421 | ||
924a93ed DK |
422 | return 0; |
423 | } | |
424 | ||
56f9eac0 DK |
425 | /* |
426 | * The gmbus controller can combine a 1 or 2 byte write with a read that | |
427 | * immediately follows it by using an "INDEX" cycle. | |
428 | */ | |
429 | static bool | |
430 | gmbus_is_index_read(struct i2c_msg *msgs, int i, int num) | |
431 | { | |
432 | return (i + 1 < num && | |
433 | !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 && | |
434 | (msgs[i + 1].flags & I2C_M_RD)); | |
435 | } | |
436 | ||
437 | static int | |
438 | gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs) | |
439 | { | |
56f9eac0 DK |
440 | u32 gmbus1_index = 0; |
441 | u32 gmbus5 = 0; | |
442 | int ret; | |
443 | ||
444 | if (msgs[0].len == 2) | |
445 | gmbus5 = GMBUS_2BYTE_INDEX_EN | | |
446 | msgs[0].buf[1] | (msgs[0].buf[0] << 8); | |
447 | if (msgs[0].len == 1) | |
448 | gmbus1_index = GMBUS_CYCLE_INDEX | | |
449 | (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); | |
450 | ||
451 | /* GMBUS5 holds 16-bit index */ | |
452 | if (gmbus5) | |
4e6c2d58 | 453 | I915_WRITE_FW(GMBUS5, gmbus5); |
56f9eac0 DK |
454 | |
455 | ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index); | |
456 | ||
457 | /* Clear GMBUS5 after each index transfer */ | |
458 | if (gmbus5) | |
4e6c2d58 | 459 | I915_WRITE_FW(GMBUS5, 0); |
56f9eac0 DK |
460 | |
461 | return ret; | |
462 | } | |
463 | ||
f899fc64 | 464 | static int |
bffce907 | 465 | do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) |
f899fc64 CW |
466 | { |
467 | struct intel_gmbus *bus = container_of(adapter, | |
468 | struct intel_gmbus, | |
469 | adapter); | |
c2b9152f | 470 | struct drm_i915_private *dev_priv = bus->dev_priv; |
4e6c2d58 CW |
471 | const unsigned int fw = |
472 | intel_uncore_forcewake_for_reg(dev_priv, GMBUS0, | |
473 | FW_REG_READ | FW_REG_WRITE); | |
699fc401 | 474 | int i = 0, inc, try = 0; |
72d66afd | 475 | int ret = 0; |
f899fc64 | 476 | |
4e6c2d58 | 477 | intel_uncore_forcewake_get(dev_priv, fw); |
3f5f1554 | 478 | retry: |
4e6c2d58 | 479 | I915_WRITE_FW(GMBUS0, bus->reg0); |
f899fc64 | 480 | |
3f5f1554 JN |
481 | for (; i < num; i += inc) { |
482 | inc = 1; | |
56f9eac0 DK |
483 | if (gmbus_is_index_read(msgs, i, num)) { |
484 | ret = gmbus_xfer_index_read(dev_priv, &msgs[i]); | |
3f5f1554 | 485 | inc = 2; /* an index read is two msgs */ |
56f9eac0 DK |
486 | } else if (msgs[i].flags & I2C_M_RD) { |
487 | ret = gmbus_xfer_read(dev_priv, &msgs[i], 0); | |
488 | } else { | |
72d66afd | 489 | ret = gmbus_xfer_write(dev_priv, &msgs[i]); |
56f9eac0 | 490 | } |
924a93ed | 491 | |
0aeb9048 | 492 | if (!ret) |
4e6c2d58 CW |
493 | ret = gmbus_wait(dev_priv, |
494 | GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); | |
924a93ed DK |
495 | if (ret == -ETIMEDOUT) |
496 | goto timeout; | |
0aeb9048 | 497 | else if (ret) |
924a93ed | 498 | goto clear_err; |
f899fc64 CW |
499 | } |
500 | ||
72d66afd DK |
501 | /* Generate a STOP condition on the bus. Note that gmbus can't generata |
502 | * a STOP on the very first cycle. To simplify the code we | |
503 | * unconditionally generate the STOP condition with an additional gmbus | |
504 | * cycle. */ | |
4e6c2d58 | 505 | I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); |
72d66afd | 506 | |
e646d577 DK |
507 | /* Mark the GMBUS interface as disabled after waiting for idle. |
508 | * We will re-enable it at the start of the next xfer, | |
509 | * till then let it sleep. | |
510 | */ | |
2c438c02 | 511 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f | 512 | DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", |
e646d577 | 513 | adapter->name); |
72d66afd DK |
514 | ret = -ETIMEDOUT; |
515 | } | |
4e6c2d58 | 516 | I915_WRITE_FW(GMBUS0, 0); |
72d66afd | 517 | ret = ret ?: i; |
e646d577 | 518 | goto out; |
7f58aabc CW |
519 | |
520 | clear_err: | |
e646d577 DK |
521 | /* |
522 | * Wait for bus to IDLE before clearing NAK. | |
523 | * If we clear the NAK while bus is still active, then it will stay | |
524 | * active and the next transaction may fail. | |
65e81866 DV |
525 | * |
526 | * If no ACK is received during the address phase of a transaction, the | |
527 | * adapter must report -ENXIO. It is not clear what to return if no ACK | |
528 | * is received at other times. But we have to be careful to not return | |
529 | * spurious -ENXIO because that will prevent i2c and drm edid functions | |
530 | * from retrying. So return -ENXIO only when gmbus properly quiescents - | |
531 | * timing out seems to happen when there _is_ a ddc chip present, but | |
532 | * it's slow responding and only answers on the 2nd retry. | |
e646d577 | 533 | */ |
65e81866 | 534 | ret = -ENXIO; |
2c438c02 | 535 | if (gmbus_wait_idle(dev_priv)) { |
56fa6d6f DK |
536 | DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", |
537 | adapter->name); | |
65e81866 DV |
538 | ret = -ETIMEDOUT; |
539 | } | |
e646d577 | 540 | |
7f58aabc CW |
541 | /* Toggle the Software Clear Interrupt bit. This has the effect |
542 | * of resetting the GMBUS controller and so clearing the | |
543 | * BUS_ERROR raised by the slave's NAK. | |
544 | */ | |
4e6c2d58 CW |
545 | I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); |
546 | I915_WRITE_FW(GMBUS1, 0); | |
547 | I915_WRITE_FW(GMBUS0, 0); | |
7f58aabc | 548 | |
56fa6d6f | 549 | DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", |
e646d577 DK |
550 | adapter->name, msgs[i].addr, |
551 | (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); | |
552 | ||
3f5f1554 JN |
553 | /* |
554 | * Passive adapters sometimes NAK the first probe. Retry the first | |
555 | * message once on -ENXIO for GMBUS transfers; the bit banging algorithm | |
556 | * has retries internally. See also the retry loop in | |
557 | * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. | |
558 | */ | |
559 | if (ret == -ENXIO && i == 0 && try++ == 0) { | |
560 | DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", | |
561 | adapter->name); | |
562 | goto retry; | |
563 | } | |
564 | ||
8a8ed1f5 | 565 | goto out; |
f899fc64 CW |
566 | |
567 | timeout: | |
70677801 VS |
568 | DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", |
569 | bus->adapter.name, bus->reg0 & 0xff); | |
4e6c2d58 | 570 | I915_WRITE_FW(GMBUS0, 0); |
7f58aabc | 571 | |
bffce907 JN |
572 | /* |
573 | * Hardware may not support GMBUS over these pins? Try GPIO bitbanging | |
574 | * instead. Use EAGAIN to have i2c core retry. | |
575 | */ | |
bffce907 | 576 | ret = -EAGAIN; |
489fbc10 | 577 | |
8a8ed1f5 | 578 | out: |
4e6c2d58 | 579 | intel_uncore_forcewake_put(dev_priv, fw); |
bffce907 JN |
580 | return ret; |
581 | } | |
582 | ||
583 | static int | |
584 | gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) | |
585 | { | |
586 | struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, | |
587 | adapter); | |
588 | struct drm_i915_private *dev_priv = bus->dev_priv; | |
589 | int ret; | |
590 | ||
591 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); | |
592 | mutex_lock(&dev_priv->gmbus_mutex); | |
593 | ||
3e4d44e0 | 594 | if (bus->force_bit) { |
bffce907 | 595 | ret = i2c_bit_algo.master_xfer(adapter, msgs, num); |
3e4d44e0 VS |
596 | if (ret < 0) |
597 | bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; | |
598 | } else { | |
bffce907 | 599 | ret = do_gmbus_xfer(adapter, msgs, num); |
3e4d44e0 VS |
600 | if (ret == -EAGAIN) |
601 | bus->force_bit |= GMBUS_FORCE_BIT_RETRY; | |
602 | } | |
f0ab43e6 | 603 | |
bffce907 | 604 | mutex_unlock(&dev_priv->gmbus_mutex); |
f0ab43e6 VS |
605 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
606 | ||
8a8ed1f5 | 607 | return ret; |
f899fc64 CW |
608 | } |
609 | ||
610 | static u32 gmbus_func(struct i2c_adapter *adapter) | |
611 | { | |
f6f808c8 DV |
612 | return i2c_bit_algo.functionality(adapter) & |
613 | (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | | |
f899fc64 CW |
614 | /* I2C_FUNC_10BIT_ADDR | */ |
615 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | | |
616 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); | |
617 | } | |
618 | ||
619 | static const struct i2c_algorithm gmbus_algorithm = { | |
620 | .master_xfer = gmbus_xfer, | |
621 | .functionality = gmbus_func | |
622 | }; | |
623 | ||
79e53945 | 624 | /** |
f899fc64 CW |
625 | * intel_gmbus_setup - instantiate all Intel i2c GMBuses |
626 | * @dev: DRM device | |
79e53945 | 627 | */ |
f899fc64 CW |
628 | int intel_setup_gmbus(struct drm_device *dev) |
629 | { | |
fac5e23e | 630 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 631 | struct pci_dev *pdev = dev_priv->drm.pdev; |
5ea6e5e3 JN |
632 | struct intel_gmbus *bus; |
633 | unsigned int pin; | |
634 | int ret; | |
f899fc64 | 635 | |
ab5c608b BW |
636 | if (HAS_PCH_NOP(dev)) |
637 | return 0; | |
b2e8c6cd | 638 | |
666a4537 | 639 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
d8112150 | 640 | dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |
f0f59a00 VS |
641 | else if (!HAS_GMCH_DISPLAY(dev_priv)) |
642 | dev_priv->gpio_mmio_base = | |
643 | i915_mmio_reg_offset(PCH_GPIOA) - | |
644 | i915_mmio_reg_offset(GPIOA); | |
110447fc | 645 | |
8a8ed1f5 | 646 | mutex_init(&dev_priv->gmbus_mutex); |
28c70f16 | 647 | init_waitqueue_head(&dev_priv->gmbus_wait_queue); |
8a8ed1f5 | 648 | |
5ea6e5e3 | 649 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { |
88ac7939 | 650 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 JN |
651 | continue; |
652 | ||
653 | bus = &dev_priv->gmbus[pin]; | |
f899fc64 CW |
654 | |
655 | bus->adapter.owner = THIS_MODULE; | |
656 | bus->adapter.class = I2C_CLASS_DDC; | |
657 | snprintf(bus->adapter.name, | |
69669455 JD |
658 | sizeof(bus->adapter.name), |
659 | "i915 gmbus %s", | |
4c272834 | 660 | get_gmbus_pin(dev_priv, pin)->name); |
f899fc64 | 661 | |
52a05c30 | 662 | bus->adapter.dev.parent = &pdev->dev; |
c2b9152f | 663 | bus->dev_priv = dev_priv; |
f899fc64 CW |
664 | |
665 | bus->adapter.algo = &gmbus_algorithm; | |
f899fc64 | 666 | |
8b1f165a VS |
667 | /* |
668 | * We wish to retry with bit banging | |
669 | * after a timed out GMBUS attempt. | |
670 | */ | |
671 | bus->adapter.retries = 1; | |
672 | ||
e957d772 | 673 | /* By default use a conservative clock rate */ |
5ea6e5e3 | 674 | bus->reg0 = pin | GMBUS_RATE_100KHZ; |
cb8ea752 | 675 | |
83ee9e64 DV |
676 | /* gmbus seems to be broken on i830 */ |
677 | if (IS_I830(dev)) | |
f2ce9faf | 678 | bus->force_bit = 1; |
83ee9e64 | 679 | |
5ea6e5e3 | 680 | intel_gpio_setup(bus, pin); |
cee25168 JN |
681 | |
682 | ret = i2c_add_adapter(&bus->adapter); | |
683 | if (ret) | |
684 | goto err; | |
f899fc64 CW |
685 | } |
686 | ||
91c8a326 | 687 | intel_i2c_reset(&dev_priv->drm); |
f899fc64 CW |
688 | |
689 | return 0; | |
690 | ||
691 | err: | |
2417c8c0 | 692 | while (pin--) { |
88ac7939 | 693 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 JN |
694 | continue; |
695 | ||
696 | bus = &dev_priv->gmbus[pin]; | |
f899fc64 CW |
697 | i2c_del_adapter(&bus->adapter); |
698 | } | |
f899fc64 CW |
699 | return ret; |
700 | } | |
701 | ||
3bd7d909 | 702 | struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, |
0184df46 | 703 | unsigned int pin) |
3bd7d909 | 704 | { |
88ac7939 | 705 | if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) |
5ea6e5e3 JN |
706 | return NULL; |
707 | ||
708 | return &dev_priv->gmbus[pin].adapter; | |
3bd7d909 DK |
709 | } |
710 | ||
e957d772 CW |
711 | void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) |
712 | { | |
713 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
714 | ||
d5090b96 | 715 | bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; |
e957d772 CW |
716 | } |
717 | ||
718 | void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) | |
719 | { | |
720 | struct intel_gmbus *bus = to_intel_gmbus(adapter); | |
ade754ec VS |
721 | struct drm_i915_private *dev_priv = bus->dev_priv; |
722 | ||
723 | mutex_lock(&dev_priv->gmbus_mutex); | |
e957d772 | 724 | |
f2ce9faf CW |
725 | bus->force_bit += force_bit ? 1 : -1; |
726 | DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", | |
727 | force_bit ? "en" : "dis", adapter->name, | |
728 | bus->force_bit); | |
ade754ec VS |
729 | |
730 | mutex_unlock(&dev_priv->gmbus_mutex); | |
e957d772 CW |
731 | } |
732 | ||
f899fc64 | 733 | void intel_teardown_gmbus(struct drm_device *dev) |
79e53945 | 734 | { |
fac5e23e | 735 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ea6e5e3 JN |
736 | struct intel_gmbus *bus; |
737 | unsigned int pin; | |
738 | ||
739 | for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { | |
88ac7939 | 740 | if (!intel_gmbus_is_valid_pin(dev_priv, pin)) |
5ea6e5e3 | 741 | continue; |
f9c10a9b | 742 | |
5ea6e5e3 | 743 | bus = &dev_priv->gmbus[pin]; |
f899fc64 CW |
744 | i2c_del_adapter(&bus->adapter); |
745 | } | |
79e53945 | 746 | } |