Merge remote-tracking branch 'spi/for-next'
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_lrc.h
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1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef _INTEL_LRC_H_
25#define _INTEL_LRC_H_
26
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27#include "intel_ringbuffer.h"
28
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29#define GEN8_LR_CONTEXT_ALIGN 4096
30
4ba70e44 31/* Execlists regs */
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32#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
33#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
34#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
35#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
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36#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
37#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
6922528a 38#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
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39#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
40#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
41#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
42#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
4ba70e44 43
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44/* The docs specify that the write pointer wraps around after 5h, "After status
45 * is written out to the last available status QW at offset 5h, this pointer
46 * wraps to 0."
47 *
48 * Therefore, one must infer than even though there are 3 bits available, 6 and
49 * 7 appear to be * reserved.
50 */
51#define GEN8_CSB_ENTRIES 6
52#define GEN8_CSB_PTR_MASK 0x7
53#define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8)
54#define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
55#define GEN8_CSB_WRITE_PTR(csb_status) \
56 (((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
57#define GEN8_CSB_READ_PTR(csb_status) \
58 (((csb_status) & GEN8_CSB_READ_PTR_MASK) >> 8)
59
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60enum {
61 INTEL_CONTEXT_SCHEDULE_IN = 0,
62 INTEL_CONTEXT_SCHEDULE_OUT,
63};
64
454afebd 65/* Logical Rings */
40e895ce 66int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
ccd98fe4 67int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
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68void intel_logical_ring_stop(struct intel_engine_cs *engine);
69void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
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70int logical_render_ring_init(struct intel_engine_cs *engine);
71int logical_xcs_ring_init(struct intel_engine_cs *engine);
72
8b3e2d36 73int intel_engines_init(struct drm_device *dev);
454afebd 74
ede7d42b 75/* Logical Ring Contexts */
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76
77/* One extra page is added before LRC for GuC as shared data */
78#define LRC_GUCSHR_PN (0)
79#define LRC_PPHWSP_PN (LRC_GUCSHR_PN + 1)
80#define LRC_STATE_PN (LRC_PPHWSP_PN + 1)
81
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82struct i915_gem_context;
83
0bc40be8 84uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
e2efd130 85void intel_lr_context_unpin(struct i915_gem_context *ctx,
e5292823 86 struct intel_engine_cs *engine);
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87
88struct drm_i915_private;
89
821ed7df 90void intel_lr_context_resume(struct drm_i915_private *dev_priv);
e2efd130 91uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
0bc40be8 92 struct intel_engine_cs *engine);
ede7d42b 93
127f1003 94/* Execlists */
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95int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv,
96 int enable_execlists);
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97void intel_execlists_enable_submission(struct drm_i915_private *dev_priv);
98
b20385f1 99#endif /* _INTEL_LRC_H_ */
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