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drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
CommitLineData
9c065a7d
DV		 1/*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29#include <linux/pm_runtime.h>
30#include <linux/vgaarb.h>
31
32#include "i915_drv.h"
33#include "intel_drv.h"
9c065a7d 34
e4e7684f
DV		 35/**
36 * DOC: runtime pm
37 *
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
43 *
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
50 */
51
9c065a7d
DV		 52#define for_each_power_well(i, power_well, domain_mask, power_domains) \
53 for (i = 0; \
54 i < (power_domains)->power_well_count && \
55 ((power_well) = &(power_domains)->power_wells[i]); \
56 i++) \
95150bdf 57 for_each_if ((power_well)->domains & (domain_mask))
9c065a7d
DV		 58
59#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
60 for (i = (power_domains)->power_well_count - 1; \
61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
62 i--) \
95150bdf 63 for_each_if ((power_well)->domains & (domain_mask))
9c065a7d 64
5aefb239
SS		 65bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
66 int power_well_id);
67
9c8d0b8e
ID		 68static struct i915_power_well *
69lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
70
9895ad03
DS		 71const char *
72intel_display_power_domain_str(enum intel_display_power_domain domain)
73{
74 switch (domain) {
75 case POWER_DOMAIN_PIPE_A:
76 return "PIPE_A";
77 case POWER_DOMAIN_PIPE_B:
78 return "PIPE_B";
79 case POWER_DOMAIN_PIPE_C:
80 return "PIPE_C";
81 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
82 return "PIPE_A_PANEL_FITTER";
83 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
84 return "PIPE_B_PANEL_FITTER";
85 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
86 return "PIPE_C_PANEL_FITTER";
87 case POWER_DOMAIN_TRANSCODER_A:
88 return "TRANSCODER_A";
89 case POWER_DOMAIN_TRANSCODER_B:
90 return "TRANSCODER_B";
91 case POWER_DOMAIN_TRANSCODER_C:
92 return "TRANSCODER_C";
93 case POWER_DOMAIN_TRANSCODER_EDP:
94 return "TRANSCODER_EDP";
4d1de975
JN		 95 case POWER_DOMAIN_TRANSCODER_DSI_A:
96 return "TRANSCODER_DSI_A";
97 case POWER_DOMAIN_TRANSCODER_DSI_C:
98 return "TRANSCODER_DSI_C";
9895ad03
DS		 99 case POWER_DOMAIN_PORT_DDI_A_LANES:
100 return "PORT_DDI_A_LANES";
101 case POWER_DOMAIN_PORT_DDI_B_LANES:
102 return "PORT_DDI_B_LANES";
103 case POWER_DOMAIN_PORT_DDI_C_LANES:
104 return "PORT_DDI_C_LANES";
105 case POWER_DOMAIN_PORT_DDI_D_LANES:
106 return "PORT_DDI_D_LANES";
107 case POWER_DOMAIN_PORT_DDI_E_LANES:
108 return "PORT_DDI_E_LANES";
109 case POWER_DOMAIN_PORT_DSI:
110 return "PORT_DSI";
111 case POWER_DOMAIN_PORT_CRT:
112 return "PORT_CRT";
113 case POWER_DOMAIN_PORT_OTHER:
114 return "PORT_OTHER";
115 case POWER_DOMAIN_VGA:
116 return "VGA";
117 case POWER_DOMAIN_AUDIO:
118 return "AUDIO";
119 case POWER_DOMAIN_PLLS:
120 return "PLLS";
121 case POWER_DOMAIN_AUX_A:
122 return "AUX_A";
123 case POWER_DOMAIN_AUX_B:
124 return "AUX_B";
125 case POWER_DOMAIN_AUX_C:
126 return "AUX_C";
127 case POWER_DOMAIN_AUX_D:
128 return "AUX_D";
129 case POWER_DOMAIN_GMBUS:
130 return "GMBUS";
131 case POWER_DOMAIN_INIT:
132 return "INIT";
133 case POWER_DOMAIN_MODESET:
134 return "MODESET";
135 default:
136 MISSING_CASE(domain);
137 return "?";
138 }
139}
140
e8ca9320
DL		 141static void intel_power_well_enable(struct drm_i915_private *dev_priv,
142 struct i915_power_well *power_well)
143{
144 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
145 power_well->ops->enable(dev_priv, power_well);
146 power_well->hw_enabled = true;
147}
148
dcddab3a
DL		 149static void intel_power_well_disable(struct drm_i915_private *dev_priv,
150 struct i915_power_well *power_well)
151{
152 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
153 power_well->hw_enabled = false;
154 power_well->ops->disable(dev_priv, power_well);
155}
156
b409ca95
ID		 157static void intel_power_well_get(struct drm_i915_private *dev_priv,
158 struct i915_power_well *power_well)
159{
160 if (!power_well->count++)
161 intel_power_well_enable(dev_priv, power_well);
162}
163
164static void intel_power_well_put(struct drm_i915_private *dev_priv,
165 struct i915_power_well *power_well)
166{
167 WARN(!power_well->count, "Use count on power well %s is already zero",
168 power_well->name);
169
170 if (!--power_well->count)
171 intel_power_well_disable(dev_priv, power_well);
172}
173
e4e7684f 174/*
9c065a7d
DV		 175 * We should only use the power well if we explicitly asked the hardware to
176 * enable it, so check if it's enabled and also check if we've requested it to
177 * be enabled.
178 */
179static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
180 struct i915_power_well *power_well)
181{
182 return I915_READ(HSW_PWR_WELL_DRIVER) ==
183 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
184}
185
e4e7684f
DV		 186/**
187 * __intel_display_power_is_enabled - unlocked check for a power domain
188 * @dev_priv: i915 device instance
189 * @domain: power domain to check
190 *
191 * This is the unlocked version of intel_display_power_is_enabled() and should
192 * only be used from error capture and recovery code where deadlocks are
193 * possible.
194 *
195 * Returns:
196 * True when the power domain is enabled, false otherwise.
197 */
f458ebbc
DV		 198bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
199 enum intel_display_power_domain domain)
9c065a7d
DV		 200{
201 struct i915_power_domains *power_domains;
202 struct i915_power_well *power_well;
203 bool is_enabled;
204 int i;
205
206 if (dev_priv->pm.suspended)
207 return false;
208
209 power_domains = &dev_priv->power_domains;
210
211 is_enabled = true;
212
213 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
214 if (power_well->always_on)
215 continue;
216
217 if (!power_well->hw_enabled) {
218 is_enabled = false;
219 break;
220 }
221 }
222
223 return is_enabled;
224}
225
e4e7684f 226/**
f61ccae3 227 * intel_display_power_is_enabled - check for a power domain
e4e7684f
DV		 228 * @dev_priv: i915 device instance
229 * @domain: power domain to check
230 *
231 * This function can be used to check the hw power domain state. It is mostly
232 * used in hardware state readout functions. Everywhere else code should rely
233 * upon explicit power domain reference counting to ensure that the hardware
234 * block is powered up before accessing it.
235 *
236 * Callers must hold the relevant modesetting locks to ensure that concurrent
237 * threads can't disable the power well while the caller tries to read a few
238 * registers.
239 *
240 * Returns:
241 * True when the power domain is enabled, false otherwise.
242 */
f458ebbc
DV		 243bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
244 enum intel_display_power_domain domain)
9c065a7d
DV		 245{
246 struct i915_power_domains *power_domains;
247 bool ret;
248
249 power_domains = &dev_priv->power_domains;
250
251 mutex_lock(&power_domains->lock);
f458ebbc 252 ret = __intel_display_power_is_enabled(dev_priv, domain);
9c065a7d
DV		 253 mutex_unlock(&power_domains->lock);
254
255 return ret;
256}
257
e4e7684f
DV		 258/**
259 * intel_display_set_init_power - set the initial power domain state
260 * @dev_priv: i915 device instance
261 * @enable: whether to enable or disable the initial power domain state
262 *
263 * For simplicity our driver load/unload and system suspend/resume code assumes
264 * that all power domains are always enabled. This functions controls the state
265 * of this little hack. While the initial power domain state is enabled runtime
266 * pm is effectively disabled.
267 */
d9bc89d9
DV		 268void intel_display_set_init_power(struct drm_i915_private *dev_priv,
269 bool enable)
270{
271 if (dev_priv->power_domains.init_power_on == enable)
272 return;
273
274 if (enable)
275 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
276 else
277 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
278
279 dev_priv->power_domains.init_power_on = enable;
280}
281
9c065a7d
DV		 282/*
283 * Starting with Haswell, we have a "Power Down Well" that can be turned off
284 * when not needed anymore. We have 4 registers that can request the power well
285 * to be enabled, and it will only be disabled if none of the registers is
286 * requesting it to be enabled.
287 */
288static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
289{
290 struct drm_device *dev = dev_priv->dev;
291
292 /*
293 * After we re-enable the power well, if we touch VGA register 0x3d5
294 * we'll get unclaimed register interrupts. This stops after we write
295 * anything to the VGA MSR register. The vgacon module uses this
296 * register all the time, so if we unbind our driver and, as a
297 * consequence, bind vgacon, we'll get stuck in an infinite loop at
298 * console_unlock(). So make here we touch the VGA MSR register, making
299 * sure vgacon can keep working normally without triggering interrupts
300 * and error messages.
301 */
302 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
303 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
304 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
305
25400392 306 if (IS_BROADWELL(dev))
4c6c03be
DL		 307 gen8_irq_power_well_post_enable(dev_priv,
308 1 << PIPE_C | 1 << PIPE_B);
9c065a7d
DV		 309}
310
aae8ba84
VS		 311static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
312{
313 if (IS_BROADWELL(dev_priv))
314 gen8_irq_power_well_pre_disable(dev_priv,
315 1 << PIPE_C | 1 << PIPE_B);
316}
317
d14c0343
DL		 318static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
319 struct i915_power_well *power_well)
320{
321 struct drm_device *dev = dev_priv->dev;
322
323 /*
324 * After we re-enable the power well, if we touch VGA register 0x3d5
325 * we'll get unclaimed register interrupts. This stops after we write
326 * anything to the VGA MSR register. The vgacon module uses this
327 * register all the time, so if we unbind our driver and, as a
328 * consequence, bind vgacon, we'll get stuck in an infinite loop at
329 * console_unlock(). So make here we touch the VGA MSR register, making
330 * sure vgacon can keep working normally without triggering interrupts
331 * and error messages.
332 */
333 if (power_well->data == SKL_DISP_PW_2) {
334 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
335 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
336 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
337
338 gen8_irq_power_well_post_enable(dev_priv,
339 1 << PIPE_C | 1 << PIPE_B);
340 }
d14c0343
DL		 341}
342
aae8ba84
VS		 343static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
344 struct i915_power_well *power_well)
345{
346 if (power_well->data == SKL_DISP_PW_2)
347 gen8_irq_power_well_pre_disable(dev_priv,
348 1 << PIPE_C | 1 << PIPE_B);
349}
350
9c065a7d
DV		 351static void hsw_set_power_well(struct drm_i915_private *dev_priv,
352 struct i915_power_well *power_well, bool enable)
353{
354 bool is_enabled, enable_requested;
355 uint32_t tmp;
356
357 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
358 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
359 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
360
361 if (enable) {
362 if (!enable_requested)
363 I915_WRITE(HSW_PWR_WELL_DRIVER,
364 HSW_PWR_WELL_ENABLE_REQUEST);
365
366 if (!is_enabled) {
367 DRM_DEBUG_KMS("Enabling power well\n");
2c2ccc3a
CW		 368 if (intel_wait_for_register(dev_priv,
369 HSW_PWR_WELL_DRIVER,
370 HSW_PWR_WELL_STATE_ENABLED,
371 HSW_PWR_WELL_STATE_ENABLED,
372 20))
9c065a7d 373 DRM_ERROR("Timeout enabling power well\n");
6d729bff 374 hsw_power_well_post_enable(dev_priv);
9c065a7d
DV		 375 }
376
9c065a7d
DV		 377 } else {
378 if (enable_requested) {
aae8ba84 379 hsw_power_well_pre_disable(dev_priv);
9c065a7d
DV		 380 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
381 POSTING_READ(HSW_PWR_WELL_DRIVER);
382 DRM_DEBUG_KMS("Requesting to disable the power well\n");
383 }
384 }
385}
386
94dd5138
S		 387#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
388 BIT(POWER_DOMAIN_TRANSCODER_A) | \
389 BIT(POWER_DOMAIN_PIPE_B) | \
390 BIT(POWER_DOMAIN_TRANSCODER_B) | \
391 BIT(POWER_DOMAIN_PIPE_C) | \
392 BIT(POWER_DOMAIN_TRANSCODER_C) | \
393 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
394 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
6331a704
PJ		 395 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
396 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
397 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
398 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
94dd5138
S		 399 BIT(POWER_DOMAIN_AUX_B) | \
400 BIT(POWER_DOMAIN_AUX_C) | \
401 BIT(POWER_DOMAIN_AUX_D) | \
402 BIT(POWER_DOMAIN_AUDIO) | \
403 BIT(POWER_DOMAIN_VGA) | \
404 BIT(POWER_DOMAIN_INIT))
94dd5138 405#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
6331a704
PJ		 406 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
407 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
94dd5138
S		 408 BIT(POWER_DOMAIN_INIT))
409#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
6331a704 410 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
94dd5138
S		 411 BIT(POWER_DOMAIN_INIT))
412#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
6331a704 413 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
94dd5138
S		 414 BIT(POWER_DOMAIN_INIT))
415#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
6331a704 416 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
94dd5138 417 BIT(POWER_DOMAIN_INIT))
9f836f90
PJ		 418#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
419 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
420 BIT(POWER_DOMAIN_MODESET) | \
421 BIT(POWER_DOMAIN_AUX_A) | \
422 BIT(POWER_DOMAIN_INIT))
94dd5138 423
0b4a2a36
S		 424#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
425 BIT(POWER_DOMAIN_TRANSCODER_A) | \
426 BIT(POWER_DOMAIN_PIPE_B) | \
427 BIT(POWER_DOMAIN_TRANSCODER_B) | \
428 BIT(POWER_DOMAIN_PIPE_C) | \
429 BIT(POWER_DOMAIN_TRANSCODER_C) | \
430 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
431 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
6331a704
PJ		 432 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
433 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
0b4a2a36
S		 434 BIT(POWER_DOMAIN_AUX_B) | \
435 BIT(POWER_DOMAIN_AUX_C) | \
436 BIT(POWER_DOMAIN_AUDIO) | \
437 BIT(POWER_DOMAIN_VGA) | \
f0ab43e6 438 BIT(POWER_DOMAIN_GMBUS) | \
0b4a2a36 439 BIT(POWER_DOMAIN_INIT))
9f836f90
PJ		 440#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
441 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
442 BIT(POWER_DOMAIN_MODESET) | \
443 BIT(POWER_DOMAIN_AUX_A) | \
444 BIT(POWER_DOMAIN_INIT))
9c8d0b8e
ID		 445#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
446 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
447 BIT(POWER_DOMAIN_AUX_A) | \
448 BIT(POWER_DOMAIN_INIT))
449#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
450 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
451 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
452 BIT(POWER_DOMAIN_AUX_B) | \
453 BIT(POWER_DOMAIN_AUX_C) | \
454 BIT(POWER_DOMAIN_INIT))
0b4a2a36 455
664326f8
SK		 456static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
457{
bfcdabe8
ID		 458 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
459 "DC9 already programmed to be enabled.\n");
460 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
461 "DC5 still not disabled to enable DC9.\n");
462 WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
463 WARN_ONCE(intel_irqs_enabled(dev_priv),
464 "Interrupts not disabled yet.\n");
664326f8
SK		 465
466 /*
467 * TODO: check for the following to verify the conditions to enter DC9
468 * state are satisfied:
469 * 1] Check relevant display engine registers to verify if mode set
470 * disable sequence was followed.
471 * 2] Check if display uninitialize sequence is initialized.
472 */
473}
474
475static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
476{
bfcdabe8
ID		 477 WARN_ONCE(intel_irqs_enabled(dev_priv),
478 "Interrupts not disabled yet.\n");
479 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
480 "DC5 still not disabled.\n");
664326f8
SK		 481
482 /*
483 * TODO: check for the following to verify DC9 state was indeed
484 * entered before programming to disable it:
485 * 1] Check relevant display engine registers to verify if mode
486 * set disable sequence was followed.
487 * 2] Check if display uninitialize sequence is initialized.
488 */
489}
490
779cb5d3
MK		 491static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
492 u32 state)
493{
494 int rewrites = 0;
495 int rereads = 0;
496 u32 v;
497
498 I915_WRITE(DC_STATE_EN, state);
499
500 /* It has been observed that disabling the dc6 state sometimes
501 * doesn't stick and dmc keeps returning old value. Make sure
502 * the write really sticks enough times and also force rewrite until
503 * we are confident that state is exactly what we want.
504 */
505 do {
506 v = I915_READ(DC_STATE_EN);
507
508 if (v != state) {
509 I915_WRITE(DC_STATE_EN, state);
510 rewrites++;
511 rereads = 0;
512 } else if (rereads++ > 5) {
513 break;
514 }
515
516 } while (rewrites < 100);
517
518 if (v != state)
519 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
520 state, v);
521
522 /* Most of the times we need one retry, avoid spam */
523 if (rewrites > 1)
524 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
525 state, rewrites);
526}
527
da2f41d1 528static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
664326f8 529{
da2f41d1 530 u32 mask;
664326f8 531
13ae3a0d
ID		 532 mask = DC_STATE_EN_UPTO_DC5;
533 if (IS_BROXTON(dev_priv))
534 mask |= DC_STATE_EN_DC9;
535 else
536 mask |= DC_STATE_EN_UPTO_DC6;
664326f8 537
da2f41d1
ID		 538 return mask;
539}
540
541void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
542{
543 u32 val;
544
545 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
546
547 DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
548 dev_priv->csr.dc_state, val);
549 dev_priv->csr.dc_state = val;
550}
551
552static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
553{
554 uint32_t val;
555 uint32_t mask;
556
a37baf3b
ID		 557 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
558 state &= dev_priv->csr.allowed_dc_mask;
443646c7 559
664326f8 560 val = I915_READ(DC_STATE_EN);
da2f41d1 561 mask = gen9_dc_mask(dev_priv);
13ae3a0d
ID		 562 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
563 val & mask, state);
832dba88
PJ		 564
565 /* Check if DMC is ignoring our DC state requests */
566 if ((val & mask) != dev_priv->csr.dc_state)
567 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
568 dev_priv->csr.dc_state, val & mask);
569
13ae3a0d
ID		 570 val &= ~mask;
571 val |= state;
779cb5d3
MK		 572
573 gen9_write_dc_state(dev_priv, val);
832dba88
PJ		 574
575 dev_priv->csr.dc_state = val & mask;
664326f8
SK		 576}
577
13ae3a0d 578void bxt_enable_dc9(struct drm_i915_private *dev_priv)
664326f8 579{
13ae3a0d
ID		 580 assert_can_enable_dc9(dev_priv);
581
582 DRM_DEBUG_KMS("Enabling DC9\n");
664326f8 583
78597996 584 intel_power_sequencer_reset(dev_priv);
13ae3a0d
ID		 585 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
586}
587
588void bxt_disable_dc9(struct drm_i915_private *dev_priv)
589{
664326f8
SK		 590 assert_can_disable_dc9(dev_priv);
591
592 DRM_DEBUG_KMS("Disabling DC9\n");
593
13ae3a0d 594 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
664326f8
SK		 595}
596
af5fead2
DV		 597static void assert_csr_loaded(struct drm_i915_private *dev_priv)
598{
599 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
600 "CSR program storage start is NULL\n");
601 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
602 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
603}
604
5aefb239 605static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
dc174300 606{
5aefb239
SS		 607 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
608 SKL_DISP_PW_2);
609
6ff8ab0d 610 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
5aefb239 611
6ff8ab0d
JB		 612 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
613 "DC5 already programmed to be enabled.\n");
c9b8846a 614 assert_rpm_wakelock_held(dev_priv);
5aefb239
SS		 615
616 assert_csr_loaded(dev_priv);
617}
618
f62c79b3 619void gen9_enable_dc5(struct drm_i915_private *dev_priv)
5aefb239 620{
5aefb239 621 assert_can_enable_dc5(dev_priv);
6b457d31
SK		 622
623 DRM_DEBUG_KMS("Enabling DC5\n");
624
13ae3a0d 625 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
dc174300
SS		 626}
627
93c7cb6c 628static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
f75a1985 629{
6ff8ab0d
JB		 630 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
631 "Backlight is not disabled.\n");
632 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
633 "DC6 already programmed to be enabled.\n");
93c7cb6c
SS		 634
635 assert_csr_loaded(dev_priv);
636}
637
0a9d2bed 638void skl_enable_dc6(struct drm_i915_private *dev_priv)
93c7cb6c 639{
93c7cb6c 640 assert_can_enable_dc6(dev_priv);
74b4f371
SK		 641
642 DRM_DEBUG_KMS("Enabling DC6\n");
643
13ae3a0d
ID		 644 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
645
f75a1985
SS		 646}
647
0a9d2bed 648void skl_disable_dc6(struct drm_i915_private *dev_priv)
f75a1985 649{
74b4f371
SK		 650 DRM_DEBUG_KMS("Disabling DC6\n");
651
13ae3a0d 652 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
f75a1985
SS		 653}
654
c6782b76
ID		 655static void
656gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
657 struct i915_power_well *power_well)
658{
659 enum skl_disp_power_wells power_well_id = power_well->data;
660 u32 val;
661 u32 mask;
662
663 mask = SKL_POWER_WELL_REQ(power_well_id);
664
665 val = I915_READ(HSW_PWR_WELL_KVMR);
666 if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
667 power_well->name))
668 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
669
670 val = I915_READ(HSW_PWR_WELL_BIOS);
671 val |= I915_READ(HSW_PWR_WELL_DEBUG);
672
673 if (!(val & mask))
674 return;
675
676 /*
677 * DMC is known to force on the request bits for power well 1 on SKL
678 * and BXT and the misc IO power well on SKL but we don't expect any
679 * other request bits to be set, so WARN for those.
680 */
681 if (power_well_id == SKL_DISP_PW_1 ||
80dbe997
ID		 682 ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
683 power_well_id == SKL_DISP_PW_MISC_IO))
c6782b76
ID		 684 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
685 "by DMC\n", power_well->name);
686 else
687 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
688 power_well->name);
689
690 I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
691 I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
692}
693
94dd5138
S		 694static void skl_set_power_well(struct drm_i915_private *dev_priv,
695 struct i915_power_well *power_well, bool enable)
696{
697 uint32_t tmp, fuse_status;
698 uint32_t req_mask, state_mask;
2a51835f 699 bool is_enabled, enable_requested, check_fuse_status = false;
94dd5138
S		 700
701 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
702 fuse_status = I915_READ(SKL_FUSE_STATUS);
703
704 switch (power_well->data) {
705 case SKL_DISP_PW_1:
706 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
707 SKL_FUSE_PG0_DIST_STATUS), 1)) {
708 DRM_ERROR("PG0 not enabled\n");
709 return;
710 }
711 break;
712 case SKL_DISP_PW_2:
713 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
714 DRM_ERROR("PG1 in disabled state\n");
715 return;
716 }
717 break;
718 case SKL_DISP_PW_DDI_A_E:
719 case SKL_DISP_PW_DDI_B:
720 case SKL_DISP_PW_DDI_C:
721 case SKL_DISP_PW_DDI_D:
722 case SKL_DISP_PW_MISC_IO:
723 break;
724 default:
725 WARN(1, "Unknown power well %lu\n", power_well->data);
726 return;
727 }
728
729 req_mask = SKL_POWER_WELL_REQ(power_well->data);
2a51835f 730 enable_requested = tmp & req_mask;
94dd5138 731 state_mask = SKL_POWER_WELL_STATE(power_well->data);
2a51835f 732 is_enabled = tmp & state_mask;
94dd5138 733
aae8ba84
VS		 734 if (!enable && enable_requested)
735 skl_power_well_pre_disable(dev_priv, power_well);
736
94dd5138 737 if (enable) {
2a51835f 738 if (!enable_requested) {
dc174300
SS		 739 WARN((tmp & state_mask) &&
740 !I915_READ(HSW_PWR_WELL_BIOS),
741 "Invalid for power well status to be enabled, unless done by the BIOS, \
742 when request is to disable!\n");
94dd5138 743 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
94dd5138
S		 744 }
745
2a51835f 746 if (!is_enabled) {
510e6fdd 747 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
94dd5138
S		 748 check_fuse_status = true;
749 }
750 } else {
2a51835f 751 if (enable_requested) {
4a76f295
ID		 752 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
753 POSTING_READ(HSW_PWR_WELL_DRIVER);
754 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
94dd5138 755 }
c6782b76 756
5f304c87 757 if (IS_GEN9(dev_priv))
c6782b76 758 gen9_sanitize_power_well_requests(dev_priv, power_well);
94dd5138
S		 759 }
760
1d963afa
ID		 761 if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
762 1))
763 DRM_ERROR("%s %s timeout\n",
764 power_well->name, enable ? "enable" : "disable");
765
94dd5138
S		 766 if (check_fuse_status) {
767 if (power_well->data == SKL_DISP_PW_1) {
768 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
769 SKL_FUSE_PG1_DIST_STATUS), 1))
770 DRM_ERROR("PG1 distributing status timeout\n");
771 } else if (power_well->data == SKL_DISP_PW_2) {
772 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
773 SKL_FUSE_PG2_DIST_STATUS), 1))
774 DRM_ERROR("PG2 distributing status timeout\n");
775 }
776 }
d14c0343
DL		 777
778 if (enable && !is_enabled)
779 skl_power_well_post_enable(dev_priv, power_well);
94dd5138
S		 780}
781
9c065a7d
DV		 782static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
783 struct i915_power_well *power_well)
784{
785 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
786
787 /*
788 * We're taking over the BIOS, so clear any requests made by it since
789 * the driver is in charge now.
790 */
791 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
792 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
793}
794
795static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
796 struct i915_power_well *power_well)
797{
798 hsw_set_power_well(dev_priv, power_well, true);
799}
800
801static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
802 struct i915_power_well *power_well)
803{
804 hsw_set_power_well(dev_priv, power_well, false);
805}
806
94dd5138
S		 807static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
808 struct i915_power_well *power_well)
809{
810 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
811 SKL_POWER_WELL_STATE(power_well->data);
812
813 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
814}
815
816static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
817 struct i915_power_well *power_well)
818{
819 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
820
821 /* Clear any request made by BIOS as driver is taking over */
822 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
823}
824
825static void skl_power_well_enable(struct drm_i915_private *dev_priv,
826 struct i915_power_well *power_well)
827{
828 skl_set_power_well(dev_priv, power_well, true);
829}
830
831static void skl_power_well_disable(struct drm_i915_private *dev_priv,
832 struct i915_power_well *power_well)
833{
834 skl_set_power_well(dev_priv, power_well, false);
835}
836
9c8d0b8e
ID		 837static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
838{
839 enum skl_disp_power_wells power_well_id = power_well->data;
840
841 return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
842}
843
844static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
845 struct i915_power_well *power_well)
846{
847 enum skl_disp_power_wells power_well_id = power_well->data;
848 struct i915_power_well *cmn_a_well;
849
850 if (power_well_id == BXT_DPIO_CMN_BC) {
851 /*
852 * We need to copy the GRC calibration value from the eDP PHY,
853 * so make sure it's powered up.
854 */
855 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
856 intel_power_well_get(dev_priv, cmn_a_well);
857 }
858
859 bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
860
861 if (power_well_id == BXT_DPIO_CMN_BC)
862 intel_power_well_put(dev_priv, cmn_a_well);
863}
864
865static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
866 struct i915_power_well *power_well)
867{
868 bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
869}
870
871static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
872 struct i915_power_well *power_well)
873{
874 return bxt_ddi_phy_is_enabled(dev_priv,
875 bxt_power_well_to_phy(power_well));
876}
877
878static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
879 struct i915_power_well *power_well)
880{
881 if (power_well->count > 0)
882 bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
883 else
884 bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
885}
886
887
888static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
889{
890 struct i915_power_well *power_well;
891
892 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
893 if (power_well->count > 0)
894 bxt_ddi_phy_verify_state(dev_priv,
895 bxt_power_well_to_phy(power_well));
896
897 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
898 if (power_well->count > 0)
899 bxt_ddi_phy_verify_state(dev_priv,
900 bxt_power_well_to_phy(power_well));
901}
902
9f836f90
PJ		 903static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
904 struct i915_power_well *power_well)
905{
906 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
907}
908
18a8067c
VS		 909static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
910{
911 u32 tmp = I915_READ(DBUF_CTL);
912
913 WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
914 (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
915 "Unexpected DBuf power power state (0x%08x)\n", tmp);
916}
917
9f836f90
PJ		 918static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
919 struct i915_power_well *power_well)
920{
5b773eb4 921 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
adc7f04b 922
342be926
VS		 923 WARN_ON(dev_priv->cdclk_freq !=
924 dev_priv->display.get_display_clock_speed(dev_priv->dev));
925
18a8067c
VS		 926 gen9_assert_dbuf_enabled(dev_priv);
927
342be926 928 if (IS_BROXTON(dev_priv))
9c8d0b8e 929 bxt_verify_ddi_phy_power_wells(dev_priv);
9f836f90
PJ		 930}
931
932static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
933 struct i915_power_well *power_well)
934{
f74ed08d
ID		 935 if (!dev_priv->csr.dmc_payload)
936 return;
937
a37baf3b 938 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
9f836f90 939 skl_enable_dc6(dev_priv);
a37baf3b 940 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
9f836f90
PJ		 941 gen9_enable_dc5(dev_priv);
942}
943
944static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
945 struct i915_power_well *power_well)
946{
a37baf3b
ID		 947 if (power_well->count > 0)
948 gen9_dc_off_power_well_enable(dev_priv, power_well);
949 else
950 gen9_dc_off_power_well_disable(dev_priv, power_well);
9f836f90
PJ		 951}
952
9c065a7d
DV		 953static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
954 struct i915_power_well *power_well)
955{
956}
957
958static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
959 struct i915_power_well *power_well)
960{
961 return true;
962}
963
964static void vlv_set_power_well(struct drm_i915_private *dev_priv,
965 struct i915_power_well *power_well, bool enable)
966{
967 enum punit_power_well power_well_id = power_well->data;
968 u32 mask;
969 u32 state;
970 u32 ctrl;
971
972 mask = PUNIT_PWRGT_MASK(power_well_id);
973 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
974 PUNIT_PWRGT_PWR_GATE(power_well_id);
975
976 mutex_lock(&dev_priv->rps.hw_lock);
977
978#define COND \
979 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
980
981 if (COND)
982 goto out;
983
984 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
985 ctrl &= ~mask;
986 ctrl |= state;
987 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
988
989 if (wait_for(COND, 100))
7e35ab88 990 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
DV		 991 state,
992 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
993
994#undef COND
995
996out:
997 mutex_unlock(&dev_priv->rps.hw_lock);
998}
999
1000static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
1001 struct i915_power_well *power_well)
1002{
1003 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
1004}
1005
1006static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1007 struct i915_power_well *power_well)
1008{
1009 vlv_set_power_well(dev_priv, power_well, true);
1010}
1011
1012static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1013 struct i915_power_well *power_well)
1014{
1015 vlv_set_power_well(dev_priv, power_well, false);
1016}
1017
1018static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1019 struct i915_power_well *power_well)
1020{
1021 int power_well_id = power_well->data;
1022 bool enabled = false;
1023 u32 mask;
1024 u32 state;
1025 u32 ctrl;
1026
1027 mask = PUNIT_PWRGT_MASK(power_well_id);
1028 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
1029
1030 mutex_lock(&dev_priv->rps.hw_lock);
1031
1032 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1033 /*
1034 * We only ever set the power-on and power-gate states, anything
1035 * else is unexpected.
1036 */
1037 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
1038 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
1039 if (state == ctrl)
1040 enabled = true;
1041
1042 /*
1043 * A transient state at this point would mean some unexpected party
1044 * is poking at the power controls too.
1045 */
1046 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1047 WARN_ON(ctrl != state);
1048
1049 mutex_unlock(&dev_priv->rps.hw_lock);
1050
1051 return enabled;
1052}
1053
766078df
VS		 1054static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1055{
1056 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
1057
1058 /*
1059 * Disable trickle feed and enable pnd deadline calculation
1060 */
1061 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1062 I915_WRITE(CBR1_VLV, 0);
19ab4ed3
VS		 1063
1064 WARN_ON(dev_priv->rawclk_freq == 0);
1065
1066 I915_WRITE(RAWCLK_FREQ_VLV,
1067 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
766078df
VS		 1068}
1069
2be7d540 1070static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
9c065a7d 1071{
5a8fbb7d
VS		 1072 enum pipe pipe;
1073
1074 /*
1075 * Enable the CRI clock source so we can get at the
1076 * display and the reference clock for VGA
1077 * hotplug / manual detection. Supposedly DSI also
1078 * needs the ref clock up and running.
1079 *
1080 * CHV DPLL B/C have some issues if VGA mode is enabled.
1081 */
1082 for_each_pipe(dev_priv->dev, pipe) {
1083 u32 val = I915_READ(DPLL(pipe));
1084
1085 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1086 if (pipe != PIPE_A)
1087 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1088
1089 I915_WRITE(DPLL(pipe), val);
1090 }
9c065a7d 1091
766078df
VS		 1092 vlv_init_display_clock_gating(dev_priv);
1093
9c065a7d
DV		 1094 spin_lock_irq(&dev_priv->irq_lock);
1095 valleyview_enable_display_irqs(dev_priv);
1096 spin_unlock_irq(&dev_priv->irq_lock);
1097
1098 /*
1099 * During driver initialization/resume we can avoid restoring the
1100 * part of the HW/SW state that will be inited anyway explicitly.
1101 */
1102 if (dev_priv->power_domains.initializing)
1103 return;
1104
b963291c 1105 intel_hpd_init(dev_priv);
9c065a7d
DV		 1106
1107 i915_redisable_vga_power_on(dev_priv->dev);
1108}
1109
2be7d540
VS		 1110static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1111{
1112 spin_lock_irq(&dev_priv->irq_lock);
1113 valleyview_disable_display_irqs(dev_priv);
1114 spin_unlock_irq(&dev_priv->irq_lock);
1115
2230fde8
VS		 1116 /* make sure we're done processing display irqs */
1117 synchronize_irq(dev_priv->dev->irq);
1118
78597996 1119 intel_power_sequencer_reset(dev_priv);
2be7d540
VS		 1120}
1121
1122static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1123 struct i915_power_well *power_well)
1124{
1125 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1126
1127 vlv_set_power_well(dev_priv, power_well, true);
1128
1129 vlv_display_power_well_init(dev_priv);
1130}
1131
9c065a7d
DV		 1132static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1133 struct i915_power_well *power_well)
1134{
1135 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1136
2be7d540 1137 vlv_display_power_well_deinit(dev_priv);
9c065a7d
DV		 1138
1139 vlv_set_power_well(dev_priv, power_well, false);
9c065a7d
DV		 1140}
1141
1142static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1143 struct i915_power_well *power_well)
1144{
1145 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1146
5a8fbb7d 1147 /* since ref/cri clock was enabled */
9c065a7d
DV		 1148 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1149
1150 vlv_set_power_well(dev_priv, power_well, true);
1151
1152 /*
1153 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1154 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1155 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1156 * b. The other bits such as sfr settings / modesel may all
1157 * be set to 0.
1158 *
1159 * This should only be done on init and resume from S3 with
1160 * both PLLs disabled, or we risk losing DPIO and PLL
1161 * synchronization.
1162 */
1163 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1164}
1165
1166static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1167 struct i915_power_well *power_well)
1168{
1169 enum pipe pipe;
1170
1171 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1172
1173 for_each_pipe(dev_priv, pipe)
1174 assert_pll_disabled(dev_priv, pipe);
1175
1176 /* Assert common reset */
1177 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1178
1179 vlv_set_power_well(dev_priv, power_well, false);
1180}
1181
30142273
VS		 1182#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1183
1184static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1185 int power_well_id)
1186{
1187 struct i915_power_domains *power_domains = &dev_priv->power_domains;
30142273
VS		 1188 int i;
1189
fc17f227
ID		 1190 for (i = 0; i < power_domains->power_well_count; i++) {
1191 struct i915_power_well *power_well;
1192
1193 power_well = &power_domains->power_wells[i];
30142273
VS		 1194 if (power_well->data == power_well_id)
1195 return power_well;
1196 }
1197
1198 return NULL;
1199}
1200
1201#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1202
1203static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1204{
1205 struct i915_power_well *cmn_bc =
1206 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1207 struct i915_power_well *cmn_d =
1208 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1209 u32 phy_control = dev_priv->chv_phy_control;
1210 u32 phy_status = 0;
3be60de9 1211 u32 phy_status_mask = 0xffffffff;
30142273
VS		 1212 u32 tmp;
1213
3be60de9
VS		 1214 /*
1215 * The BIOS can leave the PHY is some weird state
1216 * where it doesn't fully power down some parts.
1217 * Disable the asserts until the PHY has been fully
1218 * reset (ie. the power well has been disabled at
1219 * least once).
1220 */
1221 if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1222 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1223 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1224 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1225 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1226 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1227 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1228
1229 if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1230 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1231 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1232 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1233
30142273
VS		 1234 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1235 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1236
1237 /* this assumes override is only used to enable lanes */
1238 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1239 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1240
1241 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1242 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1243
1244 /* CL1 is on whenever anything is on in either channel */
1245 if (BITS_SET(phy_control,
1246 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1247 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1248 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1249
1250 /*
1251 * The DPLLB check accounts for the pipe B + port A usage
1252 * with CL2 powered up but all the lanes in the second channel
1253 * powered down.
1254 */
1255 if (BITS_SET(phy_control,
1256 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1257 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1258 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1259
1260 if (BITS_SET(phy_control,
1261 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1262 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1263 if (BITS_SET(phy_control,
1264 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1265 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1266
1267 if (BITS_SET(phy_control,
1268 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1269 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1270 if (BITS_SET(phy_control,
1271 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1272 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1273 }
1274
1275 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1276 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1277
1278 /* this assumes override is only used to enable lanes */
1279 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1280 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1281
1282 if (BITS_SET(phy_control,
1283 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1284 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1285
1286 if (BITS_SET(phy_control,
1287 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1288 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1289 if (BITS_SET(phy_control,
1290 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1291 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1292 }
1293
3be60de9
VS		 1294 phy_status &= phy_status_mask;
1295
30142273
VS		 1296 /*
1297 * The PHY may be busy with some initial calibration and whatnot,
1298 * so the power state can take a while to actually change.
1299 */
3be60de9 1300 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
30142273
VS		 1301 WARN(phy_status != tmp,
1302 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1303 tmp, phy_status, dev_priv->chv_phy_control);
1304}
1305
1306#undef BITS_SET
1307
9c065a7d
DV		 1308static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1309 struct i915_power_well *power_well)
1310{
1311 enum dpio_phy phy;
e0fce78f
VS		 1312 enum pipe pipe;
1313 uint32_t tmp;
9c065a7d
DV		 1314
1315 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1316 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1317
e0fce78f
VS		 1318 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1319 pipe = PIPE_A;
9c065a7d 1320 phy = DPIO_PHY0;
e0fce78f
VS		 1321 } else {
1322 pipe = PIPE_C;
9c065a7d 1323 phy = DPIO_PHY1;
e0fce78f 1324 }
5a8fbb7d
VS		 1325
1326 /* since ref/cri clock was enabled */
9c065a7d
DV		 1327 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1328 vlv_set_power_well(dev_priv, power_well, true);
1329
1330 /* Poll for phypwrgood signal */
1331 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1332 DRM_ERROR("Display PHY %d is not power up\n", phy);
1333
e0fce78f
VS		 1334 mutex_lock(&dev_priv->sb_lock);
1335
1336 /* Enable dynamic power down */
1337 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
ee279218
VS		 1338 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1339 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
e0fce78f
VS		 1340 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1341
1342 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1343 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1344 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1345 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
3e288786
VS		 1346 } else {
1347 /*
1348 * Force the non-existing CL2 off. BXT does this
1349 * too, so maybe it saves some power even though
1350 * CL2 doesn't exist?
1351 */
1352 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1353 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1354 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
e0fce78f
VS		 1355 }
1356
1357 mutex_unlock(&dev_priv->sb_lock);
1358
70722468
VS		 1359 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1360 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
e0fce78f
VS		 1361
1362 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1363 phy, dev_priv->chv_phy_control);
30142273
VS		 1364
1365 assert_chv_phy_status(dev_priv);
9c065a7d
DV		 1366}
1367
1368static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1369 struct i915_power_well *power_well)
1370{
1371 enum dpio_phy phy;
1372
1373 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1374 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1375
1376 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1377 phy = DPIO_PHY0;
1378 assert_pll_disabled(dev_priv, PIPE_A);
1379 assert_pll_disabled(dev_priv, PIPE_B);
1380 } else {
1381 phy = DPIO_PHY1;
1382 assert_pll_disabled(dev_priv, PIPE_C);
1383 }
1384
70722468
VS		 1385 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1386 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
9c065a7d
DV		 1387
1388 vlv_set_power_well(dev_priv, power_well, false);
e0fce78f
VS		 1389
1390 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1391 phy, dev_priv->chv_phy_control);
30142273 1392
3be60de9
VS		 1393 /* PHY is fully reset now, so we can enable the PHY state asserts */
1394 dev_priv->chv_phy_assert[phy] = true;
1395
30142273 1396 assert_chv_phy_status(dev_priv);
e0fce78f
VS		 1397}
1398
6669e39f
VS		 1399static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1400 enum dpio_channel ch, bool override, unsigned int mask)
1401{
1402 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1403 u32 reg, val, expected, actual;
1404
3be60de9
VS		 1405 /*
1406 * The BIOS can leave the PHY is some weird state
1407 * where it doesn't fully power down some parts.
1408 * Disable the asserts until the PHY has been fully
1409 * reset (ie. the power well has been disabled at
1410 * least once).
1411 */
1412 if (!dev_priv->chv_phy_assert[phy])
1413 return;
1414
6669e39f
VS		 1415 if (ch == DPIO_CH0)
1416 reg = _CHV_CMN_DW0_CH0;
1417 else
1418 reg = _CHV_CMN_DW6_CH1;
1419
1420 mutex_lock(&dev_priv->sb_lock);
1421 val = vlv_dpio_read(dev_priv, pipe, reg);
1422 mutex_unlock(&dev_priv->sb_lock);
1423
1424 /*
1425 * This assumes !override is only used when the port is disabled.
1426 * All lanes should power down even without the override when
1427 * the port is disabled.
1428 */
1429 if (!override || mask == 0xf) {
1430 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1431 /*
1432 * If CH1 common lane is not active anymore
1433 * (eg. for pipe B DPLL) the entire channel will
1434 * shut down, which causes the common lane registers
1435 * to read as 0. That means we can't actually check
1436 * the lane power down status bits, but as the entire
1437 * register reads as 0 it's a good indication that the
1438 * channel is indeed entirely powered down.
1439 */
1440 if (ch == DPIO_CH1 && val == 0)
1441 expected = 0;
1442 } else if (mask != 0x0) {
1443 expected = DPIO_ANYDL_POWERDOWN;
1444 } else {
1445 expected = 0;
1446 }
1447
1448 if (ch == DPIO_CH0)
1449 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1450 else
1451 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1452 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1453
1454 WARN(actual != expected,
1455 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1456 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1457 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1458 reg, val);
1459}
1460
b0b33846
VS		 1461bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1462 enum dpio_channel ch, bool override)
1463{
1464 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1465 bool was_override;
1466
1467 mutex_lock(&power_domains->lock);
1468
1469 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1470
1471 if (override == was_override)
1472 goto out;
1473
1474 if (override)
1475 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1476 else
1477 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1478
1479 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1480
1481 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1482 phy, ch, dev_priv->chv_phy_control);
1483
30142273
VS		 1484 assert_chv_phy_status(dev_priv);
1485
b0b33846
VS		 1486out:
1487 mutex_unlock(&power_domains->lock);
1488
1489 return was_override;
1490}
1491
e0fce78f
VS		 1492void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1493 bool override, unsigned int mask)
1494{
1495 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1496 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1497 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1498 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1499
1500 mutex_lock(&power_domains->lock);
1501
1502 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1503 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1504
1505 if (override)
1506 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1507 else
1508 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1509
1510 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1511
1512 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1513 phy, ch, mask, dev_priv->chv_phy_control);
1514
30142273
VS		 1515 assert_chv_phy_status(dev_priv);
1516
6669e39f
VS		 1517 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1518
e0fce78f 1519 mutex_unlock(&power_domains->lock);
9c065a7d
DV		 1520}
1521
1522static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1523 struct i915_power_well *power_well)
1524{
1525 enum pipe pipe = power_well->data;
1526 bool enabled;
1527 u32 state, ctrl;
1528
1529 mutex_lock(&dev_priv->rps.hw_lock);
1530
1531 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1532 /*
1533 * We only ever set the power-on and power-gate states, anything
1534 * else is unexpected.
1535 */
1536 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1537 enabled = state == DP_SSS_PWR_ON(pipe);
1538
1539 /*
1540 * A transient state at this point would mean some unexpected party
1541 * is poking at the power controls too.
1542 */
1543 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1544 WARN_ON(ctrl << 16 != state);
1545
1546 mutex_unlock(&dev_priv->rps.hw_lock);
1547
1548 return enabled;
1549}
1550
1551static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1552 struct i915_power_well *power_well,
1553 bool enable)
1554{
1555 enum pipe pipe = power_well->data;
1556 u32 state;
1557 u32 ctrl;
1558
1559 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1560
1561 mutex_lock(&dev_priv->rps.hw_lock);
1562
1563#define COND \
1564 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1565
1566 if (COND)
1567 goto out;
1568
1569 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1570 ctrl &= ~DP_SSC_MASK(pipe);
1571 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1572 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1573
1574 if (wait_for(COND, 100))
7e35ab88 1575 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
DV		 1576 state,
1577 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1578
1579#undef COND
1580
1581out:
1582 mutex_unlock(&dev_priv->rps.hw_lock);
1583}
1584
1585static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1586 struct i915_power_well *power_well)
1587{
8fcd5cd8
VS		 1588 WARN_ON_ONCE(power_well->data != PIPE_A);
1589
9c065a7d
DV		 1590 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1591}
1592
1593static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1594 struct i915_power_well *power_well)
1595{
8fcd5cd8 1596 WARN_ON_ONCE(power_well->data != PIPE_A);
9c065a7d
DV		 1597
1598 chv_set_pipe_power_well(dev_priv, power_well, true);
afd6275d 1599
2be7d540 1600 vlv_display_power_well_init(dev_priv);
9c065a7d
DV		 1601}
1602
1603static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1604 struct i915_power_well *power_well)
1605{
8fcd5cd8
VS		 1606 WARN_ON_ONCE(power_well->data != PIPE_A);
1607
2be7d540 1608 vlv_display_power_well_deinit(dev_priv);
afd6275d 1609
9c065a7d
DV		 1610 chv_set_pipe_power_well(dev_priv, power_well, false);
1611}
1612
09731280
ID		 1613static void
1614__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1615 enum intel_display_power_domain domain)
1616{
1617 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1618 struct i915_power_well *power_well;
1619 int i;
1620
b409ca95
ID		 1621 for_each_power_well(i, power_well, BIT(domain), power_domains)
1622 intel_power_well_get(dev_priv, power_well);
09731280
ID		 1623
1624 power_domains->domain_use_count[domain]++;
1625}
1626
e4e7684f
DV		 1627/**
1628 * intel_display_power_get - grab a power domain reference
1629 * @dev_priv: i915 device instance
1630 * @domain: power domain to reference
1631 *
1632 * This function grabs a power domain reference for @domain and ensures that the
1633 * power domain and all its parents are powered up. Therefore users should only
1634 * grab a reference to the innermost power domain they need.
1635 *
1636 * Any power domain reference obtained by this function must have a symmetric
1637 * call to intel_display_power_put() to release the reference again.
1638 */
9c065a7d
DV		 1639void intel_display_power_get(struct drm_i915_private *dev_priv,
1640 enum intel_display_power_domain domain)
1641{
09731280 1642 struct i915_power_domains *power_domains = &dev_priv->power_domains;
9c065a7d
DV		 1643
1644 intel_runtime_pm_get(dev_priv);
1645
09731280
ID		 1646 mutex_lock(&power_domains->lock);
1647
1648 __intel_display_power_get_domain(dev_priv, domain);
1649
1650 mutex_unlock(&power_domains->lock);
1651}
1652
1653/**
1654 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1655 * @dev_priv: i915 device instance
1656 * @domain: power domain to reference
1657 *
1658 * This function grabs a power domain reference for @domain and ensures that the
1659 * power domain and all its parents are powered up. Therefore users should only
1660 * grab a reference to the innermost power domain they need.
1661 *
1662 * Any power domain reference obtained by this function must have a symmetric
1663 * call to intel_display_power_put() to release the reference again.
1664 */
1665bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1666 enum intel_display_power_domain domain)
1667{
1668 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1669 bool is_enabled;
1670
1671 if (!intel_runtime_pm_get_if_in_use(dev_priv))
1672 return false;
9c065a7d
DV		 1673
1674 mutex_lock(&power_domains->lock);
1675
09731280
ID		 1676 if (__intel_display_power_is_enabled(dev_priv, domain)) {
1677 __intel_display_power_get_domain(dev_priv, domain);
1678 is_enabled = true;
1679 } else {
1680 is_enabled = false;
9c065a7d
DV		 1681 }
1682
9c065a7d 1683 mutex_unlock(&power_domains->lock);
09731280
ID		 1684
1685 if (!is_enabled)
1686 intel_runtime_pm_put(dev_priv);
1687
1688 return is_enabled;
9c065a7d
DV		 1689}
1690
e4e7684f
DV		 1691/**
1692 * intel_display_power_put - release a power domain reference
1693 * @dev_priv: i915 device instance
1694 * @domain: power domain to reference
1695 *
1696 * This function drops the power domain reference obtained by
1697 * intel_display_power_get() and might power down the corresponding hardware
1698 * block right away if this is the last reference.
1699 */
9c065a7d
DV		 1700void intel_display_power_put(struct drm_i915_private *dev_priv,
1701 enum intel_display_power_domain domain)
1702{
1703 struct i915_power_domains *power_domains;
1704 struct i915_power_well *power_well;
1705 int i;
1706
1707 power_domains = &dev_priv->power_domains;
1708
1709 mutex_lock(&power_domains->lock);
1710
11c86db8
DS		 1711 WARN(!power_domains->domain_use_count[domain],
1712 "Use count on domain %s is already zero\n",
1713 intel_display_power_domain_str(domain));
9c065a7d
DV		 1714 power_domains->domain_use_count[domain]--;
1715
b409ca95
ID		 1716 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
1717 intel_power_well_put(dev_priv, power_well);
9c065a7d
DV		 1718
1719 mutex_unlock(&power_domains->lock);
1720
1721 intel_runtime_pm_put(dev_priv);
1722}
1723
9d0996b5
VS		 1724#define HSW_DISPLAY_POWER_DOMAINS ( \
1725 BIT(POWER_DOMAIN_PIPE_B) | \
1726 BIT(POWER_DOMAIN_PIPE_C) | \
1727 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1728 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1729 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1730 BIT(POWER_DOMAIN_TRANSCODER_A) | \
1731 BIT(POWER_DOMAIN_TRANSCODER_B) | \
1732 BIT(POWER_DOMAIN_TRANSCODER_C) | \
6331a704
PJ		 1733 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1734 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1735 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
9d0996b5
VS		 1736 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
1737 BIT(POWER_DOMAIN_VGA) | \
1738 BIT(POWER_DOMAIN_AUDIO) | \
9c065a7d
DV		 1739 BIT(POWER_DOMAIN_INIT))
1740
9d0996b5
VS		 1741#define BDW_DISPLAY_POWER_DOMAINS ( \
1742 BIT(POWER_DOMAIN_PIPE_B) | \
1743 BIT(POWER_DOMAIN_PIPE_C) | \
1744 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1745 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1746 BIT(POWER_DOMAIN_TRANSCODER_A) | \
1747 BIT(POWER_DOMAIN_TRANSCODER_B) | \
1748 BIT(POWER_DOMAIN_TRANSCODER_C) | \
1749 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1750 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1751 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1752 BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
1753 BIT(POWER_DOMAIN_VGA) | \
1754 BIT(POWER_DOMAIN_AUDIO) | \
9c065a7d
DV		 1755 BIT(POWER_DOMAIN_INIT))
1756
465ac0c6
VS		 1757#define VLV_DISPLAY_POWER_DOMAINS ( \
1758 BIT(POWER_DOMAIN_PIPE_A) | \
1759 BIT(POWER_DOMAIN_PIPE_B) | \
1760 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1761 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1762 BIT(POWER_DOMAIN_TRANSCODER_A) | \
1763 BIT(POWER_DOMAIN_TRANSCODER_B) | \
1764 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1765 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1766 BIT(POWER_DOMAIN_PORT_DSI) | \
1767 BIT(POWER_DOMAIN_PORT_CRT) | \
1768 BIT(POWER_DOMAIN_VGA) | \
1769 BIT(POWER_DOMAIN_AUDIO) | \
1770 BIT(POWER_DOMAIN_AUX_B) | \
1771 BIT(POWER_DOMAIN_AUX_C) | \
1772 BIT(POWER_DOMAIN_GMBUS) | \
1773 BIT(POWER_DOMAIN_INIT))
9c065a7d
DV		 1774
1775#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6331a704
PJ		 1776 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1777 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
9c065a7d 1778 BIT(POWER_DOMAIN_PORT_CRT) | \
1407121a
S		 1779 BIT(POWER_DOMAIN_AUX_B) | \
1780 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1781 BIT(POWER_DOMAIN_INIT))
1782
1783#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6331a704 1784 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1407121a 1785 BIT(POWER_DOMAIN_AUX_B) | \
9c065a7d
DV		 1786 BIT(POWER_DOMAIN_INIT))
1787
1788#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6331a704 1789 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1407121a 1790 BIT(POWER_DOMAIN_AUX_B) | \
9c065a7d
DV		 1791 BIT(POWER_DOMAIN_INIT))
1792
1793#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6331a704 1794 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a 1795 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1796 BIT(POWER_DOMAIN_INIT))
1797
1798#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6331a704 1799 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a 1800 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1801 BIT(POWER_DOMAIN_INIT))
1802
465ac0c6
VS		 1803#define CHV_DISPLAY_POWER_DOMAINS ( \
1804 BIT(POWER_DOMAIN_PIPE_A) | \
1805 BIT(POWER_DOMAIN_PIPE_B) | \
1806 BIT(POWER_DOMAIN_PIPE_C) | \
1807 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1808 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1809 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1810 BIT(POWER_DOMAIN_TRANSCODER_A) | \
1811 BIT(POWER_DOMAIN_TRANSCODER_B) | \
1812 BIT(POWER_DOMAIN_TRANSCODER_C) | \
1813 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1814 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1815 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1816 BIT(POWER_DOMAIN_PORT_DSI) | \
1817 BIT(POWER_DOMAIN_VGA) | \
1818 BIT(POWER_DOMAIN_AUDIO) | \
1819 BIT(POWER_DOMAIN_AUX_B) | \
1820 BIT(POWER_DOMAIN_AUX_C) | \
1821 BIT(POWER_DOMAIN_AUX_D) | \
1822 BIT(POWER_DOMAIN_GMBUS) | \
1823 BIT(POWER_DOMAIN_INIT))
1824
9c065a7d 1825#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6331a704
PJ		 1826 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1827 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a
S		 1828 BIT(POWER_DOMAIN_AUX_B) | \
1829 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1830 BIT(POWER_DOMAIN_INIT))
1831
1832#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6331a704 1833 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1407121a 1834 BIT(POWER_DOMAIN_AUX_D) | \
9c065a7d
DV		 1835 BIT(POWER_DOMAIN_INIT))
1836
9c065a7d
DV		 1837static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1838 .sync_hw = i9xx_always_on_power_well_noop,
1839 .enable = i9xx_always_on_power_well_noop,
1840 .disable = i9xx_always_on_power_well_noop,
1841 .is_enabled = i9xx_always_on_power_well_enabled,
1842};
1843
1844static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1845 .sync_hw = chv_pipe_power_well_sync_hw,
1846 .enable = chv_pipe_power_well_enable,
1847 .disable = chv_pipe_power_well_disable,
1848 .is_enabled = chv_pipe_power_well_enabled,
1849};
1850
1851static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1852 .sync_hw = vlv_power_well_sync_hw,
1853 .enable = chv_dpio_cmn_power_well_enable,
1854 .disable = chv_dpio_cmn_power_well_disable,
1855 .is_enabled = vlv_power_well_enabled,
1856};
1857
1858static struct i915_power_well i9xx_always_on_power_well[] = {
1859 {
1860 .name = "always-on",
1861 .always_on = 1,
1862 .domains = POWER_DOMAIN_MASK,
1863 .ops = &i9xx_always_on_power_well_ops,
1864 },
1865};
1866
1867static const struct i915_power_well_ops hsw_power_well_ops = {
1868 .sync_hw = hsw_power_well_sync_hw,
1869 .enable = hsw_power_well_enable,
1870 .disable = hsw_power_well_disable,
1871 .is_enabled = hsw_power_well_enabled,
1872};
1873
94dd5138
S		 1874static const struct i915_power_well_ops skl_power_well_ops = {
1875 .sync_hw = skl_power_well_sync_hw,
1876 .enable = skl_power_well_enable,
1877 .disable = skl_power_well_disable,
1878 .is_enabled = skl_power_well_enabled,
1879};
1880
9f836f90
PJ		 1881static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1882 .sync_hw = gen9_dc_off_power_well_sync_hw,
1883 .enable = gen9_dc_off_power_well_enable,
1884 .disable = gen9_dc_off_power_well_disable,
1885 .is_enabled = gen9_dc_off_power_well_enabled,
1886};
1887
9c8d0b8e
ID		 1888static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1889 .sync_hw = bxt_dpio_cmn_power_well_sync_hw,
1890 .enable = bxt_dpio_cmn_power_well_enable,
1891 .disable = bxt_dpio_cmn_power_well_disable,
1892 .is_enabled = bxt_dpio_cmn_power_well_enabled,
1893};
1894
9c065a7d
DV		 1895static struct i915_power_well hsw_power_wells[] = {
1896 {
1897 .name = "always-on",
1898 .always_on = 1,
998bd66a 1899 .domains = POWER_DOMAIN_MASK,
9c065a7d
DV		 1900 .ops = &i9xx_always_on_power_well_ops,
1901 },
1902 {
1903 .name = "display",
1904 .domains = HSW_DISPLAY_POWER_DOMAINS,
1905 .ops = &hsw_power_well_ops,
1906 },
1907};
1908
1909static struct i915_power_well bdw_power_wells[] = {
1910 {
1911 .name = "always-on",
1912 .always_on = 1,
998bd66a 1913 .domains = POWER_DOMAIN_MASK,
9c065a7d
DV		 1914 .ops = &i9xx_always_on_power_well_ops,
1915 },
1916 {
1917 .name = "display",
1918 .domains = BDW_DISPLAY_POWER_DOMAINS,
1919 .ops = &hsw_power_well_ops,
1920 },
1921};
1922
1923static const struct i915_power_well_ops vlv_display_power_well_ops = {
1924 .sync_hw = vlv_power_well_sync_hw,
1925 .enable = vlv_display_power_well_enable,
1926 .disable = vlv_display_power_well_disable,
1927 .is_enabled = vlv_power_well_enabled,
1928};
1929
1930static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1931 .sync_hw = vlv_power_well_sync_hw,
1932 .enable = vlv_dpio_cmn_power_well_enable,
1933 .disable = vlv_dpio_cmn_power_well_disable,
1934 .is_enabled = vlv_power_well_enabled,
1935};
1936
1937static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1938 .sync_hw = vlv_power_well_sync_hw,
1939 .enable = vlv_power_well_enable,
1940 .disable = vlv_power_well_disable,
1941 .is_enabled = vlv_power_well_enabled,
1942};
1943
1944static struct i915_power_well vlv_power_wells[] = {
1945 {
1946 .name = "always-on",
1947 .always_on = 1,
998bd66a 1948 .domains = POWER_DOMAIN_MASK,
9c065a7d 1949 .ops = &i9xx_always_on_power_well_ops,
56fcfd63 1950 .data = PUNIT_POWER_WELL_ALWAYS_ON,
9c065a7d
DV		 1951 },
1952 {
1953 .name = "display",
1954 .domains = VLV_DISPLAY_POWER_DOMAINS,
1955 .data = PUNIT_POWER_WELL_DISP2D,
1956 .ops = &vlv_display_power_well_ops,
1957 },
1958 {
1959 .name = "dpio-tx-b-01",
1960 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1961 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1962 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1963 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1964 .ops = &vlv_dpio_power_well_ops,
1965 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1966 },
1967 {
1968 .name = "dpio-tx-b-23",
1969 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1970 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1971 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1972 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1973 .ops = &vlv_dpio_power_well_ops,
1974 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1975 },
1976 {
1977 .name = "dpio-tx-c-01",
1978 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1979 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1980 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1981 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1982 .ops = &vlv_dpio_power_well_ops,
1983 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1984 },
1985 {
1986 .name = "dpio-tx-c-23",
1987 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1988 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1989 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1990 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1991 .ops = &vlv_dpio_power_well_ops,
1992 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1993 },
1994 {
1995 .name = "dpio-common",
1996 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1997 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1998 .ops = &vlv_dpio_cmn_power_well_ops,
1999 },
2000};
2001
2002static struct i915_power_well chv_power_wells[] = {
2003 {
2004 .name = "always-on",
2005 .always_on = 1,
998bd66a 2006 .domains = POWER_DOMAIN_MASK,
9c065a7d
DV		 2007 .ops = &i9xx_always_on_power_well_ops,
2008 },
9c065a7d
DV		 2009 {
2010 .name = "display",
baa4e575 2011 /*
fde61e4b
VS		 2012 * Pipe A power well is the new disp2d well. Pipe B and C
2013 * power wells don't actually exist. Pipe A power well is
2014 * required for any pipe to work.
baa4e575 2015 */
465ac0c6 2016 .domains = CHV_DISPLAY_POWER_DOMAINS,
9c065a7d
DV		 2017 .data = PIPE_A,
2018 .ops = &chv_pipe_power_well_ops,
2019 },
9c065a7d
DV		 2020 {
2021 .name = "dpio-common-bc",
71849b67 2022 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
9c065a7d
DV		 2023 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2024 .ops = &chv_dpio_cmn_power_well_ops,
2025 },
2026 {
2027 .name = "dpio-common-d",
71849b67 2028 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
9c065a7d
DV		 2029 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
2030 .ops = &chv_dpio_cmn_power_well_ops,
2031 },
9c065a7d
DV		 2032};
2033
5aefb239
SS		 2034bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2035 int power_well_id)
2036{
2037 struct i915_power_well *power_well;
2038 bool ret;
2039
2040 power_well = lookup_power_well(dev_priv, power_well_id);
2041 ret = power_well->ops->is_enabled(dev_priv, power_well);
2042
2043 return ret;
2044}
2045
94dd5138
S		 2046static struct i915_power_well skl_power_wells[] = {
2047 {
2048 .name = "always-on",
2049 .always_on = 1,
998bd66a 2050 .domains = POWER_DOMAIN_MASK,
94dd5138 2051 .ops = &i9xx_always_on_power_well_ops,
56fcfd63 2052 .data = SKL_DISP_PW_ALWAYS_ON,
94dd5138
S		 2053 },
2054 {
2055 .name = "power well 1",
4a76f295
ID		 2056 /* Handled by the DMC firmware */
2057 .domains = 0,
94dd5138
S		 2058 .ops = &skl_power_well_ops,
2059 .data = SKL_DISP_PW_1,
2060 },
2061 {
2062 .name = "MISC IO power well",
4a76f295
ID		 2063 /* Handled by the DMC firmware */
2064 .domains = 0,
94dd5138
S		 2065 .ops = &skl_power_well_ops,
2066 .data = SKL_DISP_PW_MISC_IO,
2067 },
9f836f90
PJ		 2068 {
2069 .name = "DC off",
2070 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2071 .ops = &gen9_dc_off_power_well_ops,
2072 .data = SKL_DISP_PW_DC_OFF,
2073 },
94dd5138
S		 2074 {
2075 .name = "power well 2",
2076 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2077 .ops = &skl_power_well_ops,
2078 .data = SKL_DISP_PW_2,
2079 },
2080 {
2081 .name = "DDI A/E power well",
2082 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
2083 .ops = &skl_power_well_ops,
2084 .data = SKL_DISP_PW_DDI_A_E,
2085 },
2086 {
2087 .name = "DDI B power well",
2088 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
2089 .ops = &skl_power_well_ops,
2090 .data = SKL_DISP_PW_DDI_B,
2091 },
2092 {
2093 .name = "DDI C power well",
2094 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
2095 .ops = &skl_power_well_ops,
2096 .data = SKL_DISP_PW_DDI_C,
2097 },
2098 {
2099 .name = "DDI D power well",
2100 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
2101 .ops = &skl_power_well_ops,
2102 .data = SKL_DISP_PW_DDI_D,
2103 },
2104};
2105
0b4a2a36
S		 2106static struct i915_power_well bxt_power_wells[] = {
2107 {
2108 .name = "always-on",
2109 .always_on = 1,
998bd66a 2110 .domains = POWER_DOMAIN_MASK,
0b4a2a36
S		 2111 .ops = &i9xx_always_on_power_well_ops,
2112 },
2113 {
2114 .name = "power well 1",
d7d7c9ee 2115 .domains = 0,
0b4a2a36
S		 2116 .ops = &skl_power_well_ops,
2117 .data = SKL_DISP_PW_1,
2118 },
9f836f90
PJ		 2119 {
2120 .name = "DC off",
2121 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2122 .ops = &gen9_dc_off_power_well_ops,
2123 .data = SKL_DISP_PW_DC_OFF,
2124 },
0b4a2a36
S		 2125 {
2126 .name = "power well 2",
2127 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2128 .ops = &skl_power_well_ops,
2129 .data = SKL_DISP_PW_2,
9f836f90 2130 },
9c8d0b8e
ID		 2131 {
2132 .name = "dpio-common-a",
2133 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2134 .ops = &bxt_dpio_cmn_power_well_ops,
2135 .data = BXT_DPIO_CMN_A,
2136 },
2137 {
2138 .name = "dpio-common-bc",
2139 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2140 .ops = &bxt_dpio_cmn_power_well_ops,
2141 .data = BXT_DPIO_CMN_BC,
2142 },
0b4a2a36
S		 2143};
2144
1b0e3a04
ID		 2145static int
2146sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2147 int disable_power_well)
2148{
2149 if (disable_power_well >= 0)
2150 return !!disable_power_well;
2151
1b0e3a04
ID		 2152 return 1;
2153}
2154
a37baf3b
ID		 2155static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2156 int enable_dc)
2157{
2158 uint32_t mask;
2159 int requested_dc;
2160 int max_dc;
2161
2162 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2163 max_dc = 2;
2164 mask = 0;
2165 } else if (IS_BROXTON(dev_priv)) {
2166 max_dc = 1;
2167 /*
2168 * DC9 has a separate HW flow from the rest of the DC states,
2169 * not depending on the DMC firmware. It's needed by system
2170 * suspend/resume, so allow it unconditionally.
2171 */
2172 mask = DC_STATE_EN_DC9;
2173 } else {
2174 max_dc = 0;
2175 mask = 0;
2176 }
2177
66e2c4c3
ID		 2178 if (!i915.disable_power_well)
2179 max_dc = 0;
2180
a37baf3b
ID		 2181 if (enable_dc >= 0 && enable_dc <= max_dc) {
2182 requested_dc = enable_dc;
2183 } else if (enable_dc == -1) {
2184 requested_dc = max_dc;
2185 } else if (enable_dc > max_dc && enable_dc <= 2) {
2186 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2187 enable_dc, max_dc);
2188 requested_dc = max_dc;
2189 } else {
2190 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2191 requested_dc = max_dc;
2192 }
2193
2194 if (requested_dc > 1)
2195 mask |= DC_STATE_EN_UPTO_DC6;
2196 if (requested_dc > 0)
2197 mask |= DC_STATE_EN_UPTO_DC5;
2198
2199 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2200
2201 return mask;
2202}
2203
9c065a7d
DV		 2204#define set_power_wells(power_domains, __power_wells) ({ \
2205 (power_domains)->power_wells = (__power_wells); \
2206 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
2207})
2208
e4e7684f
DV		 2209/**
2210 * intel_power_domains_init - initializes the power domain structures
2211 * @dev_priv: i915 device instance
2212 *
2213 * Initializes the power domain structures for @dev_priv depending upon the
2214 * supported platform.
2215 */
9c065a7d
DV		 2216int intel_power_domains_init(struct drm_i915_private *dev_priv)
2217{
2218 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2219
1b0e3a04
ID		 2220 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2221 i915.disable_power_well);
a37baf3b
ID		 2222 dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2223 i915.enable_dc);
1b0e3a04 2224
f0ab43e6
VS		 2225 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2226
9c065a7d
DV		 2227 mutex_init(&power_domains->lock);
2228
2229 /*
2230 * The enabling order will be from lower to higher indexed wells,
2231 * the disabling order is reversed.
2232 */
2d1fe073 2233 if (IS_HASWELL(dev_priv)) {
9c065a7d 2234 set_power_wells(power_domains, hsw_power_wells);
2d1fe073 2235 } else if (IS_BROADWELL(dev_priv)) {
9c065a7d 2236 set_power_wells(power_domains, bdw_power_wells);
2d1fe073 2237 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
94dd5138 2238 set_power_wells(power_domains, skl_power_wells);
2d1fe073 2239 } else if (IS_BROXTON(dev_priv)) {
0b4a2a36 2240 set_power_wells(power_domains, bxt_power_wells);
2d1fe073 2241 } else if (IS_CHERRYVIEW(dev_priv)) {
9c065a7d 2242 set_power_wells(power_domains, chv_power_wells);
2d1fe073 2243 } else if (IS_VALLEYVIEW(dev_priv)) {
9c065a7d
DV		 2244 set_power_wells(power_domains, vlv_power_wells);
2245 } else {
2246 set_power_wells(power_domains, i9xx_always_on_power_well);
2247 }
2248
2249 return 0;
2250}
2251
e4e7684f
DV		 2252/**
2253 * intel_power_domains_fini - finalizes the power domain structures
2254 * @dev_priv: i915 device instance
2255 *
2256 * Finalizes the power domain structures for @dev_priv depending upon the
2257 * supported platform. This function also disables runtime pm and ensures that
2258 * the device stays powered up so that the driver can be reloaded.
2259 */
f458ebbc 2260void intel_power_domains_fini(struct drm_i915_private *dev_priv)
9c065a7d 2261{
25b181b4
ID		 2262 struct device *device = &dev_priv->dev->pdev->dev;
2263
aabee1bb
ID		 2264 /*
2265 * The i915.ko module is still not prepared to be loaded when
f458ebbc 2266 * the power well is not enabled, so just enable it in case
aabee1bb
ID		 2267 * we're going to unload/reload.
2268 * The following also reacquires the RPM reference the core passed
2269 * to the driver during loading, which is dropped in
2270 * intel_runtime_pm_enable(). We have to hand back the control of the
2271 * device to the core with this reference held.
2272 */
f458ebbc 2273 intel_display_set_init_power(dev_priv, true);
d314cd43
ID		 2274
2275 /* Remove the refcount we took to keep power well support disabled. */
2276 if (!i915.disable_power_well)
2277 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
25b181b4
ID		 2278
2279 /*
2280 * Remove the refcount we took in intel_runtime_pm_enable() in case
2281 * the platform doesn't support runtime PM.
2282 */
2283 if (!HAS_RUNTIME_PM(dev_priv))
2284 pm_runtime_put(device);
9c065a7d
DV		 2285}
2286
30eade12 2287static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
9c065a7d
DV		 2288{
2289 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2290 struct i915_power_well *power_well;
2291 int i;
2292
2293 mutex_lock(&power_domains->lock);
2294 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2295 power_well->ops->sync_hw(dev_priv, power_well);
2296 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2297 power_well);
2298 }
2299 mutex_unlock(&power_domains->lock);
2300}
2301
70c2c184
VS		 2302static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2303{
2304 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2305 POSTING_READ(DBUF_CTL);
2306
2307 udelay(10);
2308
2309 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2310 DRM_ERROR("DBuf power enable timeout\n");
2311}
2312
2313static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2314{
2315 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2316 POSTING_READ(DBUF_CTL);
2317
2318 udelay(10);
2319
2320 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2321 DRM_ERROR("DBuf power disable timeout!\n");
2322}
2323
73dfc227 2324static void skl_display_core_init(struct drm_i915_private *dev_priv,
443a93ac 2325 bool resume)
73dfc227
ID		 2326{
2327 struct i915_power_domains *power_domains = &dev_priv->power_domains;
443a93ac 2328 struct i915_power_well *well;
73dfc227
ID		 2329 uint32_t val;
2330
d26fa1d5
ID		 2331 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2332
73dfc227
ID		 2333 /* enable PCH reset handshake */
2334 val = I915_READ(HSW_NDE_RSTWRN_OPT);
2335 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2336
2337 /* enable PG1 and Misc I/O */
2338 mutex_lock(&power_domains->lock);
443a93ac
ID		 2339
2340 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2341 intel_power_well_enable(dev_priv, well);
2342
2343 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2344 intel_power_well_enable(dev_priv, well);
2345
73dfc227
ID		 2346 mutex_unlock(&power_domains->lock);
2347
73dfc227
ID		 2348 skl_init_cdclk(dev_priv);
2349
70c2c184
VS		 2350 gen9_dbuf_enable(dev_priv);
2351
9f7eb31a 2352 if (resume && dev_priv->csr.dmc_payload)
2abc525b 2353 intel_csr_load_program(dev_priv);
73dfc227
ID		 2354}
2355
2356static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2357{
2358 struct i915_power_domains *power_domains = &dev_priv->power_domains;
443a93ac 2359 struct i915_power_well *well;
73dfc227 2360
d26fa1d5
ID		 2361 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2362
70c2c184
VS		 2363 gen9_dbuf_disable(dev_priv);
2364
73dfc227
ID		 2365 skl_uninit_cdclk(dev_priv);
2366
2367 /* The spec doesn't call for removing the reset handshake flag */
2368 /* disable PG1 and Misc I/O */
443a93ac 2369
73dfc227 2370 mutex_lock(&power_domains->lock);
443a93ac
ID		 2371
2372 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2373 intel_power_well_disable(dev_priv, well);
2374
2375 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2376 intel_power_well_disable(dev_priv, well);
2377
73dfc227
ID		 2378 mutex_unlock(&power_domains->lock);
2379}
2380
d7d7c9ee
ID		 2381void bxt_display_core_init(struct drm_i915_private *dev_priv,
2382 bool resume)
2383{
2384 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2385 struct i915_power_well *well;
2386 uint32_t val;
2387
2388 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2389
2390 /*
2391 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2392 * or else the reset will hang because there is no PCH to respond.
2393 * Move the handshake programming to initialization sequence.
2394 * Previously was left up to BIOS.
2395 */
2396 val = I915_READ(HSW_NDE_RSTWRN_OPT);
2397 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2398 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2399
2400 /* Enable PG1 */
2401 mutex_lock(&power_domains->lock);
2402
2403 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2404 intel_power_well_enable(dev_priv, well);
2405
2406 mutex_unlock(&power_domains->lock);
2407
324513c0 2408 bxt_init_cdclk(dev_priv);
70c2c184
VS		 2409
2410 gen9_dbuf_enable(dev_priv);
2411
d7d7c9ee
ID		 2412 if (resume && dev_priv->csr.dmc_payload)
2413 intel_csr_load_program(dev_priv);
2414}
2415
2416void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2417{
2418 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2419 struct i915_power_well *well;
2420
2421 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2422
70c2c184
VS		 2423 gen9_dbuf_disable(dev_priv);
2424
324513c0 2425 bxt_uninit_cdclk(dev_priv);
d7d7c9ee
ID		 2426
2427 /* The spec doesn't call for removing the reset handshake flag */
2428
2429 /* Disable PG1 */
2430 mutex_lock(&power_domains->lock);
2431
2432 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2433 intel_power_well_disable(dev_priv, well);
2434
2435 mutex_unlock(&power_domains->lock);
2436}
2437
70722468
VS		 2438static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2439{
2440 struct i915_power_well *cmn_bc =
2441 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2442 struct i915_power_well *cmn_d =
2443 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2444
2445 /*
2446 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2447 * workaround never ever read DISPLAY_PHY_CONTROL, and
2448 * instead maintain a shadow copy ourselves. Use the actual
e0fce78f
VS		 2449 * power well state and lane status to reconstruct the
2450 * expected initial value.
70722468
VS		 2451 */
2452 dev_priv->chv_phy_control =
bc284542
VS		 2453 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2454 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
e0fce78f
VS		 2455 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2456 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2457 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2458
2459 /*
2460 * If all lanes are disabled we leave the override disabled
2461 * with all power down bits cleared to match the state we
2462 * would use after disabling the port. Otherwise enable the
2463 * override and set the lane powerdown bits accding to the
2464 * current lane status.
2465 */
2466 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2467 uint32_t status = I915_READ(DPLL(PIPE_A));
2468 unsigned int mask;
2469
2470 mask = status & DPLL_PORTB_READY_MASK;
2471 if (mask == 0xf)
2472 mask = 0x0;
2473 else
2474 dev_priv->chv_phy_control |=
2475 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2476
2477 dev_priv->chv_phy_control |=
2478 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2479
2480 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2481 if (mask == 0xf)
2482 mask = 0x0;
2483 else
2484 dev_priv->chv_phy_control |=
2485 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2486
2487 dev_priv->chv_phy_control |=
2488 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2489
70722468 2490 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
3be60de9
VS		 2491
2492 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2493 } else {
2494 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
e0fce78f
VS		 2495 }
2496
2497 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2498 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2499 unsigned int mask;
2500
2501 mask = status & DPLL_PORTD_READY_MASK;
2502
2503 if (mask == 0xf)
2504 mask = 0x0;
2505 else
2506 dev_priv->chv_phy_control |=
2507 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2508
2509 dev_priv->chv_phy_control |=
2510 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2511
70722468 2512 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
3be60de9
VS		 2513
2514 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2515 } else {
2516 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
e0fce78f
VS		 2517 }
2518
2519 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2520
2521 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2522 dev_priv->chv_phy_control);
70722468
VS		 2523}
2524
9c065a7d
DV		 2525static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2526{
2527 struct i915_power_well *cmn =
2528 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2529 struct i915_power_well *disp2d =
2530 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2531
9c065a7d 2532 /* If the display might be already active skip this */
5d93a6e5
VS		 2533 if (cmn->ops->is_enabled(dev_priv, cmn) &&
2534 disp2d->ops->is_enabled(dev_priv, disp2d) &&
9c065a7d
DV		 2535 I915_READ(DPIO_CTL) & DPIO_CMNRST)
2536 return;
2537
2538 DRM_DEBUG_KMS("toggling display PHY side reset\n");
2539
2540 /* cmnlane needs DPLL registers */
2541 disp2d->ops->enable(dev_priv, disp2d);
2542
2543 /*
2544 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2545 * Need to assert and de-assert PHY SB reset by gating the
2546 * common lane power, then un-gating it.
2547 * Simply ungating isn't enough to reset the PHY enough to get
2548 * ports and lanes running.
2549 */
2550 cmn->ops->disable(dev_priv, cmn);
2551}
2552
e4e7684f
DV		 2553/**
2554 * intel_power_domains_init_hw - initialize hardware power domain state
2555 * @dev_priv: i915 device instance
14bb2c11 2556 * @resume: Called from resume code paths or not
e4e7684f
DV		 2557 *
2558 * This function initializes the hardware power domain state and enables all
2559 * power domains using intel_display_set_init_power().
2560 */
73dfc227 2561void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
9c065a7d
DV		 2562{
2563 struct drm_device *dev = dev_priv->dev;
2564 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2565
2566 power_domains->initializing = true;
2567
73dfc227
ID		 2568 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2569 skl_display_core_init(dev_priv, resume);
d7d7c9ee
ID		 2570 } else if (IS_BROXTON(dev)) {
2571 bxt_display_core_init(dev_priv, resume);
73dfc227 2572 } else if (IS_CHERRYVIEW(dev)) {
770effb1 2573 mutex_lock(&power_domains->lock);
70722468 2574 chv_phy_control_init(dev_priv);
770effb1 2575 mutex_unlock(&power_domains->lock);
70722468 2576 } else if (IS_VALLEYVIEW(dev)) {
9c065a7d
DV		 2577 mutex_lock(&power_domains->lock);
2578 vlv_cmnlane_wa(dev_priv);
2579 mutex_unlock(&power_domains->lock);
2580 }
2581
2582 /* For now, we need the power well to be always enabled. */
2583 intel_display_set_init_power(dev_priv, true);
d314cd43
ID		 2584 /* Disable power support if the user asked so. */
2585 if (!i915.disable_power_well)
2586 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
30eade12 2587 intel_power_domains_sync_hw(dev_priv);
9c065a7d
DV		 2588 power_domains->initializing = false;
2589}
2590
73dfc227
ID		 2591/**
2592 * intel_power_domains_suspend - suspend power domain state
2593 * @dev_priv: i915 device instance
2594 *
2595 * This function prepares the hardware power domain state before entering
2596 * system suspend. It must be paired with intel_power_domains_init_hw().
2597 */
2598void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2599{
d314cd43
ID		 2600 /*
2601 * Even if power well support was disabled we still want to disable
2602 * power wells while we are system suspended.
2603 */
2604 if (!i915.disable_power_well)
2605 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2622d79b
ID		 2606
2607 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2608 skl_display_core_uninit(dev_priv);
d7d7c9ee
ID		 2609 else if (IS_BROXTON(dev_priv))
2610 bxt_display_core_uninit(dev_priv);
73dfc227
ID		 2611}
2612
e4e7684f
DV		 2613/**
2614 * intel_runtime_pm_get - grab a runtime pm reference
2615 * @dev_priv: i915 device instance
2616 *
2617 * This function grabs a device-level runtime pm reference (mostly used for GEM
2618 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2619 *
2620 * Any runtime pm reference obtained by this function must have a symmetric
2621 * call to intel_runtime_pm_put() to release the reference again.
2622 */
9c065a7d
DV		 2623void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2624{
2625 struct drm_device *dev = dev_priv->dev;
2626 struct device *device = &dev->pdev->dev;
2627
9c065a7d 2628 pm_runtime_get_sync(device);
1f814dac
ID		 2629
2630 atomic_inc(&dev_priv->pm.wakeref_count);
c9b8846a 2631 assert_rpm_wakelock_held(dev_priv);
9c065a7d
DV		 2632}
2633
09731280
ID		 2634/**
2635 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2636 * @dev_priv: i915 device instance
2637 *
2638 * This function grabs a device-level runtime pm reference if the device is
2639 * already in use and ensures that it is powered up.
2640 *
2641 * Any runtime pm reference obtained by this function must have a symmetric
2642 * call to intel_runtime_pm_put() to release the reference again.
2643 */
2644bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2645{
2646 struct drm_device *dev = dev_priv->dev;
2647 struct device *device = &dev->pdev->dev;
09731280 2648
135dc79e
CW		 2649 if (IS_ENABLED(CONFIG_PM)) {
2650 int ret = pm_runtime_get_if_in_use(device);
09731280 2651
135dc79e
CW		 2652 /*
2653 * In cases runtime PM is disabled by the RPM core and we get
2654 * an -EINVAL return value we are not supposed to call this
2655 * function, since the power state is undefined. This applies
2656 * atm to the late/early system suspend/resume handlers.
2657 */
2658 WARN_ON_ONCE(ret < 0);
2659 if (ret <= 0)
2660 return false;
2661 }
09731280
ID		 2662
2663 atomic_inc(&dev_priv->pm.wakeref_count);
2664 assert_rpm_wakelock_held(dev_priv);
2665
2666 return true;
2667}
2668
e4e7684f
DV		 2669/**
2670 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2671 * @dev_priv: i915 device instance
2672 *
2673 * This function grabs a device-level runtime pm reference (mostly used for GEM
2674 * code to ensure the GTT or GT is on).
2675 *
2676 * It will _not_ power up the device but instead only check that it's powered
2677 * on. Therefore it is only valid to call this functions from contexts where
2678 * the device is known to be powered up and where trying to power it up would
2679 * result in hilarity and deadlocks. That pretty much means only the system
2680 * suspend/resume code where this is used to grab runtime pm references for
2681 * delayed setup down in work items.
2682 *
2683 * Any runtime pm reference obtained by this function must have a symmetric
2684 * call to intel_runtime_pm_put() to release the reference again.
2685 */
9c065a7d
DV		 2686void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2687{
2688 struct drm_device *dev = dev_priv->dev;
2689 struct device *device = &dev->pdev->dev;
2690
c9b8846a 2691 assert_rpm_wakelock_held(dev_priv);
9c065a7d 2692 pm_runtime_get_noresume(device);
1f814dac
ID		 2693
2694 atomic_inc(&dev_priv->pm.wakeref_count);
9c065a7d
DV		 2695}
2696
e4e7684f
DV		 2697/**
2698 * intel_runtime_pm_put - release a runtime pm reference
2699 * @dev_priv: i915 device instance
2700 *
2701 * This function drops the device-level runtime pm reference obtained by
2702 * intel_runtime_pm_get() and might power down the corresponding
2703 * hardware block right away if this is the last reference.
2704 */
9c065a7d
DV		 2705void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2706{
2707 struct drm_device *dev = dev_priv->dev;
2708 struct device *device = &dev->pdev->dev;
2709
542db3cd 2710 assert_rpm_wakelock_held(dev_priv);
2b19efeb
ID		 2711 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2712 atomic_inc(&dev_priv->pm.atomic_seq);
1f814dac 2713
9c065a7d
DV		 2714 pm_runtime_mark_last_busy(device);
2715 pm_runtime_put_autosuspend(device);
2716}
2717
e4e7684f
DV		 2718/**
2719 * intel_runtime_pm_enable - enable runtime pm
2720 * @dev_priv: i915 device instance
2721 *
2722 * This function enables runtime pm at the end of the driver load sequence.
2723 *
2724 * Note that this function does currently not enable runtime pm for the
2725 * subordinate display power domains. That is only done on the first modeset
2726 * using intel_display_set_init_power().
2727 */
f458ebbc 2728void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
9c065a7d
DV		 2729{
2730 struct drm_device *dev = dev_priv->dev;
2731 struct device *device = &dev->pdev->dev;
2732
cbc68dc9
ID		 2733 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2734 pm_runtime_mark_last_busy(device);
2735
25b181b4
ID		 2736 /*
2737 * Take a permanent reference to disable the RPM functionality and drop
2738 * it only when unloading the driver. Use the low level get/put helpers,
2739 * so the driver's own RPM reference tracking asserts also work on
2740 * platforms without RPM support.
2741 */
cbc68dc9
ID		 2742 if (!HAS_RUNTIME_PM(dev)) {
2743 pm_runtime_dont_use_autosuspend(device);
25b181b4 2744 pm_runtime_get_sync(device);
cbc68dc9
ID		 2745 } else {
2746 pm_runtime_use_autosuspend(device);
2747 }
9c065a7d 2748
aabee1bb
ID		 2749 /*
2750 * The core calls the driver load handler with an RPM reference held.
2751 * We drop that here and will reacquire it during unloading in
2752 * intel_power_domains_fini().
2753 */
9c065a7d
DV		 2754 pm_runtime_put_autosuspend(device);
2755}
2756
Linux kernel - Deliverables
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