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Merge remote-tracking branch 'xen-tip/linux-next'
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7 32#include <drm/drmP.h>
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ea5b213a 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945
JB		 38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
4d9194de 56static const char * const tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
53abb679 66#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
ce6feabd 67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
f0f59a00 77 i915_reg_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
19d415a2 84 * intel_sdvo_get_capabilities()
e2f0ba97 85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
5fa7ac9c 100 uint16_t hotplug_active;
cc68c81a 101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
55bc60db 107 bool color_range_auto;
e953fd7b 108
7949dd47
VS		 109 /**
110 * HDMI user specified aspect ratio
111 */
112 enum hdmi_picture_aspect aspect_ratio;
113
e2f0ba97
JB		 114 /**
115 * This is set if we're going to treat the device as TV-out.
116 *
117 * While we have these nice friendly flags for output types that ought
118 * to decide this for us, the S-Video output on our HDMI+S-Video card
119 * shows up as RGB1 (VGA).
120 */
121 bool is_tv;
122
2a5c0832 123 enum port port;
eef4eacb 124
ce6feabd 125 /* This is for current tv format name */
40039750 126 int tv_format_index;
ce6feabd 127
e2f0ba97
JB		 128 /**
129 * This is set if we treat the device as HDMI, instead of DVI.
130 */
131 bool is_hdmi;
da79de97
CW		 132 bool has_hdmi_monitor;
133 bool has_hdmi_audio;
abedc077 134 bool rgb_quant_range_selectable;
12682a97 135
7086c87f 136 /**
6c9547ff
CW		 137 * This is set if we detect output of sdvo device as LVDS and
138 * have a valid fixed mode to use with the panel.
7086c87f
ML		 139 */
140 bool is_lvds;
e2f0ba97 141
12682a97 142 /**
143 * This is sdvo fixed pannel mode pointer
144 */
145 struct drm_display_mode *sdvo_lvds_fixed_mode;
146
c751ce4f 147 /* DDC bus used by this SDVO encoder */
e2f0ba97 148 uint8_t ddc_bus;
e751823d
EE		 149
150 /*
151 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
152 */
153 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 154};
155
156struct intel_sdvo_connector {
615fb93f
CW		 157 struct intel_connector base;
158
14571b4c
ZW		 159 /* Mark the type of connector */
160 uint16_t output_flag;
161
c3e5f67b 162 enum hdmi_force_audio force_audio;
7f36e7ed 163
14571b4c 164 /* This contains all current supported TV format */
40039750 165 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 166 int format_supported_num;
c5521706 167 struct drm_property *tv_format;
14571b4c 168
b9219c5e 169 /* add the property for the SDVO-TV */
c5521706
CW		 170 struct drm_property *left;
171 struct drm_property *right;
172 struct drm_property *top;
173 struct drm_property *bottom;
174 struct drm_property *hpos;
175 struct drm_property *vpos;
176 struct drm_property *contrast;
177 struct drm_property *saturation;
178 struct drm_property *hue;
179 struct drm_property *sharpness;
180 struct drm_property *flicker_filter;
181 struct drm_property *flicker_filter_adaptive;
182 struct drm_property *flicker_filter_2d;
183 struct drm_property *tv_chroma_filter;
184 struct drm_property *tv_luma_filter;
e044218a 185 struct drm_property *dot_crawl;
b9219c5e
ZY		 186
187 /* add the property for the SDVO-TV/LVDS */
c5521706 188 struct drm_property *brightness;
b9219c5e
ZY		 189
190 /* Add variable to record current setting for the above property */
191 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 192
b9219c5e
ZY		 193 /* this is to get the range of margin.*/
194 u32 max_hscan, max_vscan;
195 u32 max_hpos, cur_hpos;
196 u32 max_vpos, cur_vpos;
197 u32 cur_brightness, max_brightness;
198 u32 cur_contrast, max_contrast;
199 u32 cur_saturation, max_saturation;
200 u32 cur_hue, max_hue;
c5521706
CW		 201 u32 cur_sharpness, max_sharpness;
202 u32 cur_flicker_filter, max_flicker_filter;
203 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
204 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
205 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
206 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 207 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 208};
209
8aca63aa 210static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 211{
8aca63aa 212 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 213}
214
df0e9248
CW		 215static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
216{
8aca63aa 217 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 218}
219
615fb93f
CW		 220static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
221{
222 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
223}
224
fb7a46f3 225static bool
ea5b213a 226intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 227static bool
228intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector,
230 int type);
231static bool
232intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
233 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 234
79e53945
JB		 235/**
236 * Writes the SDVOB or SDVOC with the given value, but always writes both
237 * SDVOB and SDVOC to work around apparent hardware issues (according to
238 * comments in the BIOS).
239 */
ea5b213a 240static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 241{
4ef69c7a 242 struct drm_device *dev = intel_sdvo->base.base.dev;
fac5e23e 243 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 244 u32 bval = val, cval = val;
245 int i;
246
2a5c0832 247 if (HAS_PCH_SPLIT(dev_priv)) {
ea5b213a 248 I915_WRITE(intel_sdvo->sdvo_reg, val);
abab6311 249 POSTING_READ(intel_sdvo->sdvo_reg);
e8504ee2
VS		 250 /*
251 * HW workaround, need to write this twice for issue
252 * that may result in first write getting masked.
253 */
254 if (HAS_PCH_IBX(dev)) {
255 I915_WRITE(intel_sdvo->sdvo_reg, val);
256 POSTING_READ(intel_sdvo->sdvo_reg);
257 }
461ed3ca
ZY		 258 return;
259 }
260
2a5c0832 261 if (intel_sdvo->port == PORT_B)
e2debe91
PZ		 262 cval = I915_READ(GEN3_SDVOC);
263 else
264 bval = I915_READ(GEN3_SDVOB);
265
79e53945
JB		 266 /*
267 * Write the registers twice for luck. Sometimes,
268 * writing them only once doesn't appear to 'stick'.
269 * The BIOS does this too. Yay, magic
270 */
271 for (i = 0; i < 2; i++)
272 {
e2debe91 273 I915_WRITE(GEN3_SDVOB, bval);
abab6311 274 POSTING_READ(GEN3_SDVOB);
e2debe91 275 I915_WRITE(GEN3_SDVOC, cval);
abab6311 276 POSTING_READ(GEN3_SDVOC);
79e53945
JB		 277 }
278}
279
32aad86f 280static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 281{
79e53945
JB		 282 struct i2c_msg msgs[] = {
283 {
e957d772 284 .addr = intel_sdvo->slave_addr,
79e53945
JB		 285 .flags = 0,
286 .len = 1,
e957d772 287 .buf = &addr,
79e53945
JB		 288 },
289 {
e957d772 290 .addr = intel_sdvo->slave_addr,
79e53945
JB		 291 .flags = I2C_M_RD,
292 .len = 1,
e957d772 293 .buf = ch,
79e53945
JB		 294 }
295 };
32aad86f 296 int ret;
79e53945 297
f899fc64 298 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 299 return true;
79e53945 300
8a4c47f3 301 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 302 return false;
303}
304
79e53945
JB		 305#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
306/** Mapping of command numbers to names, for debug output */
005568be 307static const struct _sdvo_cmd_name {
e2f0ba97 308 u8 cmd;
2e88e40b 309 const char *name;
79e53945 310} sdvo_cmd_names[] = {
0206e353
AJ		 311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
354
355 /* Add the op code for SDVO enhancements */
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
400
401 /* HDMI op code */
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
413 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
414 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
415 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
416 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
417 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
418 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
419 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
420 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
421 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 422};
423
2a5c0832 424#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
79e53945 425
ea5b213a 426static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 427 const void *args, int args_len)
79e53945 428{
84fcb469
DV		 429 int i, pos = 0;
430#define BUF_LEN 256
431 char buffer[BUF_LEN];
432
433#define BUF_PRINT(args...) \
434 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
435
79e53945 436
84fcb469
DV		 437 for (i = 0; i < args_len; i++) {
438 BUF_PRINT("%02X ", ((u8 *)args)[i]);
439 }
440 for (; i < 8; i++) {
441 BUF_PRINT(" ");
442 }
04ad327f 443 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 444 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 445 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 446 break;
447 }
448 }
84fcb469
DV		 449 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
450 BUF_PRINT("(%02X)", cmd);
451 }
452 BUG_ON(pos >= BUF_LEN - 1);
453#undef BUF_PRINT
454#undef BUF_LEN
455
456 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 457}
79e53945 458
4d9194de 459static const char * const cmd_status_names[] = {
e957d772
CW		 460 "Power on",
461 "Success",
462 "Not supported",
463 "Invalid arg",
464 "Pending",
465 "Target not specified",
466 "Scaling not supported"
467};
468
32aad86f
CW		 469static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
470 const void *args, int args_len)
79e53945 471{
3bf3f452
BW		 472 u8 *buf, status;
473 struct i2c_msg *msgs;
474 int i, ret = true;
475
0274df3e 476 /* Would be simpler to allocate both in one go ? */
5c67eeb6 477 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 478 if (!buf)
479 return false;
480
481 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 482 if (!msgs) {
483 kfree(buf);
3bf3f452 484 return false;
0274df3e 485 }
79e53945 486
ea5b213a 487 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 488
489 for (i = 0; i < args_len; i++) {
e957d772
CW		 490 msgs[i].addr = intel_sdvo->slave_addr;
491 msgs[i].flags = 0;
492 msgs[i].len = 2;
493 msgs[i].buf = buf + 2 *i;
494 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
495 buf[2*i + 1] = ((u8*)args)[i];
496 }
497 msgs[i].addr = intel_sdvo->slave_addr;
498 msgs[i].flags = 0;
499 msgs[i].len = 2;
500 msgs[i].buf = buf + 2*i;
501 buf[2*i + 0] = SDVO_I2C_OPCODE;
502 buf[2*i + 1] = cmd;
503
504 /* the following two are to read the response */
505 status = SDVO_I2C_CMD_STATUS;
506 msgs[i+1].addr = intel_sdvo->slave_addr;
507 msgs[i+1].flags = 0;
508 msgs[i+1].len = 1;
509 msgs[i+1].buf = &status;
510
511 msgs[i+2].addr = intel_sdvo->slave_addr;
512 msgs[i+2].flags = I2C_M_RD;
513 msgs[i+2].len = 1;
514 msgs[i+2].buf = &status;
515
516 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
517 if (ret < 0) {
518 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 519 ret = false;
520 goto out;
e957d772
CW		 521 }
522 if (ret != i+3) {
523 /* failure in I2C transfer */
524 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 525 ret = false;
e957d772
CW		 526 }
527
3bf3f452
BW		 528out:
529 kfree(msgs);
530 kfree(buf);
531 return ret;
79e53945
JB		 532}
533
b5c616a7
CW		 534static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
535 void *response, int response_len)
79e53945 536{
fc37381c 537 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 538 u8 status;
84fcb469
DV		 539 int i, pos = 0;
540#define BUF_LEN 256
541 char buffer[BUF_LEN];
79e53945 542
d121a5d2 543
b5c616a7
CW		 544 /*
545 * The documentation states that all commands will be
546 * processed within 15µs, and that we need only poll
547 * the status byte a maximum of 3 times in order for the
548 * command to be complete.
549 *
550 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 551 *
552 * Also beware that the first response by many devices is to
553 * reply PENDING and stall for time. TVs are notorious for
554 * requiring longer than specified to complete their replies.
555 * Originally (in the DDX long ago), the delay was only ever 15ms
556 * with an additional delay of 30ms applied for TVs added later after
557 * many experiments. To accommodate both sets of delays, we do a
558 * sequence of slow checks if the device is falling behind and fails
559 * to reply within 5*15µs.
b5c616a7 560 */
d121a5d2
CW		 561 if (!intel_sdvo_read_byte(intel_sdvo,
562 SDVO_I2C_CMD_STATUS,
563 &status))
564 goto log_fail;
565
1ad87e72 566 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 567 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 568 if (retry < 10)
569 msleep(15);
570 else
571 udelay(15);
572
b5c616a7
CW		 573 if (!intel_sdvo_read_byte(intel_sdvo,
574 SDVO_I2C_CMD_STATUS,
575 &status))
d121a5d2
CW		 576 goto log_fail;
577 }
b5c616a7 578
84fcb469
DV		 579#define BUF_PRINT(args...) \
580 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
581
79e53945 582 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 583 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 584 else
84fcb469 585 BUF_PRINT("(??? %d)", status);
79e53945 586
b5c616a7
CW		 587 if (status != SDVO_CMD_STATUS_SUCCESS)
588 goto log_fail;
79e53945 589
b5c616a7
CW		 590 /* Read the command response */
591 for (i = 0; i < response_len; i++) {
592 if (!intel_sdvo_read_byte(intel_sdvo,
593 SDVO_I2C_RETURN_0 + i,
594 &((u8 *)response)[i]))
595 goto log_fail;
84fcb469 596 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 597 }
84fcb469
DV		 598 BUG_ON(pos >= BUF_LEN - 1);
599#undef BUF_PRINT
600#undef BUF_LEN
601
602 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 603 return true;
79e53945 604
b5c616a7 605log_fail:
84fcb469 606 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 607 return false;
79e53945
JB		 608}
609
5e7234c9 610static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
79e53945 611{
aad941d5 612 if (adjusted_mode->crtc_clock >= 100000)
79e53945 613 return 1;
aad941d5 614 else if (adjusted_mode->crtc_clock >= 50000)
79e53945
JB		 615 return 2;
616 else
617 return 4;
618}
619
e957d772
CW		 620static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
621 u8 ddc_bus)
79e53945 622{
d121a5d2 623 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 624 return intel_sdvo_write_cmd(intel_sdvo,
625 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
626 &ddc_bus, 1);
79e53945
JB		 627}
628
32aad86f 629static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 630{
d121a5d2
CW		 631 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
632 return false;
633
634 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 635}
79e53945 636
32aad86f
CW		 637static bool
638intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
639{
640 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
641 return false;
79e53945 642
32aad86f
CW		 643 return intel_sdvo_read_response(intel_sdvo, value, len);
644}
79e53945 645
32aad86f
CW		 646static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
647{
648 struct intel_sdvo_set_target_input_args targets = {0};
649 return intel_sdvo_set_value(intel_sdvo,
650 SDVO_CMD_SET_TARGET_INPUT,
651 &targets, sizeof(targets));
79e53945
JB		 652}
653
654/**
655 * Return whether each input is trained.
656 *
657 * This function is making an assumption about the layout of the response,
658 * which should be checked against the docs.
659 */
ea5b213a 660static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 661{
662 struct intel_sdvo_get_trained_inputs_response response;
79e53945 663
1a3665c8 664 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 665 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
666 &response, sizeof(response)))
79e53945
JB		 667 return false;
668
669 *input_1 = response.input0_trained;
670 *input_2 = response.input1_trained;
671 return true;
672}
673
ea5b213a 674static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 675 u16 outputs)
676{
32aad86f
CW		 677 return intel_sdvo_set_value(intel_sdvo,
678 SDVO_CMD_SET_ACTIVE_OUTPUTS,
679 &outputs, sizeof(outputs));
79e53945
JB		 680}
681
4ac41f47
DV		 682static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
683 u16 *outputs)
684{
685 return intel_sdvo_get_value(intel_sdvo,
686 SDVO_CMD_GET_ACTIVE_OUTPUTS,
687 outputs, sizeof(*outputs));
688}
689
ea5b213a 690static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 691 int mode)
692{
32aad86f 693 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 694
695 switch (mode) {
696 case DRM_MODE_DPMS_ON:
697 state = SDVO_ENCODER_STATE_ON;
698 break;
699 case DRM_MODE_DPMS_STANDBY:
700 state = SDVO_ENCODER_STATE_STANDBY;
701 break;
702 case DRM_MODE_DPMS_SUSPEND:
703 state = SDVO_ENCODER_STATE_SUSPEND;
704 break;
705 case DRM_MODE_DPMS_OFF:
706 state = SDVO_ENCODER_STATE_OFF;
707 break;
708 }
709
32aad86f
CW		 710 return intel_sdvo_set_value(intel_sdvo,
711 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 712}
713
ea5b213a 714static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 715 int *clock_min,
716 int *clock_max)
717{
718 struct intel_sdvo_pixel_clock_range clocks;
79e53945 719
1a3665c8 720 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 721 if (!intel_sdvo_get_value(intel_sdvo,
722 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
723 &clocks, sizeof(clocks)))
79e53945
JB		 724 return false;
725
726 /* Convert the values from units of 10 kHz to kHz. */
727 *clock_min = clocks.min * 10;
728 *clock_max = clocks.max * 10;
79e53945
JB		 729 return true;
730}
731
ea5b213a 732static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 733 u16 outputs)
734{
32aad86f
CW		 735 return intel_sdvo_set_value(intel_sdvo,
736 SDVO_CMD_SET_TARGET_OUTPUT,
737 &outputs, sizeof(outputs));
79e53945
JB		 738}
739
ea5b213a 740static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 741 struct intel_sdvo_dtd *dtd)
742{
32aad86f
CW		 743 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
744 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 745}
746
045ac3b5
JB		 747static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
748 struct intel_sdvo_dtd *dtd)
749{
750 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
751 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
752}
753
ea5b213a 754static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 755 struct intel_sdvo_dtd *dtd)
756{
ea5b213a 757 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 758 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
759}
760
ea5b213a 761static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 762 struct intel_sdvo_dtd *dtd)
763{
ea5b213a 764 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 765 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
766}
767
045ac3b5
JB		 768static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
769 struct intel_sdvo_dtd *dtd)
770{
771 return intel_sdvo_get_timing(intel_sdvo,
772 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
773}
774
e2f0ba97 775static bool
ea5b213a 776intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 777 uint16_t clock,
778 uint16_t width,
779 uint16_t height)
780{
781 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 782
e642c6f1 783 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 784 args.clock = clock;
785 args.width = width;
786 args.height = height;
e642c6f1 787 args.interlace = 0;
12682a97 788
ea5b213a
CW		 789 if (intel_sdvo->is_lvds &&
790 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
791 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 792 args.scaled = 1;
793
32aad86f
CW		 794 return intel_sdvo_set_value(intel_sdvo,
795 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
796 &args, sizeof(args));
e2f0ba97
JB		 797}
798
ea5b213a 799static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 800 struct intel_sdvo_dtd *dtd)
801{
1a3665c8
CW		 802 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
803 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 804 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
805 &dtd->part1, sizeof(dtd->part1)) &&
806 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
807 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 808}
79e53945 809
ea5b213a 810static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 811{
32aad86f 812 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 813}
814
e2f0ba97 815static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 816 const struct drm_display_mode *mode)
79e53945 817{
e2f0ba97
JB		 818 uint16_t width, height;
819 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
820 uint16_t h_sync_offset, v_sync_offset;
6651819b 821 int mode_clock;
79e53945 822
1c4a814e
DV		 823 memset(dtd, 0, sizeof(*dtd));
824
c6ebd4c0
DV		 825 width = mode->hdisplay;
826 height = mode->vdisplay;
79e53945
JB		 827
828 /* do some mode translations */
c6ebd4c0
DV		 829 h_blank_len = mode->htotal - mode->hdisplay;
830 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 831
c6ebd4c0
DV		 832 v_blank_len = mode->vtotal - mode->vdisplay;
833 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 834
c6ebd4c0
DV		 835 h_sync_offset = mode->hsync_start - mode->hdisplay;
836 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 837
6651819b 838 mode_clock = mode->clock;
6651819b
DV		 839 mode_clock /= 10;
840 dtd->part1.clock = mode_clock;
841
e2f0ba97
JB		 842 dtd->part1.h_active = width & 0xff;
843 dtd->part1.h_blank = h_blank_len & 0xff;
844 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 845 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 846 dtd->part1.v_active = height & 0xff;
847 dtd->part1.v_blank = v_blank_len & 0xff;
848 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 849 ((v_blank_len >> 8) & 0xf);
850
171a9e96 851 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 852 dtd->part2.h_sync_width = h_sync_len & 0xff;
853 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 854 (v_sync_len & 0xf);
e2f0ba97 855 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 856 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
857 ((v_sync_len & 0x30) >> 4);
858
e2f0ba97 859 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 860 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
861 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 862 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 863 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 864 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 865 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 866
e2f0ba97 867 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 868}
869
1c4a814e 870static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 871 const struct intel_sdvo_dtd *dtd)
e2f0ba97 872{
1c4a814e
DV		 873 struct drm_display_mode mode = {};
874
875 mode.hdisplay = dtd->part1.h_active;
876 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
877 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
878 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
879 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
880 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
881 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
882 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
883
884 mode.vdisplay = dtd->part1.v_active;
885 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
886 mode.vsync_start = mode.vdisplay;
887 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
888 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
889 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
890 mode.vsync_end = mode.vsync_start +
e2f0ba97 891 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 892 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
893 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
894 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 895
1c4a814e 896 mode.clock = dtd->part1.clock * 10;
e2f0ba97 897
59d92bfa 898 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 899 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 900 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 901 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 902 else
1c4a814e 903 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 904 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 905 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 906 else
1c4a814e
DV		 907 mode.flags |= DRM_MODE_FLAG_NVSYNC;
908
909 drm_mode_set_crtcinfo(&mode, 0);
910
911 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 912}
913
e27d8538 914static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 915{
e27d8538 916 struct intel_sdvo_encode encode;
e2f0ba97 917
1a3665c8 918 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 919 return intel_sdvo_get_value(intel_sdvo,
920 SDVO_CMD_GET_SUPP_ENCODE,
921 &encode, sizeof(encode));
e2f0ba97
JB		 922}
923
ea5b213a 924static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 925 uint8_t mode)
e2f0ba97 926{
32aad86f 927 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 928}
929
ea5b213a 930static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 931 uint8_t mode)
932{
32aad86f 933 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 934}
935
936#if 0
ea5b213a 937static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 938{
939 int i, j;
940 uint8_t set_buf_index[2];
941 uint8_t av_split;
942 uint8_t buf_size;
943 uint8_t buf[48];
944 uint8_t *pos;
945
32aad86f 946 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 947
948 for (i = 0; i <= av_split; i++) {
949 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 950 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 951 set_buf_index, 2);
c751ce4f
EA		 952 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
953 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 954
955 pos = buf;
956 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 957 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 958 NULL, 0);
c751ce4f 959 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 960 pos += 8;
961 }
962 }
963}
964#endif
965
b6e0e543
DV		 966static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
967 unsigned if_index, uint8_t tx_rate,
fff63867 968 const uint8_t *data, unsigned length)
b6e0e543
DV		 969{
970 uint8_t set_buf_index[2] = { if_index, 0 };
971 uint8_t hbuf_size, tmp[8];
972 int i;
973
974 if (!intel_sdvo_set_value(intel_sdvo,
975 SDVO_CMD_SET_HBUF_INDEX,
976 set_buf_index, 2))
977 return false;
978
979 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
980 &hbuf_size, 1))
981 return false;
982
983 /* Buffer size is 0 based, hooray! */
984 hbuf_size++;
985
986 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
987 if_index, length, hbuf_size);
988
989 for (i = 0; i < hbuf_size; i += 8) {
990 memset(tmp, 0, 8);
991 if (i < length)
992 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
993
994 if (!intel_sdvo_set_value(intel_sdvo,
995 SDVO_CMD_SET_HBUF_DATA,
996 tmp, 8))
997 return false;
998 }
999
1000 return intel_sdvo_set_value(intel_sdvo,
1001 SDVO_CMD_SET_HBUF_TXRATE,
1002 &tx_rate, 1);
1003}
1004
abedc077 1005static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
f9fe0530 1006 struct intel_crtc_state *pipe_config)
e2f0ba97 1007{
15dcd350 1008 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
15dcd350
DL		 1009 union hdmi_infoframe frame;
1010 int ret;
1011 ssize_t len;
1012
1013 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
f9fe0530 1014 &pipe_config->base.adjusted_mode);
15dcd350
DL		 1015 if (ret < 0) {
1016 DRM_ERROR("couldn't fill AVI infoframe\n");
1017 return false;
1018 }
3c17fe4b 1019
abedc077 1020 if (intel_sdvo->rgb_quant_range_selectable) {
f9fe0530 1021 if (pipe_config->limited_color_range)
15dcd350
DL		 1022 frame.avi.quantization_range =
1023 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1024 else
15dcd350
DL		 1025 frame.avi.quantization_range =
1026 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1027 }
1028
15dcd350
DL		 1029 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1030 if (len < 0)
1031 return false;
81014b9d 1032
b6e0e543
DV		 1033 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1034 SDVO_HBUF_TX_VSYNC,
1035 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1036}
1037
32aad86f 1038static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 1039{
ce6feabd 1040 struct intel_sdvo_tv_format format;
40039750 1041 uint32_t format_map;
ce6feabd 1042
40039750 1043 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1044 memset(&format, 0, sizeof(format));
32aad86f 1045 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1046
32aad86f
CW		 1047 BUILD_BUG_ON(sizeof(format) != 6);
1048 return intel_sdvo_set_value(intel_sdvo,
1049 SDVO_CMD_SET_TV_FORMAT,
1050 &format, sizeof(format));
7026d4ac
ZW		 1051}
1052
32aad86f
CW		 1053static bool
1054intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1055 const struct drm_display_mode *mode)
e2f0ba97 1056{
32aad86f 1057 struct intel_sdvo_dtd output_dtd;
79e53945 1058
32aad86f
CW		 1059 if (!intel_sdvo_set_target_output(intel_sdvo,
1060 intel_sdvo->attached_output))
1061 return false;
e2f0ba97 1062
32aad86f
CW		 1063 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1064 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1065 return false;
e2f0ba97 1066
32aad86f
CW		 1067 return true;
1068}
1069
c9a29698
DV		 1070/* Asks the sdvo controller for the preferred input mode given the output mode.
1071 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1072static bool
c9a29698 1073intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1074 const struct drm_display_mode *mode,
c9a29698 1075 struct drm_display_mode *adjusted_mode)
32aad86f 1076{
c9a29698
DV		 1077 struct intel_sdvo_dtd input_dtd;
1078
32aad86f
CW		 1079 /* Reset the input timing to the screen. Assume always input 0. */
1080 if (!intel_sdvo_set_target_input(intel_sdvo))
1081 return false;
e2f0ba97 1082
32aad86f
CW		 1083 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1084 mode->clock / 10,
1085 mode->hdisplay,
1086 mode->vdisplay))
1087 return false;
e2f0ba97 1088
32aad86f 1089 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1090 &input_dtd))
32aad86f 1091 return false;
e2f0ba97 1092
c9a29698 1093 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1094 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1095
32aad86f
CW		 1096 return true;
1097}
12682a97 1098
5cec258b 1099static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
70484559 1100{
3c52f4eb 1101 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1102 struct dpll *clock = &pipe_config->dpll;
1103
1104 /* SDVO TV has fixed PLL values depend on its clock range,
1105 this mirrors vbios setting. */
1106 if (dotclock >= 100000 && dotclock < 140500) {
1107 clock->p1 = 2;
1108 clock->p2 = 10;
1109 clock->n = 3;
1110 clock->m1 = 16;
1111 clock->m2 = 8;
1112 } else if (dotclock >= 140500 && dotclock <= 200000) {
1113 clock->p1 = 1;
1114 clock->p2 = 10;
1115 clock->n = 6;
1116 clock->m1 = 12;
1117 clock->m2 = 8;
1118 } else {
1119 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1120 }
1121
1122 pipe_config->clock_set = true;
1123}
1124
6cc5f341 1125static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1126 struct intel_crtc_state *pipe_config,
1127 struct drm_connector_state *conn_state)
32aad86f 1128{
8aca63aa 1129 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2d112de7
ACO		 1130 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1131 struct drm_display_mode *mode = &pipe_config->base.mode;
12682a97 1132
5d2d38dd
DV		 1133 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1134 pipe_config->pipe_bpp = 8*3;
1135
5bfe2ac0
DV		 1136 if (HAS_PCH_SPLIT(encoder->base.dev))
1137 pipe_config->has_pch_encoder = true;
1138
32aad86f
CW		 1139 /* We need to construct preferred input timings based on our
1140 * output timings. To do that, we have to set the output
1141 * timings, even though this isn't really the right place in
1142 * the sequence to do it. Oh well.
1143 */
1144 if (intel_sdvo->is_tv) {
1145 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1146 return false;
12682a97 1147
c9a29698
DV		 1148 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1149 mode,
1150 adjusted_mode);
09ede541 1151 pipe_config->sdvo_tv_clock = true;
ea5b213a 1152 } else if (intel_sdvo->is_lvds) {
32aad86f 1153 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1154 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1155 return false;
12682a97 1156
c9a29698
DV		 1157 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1158 mode,
1159 adjusted_mode);
e2f0ba97 1160 }
32aad86f
CW		 1161
1162 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1163 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1164 */
6cc5f341
DV		 1165 pipe_config->pixel_multiplier =
1166 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1167
9f04003e
DV		 1168 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1169
55bc60db
VS		 1170 if (intel_sdvo->color_range_auto) {
1171 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1172 /* FIXME: This bit is only valid when using TMDS encoding and 8
1173 * bit per color mode. */
9f04003e 1174 if (pipe_config->has_hdmi_sink &&
18316c8c 1175 drm_match_cea_mode(adjusted_mode) > 1)
69f5acc8
DV		 1176 pipe_config->limited_color_range = true;
1177 } else {
9f04003e 1178 if (pipe_config->has_hdmi_sink &&
69f5acc8
DV		 1179 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
1180 pipe_config->limited_color_range = true;
55bc60db
VS		 1181 }
1182
70484559
DV		 1183 /* Clock computation needs to happen after pixel multiplier. */
1184 if (intel_sdvo->is_tv)
1185 i9xx_adjust_sdvo_tv_clock(pipe_config);
1186
7949dd47
VS		 1187 /* Set user selected PAR to incoming mode's member */
1188 if (intel_sdvo->is_hdmi)
1189 adjusted_mode->picture_aspect_ratio = intel_sdvo->aspect_ratio;
1190
e2f0ba97
JB		 1191 return true;
1192}
1193
fd6bbda9
ML		 1194static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1195 struct intel_crtc_state *crtc_state,
1196 struct drm_connector_state *conn_state)
e2f0ba97 1197{
6cc5f341 1198 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 1199 struct drm_i915_private *dev_priv = to_i915(dev);
f9fe0530
ML		 1200 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1201 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1202 struct drm_display_mode *mode = &crtc_state->base.mode;
8aca63aa 1203 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1204 u32 sdvox;
e2f0ba97 1205 struct intel_sdvo_in_out_map in_out;
6651819b 1206 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1207 int rate;
e2f0ba97 1208
e2f0ba97
JB		 1209 /* First, set the input mapping for the first input to our controlled
1210 * output. This is only correct if we're a single-input device, in
1211 * which case the first input is the output from the appropriate SDVO
1212 * channel on the motherboard. In a two-input device, the first input
1213 * will be SDVOB and the second SDVOC.
1214 */
ea5b213a 1215 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1216 in_out.in1 = 0;
1217
c74696b9
PR		 1218 intel_sdvo_set_value(intel_sdvo,
1219 SDVO_CMD_SET_IN_OUT_MAP,
1220 &in_out, sizeof(in_out));
e2f0ba97 1221
6c9547ff
CW		 1222 /* Set the output timings to the screen */
1223 if (!intel_sdvo_set_target_output(intel_sdvo,
1224 intel_sdvo->attached_output))
1225 return;
e2f0ba97 1226
6651819b
DV		 1227 /* lvds has a special fixed output timing. */
1228 if (intel_sdvo->is_lvds)
1229 intel_sdvo_get_dtd_from_mode(&output_dtd,
1230 intel_sdvo->sdvo_lvds_fixed_mode);
1231 else
1232 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1233 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1234 DRM_INFO("Setting output timings on %s failed\n",
1235 SDVO_NAME(intel_sdvo));
79e53945
JB		 1236
1237 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1238 if (!intel_sdvo_set_target_input(intel_sdvo))
1239 return;
79e53945 1240
f9fe0530 1241 if (crtc_state->has_hdmi_sink) {
97aaf910
CW		 1242 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1243 intel_sdvo_set_colorimetry(intel_sdvo,
1244 SDVO_COLORIMETRY_RGB256);
f9fe0530 1245 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
97aaf910
CW		 1246 } else
1247 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1248
6c9547ff
CW		 1249 if (intel_sdvo->is_tv &&
1250 !intel_sdvo_set_tv_format(intel_sdvo))
1251 return;
e2f0ba97 1252
6651819b 1253 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1254
e751823d
EE		 1255 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1256 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1257 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1258 DRM_INFO("Setting input timings on %s failed\n",
1259 SDVO_NAME(intel_sdvo));
79e53945 1260
f9fe0530 1261 switch (crtc_state->pixel_multiplier) {
6c9547ff 1262 default:
fd0753cf 1263 WARN(1, "unknown pixel multiplier specified\n");
32aad86f
CW		 1264 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1265 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1266 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1267 }
32aad86f
CW		 1268 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1269 return;
79e53945
JB		 1270
1271 /* Set the SDVO control regs. */
a6c45cf0 1272 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1273 /* The real mode polarity is set by the SDVO commands, using
1274 * struct intel_sdvo_dtd. */
1275 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
f9fe0530 1276 if (!HAS_PCH_SPLIT(dev) && crtc_state->limited_color_range)
69f5acc8 1277 sdvox |= HDMI_COLOR_RANGE_16_235;
6714afb1
CW		 1278 if (INTEL_INFO(dev)->gen < 5)
1279 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1280 } else {
6c9547ff 1281 sdvox = I915_READ(intel_sdvo->sdvo_reg);
2a5c0832 1282 if (intel_sdvo->port == PORT_B)
e2f0ba97 1283 sdvox &= SDVOB_PRESERVE_MASK;
2a5c0832 1284 else
e2f0ba97 1285 sdvox &= SDVOC_PRESERVE_MASK;
e2f0ba97
JB		 1286 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1287 }
3573c410
PZ		 1288
1289 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
eeb47937 1290 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1291 else
eeb47937 1292 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1293
da79de97 1294 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1295 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1296
a6c45cf0 1297 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1298 /* done in crtc_mode_set as the dpll_md reg must be written early */
1299 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1300 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1301 } else {
f9fe0530 1302 sdvox |= (crtc_state->pixel_multiplier - 1)
6cc5f341 1303 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1304 }
1305
6714afb1
CW		 1306 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1307 INTEL_INFO(dev)->gen < 5)
12682a97 1308 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1309 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1310}
1311
4ac41f47 1312static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1313{
4ac41f47
DV		 1314 struct intel_sdvo_connector *intel_sdvo_connector =
1315 to_intel_sdvo_connector(&connector->base);
1316 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1317 u16 active_outputs = 0;
4ac41f47
DV		 1318
1319 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1320
1321 if (active_outputs & intel_sdvo_connector->output_flag)
1322 return true;
1323 else
1324 return false;
1325}
1326
1327static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1328 enum pipe *pipe)
1329{
1330 struct drm_device *dev = encoder->base.dev;
fac5e23e 1331 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1332 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1333 u16 active_outputs = 0;
4ac41f47
DV		 1334 u32 tmp;
1335
1336 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1337 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1338
7a7d1fb7 1339 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1340 return false;
1341
1342 if (HAS_PCH_CPT(dev))
1343 *pipe = PORT_TO_PIPE_CPT(tmp);
1344 else
1345 *pipe = PORT_TO_PIPE(tmp);
1346
1347 return true;
1348}
1349
045ac3b5 1350static void intel_sdvo_get_config(struct intel_encoder *encoder,
5cec258b 1351 struct intel_crtc_state *pipe_config)
045ac3b5 1352{
6c49f241 1353 struct drm_device *dev = encoder->base.dev;
fac5e23e 1354 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1355 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1356 struct intel_sdvo_dtd dtd;
6c49f241 1357 int encoder_pixel_multiplier = 0;
18442d08 1358 int dotclock;
6c49f241
DV		 1359 u32 flags = 0, sdvox;
1360 u8 val;
045ac3b5
JB		 1361 bool ret;
1362
b5a9fa09
DV		 1363 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1364
045ac3b5
JB		 1365 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1366 if (!ret) {
bb760063
DV		 1367 /* Some sdvo encoders are not spec compliant and don't
1368 * implement the mandatory get_timings function. */
045ac3b5 1369 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1370 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1371 } else {
1372 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1373 flags |= DRM_MODE_FLAG_PHSYNC;
1374 else
1375 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1376
bb760063
DV		 1377 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1378 flags |= DRM_MODE_FLAG_PVSYNC;
1379 else
1380 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1381 }
1382
2d112de7 1383 pipe_config->base.adjusted_mode.flags |= flags;
045ac3b5 1384
fdafa9e2
DV		 1385 /*
1386 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1387 * the sdvo port register, on all other platforms it is part of the dpll
1388 * state. Since the general pipe state readout happens before the
1389 * encoder->get_config we so already have a valid pixel multplier on all
1390 * other platfroms.
1391 */
6c49f241 1392 if (IS_I915G(dev) || IS_I915GM(dev)) {
6c49f241
DV		 1393 pipe_config->pixel_multiplier =
1394 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1395 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1396 }
045ac3b5 1397
2b85886a 1398 dotclock = pipe_config->port_clock;
e3b247da 1399
2b85886a
VS		 1400 if (pipe_config->pixel_multiplier)
1401 dotclock /= pipe_config->pixel_multiplier;
18442d08 1402
2d112de7 1403 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
18442d08 1404
6c49f241 1405 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1406 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1407 &val, 1)) {
1408 switch (val) {
1409 case SDVO_CLOCK_RATE_MULT_1X:
1410 encoder_pixel_multiplier = 1;
1411 break;
1412 case SDVO_CLOCK_RATE_MULT_2X:
1413 encoder_pixel_multiplier = 2;
1414 break;
1415 case SDVO_CLOCK_RATE_MULT_4X:
1416 encoder_pixel_multiplier = 4;
1417 break;
1418 }
6c49f241 1419 }
fdafa9e2 1420
b5a9fa09
DV		 1421 if (sdvox & HDMI_COLOR_RANGE_16_235)
1422 pipe_config->limited_color_range = true;
1423
9f04003e
DV		 1424 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1425 &val, 1)) {
1426 if (val == SDVO_ENCODE_HDMI)
1427 pipe_config->has_hdmi_sink = true;
1428 }
1429
6c49f241
DV		 1430 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1431 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1432 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1433}
1434
fd6bbda9
ML		 1435static void intel_disable_sdvo(struct intel_encoder *encoder,
1436 struct intel_crtc_state *old_crtc_state,
1437 struct drm_connector_state *conn_state)
ce22c320 1438{
fac5e23e 1439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1440 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1612c8bd 1441 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
ce22c320
DV		 1442 u32 temp;
1443
1444 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1445 if (0)
1446 intel_sdvo_set_encoder_power_state(intel_sdvo,
1447 DRM_MODE_DPMS_OFF);
1448
1449 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf 1450
1612c8bd
VS		 1451 temp &= ~SDVO_ENABLE;
1452 intel_sdvo_write_sdvox(intel_sdvo, temp);
1453
1454 /*
1455 * HW workaround for IBX, we need to move the port
1456 * to transcoder A after disabling it to allow the
1457 * matching DP port to be enabled on transcoder A.
1458 */
1459 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1460 /*
1461 * We get CPU/PCH FIFO underruns on the other pipe when
1462 * doing the workaround. Sweep them under the rug.
1463 */
1464 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1465 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1466
1612c8bd
VS		 1467 temp &= ~SDVO_PIPE_B_SELECT;
1468 temp |= SDVO_ENABLE;
1469 intel_sdvo_write_sdvox(intel_sdvo, temp);
1470
1471 temp &= ~SDVO_ENABLE;
1472 intel_sdvo_write_sdvox(intel_sdvo, temp);
0c241d5b 1473
91c8a326 1474 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
0c241d5b
VS		 1475 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1476 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
ce22c320
DV		 1477 }
1478}
1479
fd6bbda9
ML		 1480static void pch_disable_sdvo(struct intel_encoder *encoder,
1481 struct intel_crtc_state *old_crtc_state,
1482 struct drm_connector_state *old_conn_state)
3c65d1d1
VS		 1483{
1484}
1485
fd6bbda9
ML		 1486static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1487 struct intel_crtc_state *old_crtc_state,
1488 struct drm_connector_state *old_conn_state)
3c65d1d1 1489{
fd6bbda9 1490 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
3c65d1d1
VS		 1491}
1492
fd6bbda9
ML		 1493static void intel_enable_sdvo(struct intel_encoder *encoder,
1494 struct intel_crtc_state *pipe_config,
1495 struct drm_connector_state *conn_state)
ce22c320
DV		 1496{
1497 struct drm_device *dev = encoder->base.dev;
fac5e23e 1498 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1499 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1500 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1501 u32 temp;
ce22c320
DV		 1502 bool input1, input2;
1503 int i;
d0a7b6de 1504 bool success;
ce22c320
DV		 1505
1506 temp = I915_READ(intel_sdvo->sdvo_reg);
3c65d1d1
VS		 1507 temp |= SDVO_ENABLE;
1508 intel_sdvo_write_sdvox(intel_sdvo, temp);
776ca7cf 1509
ce22c320
DV		 1510 for (i = 0; i < 2; i++)
1511 intel_wait_for_vblank(dev, intel_crtc->pipe);
1512
d0a7b6de 1513 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
ce22c320
DV		 1514 /* Warn if the device reported failure to sync.
1515 * A lot of SDVO devices fail to notify of sync, but it's
1516 * a given it the status is a success, we succeeded.
1517 */
d0a7b6de 1518 if (success && !input1) {
ce22c320
DV		 1519 DRM_DEBUG_KMS("First %s output reported failure to "
1520 "sync\n", SDVO_NAME(intel_sdvo));
1521 }
1522
1523 if (0)
1524 intel_sdvo_set_encoder_power_state(intel_sdvo,
1525 DRM_MODE_DPMS_ON);
1526 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1527}
1528
c19de8eb
DL		 1529static enum drm_mode_status
1530intel_sdvo_mode_valid(struct drm_connector *connector,
1531 struct drm_display_mode *mode)
79e53945 1532{
df0e9248 1533 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
24b23882 1534 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
79e53945
JB		 1535
1536 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1537 return MODE_NO_DBLESCAN;
1538
ea5b213a 1539 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1540 return MODE_CLOCK_LOW;
1541
ea5b213a 1542 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1543 return MODE_CLOCK_HIGH;
1544
24b23882
MK		 1545 if (mode->clock > max_dotclk)
1546 return MODE_CLOCK_HIGH;
1547
8545423a 1548 if (intel_sdvo->is_lvds) {
ea5b213a 1549 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1550 return MODE_PANEL;
1551
ea5b213a 1552 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1553 return MODE_PANEL;
1554 }
1555
79e53945
JB		 1556 return MODE_OK;
1557}
1558
ea5b213a 1559static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1560{
1a3665c8 1561 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1562 if (!intel_sdvo_get_value(intel_sdvo,
1563 SDVO_CMD_GET_DEVICE_CAPS,
1564 caps, sizeof(*caps)))
1565 return false;
1566
1567 DRM_DEBUG_KMS("SDVO capabilities:\n"
1568 " vendor_id: %d\n"
1569 " device_id: %d\n"
1570 " device_rev_id: %d\n"
1571 " sdvo_version_major: %d\n"
1572 " sdvo_version_minor: %d\n"
1573 " sdvo_inputs_mask: %d\n"
1574 " smooth_scaling: %d\n"
1575 " sharp_scaling: %d\n"
1576 " up_scaling: %d\n"
1577 " down_scaling: %d\n"
1578 " stall_support: %d\n"
1579 " output_flags: %d\n",
1580 caps->vendor_id,
1581 caps->device_id,
1582 caps->device_rev_id,
1583 caps->sdvo_version_major,
1584 caps->sdvo_version_minor,
1585 caps->sdvo_inputs_mask,
1586 caps->smooth_scaling,
1587 caps->sharp_scaling,
1588 caps->up_scaling,
1589 caps->down_scaling,
1590 caps->stall_support,
1591 caps->output_flags);
1592
1593 return true;
79e53945
JB		 1594}
1595
5fa7ac9c 1596static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1597{
768b107e 1598 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1599 uint16_t hotplug;
79e53945 1600
1d83d957
VS		 1601 if (!I915_HAS_HOTPLUG(dev))
1602 return 0;
1603
768b107e
DV		 1604 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1605 * on the line. */
1606 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1607 return 0;
768b107e 1608
5fa7ac9c
JN		 1609 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1610 &hotplug, sizeof(hotplug)))
1611 return 0;
768b107e 1612
5fa7ac9c 1613 return hotplug;
79e53945
JB		 1614}
1615
cc68c81a 1616static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1617{
8aca63aa 1618 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1619
5fa7ac9c
JN		 1620 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1621 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1622}
1623
fb7a46f3 1624static bool
ea5b213a 1625intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1626{
bc65212c 1627 /* Is there more than one type of output? */
2294488d 1628 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1629}
1630
f899fc64 1631static struct edid *
e957d772 1632intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1633{
e957d772
CW		 1634 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1635 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1636}
1637
ff482d83
CW		 1638/* Mac mini hack -- use the same DDC as the analog connector */
1639static struct edid *
1640intel_sdvo_get_analog_edid(struct drm_connector *connector)
1641{
fac5e23e 1642 struct drm_i915_private *dev_priv = to_i915(connector->dev);
ff482d83 1643
0c1dab89 1644 return drm_get_edid(connector,
3bd7d909 1645 intel_gmbus_get_adapter(dev_priv,
41aa3448 1646 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1647}
1648
c43b5634 1649static enum drm_connector_status
8bf38485 1650intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1651{
df0e9248 1652 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1653 enum drm_connector_status status;
1654 struct edid *edid;
9dff6af8 1655
e957d772 1656 edid = intel_sdvo_get_edid(connector);
57cdaf90 1657
ea5b213a 1658 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1659 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1660
7c3f0a27
ZY		 1661 /*
1662 * Don't use the 1 as the argument of DDC bus switch to get
1663 * the EDID. It is used for SDVO SPD ROM.
1664 */
9d1a903d 1665 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1666 intel_sdvo->ddc_bus = ddc;
1667 edid = intel_sdvo_get_edid(connector);
1668 if (edid)
7c3f0a27 1669 break;
7c3f0a27 1670 }
e957d772
CW		 1671 /*
1672 * If we found the EDID on the other bus,
1673 * assume that is the correct DDC bus.
1674 */
1675 if (edid == NULL)
1676 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1677 }
9d1a903d
CW		 1678
1679 /*
1680 * When there is no edid and no monitor is connected with VGA
1681 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1682 */
ff482d83
CW		 1683 if (edid == NULL)
1684 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1685
2f551c84 1686 status = connector_status_unknown;
9dff6af8 1687 if (edid != NULL) {
149c36a3 1688 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1689 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1690 status = connector_status_connected;
da79de97
CW		 1691 if (intel_sdvo->is_hdmi) {
1692 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1693 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1694 intel_sdvo->rgb_quant_range_selectable =
1695 drm_rgb_quant_range_selectable(edid);
da79de97 1696 }
13946743
CW		 1697 } else
1698 status = connector_status_disconnected;
9d1a903d
CW		 1699 kfree(edid);
1700 }
7f36e7ed
CW		 1701
1702 if (status == connector_status_connected) {
1703 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1704 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1705 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1706 }
1707
2b8d33f7 1708 return status;
9dff6af8
ML		 1709}
1710
52220085
CW		 1711static bool
1712intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1713 struct edid *edid)
1714{
1715 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1716 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1717
1718 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1719 connector_is_digital, monitor_is_digital);
1720 return connector_is_digital == monitor_is_digital;
1721}
1722
7b334fcb 1723static enum drm_connector_status
930a9e28 1724intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1725{
fb7a46f3 1726 uint16_t response;
df0e9248 1727 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1728 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1729 enum drm_connector_status ret;
79e53945 1730
164c8598 1731 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1732 connector->base.id, connector->name);
164c8598 1733
fc37381c
CW		 1734 if (!intel_sdvo_get_value(intel_sdvo,
1735 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1736 &response, 2))
32aad86f 1737 return connector_status_unknown;
79e53945 1738
e957d772
CW		 1739 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1740 response & 0xff, response >> 8,
1741 intel_sdvo_connector->output_flag);
e2f0ba97 1742
fb7a46f3 1743 if (response == 0)
79e53945 1744 return connector_status_disconnected;
fb7a46f3 1745
ea5b213a 1746 intel_sdvo->attached_output = response;
14571b4c 1747
97aaf910
CW		 1748 intel_sdvo->has_hdmi_monitor = false;
1749 intel_sdvo->has_hdmi_audio = false;
abedc077 1750 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1751
615fb93f 1752 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1753 ret = connector_status_disconnected;
13946743 1754 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1755 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1756 else {
1757 struct edid *edid;
1758
1759 /* if we have an edid check it matches the connection */
1760 edid = intel_sdvo_get_edid(connector);
1761 if (edid == NULL)
1762 edid = intel_sdvo_get_analog_edid(connector);
1763 if (edid != NULL) {
52220085
CW		 1764 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1765 edid))
13946743 1766 ret = connector_status_connected;
52220085
CW		 1767 else
1768 ret = connector_status_disconnected;
1769
13946743
CW		 1770 kfree(edid);
1771 } else
1772 ret = connector_status_connected;
1773 }
14571b4c
ZW		 1774
1775 /* May update encoder flag for like clock for SDVO TV, etc.*/
1776 if (ret == connector_status_connected) {
ea5b213a
CW		 1777 intel_sdvo->is_tv = false;
1778 intel_sdvo->is_lvds = false;
14571b4c 1779
09ede541 1780 if (response & SDVO_TV_MASK)
ea5b213a 1781 intel_sdvo->is_tv = true;
14571b4c 1782 if (response & SDVO_LVDS_MASK)
8545423a 1783 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1784 }
14571b4c
ZW		 1785
1786 return ret;
79e53945
JB		 1787}
1788
e2f0ba97 1789static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1790{
ff482d83 1791 struct edid *edid;
79e53945 1792
46a3f4a3 1793 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1794 connector->base.id, connector->name);
46a3f4a3 1795
79e53945 1796 /* set the bus switch and get the modes */
e957d772 1797 edid = intel_sdvo_get_edid(connector);
79e53945 1798
57cdaf90
KP		 1799 /*
1800 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1801 * link between analog and digital outputs. So, if the regular SDVO
1802 * DDC fails, check to see if the analog output is disconnected, in
1803 * which case we'll look there for the digital DDC data.
e2f0ba97 1804 */
f899fc64
CW		 1805 if (edid == NULL)
1806 edid = intel_sdvo_get_analog_edid(connector);
1807
ff482d83 1808 if (edid != NULL) {
52220085
CW		 1809 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1810 edid)) {
0c1dab89
CW		 1811 drm_mode_connector_update_edid_property(connector, edid);
1812 drm_add_edid_modes(connector, edid);
1813 }
13946743 1814
ff482d83 1815 kfree(edid);
e2f0ba97 1816 }
e2f0ba97
JB		 1817}
1818
1819/*
1820 * Set of SDVO TV modes.
1821 * Note! This is in reply order (see loop in get_tv_modes).
1822 * XXX: all 60Hz refresh?
1823 */
b1f559ec 1824static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1825 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1826 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1828 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1829 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1831 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1832 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1834 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1835 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1837 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1838 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1840 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1841 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1843 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1844 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1846 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1847 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1848 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1849 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1850 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1852 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1853 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1855 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1856 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1858 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1859 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1860 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1861 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1862 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1864 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1865 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1867 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1868 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1870 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1871 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1873 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1874 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1875 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1876 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1877 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1879 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1880 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1881 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1882};
1883
1884static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1885{
df0e9248 1886 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1887 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1888 uint32_t reply = 0, format_map = 0;
1889 int i;
e2f0ba97 1890
46a3f4a3 1891 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1892 connector->base.id, connector->name);
46a3f4a3 1893
e2f0ba97
JB		 1894 /* Read the list of supported input resolutions for the selected TV
1895 * format.
1896 */
40039750 1897 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1898 memcpy(&tv_res, &format_map,
32aad86f 1899 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1900
32aad86f
CW		 1901 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1902 return;
ce6feabd 1903
32aad86f 1904 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1905 if (!intel_sdvo_write_cmd(intel_sdvo,
1906 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1907 &tv_res, sizeof(tv_res)))
1908 return;
1909 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1910 return;
1911
1912 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1913 if (reply & (1 << i)) {
1914 struct drm_display_mode *nmode;
1915 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1916 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1917 if (nmode)
1918 drm_mode_probed_add(connector, nmode);
1919 }
e2f0ba97
JB		 1920}
1921
7086c87f
ML		 1922static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1923{
df0e9248 1924 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
fac5e23e 1925 struct drm_i915_private *dev_priv = to_i915(connector->dev);
12682a97 1926 struct drm_display_mode *newmode;
7086c87f 1927
46a3f4a3 1928 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1929 connector->base.id, connector->name);
46a3f4a3 1930
7086c87f 1931 /*
c3456fb3 1932 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1933 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1934 */
41aa3448 1935 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1936 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1937 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1938 if (newmode != NULL) {
1939 /* Guarantee the mode is preferred */
1940 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1941 DRM_MODE_TYPE_DRIVER);
1942 drm_mode_probed_add(connector, newmode);
1943 }
1944 }
12682a97 1945
4300a0f8
DA		 1946 /*
1947 * Attempt to get the mode list from DDC.
1948 * Assume that the preferred modes are
1949 * arranged in priority order.
1950 */
1951 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1952
12682a97 1953 list_for_each_entry(newmode, &connector->probed_modes, head) {
1954 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1955 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1956 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1957
8545423a 1958 intel_sdvo->is_lvds = true;
12682a97 1959 break;
1960 }
1961 }
7086c87f
ML		 1962}
1963
e2f0ba97
JB		 1964static int intel_sdvo_get_modes(struct drm_connector *connector)
1965{
615fb93f 1966 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1967
615fb93f 1968 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1969 intel_sdvo_get_tv_modes(connector);
615fb93f 1970 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1971 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1972 else
1973 intel_sdvo_get_ddc_modes(connector);
1974
32aad86f 1975 return !list_empty(&connector->probed_modes);
79e53945
JB		 1976}
1977
1978static void intel_sdvo_destroy(struct drm_connector *connector)
1979{
615fb93f 1980 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1981
79e53945 1982 drm_connector_cleanup(connector);
4b745b1e 1983 kfree(intel_sdvo_connector);
79e53945
JB		 1984}
1985
1aad7ac0
CW		 1986static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1987{
1988 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1989 struct edid *edid;
1990 bool has_audio = false;
1991
1992 if (!intel_sdvo->is_hdmi)
1993 return false;
1994
1995 edid = intel_sdvo_get_edid(connector);
1996 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1997 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1998 kfree(edid);
1aad7ac0
CW		 1999
2000 return has_audio;
2001}
2002
ce6feabd
ZY		 2003static int
2004intel_sdvo_set_property(struct drm_connector *connector,
2005 struct drm_property *property,
2006 uint64_t val)
2007{
df0e9248 2008 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 2009 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
fac5e23e 2010 struct drm_i915_private *dev_priv = to_i915(connector->dev);
b9219c5e 2011 uint16_t temp_value;
32aad86f
CW		 2012 uint8_t cmd;
2013 int ret;
ce6feabd 2014
662595df 2015 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 2016 if (ret)
2017 return ret;
ce6feabd 2018
3f43c48d 2019 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2020 int i = val;
2021 bool has_audio;
2022
2023 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 2024 return 0;
2025
1aad7ac0 2026 intel_sdvo_connector->force_audio = i;
7f36e7ed 2027
c3e5f67b 2028 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2029 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2030 else
c3e5f67b 2031 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 2032
1aad7ac0 2033 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 2034 return 0;
7f36e7ed 2035
1aad7ac0 2036 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2037 goto done;
2038 }
2039
e953fd7b 2040 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2041 bool old_auto = intel_sdvo->color_range_auto;
2042 uint32_t old_range = intel_sdvo->color_range;
2043
55bc60db
VS		 2044 switch (val) {
2045 case INTEL_BROADCAST_RGB_AUTO:
2046 intel_sdvo->color_range_auto = true;
2047 break;
2048 case INTEL_BROADCAST_RGB_FULL:
2049 intel_sdvo->color_range_auto = false;
2050 intel_sdvo->color_range = 0;
2051 break;
2052 case INTEL_BROADCAST_RGB_LIMITED:
2053 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2054 /* FIXME: this bit is only valid when using TMDS
2055 * encoding and 8 bit per color mode. */
2056 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2057 break;
2058 default:
2059 return -EINVAL;
2060 }
ae4edb80
DV		 2061
2062 if (old_auto == intel_sdvo->color_range_auto &&
2063 old_range == intel_sdvo->color_range)
2064 return 0;
2065
7f36e7ed
CW		 2066 goto done;
2067 }
2068
7949dd47
VS		 2069 if (property == connector->dev->mode_config.aspect_ratio_property) {
2070 switch (val) {
2071 case DRM_MODE_PICTURE_ASPECT_NONE:
2072 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2073 break;
2074 case DRM_MODE_PICTURE_ASPECT_4_3:
2075 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
2076 break;
2077 case DRM_MODE_PICTURE_ASPECT_16_9:
2078 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
2079 break;
2080 default:
2081 return -EINVAL;
2082 }
2083 goto done;
2084 }
2085
c5521706
CW		 2086#define CHECK_PROPERTY(name, NAME) \
2087 if (intel_sdvo_connector->name == property) { \
2088 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2089 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2090 cmd = SDVO_CMD_SET_##NAME; \
2091 intel_sdvo_connector->cur_##name = temp_value; \
2092 goto set_value; \
2093 }
2094
2095 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2096 if (val >= TV_FORMAT_NUM)
2097 return -EINVAL;
2098
40039750 2099 if (intel_sdvo->tv_format_index ==
615fb93f 2100 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2101 return 0;
ce6feabd 2102
40039750 2103 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2104 goto done;
32aad86f 2105 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2106 temp_value = val;
c5521706 2107 if (intel_sdvo_connector->left == property) {
662595df 2108 drm_object_property_set_value(&connector->base,
c5521706 2109 intel_sdvo_connector->right, val);
615fb93f 2110 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2111 return 0;
b9219c5e 2112
615fb93f
CW		 2113 intel_sdvo_connector->left_margin = temp_value;
2114 intel_sdvo_connector->right_margin = temp_value;
2115 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2116 intel_sdvo_connector->left_margin;
b9219c5e 2117 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2118 goto set_value;
2119 } else if (intel_sdvo_connector->right == property) {
662595df 2120 drm_object_property_set_value(&connector->base,
c5521706 2121 intel_sdvo_connector->left, val);
615fb93f 2122 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2123 return 0;
b9219c5e 2124
615fb93f
CW		 2125 intel_sdvo_connector->left_margin = temp_value;
2126 intel_sdvo_connector->right_margin = temp_value;
2127 temp_value = intel_sdvo_connector->max_hscan -
2128 intel_sdvo_connector->left_margin;
b9219c5e 2129 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2130 goto set_value;
2131 } else if (intel_sdvo_connector->top == property) {
662595df 2132 drm_object_property_set_value(&connector->base,
c5521706 2133 intel_sdvo_connector->bottom, val);
615fb93f 2134 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2135 return 0;
b9219c5e 2136
615fb93f
CW		 2137 intel_sdvo_connector->top_margin = temp_value;
2138 intel_sdvo_connector->bottom_margin = temp_value;
2139 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2140 intel_sdvo_connector->top_margin;
b9219c5e 2141 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2142 goto set_value;
2143 } else if (intel_sdvo_connector->bottom == property) {
662595df 2144 drm_object_property_set_value(&connector->base,
c5521706 2145 intel_sdvo_connector->top, val);
615fb93f 2146 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2147 return 0;
2148
615fb93f
CW		 2149 intel_sdvo_connector->top_margin = temp_value;
2150 intel_sdvo_connector->bottom_margin = temp_value;
2151 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2152 intel_sdvo_connector->top_margin;
b9219c5e 2153 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2154 goto set_value;
2155 }
2156 CHECK_PROPERTY(hpos, HPOS)
2157 CHECK_PROPERTY(vpos, VPOS)
2158 CHECK_PROPERTY(saturation, SATURATION)
2159 CHECK_PROPERTY(contrast, CONTRAST)
2160 CHECK_PROPERTY(hue, HUE)
2161 CHECK_PROPERTY(brightness, BRIGHTNESS)
2162 CHECK_PROPERTY(sharpness, SHARPNESS)
2163 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2164 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2165 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2166 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2167 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2168 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2169 }
b9219c5e 2170
c5521706 2171 return -EINVAL; /* unknown property */
b9219c5e 2172
c5521706
CW		 2173set_value:
2174 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2175 return -EIO;
b9219c5e 2176
b9219c5e 2177
c5521706 2178done:
c0c36b94
CW		 2179 if (intel_sdvo->base.base.crtc)
2180 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2181
32aad86f 2182 return 0;
c5521706 2183#undef CHECK_PROPERTY
ce6feabd
ZY		 2184}
2185
7a418e34
CW		 2186static int
2187intel_sdvo_connector_register(struct drm_connector *connector)
2188{
2189 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1ebaa0b9
CW		 2190 int ret;
2191
2192 ret = intel_connector_register(connector);
2193 if (ret)
2194 return ret;
7a418e34
CW		 2195
2196 return sysfs_create_link(&connector->kdev->kobj,
2197 &sdvo->ddc.dev.kobj,
2198 sdvo->ddc.dev.kobj.name);
2199}
2200
c191eca1
CW		 2201static void
2202intel_sdvo_connector_unregister(struct drm_connector *connector)
2203{
2204 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2205
2206 sysfs_remove_link(&connector->kdev->kobj,
2207 sdvo->ddc.dev.kobj.name);
2208 intel_connector_unregister(connector);
2209}
2210
79e53945 2211static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
4d688a2a 2212 .dpms = drm_atomic_helper_connector_dpms,
79e53945
JB		 2213 .detect = intel_sdvo_detect,
2214 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2215 .set_property = intel_sdvo_set_property,
2545e4a6 2216 .atomic_get_property = intel_connector_atomic_get_property,
7a418e34 2217 .late_register = intel_sdvo_connector_register,
c191eca1 2218 .early_unregister = intel_sdvo_connector_unregister,
79e53945 2219 .destroy = intel_sdvo_destroy,
c6f95f27 2220 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 2221 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
79e53945
JB		 2222};
2223
2224static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2225 .get_modes = intel_sdvo_get_modes,
2226 .mode_valid = intel_sdvo_mode_valid,
79e53945
JB		 2227};
2228
b358d0a6 2229static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2230{
8aca63aa 2231 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2232
ea5b213a 2233 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2234 drm_mode_destroy(encoder->dev,
ea5b213a 2235 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2236
e957d772 2237 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2238 intel_encoder_destroy(encoder);
79e53945
JB		 2239}
2240
2241static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2242 .destroy = intel_sdvo_enc_destroy,
2243};
2244
b66d8424
CW		 2245static void
2246intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2247{
2248 uint16_t mask = 0;
2249 unsigned int num_bits;
2250
2251 /* Make a mask of outputs less than or equal to our own priority in the
2252 * list.
2253 */
2254 switch (sdvo->controlled_output) {
2255 case SDVO_OUTPUT_LVDS1:
2256 mask |= SDVO_OUTPUT_LVDS1;
2257 case SDVO_OUTPUT_LVDS0:
2258 mask |= SDVO_OUTPUT_LVDS0;
2259 case SDVO_OUTPUT_TMDS1:
2260 mask |= SDVO_OUTPUT_TMDS1;
2261 case SDVO_OUTPUT_TMDS0:
2262 mask |= SDVO_OUTPUT_TMDS0;
2263 case SDVO_OUTPUT_RGB1:
2264 mask |= SDVO_OUTPUT_RGB1;
2265 case SDVO_OUTPUT_RGB0:
2266 mask |= SDVO_OUTPUT_RGB0;
2267 break;
2268 }
2269
2270 /* Count bits to find what number we are in the priority list. */
2271 mask &= sdvo->caps.output_flags;
2272 num_bits = hweight16(mask);
2273 /* If more than 3 outputs, default to DDC bus 3 for now. */
2274 if (num_bits > 3)
2275 num_bits = 3;
2276
2277 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2278 sdvo->ddc_bus = 1 << num_bits;
2279}
79e53945 2280
e2f0ba97
JB		 2281/**
2282 * Choose the appropriate DDC bus for control bus switch command for this
2283 * SDVO output based on the controlled output.
2284 *
2285 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2286 * outputs, then LVDS outputs.
2287 */
2288static void
b1083333 2289intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
8bd864b8 2290 struct intel_sdvo *sdvo)
e2f0ba97 2291{
b1083333 2292 struct sdvo_device_mapping *mapping;
e2f0ba97 2293
2a5c0832 2294 if (sdvo->port == PORT_B)
9d6c875d 2295 mapping = &dev_priv->vbt.sdvo_mappings[0];
b1083333 2296 else
9d6c875d 2297 mapping = &dev_priv->vbt.sdvo_mappings[1];
e2f0ba97 2298
b66d8424
CW		 2299 if (mapping->initialized)
2300 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2301 else
2302 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2303}
2304
e957d772
CW		 2305static void
2306intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
8bd864b8 2307 struct intel_sdvo *sdvo)
e957d772
CW		 2308{
2309 struct sdvo_device_mapping *mapping;
46eb3036 2310 u8 pin;
e957d772 2311
2a5c0832 2312 if (sdvo->port == PORT_B)
9d6c875d 2313 mapping = &dev_priv->vbt.sdvo_mappings[0];
e957d772 2314 else
9d6c875d 2315 mapping = &dev_priv->vbt.sdvo_mappings[1];
e957d772 2316
88ac7939
JN		 2317 if (mapping->initialized &&
2318 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
e957d772 2319 pin = mapping->i2c_pin;
6cb1612a 2320 else
988c7015 2321 pin = GMBUS_PIN_DPB;
e957d772 2322
6cb1612a
JN		 2323 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2324
2325 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2326 * our code totally fails once we start using gmbus. Hence fall back to
2327 * bit banging for now. */
2328 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2329}
2330
fbfcc4f3
JN		 2331/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2332static void
2333intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2334{
2335 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2336}
2337
e2f0ba97 2338static bool
e27d8538 2339intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2340{
97aaf910 2341 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2342}
2343
714605e4 2344static u8
eef4eacb 2345intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2346{
fac5e23e 2347 struct drm_i915_private *dev_priv = to_i915(dev);
714605e4 2348 struct sdvo_device_mapping *my_mapping, *other_mapping;
2349
2a5c0832 2350 if (sdvo->port == PORT_B) {
9d6c875d
JN		 2351 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2352 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
714605e4 2353 } else {
9d6c875d
JN		 2354 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2355 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
714605e4 2356 }
2357
2358 /* If the BIOS described our SDVO device, take advantage of it. */
2359 if (my_mapping->slave_addr)
2360 return my_mapping->slave_addr;
2361
2362 /* If the BIOS only described a different SDVO device, use the
2363 * address that it isn't using.
2364 */
2365 if (other_mapping->slave_addr) {
2366 if (other_mapping->slave_addr == 0x70)
2367 return 0x72;
2368 else
2369 return 0x70;
2370 }
2371
2372 /* No SDVO device info is found for another DVO port,
2373 * so use mapping assumption we had before BIOS parsing.
2374 */
2a5c0832 2375 if (sdvo->port == PORT_B)
714605e4 2376 return 0x70;
2377 else
2378 return 0x72;
2379}
2380
c393454d 2381static int
df0e9248
CW		 2382intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2383 struct intel_sdvo *encoder)
14571b4c 2384{
c393454d
ID		 2385 struct drm_connector *drm_connector;
2386 int ret;
2387
2388 drm_connector = &connector->base.base;
2389 ret = drm_connector_init(encoder->base.base.dev,
2390 drm_connector,
df0e9248
CW		 2391 &intel_sdvo_connector_funcs,
2392 connector->base.base.connector_type);
c393454d
ID		 2393 if (ret < 0)
2394 return ret;
6070a4a9 2395
c393454d 2396 drm_connector_helper_add(drm_connector,
df0e9248 2397 &intel_sdvo_connector_helper_funcs);
14571b4c 2398
8f4839e2 2399 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2400 connector->base.base.doublescan_allowed = 0;
2401 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2402 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2403
df0e9248 2404 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2405
2406 return 0;
14571b4c 2407}
6070a4a9 2408
7f36e7ed 2409static void
55bc60db
VS		 2410intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2411 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2412{
2413 struct drm_device *dev = connector->base.base.dev;
2414
3f43c48d 2415 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2416 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2417 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2418 intel_sdvo->color_range_auto = true;
2419 }
7949dd47
VS		 2420 intel_attach_aspect_ratio_property(&connector->base.base);
2421 intel_sdvo->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
7f36e7ed
CW		 2422}
2423
08d9bc92
ACO		 2424static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2425{
2426 struct intel_sdvo_connector *sdvo_connector;
2427
2428 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2429 if (!sdvo_connector)
2430 return NULL;
2431
2432 if (intel_connector_init(&sdvo_connector->base) < 0) {
2433 kfree(sdvo_connector);
2434 return NULL;
2435 }
2436
2437 return sdvo_connector;
2438}
2439
fb7a46f3 2440static bool
ea5b213a 2441intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2442{
4ef69c7a 2443 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2444 struct drm_connector *connector;
cc68c81a 2445 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2446 struct intel_connector *intel_connector;
615fb93f 2447 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2448
46a3f4a3
CW		 2449 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2450
08d9bc92 2451 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f 2452 if (!intel_sdvo_connector)
14571b4c
ZW		 2453 return false;
2454
14571b4c 2455 if (device == 0) {
ea5b213a 2456 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2457 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2458 } else if (device == 1) {
ea5b213a 2459 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2460 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2461 }
2462
615fb93f 2463 intel_connector = &intel_sdvo_connector->base;
14571b4c 2464 connector = &intel_connector->base;
5fa7ac9c
JN		 2465 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2466 intel_sdvo_connector->output_flag) {
5fa7ac9c 2467 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2468 /* Some SDVO devices have one-shot hotplug interrupts.
2469 * Ensure that they get re-enabled when an interrupt happens.
2470 */
2471 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
3a2fb2c3 2472 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2473 } else {
821450c6 2474 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2475 }
14571b4c
ZW		 2476 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2477 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2478
e27d8538 2479 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2480 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2481 intel_sdvo->is_hdmi = true;
14571b4c 2482 }
14571b4c 2483
c393454d
ID		 2484 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2485 kfree(intel_sdvo_connector);
2486 return false;
2487 }
2488
f797d221 2489 if (intel_sdvo->is_hdmi)
55bc60db 2490 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2491
2492 return true;
2493}
2494
2495static bool
ea5b213a 2496intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2497{
4ef69c7a
CW		 2498 struct drm_encoder *encoder = &intel_sdvo->base.base;
2499 struct drm_connector *connector;
2500 struct intel_connector *intel_connector;
2501 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2502
46a3f4a3
CW		 2503 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2504
08d9bc92 2505 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2506 if (!intel_sdvo_connector)
2507 return false;
14571b4c 2508
615fb93f 2509 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2510 connector = &intel_connector->base;
2511 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2512 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2513
4ef69c7a
CW		 2514 intel_sdvo->controlled_output |= type;
2515 intel_sdvo_connector->output_flag = type;
14571b4c 2516
4ef69c7a 2517 intel_sdvo->is_tv = true;
14571b4c 2518
c393454d
ID		 2519 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2520 kfree(intel_sdvo_connector);
2521 return false;
2522 }
14571b4c 2523
4ef69c7a 2524 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2525 goto err;
14571b4c 2526
4ef69c7a 2527 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2528 goto err;
14571b4c 2529
4ef69c7a 2530 return true;
32aad86f
CW		 2531
2532err:
123d5c01 2533 intel_sdvo_destroy(connector);
32aad86f 2534 return false;
14571b4c
ZW		 2535}
2536
2537static bool
ea5b213a 2538intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2539{
4ef69c7a
CW		 2540 struct drm_encoder *encoder = &intel_sdvo->base.base;
2541 struct drm_connector *connector;
2542 struct intel_connector *intel_connector;
2543 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2544
46a3f4a3
CW		 2545 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2546
8ce7da47 2547 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2548 if (!intel_sdvo_connector)
2549 return false;
14571b4c 2550
615fb93f 2551 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2552 connector = &intel_connector->base;
821450c6 2553 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2554 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2555 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2556
2557 if (device == 0) {
2558 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2559 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2560 } else if (device == 1) {
2561 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2562 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2563 }
2564
c393454d
ID		 2565 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2566 kfree(intel_sdvo_connector);
2567 return false;
2568 }
2569
4ef69c7a 2570 return true;
14571b4c
ZW		 2571}
2572
2573static bool
ea5b213a 2574intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2575{
4ef69c7a
CW		 2576 struct drm_encoder *encoder = &intel_sdvo->base.base;
2577 struct drm_connector *connector;
2578 struct intel_connector *intel_connector;
2579 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2580
46a3f4a3
CW		 2581 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2582
08d9bc92 2583 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2584 if (!intel_sdvo_connector)
2585 return false;
14571b4c 2586
615fb93f
CW		 2587 intel_connector = &intel_sdvo_connector->base;
2588 connector = &intel_connector->base;
4ef69c7a
CW		 2589 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2590 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2591
2592 if (device == 0) {
2593 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2594 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2595 } else if (device == 1) {
2596 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2597 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2598 }
2599
c393454d
ID		 2600 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2601 kfree(intel_sdvo_connector);
2602 return false;
2603 }
2604
4ef69c7a 2605 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2606 goto err;
2607
2608 return true;
2609
2610err:
123d5c01 2611 intel_sdvo_destroy(connector);
32aad86f 2612 return false;
14571b4c
ZW		 2613}
2614
2615static bool
ea5b213a 2616intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2617{
ea5b213a 2618 intel_sdvo->is_tv = false;
ea5b213a 2619 intel_sdvo->is_lvds = false;
fb7a46f3 2620
14571b4c 2621 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2622
14571b4c 2623 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2624 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2625 return false;
2626
2627 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2628 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2629 return false;
2630
2631 /* TV has no XXX1 function block */
a1f4b7ff 2632 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2633 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2634 return false;
2635
2636 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2637 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2638 return false;
fb7a46f3 2639
a0b1c7a5
CW		 2640 if (flags & SDVO_OUTPUT_YPRPB0)
2641 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2642 return false;
2643
14571b4c 2644 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2645 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2646 return false;
2647
2648 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2649 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2650 return false;
2651
2652 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2653 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2654 return false;
2655
2656 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2657 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2658 return false;
fb7a46f3 2659
14571b4c 2660 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2661 unsigned char bytes[2];
2662
ea5b213a
CW		 2663 intel_sdvo->controlled_output = 0;
2664 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2665 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2666 SDVO_NAME(intel_sdvo),
51c8b407 2667 bytes[0], bytes[1]);
14571b4c 2668 return false;
fb7a46f3 2669 }
27f8227b 2670 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2671
14571b4c 2672 return true;
fb7a46f3 2673}
2674
d0ddfbd3
JN		 2675static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2676{
2677 struct drm_device *dev = intel_sdvo->base.base.dev;
2678 struct drm_connector *connector, *tmp;
2679
2680 list_for_each_entry_safe(connector, tmp,
2681 &dev->mode_config.connector_list, head) {
d9255d57 2682 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
34ea3d38 2683 drm_connector_unregister(connector);
d0ddfbd3 2684 intel_sdvo_destroy(connector);
d9255d57 2685 }
d0ddfbd3
JN		 2686 }
2687}
2688
32aad86f
CW		 2689static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2690 struct intel_sdvo_connector *intel_sdvo_connector,
2691 int type)
ce6feabd 2692{
4ef69c7a 2693 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2694 struct intel_sdvo_tv_format format;
2695 uint32_t format_map, i;
ce6feabd 2696
32aad86f
CW		 2697 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2698 return false;
ce6feabd 2699
1a3665c8 2700 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2701 if (!intel_sdvo_get_value(intel_sdvo,
2702 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2703 &format, sizeof(format)))
2704 return false;
ce6feabd 2705
32aad86f 2706 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2707
2708 if (format_map == 0)
32aad86f 2709 return false;
ce6feabd 2710
615fb93f 2711 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2712 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2713 if (format_map & (1 << i))
2714 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2715
2716
c5521706 2717 intel_sdvo_connector->tv_format =
32aad86f
CW		 2718 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2719 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2720 if (!intel_sdvo_connector->tv_format)
fcc8d672 2721 return false;
ce6feabd 2722
615fb93f 2723 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2724 drm_property_add_enum(
c5521706 2725 intel_sdvo_connector->tv_format, i,
40039750 2726 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2727
40039750 2728 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2729 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2730 intel_sdvo_connector->tv_format, 0);
32aad86f 2731 return true;
ce6feabd
ZY		 2732
2733}
2734
c5521706
CW		 2735#define ENHANCEMENT(name, NAME) do { \
2736 if (enhancements.name) { \
2737 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2738 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2739 return false; \
2740 intel_sdvo_connector->max_##name = data_value[0]; \
2741 intel_sdvo_connector->cur_##name = response; \
2742 intel_sdvo_connector->name = \
d9bc3c02 2743 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2744 if (!intel_sdvo_connector->name) return false; \
662595df 2745 drm_object_attach_property(&connector->base, \
c5521706
CW		 2746 intel_sdvo_connector->name, \
2747 intel_sdvo_connector->cur_##name); \
2748 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2749 data_value[0], data_value[1], response); \
2750 } \
0206e353 2751} while (0)
c5521706
CW		 2752
2753static bool
2754intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2755 struct intel_sdvo_connector *intel_sdvo_connector,
2756 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2757{
4ef69c7a 2758 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2759 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2760 uint16_t response, data_value[2];
2761
c5521706
CW		 2762 /* when horizontal overscan is supported, Add the left/right property */
2763 if (enhancements.overscan_h) {
2764 if (!intel_sdvo_get_value(intel_sdvo,
2765 SDVO_CMD_GET_MAX_OVERSCAN_H,
2766 &data_value, 4))
2767 return false;
32aad86f 2768
c5521706
CW		 2769 if (!intel_sdvo_get_value(intel_sdvo,
2770 SDVO_CMD_GET_OVERSCAN_H,
2771 &response, 2))
2772 return false;
fcc8d672 2773
c5521706
CW		 2774 intel_sdvo_connector->max_hscan = data_value[0];
2775 intel_sdvo_connector->left_margin = data_value[0] - response;
2776 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2777 intel_sdvo_connector->left =
d9bc3c02 2778 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2779 if (!intel_sdvo_connector->left)
2780 return false;
fcc8d672 2781
662595df 2782 drm_object_attach_property(&connector->base,
c5521706
CW		 2783 intel_sdvo_connector->left,
2784 intel_sdvo_connector->left_margin);
fcc8d672 2785
c5521706 2786 intel_sdvo_connector->right =
d9bc3c02 2787 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2788 if (!intel_sdvo_connector->right)
2789 return false;
32aad86f 2790
662595df 2791 drm_object_attach_property(&connector->base,
c5521706
CW		 2792 intel_sdvo_connector->right,
2793 intel_sdvo_connector->right_margin);
2794 DRM_DEBUG_KMS("h_overscan: max %d, "
2795 "default %d, current %d\n",
2796 data_value[0], data_value[1], response);
2797 }
32aad86f 2798
c5521706
CW		 2799 if (enhancements.overscan_v) {
2800 if (!intel_sdvo_get_value(intel_sdvo,
2801 SDVO_CMD_GET_MAX_OVERSCAN_V,
2802 &data_value, 4))
2803 return false;
fcc8d672 2804
c5521706
CW		 2805 if (!intel_sdvo_get_value(intel_sdvo,
2806 SDVO_CMD_GET_OVERSCAN_V,
2807 &response, 2))
2808 return false;
32aad86f 2809
c5521706
CW		 2810 intel_sdvo_connector->max_vscan = data_value[0];
2811 intel_sdvo_connector->top_margin = data_value[0] - response;
2812 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2813 intel_sdvo_connector->top =
d9bc3c02
SH		 2814 drm_property_create_range(dev, 0,
2815 "top_margin", 0, data_value[0]);
c5521706
CW		 2816 if (!intel_sdvo_connector->top)
2817 return false;
32aad86f 2818
662595df 2819 drm_object_attach_property(&connector->base,
c5521706
CW		 2820 intel_sdvo_connector->top,
2821 intel_sdvo_connector->top_margin);
fcc8d672 2822
c5521706 2823 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2824 drm_property_create_range(dev, 0,
2825 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2826 if (!intel_sdvo_connector->bottom)
2827 return false;
32aad86f 2828
662595df 2829 drm_object_attach_property(&connector->base,
c5521706
CW		 2830 intel_sdvo_connector->bottom,
2831 intel_sdvo_connector->bottom_margin);
2832 DRM_DEBUG_KMS("v_overscan: max %d, "
2833 "default %d, current %d\n",
2834 data_value[0], data_value[1], response);
2835 }
32aad86f 2836
c5521706
CW		 2837 ENHANCEMENT(hpos, HPOS);
2838 ENHANCEMENT(vpos, VPOS);
2839 ENHANCEMENT(saturation, SATURATION);
2840 ENHANCEMENT(contrast, CONTRAST);
2841 ENHANCEMENT(hue, HUE);
2842 ENHANCEMENT(sharpness, SHARPNESS);
2843 ENHANCEMENT(brightness, BRIGHTNESS);
2844 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2845 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2846 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2847 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2848 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2849
e044218a
CW		 2850 if (enhancements.dot_crawl) {
2851 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2852 return false;
2853
2854 intel_sdvo_connector->max_dot_crawl = 1;
2855 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2856 intel_sdvo_connector->dot_crawl =
d9bc3c02 2857 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2858 if (!intel_sdvo_connector->dot_crawl)
2859 return false;
2860
662595df 2861 drm_object_attach_property(&connector->base,
e044218a
CW		 2862 intel_sdvo_connector->dot_crawl,
2863 intel_sdvo_connector->cur_dot_crawl);
2864 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2865 }
2866
c5521706
CW		 2867 return true;
2868}
32aad86f 2869
c5521706
CW		 2870static bool
2871intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2872 struct intel_sdvo_connector *intel_sdvo_connector,
2873 struct intel_sdvo_enhancements_reply enhancements)
2874{
4ef69c7a 2875 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2876 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2877 uint16_t response, data_value[2];
32aad86f 2878
c5521706 2879 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2880
c5521706
CW		 2881 return true;
2882}
2883#undef ENHANCEMENT
32aad86f 2884
c5521706
CW		 2885static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2886 struct intel_sdvo_connector *intel_sdvo_connector)
2887{
2888 union {
2889 struct intel_sdvo_enhancements_reply reply;
2890 uint16_t response;
2891 } enhancements;
32aad86f 2892
1a3665c8
CW		 2893 BUILD_BUG_ON(sizeof(enhancements) != 2);
2894
cf9a2f3a
CW		 2895 enhancements.response = 0;
2896 intel_sdvo_get_value(intel_sdvo,
2897 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2898 &enhancements, sizeof(enhancements));
c5521706
CW		 2899 if (enhancements.response == 0) {
2900 DRM_DEBUG_KMS("No enhancement is supported\n");
2901 return true;
b9219c5e 2902 }
32aad86f 2903
c5521706
CW		 2904 if (IS_TV(intel_sdvo_connector))
2905 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2906 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2907 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2908 else
2909 return true;
e957d772
CW		 2910}
2911
2912static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2913 struct i2c_msg *msgs,
2914 int num)
2915{
2916 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2917
e957d772
CW		 2918 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2919 return -EIO;
2920
2921 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2922}
2923
2924static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2925{
2926 struct intel_sdvo *sdvo = adapter->algo_data;
2927 return sdvo->i2c->algo->functionality(sdvo->i2c);
2928}
2929
2930static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2931 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2932 .functionality = intel_sdvo_ddc_proxy_func
2933};
2934
2935static bool
2936intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2937 struct drm_device *dev)
2938{
52a05c30
DW		 2939 struct pci_dev *pdev = dev->pdev;
2940
e957d772
CW		 2941 sdvo->ddc.owner = THIS_MODULE;
2942 sdvo->ddc.class = I2C_CLASS_DDC;
2943 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
52a05c30 2944 sdvo->ddc.dev.parent = &pdev->dev;
e957d772
CW		 2945 sdvo->ddc.algo_data = sdvo;
2946 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2947
2948 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2949}
2950
2a5c0832
VS		 2951static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
2952 enum port port)
2953{
2954 if (HAS_PCH_SPLIT(dev_priv))
2955 WARN_ON(port != PORT_B);
2956 else
2957 WARN_ON(port != PORT_B && port != PORT_C);
2958}
2959
f0f59a00
VS		 2960bool intel_sdvo_init(struct drm_device *dev,
2961 i915_reg_t sdvo_reg, enum port port)
79e53945 2962{
fac5e23e 2963 struct drm_i915_private *dev_priv = to_i915(dev);
21d40d37 2964 struct intel_encoder *intel_encoder;
ea5b213a 2965 struct intel_sdvo *intel_sdvo;
79e53945 2966 int i;
2a5c0832
VS		 2967
2968 assert_sdvo_port_valid(dev_priv, port);
2969
b14c5679 2970 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 2971 if (!intel_sdvo)
7d57382e 2972 return false;
79e53945 2973
56184e3d 2974 intel_sdvo->sdvo_reg = sdvo_reg;
2a5c0832 2975 intel_sdvo->port = port;
eef4eacb 2976 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
8bd864b8 2977 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
fbfcc4f3
JN		 2978 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2979 goto err_i2c_bus;
e957d772 2980
56184e3d 2981 /* encoder type will be decided later */
ea5b213a 2982 intel_encoder = &intel_sdvo->base;
21d40d37 2983 intel_encoder->type = INTEL_OUTPUT_SDVO;
13a3d91f 2984 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0,
580d8ed5 2985 "SDVO %c", port_name(port));
79e53945 2986
79e53945
JB		 2987 /* Read the regs to test if we can talk to the device */
2988 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2989 u8 byte;
2990
2991 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2992 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2993 SDVO_NAME(intel_sdvo));
f899fc64 2994 goto err;
79e53945
JB		 2995 }
2996 }
2997
6cc5f341 2998 intel_encoder->compute_config = intel_sdvo_compute_config;
3c65d1d1
VS		 2999 if (HAS_PCH_SPLIT(dev)) {
3000 intel_encoder->disable = pch_disable_sdvo;
3001 intel_encoder->post_disable = pch_post_disable_sdvo;
3002 } else {
3003 intel_encoder->disable = intel_disable_sdvo;
3004 }
192d47a6 3005 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 3006 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3007 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3008 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3009
af901ca1 3010 /* In default case sdvo lvds is false */
32aad86f 3011 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3012 goto err;
79e53945 3013
ea5b213a
CW		 3014 if (intel_sdvo_output_setup(intel_sdvo,
3015 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3016 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3017 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3018 /* Output_setup can leave behind connectors! */
3019 goto err_output;
79e53945
JB		 3020 }
3021
7ba220ce
CW		 3022 /* Only enable the hotplug irq if we need it, to work around noisy
3023 * hotplug lines.
3024 */
3025 if (intel_sdvo->hotplug_active) {
2a5c0832
VS		 3026 if (intel_sdvo->port == PORT_B)
3027 intel_encoder->hpd_pin = HPD_SDVO_B;
3028 else
3029 intel_encoder->hpd_pin = HPD_SDVO_C;
7ba220ce
CW		 3030 }
3031
e506d6fd
DV		 3032 /*
3033 * Cloning SDVO with anything is often impossible, since the SDVO
3034 * encoder can request a special input timing mode. And even if that's
3035 * not the case we have evidence that cloning a plain unscaled mode with
3036 * VGA doesn't really work. Furthermore the cloning flags are way too
3037 * simplistic anyway to express such constraints, so just give up on
3038 * cloning for SDVO encoders.
3039 */
bc079e8b 3040 intel_sdvo->base.cloneable = 0;
e506d6fd 3041
8bd864b8 3042 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
e2f0ba97 3043
79e53945 3044 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3045 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3046 goto err_output;
79e53945 3047
32aad86f
CW		 3048 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3049 &intel_sdvo->pixel_clock_min,
3050 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3051 goto err_output;
79e53945 3052
8a4c47f3 3053 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3054 "clock range %dMHz - %dMHz, "
3055 "input 1: %c, input 2: %c, "
3056 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3057 SDVO_NAME(intel_sdvo),
3058 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3059 intel_sdvo->caps.device_rev_id,
3060 intel_sdvo->pixel_clock_min / 1000,
3061 intel_sdvo->pixel_clock_max / 1000,
3062 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3063 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3064 /* check currently supported outputs */
ea5b213a 3065 intel_sdvo->caps.output_flags &
79e53945 3066 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3067 intel_sdvo->caps.output_flags &
79e53945 3068 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3069 return true;
79e53945 3070
d0ddfbd3
JN		 3071err_output:
3072 intel_sdvo_output_cleanup(intel_sdvo);
3073
f899fc64 3074err:
373a3cf7 3075 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3076 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3077err_i2c_bus:
3078 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3079 kfree(intel_sdvo);
79e53945 3080
7d57382e 3081 return false;
79e53945 3082}
Linux kernel - Deliverables
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