[deliverable/linux.git] / drivers / gpu / drm / imx / ipuv3-plane.c

/*
 * i.MX IPUv3 DP Overlay Planes
 *
 * Copyright (C) 2013 Philipp Zabel, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <drm/drmP.h>
#include <drm/drm_fb_cma_helper.h>
#include <drm/drm_gem_cma_helper.h>

#include "video/imx-ipu-v3.h"
#include "ipuv3-plane.h"

#define to_ipu_plane(x)	container_of(x, struct ipu_plane, base)

static const uint32_t ipu_plane_formats[] = {
	DRM_FORMAT_ARGB1555,
	DRM_FORMAT_XRGB1555,
	DRM_FORMAT_ABGR1555,
	DRM_FORMAT_XBGR1555,
	DRM_FORMAT_RGBA5551,
	DRM_FORMAT_BGRA5551,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_RGBA8888,
	DRM_FORMAT_RGBX8888,
	DRM_FORMAT_BGRA8888,
	DRM_FORMAT_BGRA8888,
	DRM_FORMAT_YUYV,
	DRM_FORMAT_YVYU,
	DRM_FORMAT_YUV420,
	DRM_FORMAT_YVU420,
};

int ipu_plane_irq(struct ipu_plane *ipu_plane)
{
	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
				     IPU_IRQ_EOF);
}

static int calc_vref(struct drm_display_mode *mode)
{
	unsigned long htotal, vtotal;

	htotal = mode->htotal;
	vtotal = mode->vtotal;

	if (!htotal || !vtotal)
		return 60;

	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
}

static inline int calc_bandwidth(int width, int height, unsigned int vref)
{
	return width * height * vref;
}

int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
		       int x, int y)
{
	struct drm_gem_cma_object *cma_obj;
	unsigned long eba;
	int active;

	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	if (!cma_obj) {
		DRM_DEBUG_KMS("entry is null.\n");
		return -EFAULT;
	}

	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
		&cma_obj->paddr, x, y);

	eba = cma_obj->paddr + fb->offsets[0] +
	      fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;

	if (ipu_plane->enabled) {
		active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
		ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
	} else {
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
	}

	/* cache offsets for subsequent pageflips */
	ipu_plane->x = x;
	ipu_plane->y = y;

	return 0;
}

int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
		       struct drm_display_mode *mode,
		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
		       unsigned int crtc_w, unsigned int crtc_h,
		       uint32_t src_x, uint32_t src_y,
		       uint32_t src_w, uint32_t src_h, bool interlaced)
{
	struct device *dev = ipu_plane->base.dev->dev;
	int ret;

	/* no scaling */
	if (src_w != crtc_w || src_h != crtc_h)
		return -EINVAL;

	/* clip to crtc bounds */
	if (crtc_x < 0) {
		if (-crtc_x > crtc_w)
			return -EINVAL;
		src_x += -crtc_x;
		src_w -= -crtc_x;
		crtc_w -= -crtc_x;
		crtc_x = 0;
	}
	if (crtc_y < 0) {
		if (-crtc_y > crtc_h)
			return -EINVAL;
		src_y += -crtc_y;
		src_h -= -crtc_y;
		crtc_h -= -crtc_y;
		crtc_y = 0;
	}
	if (crtc_x + crtc_w > mode->hdisplay) {
		if (crtc_x > mode->hdisplay)
			return -EINVAL;
		crtc_w = mode->hdisplay - crtc_x;
		src_w = crtc_w;
	}
	if (crtc_y + crtc_h > mode->vdisplay) {
		if (crtc_y > mode->vdisplay)
			return -EINVAL;
		crtc_h = mode->vdisplay - crtc_y;
		src_h = crtc_h;
	}
	/* full plane minimum width is 13 pixels */
	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
		return -EINVAL;
	if (crtc_h < 2)
		return -EINVAL;

	/*
	 * since we cannot touch active IDMAC channels, we do not support
	 * resizing the enabled plane or changing its format
	 */
	if (ipu_plane->enabled) {
		if (src_w != ipu_plane->w || src_h != ipu_plane->h ||
		    fb->pixel_format != ipu_plane->base.fb->pixel_format)
			return -EINVAL;

		return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	}

	switch (ipu_plane->dp_flow) {
	case IPU_DP_FLOW_SYNC_BG:
		ret = ipu_dp_setup_channel(ipu_plane->dp,
				IPUV3_COLORSPACE_RGB,
				IPUV3_COLORSPACE_RGB);
		if (ret) {
			dev_err(dev,
				"initializing display processor failed with %d\n",
				ret);
			return ret;
		}
		ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
		break;
	case IPU_DP_FLOW_SYNC_FG:
		ipu_dp_setup_channel(ipu_plane->dp,
				ipu_drm_fourcc_to_colorspace(fb->pixel_format),
				IPUV3_COLORSPACE_UNKNOWN);
		ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
		/* Enable local alpha on partial plane */
		switch (fb->pixel_format) {
		case DRM_FORMAT_ARGB1555:
		case DRM_FORMAT_ABGR1555:
		case DRM_FORMAT_RGBA5551:
		case DRM_FORMAT_BGRA5551:
		case DRM_FORMAT_ARGB8888:
		case DRM_FORMAT_ABGR8888:
		case DRM_FORMAT_RGBA8888:
		case DRM_FORMAT_BGRA8888:
			ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
			break;
		default:
			break;
		}
	}

	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	if (ret) {
		dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
		return ret;
	}

	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
			calc_bandwidth(crtc_w, crtc_h,
				       calc_vref(mode)), 64);
	if (ret) {
		dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
		return ret;
	}

	ipu_cpmem_zero(ipu_plane->ipu_ch);
	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
	if (ret < 0) {
		dev_err(dev, "unsupported pixel format 0x%08x\n",
			fb->pixel_format);
		return ret;
	}
	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);

	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	if (ret < 0)
		return ret;
	if (interlaced)
		ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);

	ipu_plane->w = src_w;
	ipu_plane->h = src_h;

	return 0;
}

void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
{
	if (!IS_ERR_OR_NULL(ipu_plane->dp))
		ipu_dp_put(ipu_plane->dp);
	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
		ipu_dmfc_put(ipu_plane->dmfc);
	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
		ipu_idmac_put(ipu_plane->ipu_ch);
}

int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
{
	int ret;

	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->ipu_ch)) {
		ret = PTR_ERR(ipu_plane->ipu_ch);
		DRM_ERROR("failed to get idmac channel: %d\n", ret);
		return ret;
	}

	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	if (IS_ERR(ipu_plane->dmfc)) {
		ret = PTR_ERR(ipu_plane->dmfc);
		DRM_ERROR("failed to get dmfc: ret %d\n", ret);
		goto err_out;
	}

	if (ipu_plane->dp_flow >= 0) {
		ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
		if (IS_ERR(ipu_plane->dp)) {
			ret = PTR_ERR(ipu_plane->dp);
			DRM_ERROR("failed to get dp flow: %d\n", ret);
			goto err_out;
		}
	}

	return 0;
err_out:
	ipu_plane_put_resources(ipu_plane);

	return ret;
}

void ipu_plane_enable(struct ipu_plane *ipu_plane)
{
	if (ipu_plane->dp)
		ipu_dp_enable(ipu_plane->ipu);
	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	if (ipu_plane->dp)
		ipu_dp_enable_channel(ipu_plane->dp);

	ipu_plane->enabled = true;
}

void ipu_plane_disable(struct ipu_plane *ipu_plane)
{
	ipu_plane->enabled = false;

	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);

	if (ipu_plane->dp)
		ipu_dp_disable_channel(ipu_plane->dp);
	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	ipu_dmfc_disable_channel(ipu_plane->dmfc);
	if (ipu_plane->dp)
		ipu_dp_disable(ipu_plane->ipu);
}

/*
 * drm_plane API
 */

static int ipu_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
			    struct drm_framebuffer *fb, int crtc_x, int crtc_y,
			    unsigned int crtc_w, unsigned int crtc_h,
			    uint32_t src_x, uint32_t src_y,
			    uint32_t src_w, uint32_t src_h)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	int ret = 0;

	DRM_DEBUG_KMS("plane - %p\n", plane);

	if (!ipu_plane->enabled)
		ret = ipu_plane_get_resources(ipu_plane);
	if (ret < 0)
		return ret;

	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
			crtc_x, crtc_y, crtc_w, crtc_h,
			src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
			false);
	if (ret < 0) {
		ipu_plane_put_resources(ipu_plane);
		return ret;
	}

	if (crtc != plane->crtc)
		dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
				plane->crtc, crtc);
	plane->crtc = crtc;

	if (!ipu_plane->enabled)
		ipu_plane_enable(ipu_plane);

	return 0;
}

static int ipu_disable_plane(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	if (ipu_plane->enabled)
		ipu_plane_disable(ipu_plane);

	ipu_plane_put_resources(ipu_plane);

	return 0;
}

static void ipu_plane_destroy(struct drm_plane *plane)
{
	struct ipu_plane *ipu_plane = to_ipu_plane(plane);

	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);

	ipu_disable_plane(plane);
	drm_plane_cleanup(plane);
	kfree(ipu_plane);
}

static struct drm_plane_funcs ipu_plane_funcs = {
	.update_plane	= ipu_update_plane,
	.disable_plane	= ipu_disable_plane,
	.destroy	= ipu_plane_destroy,
};

struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
				 int dma, int dp, unsigned int possible_crtcs,
				 bool priv)
{
	struct ipu_plane *ipu_plane;
	int ret;

	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
		      dma, dp, possible_crtcs);

	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	if (!ipu_plane) {
		DRM_ERROR("failed to allocate plane\n");
		return ERR_PTR(-ENOMEM);
	}

	ipu_plane->ipu = ipu;
	ipu_plane->dma = dma;
	ipu_plane->dp_flow = dp;

	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
			     &ipu_plane_funcs, ipu_plane_formats,
			     ARRAY_SIZE(ipu_plane_formats),
			     priv);
	if (ret) {
		DRM_ERROR("failed to initialize plane\n");
		kfree(ipu_plane);
		return ERR_PTR(ret);
	}

	return ipu_plane;
}
Commit	Line	Data
b8d181e4 PZ	1	/*
	2	* i.MX IPUv3 DP Overlay Planes
	3	*
	4	* Copyright (C) 2013 Philipp Zabel, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <drm/drmP.h>
	17	#include <drm/drm_fb_cma_helper.h>
	18	#include <drm/drm_gem_cma_helper.h>
	19
39b9004d	20	#include "video/imx-ipu-v3.h"
b8d181e4 PZ	21	#include "ipuv3-plane.h"
	22
	23	#define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
	24
	25	static const uint32_t ipu_plane_formats[] = {
c639a1cf	26	DRM_FORMAT_ARGB1555,
b8d181e4	27	DRM_FORMAT_XRGB1555,
c639a1cf	28	DRM_FORMAT_ABGR1555,
b8d181e4	29	DRM_FORMAT_XBGR1555,
c639a1cf PZ	30	DRM_FORMAT_RGBA5551,
c639a1cf PZ	31	DRM_FORMAT_BGRA5551,
b8d181e4 PZ	32	DRM_FORMAT_ARGB8888,
	33	DRM_FORMAT_XRGB8888,
	34	DRM_FORMAT_ABGR8888,
	35	DRM_FORMAT_XBGR8888,
59d6b718 PZ	36	DRM_FORMAT_RGBA8888,
	37	DRM_FORMAT_RGBX8888,
	38	DRM_FORMAT_BGRA8888,
	39	DRM_FORMAT_BGRA8888,
b8d181e4 PZ	40	DRM_FORMAT_YUYV,
	41	DRM_FORMAT_YVYU,
	42	DRM_FORMAT_YUV420,
	43	DRM_FORMAT_YVU420,
	44	};
	45
	46	int ipu_plane_irq(struct ipu_plane *ipu_plane)
	47	{
	48	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
	49	IPU_IRQ_EOF);
	50	}
	51
	52	static int calc_vref(struct drm_display_mode *mode)
	53	{
	54	unsigned long htotal, vtotal;
	55
	56	htotal = mode->htotal;
	57	vtotal = mode->vtotal;
	58
	59	if (!htotal \|\| !vtotal)
	60	return 60;
	61
	62	return DIV_ROUND_UP(mode->clock * 1000, vtotal * htotal);
	63	}
	64
	65	static inline int calc_bandwidth(int width, int height, unsigned int vref)
	66	{
	67	return width * height * vref;
	68	}
	69
	70	int ipu_plane_set_base(struct ipu_plane ipu_plane, struct drm_framebuffer fb,
	71	int x, int y)
	72	{
b8d181e4	73	struct drm_gem_cma_object *cma_obj;
ee2e072e	74	unsigned long eba;
356f9524	75	int active;
b8d181e4 PZ	76
	77	cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
	78	if (!cma_obj) {
38821e64	79	DRM_DEBUG_KMS("entry is null.\n");
b8d181e4 PZ	80	return -EFAULT;
	81	}
	82
18589738 FE	83	dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
18589738 FE	84	&cma_obj->paddr, x, y);
b8d181e4	85
bc2b067a LS	86	eba = cma_obj->paddr + fb->offsets[0] +
bc2b067a LS	87	fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
356f9524 PZ	88
	89	if (ipu_plane->enabled) {
	90	active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
	91	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
	92	ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
	93	} else {
	94	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
	95	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
	96	}
b8d181e4	97
32f71106 LS	98	/* cache offsets for subsequent pageflips */
	99	ipu_plane->x = x;
	100	ipu_plane->y = y;
	101
b8d181e4 PZ	102	return 0;
	103	}
	104
	105	int ipu_plane_mode_set(struct ipu_plane ipu_plane, struct drm_crtc crtc,
	106	struct drm_display_mode *mode,
	107	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	108	unsigned int crtc_w, unsigned int crtc_h,
	109	uint32_t src_x, uint32_t src_y,
dd7fa6d8	110	uint32_t src_w, uint32_t src_h, bool interlaced)
b8d181e4	111	{
b8d181e4 PZ	112	struct device *dev = ipu_plane->base.dev->dev;
	113	int ret;
	114
	115	/* no scaling */
	116	if (src_w != crtc_w \|\| src_h != crtc_h)
	117	return -EINVAL;
	118
	119	/* clip to crtc bounds */
	120	if (crtc_x < 0) {
	121	if (-crtc_x > crtc_w)
	122	return -EINVAL;
	123	src_x += -crtc_x;
	124	src_w -= -crtc_x;
	125	crtc_w -= -crtc_x;
	126	crtc_x = 0;
	127	}
	128	if (crtc_y < 0) {
	129	if (-crtc_y > crtc_h)
	130	return -EINVAL;
	131	src_y += -crtc_y;
	132	src_h -= -crtc_y;
	133	crtc_h -= -crtc_y;
	134	crtc_y = 0;
	135	}
	136	if (crtc_x + crtc_w > mode->hdisplay) {
	137	if (crtc_x > mode->hdisplay)
	138	return -EINVAL;
	139	crtc_w = mode->hdisplay - crtc_x;
	140	src_w = crtc_w;
	141	}
	142	if (crtc_y + crtc_h > mode->vdisplay) {
	143	if (crtc_y > mode->vdisplay)
	144	return -EINVAL;
	145	crtc_h = mode->vdisplay - crtc_y;
	146	src_h = crtc_h;
	147	}
	148	/* full plane minimum width is 13 pixels */
	149	if (crtc_w < 13 && (ipu_plane->dp_flow != IPU_DP_FLOW_SYNC_FG))
	150	return -EINVAL;
	151	if (crtc_h < 2)
	152	return -EINVAL;
	153
9a666030 PZ	154	/*
	155	* since we cannot touch active IDMAC channels, we do not support
	156	* resizing the enabled plane or changing its format
	157	*/
	158	if (ipu_plane->enabled) {
	159	if (src_w != ipu_plane->w \|\| src_h != ipu_plane->h \|\|
	160	fb->pixel_format != ipu_plane->base.fb->pixel_format)
	161	return -EINVAL;
	162
	163	return ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	164	}
	165
b8d181e4 PZ	166	switch (ipu_plane->dp_flow) {
	167	case IPU_DP_FLOW_SYNC_BG:
	168	ret = ipu_dp_setup_channel(ipu_plane->dp,
	169	IPUV3_COLORSPACE_RGB,
	170	IPUV3_COLORSPACE_RGB);
	171	if (ret) {
	172	dev_err(dev,
	173	"initializing display processor failed with %d\n",
	174	ret);
	175	return ret;
	176	}
e6245fc7	177	ipu_dp_set_global_alpha(ipu_plane->dp, true, 0, true);
b8d181e4 PZ	178	break;
	179	case IPU_DP_FLOW_SYNC_FG:
	180	ipu_dp_setup_channel(ipu_plane->dp,
	181	ipu_drm_fourcc_to_colorspace(fb->pixel_format),
	182	IPUV3_COLORSPACE_UNKNOWN);
	183	ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y);
e6245fc7 PZ	184	/* Enable local alpha on partial plane */
e6245fc7 PZ	185	switch (fb->pixel_format) {
c639a1cf PZ	186	case DRM_FORMAT_ARGB1555:
	187	case DRM_FORMAT_ABGR1555:
	188	case DRM_FORMAT_RGBA5551:
	189	case DRM_FORMAT_BGRA5551:
e6245fc7 PZ	190	case DRM_FORMAT_ARGB8888:
e6245fc7 PZ	191	case DRM_FORMAT_ABGR8888:
59d6b718 PZ	192	case DRM_FORMAT_RGBA8888:
59d6b718 PZ	193	case DRM_FORMAT_BGRA8888:
e6245fc7 PZ	194	ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false);
	195	break;
	196	default:
	197	break;
	198	}
b8d181e4 PZ	199	}
	200
	201	ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
	202	if (ret) {
	203	dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
	204	return ret;
	205	}
	206
	207	ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
	208	calc_bandwidth(crtc_w, crtc_h,
	209	calc_vref(mode)), 64);
	210	if (ret) {
	211	dev_err(dev, "allocating dmfc bandwidth failed with %d\n", ret);
	212	return ret;
	213	}
	214
2eb671c4 SL	215	ipu_cpmem_zero(ipu_plane->ipu_ch);
	216	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
	217	ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
b8d181e4 PZ	218	if (ret < 0) {
	219	dev_err(dev, "unsupported pixel format 0x%08x\n",
	220	fb->pixel_format);
	221	return ret;
	222	}
	223	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
356f9524	224	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
7cd9bebe	225	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4 PZ	226
	227	ret = ipu_plane_set_base(ipu_plane, fb, src_x, src_y);
	228	if (ret < 0)
	229	return ret;
dd7fa6d8 PZ	230	if (interlaced)
dd7fa6d8 PZ	231	ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);
b8d181e4	232
9a666030 PZ	233	ipu_plane->w = src_w;
	234	ipu_plane->h = src_h;
	235
b8d181e4 PZ	236	return 0;
	237	}
	238
	239	void ipu_plane_put_resources(struct ipu_plane *ipu_plane)
	240	{
	241	if (!IS_ERR_OR_NULL(ipu_plane->dp))
	242	ipu_dp_put(ipu_plane->dp);
	243	if (!IS_ERR_OR_NULL(ipu_plane->dmfc))
	244	ipu_dmfc_put(ipu_plane->dmfc);
	245	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
	246	ipu_idmac_put(ipu_plane->ipu_ch);
	247	}
	248
	249	int ipu_plane_get_resources(struct ipu_plane *ipu_plane)
	250	{
	251	int ret;
	252
	253	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
	254	if (IS_ERR(ipu_plane->ipu_ch)) {
	255	ret = PTR_ERR(ipu_plane->ipu_ch);
	256	DRM_ERROR("failed to get idmac channel: %d\n", ret);
	257	return ret;
	258	}
	259
	260	ipu_plane->dmfc = ipu_dmfc_get(ipu_plane->ipu, ipu_plane->dma);
	261	if (IS_ERR(ipu_plane->dmfc)) {
	262	ret = PTR_ERR(ipu_plane->dmfc);
	263	DRM_ERROR("failed to get dmfc: ret %d\n", ret);
	264	goto err_out;
	265	}
	266
	267	if (ipu_plane->dp_flow >= 0) {
	268	ipu_plane->dp = ipu_dp_get(ipu_plane->ipu, ipu_plane->dp_flow);
	269	if (IS_ERR(ipu_plane->dp)) {
	270	ret = PTR_ERR(ipu_plane->dp);
	271	DRM_ERROR("failed to get dp flow: %d\n", ret);
	272	goto err_out;
	273	}
	274	}
	275
	276	return 0;
	277	err_out:
	278	ipu_plane_put_resources(ipu_plane);
	279
	280	return ret;
	281	}
	282
	283	void ipu_plane_enable(struct ipu_plane *ipu_plane)
	284	{
285bbb01 PZ	285	if (ipu_plane->dp)
285bbb01 PZ	286	ipu_dp_enable(ipu_plane->ipu);
b8d181e4 PZ	287	ipu_dmfc_enable_channel(ipu_plane->dmfc);
	288	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
	289	if (ipu_plane->dp)
	290	ipu_dp_enable_channel(ipu_plane->dp);
	291
	292	ipu_plane->enabled = true;
	293	}
	294
	295	void ipu_plane_disable(struct ipu_plane *ipu_plane)
	296	{
	297	ipu_plane->enabled = false;
	298
	299	ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
	300
	301	if (ipu_plane->dp)
	302	ipu_dp_disable_channel(ipu_plane->dp);
	303	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
	304	ipu_dmfc_disable_channel(ipu_plane->dmfc);
285bbb01 PZ	305	if (ipu_plane->dp)
285bbb01 PZ	306	ipu_dp_disable(ipu_plane->ipu);
b8d181e4 PZ	307	}
b8d181e4 PZ	308
b8d181e4 PZ	309	/*
	310	* drm_plane API
	311	*/
	312
	313	static int ipu_update_plane(struct drm_plane plane, struct drm_crtc crtc,
	314	struct drm_framebuffer *fb, int crtc_x, int crtc_y,
	315	unsigned int crtc_w, unsigned int crtc_h,
	316	uint32_t src_x, uint32_t src_y,
	317	uint32_t src_w, uint32_t src_h)
	318	{
	319	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	320	int ret = 0;
	321
	322	DRM_DEBUG_KMS("plane - %p\n", plane);
	323
	324	if (!ipu_plane->enabled)
	325	ret = ipu_plane_get_resources(ipu_plane);
	326	if (ret < 0)
	327	return ret;
	328
	329	ret = ipu_plane_mode_set(ipu_plane, crtc, &crtc->hwmode, fb,
	330	crtc_x, crtc_y, crtc_w, crtc_h,
dd7fa6d8 PZ	331	src_x >> 16, src_y >> 16, src_w >> 16, src_h >> 16,
dd7fa6d8 PZ	332	false);
b8d181e4 PZ	333	if (ret < 0) {
	334	ipu_plane_put_resources(ipu_plane);
	335	return ret;
	336	}
	337
	338	if (crtc != plane->crtc)
	339	dev_info(plane->dev->dev, "crtc change: %p -> %p\n",
	340	plane->crtc, crtc);
	341	plane->crtc = crtc;
	342
b46355f0 SG	343	if (!ipu_plane->enabled)
b46355f0 SG	344	ipu_plane_enable(ipu_plane);
b8d181e4 PZ	345
	346	return 0;
	347	}
	348
	349	static int ipu_disable_plane(struct drm_plane *plane)
	350	{
	351	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	352
	353	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	354
b46355f0 SG	355	if (ipu_plane->enabled)
b46355f0 SG	356	ipu_plane_disable(ipu_plane);
b8d181e4 PZ	357
	358	ipu_plane_put_resources(ipu_plane);
	359
	360	return 0;
	361	}
	362
	363	static void ipu_plane_destroy(struct drm_plane *plane)
	364	{
	365	struct ipu_plane *ipu_plane = to_ipu_plane(plane);
	366
	367	DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
	368
	369	ipu_disable_plane(plane);
	370	drm_plane_cleanup(plane);
	371	kfree(ipu_plane);
	372	}
	373
	374	static struct drm_plane_funcs ipu_plane_funcs = {
	375	.update_plane = ipu_update_plane,
	376	.disable_plane = ipu_disable_plane,
	377	.destroy = ipu_plane_destroy,
	378	};
	379
	380	struct ipu_plane ipu_plane_init(struct drm_device dev, struct ipu_soc *ipu,
	381	int dma, int dp, unsigned int possible_crtcs,
	382	bool priv)
	383	{
	384	struct ipu_plane *ipu_plane;
	385	int ret;
	386
	387	DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
	388	dma, dp, possible_crtcs);
	389
	390	ipu_plane = kzalloc(sizeof(*ipu_plane), GFP_KERNEL);
	391	if (!ipu_plane) {
	392	DRM_ERROR("failed to allocate plane\n");
	393	return ERR_PTR(-ENOMEM);
	394	}
	395
	396	ipu_plane->ipu = ipu;
	397	ipu_plane->dma = dma;
	398	ipu_plane->dp_flow = dp;
	399
	400	ret = drm_plane_init(dev, &ipu_plane->base, possible_crtcs,
	401	&ipu_plane_funcs, ipu_plane_formats,
	402	ARRAY_SIZE(ipu_plane_formats),
	403	priv);
	404	if (ret) {
	405	DRM_ERROR("failed to initialize plane\n");
	406	kfree(ipu_plane);
	407	return ERR_PTR(ret);
	408	}
	409
	410	return ipu_plane;
	411	}