[deliverable/linux.git] / drivers / gpu / drm / msm / msm_drv.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MSM_DRV_H__
#define __MSM_DRV_H__

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/module.h>
#include <linux/component.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/iommu.h>
#include <linux/types.h>
#include <linux/of_graph.h>
#include <linux/of_device.h>
#include <asm/sizes.h>

#include <drm/drmP.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/msm_drm.h>
#include <drm/drm_gem.h>

struct msm_kms;
struct msm_gpu;
struct msm_mmu;
struct msm_mdss;
struct msm_rd_state;
struct msm_perf_state;
struct msm_gem_submit;
struct msm_fence_context;
struct msm_fence_cb;

#define NUM_DOMAINS 2    /* one for KMS, then one per gpu core (?) */

struct msm_file_private {
	/* currently we don't do anything useful with this.. but when
	 * per-context address spaces are supported we'd keep track of
	 * the context's page-tables here.
	 */
	int dummy;
};

enum msm_mdp_plane_property {
	PLANE_PROP_ZPOS,
	PLANE_PROP_ALPHA,
	PLANE_PROP_PREMULTIPLIED,
	PLANE_PROP_MAX_NUM
};

struct msm_vblank_ctrl {
	struct work_struct work;
	struct list_head event_list;
	spinlock_t lock;
};

struct msm_drm_private {

	struct drm_device *dev;

	struct msm_kms *kms;

	/* subordinate devices, if present: */
	struct platform_device *gpu_pdev;

	/* top level MDSS wrapper device (for MDP5 only) */
	struct msm_mdss *mdss;

	/* possibly this should be in the kms component, but it is
	 * shared by both mdp4 and mdp5..
	 */
	struct hdmi *hdmi;

	/* eDP is for mdp5 only, but kms has not been created
	 * when edp_bind() and edp_init() are called. Here is the only
	 * place to keep the edp instance.
	 */
	struct msm_edp *edp;

	/* DSI is shared by mdp4 and mdp5 */
	struct msm_dsi *dsi[2];

	/* when we have more than one 'msm_gpu' these need to be an array: */
	struct msm_gpu *gpu;
	struct msm_file_private *lastctx;

	struct drm_fb_helper *fbdev;

	struct msm_rd_state *rd;
	struct msm_perf_state *perf;

	/* list of GEM objects: */
	struct list_head inactive_list;

	struct workqueue_struct *wq;
	struct workqueue_struct *atomic_wq;

	/* crtcs pending async atomic updates: */
	uint32_t pending_crtcs;
	wait_queue_head_t pending_crtcs_event;

	/* registered MMUs: */
	unsigned int num_mmus;
	struct msm_mmu *mmus[NUM_DOMAINS];

	unsigned int num_planes;
	struct drm_plane *planes[8];

	unsigned int num_crtcs;
	struct drm_crtc *crtcs[8];

	unsigned int num_encoders;
	struct drm_encoder *encoders[8];

	unsigned int num_bridges;
	struct drm_bridge *bridges[8];

	unsigned int num_connectors;
	struct drm_connector *connectors[8];

	/* Properties */
	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];

	/* VRAM carveout, used when no IOMMU: */
	struct {
		unsigned long size;
		dma_addr_t paddr;
		/* NOTE: mm managed at the page level, size is in # of pages
		 * and position mm_node->start is in # of pages:
		 */
		struct drm_mm mm;
	} vram;

	struct notifier_block vmap_notifier;
	struct shrinker shrinker;

	struct msm_vblank_ctrl vblank_ctrl;

	/* task holding struct_mutex.. currently only used in submit path
	 * to detect and reject faults from copy_from_user() for submit
	 * ioctl.
	 */
	struct task_struct *struct_mutex_task;
};

struct msm_format {
	uint32_t pixel_format;
};

int msm_atomic_check(struct drm_device *dev,
		     struct drm_atomic_state *state);
int msm_atomic_commit(struct drm_device *dev,
		struct drm_atomic_state *state, bool nonblock);

int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu);

void msm_gem_submit_free(struct msm_gem_submit *submit);
int msm_ioctl_gem_submit(struct drm_device *dev, void *data,
		struct drm_file *file);

void msm_gem_shrinker_init(struct drm_device *dev);
void msm_gem_shrinker_cleanup(struct drm_device *dev);

int msm_gem_mmap_obj(struct drm_gem_object *obj,
			struct vm_area_struct *vma);
int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma);
int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
		uint32_t *iova);
int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova);
uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
struct page **msm_gem_get_pages(struct drm_gem_object *obj);
void msm_gem_put_pages(struct drm_gem_object *obj);
void msm_gem_put_iova(struct drm_gem_object *obj, int id);
int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
		struct drm_mode_create_dumb *args);
int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
		uint32_t handle, uint64_t *offset);
struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj);
void *msm_gem_prime_vmap(struct drm_gem_object *obj);
void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev,
		struct dma_buf_attachment *attach, struct sg_table *sg);
int msm_gem_prime_pin(struct drm_gem_object *obj);
void msm_gem_prime_unpin(struct drm_gem_object *obj);
void *msm_gem_get_vaddr_locked(struct drm_gem_object *obj);
void *msm_gem_get_vaddr(struct drm_gem_object *obj);
void msm_gem_put_vaddr_locked(struct drm_gem_object *obj);
void msm_gem_put_vaddr(struct drm_gem_object *obj);
int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
void msm_gem_purge(struct drm_gem_object *obj);
void msm_gem_vunmap(struct drm_gem_object *obj);
int msm_gem_sync_object(struct drm_gem_object *obj,
		struct msm_fence_context *fctx, bool exclusive);
void msm_gem_move_to_active(struct drm_gem_object *obj,
		struct msm_gpu *gpu, bool exclusive, struct fence *fence);
void msm_gem_move_to_inactive(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
		uint32_t size, uint32_t flags, uint32_t *handle);
struct drm_gem_object *msm_gem_new(struct drm_device *dev,
		uint32_t size, uint32_t flags);
struct drm_gem_object *msm_gem_import(struct drm_device *dev,
		struct dma_buf *dmabuf, struct sg_table *sgt);

int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane);
const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb);
struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev,
		const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos);
struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev,
		struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd);

struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev);
void msm_fbdev_free(struct drm_device *dev);

struct hdmi;
int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev,
		struct drm_encoder *encoder);
void __init msm_hdmi_register(void);
void __exit msm_hdmi_unregister(void);

struct msm_edp;
void __init msm_edp_register(void);
void __exit msm_edp_unregister(void);
int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev,
		struct drm_encoder *encoder);

struct msm_dsi;
enum msm_dsi_encoder_id {
	MSM_DSI_VIDEO_ENCODER_ID = 0,
	MSM_DSI_CMD_ENCODER_ID = 1,
	MSM_DSI_ENCODER_NUM = 2
};
#ifdef CONFIG_DRM_MSM_DSI
void __init msm_dsi_register(void);
void __exit msm_dsi_unregister(void);
int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev,
		struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
#else
static inline void __init msm_dsi_register(void)
{
}
static inline void __exit msm_dsi_unregister(void)
{
}
static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
		struct drm_device *dev,
		struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
{
	return -EINVAL;
}
#endif

void __init msm_mdp_register(void);
void __exit msm_mdp_unregister(void);

#ifdef CONFIG_DEBUG_FS
void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m);
void msm_gem_describe_objects(struct list_head *list, struct seq_file *m);
void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m);
int msm_debugfs_late_init(struct drm_device *dev);
int msm_rd_debugfs_init(struct drm_minor *minor);
void msm_rd_debugfs_cleanup(struct drm_minor *minor);
void msm_rd_dump_submit(struct msm_gem_submit *submit);
int msm_perf_debugfs_init(struct drm_minor *minor);
void msm_perf_debugfs_cleanup(struct drm_minor *minor);
#else
static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
#endif

void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
		const char *dbgname);
void msm_writel(u32 data, void __iomem *addr);
u32 msm_readl(const void __iomem *addr);

#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)

static inline int align_pitch(int width, int bpp)
{
	int bytespp = (bpp + 7) / 8;
	/* adreno needs pitch aligned to 32 pixels: */
	return bytespp * ALIGN(width, 32);
}

/* for the generated headers: */
#define INVALID_IDX(idx) ({BUG(); 0;})
#define fui(x)                ({BUG(); 0;})
#define util_float_to_half(x) ({BUG(); 0;})


#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)

/* for conditionally setting boolean flag(s): */
#define COND(bool, val) ((bool) ? (val) : 0)

static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
{
	ktime_t now = ktime_get();
	unsigned long remaining_jiffies;

	if (ktime_compare(*timeout, now) < 0) {
		remaining_jiffies = 0;
	} else {
		ktime_t rem = ktime_sub(*timeout, now);
		struct timespec ts = ktime_to_timespec(rem);
		remaining_jiffies = timespec_to_jiffies(&ts);
	}

	return remaining_jiffies;
}

#endif /* __MSM_DRV_H__ */
Commit	Line	Data
c8afe684 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __MSM_DRV_H__
	19	#define __MSM_DRV_H__
	20
	21	#include <linux/kernel.h>
	22	#include <linux/clk.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/module.h>
060530f1	25	#include <linux/component.h>
c8afe684 RC	26	#include <linux/platform_device.h>
	27	#include <linux/pm.h>
	28	#include <linux/pm_runtime.h>
	29	#include <linux/slab.h>
	30	#include <linux/list.h>
	31	#include <linux/iommu.h>
	32	#include <linux/types.h>
3d6df062	33	#include <linux/of_graph.h>
e9fbdaf2	34	#include <linux/of_device.h>
c8afe684 RC	35	#include <asm/sizes.h>
c8afe684 RC	36
c8afe684	37	#include <drm/drmP.h>
cf3a7e4c RC	38	#include <drm/drm_atomic.h>
cf3a7e4c RC	39	#include <drm/drm_atomic_helper.h>
c8afe684	40	#include <drm/drm_crtc_helper.h>
cf3a7e4c	41	#include <drm/drm_plane_helper.h>
c8afe684	42	#include <drm/drm_fb_helper.h>
7198e6b0	43	#include <drm/msm_drm.h>
d9fc9413	44	#include <drm/drm_gem.h>
c8afe684 RC	45
c8afe684 RC	46	struct msm_kms;
7198e6b0	47	struct msm_gpu;
871d812a	48	struct msm_mmu;
990a4007	49	struct msm_mdss;
a7d3c950	50	struct msm_rd_state;
70c70f09	51	struct msm_perf_state;
a7d3c950	52	struct msm_gem_submit;
ca762a8a	53	struct msm_fence_context;
fde5de6c	54	struct msm_fence_cb;
c8afe684	55
7198e6b0 RC	56	#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */
	57
	58	struct msm_file_private {
	59	/* currently we don't do anything useful with this.. but when
	60	* per-context address spaces are supported we'd keep track of
	61	* the context's page-tables here.
	62	*/
	63	int dummy;
	64	};
c8afe684	65
12987781	66	enum msm_mdp_plane_property {
	67	PLANE_PROP_ZPOS,
	68	PLANE_PROP_ALPHA,
	69	PLANE_PROP_PREMULTIPLIED,
	70	PLANE_PROP_MAX_NUM
	71	};
	72
78b1d470 HL	73	struct msm_vblank_ctrl {
	74	struct work_struct work;
	75	struct list_head event_list;
	76	spinlock_t lock;
	77	};
	78
c8afe684 RC	79	struct msm_drm_private {
c8afe684 RC	80
68209390 RC	81	struct drm_device *dev;
68209390 RC	82
c8afe684 RC	83	struct msm_kms *kms;
c8afe684 RC	84
060530f1	85	/* subordinate devices, if present: */
067fef37 RC	86	struct platform_device *gpu_pdev;
067fef37 RC	87
990a4007 AT	88	/* top level MDSS wrapper device (for MDP5 only) */
	89	struct msm_mdss *mdss;
	90
067fef37 RC	91	/* possibly this should be in the kms component, but it is
	92	* shared by both mdp4 and mdp5..
	93	*/
	94	struct hdmi *hdmi;
060530f1	95
ab5b0107 HL	96	/* eDP is for mdp5 only, but kms has not been created
	97	* when edp_bind() and edp_init() are called. Here is the only
	98	* place to keep the edp instance.
	99	*/
	100	struct msm_edp *edp;
	101
a689554b HL	102	/* DSI is shared by mdp4 and mdp5 */
	103	struct msm_dsi *dsi[2];
	104
7198e6b0 RC	105	/* when we have more than one 'msm_gpu' these need to be an array: */
	106	struct msm_gpu *gpu;
	107	struct msm_file_private *lastctx;
	108
c8afe684 RC	109	struct drm_fb_helper *fbdev;
c8afe684 RC	110
a7d3c950	111	struct msm_rd_state *rd;
70c70f09	112	struct msm_perf_state *perf;
a7d3c950	113
c8afe684 RC	114	/* list of GEM objects: */
	115	struct list_head inactive_list;
	116
	117	struct workqueue_struct *wq;
ba00c3f2	118	struct workqueue_struct *atomic_wq;
c8afe684	119
f86afecf RC	120	/* crtcs pending async atomic updates: */
	121	uint32_t pending_crtcs;
	122	wait_queue_head_t pending_crtcs_event;
	123
871d812a RC	124	/* registered MMUs: */
	125	unsigned int num_mmus;
	126	struct msm_mmu *mmus[NUM_DOMAINS];
c8afe684	127
a8623918 RC	128	unsigned int num_planes;
	129	struct drm_plane *planes[8];
	130
c8afe684 RC	131	unsigned int num_crtcs;
	132	struct drm_crtc *crtcs[8];
	133
	134	unsigned int num_encoders;
	135	struct drm_encoder *encoders[8];
	136
a3376e3e RC	137	unsigned int num_bridges;
	138	struct drm_bridge *bridges[8];
	139
c8afe684 RC	140	unsigned int num_connectors;
c8afe684 RC	141	struct drm_connector *connectors[8];
871d812a	142
12987781	143	/* Properties */
	144	struct drm_property *plane_property[PLANE_PROP_MAX_NUM];
	145
871d812a RC	146	/* VRAM carveout, used when no IOMMU: */
	147	struct {
	148	unsigned long size;
	149	dma_addr_t paddr;
	150	/* NOTE: mm managed at the page level, size is in # of pages
	151	* and position mm_node->start is in # of pages:
	152	*/
	153	struct drm_mm mm;
	154	} vram;
78b1d470	155
e1e9db2c	156	struct notifier_block vmap_notifier;
68209390 RC	157	struct shrinker shrinker;
68209390 RC	158
78b1d470	159	struct msm_vblank_ctrl vblank_ctrl;
d78d383a RC	160
	161	/* task holding struct_mutex.. currently only used in submit path
	162	* to detect and reject faults from copy_from_user() for submit
	163	* ioctl.
	164	*/
	165	struct task_struct *struct_mutex_task;
c8afe684 RC	166	};
	167
	168	struct msm_format {
	169	uint32_t pixel_format;
	170	};
	171
b4274fbe DV	172	int msm_atomic_check(struct drm_device *dev,
b4274fbe DV	173	struct drm_atomic_state *state);
cf3a7e4c	174	int msm_atomic_commit(struct drm_device *dev,
a3ccfb9f	175	struct drm_atomic_state *state, bool nonblock);
cf3a7e4c	176
871d812a	177	int msm_register_mmu(struct drm_device dev, struct msm_mmu mmu);
c8afe684	178
40e6815b	179	void msm_gem_submit_free(struct msm_gem_submit *submit);
7198e6b0 RC	180	int msm_ioctl_gem_submit(struct drm_device dev, void data,
	181	struct drm_file *file);
	182
68209390 RC	183	void msm_gem_shrinker_init(struct drm_device *dev);
	184	void msm_gem_shrinker_cleanup(struct drm_device *dev);
	185
77a147e7 DT	186	int msm_gem_mmap_obj(struct drm_gem_object *obj,
77a147e7 DT	187	struct vm_area_struct *vma);
c8afe684 RC	188	int msm_gem_mmap(struct file filp, struct vm_area_struct vma);
	189	int msm_gem_fault(struct vm_area_struct vma, struct vm_fault vmf);
	190	uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj);
	191	int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id,
	192	uint32_t *iova);
	193	int msm_gem_get_iova(struct drm_gem_object obj, int id, uint32_t iova);
2638d90a	194	uint32_t msm_gem_iova(struct drm_gem_object *obj, int id);
05b84911 RC	195	struct page *msm_gem_get_pages(struct drm_gem_object obj);
05b84911 RC	196	void msm_gem_put_pages(struct drm_gem_object *obj);
c8afe684 RC	197	void msm_gem_put_iova(struct drm_gem_object *obj, int id);
	198	int msm_gem_dumb_create(struct drm_file file, struct drm_device dev,
	199	struct drm_mode_create_dumb *args);
c8afe684 RC	200	int msm_gem_dumb_map_offset(struct drm_file file, struct drm_device dev,
c8afe684 RC	201	uint32_t handle, uint64_t *offset);
05b84911 RC	202	struct sg_table msm_gem_prime_get_sg_table(struct drm_gem_object obj);
	203	void msm_gem_prime_vmap(struct drm_gem_object obj);
	204	void msm_gem_prime_vunmap(struct drm_gem_object obj, void vaddr);
77a147e7	205	int msm_gem_prime_mmap(struct drm_gem_object obj, struct vm_area_struct vma);
05b84911	206	struct drm_gem_object msm_gem_prime_import_sg_table(struct drm_device dev,
b5e9c1a2	207	struct dma_buf_attachment attach, struct sg_table sg);
05b84911 RC	208	int msm_gem_prime_pin(struct drm_gem_object *obj);
05b84911 RC	209	void msm_gem_prime_unpin(struct drm_gem_object *obj);
18f23049 RC	210	void msm_gem_get_vaddr_locked(struct drm_gem_object obj);
	211	void msm_gem_get_vaddr(struct drm_gem_object obj);
	212	void msm_gem_put_vaddr_locked(struct drm_gem_object *obj);
	213	void msm_gem_put_vaddr(struct drm_gem_object *obj);
4cd33c48	214	int msm_gem_madvise(struct drm_gem_object *obj, unsigned madv);
68209390	215	void msm_gem_purge(struct drm_gem_object *obj);
e1e9db2c	216	void msm_gem_vunmap(struct drm_gem_object *obj);
b6295f9a RC	217	int msm_gem_sync_object(struct drm_gem_object *obj,
b6295f9a RC	218	struct msm_fence_context *fctx, bool exclusive);
7198e6b0	219	void msm_gem_move_to_active(struct drm_gem_object *obj,
b6295f9a	220	struct msm_gpu gpu, bool exclusive, struct fence fence);
7198e6b0	221	void msm_gem_move_to_inactive(struct drm_gem_object *obj);
ba00c3f2	222	int msm_gem_cpu_prep(struct drm_gem_object obj, uint32_t op, ktime_t timeout);
7198e6b0	223	int msm_gem_cpu_fini(struct drm_gem_object *obj);
c8afe684 RC	224	void msm_gem_free_object(struct drm_gem_object *obj);
	225	int msm_gem_new_handle(struct drm_device dev, struct drm_file file,
	226	uint32_t size, uint32_t flags, uint32_t *handle);
	227	struct drm_gem_object msm_gem_new(struct drm_device dev,
	228	uint32_t size, uint32_t flags);
05b84911	229	struct drm_gem_object msm_gem_import(struct drm_device dev,
79f0e202	230	struct dma_buf dmabuf, struct sg_table sgt);
c8afe684	231
2638d90a RC	232	int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id);
	233	void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id);
	234	uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane);
c8afe684 RC	235	struct drm_gem_object msm_framebuffer_bo(struct drm_framebuffer fb, int plane);
	236	const struct msm_format msm_framebuffer_format(struct drm_framebuffer fb);
	237	struct drm_framebuffer msm_framebuffer_init(struct drm_device dev,
1eb83451	238	const struct drm_mode_fb_cmd2 mode_cmd, struct drm_gem_object *bos);
c8afe684	239	struct drm_framebuffer msm_framebuffer_create(struct drm_device dev,
1eb83451	240	struct drm_file file, const struct drm_mode_fb_cmd2 mode_cmd);
c8afe684 RC	241
c8afe684 RC	242	struct drm_fb_helper msm_fbdev_init(struct drm_device dev);
1aaa57f5	243	void msm_fbdev_free(struct drm_device *dev);
c8afe684	244
dada25bd	245	struct hdmi;
fcda50c8	246	int msm_hdmi_modeset_init(struct hdmi hdmi, struct drm_device dev,
067fef37	247	struct drm_encoder *encoder);
fcda50c8 AB	248	void __init msm_hdmi_register(void);
fcda50c8 AB	249	void __exit msm_hdmi_unregister(void);
c8afe684	250
00453981 HL	251	struct msm_edp;
	252	void __init msm_edp_register(void);
	253	void __exit msm_edp_unregister(void);
	254	int msm_edp_modeset_init(struct msm_edp edp, struct drm_device dev,
	255	struct drm_encoder *encoder);
	256
a689554b HL	257	struct msm_dsi;
	258	enum msm_dsi_encoder_id {
	259	MSM_DSI_VIDEO_ENCODER_ID = 0,
	260	MSM_DSI_CMD_ENCODER_ID = 1,
	261	MSM_DSI_ENCODER_NUM = 2
	262	};
	263	#ifdef CONFIG_DRM_MSM_DSI
	264	void __init msm_dsi_register(void);
	265	void __exit msm_dsi_unregister(void);
	266	int msm_dsi_modeset_init(struct msm_dsi msm_dsi, struct drm_device dev,
	267	struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]);
	268	#else
	269	static inline void __init msm_dsi_register(void)
	270	{
	271	}
	272	static inline void __exit msm_dsi_unregister(void)
	273	{
	274	}
	275	static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi,
	276	struct drm_device *dev,
	277	struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM])
	278	{
	279	return -EINVAL;
	280	}
	281	#endif
	282
1dd0a0b1 AT	283	void __init msm_mdp_register(void);
	284	void __exit msm_mdp_unregister(void);
	285
c8afe684 RC	286	#ifdef CONFIG_DEBUG_FS
	287	void msm_gem_describe(struct drm_gem_object obj, struct seq_file m);
	288	void msm_gem_describe_objects(struct list_head list, struct seq_file m);
	289	void msm_framebuffer_describe(struct drm_framebuffer fb, struct seq_file m);
a7d3c950 RC	290	int msm_debugfs_late_init(struct drm_device *dev);
	291	int msm_rd_debugfs_init(struct drm_minor *minor);
	292	void msm_rd_debugfs_cleanup(struct drm_minor *minor);
	293	void msm_rd_dump_submit(struct msm_gem_submit *submit);
70c70f09 RC	294	int msm_perf_debugfs_init(struct drm_minor *minor);
70c70f09 RC	295	void msm_perf_debugfs_cleanup(struct drm_minor *minor);
a7d3c950 RC	296	#else
	297	static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; }
	298	static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {}
c8afe684 RC	299	#endif
	300
	301	void __iomem msm_ioremap(struct platform_device pdev, const char *name,
	302	const char *dbgname);
	303	void msm_writel(u32 data, void __iomem *addr);
	304	u32 msm_readl(const void __iomem *addr);
	305
	306	#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
	307	#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
	308
	309	static inline int align_pitch(int width, int bpp)
	310	{
	311	int bytespp = (bpp + 7) / 8;
	312	/* adreno needs pitch aligned to 32 pixels: */
	313	return bytespp * ALIGN(width, 32);
	314	}
	315
	316	/* for the generated headers: */
	317	#define INVALID_IDX(idx) ({BUG(); 0;})
7198e6b0 RC	318	#define fui(x) ({BUG(); 0;})
	319	#define util_float_to_half(x) ({BUG(); 0;})
	320
c8afe684 RC	321
	322	#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)
	323
	324	/* for conditionally setting boolean flag(s): */
	325	#define COND(bool, val) ((bool) ? (val) : 0)
	326
340ff410 RC	327	static inline unsigned long timeout_to_jiffies(const ktime_t *timeout)
	328	{
	329	ktime_t now = ktime_get();
	330	unsigned long remaining_jiffies;
	331
	332	if (ktime_compare(*timeout, now) < 0) {
	333	remaining_jiffies = 0;
	334	} else {
	335	ktime_t rem = ktime_sub(*timeout, now);
	336	struct timespec ts = ktime_to_timespec(rem);
	337	remaining_jiffies = timespec_to_jiffies(&ts);
	338	}
	339
	340	return remaining_jiffies;
	341	}
c8afe684 RC	342
c8afe684 RC	343	#endif /* __MSM_DRV_H__ */