Commit | Line | Data |
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4b223eef | 1 | /* |
ebb945a9 | 2 | * Copyright 2012 Red Hat Inc. |
4b223eef BS |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
e3c71eb2 BS |
24 | #include "gf100.h" |
25 | #include "ctxgf100.h" | |
26 | #include "fuc/os.h" | |
27 | ||
28 | #include <core/client.h> | |
e3c71eb2 | 29 | #include <core/option.h> |
e3c71eb2 BS |
30 | #include <subdev/fb.h> |
31 | #include <subdev/mc.h> | |
c85ee6ca | 32 | #include <subdev/pmu.h> |
e3c71eb2 | 33 | #include <subdev/timer.h> |
a65955e1 | 34 | #include <engine/fifo.h> |
e3c71eb2 BS |
35 | |
36 | #include <nvif/class.h> | |
53a6df77 | 37 | #include <nvif/cl9097.h> |
e3c71eb2 | 38 | #include <nvif/unpack.h> |
0411de85 | 39 | |
ac9738bb BS |
40 | /******************************************************************************* |
41 | * Zero Bandwidth Clear | |
42 | ******************************************************************************/ | |
43 | ||
44 | static void | |
bfee3f3d | 45 | gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) |
ac9738bb | 46 | { |
276836d4 | 47 | struct nvkm_device *device = gr->base.engine.subdev.device; |
bfee3f3d | 48 | if (gr->zbc_color[zbc].format) { |
276836d4 BS |
49 | nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); |
50 | nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); | |
51 | nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); | |
52 | nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); | |
53 | } | |
54 | nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); | |
55 | nvkm_wr32(device, 0x405820, zbc); | |
56 | nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ | |
ac9738bb BS |
57 | } |
58 | ||
59 | static int | |
bfee3f3d | 60 | gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, |
e3c71eb2 | 61 | const u32 ds[4], const u32 l2[4]) |
ac9738bb | 62 | { |
70bc7182 | 63 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
ac9738bb BS |
64 | int zbc = -ENOSPC, i; |
65 | ||
66 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { | |
bfee3f3d BS |
67 | if (gr->zbc_color[i].format) { |
68 | if (gr->zbc_color[i].format != format) | |
ac9738bb | 69 | continue; |
bfee3f3d BS |
70 | if (memcmp(gr->zbc_color[i].ds, ds, sizeof( |
71 | gr->zbc_color[i].ds))) | |
ac9738bb | 72 | continue; |
bfee3f3d BS |
73 | if (memcmp(gr->zbc_color[i].l2, l2, sizeof( |
74 | gr->zbc_color[i].l2))) { | |
ac9738bb BS |
75 | WARN_ON(1); |
76 | return -EINVAL; | |
77 | } | |
78 | return i; | |
79 | } else { | |
80 | zbc = (zbc < 0) ? i : zbc; | |
81 | } | |
82 | } | |
83 | ||
da7c74ea BS |
84 | if (zbc < 0) |
85 | return zbc; | |
86 | ||
bfee3f3d BS |
87 | memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); |
88 | memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); | |
89 | gr->zbc_color[zbc].format = format; | |
70bc7182 | 90 | nvkm_ltc_zbc_color_get(ltc, zbc, l2); |
bfee3f3d | 91 | gf100_gr_zbc_clear_color(gr, zbc); |
ac9738bb BS |
92 | return zbc; |
93 | } | |
94 | ||
95 | static void | |
bfee3f3d | 96 | gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) |
ac9738bb | 97 | { |
276836d4 | 98 | struct nvkm_device *device = gr->base.engine.subdev.device; |
bfee3f3d | 99 | if (gr->zbc_depth[zbc].format) |
276836d4 BS |
100 | nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); |
101 | nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); | |
102 | nvkm_wr32(device, 0x405820, zbc); | |
103 | nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ | |
ac9738bb BS |
104 | } |
105 | ||
106 | static int | |
bfee3f3d | 107 | gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, |
e3c71eb2 | 108 | const u32 ds, const u32 l2) |
ac9738bb | 109 | { |
70bc7182 | 110 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
ac9738bb BS |
111 | int zbc = -ENOSPC, i; |
112 | ||
113 | for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { | |
bfee3f3d BS |
114 | if (gr->zbc_depth[i].format) { |
115 | if (gr->zbc_depth[i].format != format) | |
ac9738bb | 116 | continue; |
bfee3f3d | 117 | if (gr->zbc_depth[i].ds != ds) |
ac9738bb | 118 | continue; |
bfee3f3d | 119 | if (gr->zbc_depth[i].l2 != l2) { |
ac9738bb BS |
120 | WARN_ON(1); |
121 | return -EINVAL; | |
122 | } | |
123 | return i; | |
124 | } else { | |
125 | zbc = (zbc < 0) ? i : zbc; | |
126 | } | |
127 | } | |
128 | ||
da7c74ea BS |
129 | if (zbc < 0) |
130 | return zbc; | |
131 | ||
bfee3f3d BS |
132 | gr->zbc_depth[zbc].format = format; |
133 | gr->zbc_depth[zbc].ds = ds; | |
134 | gr->zbc_depth[zbc].l2 = l2; | |
70bc7182 | 135 | nvkm_ltc_zbc_depth_get(ltc, zbc, l2); |
bfee3f3d | 136 | gf100_gr_zbc_clear_depth(gr, zbc); |
ac9738bb BS |
137 | return zbc; |
138 | } | |
139 | ||
ebb945a9 BS |
140 | /******************************************************************************* |
141 | * Graphics object classes | |
142 | ******************************************************************************/ | |
143 | ||
ac9738bb | 144 | static int |
e3c71eb2 | 145 | gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) |
ac9738bb | 146 | { |
0d7fc246 | 147 | struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); |
ac9738bb BS |
148 | union { |
149 | struct fermi_a_zbc_color_v0 v0; | |
150 | } *args = data; | |
f01c4e68 | 151 | int ret = -ENOSYS; |
ac9738bb | 152 | |
f01c4e68 | 153 | if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { |
ac9738bb BS |
154 | switch (args->v0.format) { |
155 | case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: | |
156 | case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: | |
157 | case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: | |
158 | case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: | |
159 | case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: | |
160 | case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: | |
161 | case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: | |
162 | case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: | |
163 | case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: | |
164 | case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: | |
165 | case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: | |
166 | case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: | |
167 | case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: | |
168 | case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: | |
169 | case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: | |
170 | case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: | |
171 | case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: | |
172 | case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: | |
173 | case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: | |
bfee3f3d | 174 | ret = gf100_gr_zbc_color_get(gr, args->v0.format, |
e3c71eb2 BS |
175 | args->v0.ds, |
176 | args->v0.l2); | |
ac9738bb BS |
177 | if (ret >= 0) { |
178 | args->v0.index = ret; | |
179 | return 0; | |
180 | } | |
181 | break; | |
182 | default: | |
183 | return -EINVAL; | |
184 | } | |
185 | } | |
186 | ||
187 | return ret; | |
188 | } | |
189 | ||
190 | static int | |
e3c71eb2 | 191 | gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) |
ac9738bb | 192 | { |
0d7fc246 | 193 | struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine)); |
ac9738bb BS |
194 | union { |
195 | struct fermi_a_zbc_depth_v0 v0; | |
196 | } *args = data; | |
f01c4e68 | 197 | int ret = -ENOSYS; |
ac9738bb | 198 | |
f01c4e68 | 199 | if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { |
ac9738bb BS |
200 | switch (args->v0.format) { |
201 | case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: | |
bfee3f3d | 202 | ret = gf100_gr_zbc_depth_get(gr, args->v0.format, |
e3c71eb2 BS |
203 | args->v0.ds, |
204 | args->v0.l2); | |
ac9738bb BS |
205 | return (ret >= 0) ? 0 : -ENOSPC; |
206 | default: | |
207 | return -EINVAL; | |
208 | } | |
209 | } | |
210 | ||
211 | return ret; | |
212 | } | |
213 | ||
214 | static int | |
e3c71eb2 | 215 | gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) |
ac9738bb | 216 | { |
f01c4e68 | 217 | nvif_ioctl(object, "fermi mthd %08x\n", mthd); |
ac9738bb BS |
218 | switch (mthd) { |
219 | case FERMI_A_ZBC_COLOR: | |
e3c71eb2 | 220 | return gf100_fermi_mthd_zbc_color(object, data, size); |
ac9738bb | 221 | case FERMI_A_ZBC_DEPTH: |
e3c71eb2 | 222 | return gf100_fermi_mthd_zbc_depth(object, data, size); |
ac9738bb BS |
223 | default: |
224 | break; | |
225 | } | |
226 | return -EINVAL; | |
227 | } | |
228 | ||
27f3d6cf BS |
229 | const struct nvkm_object_func |
230 | gf100_fermi = { | |
e3c71eb2 | 231 | .mthd = gf100_fermi_mthd, |
ac9738bb BS |
232 | }; |
233 | ||
a65955e1 BS |
234 | static void |
235 | gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) | |
d6bd3803 | 236 | { |
a65955e1 BS |
237 | nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); |
238 | nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); | |
d6bd3803 BS |
239 | } |
240 | ||
a65955e1 BS |
241 | static bool |
242 | gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) | |
243 | { | |
244 | switch (class & 0x00ff) { | |
245 | case 0x97: | |
246 | case 0xc0: | |
247 | switch (mthd) { | |
248 | case 0x1528: | |
249 | gf100_gr_mthd_set_shader_exceptions(device, data); | |
250 | return true; | |
251 | default: | |
252 | break; | |
253 | } | |
254 | break; | |
255 | default: | |
256 | break; | |
257 | } | |
258 | return false; | |
259 | } | |
d6bd3803 | 260 | |
27f3d6cf BS |
261 | static int |
262 | gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) | |
263 | { | |
264 | struct gf100_gr *gr = gf100_gr(base); | |
265 | int c = 0; | |
266 | ||
267 | while (gr->func->sclass[c].oclass) { | |
268 | if (c++ == index) { | |
269 | *sclass = gr->func->sclass[index]; | |
270 | return index; | |
271 | } | |
272 | } | |
273 | ||
274 | return c; | |
275 | } | |
ebb945a9 | 276 | |
ebb945a9 BS |
277 | /******************************************************************************* |
278 | * PGRAPH context | |
279 | ******************************************************************************/ | |
966a5b7d | 280 | |
27f3d6cf BS |
281 | static int |
282 | gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, | |
283 | int align, struct nvkm_gpuobj **pgpuobj) | |
966a5b7d | 284 | { |
27f3d6cf BS |
285 | struct gf100_gr_chan *chan = gf100_gr_chan(object); |
286 | struct gf100_gr *gr = chan->gr; | |
287 | int ret, i; | |
288 | ||
289 | ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, | |
290 | align, false, parent, pgpuobj); | |
291 | if (ret) | |
292 | return ret; | |
293 | ||
294 | nvkm_kmap(*pgpuobj); | |
295 | for (i = 0; i < gr->size; i += 4) | |
296 | nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); | |
297 | ||
298 | if (!gr->firmware) { | |
299 | nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); | |
300 | nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma.offset >> 8); | |
301 | } else { | |
302 | nvkm_wo32(*pgpuobj, 0xf4, 0); | |
303 | nvkm_wo32(*pgpuobj, 0xf8, 0); | |
304 | nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); | |
305 | nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma.offset)); | |
306 | nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma.offset)); | |
307 | nvkm_wo32(*pgpuobj, 0x1c, 1); | |
308 | nvkm_wo32(*pgpuobj, 0x20, 0); | |
309 | nvkm_wo32(*pgpuobj, 0x28, 0); | |
310 | nvkm_wo32(*pgpuobj, 0x2c, 0); | |
311 | } | |
312 | nvkm_done(*pgpuobj); | |
313 | return 0; | |
314 | } | |
315 | ||
316 | static void * | |
317 | gf100_gr_chan_dtor(struct nvkm_object *object) | |
318 | { | |
319 | struct gf100_gr_chan *chan = gf100_gr_chan(object); | |
320 | int i; | |
321 | ||
322 | for (i = 0; i < ARRAY_SIZE(chan->data); i++) { | |
323 | if (chan->data[i].vma.node) { | |
324 | nvkm_vm_unmap(&chan->data[i].vma); | |
325 | nvkm_vm_put(&chan->data[i].vma); | |
326 | } | |
327 | nvkm_memory_del(&chan->data[i].mem); | |
328 | } | |
329 | ||
330 | if (chan->mmio_vma.node) { | |
331 | nvkm_vm_unmap(&chan->mmio_vma); | |
332 | nvkm_vm_put(&chan->mmio_vma); | |
333 | } | |
334 | nvkm_memory_del(&chan->mmio); | |
335 | return chan; | |
336 | } | |
337 | ||
338 | static const struct nvkm_object_func | |
339 | gf100_gr_chan = { | |
340 | .dtor = gf100_gr_chan_dtor, | |
341 | .bind = gf100_gr_chan_bind, | |
342 | }; | |
343 | ||
344 | static int | |
345 | gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, | |
346 | const struct nvkm_oclass *oclass, | |
347 | struct nvkm_object **pobject) | |
348 | { | |
349 | struct gf100_gr *gr = gf100_gr(base); | |
bfee3f3d BS |
350 | struct gf100_gr_data *data = gr->mmio_data; |
351 | struct gf100_gr_mmio *mmio = gr->mmio_list; | |
e3c71eb2 | 352 | struct gf100_gr_chan *chan; |
227c95d9 | 353 | struct nvkm_device *device = gr->base.engine.subdev.device; |
966a5b7d | 354 | int ret, i; |
966a5b7d | 355 | |
27f3d6cf BS |
356 | if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) |
357 | return -ENOMEM; | |
358 | nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); | |
359 | chan->gr = gr; | |
360 | *pobject = &chan->object; | |
966a5b7d | 361 | |
ac1499d9 BS |
362 | /* allocate memory for a "mmio list" buffer that's used by the HUB |
363 | * fuc to modify some per-context register settings on first load | |
364 | * of the context. | |
365 | */ | |
227c95d9 BS |
366 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, |
367 | false, &chan->mmio); | |
73a60c0d BS |
368 | if (ret) |
369 | return ret; | |
370 | ||
27f3d6cf | 371 | ret = nvkm_vm_get(fifoch->vm, 0x1000, 12, NV_MEM_ACCESS_RW | |
227c95d9 | 372 | NV_MEM_ACCESS_SYS, &chan->mmio_vma); |
73a60c0d BS |
373 | if (ret) |
374 | return ret; | |
375 | ||
227c95d9 BS |
376 | nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0); |
377 | ||
ac1499d9 | 378 | /* allocate buffers referenced by mmio list */ |
bfee3f3d | 379 | for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { |
227c95d9 BS |
380 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, |
381 | data->size, data->align, false, | |
382 | &chan->data[i].mem); | |
ac1499d9 BS |
383 | if (ret) |
384 | return ret; | |
73a60c0d | 385 | |
27f3d6cf BS |
386 | ret = nvkm_vm_get(fifoch->vm, |
387 | nvkm_memory_size(chan->data[i].mem), 12, | |
388 | data->access, &chan->data[i].vma); | |
ac1499d9 BS |
389 | if (ret) |
390 | return ret; | |
966a5b7d | 391 | |
227c95d9 | 392 | nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0); |
ac1499d9 | 393 | data++; |
966a5b7d BS |
394 | } |
395 | ||
ac1499d9 | 396 | /* finally, fill in the mmio list and point the context at it */ |
142ea05f | 397 | nvkm_kmap(chan->mmio); |
bfee3f3d | 398 | for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { |
ac1499d9 BS |
399 | u32 addr = mmio->addr; |
400 | u32 data = mmio->data; | |
966a5b7d | 401 | |
694c6caf | 402 | if (mmio->buffer >= 0) { |
ebb945a9 | 403 | u64 info = chan->data[mmio->buffer].vma.offset; |
ac1499d9 BS |
404 | data |= info >> mmio->shift; |
405 | } | |
73a60c0d | 406 | |
142ea05f BS |
407 | nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); |
408 | nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); | |
ac1499d9 BS |
409 | mmio++; |
410 | } | |
142ea05f | 411 | nvkm_done(chan->mmio); |
ebb945a9 | 412 | return 0; |
4b223eef BS |
413 | } |
414 | ||
ebb945a9 | 415 | /******************************************************************************* |
c33b1e8c | 416 | * PGRAPH register lists |
ebb945a9 BS |
417 | ******************************************************************************/ |
418 | ||
e3c71eb2 BS |
419 | const struct gf100_gr_init |
420 | gf100_gr_init_main_0[] = { | |
30f4e087 BS |
421 | { 0x400080, 1, 0x04, 0x003083c2 }, |
422 | { 0x400088, 1, 0x04, 0x00006fe7 }, | |
423 | { 0x40008c, 1, 0x04, 0x00000000 }, | |
424 | { 0x400090, 1, 0x04, 0x00000030 }, | |
425 | { 0x40013c, 1, 0x04, 0x013901f7 }, | |
426 | { 0x400140, 1, 0x04, 0x00000100 }, | |
427 | { 0x400144, 1, 0x04, 0x00000000 }, | |
428 | { 0x400148, 1, 0x04, 0x00000110 }, | |
429 | { 0x400138, 1, 0x04, 0x00000000 }, | |
430 | { 0x400130, 2, 0x04, 0x00000000 }, | |
431 | { 0x400124, 1, 0x04, 0x00000002 }, | |
432 | {} | |
433 | }; | |
434 | ||
e3c71eb2 BS |
435 | const struct gf100_gr_init |
436 | gf100_gr_init_fe_0[] = { | |
30f4e087 BS |
437 | { 0x40415c, 1, 0x04, 0x00000000 }, |
438 | { 0x404170, 1, 0x04, 0x00000000 }, | |
439 | {} | |
440 | }; | |
441 | ||
e3c71eb2 BS |
442 | const struct gf100_gr_init |
443 | gf100_gr_init_pri_0[] = { | |
30f4e087 BS |
444 | { 0x404488, 2, 0x04, 0x00000000 }, |
445 | {} | |
446 | }; | |
447 | ||
e3c71eb2 BS |
448 | const struct gf100_gr_init |
449 | gf100_gr_init_rstr2d_0[] = { | |
30f4e087 BS |
450 | { 0x407808, 1, 0x04, 0x00000000 }, |
451 | {} | |
452 | }; | |
453 | ||
e3c71eb2 BS |
454 | const struct gf100_gr_init |
455 | gf100_gr_init_pd_0[] = { | |
30f4e087 BS |
456 | { 0x406024, 1, 0x04, 0x00000000 }, |
457 | {} | |
458 | }; | |
459 | ||
e3c71eb2 BS |
460 | const struct gf100_gr_init |
461 | gf100_gr_init_ds_0[] = { | |
30f4e087 BS |
462 | { 0x405844, 1, 0x04, 0x00ffffff }, |
463 | { 0x405850, 1, 0x04, 0x00000000 }, | |
464 | { 0x405908, 1, 0x04, 0x00000000 }, | |
465 | {} | |
466 | }; | |
467 | ||
e3c71eb2 BS |
468 | const struct gf100_gr_init |
469 | gf100_gr_init_scc_0[] = { | |
30f4e087 BS |
470 | { 0x40803c, 1, 0x04, 0x00000000 }, |
471 | {} | |
472 | }; | |
473 | ||
e3c71eb2 BS |
474 | const struct gf100_gr_init |
475 | gf100_gr_init_prop_0[] = { | |
30f4e087 | 476 | { 0x4184a0, 1, 0x04, 0x00000000 }, |
97af71fa BS |
477 | {} |
478 | }; | |
479 | ||
e3c71eb2 BS |
480 | const struct gf100_gr_init |
481 | gf100_gr_init_gpc_unk_0[] = { | |
30f4e087 BS |
482 | { 0x418604, 1, 0x04, 0x00000000 }, |
483 | { 0x418680, 1, 0x04, 0x00000000 }, | |
484 | { 0x418714, 1, 0x04, 0x80000000 }, | |
485 | { 0x418384, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
486 | {} |
487 | }; | |
488 | ||
e3c71eb2 BS |
489 | const struct gf100_gr_init |
490 | gf100_gr_init_setup_0[] = { | |
30f4e087 | 491 | { 0x418814, 3, 0x04, 0x00000000 }, |
97af71fa BS |
492 | {} |
493 | }; | |
494 | ||
e3c71eb2 BS |
495 | const struct gf100_gr_init |
496 | gf100_gr_init_crstr_0[] = { | |
30f4e087 | 497 | { 0x418b04, 1, 0x04, 0x00000000 }, |
97af71fa BS |
498 | {} |
499 | }; | |
500 | ||
e3c71eb2 BS |
501 | const struct gf100_gr_init |
502 | gf100_gr_init_setup_1[] = { | |
30f4e087 BS |
503 | { 0x4188c8, 1, 0x04, 0x80000000 }, |
504 | { 0x4188cc, 1, 0x04, 0x00000000 }, | |
505 | { 0x4188d0, 1, 0x04, 0x00010000 }, | |
506 | { 0x4188d4, 1, 0x04, 0x00000001 }, | |
97af71fa BS |
507 | {} |
508 | }; | |
509 | ||
e3c71eb2 BS |
510 | const struct gf100_gr_init |
511 | gf100_gr_init_zcull_0[] = { | |
30f4e087 BS |
512 | { 0x418910, 1, 0x04, 0x00010001 }, |
513 | { 0x418914, 1, 0x04, 0x00000301 }, | |
514 | { 0x418918, 1, 0x04, 0x00800000 }, | |
515 | { 0x418980, 1, 0x04, 0x77777770 }, | |
516 | { 0x418984, 3, 0x04, 0x77777777 }, | |
97af71fa BS |
517 | {} |
518 | }; | |
519 | ||
e3c71eb2 BS |
520 | const struct gf100_gr_init |
521 | gf100_gr_init_gpm_0[] = { | |
30f4e087 BS |
522 | { 0x418c04, 1, 0x04, 0x00000000 }, |
523 | { 0x418c88, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
524 | {} |
525 | }; | |
526 | ||
e3c71eb2 BS |
527 | const struct gf100_gr_init |
528 | gf100_gr_init_gpc_unk_1[] = { | |
30f4e087 BS |
529 | { 0x418d00, 1, 0x04, 0x00000000 }, |
530 | { 0x418f08, 1, 0x04, 0x00000000 }, | |
531 | { 0x418e00, 1, 0x04, 0x00000050 }, | |
532 | { 0x418e08, 1, 0x04, 0x00000000 }, | |
97af71fa BS |
533 | {} |
534 | }; | |
535 | ||
e3c71eb2 BS |
536 | const struct gf100_gr_init |
537 | gf100_gr_init_gcc_0[] = { | |
30f4e087 BS |
538 | { 0x41900c, 1, 0x04, 0x00000000 }, |
539 | { 0x419018, 1, 0x04, 0x00000000 }, | |
540 | {} | |
541 | }; | |
542 | ||
e3c71eb2 BS |
543 | const struct gf100_gr_init |
544 | gf100_gr_init_tpccs_0[] = { | |
30f4e087 BS |
545 | { 0x419d08, 2, 0x04, 0x00000000 }, |
546 | { 0x419d10, 1, 0x04, 0x00000014 }, | |
7e194533 BS |
547 | {} |
548 | }; | |
549 | ||
e3c71eb2 BS |
550 | const struct gf100_gr_init |
551 | gf100_gr_init_tex_0[] = { | |
30f4e087 BS |
552 | { 0x419ab0, 1, 0x04, 0x00000000 }, |
553 | { 0x419ab8, 1, 0x04, 0x000000e7 }, | |
554 | { 0x419abc, 2, 0x04, 0x00000000 }, | |
7e194533 BS |
555 | {} |
556 | }; | |
557 | ||
e3c71eb2 BS |
558 | const struct gf100_gr_init |
559 | gf100_gr_init_pe_0[] = { | |
30f4e087 BS |
560 | { 0x41980c, 3, 0x04, 0x00000000 }, |
561 | { 0x419844, 1, 0x04, 0x00000000 }, | |
562 | { 0x41984c, 1, 0x04, 0x00005bc5 }, | |
563 | { 0x419850, 4, 0x04, 0x00000000 }, | |
7e194533 BS |
564 | {} |
565 | }; | |
566 | ||
e3c71eb2 BS |
567 | const struct gf100_gr_init |
568 | gf100_gr_init_l1c_0[] = { | |
30f4e087 BS |
569 | { 0x419c98, 1, 0x04, 0x00000000 }, |
570 | { 0x419ca8, 1, 0x04, 0x80000000 }, | |
571 | { 0x419cb4, 1, 0x04, 0x00000000 }, | |
572 | { 0x419cb8, 1, 0x04, 0x00008bf4 }, | |
573 | { 0x419cbc, 1, 0x04, 0x28137606 }, | |
574 | { 0x419cc0, 2, 0x04, 0x00000000 }, | |
7e194533 BS |
575 | {} |
576 | }; | |
577 | ||
e3c71eb2 BS |
578 | const struct gf100_gr_init |
579 | gf100_gr_init_wwdx_0[] = { | |
30f4e087 BS |
580 | { 0x419bd4, 1, 0x04, 0x00800000 }, |
581 | { 0x419bdc, 1, 0x04, 0x00000000 }, | |
7e194533 BS |
582 | {} |
583 | }; | |
584 | ||
e3c71eb2 BS |
585 | const struct gf100_gr_init |
586 | gf100_gr_init_tpccs_1[] = { | |
30f4e087 | 587 | { 0x419d2c, 1, 0x04, 0x00000000 }, |
7e194533 BS |
588 | {} |
589 | }; | |
590 | ||
e3c71eb2 BS |
591 | const struct gf100_gr_init |
592 | gf100_gr_init_mpc_0[] = { | |
30f4e087 | 593 | { 0x419c0c, 1, 0x04, 0x00000000 }, |
7e194533 BS |
594 | {} |
595 | }; | |
596 | ||
e3c71eb2 BS |
597 | static const struct gf100_gr_init |
598 | gf100_gr_init_sm_0[] = { | |
30f4e087 BS |
599 | { 0x419e00, 1, 0x04, 0x00000000 }, |
600 | { 0x419ea0, 1, 0x04, 0x00000000 }, | |
601 | { 0x419ea4, 1, 0x04, 0x00000100 }, | |
602 | { 0x419ea8, 1, 0x04, 0x00001100 }, | |
603 | { 0x419eac, 1, 0x04, 0x11100702 }, | |
604 | { 0x419eb0, 1, 0x04, 0x00000003 }, | |
605 | { 0x419eb4, 4, 0x04, 0x00000000 }, | |
606 | { 0x419ec8, 1, 0x04, 0x06060618 }, | |
607 | { 0x419ed0, 1, 0x04, 0x0eff0e38 }, | |
608 | { 0x419ed4, 1, 0x04, 0x011104f1 }, | |
609 | { 0x419edc, 1, 0x04, 0x00000000 }, | |
610 | { 0x419f00, 1, 0x04, 0x00000000 }, | |
611 | { 0x419f2c, 1, 0x04, 0x00000000 }, | |
612 | {} | |
613 | }; | |
614 | ||
e3c71eb2 BS |
615 | const struct gf100_gr_init |
616 | gf100_gr_init_be_0[] = { | |
30f4e087 BS |
617 | { 0x40880c, 1, 0x04, 0x00000000 }, |
618 | { 0x408910, 9, 0x04, 0x00000000 }, | |
619 | { 0x408950, 1, 0x04, 0x00000000 }, | |
620 | { 0x408954, 1, 0x04, 0x0000ffff }, | |
621 | { 0x408984, 1, 0x04, 0x00000000 }, | |
622 | { 0x408988, 1, 0x04, 0x08040201 }, | |
623 | { 0x40898c, 1, 0x04, 0x80402010 }, | |
624 | {} | |
625 | }; | |
626 | ||
e3c71eb2 BS |
627 | const struct gf100_gr_init |
628 | gf100_gr_init_fe_1[] = { | |
c33b1e8c BS |
629 | { 0x4040f0, 1, 0x04, 0x00000000 }, |
630 | {} | |
631 | }; | |
632 | ||
e3c71eb2 BS |
633 | const struct gf100_gr_init |
634 | gf100_gr_init_pe_1[] = { | |
c33b1e8c BS |
635 | { 0x419880, 1, 0x04, 0x00000002 }, |
636 | {} | |
637 | }; | |
638 | ||
e3c71eb2 BS |
639 | static const struct gf100_gr_pack |
640 | gf100_gr_pack_mmio[] = { | |
641 | { gf100_gr_init_main_0 }, | |
642 | { gf100_gr_init_fe_0 }, | |
643 | { gf100_gr_init_pri_0 }, | |
644 | { gf100_gr_init_rstr2d_0 }, | |
645 | { gf100_gr_init_pd_0 }, | |
646 | { gf100_gr_init_ds_0 }, | |
647 | { gf100_gr_init_scc_0 }, | |
648 | { gf100_gr_init_prop_0 }, | |
649 | { gf100_gr_init_gpc_unk_0 }, | |
650 | { gf100_gr_init_setup_0 }, | |
651 | { gf100_gr_init_crstr_0 }, | |
652 | { gf100_gr_init_setup_1 }, | |
653 | { gf100_gr_init_zcull_0 }, | |
654 | { gf100_gr_init_gpm_0 }, | |
655 | { gf100_gr_init_gpc_unk_1 }, | |
656 | { gf100_gr_init_gcc_0 }, | |
657 | { gf100_gr_init_tpccs_0 }, | |
658 | { gf100_gr_init_tex_0 }, | |
659 | { gf100_gr_init_pe_0 }, | |
660 | { gf100_gr_init_l1c_0 }, | |
661 | { gf100_gr_init_wwdx_0 }, | |
662 | { gf100_gr_init_tpccs_1 }, | |
663 | { gf100_gr_init_mpc_0 }, | |
664 | { gf100_gr_init_sm_0 }, | |
665 | { gf100_gr_init_be_0 }, | |
666 | { gf100_gr_init_fe_1 }, | |
667 | { gf100_gr_init_pe_1 }, | |
26410c67 ML |
668 | {} |
669 | }; | |
670 | ||
c33b1e8c BS |
671 | /******************************************************************************* |
672 | * PGRAPH engine/subdev functions | |
673 | ******************************************************************************/ | |
674 | ||
ac9738bb | 675 | void |
bfee3f3d | 676 | gf100_gr_zbc_init(struct gf100_gr *gr) |
ac9738bb BS |
677 | { |
678 | const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, | |
679 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; | |
680 | const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, | |
681 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; | |
682 | const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, | |
683 | 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; | |
684 | const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, | |
685 | 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; | |
70bc7182 | 686 | struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; |
ac9738bb BS |
687 | int index; |
688 | ||
bfee3f3d BS |
689 | if (!gr->zbc_color[0].format) { |
690 | gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); | |
691 | gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); | |
692 | gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); | |
693 | gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); | |
694 | gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); | |
695 | gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); | |
ac9738bb BS |
696 | } |
697 | ||
698 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) | |
bfee3f3d | 699 | gf100_gr_zbc_clear_color(gr, index); |
ac9738bb | 700 | for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) |
bfee3f3d | 701 | gf100_gr_zbc_clear_depth(gr, index); |
ac9738bb BS |
702 | } |
703 | ||
4a8cf451 AC |
704 | /** |
705 | * Wait until GR goes idle. GR is considered idle if it is disabled by the | |
706 | * MC (0x200) register, or GR is not busy and a context switch is not in | |
707 | * progress. | |
708 | */ | |
709 | int | |
bfee3f3d | 710 | gf100_gr_wait_idle(struct gf100_gr *gr) |
4a8cf451 | 711 | { |
109c2f2f BS |
712 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
713 | struct nvkm_device *device = subdev->device; | |
4a8cf451 AC |
714 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); |
715 | bool gr_enabled, ctxsw_active, gr_busy; | |
716 | ||
717 | do { | |
718 | /* | |
719 | * required to make sure FIFO_ENGINE_STATUS (0x2640) is | |
720 | * up-to-date | |
721 | */ | |
276836d4 | 722 | nvkm_rd32(device, 0x400700); |
4a8cf451 | 723 | |
276836d4 BS |
724 | gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; |
725 | ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; | |
726 | gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; | |
4a8cf451 AC |
727 | |
728 | if (!gr_enabled || (!gr_busy && !ctxsw_active)) | |
729 | return 0; | |
730 | } while (time_before(jiffies, end_jiffies)); | |
731 | ||
109c2f2f BS |
732 | nvkm_error(subdev, |
733 | "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", | |
734 | gr_enabled, ctxsw_active, gr_busy); | |
4a8cf451 AC |
735 | return -EAGAIN; |
736 | } | |
737 | ||
30f4e087 | 738 | void |
bfee3f3d | 739 | gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
4b223eef | 740 | { |
276836d4 | 741 | struct nvkm_device *device = gr->base.engine.subdev.device; |
e3c71eb2 BS |
742 | const struct gf100_gr_pack *pack; |
743 | const struct gf100_gr_init *init; | |
c33b1e8c BS |
744 | |
745 | pack_for_each_init(init, pack, p) { | |
746 | u32 next = init->addr + init->count * init->pitch; | |
747 | u32 addr = init->addr; | |
748 | while (addr < next) { | |
276836d4 | 749 | nvkm_wr32(device, addr, init->data); |
30f4e087 BS |
750 | addr += init->pitch; |
751 | } | |
752 | } | |
ebb945a9 BS |
753 | } |
754 | ||
755 | void | |
bfee3f3d | 756 | gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
ebb945a9 | 757 | { |
276836d4 | 758 | struct nvkm_device *device = gr->base.engine.subdev.device; |
e3c71eb2 BS |
759 | const struct gf100_gr_pack *pack; |
760 | const struct gf100_gr_init *init; | |
c33b1e8c | 761 | u32 data = 0; |
30f4e087 | 762 | |
276836d4 | 763 | nvkm_wr32(device, 0x400208, 0x80000000); |
c33b1e8c BS |
764 | |
765 | pack_for_each_init(init, pack, p) { | |
766 | u32 next = init->addr + init->count * init->pitch; | |
767 | u32 addr = init->addr; | |
768 | ||
769 | if ((pack == p && init == p->init) || data != init->data) { | |
276836d4 | 770 | nvkm_wr32(device, 0x400204, init->data); |
30f4e087 BS |
771 | data = init->data; |
772 | } | |
ebb945a9 | 773 | |
c33b1e8c | 774 | while (addr < next) { |
276836d4 | 775 | nvkm_wr32(device, 0x400200, addr); |
4a8cf451 AC |
776 | /** |
777 | * Wait for GR to go idle after submitting a | |
778 | * GO_IDLE bundle | |
779 | */ | |
780 | if ((addr & 0xffff) == 0xe100) | |
bfee3f3d | 781 | gf100_gr_wait_idle(gr); |
c4584adc BS |
782 | nvkm_msec(device, 2000, |
783 | if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) | |
784 | break; | |
785 | ); | |
30f4e087 | 786 | addr += init->pitch; |
30f4e087 BS |
787 | } |
788 | } | |
c33b1e8c | 789 | |
276836d4 | 790 | nvkm_wr32(device, 0x400208, 0x00000000); |
30f4e087 BS |
791 | } |
792 | ||
793 | void | |
bfee3f3d | 794 | gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) |
30f4e087 | 795 | { |
276836d4 | 796 | struct nvkm_device *device = gr->base.engine.subdev.device; |
e3c71eb2 BS |
797 | const struct gf100_gr_pack *pack; |
798 | const struct gf100_gr_init *init; | |
c33b1e8c | 799 | u32 data = 0; |
30f4e087 | 800 | |
c33b1e8c BS |
801 | pack_for_each_init(init, pack, p) { |
802 | u32 ctrl = 0x80000000 | pack->type; | |
803 | u32 next = init->addr + init->count * init->pitch; | |
804 | u32 addr = init->addr; | |
805 | ||
806 | if ((pack == p && init == p->init) || data != init->data) { | |
276836d4 | 807 | nvkm_wr32(device, 0x40448c, init->data); |
c33b1e8c BS |
808 | data = init->data; |
809 | } | |
810 | ||
811 | while (addr < next) { | |
276836d4 | 812 | nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); |
c33b1e8c | 813 | addr += init->pitch; |
30f4e087 BS |
814 | } |
815 | } | |
816 | } | |
817 | ||
818 | u64 | |
c85ee6ca | 819 | gf100_gr_units(struct nvkm_gr *base) |
30f4e087 | 820 | { |
c85ee6ca | 821 | struct gf100_gr *gr = gf100_gr(base); |
30f4e087 BS |
822 | u64 cfg; |
823 | ||
bfee3f3d BS |
824 | cfg = (u32)gr->gpc_nr; |
825 | cfg |= (u32)gr->tpc_total << 8; | |
826 | cfg |= (u64)gr->rop_nr << 32; | |
30f4e087 BS |
827 | |
828 | return cfg; | |
ebb945a9 BS |
829 | } |
830 | ||
109c2f2f BS |
831 | static const struct nvkm_bitfield gk104_sked_error[] = { |
832 | { 0x00000080, "CONSTANT_BUFFER_SIZE" }, | |
833 | { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, | |
834 | { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, | |
835 | { 0x00000800, "WARP_CSTACK_SIZE" }, | |
836 | { 0x00001000, "TOTAL_TEMP_SIZE" }, | |
837 | { 0x00002000, "REGISTER_COUNT" }, | |
838 | { 0x00040000, "TOTAL_THREADS" }, | |
839 | { 0x00100000, "PROGRAM_OFFSET" }, | |
840 | { 0x00200000, "SHARED_MEMORY_SIZE" }, | |
841 | { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, | |
842 | { 0x04000000, "TOTAL_REGISTER_COUNT" }, | |
30f4e087 BS |
843 | {} |
844 | }; | |
845 | ||
109c2f2f BS |
846 | static const struct nvkm_bitfield gf100_gpc_rop_error[] = { |
847 | { 0x00000002, "RT_PITCH_OVERRUN" }, | |
848 | { 0x00000010, "RT_WIDTH_OVERRUN" }, | |
849 | { 0x00000020, "RT_HEIGHT_OVERRUN" }, | |
850 | { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, | |
851 | { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, | |
852 | { 0x00000400, "RT_LINEAR_MISMATCH" }, | |
30f4e087 BS |
853 | {} |
854 | }; | |
855 | ||
ebb945a9 | 856 | static void |
bfee3f3d | 857 | gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) |
ebb945a9 | 858 | { |
109c2f2f BS |
859 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
860 | struct nvkm_device *device = subdev->device; | |
861 | char error[128]; | |
30f4e087 | 862 | u32 trap[4]; |
ebb945a9 | 863 | |
109c2f2f | 864 | trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; |
276836d4 BS |
865 | trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); |
866 | trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); | |
867 | trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); | |
ebb945a9 | 868 | |
109c2f2f | 869 | nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); |
30f4e087 | 870 | |
109c2f2f BS |
871 | nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " |
872 | "format = %x, storage type = %x\n", | |
873 | gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, | |
874 | (trap[2] >> 8) & 0x3f, trap[3] & 0xff); | |
276836d4 | 875 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
ebb945a9 BS |
876 | } |
877 | ||
e3c71eb2 | 878 | static const struct nvkm_enum gf100_mp_warp_error[] = { |
fec43a72 BS |
879 | { 0x00, "NO_ERROR" }, |
880 | { 0x01, "STACK_MISMATCH" }, | |
881 | { 0x05, "MISALIGNED_PC" }, | |
882 | { 0x08, "MISALIGNED_GPR" }, | |
883 | { 0x09, "INVALID_OPCODE" }, | |
884 | { 0x0d, "GPR_OUT_OF_BOUNDS" }, | |
885 | { 0x0e, "MEM_OUT_OF_BOUNDS" }, | |
886 | { 0x0f, "UNALIGNED_MEM_ACCESS" }, | |
3988f645 | 887 | { 0x10, "INVALID_ADDR_SPACE" }, |
fec43a72 BS |
888 | { 0x11, "INVALID_PARAM" }, |
889 | {} | |
890 | }; | |
891 | ||
e3c71eb2 | 892 | static const struct nvkm_bitfield gf100_mp_global_error[] = { |
fec43a72 BS |
893 | { 0x00000004, "MULTIPLE_WARP_ERRORS" }, |
894 | { 0x00000008, "OUT_OF_STACK_SPACE" }, | |
895 | {} | |
896 | }; | |
897 | ||
898 | static void | |
bfee3f3d | 899 | gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) |
fec43a72 | 900 | { |
109c2f2f BS |
901 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
902 | struct nvkm_device *device = subdev->device; | |
276836d4 BS |
903 | u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); |
904 | u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); | |
109c2f2f BS |
905 | const struct nvkm_enum *warp; |
906 | char glob[128]; | |
fec43a72 | 907 | |
109c2f2f BS |
908 | nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); |
909 | warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); | |
910 | ||
911 | nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " | |
912 | "global %08x [%s] warp %04x [%s]\n", | |
913 | gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); | |
fec43a72 | 914 | |
276836d4 BS |
915 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); |
916 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); | |
fec43a72 BS |
917 | } |
918 | ||
f73221e4 | 919 | static void |
bfee3f3d | 920 | gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) |
f73221e4 | 921 | { |
109c2f2f BS |
922 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
923 | struct nvkm_device *device = subdev->device; | |
276836d4 | 924 | u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); |
f73221e4 BS |
925 | |
926 | if (stat & 0x00000001) { | |
276836d4 | 927 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); |
109c2f2f | 928 | nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); |
276836d4 | 929 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); |
f73221e4 BS |
930 | stat &= ~0x00000001; |
931 | } | |
932 | ||
933 | if (stat & 0x00000002) { | |
bfee3f3d | 934 | gf100_gr_trap_mp(gr, gpc, tpc); |
f73221e4 BS |
935 | stat &= ~0x00000002; |
936 | } | |
937 | ||
938 | if (stat & 0x00000004) { | |
276836d4 | 939 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); |
109c2f2f | 940 | nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); |
276836d4 | 941 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); |
f73221e4 BS |
942 | stat &= ~0x00000004; |
943 | } | |
944 | ||
945 | if (stat & 0x00000008) { | |
276836d4 | 946 | u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); |
109c2f2f | 947 | nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); |
276836d4 | 948 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); |
f73221e4 BS |
949 | stat &= ~0x00000008; |
950 | } | |
951 | ||
952 | if (stat) { | |
109c2f2f | 953 | nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); |
f73221e4 BS |
954 | } |
955 | } | |
956 | ||
957 | static void | |
bfee3f3d | 958 | gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) |
f73221e4 | 959 | { |
109c2f2f BS |
960 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
961 | struct nvkm_device *device = subdev->device; | |
276836d4 | 962 | u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); |
f73221e4 BS |
963 | int tpc; |
964 | ||
965 | if (stat & 0x00000001) { | |
bfee3f3d | 966 | gf100_gr_trap_gpc_rop(gr, gpc); |
f73221e4 BS |
967 | stat &= ~0x00000001; |
968 | } | |
969 | ||
970 | if (stat & 0x00000002) { | |
276836d4 | 971 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); |
109c2f2f | 972 | nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); |
276836d4 | 973 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); |
f73221e4 BS |
974 | stat &= ~0x00000002; |
975 | } | |
976 | ||
977 | if (stat & 0x00000004) { | |
276836d4 | 978 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); |
109c2f2f | 979 | nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); |
276836d4 | 980 | nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); |
f73221e4 BS |
981 | stat &= ~0x00000004; |
982 | } | |
983 | ||
984 | if (stat & 0x00000008) { | |
276836d4 | 985 | u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); |
109c2f2f | 986 | nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); |
276836d4 | 987 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); |
f73221e4 BS |
988 | stat &= ~0x00000009; |
989 | } | |
990 | ||
bfee3f3d | 991 | for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { |
f73221e4 BS |
992 | u32 mask = 0x00010000 << tpc; |
993 | if (stat & mask) { | |
bfee3f3d | 994 | gf100_gr_trap_tpc(gr, gpc, tpc); |
276836d4 | 995 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); |
f73221e4 BS |
996 | stat &= ~mask; |
997 | } | |
998 | } | |
999 | ||
1000 | if (stat) { | |
109c2f2f | 1001 | nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); |
f73221e4 BS |
1002 | } |
1003 | } | |
1004 | ||
1005 | static void | |
bfee3f3d | 1006 | gf100_gr_trap_intr(struct gf100_gr *gr) |
f73221e4 | 1007 | { |
109c2f2f BS |
1008 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1009 | struct nvkm_device *device = subdev->device; | |
276836d4 | 1010 | u32 trap = nvkm_rd32(device, 0x400108); |
109c2f2f | 1011 | int rop, gpc; |
f73221e4 BS |
1012 | |
1013 | if (trap & 0x00000001) { | |
276836d4 | 1014 | u32 stat = nvkm_rd32(device, 0x404000); |
109c2f2f | 1015 | nvkm_error(subdev, "DISPATCH %08x\n", stat); |
276836d4 BS |
1016 | nvkm_wr32(device, 0x404000, 0xc0000000); |
1017 | nvkm_wr32(device, 0x400108, 0x00000001); | |
f73221e4 BS |
1018 | trap &= ~0x00000001; |
1019 | } | |
1020 | ||
1021 | if (trap & 0x00000002) { | |
276836d4 | 1022 | u32 stat = nvkm_rd32(device, 0x404600); |
109c2f2f | 1023 | nvkm_error(subdev, "M2MF %08x\n", stat); |
276836d4 BS |
1024 | nvkm_wr32(device, 0x404600, 0xc0000000); |
1025 | nvkm_wr32(device, 0x400108, 0x00000002); | |
f73221e4 BS |
1026 | trap &= ~0x00000002; |
1027 | } | |
1028 | ||
1029 | if (trap & 0x00000008) { | |
276836d4 | 1030 | u32 stat = nvkm_rd32(device, 0x408030); |
109c2f2f | 1031 | nvkm_error(subdev, "CCACHE %08x\n", stat); |
276836d4 BS |
1032 | nvkm_wr32(device, 0x408030, 0xc0000000); |
1033 | nvkm_wr32(device, 0x400108, 0x00000008); | |
f73221e4 BS |
1034 | trap &= ~0x00000008; |
1035 | } | |
1036 | ||
1037 | if (trap & 0x00000010) { | |
276836d4 | 1038 | u32 stat = nvkm_rd32(device, 0x405840); |
109c2f2f | 1039 | nvkm_error(subdev, "SHADER %08x\n", stat); |
276836d4 BS |
1040 | nvkm_wr32(device, 0x405840, 0xc0000000); |
1041 | nvkm_wr32(device, 0x400108, 0x00000010); | |
f73221e4 BS |
1042 | trap &= ~0x00000010; |
1043 | } | |
1044 | ||
1045 | if (trap & 0x00000040) { | |
276836d4 | 1046 | u32 stat = nvkm_rd32(device, 0x40601c); |
109c2f2f | 1047 | nvkm_error(subdev, "UNK6 %08x\n", stat); |
276836d4 BS |
1048 | nvkm_wr32(device, 0x40601c, 0xc0000000); |
1049 | nvkm_wr32(device, 0x400108, 0x00000040); | |
f73221e4 BS |
1050 | trap &= ~0x00000040; |
1051 | } | |
1052 | ||
1053 | if (trap & 0x00000080) { | |
276836d4 | 1054 | u32 stat = nvkm_rd32(device, 0x404490); |
109c2f2f | 1055 | nvkm_error(subdev, "MACRO %08x\n", stat); |
276836d4 BS |
1056 | nvkm_wr32(device, 0x404490, 0xc0000000); |
1057 | nvkm_wr32(device, 0x400108, 0x00000080); | |
f73221e4 BS |
1058 | trap &= ~0x00000080; |
1059 | } | |
1060 | ||
30f4e087 | 1061 | if (trap & 0x00000100) { |
109c2f2f BS |
1062 | u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; |
1063 | char sked[128]; | |
30f4e087 | 1064 | |
109c2f2f BS |
1065 | nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat); |
1066 | nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked); | |
30f4e087 | 1067 | |
109c2f2f | 1068 | if (stat) |
276836d4 BS |
1069 | nvkm_wr32(device, 0x407020, 0x40000000); |
1070 | nvkm_wr32(device, 0x400108, 0x00000100); | |
30f4e087 BS |
1071 | trap &= ~0x00000100; |
1072 | } | |
1073 | ||
f73221e4 | 1074 | if (trap & 0x01000000) { |
276836d4 | 1075 | u32 stat = nvkm_rd32(device, 0x400118); |
bfee3f3d | 1076 | for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { |
f73221e4 BS |
1077 | u32 mask = 0x00000001 << gpc; |
1078 | if (stat & mask) { | |
bfee3f3d | 1079 | gf100_gr_trap_gpc(gr, gpc); |
276836d4 | 1080 | nvkm_wr32(device, 0x400118, mask); |
f73221e4 BS |
1081 | stat &= ~mask; |
1082 | } | |
1083 | } | |
276836d4 | 1084 | nvkm_wr32(device, 0x400108, 0x01000000); |
f73221e4 BS |
1085 | trap &= ~0x01000000; |
1086 | } | |
1087 | ||
1088 | if (trap & 0x02000000) { | |
bfee3f3d | 1089 | for (rop = 0; rop < gr->rop_nr; rop++) { |
276836d4 BS |
1090 | u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); |
1091 | u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); | |
109c2f2f | 1092 | nvkm_error(subdev, "ROP%d %08x %08x\n", |
f73221e4 | 1093 | rop, statz, statc); |
276836d4 BS |
1094 | nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); |
1095 | nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); | |
f73221e4 | 1096 | } |
276836d4 | 1097 | nvkm_wr32(device, 0x400108, 0x02000000); |
f73221e4 BS |
1098 | trap &= ~0x02000000; |
1099 | } | |
1100 | ||
1101 | if (trap) { | |
109c2f2f | 1102 | nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); |
276836d4 | 1103 | nvkm_wr32(device, 0x400108, trap); |
f73221e4 BS |
1104 | } |
1105 | } | |
1106 | ||
30f4e087 | 1107 | static void |
bfee3f3d | 1108 | gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) |
30f4e087 | 1109 | { |
109c2f2f BS |
1110 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1111 | struct nvkm_device *device = subdev->device; | |
1112 | nvkm_error(subdev, "%06x - done %08x\n", base, | |
1113 | nvkm_rd32(device, base + 0x400)); | |
1114 | nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, | |
1115 | nvkm_rd32(device, base + 0x800), | |
1116 | nvkm_rd32(device, base + 0x804), | |
1117 | nvkm_rd32(device, base + 0x808), | |
1118 | nvkm_rd32(device, base + 0x80c)); | |
1119 | nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, | |
1120 | nvkm_rd32(device, base + 0x810), | |
1121 | nvkm_rd32(device, base + 0x814), | |
1122 | nvkm_rd32(device, base + 0x818), | |
1123 | nvkm_rd32(device, base + 0x81c)); | |
30f4e087 BS |
1124 | } |
1125 | ||
1126 | void | |
bfee3f3d | 1127 | gf100_gr_ctxctl_debug(struct gf100_gr *gr) |
30f4e087 | 1128 | { |
276836d4 BS |
1129 | struct nvkm_device *device = gr->base.engine.subdev.device; |
1130 | u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; | |
30f4e087 BS |
1131 | u32 gpc; |
1132 | ||
bfee3f3d | 1133 | gf100_gr_ctxctl_debug_unit(gr, 0x409000); |
30f4e087 | 1134 | for (gpc = 0; gpc < gpcnr; gpc++) |
bfee3f3d | 1135 | gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); |
30f4e087 BS |
1136 | } |
1137 | ||
1138 | static void | |
bfee3f3d | 1139 | gf100_gr_ctxctl_isr(struct gf100_gr *gr) |
30f4e087 | 1140 | { |
109c2f2f BS |
1141 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1142 | struct nvkm_device *device = subdev->device; | |
276836d4 | 1143 | u32 stat = nvkm_rd32(device, 0x409c18); |
30f4e087 | 1144 | |
23f67841 | 1145 | if (stat & 0x00000001) { |
276836d4 | 1146 | u32 code = nvkm_rd32(device, 0x409814); |
23f67841 | 1147 | if (code == E_BAD_FWMTHD) { |
276836d4 BS |
1148 | u32 class = nvkm_rd32(device, 0x409808); |
1149 | u32 addr = nvkm_rd32(device, 0x40980c); | |
23f67841 BS |
1150 | u32 subc = (addr & 0x00070000) >> 16; |
1151 | u32 mthd = (addr & 0x00003ffc); | |
276836d4 | 1152 | u32 data = nvkm_rd32(device, 0x409810); |
23f67841 | 1153 | |
109c2f2f BS |
1154 | nvkm_error(subdev, "FECS MTHD subc %d class %04x " |
1155 | "mthd %04x data %08x\n", | |
1156 | subc, class, mthd, data); | |
23f67841 | 1157 | |
276836d4 | 1158 | nvkm_wr32(device, 0x409c20, 0x00000001); |
23f67841 BS |
1159 | stat &= ~0x00000001; |
1160 | } else { | |
109c2f2f | 1161 | nvkm_error(subdev, "FECS ucode error %d\n", code); |
23f67841 BS |
1162 | } |
1163 | } | |
30f4e087 | 1164 | |
23f67841 | 1165 | if (stat & 0x00080000) { |
109c2f2f | 1166 | nvkm_error(subdev, "FECS watchdog timeout\n"); |
bfee3f3d | 1167 | gf100_gr_ctxctl_debug(gr); |
276836d4 | 1168 | nvkm_wr32(device, 0x409c20, 0x00080000); |
23f67841 BS |
1169 | stat &= ~0x00080000; |
1170 | } | |
1171 | ||
1172 | if (stat) { | |
109c2f2f | 1173 | nvkm_error(subdev, "FECS %08x\n", stat); |
bfee3f3d | 1174 | gf100_gr_ctxctl_debug(gr); |
276836d4 | 1175 | nvkm_wr32(device, 0x409c20, stat); |
23f67841 | 1176 | } |
30f4e087 BS |
1177 | } |
1178 | ||
ebb945a9 | 1179 | static void |
c85ee6ca | 1180 | gf100_gr_intr(struct nvkm_gr *base) |
ebb945a9 | 1181 | { |
c85ee6ca BS |
1182 | struct gf100_gr *gr = gf100_gr(base); |
1183 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; | |
1184 | struct nvkm_device *device = subdev->device; | |
a65955e1 BS |
1185 | struct nvkm_fifo_chan *chan; |
1186 | unsigned long flags; | |
276836d4 BS |
1187 | u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; |
1188 | u32 stat = nvkm_rd32(device, 0x400100); | |
1189 | u32 addr = nvkm_rd32(device, 0x400704); | |
ebb945a9 BS |
1190 | u32 mthd = (addr & 0x00003ffc); |
1191 | u32 subc = (addr & 0x00070000) >> 16; | |
276836d4 BS |
1192 | u32 data = nvkm_rd32(device, 0x400708); |
1193 | u32 code = nvkm_rd32(device, 0x400110); | |
91c772ec | 1194 | u32 class; |
8f0649b5 BS |
1195 | const char *name = "unknown"; |
1196 | int chid = -1; | |
72a14827 | 1197 | |
a65955e1 | 1198 | chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); |
8f0649b5 BS |
1199 | if (chan) { |
1200 | name = chan->object.client->name; | |
1201 | chid = chan->chid; | |
1202 | } | |
a65955e1 | 1203 | |
c85ee6ca | 1204 | if (device->card_type < NV_E0 || subc < 4) |
276836d4 | 1205 | class = nvkm_rd32(device, 0x404200 + (subc * 4)); |
91c772ec BS |
1206 | else |
1207 | class = 0x0000; | |
1208 | ||
c6a7b026 LP |
1209 | if (stat & 0x00000001) { |
1210 | /* | |
1211 | * notifier interrupt, only needed for cyclestats | |
1212 | * can be safely ignored | |
1213 | */ | |
276836d4 | 1214 | nvkm_wr32(device, 0x400100, 0x00000001); |
c6a7b026 LP |
1215 | stat &= ~0x00000001; |
1216 | } | |
1217 | ||
ebb945a9 | 1218 | if (stat & 0x00000010) { |
a65955e1 | 1219 | if (!gf100_gr_mthd_sw(device, class, mthd, data)) { |
109c2f2f BS |
1220 | nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " |
1221 | "subc %d class %04x mthd %04x data %08x\n", | |
8f0649b5 BS |
1222 | chid, inst << 12, name, subc, |
1223 | class, mthd, data); | |
ebb945a9 | 1224 | } |
276836d4 | 1225 | nvkm_wr32(device, 0x400100, 0x00000010); |
ebb945a9 BS |
1226 | stat &= ~0x00000010; |
1227 | } | |
1228 | ||
1229 | if (stat & 0x00000020) { | |
109c2f2f BS |
1230 | nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " |
1231 | "subc %d class %04x mthd %04x data %08x\n", | |
8f0649b5 | 1232 | chid, inst << 12, name, subc, class, mthd, data); |
276836d4 | 1233 | nvkm_wr32(device, 0x400100, 0x00000020); |
ebb945a9 BS |
1234 | stat &= ~0x00000020; |
1235 | } | |
1236 | ||
1237 | if (stat & 0x00100000) { | |
109c2f2f BS |
1238 | const struct nvkm_enum *en = |
1239 | nvkm_enum_find(nv50_data_error_names, code); | |
1240 | nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " | |
1241 | "subc %d class %04x mthd %04x data %08x\n", | |
1242 | code, en ? en->name : "", chid, inst << 12, | |
8f0649b5 | 1243 | name, subc, class, mthd, data); |
276836d4 | 1244 | nvkm_wr32(device, 0x400100, 0x00100000); |
ebb945a9 BS |
1245 | stat &= ~0x00100000; |
1246 | } | |
1247 | ||
1248 | if (stat & 0x00200000) { | |
109c2f2f | 1249 | nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", |
8f0649b5 | 1250 | chid, inst << 12, name); |
bfee3f3d | 1251 | gf100_gr_trap_intr(gr); |
276836d4 | 1252 | nvkm_wr32(device, 0x400100, 0x00200000); |
ebb945a9 BS |
1253 | stat &= ~0x00200000; |
1254 | } | |
1255 | ||
1256 | if (stat & 0x00080000) { | |
bfee3f3d | 1257 | gf100_gr_ctxctl_isr(gr); |
276836d4 | 1258 | nvkm_wr32(device, 0x400100, 0x00080000); |
ebb945a9 BS |
1259 | stat &= ~0x00080000; |
1260 | } | |
1261 | ||
1262 | if (stat) { | |
109c2f2f | 1263 | nvkm_error(subdev, "intr %08x\n", stat); |
276836d4 | 1264 | nvkm_wr32(device, 0x400100, stat); |
ebb945a9 BS |
1265 | } |
1266 | ||
276836d4 | 1267 | nvkm_wr32(device, 0x400500, 0x00010001); |
a65955e1 | 1268 | nvkm_fifo_chan_put(device->fifo, flags, &chan); |
ebb945a9 BS |
1269 | } |
1270 | ||
30f4e087 | 1271 | void |
bfee3f3d | 1272 | gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, |
e3c71eb2 | 1273 | struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) |
ebb945a9 | 1274 | { |
276836d4 | 1275 | struct nvkm_device *device = gr->base.engine.subdev.device; |
30f4e087 | 1276 | int i; |
ebb945a9 | 1277 | |
276836d4 | 1278 | nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); |
30f4e087 | 1279 | for (i = 0; i < data->size / 4; i++) |
276836d4 | 1280 | nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); |
ebb945a9 | 1281 | |
276836d4 | 1282 | nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); |
30f4e087 BS |
1283 | for (i = 0; i < code->size / 4; i++) { |
1284 | if ((i & 0x3f) == 0) | |
276836d4 BS |
1285 | nvkm_wr32(device, fuc_base + 0x0188, i >> 6); |
1286 | nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); | |
30f4e087 | 1287 | } |
370eec76 AC |
1288 | |
1289 | /* code must be padded to 0x40 words */ | |
1290 | for (; i & 0x3f; i++) | |
276836d4 | 1291 | nvkm_wr32(device, fuc_base + 0x0184, 0); |
966a5b7d BS |
1292 | } |
1293 | ||
a32b2ffb | 1294 | static void |
bfee3f3d | 1295 | gf100_gr_init_csdata(struct gf100_gr *gr, |
e3c71eb2 BS |
1296 | const struct gf100_gr_pack *pack, |
1297 | u32 falcon, u32 starstar, u32 base) | |
a32b2ffb | 1298 | { |
276836d4 | 1299 | struct nvkm_device *device = gr->base.engine.subdev.device; |
e3c71eb2 BS |
1300 | const struct gf100_gr_pack *iter; |
1301 | const struct gf100_gr_init *init; | |
c33b1e8c | 1302 | u32 addr = ~0, prev = ~0, xfer = 0; |
a32b2ffb BS |
1303 | u32 star, temp; |
1304 | ||
276836d4 BS |
1305 | nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); |
1306 | star = nvkm_rd32(device, falcon + 0x01c4); | |
1307 | temp = nvkm_rd32(device, falcon + 0x01c4); | |
a32b2ffb BS |
1308 | if (temp > star) |
1309 | star = temp; | |
276836d4 | 1310 | nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); |
a32b2ffb | 1311 | |
c33b1e8c BS |
1312 | pack_for_each_init(init, iter, pack) { |
1313 | u32 head = init->addr - base; | |
1314 | u32 tail = head + init->count * init->pitch; | |
1315 | while (head < tail) { | |
1316 | if (head != prev + 4 || xfer >= 32) { | |
1317 | if (xfer) { | |
1318 | u32 data = ((--xfer << 26) | addr); | |
276836d4 | 1319 | nvkm_wr32(device, falcon + 0x01c4, data); |
c33b1e8c BS |
1320 | star += 4; |
1321 | } | |
1322 | addr = head; | |
1323 | xfer = 0; | |
a32b2ffb | 1324 | } |
c33b1e8c BS |
1325 | prev = head; |
1326 | xfer = xfer + 1; | |
1327 | head = head + init->pitch; | |
a32b2ffb | 1328 | } |
c33b1e8c | 1329 | } |
a32b2ffb | 1330 | |
276836d4 BS |
1331 | nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); |
1332 | nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); | |
1333 | nvkm_wr32(device, falcon + 0x01c4, star + 4); | |
a32b2ffb BS |
1334 | } |
1335 | ||
30f4e087 | 1336 | int |
bfee3f3d | 1337 | gf100_gr_init_ctxctl(struct gf100_gr *gr) |
966a5b7d | 1338 | { |
27f3d6cf | 1339 | const struct gf100_grctx_func *grctx = gr->func->grctx; |
109c2f2f BS |
1340 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; |
1341 | struct nvkm_device *device = subdev->device; | |
30f4e087 | 1342 | int i; |
ebb945a9 | 1343 | |
bfee3f3d | 1344 | if (gr->firmware) { |
30f4e087 | 1345 | /* load fuc microcode */ |
54dcadd5 | 1346 | nvkm_mc_unk260(device->mc, 0); |
c85ee6ca BS |
1347 | gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d); |
1348 | gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad); | |
54dcadd5 | 1349 | nvkm_mc_unk260(device->mc, 1); |
ebb945a9 | 1350 | |
30f4e087 | 1351 | /* start both of them running */ |
276836d4 BS |
1352 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1353 | nvkm_wr32(device, 0x41a10c, 0x00000000); | |
1354 | nvkm_wr32(device, 0x40910c, 0x00000000); | |
1355 | nvkm_wr32(device, 0x41a100, 0x00000002); | |
1356 | nvkm_wr32(device, 0x409100, 0x00000002); | |
c4584adc BS |
1357 | if (nvkm_msec(device, 2000, |
1358 | if (nvkm_rd32(device, 0x409800) & 0x00000001) | |
1359 | break; | |
1360 | ) < 0) | |
1361 | return -EBUSY; | |
bfee3f3d | 1362 | |
276836d4 BS |
1363 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1364 | nvkm_wr32(device, 0x409500, 0x7fffffff); | |
1365 | nvkm_wr32(device, 0x409504, 0x00000021); | |
bfee3f3d | 1366 | |
276836d4 BS |
1367 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1368 | nvkm_wr32(device, 0x409500, 0x00000000); | |
1369 | nvkm_wr32(device, 0x409504, 0x00000010); | |
c4584adc BS |
1370 | if (nvkm_msec(device, 2000, |
1371 | if ((gr->size = nvkm_rd32(device, 0x409800))) | |
1372 | break; | |
1373 | ) < 0) | |
30f4e087 | 1374 | return -EBUSY; |
0411de85 | 1375 | |
276836d4 BS |
1376 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1377 | nvkm_wr32(device, 0x409500, 0x00000000); | |
1378 | nvkm_wr32(device, 0x409504, 0x00000016); | |
c4584adc BS |
1379 | if (nvkm_msec(device, 2000, |
1380 | if (nvkm_rd32(device, 0x409800)) | |
1381 | break; | |
1382 | ) < 0) | |
ac1499d9 | 1383 | return -EBUSY; |
ac1499d9 | 1384 | |
276836d4 BS |
1385 | nvkm_wr32(device, 0x409840, 0xffffffff); |
1386 | nvkm_wr32(device, 0x409500, 0x00000000); | |
1387 | nvkm_wr32(device, 0x409504, 0x00000025); | |
c4584adc BS |
1388 | if (nvkm_msec(device, 2000, |
1389 | if (nvkm_rd32(device, 0x409800)) | |
1390 | break; | |
1391 | ) < 0) | |
ac1499d9 | 1392 | return -EBUSY; |
ac1499d9 | 1393 | |
c85ee6ca | 1394 | if (device->chipset >= 0xe0) { |
276836d4 BS |
1395 | nvkm_wr32(device, 0x409800, 0x00000000); |
1396 | nvkm_wr32(device, 0x409500, 0x00000001); | |
1397 | nvkm_wr32(device, 0x409504, 0x00000030); | |
c4584adc BS |
1398 | if (nvkm_msec(device, 2000, |
1399 | if (nvkm_rd32(device, 0x409800)) | |
1400 | break; | |
1401 | ) < 0) | |
30f4e087 | 1402 | return -EBUSY; |
30f4e087 | 1403 | |
276836d4 BS |
1404 | nvkm_wr32(device, 0x409810, 0xb00095c8); |
1405 | nvkm_wr32(device, 0x409800, 0x00000000); | |
1406 | nvkm_wr32(device, 0x409500, 0x00000001); | |
1407 | nvkm_wr32(device, 0x409504, 0x00000031); | |
c4584adc BS |
1408 | if (nvkm_msec(device, 2000, |
1409 | if (nvkm_rd32(device, 0x409800)) | |
1410 | break; | |
1411 | ) < 0) | |
30f4e087 | 1412 | return -EBUSY; |
30f4e087 | 1413 | |
276836d4 BS |
1414 | nvkm_wr32(device, 0x409810, 0x00080420); |
1415 | nvkm_wr32(device, 0x409800, 0x00000000); | |
1416 | nvkm_wr32(device, 0x409500, 0x00000001); | |
1417 | nvkm_wr32(device, 0x409504, 0x00000032); | |
c4584adc BS |
1418 | if (nvkm_msec(device, 2000, |
1419 | if (nvkm_rd32(device, 0x409800)) | |
1420 | break; | |
1421 | ) < 0) | |
30f4e087 | 1422 | return -EBUSY; |
30f4e087 | 1423 | |
276836d4 BS |
1424 | nvkm_wr32(device, 0x409614, 0x00000070); |
1425 | nvkm_wr32(device, 0x409614, 0x00000770); | |
1426 | nvkm_wr32(device, 0x40802c, 0x00000001); | |
30f4e087 BS |
1427 | } |
1428 | ||
bfee3f3d BS |
1429 | if (gr->data == NULL) { |
1430 | int ret = gf100_grctx_generate(gr); | |
ebb945a9 | 1431 | if (ret) { |
109c2f2f | 1432 | nvkm_error(subdev, "failed to construct context\n"); |
ebb945a9 BS |
1433 | return ret; |
1434 | } | |
1435 | } | |
1436 | ||
1437 | return 0; | |
96616b4c | 1438 | } else |
c85ee6ca | 1439 | if (!gr->func->fecs.ucode) { |
96616b4c | 1440 | return -ENOSYS; |
0411de85 | 1441 | } |
966a5b7d | 1442 | |
ac1499d9 | 1443 | /* load HUB microcode */ |
54dcadd5 | 1444 | nvkm_mc_unk260(device->mc, 0); |
276836d4 | 1445 | nvkm_wr32(device, 0x4091c0, 0x01000000); |
c85ee6ca BS |
1446 | for (i = 0; i < gr->func->fecs.ucode->data.size / 4; i++) |
1447 | nvkm_wr32(device, 0x4091c4, gr->func->fecs.ucode->data.data[i]); | |
ac1499d9 | 1448 | |
276836d4 | 1449 | nvkm_wr32(device, 0x409180, 0x01000000); |
c85ee6ca | 1450 | for (i = 0; i < gr->func->fecs.ucode->code.size / 4; i++) { |
ac1499d9 | 1451 | if ((i & 0x3f) == 0) |
276836d4 | 1452 | nvkm_wr32(device, 0x409188, i >> 6); |
c85ee6ca | 1453 | nvkm_wr32(device, 0x409184, gr->func->fecs.ucode->code.data[i]); |
ac1499d9 BS |
1454 | } |
1455 | ||
1456 | /* load GPC microcode */ | |
276836d4 | 1457 | nvkm_wr32(device, 0x41a1c0, 0x01000000); |
c85ee6ca BS |
1458 | for (i = 0; i < gr->func->gpccs.ucode->data.size / 4; i++) |
1459 | nvkm_wr32(device, 0x41a1c4, gr->func->gpccs.ucode->data.data[i]); | |
ac1499d9 | 1460 | |
276836d4 | 1461 | nvkm_wr32(device, 0x41a180, 0x01000000); |
c85ee6ca | 1462 | for (i = 0; i < gr->func->gpccs.ucode->code.size / 4; i++) { |
ac1499d9 | 1463 | if ((i & 0x3f) == 0) |
276836d4 | 1464 | nvkm_wr32(device, 0x41a188, i >> 6); |
c85ee6ca | 1465 | nvkm_wr32(device, 0x41a184, gr->func->gpccs.ucode->code.data[i]); |
ac1499d9 | 1466 | } |
54dcadd5 | 1467 | nvkm_mc_unk260(device->mc, 1); |
966a5b7d | 1468 | |
c33b1e8c | 1469 | /* load register lists */ |
27f3d6cf BS |
1470 | gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); |
1471 | gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000); | |
1472 | gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); | |
1473 | gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); | |
a32b2ffb | 1474 | |
ac1499d9 | 1475 | /* start HUB ucode running, it'll init the GPCs */ |
276836d4 BS |
1476 | nvkm_wr32(device, 0x40910c, 0x00000000); |
1477 | nvkm_wr32(device, 0x409100, 0x00000002); | |
c4584adc BS |
1478 | if (nvkm_msec(device, 2000, |
1479 | if (nvkm_rd32(device, 0x409800) & 0x80000000) | |
1480 | break; | |
1481 | ) < 0) { | |
bfee3f3d | 1482 | gf100_gr_ctxctl_debug(gr); |
966a5b7d BS |
1483 | return -EBUSY; |
1484 | } | |
966a5b7d | 1485 | |
276836d4 | 1486 | gr->size = nvkm_rd32(device, 0x409804); |
bfee3f3d BS |
1487 | if (gr->data == NULL) { |
1488 | int ret = gf100_grctx_generate(gr); | |
ac1499d9 | 1489 | if (ret) { |
109c2f2f | 1490 | nvkm_error(subdev, "failed to construct context\n"); |
ac1499d9 BS |
1491 | return ret; |
1492 | } | |
966a5b7d BS |
1493 | } |
1494 | ||
1495 | return 0; | |
4b223eef BS |
1496 | } |
1497 | ||
c85ee6ca BS |
1498 | static int |
1499 | gf100_gr_oneinit(struct nvkm_gr *base) | |
1500 | { | |
1501 | struct gf100_gr *gr = gf100_gr(base); | |
1502 | struct nvkm_device *device = gr->base.engine.subdev.device; | |
1503 | int ret, i, j; | |
1504 | ||
1505 | nvkm_pmu_pgob(device->pmu, false); | |
1506 | ||
1507 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, | |
1508 | &gr->unk4188b4); | |
1509 | if (ret) | |
1510 | return ret; | |
1511 | ||
1512 | ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, | |
1513 | &gr->unk4188b8); | |
1514 | if (ret) | |
1515 | return ret; | |
1516 | ||
1517 | nvkm_kmap(gr->unk4188b4); | |
1518 | for (i = 0; i < 0x1000; i += 4) | |
1519 | nvkm_wo32(gr->unk4188b4, i, 0x00000010); | |
1520 | nvkm_done(gr->unk4188b4); | |
1521 | ||
1522 | nvkm_kmap(gr->unk4188b8); | |
1523 | for (i = 0; i < 0x1000; i += 4) | |
1524 | nvkm_wo32(gr->unk4188b8, i, 0x00000010); | |
1525 | nvkm_done(gr->unk4188b8); | |
1526 | ||
1527 | gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; | |
1528 | gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; | |
1529 | for (i = 0; i < gr->gpc_nr; i++) { | |
1530 | gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); | |
1531 | gr->tpc_total += gr->tpc_nr[i]; | |
1532 | gr->ppc_nr[i] = gr->func->ppc_nr; | |
1533 | for (j = 0; j < gr->ppc_nr[i]; j++) { | |
1534 | u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); | |
2fb2b3c6 BS |
1535 | if (mask) |
1536 | gr->ppc_mask[i] |= (1 << j); | |
c85ee6ca BS |
1537 | gr->ppc_tpc_nr[i][j] = hweight8(mask); |
1538 | } | |
1539 | } | |
1540 | ||
1541 | /*XXX: these need figuring out... though it might not even matter */ | |
1542 | switch (device->chipset) { | |
1543 | case 0xc0: | |
1544 | if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ | |
1545 | gr->magic_not_rop_nr = 0x07; | |
1546 | } else | |
1547 | if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ | |
1548 | gr->magic_not_rop_nr = 0x05; | |
1549 | } else | |
1550 | if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ | |
1551 | gr->magic_not_rop_nr = 0x06; | |
1552 | } | |
1553 | break; | |
1554 | case 0xc3: /* 450, 4/0/0/0, 2 */ | |
1555 | gr->magic_not_rop_nr = 0x03; | |
1556 | break; | |
1557 | case 0xc4: /* 460, 3/4/0/0, 4 */ | |
1558 | gr->magic_not_rop_nr = 0x01; | |
1559 | break; | |
1560 | case 0xc1: /* 2/0/0/0, 1 */ | |
1561 | gr->magic_not_rop_nr = 0x01; | |
1562 | break; | |
1563 | case 0xc8: /* 4/4/3/4, 5 */ | |
1564 | gr->magic_not_rop_nr = 0x06; | |
1565 | break; | |
1566 | case 0xce: /* 4/4/0/0, 4 */ | |
1567 | gr->magic_not_rop_nr = 0x03; | |
1568 | break; | |
1569 | case 0xcf: /* 4/0/0/0, 3 */ | |
1570 | gr->magic_not_rop_nr = 0x03; | |
1571 | break; | |
1572 | case 0xd7: | |
1573 | case 0xd9: /* 1/0/0/0, 1 */ | |
1574 | case 0xea: /* gk20a */ | |
1575 | case 0x12b: /* gm20b */ | |
1576 | gr->magic_not_rop_nr = 0x01; | |
1577 | break; | |
1578 | } | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
1583 | int | |
1584 | gf100_gr_init_(struct nvkm_gr *base) | |
1585 | { | |
1586 | struct gf100_gr *gr = gf100_gr(base); | |
1587 | nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); | |
1588 | return gr->func->init(gr); | |
1589 | } | |
1590 | ||
1591 | void | |
1592 | gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) | |
1593 | { | |
1594 | kfree(fuc->data); | |
1595 | fuc->data = NULL; | |
1596 | } | |
1597 | ||
1598 | void * | |
1599 | gf100_gr_dtor(struct nvkm_gr *base) | |
1600 | { | |
1601 | struct gf100_gr *gr = gf100_gr(base); | |
1602 | ||
1603 | if (gr->func->dtor) | |
1604 | gr->func->dtor(gr); | |
1605 | kfree(gr->data); | |
1606 | ||
1607 | gf100_gr_dtor_fw(&gr->fuc409c); | |
1608 | gf100_gr_dtor_fw(&gr->fuc409d); | |
1609 | gf100_gr_dtor_fw(&gr->fuc41ac); | |
1610 | gf100_gr_dtor_fw(&gr->fuc41ad); | |
1611 | ||
1612 | nvkm_memory_del(&gr->unk4188b8); | |
1613 | nvkm_memory_del(&gr->unk4188b4); | |
1614 | return gr; | |
1615 | } | |
1616 | ||
1617 | static const struct nvkm_gr_func | |
1618 | gf100_gr_ = { | |
1619 | .dtor = gf100_gr_dtor, | |
1620 | .oneinit = gf100_gr_oneinit, | |
1621 | .init = gf100_gr_init_, | |
1622 | .intr = gf100_gr_intr, | |
1623 | .units = gf100_gr_units, | |
1624 | .chan_new = gf100_gr_chan_new, | |
1625 | .object_get = gf100_gr_object_get, | |
1626 | }; | |
1627 | ||
1628 | int | |
1629 | gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, | |
1630 | struct gf100_gr_fuc *fuc) | |
1631 | { | |
1632 | struct nvkm_subdev *subdev = &gr->base.engine.subdev; | |
1633 | struct nvkm_device *device = subdev->device; | |
1634 | const struct firmware *fw; | |
1635 | char f[64]; | |
1636 | char cname[16]; | |
1637 | int ret; | |
1638 | int i; | |
1639 | ||
1640 | /* Convert device name to lowercase */ | |
1641 | strncpy(cname, device->chip->name, sizeof(cname)); | |
1642 | cname[sizeof(cname) - 1] = '\0'; | |
1643 | i = strlen(cname); | |
1644 | while (i) { | |
1645 | --i; | |
1646 | cname[i] = tolower(cname[i]); | |
1647 | } | |
1648 | ||
1649 | snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); | |
26c9e8ef | 1650 | ret = request_firmware(&fw, f, device->dev); |
c85ee6ca BS |
1651 | if (ret) { |
1652 | nvkm_error(subdev, "failed to load %s\n", fwname); | |
1653 | return ret; | |
1654 | } | |
1655 | ||
1656 | fuc->size = fw->size; | |
1657 | fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); | |
1658 | release_firmware(fw); | |
1659 | return (fuc->data != NULL) ? 0 : -ENOMEM; | |
1660 | } | |
1661 | ||
1662 | int | |
1663 | gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, | |
1664 | int index, struct gf100_gr *gr) | |
1665 | { | |
1666 | int ret; | |
1667 | ||
1668 | gr->func = func; | |
1669 | gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", | |
1670 | func->fecs.ucode == NULL); | |
1671 | ||
1672 | ret = nvkm_gr_ctor(&gf100_gr_, device, index, 0x08001000, | |
1673 | gr->firmware || func->fecs.ucode != NULL, | |
1674 | &gr->base); | |
1675 | if (ret) | |
1676 | return ret; | |
1677 | ||
1678 | if (gr->firmware) { | |
1679 | nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); | |
1680 | if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || | |
1681 | gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || | |
1682 | gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || | |
1683 | gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) | |
1684 | return -ENODEV; | |
1685 | } | |
1686 | ||
1687 | return 0; | |
1688 | } | |
1689 | ||
30f4e087 | 1690 | int |
c85ee6ca BS |
1691 | gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, |
1692 | int index, struct nvkm_gr **pgr) | |
1693 | { | |
1694 | struct gf100_gr *gr; | |
1695 | if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) | |
1696 | return -ENOMEM; | |
1697 | *pgr = &gr->base; | |
1698 | return gf100_gr_ctor(func, device, index, gr); | |
1699 | } | |
1700 | ||
1701 | int | |
1702 | gf100_gr_init(struct gf100_gr *gr) | |
4b223eef | 1703 | { |
276836d4 | 1704 | struct nvkm_device *device = gr->base.engine.subdev.device; |
bfee3f3d | 1705 | const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); |
30f4e087 BS |
1706 | u32 data[TPC_MAX / 8] = {}; |
1707 | u8 tpcnr[GPC_MAX]; | |
1708 | int gpc, tpc, rop; | |
c85ee6ca | 1709 | int i; |
ebb945a9 | 1710 | |
276836d4 BS |
1711 | nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); |
1712 | nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); | |
1713 | nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); | |
1714 | nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); | |
1715 | nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); | |
1716 | nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); | |
227c95d9 BS |
1717 | nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); |
1718 | nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); | |
30f4e087 | 1719 | |
c85ee6ca | 1720 | gf100_gr_mmio(gr, gr->func->mmio); |
30f4e087 | 1721 | |
bfee3f3d BS |
1722 | memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); |
1723 | for (i = 0, gpc = -1; i < gr->tpc_total; i++) { | |
30f4e087 | 1724 | do { |
bfee3f3d | 1725 | gpc = (gpc + 1) % gr->gpc_nr; |
30f4e087 | 1726 | } while (!tpcnr[gpc]); |
bfee3f3d | 1727 | tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; |
30f4e087 BS |
1728 | |
1729 | data[i / 8] |= tpc << ((i % 8) * 4); | |
1730 | } | |
1731 | ||
276836d4 BS |
1732 | nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); |
1733 | nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); | |
1734 | nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); | |
1735 | nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); | |
30f4e087 | 1736 | |
bfee3f3d | 1737 | for (gpc = 0; gpc < gr->gpc_nr; gpc++) { |
276836d4 | 1738 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), |
bfee3f3d | 1739 | gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); |
276836d4 | 1740 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | |
bfee3f3d | 1741 | gr->tpc_total); |
276836d4 | 1742 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); |
30f4e087 BS |
1743 | } |
1744 | ||
c85ee6ca | 1745 | if (device->chipset != 0xd7) |
276836d4 | 1746 | nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); |
26410c67 | 1747 | else |
276836d4 | 1748 | nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); |
bfee3f3d | 1749 | |
276836d4 | 1750 | nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); |
bfee3f3d | 1751 | |
276836d4 | 1752 | nvkm_wr32(device, 0x400500, 0x00010001); |
bfee3f3d | 1753 | |
276836d4 BS |
1754 | nvkm_wr32(device, 0x400100, 0xffffffff); |
1755 | nvkm_wr32(device, 0x40013c, 0xffffffff); | |
bfee3f3d | 1756 | |
276836d4 BS |
1757 | nvkm_wr32(device, 0x409c24, 0x000f0000); |
1758 | nvkm_wr32(device, 0x404000, 0xc0000000); | |
1759 | nvkm_wr32(device, 0x404600, 0xc0000000); | |
1760 | nvkm_wr32(device, 0x408030, 0xc0000000); | |
1761 | nvkm_wr32(device, 0x40601c, 0xc0000000); | |
1762 | nvkm_wr32(device, 0x404490, 0xc0000000); | |
1763 | nvkm_wr32(device, 0x406018, 0xc0000000); | |
1764 | nvkm_wr32(device, 0x405840, 0xc0000000); | |
1765 | nvkm_wr32(device, 0x405844, 0x00ffffff); | |
1766 | nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); | |
1767 | nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); | |
bfee3f3d BS |
1768 | |
1769 | for (gpc = 0; gpc < gr->gpc_nr; gpc++) { | |
276836d4 BS |
1770 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); |
1771 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); | |
1772 | nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); | |
1773 | nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); | |
bfee3f3d | 1774 | for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { |
276836d4 BS |
1775 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); |
1776 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); | |
1777 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); | |
1778 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); | |
1779 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); | |
1780 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); | |
1781 | nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); | |
30f4e087 | 1782 | } |
276836d4 BS |
1783 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); |
1784 | nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); | |
30f4e087 BS |
1785 | } |
1786 | ||
bfee3f3d | 1787 | for (rop = 0; rop < gr->rop_nr; rop++) { |
276836d4 BS |
1788 | nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); |
1789 | nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); | |
1790 | nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); | |
1791 | nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); | |
30f4e087 | 1792 | } |
ebb945a9 | 1793 | |
276836d4 BS |
1794 | nvkm_wr32(device, 0x400108, 0xffffffff); |
1795 | nvkm_wr32(device, 0x400138, 0xffffffff); | |
1796 | nvkm_wr32(device, 0x400118, 0xffffffff); | |
1797 | nvkm_wr32(device, 0x400130, 0xffffffff); | |
1798 | nvkm_wr32(device, 0x40011c, 0xffffffff); | |
1799 | nvkm_wr32(device, 0x400134, 0xffffffff); | |
30f4e087 | 1800 | |
276836d4 | 1801 | nvkm_wr32(device, 0x400054, 0x34ce3464); |
ac9738bb | 1802 | |
bfee3f3d | 1803 | gf100_gr_zbc_init(gr); |
ac9738bb | 1804 | |
bfee3f3d | 1805 | return gf100_gr_init_ctxctl(gr); |
30f4e087 BS |
1806 | } |
1807 | ||
e3c71eb2 | 1808 | #include "fuc/hubgf100.fuc3.h" |
30f4e087 | 1809 | |
e3c71eb2 BS |
1810 | struct gf100_gr_ucode |
1811 | gf100_gr_fecs_ucode = { | |
1812 | .code.data = gf100_grhub_code, | |
1813 | .code.size = sizeof(gf100_grhub_code), | |
1814 | .data.data = gf100_grhub_data, | |
1815 | .data.size = sizeof(gf100_grhub_data), | |
30f4e087 BS |
1816 | }; |
1817 | ||
e3c71eb2 | 1818 | #include "fuc/gpcgf100.fuc3.h" |
30f4e087 | 1819 | |
e3c71eb2 BS |
1820 | struct gf100_gr_ucode |
1821 | gf100_gr_gpccs_ucode = { | |
1822 | .code.data = gf100_grgpc_code, | |
1823 | .code.size = sizeof(gf100_grgpc_code), | |
1824 | .data.data = gf100_grgpc_data, | |
1825 | .data.size = sizeof(gf100_grgpc_data), | |
30f4e087 BS |
1826 | }; |
1827 | ||
27f3d6cf BS |
1828 | static const struct gf100_gr_func |
1829 | gf100_gr = { | |
c85ee6ca BS |
1830 | .init = gf100_gr_init, |
1831 | .mmio = gf100_gr_pack_mmio, | |
1832 | .fecs.ucode = &gf100_gr_fecs_ucode, | |
1833 | .gpccs.ucode = &gf100_gr_gpccs_ucode, | |
27f3d6cf BS |
1834 | .grctx = &gf100_grctx, |
1835 | .sclass = { | |
1836 | { -1, -1, FERMI_TWOD_A }, | |
1837 | { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, | |
1838 | { -1, -1, FERMI_A, &gf100_fermi }, | |
1839 | { -1, -1, FERMI_COMPUTE_A }, | |
1840 | {} | |
1841 | } | |
1842 | }; | |
1843 | ||
c85ee6ca BS |
1844 | int |
1845 | gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) | |
1846 | { | |
1847 | return gf100_gr_new_(&gf100_gr, device, index, pgr); | |
1848 | } |