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Merge tag 'drm-intel-next-2016-02-14' of git://anongit.freedesktop.org/drm-intel...
[deliverable/linux.git] / drivers / gpu / drm / panel / panel-simple.c
CommitLineData
280921de
TR		 1/*
2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/backlight.h>
cfdf0549 25#include <linux/gpio/consumer.h>
280921de 26#include <linux/module.h>
280921de
TR		 27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/regulator/consumer.h>
30
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
210fcd9d 33#include <drm/drm_mipi_dsi.h>
280921de
TR		 34#include <drm/drm_panel.h>
35
a5d3e625
PZ		 36#include <video/display_timing.h>
37#include <video/videomode.h>
38
280921de
TR		 39struct panel_desc {
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
a5d3e625
PZ		 42 const struct display_timing *timings;
43 unsigned int num_timings;
280921de 44
0208d511
SM		 45 unsigned int bpc;
46
85533e3b
UÖ		 47 /**
48 * @width: width (in millimeters) of the panel's active display area
49 * @height: height (in millimeters) of the panel's active display area
50 */
280921de
TR		 51 struct {
52 unsigned int width;
53 unsigned int height;
54 } size;
f673c37e
AK		 55
56 /**
57 * @prepare: the time (in milliseconds) that it takes for the panel to
58 * become ready and start receiving video data
59 * @enable: the time (in milliseconds) that it takes for the panel to
60 * display the first valid frame after starting to receive
61 * video data
62 * @disable: the time (in milliseconds) that it takes for the panel to
63 * turn the display off (no content is visible)
64 * @unprepare: the time (in milliseconds) that it takes for the panel
65 * to power itself down completely
66 */
67 struct {
68 unsigned int prepare;
69 unsigned int enable;
70 unsigned int disable;
71 unsigned int unprepare;
72 } delay;
795f7ab3
BB		 73
74 u32 bus_format;
280921de
TR		 75};
76
280921de
TR		 77struct panel_simple {
78 struct drm_panel base;
613a633e 79 bool prepared;
280921de
TR		 80 bool enabled;
81
82 const struct panel_desc *desc;
83
84 struct backlight_device *backlight;
85 struct regulator *supply;
86 struct i2c_adapter *ddc;
87
cfdf0549 88 struct gpio_desc *enable_gpio;
280921de
TR		 89};
90
91static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
92{
93 return container_of(panel, struct panel_simple, base);
94}
95
96static int panel_simple_get_fixed_modes(struct panel_simple *panel)
97{
98 struct drm_connector *connector = panel->base.connector;
99 struct drm_device *drm = panel->base.drm;
100 struct drm_display_mode *mode;
101 unsigned int i, num = 0;
102
103 if (!panel->desc)
104 return 0;
105
a5d3e625
PZ		 106 for (i = 0; i < panel->desc->num_timings; i++) {
107 const struct display_timing *dt = &panel->desc->timings[i];
108 struct videomode vm;
109
110 videomode_from_timing(dt, &vm);
111 mode = drm_mode_create(drm);
112 if (!mode) {
113 dev_err(drm->dev, "failed to add mode %ux%u\n",
114 dt->hactive.typ, dt->vactive.typ);
115 continue;
116 }
117
118 drm_display_mode_from_videomode(&vm, mode);
119 drm_mode_set_name(mode);
120
121 drm_mode_probed_add(connector, mode);
122 num++;
123 }
124
280921de
TR		 125 for (i = 0; i < panel->desc->num_modes; i++) {
126 const struct drm_display_mode *m = &panel->desc->modes[i];
127
128 mode = drm_mode_duplicate(drm, m);
129 if (!mode) {
130 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
131 m->hdisplay, m->vdisplay, m->vrefresh);
132 continue;
133 }
134
135 drm_mode_set_name(mode);
136
137 drm_mode_probed_add(connector, mode);
138 num++;
139 }
140
0208d511 141 connector->display_info.bpc = panel->desc->bpc;
280921de
TR		 142 connector->display_info.width_mm = panel->desc->size.width;
143 connector->display_info.height_mm = panel->desc->size.height;
795f7ab3
BB		 144 if (panel->desc->bus_format)
145 drm_display_info_set_bus_formats(&connector->display_info,
146 &panel->desc->bus_format, 1);
280921de
TR		 147
148 return num;
149}
150
151static int panel_simple_disable(struct drm_panel *panel)
152{
153 struct panel_simple *p = to_panel_simple(panel);
154
155 if (!p->enabled)
156 return 0;
157
158 if (p->backlight) {
159 p->backlight->props.power = FB_BLANK_POWERDOWN;
160 backlight_update_status(p->backlight);
161 }
162
f673c37e
AK		 163 if (p->desc->delay.disable)
164 msleep(p->desc->delay.disable);
165
280921de
TR		 166 p->enabled = false;
167
168 return 0;
169}
170
c0e1d170
AK		 171static int panel_simple_unprepare(struct drm_panel *panel)
172{
613a633e
AK		 173 struct panel_simple *p = to_panel_simple(panel);
174
175 if (!p->prepared)
176 return 0;
177
178 if (p->enable_gpio)
179 gpiod_set_value_cansleep(p->enable_gpio, 0);
180
181 regulator_disable(p->supply);
182
f673c37e
AK		 183 if (p->desc->delay.unprepare)
184 msleep(p->desc->delay.unprepare);
185
613a633e 186 p->prepared = false;
c0e1d170 187
c0e1d170
AK		 188 return 0;
189}
190
613a633e 191static int panel_simple_prepare(struct drm_panel *panel)
280921de
TR		 192{
193 struct panel_simple *p = to_panel_simple(panel);
194 int err;
195
613a633e 196 if (p->prepared)
280921de
TR		 197 return 0;
198
199 err = regulator_enable(p->supply);
200 if (err < 0) {
201 dev_err(panel->dev, "failed to enable supply: %d\n", err);
202 return err;
203 }
204
cfdf0549 205 if (p->enable_gpio)
15c1a919 206 gpiod_set_value_cansleep(p->enable_gpio, 1);
280921de 207
f673c37e
AK		 208 if (p->desc->delay.prepare)
209 msleep(p->desc->delay.prepare);
210
613a633e
AK		 211 p->prepared = true;
212
213 return 0;
214}
215
216static int panel_simple_enable(struct drm_panel *panel)
217{
218 struct panel_simple *p = to_panel_simple(panel);
219
220 if (p->enabled)
221 return 0;
222
f673c37e
AK		 223 if (p->desc->delay.enable)
224 msleep(p->desc->delay.enable);
225
280921de
TR		 226 if (p->backlight) {
227 p->backlight->props.power = FB_BLANK_UNBLANK;
228 backlight_update_status(p->backlight);
229 }
230
231 p->enabled = true;
232
233 return 0;
234}
235
236static int panel_simple_get_modes(struct drm_panel *panel)
237{
238 struct panel_simple *p = to_panel_simple(panel);
239 int num = 0;
240
241 /* probe EDID if a DDC bus is available */
242 if (p->ddc) {
243 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
70bf6878 244 drm_mode_connector_update_edid_property(panel->connector, edid);
280921de
TR		 245 if (edid) {
246 num += drm_add_edid_modes(panel->connector, edid);
247 kfree(edid);
248 }
249 }
250
251 /* add hard-coded panel modes */
252 num += panel_simple_get_fixed_modes(p);
253
254 return num;
255}
256
a5d3e625
PZ		 257static int panel_simple_get_timings(struct drm_panel *panel,
258 unsigned int num_timings,
259 struct display_timing *timings)
260{
261 struct panel_simple *p = to_panel_simple(panel);
262 unsigned int i;
263
264 if (p->desc->num_timings < num_timings)
265 num_timings = p->desc->num_timings;
266
267 if (timings)
268 for (i = 0; i < num_timings; i++)
269 timings[i] = p->desc->timings[i];
270
271 return p->desc->num_timings;
272}
273
280921de
TR		 274static const struct drm_panel_funcs panel_simple_funcs = {
275 .disable = panel_simple_disable,
c0e1d170
AK		 276 .unprepare = panel_simple_unprepare,
277 .prepare = panel_simple_prepare,
280921de
TR		 278 .enable = panel_simple_enable,
279 .get_modes = panel_simple_get_modes,
a5d3e625 280 .get_timings = panel_simple_get_timings,
280921de
TR		 281};
282
283static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
284{
285 struct device_node *backlight, *ddc;
286 struct panel_simple *panel;
280921de
TR		 287 int err;
288
289 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
290 if (!panel)
291 return -ENOMEM;
292
293 panel->enabled = false;
613a633e 294 panel->prepared = false;
280921de
TR		 295 panel->desc = desc;
296
297 panel->supply = devm_regulator_get(dev, "power");
298 if (IS_ERR(panel->supply))
299 return PTR_ERR(panel->supply);
300
a61400d8
AC		 301 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
302 GPIOD_OUT_LOW);
cfdf0549
AC		 303 if (IS_ERR(panel->enable_gpio)) {
304 err = PTR_ERR(panel->enable_gpio);
9746c619
AC		 305 dev_err(dev, "failed to request GPIO: %d\n", err);
306 return err;
307 }
280921de 308
280921de
TR		 309 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
310 if (backlight) {
311 panel->backlight = of_find_backlight_by_node(backlight);
312 of_node_put(backlight);
313
cfdf0549
AC		 314 if (!panel->backlight)
315 return -EPROBE_DEFER;
280921de
TR		 316 }
317
318 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
319 if (ddc) {
320 panel->ddc = of_find_i2c_adapter_by_node(ddc);
321 of_node_put(ddc);
322
323 if (!panel->ddc) {
324 err = -EPROBE_DEFER;
325 goto free_backlight;
326 }
327 }
328
329 drm_panel_init(&panel->base);
330 panel->base.dev = dev;
331 panel->base.funcs = &panel_simple_funcs;
332
333 err = drm_panel_add(&panel->base);
334 if (err < 0)
335 goto free_ddc;
336
337 dev_set_drvdata(dev, panel);
338
339 return 0;
340
341free_ddc:
342 if (panel->ddc)
343 put_device(&panel->ddc->dev);
344free_backlight:
345 if (panel->backlight)
346 put_device(&panel->backlight->dev);
280921de
TR		 347
348 return err;
349}
350
351static int panel_simple_remove(struct device *dev)
352{
353 struct panel_simple *panel = dev_get_drvdata(dev);
354
355 drm_panel_detach(&panel->base);
356 drm_panel_remove(&panel->base);
357
358 panel_simple_disable(&panel->base);
359
360 if (panel->ddc)
361 put_device(&panel->ddc->dev);
362
363 if (panel->backlight)
364 put_device(&panel->backlight->dev);
365
280921de
TR		 366 return 0;
367}
368
d02fd93e
TR		 369static void panel_simple_shutdown(struct device *dev)
370{
371 struct panel_simple *panel = dev_get_drvdata(dev);
372
373 panel_simple_disable(&panel->base);
374}
375
1c550fa1
PZ		 376static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
377 .clock = 33333,
378 .hdisplay = 800,
379 .hsync_start = 800 + 0,
380 .hsync_end = 800 + 0 + 255,
381 .htotal = 800 + 0 + 255 + 0,
382 .vdisplay = 480,
383 .vsync_start = 480 + 2,
384 .vsync_end = 480 + 2 + 45,
385 .vtotal = 480 + 2 + 45 + 0,
386 .vrefresh = 60,
387 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
388};
389
390static const struct panel_desc ampire_am800480r3tmqwa1h = {
391 .modes = &ampire_am800480r3tmqwa1h_mode,
392 .num_modes = 1,
393 .bpc = 6,
394 .size = {
395 .width = 152,
396 .height = 91,
397 },
398 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
399};
400
280921de
TR		 401static const struct drm_display_mode auo_b101aw03_mode = {
402 .clock = 51450,
403 .hdisplay = 1024,
404 .hsync_start = 1024 + 156,
405 .hsync_end = 1024 + 156 + 8,
406 .htotal = 1024 + 156 + 8 + 156,
407 .vdisplay = 600,
408 .vsync_start = 600 + 16,
409 .vsync_end = 600 + 16 + 6,
410 .vtotal = 600 + 16 + 6 + 16,
411 .vrefresh = 60,
412};
413
414static const struct panel_desc auo_b101aw03 = {
415 .modes = &auo_b101aw03_mode,
416 .num_modes = 1,
0208d511 417 .bpc = 6,
280921de
TR		 418 .size = {
419 .width = 223,
420 .height = 125,
421 },
422};
423
a531bc3d
HL		 424static const struct drm_display_mode auo_b101ean01_mode = {
425 .clock = 72500,
426 .hdisplay = 1280,
427 .hsync_start = 1280 + 119,
428 .hsync_end = 1280 + 119 + 32,
429 .htotal = 1280 + 119 + 32 + 21,
430 .vdisplay = 800,
431 .vsync_start = 800 + 4,
432 .vsync_end = 800 + 4 + 20,
433 .vtotal = 800 + 4 + 20 + 8,
434 .vrefresh = 60,
435};
436
437static const struct panel_desc auo_b101ean01 = {
438 .modes = &auo_b101ean01_mode,
439 .num_modes = 1,
440 .bpc = 6,
441 .size = {
442 .width = 217,
443 .height = 136,
444 },
445};
446
dac746e0
RC		 447static const struct drm_display_mode auo_b101xtn01_mode = {
448 .clock = 72000,
449 .hdisplay = 1366,
450 .hsync_start = 1366 + 20,
451 .hsync_end = 1366 + 20 + 70,
452 .htotal = 1366 + 20 + 70,
453 .vdisplay = 768,
454 .vsync_start = 768 + 14,
455 .vsync_end = 768 + 14 + 42,
456 .vtotal = 768 + 14 + 42,
457 .vrefresh = 60,
458 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
459};
460
461static const struct panel_desc auo_b101xtn01 = {
462 .modes = &auo_b101xtn01_mode,
463 .num_modes = 1,
464 .bpc = 6,
465 .size = {
466 .width = 223,
467 .height = 125,
468 },
469};
470
e35e305e
AK		 471static const struct drm_display_mode auo_b116xw03_mode = {
472 .clock = 70589,
473 .hdisplay = 1366,
474 .hsync_start = 1366 + 40,
475 .hsync_end = 1366 + 40 + 40,
476 .htotal = 1366 + 40 + 40 + 32,
477 .vdisplay = 768,
478 .vsync_start = 768 + 10,
479 .vsync_end = 768 + 10 + 12,
480 .vtotal = 768 + 10 + 12 + 6,
481 .vrefresh = 60,
482};
483
484static const struct panel_desc auo_b116xw03 = {
485 .modes = &auo_b116xw03_mode,
486 .num_modes = 1,
487 .bpc = 6,
488 .size = {
489 .width = 256,
490 .height = 144,
491 },
492};
493
a333f7ad
SM		 494static const struct drm_display_mode auo_b133xtn01_mode = {
495 .clock = 69500,
496 .hdisplay = 1366,
497 .hsync_start = 1366 + 48,
498 .hsync_end = 1366 + 48 + 32,
499 .htotal = 1366 + 48 + 32 + 20,
500 .vdisplay = 768,
501 .vsync_start = 768 + 3,
502 .vsync_end = 768 + 3 + 6,
503 .vtotal = 768 + 3 + 6 + 13,
504 .vrefresh = 60,
505};
506
507static const struct panel_desc auo_b133xtn01 = {
508 .modes = &auo_b133xtn01_mode,
509 .num_modes = 1,
0208d511 510 .bpc = 6,
a333f7ad
SM		 511 .size = {
512 .width = 293,
513 .height = 165,
514 },
515};
516
3e51d609
AK		 517static const struct drm_display_mode auo_b133htn01_mode = {
518 .clock = 150660,
519 .hdisplay = 1920,
520 .hsync_start = 1920 + 172,
521 .hsync_end = 1920 + 172 + 80,
522 .htotal = 1920 + 172 + 80 + 60,
523 .vdisplay = 1080,
524 .vsync_start = 1080 + 25,
525 .vsync_end = 1080 + 25 + 10,
526 .vtotal = 1080 + 25 + 10 + 10,
527 .vrefresh = 60,
528};
529
530static const struct panel_desc auo_b133htn01 = {
531 .modes = &auo_b133htn01_mode,
532 .num_modes = 1,
d7a839cd 533 .bpc = 6,
3e51d609
AK		 534 .size = {
535 .width = 293,
536 .height = 165,
537 },
538 .delay = {
539 .prepare = 105,
540 .enable = 20,
541 .unprepare = 50,
542 },
543};
544
d47df633
PZ		 545static const struct drm_display_mode avic_tm070ddh03_mode = {
546 .clock = 51200,
547 .hdisplay = 1024,
548 .hsync_start = 1024 + 160,
549 .hsync_end = 1024 + 160 + 4,
550 .htotal = 1024 + 160 + 4 + 156,
551 .vdisplay = 600,
552 .vsync_start = 600 + 17,
553 .vsync_end = 600 + 17 + 1,
554 .vtotal = 600 + 17 + 1 + 17,
555 .vrefresh = 60,
556};
557
558static const struct panel_desc avic_tm070ddh03 = {
559 .modes = &avic_tm070ddh03_mode,
560 .num_modes = 1,
561 .bpc = 8,
562 .size = {
563 .width = 154,
564 .height = 90,
565 },
566 .delay = {
567 .prepare = 20,
568 .enable = 200,
569 .disable = 200,
570 },
571};
572
4c930757
SW		 573static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
574 .clock = 72070,
575 .hdisplay = 1366,
576 .hsync_start = 1366 + 58,
577 .hsync_end = 1366 + 58 + 58,
578 .htotal = 1366 + 58 + 58 + 58,
579 .vdisplay = 768,
580 .vsync_start = 768 + 4,
581 .vsync_end = 768 + 4 + 4,
582 .vtotal = 768 + 4 + 4 + 4,
583 .vrefresh = 60,
584};
585
586static const struct panel_desc chunghwa_claa101wa01a = {
587 .modes = &chunghwa_claa101wa01a_mode,
588 .num_modes = 1,
0208d511 589 .bpc = 6,
4c930757
SW		 590 .size = {
591 .width = 220,
592 .height = 120,
593 },
594};
595
280921de
TR		 596static const struct drm_display_mode chunghwa_claa101wb01_mode = {
597 .clock = 69300,
598 .hdisplay = 1366,
599 .hsync_start = 1366 + 48,
600 .hsync_end = 1366 + 48 + 32,
601 .htotal = 1366 + 48 + 32 + 20,
602 .vdisplay = 768,
603 .vsync_start = 768 + 16,
604 .vsync_end = 768 + 16 + 8,
605 .vtotal = 768 + 16 + 8 + 16,
606 .vrefresh = 60,
607};
608
609static const struct panel_desc chunghwa_claa101wb01 = {
610 .modes = &chunghwa_claa101wb01_mode,
611 .num_modes = 1,
0208d511 612 .bpc = 6,
280921de
TR		 613 .size = {
614 .width = 223,
615 .height = 125,
616 },
617};
618
26ab0065
SA		 619static const struct drm_display_mode edt_et057090dhu_mode = {
620 .clock = 25175,
621 .hdisplay = 640,
622 .hsync_start = 640 + 16,
623 .hsync_end = 640 + 16 + 30,
624 .htotal = 640 + 16 + 30 + 114,
625 .vdisplay = 480,
626 .vsync_start = 480 + 10,
627 .vsync_end = 480 + 10 + 3,
628 .vtotal = 480 + 10 + 3 + 32,
629 .vrefresh = 60,
630 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
631};
632
633static const struct panel_desc edt_et057090dhu = {
634 .modes = &edt_et057090dhu_mode,
635 .num_modes = 1,
0208d511 636 .bpc = 6,
26ab0065
SA		 637 .size = {
638 .width = 115,
639 .height = 86,
640 },
641};
642
fff5de45
PZ		 643static const struct drm_display_mode edt_etm0700g0dh6_mode = {
644 .clock = 33260,
645 .hdisplay = 800,
646 .hsync_start = 800 + 40,
647 .hsync_end = 800 + 40 + 128,
648 .htotal = 800 + 40 + 128 + 88,
649 .vdisplay = 480,
650 .vsync_start = 480 + 10,
651 .vsync_end = 480 + 10 + 2,
652 .vtotal = 480 + 10 + 2 + 33,
653 .vrefresh = 60,
654 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
655};
656
657static const struct panel_desc edt_etm0700g0dh6 = {
658 .modes = &edt_etm0700g0dh6_mode,
659 .num_modes = 1,
0208d511 660 .bpc = 6,
fff5de45
PZ		 661 .size = {
662 .width = 152,
663 .height = 91,
664 },
665};
666
102932b0
BB		 667static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
668 .clock = 32260,
669 .hdisplay = 800,
670 .hsync_start = 800 + 168,
671 .hsync_end = 800 + 168 + 64,
672 .htotal = 800 + 168 + 64 + 88,
673 .vdisplay = 480,
674 .vsync_start = 480 + 37,
675 .vsync_end = 480 + 37 + 2,
676 .vtotal = 480 + 37 + 2 + 8,
677 .vrefresh = 60,
678};
679
680static const struct panel_desc foxlink_fl500wvr00_a0t = {
681 .modes = &foxlink_fl500wvr00_a0t_mode,
682 .num_modes = 1,
d7a839cd 683 .bpc = 8,
102932b0
BB		 684 .size = {
685 .width = 108,
686 .height = 65,
687 },
bb276cb3 688 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
102932b0
BB		 689};
690
d435a2af
PZ		 691static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
692 .clock = 9000,
693 .hdisplay = 480,
694 .hsync_start = 480 + 5,
695 .hsync_end = 480 + 5 + 1,
696 .htotal = 480 + 5 + 1 + 40,
697 .vdisplay = 272,
698 .vsync_start = 272 + 8,
699 .vsync_end = 272 + 8 + 1,
700 .vtotal = 272 + 8 + 1 + 8,
701 .vrefresh = 60,
702};
703
704static const struct panel_desc giantplus_gpg482739qs5 = {
705 .modes = &giantplus_gpg482739qs5_mode,
706 .num_modes = 1,
707 .bpc = 8,
708 .size = {
709 .width = 95,
710 .height = 54,
711 },
33536a09 712 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
d435a2af
PZ		 713};
714
ab07725a
PZ		 715static const struct display_timing hannstar_hsd070pww1_timing = {
716 .pixelclock = { 64300000, 71100000, 82000000 },
717 .hactive = { 1280, 1280, 1280 },
718 .hfront_porch = { 1, 1, 10 },
719 .hback_porch = { 1, 1, 10 },
d901d2ba
PZ		 720 /*
721 * According to the data sheet, the minimum horizontal blanking interval
722 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
723 * minimum working horizontal blanking interval to be 60 clocks.
724 */
725 .hsync_len = { 58, 158, 661 },
ab07725a
PZ		 726 .vactive = { 800, 800, 800 },
727 .vfront_porch = { 1, 1, 10 },
728 .vback_porch = { 1, 1, 10 },
729 .vsync_len = { 1, 21, 203 },
730 .flags = DISPLAY_FLAGS_DE_HIGH,
a853205e
PZ		 731};
732
733static const struct panel_desc hannstar_hsd070pww1 = {
ab07725a
PZ		 734 .timings = &hannstar_hsd070pww1_timing,
735 .num_timings = 1,
a853205e
PZ		 736 .bpc = 6,
737 .size = {
738 .width = 151,
739 .height = 94,
740 },
58d6a7bc 741 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
a853205e
PZ		 742};
743
c0d607e5
EN		 744static const struct display_timing hannstar_hsd100pxn1_timing = {
745 .pixelclock = { 55000000, 65000000, 75000000 },
746 .hactive = { 1024, 1024, 1024 },
747 .hfront_porch = { 40, 40, 40 },
748 .hback_porch = { 220, 220, 220 },
749 .hsync_len = { 20, 60, 100 },
750 .vactive = { 768, 768, 768 },
751 .vfront_porch = { 7, 7, 7 },
752 .vback_porch = { 21, 21, 21 },
753 .vsync_len = { 10, 10, 10 },
754 .flags = DISPLAY_FLAGS_DE_HIGH,
755};
756
757static const struct panel_desc hannstar_hsd100pxn1 = {
758 .timings = &hannstar_hsd100pxn1_timing,
759 .num_timings = 1,
760 .bpc = 6,
761 .size = {
762 .width = 203,
763 .height = 152,
764 },
4946b043 765 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
c0d607e5
EN		 766};
767
61ac0bf8
LS		 768static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
769 .clock = 33333,
770 .hdisplay = 800,
771 .hsync_start = 800 + 85,
772 .hsync_end = 800 + 85 + 86,
773 .htotal = 800 + 85 + 86 + 85,
774 .vdisplay = 480,
775 .vsync_start = 480 + 16,
776 .vsync_end = 480 + 16 + 13,
777 .vtotal = 480 + 16 + 13 + 16,
778 .vrefresh = 60,
779};
780
781static const struct panel_desc hitachi_tx23d38vm0caa = {
782 .modes = &hitachi_tx23d38vm0caa_mode,
783 .num_modes = 1,
784 .bpc = 6,
785 .size = {
786 .width = 195,
787 .height = 117,
788 },
789};
790
41bcceb4
NF		 791static const struct drm_display_mode innolux_at043tn24_mode = {
792 .clock = 9000,
793 .hdisplay = 480,
794 .hsync_start = 480 + 2,
795 .hsync_end = 480 + 2 + 41,
796 .htotal = 480 + 2 + 41 + 2,
797 .vdisplay = 272,
798 .vsync_start = 272 + 2,
799 .vsync_end = 272 + 2 + 11,
800 .vtotal = 272 + 2 + 11 + 2,
801 .vrefresh = 60,
802 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
803};
804
805static const struct panel_desc innolux_at043tn24 = {
806 .modes = &innolux_at043tn24_mode,
807 .num_modes = 1,
808 .bpc = 8,
809 .size = {
810 .width = 95,
811 .height = 54,
812 },
813 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
814};
815
d731f661 816static const struct drm_display_mode innolux_g121i1_l01_mode = {
0a2288c0 817 .clock = 71000,
d731f661
LS		 818 .hdisplay = 1280,
819 .hsync_start = 1280 + 64,
820 .hsync_end = 1280 + 64 + 32,
821 .htotal = 1280 + 64 + 32 + 64,
822 .vdisplay = 800,
823 .vsync_start = 800 + 9,
824 .vsync_end = 800 + 9 + 6,
825 .vtotal = 800 + 9 + 6 + 9,
826 .vrefresh = 60,
827};
828
829static const struct panel_desc innolux_g121i1_l01 = {
830 .modes = &innolux_g121i1_l01_mode,
831 .num_modes = 1,
832 .bpc = 6,
833 .size = {
834 .width = 261,
835 .height = 163,
836 },
837};
838
f8fa17ba
AB		 839static const struct drm_display_mode innolux_g121x1_l03_mode = {
840 .clock = 65000,
841 .hdisplay = 1024,
842 .hsync_start = 1024 + 0,
843 .hsync_end = 1024 + 1,
844 .htotal = 1024 + 0 + 1 + 320,
845 .vdisplay = 768,
846 .vsync_start = 768 + 38,
847 .vsync_end = 768 + 38 + 1,
848 .vtotal = 768 + 38 + 1 + 0,
849 .vrefresh = 60,
850};
851
852static const struct panel_desc innolux_g121x1_l03 = {
853 .modes = &innolux_g121x1_l03_mode,
854 .num_modes = 1,
855 .bpc = 6,
856 .size = {
857 .width = 246,
858 .height = 185,
859 },
860 .delay = {
861 .enable = 200,
862 .unprepare = 200,
863 .disable = 400,
864 },
865};
866
0a2288c0 867static const struct drm_display_mode innolux_n116bge_mode = {
7fe8c777 868 .clock = 76420,
0a2288c0 869 .hdisplay = 1366,
7fe8c777
DK		 870 .hsync_start = 1366 + 136,
871 .hsync_end = 1366 + 136 + 30,
872 .htotal = 1366 + 136 + 30 + 60,
0a2288c0
TR		 873 .vdisplay = 768,
874 .vsync_start = 768 + 8,
7fe8c777
DK		 875 .vsync_end = 768 + 8 + 12,
876 .vtotal = 768 + 8 + 12 + 12,
0a2288c0
TR		 877 .vrefresh = 60,
878 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
879};
880
881static const struct panel_desc innolux_n116bge = {
882 .modes = &innolux_n116bge_mode,
883 .num_modes = 1,
884 .bpc = 6,
885 .size = {
886 .width = 256,
887 .height = 144,
888 },
889};
890
ea44739d
AB		 891static const struct drm_display_mode innolux_n156bge_l21_mode = {
892 .clock = 69300,
893 .hdisplay = 1366,
894 .hsync_start = 1366 + 16,
895 .hsync_end = 1366 + 16 + 34,
896 .htotal = 1366 + 16 + 34 + 50,
897 .vdisplay = 768,
898 .vsync_start = 768 + 2,
899 .vsync_end = 768 + 2 + 6,
900 .vtotal = 768 + 2 + 6 + 12,
901 .vrefresh = 60,
902};
903
904static const struct panel_desc innolux_n156bge_l21 = {
905 .modes = &innolux_n156bge_l21_mode,
906 .num_modes = 1,
0208d511 907 .bpc = 6,
ea44739d
AB		 908 .size = {
909 .width = 344,
910 .height = 193,
911 },
912};
913
bccac3f1
MG		 914static const struct drm_display_mode innolux_zj070na_01p_mode = {
915 .clock = 51501,
916 .hdisplay = 1024,
917 .hsync_start = 1024 + 128,
918 .hsync_end = 1024 + 128 + 64,
919 .htotal = 1024 + 128 + 64 + 128,
920 .vdisplay = 600,
921 .vsync_start = 600 + 16,
922 .vsync_end = 600 + 16 + 4,
923 .vtotal = 600 + 16 + 4 + 16,
924 .vrefresh = 60,
925};
926
927static const struct panel_desc innolux_zj070na_01p = {
928 .modes = &innolux_zj070na_01p_mode,
929 .num_modes = 1,
930 .bpc = 6,
931 .size = {
932 .width = 1024,
933 .height = 600,
934 },
935};
936
8def22e5
LS		 937static const struct display_timing kyo_tcg121xglp_timing = {
938 .pixelclock = { 52000000, 65000000, 71000000 },
939 .hactive = { 1024, 1024, 1024 },
940 .hfront_porch = { 2, 2, 2 },
941 .hback_porch = { 2, 2, 2 },
942 .hsync_len = { 86, 124, 244 },
943 .vactive = { 768, 768, 768 },
944 .vfront_porch = { 2, 2, 2 },
945 .vback_porch = { 2, 2, 2 },
946 .vsync_len = { 6, 34, 73 },
947 .flags = DISPLAY_FLAGS_DE_HIGH,
948};
949
950static const struct panel_desc kyo_tcg121xglp = {
951 .timings = &kyo_tcg121xglp_timing,
952 .num_timings = 1,
953 .bpc = 8,
954 .size = {
955 .width = 246,
956 .height = 184,
957 },
958 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
959};
960
dd015002
HS		 961static const struct drm_display_mode lg_lb070wv8_mode = {
962 .clock = 33246,
963 .hdisplay = 800,
964 .hsync_start = 800 + 88,
965 .hsync_end = 800 + 88 + 80,
966 .htotal = 800 + 88 + 80 + 88,
967 .vdisplay = 480,
968 .vsync_start = 480 + 10,
969 .vsync_end = 480 + 10 + 25,
970 .vtotal = 480 + 10 + 25 + 10,
971 .vrefresh = 60,
972};
973
974static const struct panel_desc lg_lb070wv8 = {
975 .modes = &lg_lb070wv8_mode,
976 .num_modes = 1,
977 .bpc = 16,
978 .size = {
979 .width = 151,
980 .height = 91,
981 },
982 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
983};
984
ec7c5653
TR		 985static const struct drm_display_mode lg_lp129qe_mode = {
986 .clock = 285250,
987 .hdisplay = 2560,
988 .hsync_start = 2560 + 48,
989 .hsync_end = 2560 + 48 + 32,
990 .htotal = 2560 + 48 + 32 + 80,
991 .vdisplay = 1700,
992 .vsync_start = 1700 + 3,
993 .vsync_end = 1700 + 3 + 10,
994 .vtotal = 1700 + 3 + 10 + 36,
995 .vrefresh = 60,
996};
997
998static const struct panel_desc lg_lp129qe = {
999 .modes = &lg_lp129qe_mode,
1000 .num_modes = 1,
0208d511 1001 .bpc = 8,
ec7c5653
TR		 1002 .size = {
1003 .width = 272,
1004 .height = 181,
1005 },
1006};
1007
c6e87f91 1008static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1009 .clock = 10870,
1010 .hdisplay = 480,
1011 .hsync_start = 480 + 2,
1012 .hsync_end = 480 + 2 + 41,
1013 .htotal = 480 + 2 + 41 + 2,
1014 .vdisplay = 272,
1015 .vsync_start = 272 + 2,
1016 .vsync_end = 272 + 2 + 4,
1017 .vtotal = 272 + 2 + 4 + 2,
1018 .vrefresh = 74,
4bc390c6 1019 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
c6e87f91 1020};
1021
1022static const struct panel_desc nec_nl4827hc19_05b = {
1023 .modes = &nec_nl4827hc19_05b_mode,
1024 .num_modes = 1,
1025 .bpc = 8,
1026 .size = {
1027 .width = 95,
1028 .height = 54,
1029 },
1030 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1031};
1032
a99fb626
GB		 1033static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1034 .pixelclock = { 30000000, 30000000, 40000000 },
1035 .hactive = { 800, 800, 800 },
1036 .hfront_porch = { 40, 40, 40 },
1037 .hback_porch = { 40, 40, 40 },
1038 .hsync_len = { 1, 48, 48 },
1039 .vactive = { 480, 480, 480 },
1040 .vfront_porch = { 13, 13, 13 },
1041 .vback_porch = { 29, 29, 29 },
1042 .vsync_len = { 3, 3, 3 },
1043 .flags = DISPLAY_FLAGS_DE_HIGH,
1044};
1045
1046static const struct panel_desc okaya_rs800480t_7x0gp = {
1047 .timings = &okaya_rs800480t_7x0gp_timing,
1048 .num_timings = 1,
1049 .bpc = 6,
1050 .size = {
1051 .width = 154,
1052 .height = 87,
1053 },
1054 .delay = {
1055 .prepare = 41,
1056 .enable = 50,
1057 .unprepare = 41,
1058 .disable = 50,
1059 },
1060 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1061};
1062
725c9d40
PZ		 1063static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1064 .clock = 25000,
1065 .hdisplay = 480,
1066 .hsync_start = 480 + 10,
1067 .hsync_end = 480 + 10 + 10,
1068 .htotal = 480 + 10 + 10 + 15,
1069 .vdisplay = 800,
1070 .vsync_start = 800 + 3,
1071 .vsync_end = 800 + 3 + 3,
1072 .vtotal = 800 + 3 + 3 + 3,
1073 .vrefresh = 60,
1074};
1075
1076static const struct panel_desc ortustech_com43h4m85ulc = {
1077 .modes = &ortustech_com43h4m85ulc_mode,
1078 .num_modes = 1,
1079 .bpc = 8,
1080 .size = {
1081 .width = 56,
1082 .height = 93,
1083 },
1084 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1085};
1086
d2a6f0f5
JW		 1087static const struct drm_display_mode qd43003c0_40_mode = {
1088 .clock = 9000,
1089 .hdisplay = 480,
1090 .hsync_start = 480 + 8,
1091 .hsync_end = 480 + 8 + 4,
1092 .htotal = 480 + 8 + 4 + 39,
1093 .vdisplay = 272,
1094 .vsync_start = 272 + 4,
1095 .vsync_end = 272 + 4 + 10,
1096 .vtotal = 272 + 4 + 10 + 2,
1097 .vrefresh = 60,
1098};
1099
1100static const struct panel_desc qd43003c0_40 = {
1101 .modes = &qd43003c0_40_mode,
1102 .num_modes = 1,
1103 .bpc = 8,
1104 .size = {
1105 .width = 95,
1106 .height = 53,
1107 },
1108 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1109};
1110
6d54e3d2
MD		 1111static const struct drm_display_mode samsung_ltn101nt05_mode = {
1112 .clock = 54030,
1113 .hdisplay = 1024,
1114 .hsync_start = 1024 + 24,
1115 .hsync_end = 1024 + 24 + 136,
1116 .htotal = 1024 + 24 + 136 + 160,
1117 .vdisplay = 600,
1118 .vsync_start = 600 + 3,
1119 .vsync_end = 600 + 3 + 6,
1120 .vtotal = 600 + 3 + 6 + 61,
1121 .vrefresh = 60,
1122};
1123
1124static const struct panel_desc samsung_ltn101nt05 = {
1125 .modes = &samsung_ltn101nt05_mode,
1126 .num_modes = 1,
0208d511 1127 .bpc = 6,
6d54e3d2
MD		 1128 .size = {
1129 .width = 1024,
1130 .height = 600,
1131 },
1132};
1133
0c934306
SM		 1134static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1135 .clock = 76300,
1136 .hdisplay = 1366,
1137 .hsync_start = 1366 + 64,
1138 .hsync_end = 1366 + 64 + 48,
1139 .htotal = 1366 + 64 + 48 + 128,
1140 .vdisplay = 768,
1141 .vsync_start = 768 + 2,
1142 .vsync_end = 768 + 2 + 5,
1143 .vtotal = 768 + 2 + 5 + 17,
1144 .vrefresh = 60,
1145};
1146
1147static const struct panel_desc samsung_ltn140at29_301 = {
1148 .modes = &samsung_ltn140at29_301_mode,
1149 .num_modes = 1,
1150 .bpc = 6,
1151 .size = {
1152 .width = 320,
1153 .height = 187,
1154 },
1155};
1156
9c6615bc
BB		 1157static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1158 .clock = 33300,
1159 .hdisplay = 800,
1160 .hsync_start = 800 + 1,
1161 .hsync_end = 800 + 1 + 64,
1162 .htotal = 800 + 1 + 64 + 64,
1163 .vdisplay = 480,
1164 .vsync_start = 480 + 1,
1165 .vsync_end = 480 + 1 + 23,
1166 .vtotal = 480 + 1 + 23 + 22,
1167 .vrefresh = 60,
1168};
1169
1170static const struct panel_desc shelly_sca07010_bfn_lnn = {
1171 .modes = &shelly_sca07010_bfn_lnn_mode,
1172 .num_modes = 1,
1173 .size = {
1174 .width = 152,
1175 .height = 91,
1176 },
1177 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1178};
1179
280921de
TR		 1180static const struct of_device_id platform_of_match[] = {
1181 {
1c550fa1
PZ		 1182 .compatible = "ampire,am800480r3tmqwa1h",
1183 .data = &ampire_am800480r3tmqwa1h,
1184 }, {
280921de
TR		 1185 .compatible = "auo,b101aw03",
1186 .data = &auo_b101aw03,
a531bc3d
HL		 1187 }, {
1188 .compatible = "auo,b101ean01",
1189 .data = &auo_b101ean01,
dac746e0
RC		 1190 }, {
1191 .compatible = "auo,b101xtn01",
1192 .data = &auo_b101xtn01,
e35e305e
AK		 1193 }, {
1194 .compatible = "auo,b116xw03",
1195 .data = &auo_b116xw03,
3e51d609
AK		 1196 }, {
1197 .compatible = "auo,b133htn01",
1198 .data = &auo_b133htn01,
a333f7ad
SM		 1199 }, {
1200 .compatible = "auo,b133xtn01",
1201 .data = &auo_b133xtn01,
d47df633
PZ		 1202 }, {
1203 .compatible = "avic,tm070ddh03",
1204 .data = &avic_tm070ddh03,
4c930757
SW		 1205 }, {
1206 .compatible = "chunghwa,claa101wa01a",
1207 .data = &chunghwa_claa101wa01a
280921de
TR		 1208 }, {
1209 .compatible = "chunghwa,claa101wb01",
1210 .data = &chunghwa_claa101wb01
26ab0065
SA		 1211 }, {
1212 .compatible = "edt,et057090dhu",
1213 .data = &edt_et057090dhu,
fff5de45
PZ		 1214 }, {
1215 .compatible = "edt,et070080dh6",
1216 .data = &edt_etm0700g0dh6,
1217 }, {
1218 .compatible = "edt,etm0700g0dh6",
1219 .data = &edt_etm0700g0dh6,
102932b0
BB		 1220 }, {
1221 .compatible = "foxlink,fl500wvr00-a0t",
1222 .data = &foxlink_fl500wvr00_a0t,
d435a2af
PZ		 1223 }, {
1224 .compatible = "giantplus,gpg482739qs5",
1225 .data = &giantplus_gpg482739qs5
a853205e
PZ		 1226 }, {
1227 .compatible = "hannstar,hsd070pww1",
1228 .data = &hannstar_hsd070pww1,
c0d607e5
EN		 1229 }, {
1230 .compatible = "hannstar,hsd100pxn1",
1231 .data = &hannstar_hsd100pxn1,
61ac0bf8
LS		 1232 }, {
1233 .compatible = "hit,tx23d38vm0caa",
1234 .data = &hitachi_tx23d38vm0caa
41bcceb4
NF		 1235 }, {
1236 .compatible = "innolux,at043tn24",
1237 .data = &innolux_at043tn24,
d731f661
LS		 1238 }, {
1239 .compatible ="innolux,g121i1-l01",
1240 .data = &innolux_g121i1_l01
f8fa17ba
AB		 1241 }, {
1242 .compatible = "innolux,g121x1-l03",
1243 .data = &innolux_g121x1_l03,
0a2288c0
TR		 1244 }, {
1245 .compatible = "innolux,n116bge",
1246 .data = &innolux_n116bge,
ea44739d
AB		 1247 }, {
1248 .compatible = "innolux,n156bge-l21",
1249 .data = &innolux_n156bge_l21,
bccac3f1
MG		 1250 }, {
1251 .compatible = "innolux,zj070na-01p",
1252 .data = &innolux_zj070na_01p,
8def22e5
LS		 1253 }, {
1254 .compatible = "kyo,tcg121xglp",
1255 .data = &kyo_tcg121xglp,
dd015002
HS		 1256 }, {
1257 .compatible = "lg,lb070wv8",
1258 .data = &lg_lb070wv8,
ec7c5653
TR		 1259 }, {
1260 .compatible = "lg,lp129qe",
1261 .data = &lg_lp129qe,
c6e87f91 1262 }, {
1263 .compatible = "nec,nl4827hc19-05b",
1264 .data = &nec_nl4827hc19_05b,
a99fb626
GB		 1265 }, {
1266 .compatible = "okaya,rs800480t-7x0gp",
1267 .data = &okaya_rs800480t_7x0gp,
725c9d40
PZ		 1268 }, {
1269 .compatible = "ortustech,com43h4m85ulc",
1270 .data = &ortustech_com43h4m85ulc,
d2a6f0f5
JW		 1271 }, {
1272 .compatible = "qiaodian,qd43003c0-40",
1273 .data = &qd43003c0_40,
6d54e3d2
MD		 1274 }, {
1275 .compatible = "samsung,ltn101nt05",
1276 .data = &samsung_ltn101nt05,
0c934306
SM		 1277 }, {
1278 .compatible = "samsung,ltn140at29-301",
1279 .data = &samsung_ltn140at29_301,
9c6615bc
BB		 1280 }, {
1281 .compatible = "shelly,sca07010-bfn-lnn",
1282 .data = &shelly_sca07010_bfn_lnn,
280921de
TR		 1283 }, {
1284 /* sentinel */
1285 }
1286};
1287MODULE_DEVICE_TABLE(of, platform_of_match);
1288
1289static int panel_simple_platform_probe(struct platform_device *pdev)
1290{
1291 const struct of_device_id *id;
1292
1293 id = of_match_node(platform_of_match, pdev->dev.of_node);
1294 if (!id)
1295 return -ENODEV;
1296
1297 return panel_simple_probe(&pdev->dev, id->data);
1298}
1299
1300static int panel_simple_platform_remove(struct platform_device *pdev)
1301{
1302 return panel_simple_remove(&pdev->dev);
1303}
1304
d02fd93e
TR		 1305static void panel_simple_platform_shutdown(struct platform_device *pdev)
1306{
1307 panel_simple_shutdown(&pdev->dev);
1308}
1309
280921de
TR		 1310static struct platform_driver panel_simple_platform_driver = {
1311 .driver = {
1312 .name = "panel-simple",
280921de
TR		 1313 .of_match_table = platform_of_match,
1314 },
1315 .probe = panel_simple_platform_probe,
1316 .remove = panel_simple_platform_remove,
d02fd93e 1317 .shutdown = panel_simple_platform_shutdown,
280921de
TR		 1318};
1319
210fcd9d
TR		 1320struct panel_desc_dsi {
1321 struct panel_desc desc;
1322
462658b8 1323 unsigned long flags;
210fcd9d
TR		 1324 enum mipi_dsi_pixel_format format;
1325 unsigned int lanes;
1326};
1327
d718d79e
TR		 1328static const struct drm_display_mode auo_b080uan01_mode = {
1329 .clock = 154500,
1330 .hdisplay = 1200,
1331 .hsync_start = 1200 + 62,
1332 .hsync_end = 1200 + 62 + 4,
1333 .htotal = 1200 + 62 + 4 + 62,
1334 .vdisplay = 1920,
1335 .vsync_start = 1920 + 9,
1336 .vsync_end = 1920 + 9 + 2,
1337 .vtotal = 1920 + 9 + 2 + 8,
1338 .vrefresh = 60,
1339};
1340
1341static const struct panel_desc_dsi auo_b080uan01 = {
1342 .desc = {
1343 .modes = &auo_b080uan01_mode,
1344 .num_modes = 1,
1345 .bpc = 8,
1346 .size = {
1347 .width = 108,
1348 .height = 272,
1349 },
1350 },
1351 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1352 .format = MIPI_DSI_FMT_RGB888,
1353 .lanes = 4,
1354};
1355
c8521969
CZ		 1356static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1357 .clock = 160000,
1358 .hdisplay = 1200,
1359 .hsync_start = 1200 + 120,
1360 .hsync_end = 1200 + 120 + 20,
1361 .htotal = 1200 + 120 + 20 + 21,
1362 .vdisplay = 1920,
1363 .vsync_start = 1920 + 21,
1364 .vsync_end = 1920 + 21 + 3,
1365 .vtotal = 1920 + 21 + 3 + 18,
1366 .vrefresh = 60,
1367 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1368};
1369
1370static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1371 .desc = {
1372 .modes = &boe_tv080wum_nl0_mode,
1373 .num_modes = 1,
1374 .size = {
1375 .width = 107,
1376 .height = 172,
1377 },
1378 },
1379 .flags = MIPI_DSI_MODE_VIDEO |
1380 MIPI_DSI_MODE_VIDEO_BURST |
1381 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1382 .format = MIPI_DSI_FMT_RGB888,
1383 .lanes = 4,
1384};
1385
712ac1ba
AC		 1386static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1387 .clock = 71000,
1388 .hdisplay = 800,
1389 .hsync_start = 800 + 32,
1390 .hsync_end = 800 + 32 + 1,
1391 .htotal = 800 + 32 + 1 + 57,
1392 .vdisplay = 1280,
1393 .vsync_start = 1280 + 28,
1394 .vsync_end = 1280 + 28 + 1,
1395 .vtotal = 1280 + 28 + 1 + 14,
1396 .vrefresh = 60,
1397};
1398
1399static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1400 .desc = {
1401 .modes = &lg_ld070wx3_sl01_mode,
1402 .num_modes = 1,
d7a839cd 1403 .bpc = 8,
712ac1ba
AC		 1404 .size = {
1405 .width = 94,
1406 .height = 151,
1407 },
1408 },
5e4cc278 1409 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
712ac1ba
AC		 1410 .format = MIPI_DSI_FMT_RGB888,
1411 .lanes = 4,
1412};
1413
499ce85a
AC		 1414static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1415 .clock = 67000,
1416 .hdisplay = 720,
1417 .hsync_start = 720 + 12,
1418 .hsync_end = 720 + 12 + 4,
1419 .htotal = 720 + 12 + 4 + 112,
1420 .vdisplay = 1280,
1421 .vsync_start = 1280 + 8,
1422 .vsync_end = 1280 + 8 + 4,
1423 .vtotal = 1280 + 8 + 4 + 12,
1424 .vrefresh = 60,
1425};
1426
1427static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1428 .desc = {
1429 .modes = &lg_lh500wx1_sd03_mode,
1430 .num_modes = 1,
d7a839cd 1431 .bpc = 8,
499ce85a
AC		 1432 .size = {
1433 .width = 62,
1434 .height = 110,
1435 },
1436 },
1437 .flags = MIPI_DSI_MODE_VIDEO,
1438 .format = MIPI_DSI_FMT_RGB888,
1439 .lanes = 4,
1440};
1441
280921de
TR		 1442static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1443 .clock = 157200,
1444 .hdisplay = 1920,
1445 .hsync_start = 1920 + 154,
1446 .hsync_end = 1920 + 154 + 16,
1447 .htotal = 1920 + 154 + 16 + 32,
1448 .vdisplay = 1200,
1449 .vsync_start = 1200 + 17,
1450 .vsync_end = 1200 + 17 + 2,
1451 .vtotal = 1200 + 17 + 2 + 16,
1452 .vrefresh = 60,
1453};
1454
210fcd9d
TR		 1455static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1456 .desc = {
1457 .modes = &panasonic_vvx10f004b00_mode,
1458 .num_modes = 1,
d7a839cd 1459 .bpc = 8,
210fcd9d
TR		 1460 .size = {
1461 .width = 217,
1462 .height = 136,
1463 },
280921de 1464 },
5e4cc278
AC		 1465 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1466 MIPI_DSI_CLOCK_NON_CONTINUOUS,
210fcd9d
TR		 1467 .format = MIPI_DSI_FMT_RGB888,
1468 .lanes = 4,
1469};
1470
c8521969 1471
210fcd9d
TR		 1472static const struct of_device_id dsi_of_match[] = {
1473 {
d718d79e
TR		 1474 .compatible = "auo,b080uan01",
1475 .data = &auo_b080uan01
c8521969
CZ		 1476 }, {
1477 .compatible = "boe,tv080wum-nl0",
1478 .data = &boe_tv080wum_nl0
d718d79e 1479 }, {
712ac1ba
AC		 1480 .compatible = "lg,ld070wx3-sl01",
1481 .data = &lg_ld070wx3_sl01
1482 }, {
499ce85a
AC		 1483 .compatible = "lg,lh500wx1-sd03",
1484 .data = &lg_lh500wx1_sd03
1485 }, {
210fcd9d
TR		 1486 .compatible = "panasonic,vvx10f004b00",
1487 .data = &panasonic_vvx10f004b00
1488 }, {
1489 /* sentinel */
1490 }
1491};
1492MODULE_DEVICE_TABLE(of, dsi_of_match);
1493
1494static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1495{
1496 const struct panel_desc_dsi *desc;
1497 const struct of_device_id *id;
1498 int err;
1499
1500 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1501 if (!id)
1502 return -ENODEV;
1503
1504 desc = id->data;
1505
1506 err = panel_simple_probe(&dsi->dev, &desc->desc);
1507 if (err < 0)
1508 return err;
1509
462658b8 1510 dsi->mode_flags = desc->flags;
210fcd9d
TR		 1511 dsi->format = desc->format;
1512 dsi->lanes = desc->lanes;
1513
1514 return mipi_dsi_attach(dsi);
1515}
1516
1517static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1518{
1519 int err;
1520
1521 err = mipi_dsi_detach(dsi);
1522 if (err < 0)
1523 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1524
1525 return panel_simple_remove(&dsi->dev);
1526}
1527
d02fd93e
TR		 1528static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1529{
1530 panel_simple_shutdown(&dsi->dev);
1531}
1532
210fcd9d
TR		 1533static struct mipi_dsi_driver panel_simple_dsi_driver = {
1534 .driver = {
1535 .name = "panel-simple-dsi",
210fcd9d
TR		 1536 .of_match_table = dsi_of_match,
1537 },
1538 .probe = panel_simple_dsi_probe,
1539 .remove = panel_simple_dsi_remove,
d02fd93e 1540 .shutdown = panel_simple_dsi_shutdown,
280921de
TR		 1541};
1542
1543static int __init panel_simple_init(void)
1544{
210fcd9d
TR		 1545 int err;
1546
1547 err = platform_driver_register(&panel_simple_platform_driver);
1548 if (err < 0)
1549 return err;
1550
1551 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1552 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1553 if (err < 0)
1554 return err;
1555 }
1556
1557 return 0;
280921de
TR		 1558}
1559module_init(panel_simple_init);
1560
1561static void __exit panel_simple_exit(void)
1562{
210fcd9d
TR		 1563 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1564 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1565
280921de
TR		 1566 platform_driver_unregister(&panel_simple_platform_driver);
1567}
1568module_exit(panel_simple_exit);
1569
1570MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1571MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1572MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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