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drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4)
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
760285e7 27#include <drm/drmP.h>
bcc1c2a1 28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
760285e7 30#include <drm/radeon_drm.h>
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
4a15903d
AD		 40static const u32 crtc_offsets[6] =
41{
42 EVERGREEN_CRTC0_REGISTER_OFFSET,
43 EVERGREEN_CRTC1_REGISTER_OFFSET,
44 EVERGREEN_CRTC2_REGISTER_OFFSET,
45 EVERGREEN_CRTC3_REGISTER_OFFSET,
46 EVERGREEN_CRTC4_REGISTER_OFFSET,
47 EVERGREEN_CRTC5_REGISTER_OFFSET
48};
49
bcc1c2a1
AD		 50static void evergreen_gpu_init(struct radeon_device *rdev);
51void evergreen_fini(struct radeon_device *rdev);
b07759bf 52void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
1b37078b
AD		 53extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54 int ring, u32 cp_int_cntl);
bcc1c2a1 55
285484e2
JG		 56void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57 unsigned *bankh, unsigned *mtaspect,
58 unsigned *tile_split)
59{
60 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
61 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
62 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
63 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
64 switch (*bankw) {
65 default:
66 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
67 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
68 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
69 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
70 }
71 switch (*bankh) {
72 default:
73 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
74 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
75 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
76 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
77 }
78 switch (*mtaspect) {
79 default:
80 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
81 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
82 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
83 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
84 }
85}
86
23d33ba3
AD		 87static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
88 u32 cntl_reg, u32 status_reg)
89{
90 int r, i;
91 struct atom_clock_dividers dividers;
92
93 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
94 clock, false, &dividers);
95 if (r)
96 return r;
97
98 WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
99
100 for (i = 0; i < 100; i++) {
101 if (RREG32(status_reg) & DCLK_STATUS)
102 break;
103 mdelay(10);
104 }
105 if (i == 100)
106 return -ETIMEDOUT;
107
108 return 0;
109}
110
111int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
112{
113 int r = 0;
114 u32 cg_scratch = RREG32(CG_SCRATCH1);
115
116 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
117 if (r)
118 goto done;
119 cg_scratch &= 0xffff0000;
120 cg_scratch |= vclk / 100; /* Mhz */
121
122 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
123 if (r)
124 goto done;
125 cg_scratch &= 0x0000ffff;
126 cg_scratch |= (dclk / 100) << 16; /* Mhz */
127
128done:
129 WREG32(CG_SCRATCH1, cg_scratch);
130
131 return r;
132}
133
d054ac16
AD		 134void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
135{
136 u16 ctl, v;
32195aec 137 int err;
d054ac16 138
32195aec 139 err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
d054ac16
AD		 140 if (err)
141 return;
142
143 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
144
145 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
146 * to avoid hangs or perfomance issues
147 */
148 if ((v == 0) || (v == 6) || (v == 7)) {
149 ctl &= ~PCI_EXP_DEVCTL_READRQ;
150 ctl |= (2 << 12);
32195aec 151 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
d054ac16
AD		 152 }
153}
154
377edc8b
AD		 155/**
156 * dce4_wait_for_vblank - vblank wait asic callback.
157 *
158 * @rdev: radeon_device pointer
159 * @crtc: crtc to wait for vblank on
160 *
161 * Wait for vblank on the requested crtc (evergreen+).
162 */
3ae19b75
AD		 163void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
164{
3ae19b75
AD		 165 int i;
166
4a15903d
AD		 167 if (crtc >= rdev->num_crtc)
168 return;
169
170 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
3ae19b75 171 for (i = 0; i < rdev->usec_timeout; i++) {
4a15903d 172 if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
3ae19b75
AD		 173 break;
174 udelay(1);
175 }
176 for (i = 0; i < rdev->usec_timeout; i++) {
4a15903d 177 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
3ae19b75
AD		 178 break;
179 udelay(1);
180 }
181 }
182}
183
377edc8b
AD		 184/**
185 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
186 *
187 * @rdev: radeon_device pointer
188 * @crtc: crtc to prepare for pageflip on
189 *
190 * Pre-pageflip callback (evergreen+).
191 * Enables the pageflip irq (vblank irq).
192 */
6f34be50
AD		 193void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
194{
6f34be50
AD		 195 /* enable the pflip int */
196 radeon_irq_kms_pflip_irq_get(rdev, crtc);
197}
198
377edc8b
AD		 199/**
200 * evergreen_post_page_flip - pos-pageflip callback.
201 *
202 * @rdev: radeon_device pointer
203 * @crtc: crtc to cleanup pageflip on
204 *
205 * Post-pageflip callback (evergreen+).
206 * Disables the pageflip irq (vblank irq).
207 */
6f34be50
AD		 208void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
209{
210 /* disable the pflip int */
211 radeon_irq_kms_pflip_irq_put(rdev, crtc);
212}
213
377edc8b
AD		 214/**
215 * evergreen_page_flip - pageflip callback.
216 *
217 * @rdev: radeon_device pointer
218 * @crtc_id: crtc to cleanup pageflip on
219 * @crtc_base: new address of the crtc (GPU MC address)
220 *
221 * Does the actual pageflip (evergreen+).
222 * During vblank we take the crtc lock and wait for the update_pending
223 * bit to go high, when it does, we release the lock, and allow the
224 * double buffered update to take place.
225 * Returns the current update pending status.
226 */
6f34be50
AD		 227u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
228{
229 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
230 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 231 int i;
6f34be50
AD		 232
233 /* Lock the graphics update lock */
234 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
235 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
236
237 /* update the scanout addresses */
238 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
239 upper_32_bits(crtc_base));
240 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
241 (u32)crtc_base);
242
243 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
244 upper_32_bits(crtc_base));
245 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
246 (u32)crtc_base);
247
248 /* Wait for update_pending to go high. */
f6496479
AD		 249 for (i = 0; i < rdev->usec_timeout; i++) {
250 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
251 break;
252 udelay(1);
253 }
6f34be50
AD		 254 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
255
256 /* Unlock the lock, so double-buffering can take place inside vblank */
257 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
258 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
259
260 /* Return current update_pending status: */
261 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
262}
263
21a8122a 264/* get temperature in millidegrees */
20d391d7 265int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 266{
1c88d74f
AD		 267 u32 temp, toffset;
268 int actual_temp = 0;
67b3f823
AD		 269
270 if (rdev->family == CHIP_JUNIPER) {
271 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
272 TOFFSET_SHIFT;
273 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
274 TS0_ADC_DOUT_SHIFT;
275
276 if (toffset & 0x100)
277 actual_temp = temp / 2 - (0x200 - toffset);
278 else
279 actual_temp = temp / 2 + toffset;
280
281 actual_temp = actual_temp * 1000;
282
283 } else {
284 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
285 ASIC_T_SHIFT;
286
287 if (temp & 0x400)
288 actual_temp = -256;
289 else if (temp & 0x200)
290 actual_temp = 255;
291 else if (temp & 0x100) {
292 actual_temp = temp & 0x1ff;
293 actual_temp |= ~0x1ff;
294 } else
295 actual_temp = temp & 0xff;
296
297 actual_temp = (actual_temp * 1000) / 2;
298 }
21a8122a 299
67b3f823 300 return actual_temp;
21a8122a
AD		 301}
302
20d391d7 303int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 304{
305 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 306 int actual_temp = temp - 49;
e33df25f
AD		 307
308 return actual_temp * 1000;
309}
310
377edc8b
AD		 311/**
312 * sumo_pm_init_profile - Initialize power profiles callback.
313 *
314 * @rdev: radeon_device pointer
315 *
316 * Initialize the power states used in profile mode
317 * (sumo, trinity, SI).
318 * Used for profile mode only.
319 */
a4c9e2ee
AD		 320void sumo_pm_init_profile(struct radeon_device *rdev)
321{
322 int idx;
323
324 /* default */
325 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
326 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
327 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
329
330 /* low,mid sh/mh */
331 if (rdev->flags & RADEON_IS_MOBILITY)
332 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
333 else
334 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
335
336 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
337 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
338 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
340
341 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
342 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
343 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
345
346 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
347 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
348 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
350
351 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
352 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
353 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
355
356 /* high sh/mh */
357 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
358 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
359 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
360 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
362 rdev->pm.power_state[idx].num_clock_modes - 1;
363
364 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
365 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
366 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
367 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
368 rdev->pm.power_state[idx].num_clock_modes - 1;
369}
370
27810fb2
AD		 371/**
372 * btc_pm_init_profile - Initialize power profiles callback.
373 *
374 * @rdev: radeon_device pointer
375 *
376 * Initialize the power states used in profile mode
377 * (BTC, cayman).
378 * Used for profile mode only.
379 */
380void btc_pm_init_profile(struct radeon_device *rdev)
381{
382 int idx;
383
384 /* default */
385 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
386 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
388 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
389 /* starting with BTC, there is one state that is used for both
390 * MH and SH. Difference is that we always use the high clock index for
391 * mclk.
392 */
393 if (rdev->flags & RADEON_IS_MOBILITY)
394 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
395 else
396 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
397 /* low sh */
398 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
399 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
400 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
401 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
402 /* mid sh */
403 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
404 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
405 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
406 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
407 /* high sh */
408 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
409 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
410 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
411 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
412 /* low mh */
413 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
414 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
415 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
416 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
417 /* mid mh */
418 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
419 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
420 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
421 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
422 /* high mh */
423 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
424 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
425 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
426 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
427}
428
377edc8b
AD		 429/**
430 * evergreen_pm_misc - set additional pm hw parameters callback.
431 *
432 * @rdev: radeon_device pointer
433 *
434 * Set non-clock parameters associated with a power state
435 * (voltage, etc.) (evergreen+).
436 */
49e02b73
AD		 437void evergreen_pm_misc(struct radeon_device *rdev)
438{
a081a9d6
RM		 439 int req_ps_idx = rdev->pm.requested_power_state_index;
440 int req_cm_idx = rdev->pm.requested_clock_mode_index;
441 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
442 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 443
2feea49a 444 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 445 /* 0xff01 is a flag rather then an actual voltage */
446 if (voltage->voltage == 0xff01)
447 return;
2feea49a 448 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 449 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 450 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 451 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
452 }
7ae764b1
AD		 453
454 /* starting with BTC, there is one state that is used for both
455 * MH and SH. Difference is that we always use the high clock index for
456 * mclk and vddci.
457 */
458 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
459 (rdev->family >= CHIP_BARTS) &&
460 rdev->pm.active_crtc_count &&
461 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
462 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
463 voltage = &rdev->pm.power_state[req_ps_idx].
464 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
465
a377e187
AD		 466 /* 0xff01 is a flag rather then an actual voltage */
467 if (voltage->vddci == 0xff01)
468 return;
2feea49a
AD		 469 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
470 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
471 rdev->pm.current_vddci = voltage->vddci;
472 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 473 }
474 }
49e02b73
AD		 475}
476
377edc8b
AD		 477/**
478 * evergreen_pm_prepare - pre-power state change callback.
479 *
480 * @rdev: radeon_device pointer
481 *
482 * Prepare for a power state change (evergreen+).
483 */
49e02b73
AD		 484void evergreen_pm_prepare(struct radeon_device *rdev)
485{
486 struct drm_device *ddev = rdev->ddev;
487 struct drm_crtc *crtc;
488 struct radeon_crtc *radeon_crtc;
489 u32 tmp;
490
491 /* disable any active CRTCs */
492 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
493 radeon_crtc = to_radeon_crtc(crtc);
494 if (radeon_crtc->enabled) {
495 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
496 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
497 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
498 }
499 }
500}
501
377edc8b
AD		 502/**
503 * evergreen_pm_finish - post-power state change callback.
504 *
505 * @rdev: radeon_device pointer
506 *
507 * Clean up after a power state change (evergreen+).
508 */
49e02b73
AD		 509void evergreen_pm_finish(struct radeon_device *rdev)
510{
511 struct drm_device *ddev = rdev->ddev;
512 struct drm_crtc *crtc;
513 struct radeon_crtc *radeon_crtc;
514 u32 tmp;
515
516 /* enable any active CRTCs */
517 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
518 radeon_crtc = to_radeon_crtc(crtc);
519 if (radeon_crtc->enabled) {
520 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
521 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
522 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
523 }
524 }
525}
526
377edc8b
AD		 527/**
528 * evergreen_hpd_sense - hpd sense callback.
529 *
530 * @rdev: radeon_device pointer
531 * @hpd: hpd (hotplug detect) pin
532 *
533 * Checks if a digital monitor is connected (evergreen+).
534 * Returns true if connected, false if not connected.
535 */
bcc1c2a1
AD		 536bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
537{
538 bool connected = false;
0ca2ab52
AD		 539
540 switch (hpd) {
541 case RADEON_HPD_1:
542 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
543 connected = true;
544 break;
545 case RADEON_HPD_2:
546 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
547 connected = true;
548 break;
549 case RADEON_HPD_3:
550 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
551 connected = true;
552 break;
553 case RADEON_HPD_4:
554 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
555 connected = true;
556 break;
557 case RADEON_HPD_5:
558 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
559 connected = true;
560 break;
561 case RADEON_HPD_6:
562 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
563 connected = true;
564 break;
565 default:
566 break;
567 }
568
bcc1c2a1
AD		 569 return connected;
570}
571
377edc8b
AD		 572/**
573 * evergreen_hpd_set_polarity - hpd set polarity callback.
574 *
575 * @rdev: radeon_device pointer
576 * @hpd: hpd (hotplug detect) pin
577 *
578 * Set the polarity of the hpd pin (evergreen+).
579 */
bcc1c2a1
AD		 580void evergreen_hpd_set_polarity(struct radeon_device *rdev,
581 enum radeon_hpd_id hpd)
582{
0ca2ab52
AD		 583 u32 tmp;
584 bool connected = evergreen_hpd_sense(rdev, hpd);
585
586 switch (hpd) {
587 case RADEON_HPD_1:
588 tmp = RREG32(DC_HPD1_INT_CONTROL);
589 if (connected)
590 tmp &= ~DC_HPDx_INT_POLARITY;
591 else
592 tmp |= DC_HPDx_INT_POLARITY;
593 WREG32(DC_HPD1_INT_CONTROL, tmp);
594 break;
595 case RADEON_HPD_2:
596 tmp = RREG32(DC_HPD2_INT_CONTROL);
597 if (connected)
598 tmp &= ~DC_HPDx_INT_POLARITY;
599 else
600 tmp |= DC_HPDx_INT_POLARITY;
601 WREG32(DC_HPD2_INT_CONTROL, tmp);
602 break;
603 case RADEON_HPD_3:
604 tmp = RREG32(DC_HPD3_INT_CONTROL);
605 if (connected)
606 tmp &= ~DC_HPDx_INT_POLARITY;
607 else
608 tmp |= DC_HPDx_INT_POLARITY;
609 WREG32(DC_HPD3_INT_CONTROL, tmp);
610 break;
611 case RADEON_HPD_4:
612 tmp = RREG32(DC_HPD4_INT_CONTROL);
613 if (connected)
614 tmp &= ~DC_HPDx_INT_POLARITY;
615 else
616 tmp |= DC_HPDx_INT_POLARITY;
617 WREG32(DC_HPD4_INT_CONTROL, tmp);
618 break;
619 case RADEON_HPD_5:
620 tmp = RREG32(DC_HPD5_INT_CONTROL);
621 if (connected)
622 tmp &= ~DC_HPDx_INT_POLARITY;
623 else
624 tmp |= DC_HPDx_INT_POLARITY;
625 WREG32(DC_HPD5_INT_CONTROL, tmp);
626 break;
627 case RADEON_HPD_6:
628 tmp = RREG32(DC_HPD6_INT_CONTROL);
629 if (connected)
630 tmp &= ~DC_HPDx_INT_POLARITY;
631 else
632 tmp |= DC_HPDx_INT_POLARITY;
633 WREG32(DC_HPD6_INT_CONTROL, tmp);
634 break;
635 default:
636 break;
637 }
bcc1c2a1
AD		 638}
639
377edc8b
AD		 640/**
641 * evergreen_hpd_init - hpd setup callback.
642 *
643 * @rdev: radeon_device pointer
644 *
645 * Setup the hpd pins used by the card (evergreen+).
646 * Enable the pin, set the polarity, and enable the hpd interrupts.
647 */
bcc1c2a1
AD		 648void evergreen_hpd_init(struct radeon_device *rdev)
649{
0ca2ab52
AD		 650 struct drm_device *dev = rdev->ddev;
651 struct drm_connector *connector;
fb98257a 652 unsigned enabled = 0;
0ca2ab52
AD		 653 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
654 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 655
0ca2ab52
AD		 656 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
657 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
658 switch (radeon_connector->hpd.hpd) {
659 case RADEON_HPD_1:
660 WREG32(DC_HPD1_CONTROL, tmp);
0ca2ab52
AD		 661 break;
662 case RADEON_HPD_2:
663 WREG32(DC_HPD2_CONTROL, tmp);
0ca2ab52
AD		 664 break;
665 case RADEON_HPD_3:
666 WREG32(DC_HPD3_CONTROL, tmp);
0ca2ab52
AD		 667 break;
668 case RADEON_HPD_4:
669 WREG32(DC_HPD4_CONTROL, tmp);
0ca2ab52
AD		 670 break;
671 case RADEON_HPD_5:
672 WREG32(DC_HPD5_CONTROL, tmp);
0ca2ab52
AD		 673 break;
674 case RADEON_HPD_6:
675 WREG32(DC_HPD6_CONTROL, tmp);
0ca2ab52
AD		 676 break;
677 default:
678 break;
679 }
64912e99 680 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
fb98257a 681 enabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 682 }
fb98257a 683 radeon_irq_kms_enable_hpd(rdev, enabled);
bcc1c2a1
AD		 684}
685
377edc8b
AD		 686/**
687 * evergreen_hpd_fini - hpd tear down callback.
688 *
689 * @rdev: radeon_device pointer
690 *
691 * Tear down the hpd pins used by the card (evergreen+).
692 * Disable the hpd interrupts.
693 */
0ca2ab52 694void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 695{
0ca2ab52
AD		 696 struct drm_device *dev = rdev->ddev;
697 struct drm_connector *connector;
fb98257a 698 unsigned disabled = 0;
0ca2ab52
AD		 699
700 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
701 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
702 switch (radeon_connector->hpd.hpd) {
703 case RADEON_HPD_1:
704 WREG32(DC_HPD1_CONTROL, 0);
0ca2ab52
AD		 705 break;
706 case RADEON_HPD_2:
707 WREG32(DC_HPD2_CONTROL, 0);
0ca2ab52
AD		 708 break;
709 case RADEON_HPD_3:
710 WREG32(DC_HPD3_CONTROL, 0);
0ca2ab52
AD		 711 break;
712 case RADEON_HPD_4:
713 WREG32(DC_HPD4_CONTROL, 0);
0ca2ab52
AD		 714 break;
715 case RADEON_HPD_5:
716 WREG32(DC_HPD5_CONTROL, 0);
0ca2ab52
AD		 717 break;
718 case RADEON_HPD_6:
719 WREG32(DC_HPD6_CONTROL, 0);
0ca2ab52
AD		 720 break;
721 default:
722 break;
723 }
fb98257a 724 disabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 725 }
fb98257a 726 radeon_irq_kms_disable_hpd(rdev, disabled);
bcc1c2a1
AD		 727}
728
f9d9c362
AD		 729/* watermark setup */
730
731static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
732 struct radeon_crtc *radeon_crtc,
733 struct drm_display_mode *mode,
734 struct drm_display_mode *other_mode)
735{
12dfc843 736 u32 tmp;
f9d9c362
AD		 737 /*
738 * Line Buffer Setup
739 * There are 3 line buffers, each one shared by 2 display controllers.
740 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
741 * the display controllers. The paritioning is done via one of four
742 * preset allocations specified in bits 2:0:
743 * first display controller
744 * 0 - first half of lb (3840 * 2)
745 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 746 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 747 * 3 - first 1/4 of lb (1920 * 2)
748 * second display controller
749 * 4 - second half of lb (3840 * 2)
750 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 751 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 752 * 7 - last 1/4 of lb (1920 * 2)
753 */
12dfc843
AD		 754 /* this can get tricky if we have two large displays on a paired group
755 * of crtcs. Ideally for multiple large displays we'd assign them to
756 * non-linked crtcs for maximum line buffer allocation.
757 */
758 if (radeon_crtc->base.enabled && mode) {
759 if (other_mode)
f9d9c362 760 tmp = 0; /* 1/2 */
12dfc843
AD		 761 else
762 tmp = 2; /* whole */
763 } else
764 tmp = 0;
f9d9c362
AD		 765
766 /* second controller of the pair uses second half of the lb */
767 if (radeon_crtc->crtc_id % 2)
768 tmp += 4;
769 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
770
12dfc843
AD		 771 if (radeon_crtc->base.enabled && mode) {
772 switch (tmp) {
773 case 0:
774 case 4:
775 default:
776 if (ASIC_IS_DCE5(rdev))
777 return 4096 * 2;
778 else
779 return 3840 * 2;
780 case 1:
781 case 5:
782 if (ASIC_IS_DCE5(rdev))
783 return 6144 * 2;
784 else
785 return 5760 * 2;
786 case 2:
787 case 6:
788 if (ASIC_IS_DCE5(rdev))
789 return 8192 * 2;
790 else
791 return 7680 * 2;
792 case 3:
793 case 7:
794 if (ASIC_IS_DCE5(rdev))
795 return 2048 * 2;
796 else
797 return 1920 * 2;
798 }
f9d9c362 799 }
12dfc843
AD		 800
801 /* controller not enabled, so no lb used */
802 return 0;
f9d9c362
AD		 803}
804
ca7db22b 805u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
f9d9c362
AD		 806{
807 u32 tmp = RREG32(MC_SHARED_CHMAP);
808
809 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
810 case 0:
811 default:
812 return 1;
813 case 1:
814 return 2;
815 case 2:
816 return 4;
817 case 3:
818 return 8;
819 }
820}
821
822struct evergreen_wm_params {
823 u32 dram_channels; /* number of dram channels */
824 u32 yclk; /* bandwidth per dram data pin in kHz */
825 u32 sclk; /* engine clock in kHz */
826 u32 disp_clk; /* display clock in kHz */
827 u32 src_width; /* viewport width */
828 u32 active_time; /* active display time in ns */
829 u32 blank_time; /* blank time in ns */
830 bool interlaced; /* mode is interlaced */
831 fixed20_12 vsc; /* vertical scale ratio */
832 u32 num_heads; /* number of active crtcs */
833 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
834 u32 lb_size; /* line buffer allocated to pipe */
835 u32 vtaps; /* vertical scaler taps */
836};
837
838static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
839{
840 /* Calculate DRAM Bandwidth and the part allocated to display. */
841 fixed20_12 dram_efficiency; /* 0.7 */
842 fixed20_12 yclk, dram_channels, bandwidth;
843 fixed20_12 a;
844
845 a.full = dfixed_const(1000);
846 yclk.full = dfixed_const(wm->yclk);
847 yclk.full = dfixed_div(yclk, a);
848 dram_channels.full = dfixed_const(wm->dram_channels * 4);
849 a.full = dfixed_const(10);
850 dram_efficiency.full = dfixed_const(7);
851 dram_efficiency.full = dfixed_div(dram_efficiency, a);
852 bandwidth.full = dfixed_mul(dram_channels, yclk);
853 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
854
855 return dfixed_trunc(bandwidth);
856}
857
858static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
859{
860 /* Calculate DRAM Bandwidth and the part allocated to display. */
861 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
862 fixed20_12 yclk, dram_channels, bandwidth;
863 fixed20_12 a;
864
865 a.full = dfixed_const(1000);
866 yclk.full = dfixed_const(wm->yclk);
867 yclk.full = dfixed_div(yclk, a);
868 dram_channels.full = dfixed_const(wm->dram_channels * 4);
869 a.full = dfixed_const(10);
870 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
871 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
872 bandwidth.full = dfixed_mul(dram_channels, yclk);
873 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
874
875 return dfixed_trunc(bandwidth);
876}
877
878static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
879{
880 /* Calculate the display Data return Bandwidth */
881 fixed20_12 return_efficiency; /* 0.8 */
882 fixed20_12 sclk, bandwidth;
883 fixed20_12 a;
884
885 a.full = dfixed_const(1000);
886 sclk.full = dfixed_const(wm->sclk);
887 sclk.full = dfixed_div(sclk, a);
888 a.full = dfixed_const(10);
889 return_efficiency.full = dfixed_const(8);
890 return_efficiency.full = dfixed_div(return_efficiency, a);
891 a.full = dfixed_const(32);
892 bandwidth.full = dfixed_mul(a, sclk);
893 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
894
895 return dfixed_trunc(bandwidth);
896}
897
898static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
899{
900 /* Calculate the DMIF Request Bandwidth */
901 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
902 fixed20_12 disp_clk, bandwidth;
903 fixed20_12 a;
904
905 a.full = dfixed_const(1000);
906 disp_clk.full = dfixed_const(wm->disp_clk);
907 disp_clk.full = dfixed_div(disp_clk, a);
908 a.full = dfixed_const(10);
909 disp_clk_request_efficiency.full = dfixed_const(8);
910 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
911 a.full = dfixed_const(32);
912 bandwidth.full = dfixed_mul(a, disp_clk);
913 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
914
915 return dfixed_trunc(bandwidth);
916}
917
918static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
919{
920 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
921 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
922 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
923 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
924
925 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
926}
927
928static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
929{
930 /* Calculate the display mode Average Bandwidth
931 * DisplayMode should contain the source and destination dimensions,
932 * timing, etc.
933 */
934 fixed20_12 bpp;
935 fixed20_12 line_time;
936 fixed20_12 src_width;
937 fixed20_12 bandwidth;
938 fixed20_12 a;
939
940 a.full = dfixed_const(1000);
941 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
942 line_time.full = dfixed_div(line_time, a);
943 bpp.full = dfixed_const(wm->bytes_per_pixel);
944 src_width.full = dfixed_const(wm->src_width);
945 bandwidth.full = dfixed_mul(src_width, bpp);
946 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
947 bandwidth.full = dfixed_div(bandwidth, line_time);
948
949 return dfixed_trunc(bandwidth);
950}
951
952static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
953{
954 /* First calcualte the latency in ns */
955 u32 mc_latency = 2000; /* 2000 ns. */
956 u32 available_bandwidth = evergreen_available_bandwidth(wm);
957 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
958 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
959 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
960 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
961 (wm->num_heads * cursor_line_pair_return_time);
962 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
963 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
964 fixed20_12 a, b, c;
965
966 if (wm->num_heads == 0)
967 return 0;
968
969 a.full = dfixed_const(2);
970 b.full = dfixed_const(1);
971 if ((wm->vsc.full > a.full) ||
972 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
973 (wm->vtaps >= 5) ||
974 ((wm->vsc.full >= a.full) && wm->interlaced))
975 max_src_lines_per_dst_line = 4;
976 else
977 max_src_lines_per_dst_line = 2;
978
979 a.full = dfixed_const(available_bandwidth);
980 b.full = dfixed_const(wm->num_heads);
981 a.full = dfixed_div(a, b);
982
983 b.full = dfixed_const(1000);
984 c.full = dfixed_const(wm->disp_clk);
985 b.full = dfixed_div(c, b);
986 c.full = dfixed_const(wm->bytes_per_pixel);
987 b.full = dfixed_mul(b, c);
988
989 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
990
991 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
992 b.full = dfixed_const(1000);
993 c.full = dfixed_const(lb_fill_bw);
994 b.full = dfixed_div(c, b);
995 a.full = dfixed_div(a, b);
996 line_fill_time = dfixed_trunc(a);
997
998 if (line_fill_time < wm->active_time)
999 return latency;
1000 else
1001 return latency + (line_fill_time - wm->active_time);
1002
1003}
1004
1005static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
1006{
1007 if (evergreen_average_bandwidth(wm) <=
1008 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
1009 return true;
1010 else
1011 return false;
1012};
1013
1014static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
1015{
1016 if (evergreen_average_bandwidth(wm) <=
1017 (evergreen_available_bandwidth(wm) / wm->num_heads))
1018 return true;
1019 else
1020 return false;
1021};
1022
1023static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
1024{
1025 u32 lb_partitions = wm->lb_size / wm->src_width;
1026 u32 line_time = wm->active_time + wm->blank_time;
1027 u32 latency_tolerant_lines;
1028 u32 latency_hiding;
1029 fixed20_12 a;
1030
1031 a.full = dfixed_const(1);
1032 if (wm->vsc.full > a.full)
1033 latency_tolerant_lines = 1;
1034 else {
1035 if (lb_partitions <= (wm->vtaps + 1))
1036 latency_tolerant_lines = 1;
1037 else
1038 latency_tolerant_lines = 2;
1039 }
1040
1041 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1042
1043 if (evergreen_latency_watermark(wm) <= latency_hiding)
1044 return true;
1045 else
1046 return false;
1047}
1048
1049static void evergreen_program_watermarks(struct radeon_device *rdev,
1050 struct radeon_crtc *radeon_crtc,
1051 u32 lb_size, u32 num_heads)
1052{
1053 struct drm_display_mode *mode = &radeon_crtc->base.mode;
1054 struct evergreen_wm_params wm;
1055 u32 pixel_period;
1056 u32 line_time = 0;
1057 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1058 u32 priority_a_mark = 0, priority_b_mark = 0;
1059 u32 priority_a_cnt = PRIORITY_OFF;
1060 u32 priority_b_cnt = PRIORITY_OFF;
1061 u32 pipe_offset = radeon_crtc->crtc_id * 16;
1062 u32 tmp, arb_control3;
1063 fixed20_12 a, b, c;
1064
1065 if (radeon_crtc->base.enabled && num_heads && mode) {
1066 pixel_period = 1000000 / (u32)mode->clock;
1067 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1068 priority_a_cnt = 0;
1069 priority_b_cnt = 0;
1070
1071 wm.yclk = rdev->pm.current_mclk * 10;
1072 wm.sclk = rdev->pm.current_sclk * 10;
1073 wm.disp_clk = mode->clock;
1074 wm.src_width = mode->crtc_hdisplay;
1075 wm.active_time = mode->crtc_hdisplay * pixel_period;
1076 wm.blank_time = line_time - wm.active_time;
1077 wm.interlaced = false;
1078 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1079 wm.interlaced = true;
1080 wm.vsc = radeon_crtc->vsc;
1081 wm.vtaps = 1;
1082 if (radeon_crtc->rmx_type != RMX_OFF)
1083 wm.vtaps = 2;
1084 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1085 wm.lb_size = lb_size;
1086 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1087 wm.num_heads = num_heads;
1088
1089 /* set for high clocks */
1090 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1091 /* set for low clocks */
1092 /* wm.yclk = low clk; wm.sclk = low clk */
1093 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1094
1095 /* possibly force display priority to high */
1096 /* should really do this at mode validation time... */
1097 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1098 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1099 !evergreen_check_latency_hiding(&wm) ||
1100 (rdev->disp_priority == 2)) {
92bdfd4a 1101 DRM_DEBUG_KMS("force priority to high\n");
f9d9c362
AD		 1102 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1103 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1104 }
1105
1106 a.full = dfixed_const(1000);
1107 b.full = dfixed_const(mode->clock);
1108 b.full = dfixed_div(b, a);
1109 c.full = dfixed_const(latency_watermark_a);
1110 c.full = dfixed_mul(c, b);
1111 c.full = dfixed_mul(c, radeon_crtc->hsc);
1112 c.full = dfixed_div(c, a);
1113 a.full = dfixed_const(16);
1114 c.full = dfixed_div(c, a);
1115 priority_a_mark = dfixed_trunc(c);
1116 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1117
1118 a.full = dfixed_const(1000);
1119 b.full = dfixed_const(mode->clock);
1120 b.full = dfixed_div(b, a);
1121 c.full = dfixed_const(latency_watermark_b);
1122 c.full = dfixed_mul(c, b);
1123 c.full = dfixed_mul(c, radeon_crtc->hsc);
1124 c.full = dfixed_div(c, a);
1125 a.full = dfixed_const(16);
1126 c.full = dfixed_div(c, a);
1127 priority_b_mark = dfixed_trunc(c);
1128 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1129 }
1130
1131 /* select wm A */
1132 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1133 tmp = arb_control3;
1134 tmp &= ~LATENCY_WATERMARK_MASK(3);
1135 tmp |= LATENCY_WATERMARK_MASK(1);
1136 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1137 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1138 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1139 LATENCY_HIGH_WATERMARK(line_time)));
1140 /* select wm B */
1141 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1142 tmp &= ~LATENCY_WATERMARK_MASK(3);
1143 tmp |= LATENCY_WATERMARK_MASK(2);
1144 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1145 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1146 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1147 LATENCY_HIGH_WATERMARK(line_time)));
1148 /* restore original selection */
1149 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1150
1151 /* write the priority marks */
1152 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1153 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1154
1155}
1156
377edc8b
AD		 1157/**
1158 * evergreen_bandwidth_update - update display watermarks callback.
1159 *
1160 * @rdev: radeon_device pointer
1161 *
1162 * Update the display watermarks based on the requested mode(s)
1163 * (evergreen+).
1164 */
0ca2ab52 1165void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 1166{
f9d9c362
AD		 1167 struct drm_display_mode *mode0 = NULL;
1168 struct drm_display_mode *mode1 = NULL;
1169 u32 num_heads = 0, lb_size;
1170 int i;
1171
1172 radeon_update_display_priority(rdev);
1173
1174 for (i = 0; i < rdev->num_crtc; i++) {
1175 if (rdev->mode_info.crtcs[i]->base.enabled)
1176 num_heads++;
1177 }
1178 for (i = 0; i < rdev->num_crtc; i += 2) {
1179 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1180 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1181 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1182 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1183 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1184 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1185 }
bcc1c2a1
AD		 1186}
1187
377edc8b
AD		 1188/**
1189 * evergreen_mc_wait_for_idle - wait for MC idle callback.
1190 *
1191 * @rdev: radeon_device pointer
1192 *
1193 * Wait for the MC (memory controller) to be idle.
1194 * (evergreen+).
1195 * Returns 0 if the MC is idle, -1 if not.
1196 */
b9952a8a 1197int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 1198{
1199 unsigned i;
1200 u32 tmp;
1201
1202 for (i = 0; i < rdev->usec_timeout; i++) {
1203 /* read MC_STATUS */
1204 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1205 if (!tmp)
1206 return 0;
1207 udelay(1);
1208 }
1209 return -1;
1210}
1211
1212/*
1213 * GART
1214 */
0fcdb61e
AD		 1215void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1216{
1217 unsigned i;
1218 u32 tmp;
1219
6f2f48a9
AD		 1220 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1221
0fcdb61e
AD		 1222 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1223 for (i = 0; i < rdev->usec_timeout; i++) {
1224 /* read MC_STATUS */
1225 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1226 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1227 if (tmp == 2) {
1228 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1229 return;
1230 }
1231 if (tmp) {
1232 return;
1233 }
1234 udelay(1);
1235 }
1236}
1237
1109ca09 1238static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 1239{
1240 u32 tmp;
0fcdb61e 1241 int r;
bcc1c2a1 1242
c9a1be96 1243 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 1244 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1245 return -EINVAL;
1246 }
1247 r = radeon_gart_table_vram_pin(rdev);
1248 if (r)
1249 return r;
82568565 1250 radeon_gart_restore(rdev);
bcc1c2a1
AD		 1251 /* Setup L2 cache */
1252 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1253 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1254 EFFECTIVE_L2_QUEUE_SIZE(7));
1255 WREG32(VM_L2_CNTL2, 0);
1256 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1257 /* Setup TLB control */
1258 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1259 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1260 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1261 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 1262 if (rdev->flags & RADEON_IS_IGP) {
1263 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1264 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1265 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1266 } else {
1267 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1268 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1269 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 1270 if ((rdev->family == CHIP_JUNIPER) ||
1271 (rdev->family == CHIP_CYPRESS) ||
1272 (rdev->family == CHIP_HEMLOCK) ||
1273 (rdev->family == CHIP_BARTS))
1274 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
8aeb96f8 1275 }
bcc1c2a1
AD		 1276 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1277 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1278 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1279 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1280 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1281 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1282 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1283 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1284 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1285 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1286 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 1287 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 1288
0fcdb61e 1289 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1290 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1291 (unsigned)(rdev->mc.gtt_size >> 20),
1292 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 1293 rdev->gart.ready = true;
1294 return 0;
1295}
1296
1109ca09 1297static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
bcc1c2a1
AD		 1298{
1299 u32 tmp;
bcc1c2a1
AD		 1300
1301 /* Disable all tables */
0fcdb61e
AD		 1302 WREG32(VM_CONTEXT0_CNTL, 0);
1303 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1304
1305 /* Setup L2 cache */
1306 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1307 EFFECTIVE_L2_QUEUE_SIZE(7));
1308 WREG32(VM_L2_CNTL2, 0);
1309 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1310 /* Setup TLB control */
1311 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1312 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1313 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1314 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1315 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1316 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1317 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1318 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 1319 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 1320}
1321
1109ca09 1322static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
bcc1c2a1
AD		 1323{
1324 evergreen_pcie_gart_disable(rdev);
1325 radeon_gart_table_vram_free(rdev);
1326 radeon_gart_fini(rdev);
1327}
1328
1329
1109ca09 1330static void evergreen_agp_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 1331{
1332 u32 tmp;
bcc1c2a1
AD		 1333
1334 /* Setup L2 cache */
1335 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1336 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1337 EFFECTIVE_L2_QUEUE_SIZE(7));
1338 WREG32(VM_L2_CNTL2, 0);
1339 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1340 /* Setup TLB control */
1341 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1342 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1343 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1344 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1345 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1346 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1347 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1348 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1349 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1350 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1351 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 1352 WREG32(VM_CONTEXT0_CNTL, 0);
1353 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1354}
1355
b9952a8a 1356void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 1357{
62444b74
AD		 1358 u32 crtc_enabled, tmp, frame_count, blackout;
1359 int i, j;
1360
bcc1c2a1
AD		 1361 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1362 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
bcc1c2a1 1363
62444b74 1364 /* disable VGA render */
bcc1c2a1 1365 WREG32(VGA_RENDER_CONTROL, 0);
62444b74
AD		 1366 /* blank the display controllers */
1367 for (i = 0; i < rdev->num_crtc; i++) {
1368 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1369 if (crtc_enabled) {
1370 save->crtc_enabled[i] = true;
1371 if (ASIC_IS_DCE6(rdev)) {
1372 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1373 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1374 radeon_wait_for_vblank(rdev, i);
1375 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
bb588820 1376 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1377 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
bb588820 1378 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1379 }
1380 } else {
1381 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1382 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1383 radeon_wait_for_vblank(rdev, i);
1384 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
bb588820 1385 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1386 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
bb588820 1387 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1388 }
1389 }
1390 /* wait for the next frame */
1391 frame_count = radeon_get_vblank_counter(rdev, i);
1392 for (j = 0; j < rdev->usec_timeout; j++) {
1393 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1394 break;
1395 udelay(1);
1396 }
804cc4a0
AD		 1397 } else {
1398 save->crtc_enabled[i] = false;
62444b74 1399 }
18007401 1400 }
bcc1c2a1 1401
62444b74
AD		 1402 radeon_mc_wait_for_idle(rdev);
1403
1404 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1405 if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1406 /* Block CPU access */
1407 WREG32(BIF_FB_EN, 0);
1408 /* blackout the MC */
1409 blackout &= ~BLACKOUT_MODE_MASK;
1410 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
b7eff394 1411 }
ed39fadd
AD		 1412 /* wait for the MC to settle */
1413 udelay(100);
bcc1c2a1
AD		 1414}
1415
b9952a8a 1416void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 1417{
62444b74
AD		 1418 u32 tmp, frame_count;
1419 int i, j;
18007401 1420
62444b74
AD		 1421 /* update crtc base addresses */
1422 for (i = 0; i < rdev->num_crtc; i++) {
1423 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 1424 upper_32_bits(rdev->mc.vram_start));
62444b74 1425 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 1426 upper_32_bits(rdev->mc.vram_start));
62444b74 1427 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401 1428 (u32)rdev->mc.vram_start);
62444b74 1429 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401
AD		 1430 (u32)rdev->mc.vram_start);
1431 }
bcc1c2a1
AD		 1432 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1433 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
62444b74
AD		 1434
1435 /* unblackout the MC */
1436 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1437 tmp &= ~BLACKOUT_MODE_MASK;
1438 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1439 /* allow CPU access */
1440 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1441
1442 for (i = 0; i < rdev->num_crtc; i++) {
695ddeb4 1443 if (save->crtc_enabled[i]) {
62444b74
AD		 1444 if (ASIC_IS_DCE6(rdev)) {
1445 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1446 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
bb588820 1447 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1448 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
bb588820 1449 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1450 } else {
1451 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1452 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
bb588820 1453 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1454 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
bb588820 1455 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1456 }
1457 /* wait for the next frame */
1458 frame_count = radeon_get_vblank_counter(rdev, i);
1459 for (j = 0; j < rdev->usec_timeout; j++) {
1460 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1461 break;
1462 udelay(1);
1463 }
1464 }
1465 }
1466 /* Unlock vga access */
bcc1c2a1
AD		 1467 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1468 mdelay(1);
bcc1c2a1
AD		 1469 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1470}
1471
755d819e 1472void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1473{
1474 struct evergreen_mc_save save;
1475 u32 tmp;
1476 int i, j;
1477
1478 /* Initialize HDP */
1479 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1480 WREG32((0x2c14 + j), 0x00000000);
1481 WREG32((0x2c18 + j), 0x00000000);
1482 WREG32((0x2c1c + j), 0x00000000);
1483 WREG32((0x2c20 + j), 0x00000000);
1484 WREG32((0x2c24 + j), 0x00000000);
1485 }
1486 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1487
1488 evergreen_mc_stop(rdev, &save);
1489 if (evergreen_mc_wait_for_idle(rdev)) {
1490 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1491 }
1492 /* Lockout access through VGA aperture*/
1493 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1494 /* Update configuration */
1495 if (rdev->flags & RADEON_IS_AGP) {
1496 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1497 /* VRAM before AGP */
1498 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1499 rdev->mc.vram_start >> 12);
1500 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1501 rdev->mc.gtt_end >> 12);
1502 } else {
1503 /* VRAM after AGP */
1504 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1505 rdev->mc.gtt_start >> 12);
1506 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1507 rdev->mc.vram_end >> 12);
1508 }
1509 } else {
1510 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1511 rdev->mc.vram_start >> 12);
1512 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1513 rdev->mc.vram_end >> 12);
1514 }
3b9832f6 1515 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
05b3ef69
AD		 1516 /* llano/ontario only */
1517 if ((rdev->family == CHIP_PALM) ||
1518 (rdev->family == CHIP_SUMO) ||
1519 (rdev->family == CHIP_SUMO2)) {
b4183e30
AD		 1520 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1521 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1522 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1523 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1524 }
bcc1c2a1
AD		 1525 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1526 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1527 WREG32(MC_VM_FB_LOCATION, tmp);
1528 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1529 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1530 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1531 if (rdev->flags & RADEON_IS_AGP) {
1532 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1533 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1534 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1535 } else {
1536 WREG32(MC_VM_AGP_BASE, 0);
1537 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1538 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1539 }
1540 if (evergreen_mc_wait_for_idle(rdev)) {
1541 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1542 }
1543 evergreen_mc_resume(rdev, &save);
1544 /* we need to own VRAM, so turn off the VGA renderer here
1545 * to stop it overwriting our objects */
1546 rv515_vga_render_disable(rdev);
1547}
1548
bcc1c2a1
AD		 1549/*
1550 * CP.
1551 */
12920591
AD		 1552void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1553{
876dc9f3 1554 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 1555 u32 next_rptr;
7b1f2485 1556
12920591 1557 /* set to DX10/11 mode */
e32eb50d
CK		 1558 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1559 radeon_ring_write(ring, 1);
45df6803
CK		 1560
1561 if (ring->rptr_save_reg) {
89d35807 1562 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 1563 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1564 radeon_ring_write(ring, ((ring->rptr_save_reg -
1565 PACKET3_SET_CONFIG_REG_START) >> 2));
1566 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1567 } else if (rdev->wb.enabled) {
1568 next_rptr = ring->wptr + 5 + 4;
1569 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1570 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1571 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1572 radeon_ring_write(ring, next_rptr);
1573 radeon_ring_write(ring, 0);
45df6803
CK		 1574 }
1575
e32eb50d
CK		 1576 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1577 radeon_ring_write(ring,
0f234f5f
AD		 1578#ifdef __BIG_ENDIAN
1579 (2 << 0) |
1580#endif
1581 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 1582 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1583 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 1584}
1585
bcc1c2a1
AD		 1586
1587static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1588{
fe251e2f
AD		 1589 const __be32 *fw_data;
1590 int i;
1591
1592 if (!rdev->me_fw || !rdev->pfp_fw)
1593 return -EINVAL;
bcc1c2a1 1594
fe251e2f 1595 r700_cp_stop(rdev);
0f234f5f
AD		 1596 WREG32(CP_RB_CNTL,
1597#ifdef __BIG_ENDIAN
1598 BUF_SWAP_32BIT |
1599#endif
1600 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1601
1602 fw_data = (const __be32 *)rdev->pfp_fw->data;
1603 WREG32(CP_PFP_UCODE_ADDR, 0);
1604 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1605 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1606 WREG32(CP_PFP_UCODE_ADDR, 0);
1607
1608 fw_data = (const __be32 *)rdev->me_fw->data;
1609 WREG32(CP_ME_RAM_WADDR, 0);
1610 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1611 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1612
1613 WREG32(CP_PFP_UCODE_ADDR, 0);
1614 WREG32(CP_ME_RAM_WADDR, 0);
1615 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1616 return 0;
1617}
1618
7e7b41d2
AD		 1619static int evergreen_cp_start(struct radeon_device *rdev)
1620{
e32eb50d 1621 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 1622 int r, i;
7e7b41d2
AD		 1623 uint32_t cp_me;
1624
e32eb50d 1625 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 1626 if (r) {
1627 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1628 return r;
1629 }
e32eb50d
CK		 1630 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1631 radeon_ring_write(ring, 0x1);
1632 radeon_ring_write(ring, 0x0);
1633 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1634 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1635 radeon_ring_write(ring, 0);
1636 radeon_ring_write(ring, 0);
1637 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1638
1639 cp_me = 0xff;
1640 WREG32(CP_ME_CNTL, cp_me);
1641
e32eb50d 1642 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 1643 if (r) {
1644 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1645 return r;
1646 }
2281a378
AD		 1647
1648 /* setup clear context state */
e32eb50d
CK		 1649 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1650 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 1651
1652 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 1653 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 1654
e32eb50d
CK		 1655 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1656 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 1657
1658 /* set clear context state */
e32eb50d
CK		 1659 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1660 radeon_ring_write(ring, 0);
2281a378
AD		 1661
1662 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1663 radeon_ring_write(ring, 0xc0026f00);
1664 radeon_ring_write(ring, 0x00000000);
1665 radeon_ring_write(ring, 0x00000000);
1666 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 1667
1668 /* Clear consts */
e32eb50d
CK		 1669 radeon_ring_write(ring, 0xc0036f00);
1670 radeon_ring_write(ring, 0x00000bc4);
1671 radeon_ring_write(ring, 0xffffffff);
1672 radeon_ring_write(ring, 0xffffffff);
1673 radeon_ring_write(ring, 0xffffffff);
2281a378 1674
e32eb50d
CK		 1675 radeon_ring_write(ring, 0xc0026900);
1676 radeon_ring_write(ring, 0x00000316);
1677 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1678 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 1679
e32eb50d 1680 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1681
1682 return 0;
1683}
1684
1109ca09 1685static int evergreen_cp_resume(struct radeon_device *rdev)
fe251e2f 1686{
e32eb50d 1687 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 1688 u32 tmp;
1689 u32 rb_bufsz;
1690 int r;
1691
1692 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1693 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1694 SOFT_RESET_PA |
1695 SOFT_RESET_SH |
1696 SOFT_RESET_VGT |
a49a50da 1697 SOFT_RESET_SPI |
fe251e2f
AD		 1698 SOFT_RESET_SX));
1699 RREG32(GRBM_SOFT_RESET);
1700 mdelay(15);
1701 WREG32(GRBM_SOFT_RESET, 0);
1702 RREG32(GRBM_SOFT_RESET);
1703
1704 /* Set ring buffer size */
e32eb50d 1705 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 1706 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1707#ifdef __BIG_ENDIAN
1708 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1709#endif
fe251e2f 1710 WREG32(CP_RB_CNTL, tmp);
15d3332f 1711 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1712 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 1713
1714 /* Set the write pointer delay */
1715 WREG32(CP_RB_WPTR_DELAY, 0);
1716
1717 /* Initialize the ring buffer's read and write pointers */
1718 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1719 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1720 ring->wptr = 0;
1721 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1 1722
48fc7f7e 1723 /* set the wb address whether it's enabled or not */
0f234f5f 1724 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 1725 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1726 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1727 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1728
1729 if (rdev->wb.enabled)
1730 WREG32(SCRATCH_UMSK, 0xff);
1731 else {
1732 tmp |= RB_NO_UPDATE;
1733 WREG32(SCRATCH_UMSK, 0);
1734 }
1735
fe251e2f
AD		 1736 mdelay(1);
1737 WREG32(CP_RB_CNTL, tmp);
1738
e32eb50d 1739 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 1740 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1741
e32eb50d 1742 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 1743
7e7b41d2 1744 evergreen_cp_start(rdev);
e32eb50d 1745 ring->ready = true;
f712812e 1746 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
fe251e2f 1747 if (r) {
e32eb50d 1748 ring->ready = false;
fe251e2f
AD		 1749 return r;
1750 }
1751 return 0;
1752}
bcc1c2a1
AD		 1753
1754/*
1755 * Core functions
1756 */
bcc1c2a1
AD		 1757static void evergreen_gpu_init(struct radeon_device *rdev)
1758{
416a2bd2 1759 u32 gb_addr_config;
32fcdbf4 1760 u32 mc_shared_chmap, mc_arb_ramcfg;
32fcdbf4
AD		 1761 u32 sx_debug_1;
1762 u32 smx_dc_ctl0;
1763 u32 sq_config;
1764 u32 sq_lds_resource_mgmt;
1765 u32 sq_gpr_resource_mgmt_1;
1766 u32 sq_gpr_resource_mgmt_2;
1767 u32 sq_gpr_resource_mgmt_3;
1768 u32 sq_thread_resource_mgmt;
1769 u32 sq_thread_resource_mgmt_2;
1770 u32 sq_stack_resource_mgmt_1;
1771 u32 sq_stack_resource_mgmt_2;
1772 u32 sq_stack_resource_mgmt_3;
1773 u32 vgt_cache_invalidation;
f25a5c63 1774 u32 hdp_host_path_cntl, tmp;
416a2bd2 1775 u32 disabled_rb_mask;
32fcdbf4
AD		 1776 int i, j, num_shader_engines, ps_thread_count;
1777
1778 switch (rdev->family) {
1779 case CHIP_CYPRESS:
1780 case CHIP_HEMLOCK:
1781 rdev->config.evergreen.num_ses = 2;
1782 rdev->config.evergreen.max_pipes = 4;
1783 rdev->config.evergreen.max_tile_pipes = 8;
1784 rdev->config.evergreen.max_simds = 10;
1785 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1786 rdev->config.evergreen.max_gprs = 256;
1787 rdev->config.evergreen.max_threads = 248;
1788 rdev->config.evergreen.max_gs_threads = 32;
1789 rdev->config.evergreen.max_stack_entries = 512;
1790 rdev->config.evergreen.sx_num_of_sets = 4;
1791 rdev->config.evergreen.sx_max_export_size = 256;
1792 rdev->config.evergreen.sx_max_export_pos_size = 64;
1793 rdev->config.evergreen.sx_max_export_smx_size = 192;
1794 rdev->config.evergreen.max_hw_contexts = 8;
1795 rdev->config.evergreen.sq_num_cf_insts = 2;
1796
1797 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1798 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1799 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1800 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1801 break;
1802 case CHIP_JUNIPER:
1803 rdev->config.evergreen.num_ses = 1;
1804 rdev->config.evergreen.max_pipes = 4;
1805 rdev->config.evergreen.max_tile_pipes = 4;
1806 rdev->config.evergreen.max_simds = 10;
1807 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1808 rdev->config.evergreen.max_gprs = 256;
1809 rdev->config.evergreen.max_threads = 248;
1810 rdev->config.evergreen.max_gs_threads = 32;
1811 rdev->config.evergreen.max_stack_entries = 512;
1812 rdev->config.evergreen.sx_num_of_sets = 4;
1813 rdev->config.evergreen.sx_max_export_size = 256;
1814 rdev->config.evergreen.sx_max_export_pos_size = 64;
1815 rdev->config.evergreen.sx_max_export_smx_size = 192;
1816 rdev->config.evergreen.max_hw_contexts = 8;
1817 rdev->config.evergreen.sq_num_cf_insts = 2;
1818
1819 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1820 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1821 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1822 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1823 break;
1824 case CHIP_REDWOOD:
1825 rdev->config.evergreen.num_ses = 1;
1826 rdev->config.evergreen.max_pipes = 4;
1827 rdev->config.evergreen.max_tile_pipes = 4;
1828 rdev->config.evergreen.max_simds = 5;
1829 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1830 rdev->config.evergreen.max_gprs = 256;
1831 rdev->config.evergreen.max_threads = 248;
1832 rdev->config.evergreen.max_gs_threads = 32;
1833 rdev->config.evergreen.max_stack_entries = 256;
1834 rdev->config.evergreen.sx_num_of_sets = 4;
1835 rdev->config.evergreen.sx_max_export_size = 256;
1836 rdev->config.evergreen.sx_max_export_pos_size = 64;
1837 rdev->config.evergreen.sx_max_export_smx_size = 192;
1838 rdev->config.evergreen.max_hw_contexts = 8;
1839 rdev->config.evergreen.sq_num_cf_insts = 2;
1840
1841 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1842 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1843 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1844 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1845 break;
1846 case CHIP_CEDAR:
1847 default:
1848 rdev->config.evergreen.num_ses = 1;
1849 rdev->config.evergreen.max_pipes = 2;
1850 rdev->config.evergreen.max_tile_pipes = 2;
1851 rdev->config.evergreen.max_simds = 2;
1852 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1853 rdev->config.evergreen.max_gprs = 256;
1854 rdev->config.evergreen.max_threads = 192;
1855 rdev->config.evergreen.max_gs_threads = 16;
1856 rdev->config.evergreen.max_stack_entries = 256;
1857 rdev->config.evergreen.sx_num_of_sets = 4;
1858 rdev->config.evergreen.sx_max_export_size = 128;
1859 rdev->config.evergreen.sx_max_export_pos_size = 32;
1860 rdev->config.evergreen.sx_max_export_smx_size = 96;
1861 rdev->config.evergreen.max_hw_contexts = 4;
1862 rdev->config.evergreen.sq_num_cf_insts = 1;
1863
d5e455e4
AD		 1864 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1865 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1866 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1867 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5e455e4
AD		 1868 break;
1869 case CHIP_PALM:
1870 rdev->config.evergreen.num_ses = 1;
1871 rdev->config.evergreen.max_pipes = 2;
1872 rdev->config.evergreen.max_tile_pipes = 2;
1873 rdev->config.evergreen.max_simds = 2;
1874 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1875 rdev->config.evergreen.max_gprs = 256;
1876 rdev->config.evergreen.max_threads = 192;
1877 rdev->config.evergreen.max_gs_threads = 16;
1878 rdev->config.evergreen.max_stack_entries = 256;
1879 rdev->config.evergreen.sx_num_of_sets = 4;
1880 rdev->config.evergreen.sx_max_export_size = 128;
1881 rdev->config.evergreen.sx_max_export_pos_size = 32;
1882 rdev->config.evergreen.sx_max_export_smx_size = 96;
1883 rdev->config.evergreen.max_hw_contexts = 4;
1884 rdev->config.evergreen.sq_num_cf_insts = 1;
1885
d5c5a72f
AD		 1886 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1887 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1888 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1889 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 1890 break;
1891 case CHIP_SUMO:
1892 rdev->config.evergreen.num_ses = 1;
1893 rdev->config.evergreen.max_pipes = 4;
bd25f078 1894 rdev->config.evergreen.max_tile_pipes = 4;
d5c5a72f
AD		 1895 if (rdev->pdev->device == 0x9648)
1896 rdev->config.evergreen.max_simds = 3;
1897 else if ((rdev->pdev->device == 0x9647) ||
1898 (rdev->pdev->device == 0x964a))
1899 rdev->config.evergreen.max_simds = 4;
1900 else
1901 rdev->config.evergreen.max_simds = 5;
1902 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1903 rdev->config.evergreen.max_gprs = 256;
1904 rdev->config.evergreen.max_threads = 248;
1905 rdev->config.evergreen.max_gs_threads = 32;
1906 rdev->config.evergreen.max_stack_entries = 256;
1907 rdev->config.evergreen.sx_num_of_sets = 4;
1908 rdev->config.evergreen.sx_max_export_size = 256;
1909 rdev->config.evergreen.sx_max_export_pos_size = 64;
1910 rdev->config.evergreen.sx_max_export_smx_size = 192;
1911 rdev->config.evergreen.max_hw_contexts = 8;
1912 rdev->config.evergreen.sq_num_cf_insts = 2;
1913
1914 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1915 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1916 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 1917 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 1918 break;
1919 case CHIP_SUMO2:
1920 rdev->config.evergreen.num_ses = 1;
1921 rdev->config.evergreen.max_pipes = 4;
1922 rdev->config.evergreen.max_tile_pipes = 4;
1923 rdev->config.evergreen.max_simds = 2;
1924 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1925 rdev->config.evergreen.max_gprs = 256;
1926 rdev->config.evergreen.max_threads = 248;
1927 rdev->config.evergreen.max_gs_threads = 32;
1928 rdev->config.evergreen.max_stack_entries = 512;
1929 rdev->config.evergreen.sx_num_of_sets = 4;
1930 rdev->config.evergreen.sx_max_export_size = 256;
1931 rdev->config.evergreen.sx_max_export_pos_size = 64;
1932 rdev->config.evergreen.sx_max_export_smx_size = 192;
1933 rdev->config.evergreen.max_hw_contexts = 8;
1934 rdev->config.evergreen.sq_num_cf_insts = 2;
1935
adb68fa2
AD		 1936 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1937 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1938 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 1939 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1940 break;
1941 case CHIP_BARTS:
1942 rdev->config.evergreen.num_ses = 2;
1943 rdev->config.evergreen.max_pipes = 4;
1944 rdev->config.evergreen.max_tile_pipes = 8;
1945 rdev->config.evergreen.max_simds = 7;
1946 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1947 rdev->config.evergreen.max_gprs = 256;
1948 rdev->config.evergreen.max_threads = 248;
1949 rdev->config.evergreen.max_gs_threads = 32;
1950 rdev->config.evergreen.max_stack_entries = 512;
1951 rdev->config.evergreen.sx_num_of_sets = 4;
1952 rdev->config.evergreen.sx_max_export_size = 256;
1953 rdev->config.evergreen.sx_max_export_pos_size = 64;
1954 rdev->config.evergreen.sx_max_export_smx_size = 192;
1955 rdev->config.evergreen.max_hw_contexts = 8;
1956 rdev->config.evergreen.sq_num_cf_insts = 2;
1957
1958 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1959 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1960 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1961 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1962 break;
1963 case CHIP_TURKS:
1964 rdev->config.evergreen.num_ses = 1;
1965 rdev->config.evergreen.max_pipes = 4;
1966 rdev->config.evergreen.max_tile_pipes = 4;
1967 rdev->config.evergreen.max_simds = 6;
1968 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1969 rdev->config.evergreen.max_gprs = 256;
1970 rdev->config.evergreen.max_threads = 248;
1971 rdev->config.evergreen.max_gs_threads = 32;
1972 rdev->config.evergreen.max_stack_entries = 256;
1973 rdev->config.evergreen.sx_num_of_sets = 4;
1974 rdev->config.evergreen.sx_max_export_size = 256;
1975 rdev->config.evergreen.sx_max_export_pos_size = 64;
1976 rdev->config.evergreen.sx_max_export_smx_size = 192;
1977 rdev->config.evergreen.max_hw_contexts = 8;
1978 rdev->config.evergreen.sq_num_cf_insts = 2;
1979
1980 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1981 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1982 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1983 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1984 break;
1985 case CHIP_CAICOS:
1986 rdev->config.evergreen.num_ses = 1;
bd25f078 1987 rdev->config.evergreen.max_pipes = 2;
adb68fa2
AD		 1988 rdev->config.evergreen.max_tile_pipes = 2;
1989 rdev->config.evergreen.max_simds = 2;
1990 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1991 rdev->config.evergreen.max_gprs = 256;
1992 rdev->config.evergreen.max_threads = 192;
1993 rdev->config.evergreen.max_gs_threads = 16;
1994 rdev->config.evergreen.max_stack_entries = 256;
1995 rdev->config.evergreen.sx_num_of_sets = 4;
1996 rdev->config.evergreen.sx_max_export_size = 128;
1997 rdev->config.evergreen.sx_max_export_pos_size = 32;
1998 rdev->config.evergreen.sx_max_export_smx_size = 96;
1999 rdev->config.evergreen.max_hw_contexts = 4;
2000 rdev->config.evergreen.sq_num_cf_insts = 1;
2001
32fcdbf4
AD		 2002 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
2003 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2004 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2005 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 2006 break;
2007 }
2008
2009 /* Initialize HDP */
2010 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2011 WREG32((0x2c14 + j), 0x00000000);
2012 WREG32((0x2c18 + j), 0x00000000);
2013 WREG32((0x2c1c + j), 0x00000000);
2014 WREG32((0x2c20 + j), 0x00000000);
2015 WREG32((0x2c24 + j), 0x00000000);
2016 }
2017
2018 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2019
d054ac16
AD		 2020 evergreen_fix_pci_max_read_req_size(rdev);
2021
32fcdbf4 2022 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
05b3ef69
AD		 2023 if ((rdev->family == CHIP_PALM) ||
2024 (rdev->family == CHIP_SUMO) ||
2025 (rdev->family == CHIP_SUMO2))
d9282fca
AD		 2026 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
2027 else
2028 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4 2029
1aa52bd3
AD		 2030 /* setup tiling info dword. gb_addr_config is not adequate since it does
2031 * not have bank info, so create a custom tiling dword.
2032 * bits 3:0 num_pipes
2033 * bits 7:4 num_banks
2034 * bits 11:8 group_size
2035 * bits 15:12 row_size
2036 */
2037 rdev->config.evergreen.tile_config = 0;
2038 switch (rdev->config.evergreen.max_tile_pipes) {
2039 case 1:
2040 default:
2041 rdev->config.evergreen.tile_config |= (0 << 0);
2042 break;
2043 case 2:
2044 rdev->config.evergreen.tile_config |= (1 << 0);
2045 break;
2046 case 4:
2047 rdev->config.evergreen.tile_config |= (2 << 0);
2048 break;
2049 case 8:
2050 rdev->config.evergreen.tile_config |= (3 << 0);
2051 break;
2052 }
d698a34d 2053 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 2054 if (rdev->flags & RADEON_IS_IGP)
d698a34d 2055 rdev->config.evergreen.tile_config |= 1 << 4;
29d65406 2056 else {
c8d15edc
AD		 2057 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
2058 case 0: /* four banks */
29d65406 2059 rdev->config.evergreen.tile_config |= 0 << 4;
c8d15edc
AD		 2060 break;
2061 case 1: /* eight banks */
2062 rdev->config.evergreen.tile_config |= 1 << 4;
2063 break;
2064 case 2: /* sixteen banks */
2065 default:
2066 rdev->config.evergreen.tile_config |= 2 << 4;
2067 break;
2068 }
29d65406 2069 }
416a2bd2 2070 rdev->config.evergreen.tile_config |= 0 << 8;
1aa52bd3
AD		 2071 rdev->config.evergreen.tile_config |=
2072 ((gb_addr_config & 0x30000000) >> 28) << 12;
2073
416a2bd2 2074 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
32fcdbf4 2075
416a2bd2
AD		 2076 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
2077 u32 efuse_straps_4;
2078 u32 efuse_straps_3;
32fcdbf4 2079
416a2bd2
AD		 2080 WREG32(RCU_IND_INDEX, 0x204);
2081 efuse_straps_4 = RREG32(RCU_IND_DATA);
2082 WREG32(RCU_IND_INDEX, 0x203);
2083 efuse_straps_3 = RREG32(RCU_IND_DATA);
2084 tmp = (((efuse_straps_4 & 0xf) << 4) |
2085 ((efuse_straps_3 & 0xf0000000) >> 28));
2086 } else {
2087 tmp = 0;
2088 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2089 u32 rb_disable_bitmap;
2090
2091 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2092 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2093 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2094 tmp <<= 4;
2095 tmp |= rb_disable_bitmap;
32fcdbf4 2096 }
416a2bd2
AD		 2097 }
2098 /* enabled rb are just the one not disabled :) */
2099 disabled_rb_mask = tmp;
32fcdbf4 2100
416a2bd2
AD		 2101 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2102 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
32fcdbf4 2103
416a2bd2
AD		 2104 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2105 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2106 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
233d1ad5 2107 WREG32(DMA_TILING_CONFIG, gb_addr_config);
32fcdbf4 2108
f7eb9730
AD		 2109 if ((rdev->config.evergreen.max_backends == 1) &&
2110 (rdev->flags & RADEON_IS_IGP)) {
2111 if ((disabled_rb_mask & 3) == 1) {
2112 /* RB0 disabled, RB1 enabled */
2113 tmp = 0x11111111;
2114 } else {
2115 /* RB1 disabled, RB0 enabled */
2116 tmp = 0x00000000;
2117 }
2118 } else {
2119 tmp = gb_addr_config & NUM_PIPES_MASK;
2120 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2121 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2122 }
416a2bd2 2123 WREG32(GB_BACKEND_MAP, tmp);
32fcdbf4
AD		 2124
2125 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2126 WREG32(CGTS_TCC_DISABLE, 0);
2127 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2128 WREG32(CGTS_USER_TCC_DISABLE, 0);
2129
2130 /* set HW defaults for 3D engine */
2131 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2132 ROQ_IB2_START(0x2b)));
2133
2134 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2135
2136 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2137 SYNC_GRADIENT |
2138 SYNC_WALKER |
2139 SYNC_ALIGNER));
2140
2141 sx_debug_1 = RREG32(SX_DEBUG_1);
2142 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2143 WREG32(SX_DEBUG_1, sx_debug_1);
2144
2145
2146 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2147 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2148 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2149 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2150
b866d133
AD		 2151 if (rdev->family <= CHIP_SUMO2)
2152 WREG32(SMX_SAR_CTL0, 0x00010000);
2153
32fcdbf4
AD		 2154 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2155 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2156 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2157
2158 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2159 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2160 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2161
2162 WREG32(VGT_NUM_INSTANCES, 1);
2163 WREG32(SPI_CONFIG_CNTL, 0);
2164 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2165 WREG32(CP_PERFMON_CNTL, 0);
2166
2167 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2168 FETCH_FIFO_HIWATER(0x4) |
2169 DONE_FIFO_HIWATER(0xe0) |
2170 ALU_UPDATE_FIFO_HIWATER(0x8)));
2171
2172 sq_config = RREG32(SQ_CONFIG);
2173 sq_config &= ~(PS_PRIO(3) |
2174 VS_PRIO(3) |
2175 GS_PRIO(3) |
2176 ES_PRIO(3));
2177 sq_config |= (VC_ENABLE |
2178 EXPORT_SRC_C |
2179 PS_PRIO(0) |
2180 VS_PRIO(1) |
2181 GS_PRIO(2) |
2182 ES_PRIO(3));
2183
d5e455e4
AD		 2184 switch (rdev->family) {
2185 case CHIP_CEDAR:
2186 case CHIP_PALM:
d5c5a72f
AD		 2187 case CHIP_SUMO:
2188 case CHIP_SUMO2:
adb68fa2 2189 case CHIP_CAICOS:
32fcdbf4
AD		 2190 /* no vertex cache */
2191 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 2192 break;
2193 default:
2194 break;
2195 }
32fcdbf4
AD		 2196
2197 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2198
2199 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2200 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2201 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2202 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2203 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2204 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2205 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2206
d5e455e4
AD		 2207 switch (rdev->family) {
2208 case CHIP_CEDAR:
2209 case CHIP_PALM:
d5c5a72f
AD		 2210 case CHIP_SUMO:
2211 case CHIP_SUMO2:
32fcdbf4 2212 ps_thread_count = 96;
d5e455e4
AD		 2213 break;
2214 default:
32fcdbf4 2215 ps_thread_count = 128;
d5e455e4
AD		 2216 break;
2217 }
32fcdbf4
AD		 2218
2219 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2220 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2221 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2222 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2223 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2224 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2225
2226 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2227 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2228 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2229 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2230 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2231 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2232
2233 WREG32(SQ_CONFIG, sq_config);
2234 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2235 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2236 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2237 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2238 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2239 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2240 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2241 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2242 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2243 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2244
2245 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2246 FORCE_EOV_MAX_REZ_CNT(255)));
2247
d5e455e4
AD		 2248 switch (rdev->family) {
2249 case CHIP_CEDAR:
2250 case CHIP_PALM:
d5c5a72f
AD		 2251 case CHIP_SUMO:
2252 case CHIP_SUMO2:
adb68fa2 2253 case CHIP_CAICOS:
32fcdbf4 2254 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2255 break;
2256 default:
32fcdbf4 2257 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2258 break;
2259 }
32fcdbf4
AD		 2260 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2261 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2262
2263 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2264 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2265 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2266
60a4a3e0
AD		 2267 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2268 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2269
32fcdbf4
AD		 2270 WREG32(CB_PERF_CTR0_SEL_0, 0);
2271 WREG32(CB_PERF_CTR0_SEL_1, 0);
2272 WREG32(CB_PERF_CTR1_SEL_0, 0);
2273 WREG32(CB_PERF_CTR1_SEL_1, 0);
2274 WREG32(CB_PERF_CTR2_SEL_0, 0);
2275 WREG32(CB_PERF_CTR2_SEL_1, 0);
2276 WREG32(CB_PERF_CTR3_SEL_0, 0);
2277 WREG32(CB_PERF_CTR3_SEL_1, 0);
2278
60a4a3e0
AD		 2279 /* clear render buffer base addresses */
2280 WREG32(CB_COLOR0_BASE, 0);
2281 WREG32(CB_COLOR1_BASE, 0);
2282 WREG32(CB_COLOR2_BASE, 0);
2283 WREG32(CB_COLOR3_BASE, 0);
2284 WREG32(CB_COLOR4_BASE, 0);
2285 WREG32(CB_COLOR5_BASE, 0);
2286 WREG32(CB_COLOR6_BASE, 0);
2287 WREG32(CB_COLOR7_BASE, 0);
2288 WREG32(CB_COLOR8_BASE, 0);
2289 WREG32(CB_COLOR9_BASE, 0);
2290 WREG32(CB_COLOR10_BASE, 0);
2291 WREG32(CB_COLOR11_BASE, 0);
2292
2293 /* set the shader const cache sizes to 0 */
2294 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2295 WREG32(i, 0);
2296 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2297 WREG32(i, 0);
2298
f25a5c63
AD		 2299 tmp = RREG32(HDP_MISC_CNTL);
2300 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2301 WREG32(HDP_MISC_CNTL, tmp);
2302
32fcdbf4
AD		 2303 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2304 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2305
2306 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2307
2308 udelay(50);
2309
bcc1c2a1
AD		 2310}
2311
2312int evergreen_mc_init(struct radeon_device *rdev)
2313{
bcc1c2a1
AD		 2314 u32 tmp;
2315 int chansize, numchan;
bcc1c2a1
AD		 2316
2317 /* Get VRAM informations */
2318 rdev->mc.vram_is_ddr = true;
05b3ef69
AD		 2319 if ((rdev->family == CHIP_PALM) ||
2320 (rdev->family == CHIP_SUMO) ||
2321 (rdev->family == CHIP_SUMO2))
8208441b
AD		 2322 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2323 else
2324 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 2325 if (tmp & CHANSIZE_OVERRIDE) {
2326 chansize = 16;
2327 } else if (tmp & CHANSIZE_MASK) {
2328 chansize = 64;
2329 } else {
2330 chansize = 32;
2331 }
2332 tmp = RREG32(MC_SHARED_CHMAP);
2333 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2334 case 0:
2335 default:
2336 numchan = 1;
2337 break;
2338 case 1:
2339 numchan = 2;
2340 break;
2341 case 2:
2342 numchan = 4;
2343 break;
2344 case 3:
2345 numchan = 8;
2346 break;
2347 }
2348 rdev->mc.vram_width = numchan * chansize;
2349 /* Could aper size report 0 ? */
01d73a69
JC		 2350 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2351 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2352 /* Setup GPU memory space */
05b3ef69
AD		 2353 if ((rdev->family == CHIP_PALM) ||
2354 (rdev->family == CHIP_SUMO) ||
2355 (rdev->family == CHIP_SUMO2)) {
6eb18f8b
AD		 2356 /* size in bytes on fusion */
2357 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2358 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2359 } else {
05b3ef69 2360 /* size in MB on evergreen/cayman/tn */
6eb18f8b
AD		 2361 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2362 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2363 }
51e5fcd3 2364 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2365 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2366 radeon_update_bandwidth_info(rdev);
2367
bcc1c2a1
AD		 2368 return 0;
2369}
d594e46a 2370
187e3593 2371void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
bcc1c2a1 2372{
64c56e8c 2373 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
747943ea 2374 RREG32(GRBM_STATUS));
64c56e8c 2375 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
747943ea 2376 RREG32(GRBM_STATUS_SE0));
64c56e8c 2377 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
747943ea 2378 RREG32(GRBM_STATUS_SE1));
64c56e8c 2379 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
747943ea 2380 RREG32(SRBM_STATUS));
a65a4369
AD		 2381 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",
2382 RREG32(SRBM_STATUS2));
440a7cd8
JG		 2383 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2384 RREG32(CP_STALLED_STAT1));
2385 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2386 RREG32(CP_STALLED_STAT2));
2387 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2388 RREG32(CP_BUSY_STAT));
2389 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2390 RREG32(CP_STAT));
eaaa6983
JG		 2391 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2392 RREG32(DMA_STATUS_REG));
168757ea
AD		 2393 if (rdev->family >= CHIP_CAYMAN) {
2394 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
2395 RREG32(DMA_STATUS_REG + 0x800));
2396 }
0ecebb9e
AD		 2397}
2398
168757ea 2399bool evergreen_is_display_hung(struct radeon_device *rdev)
0ecebb9e 2400{
a65a4369
AD		 2401 u32 crtc_hung = 0;
2402 u32 crtc_status[6];
2403 u32 i, j, tmp;
2404
2405 for (i = 0; i < rdev->num_crtc; i++) {
2406 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
2407 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2408 crtc_hung |= (1 << i);
2409 }
2410 }
2411
2412 for (j = 0; j < 10; j++) {
2413 for (i = 0; i < rdev->num_crtc; i++) {
2414 if (crtc_hung & (1 << i)) {
2415 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2416 if (tmp != crtc_status[i])
2417 crtc_hung &= ~(1 << i);
2418 }
2419 }
2420 if (crtc_hung == 0)
2421 return false;
2422 udelay(100);
2423 }
2424
2425 return true;
2426}
2427
2428static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
2429{
2430 u32 reset_mask = 0;
b7630473 2431 u32 tmp;
0ecebb9e 2432
a65a4369
AD		 2433 /* GRBM_STATUS */
2434 tmp = RREG32(GRBM_STATUS);
2435 if (tmp & (PA_BUSY | SC_BUSY |
2436 SH_BUSY | SX_BUSY |
2437 TA_BUSY | VGT_BUSY |
2438 DB_BUSY | CB_BUSY |
2439 SPI_BUSY | VGT_BUSY_NO_DMA))
2440 reset_mask |= RADEON_RESET_GFX;
2441
2442 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2443 CP_BUSY | CP_COHERENCY_BUSY))
2444 reset_mask |= RADEON_RESET_CP;
2445
2446 if (tmp & GRBM_EE_BUSY)
2447 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
19fc42ed 2448
a65a4369
AD		 2449 /* DMA_STATUS_REG */
2450 tmp = RREG32(DMA_STATUS_REG);
2451 if (!(tmp & DMA_IDLE))
2452 reset_mask |= RADEON_RESET_DMA;
2453
2454 /* SRBM_STATUS2 */
2455 tmp = RREG32(SRBM_STATUS2);
2456 if (tmp & DMA_BUSY)
2457 reset_mask |= RADEON_RESET_DMA;
2458
2459 /* SRBM_STATUS */
2460 tmp = RREG32(SRBM_STATUS);
2461 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2462 reset_mask |= RADEON_RESET_RLC;
2463
2464 if (tmp & IH_BUSY)
2465 reset_mask |= RADEON_RESET_IH;
2466
2467 if (tmp & SEM_BUSY)
2468 reset_mask |= RADEON_RESET_SEM;
2469
2470 if (tmp & GRBM_RQ_PENDING)
2471 reset_mask |= RADEON_RESET_GRBM;
2472
2473 if (tmp & VMC_BUSY)
2474 reset_mask |= RADEON_RESET_VMC;
2475
2476 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2477 MCC_BUSY | MCD_BUSY))
2478 reset_mask |= RADEON_RESET_MC;
2479
2480 if (evergreen_is_display_hung(rdev))
2481 reset_mask |= RADEON_RESET_DISPLAY;
2482
2483 /* VM_L2_STATUS */
2484 tmp = RREG32(VM_L2_STATUS);
2485 if (tmp & L2_BUSY)
2486 reset_mask |= RADEON_RESET_VMC;
2487
d808fc88
AD		 2488 /* Skip MC reset as it's mostly likely not hung, just busy */
2489 if (reset_mask & RADEON_RESET_MC) {
2490 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
2491 reset_mask &= ~RADEON_RESET_MC;
2492 }
2493
a65a4369
AD		 2494 return reset_mask;
2495}
2496
2497static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2498{
2499 struct evergreen_mc_save save;
2500 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2501 u32 tmp;
19fc42ed 2502
0ecebb9e 2503 if (reset_mask == 0)
a65a4369 2504 return;
0ecebb9e
AD		 2505
2506 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2507
b7630473
AD		 2508 evergreen_print_gpu_status_regs(rdev);
2509
b7630473
AD		 2510 /* Disable CP parsing/prefetching */
2511 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2512
2513 if (reset_mask & RADEON_RESET_DMA) {
2514 /* Disable DMA */
2515 tmp = RREG32(DMA_RB_CNTL);
2516 tmp &= ~DMA_RB_ENABLE;
2517 WREG32(DMA_RB_CNTL, tmp);
2518 }
2519
b21b6e7a
AD		 2520 udelay(50);
2521
2522 evergreen_mc_stop(rdev, &save);
2523 if (evergreen_mc_wait_for_idle(rdev)) {
2524 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2525 }
2526
b7630473
AD		 2527 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
2528 grbm_soft_reset |= SOFT_RESET_DB |
2529 SOFT_RESET_CB |
2530 SOFT_RESET_PA |
2531 SOFT_RESET_SC |
2532 SOFT_RESET_SPI |
2533 SOFT_RESET_SX |
2534 SOFT_RESET_SH |
2535 SOFT_RESET_TC |
2536 SOFT_RESET_TA |
2537 SOFT_RESET_VC |
2538 SOFT_RESET_VGT;
2539 }
2540
2541 if (reset_mask & RADEON_RESET_CP) {
2542 grbm_soft_reset |= SOFT_RESET_CP |
2543 SOFT_RESET_VGT;
2544
2545 srbm_soft_reset |= SOFT_RESET_GRBM;
2546 }
0ecebb9e
AD		 2547
2548 if (reset_mask & RADEON_RESET_DMA)
b7630473
AD		 2549 srbm_soft_reset |= SOFT_RESET_DMA;
2550
a65a4369
AD		 2551 if (reset_mask & RADEON_RESET_DISPLAY)
2552 srbm_soft_reset |= SOFT_RESET_DC;
2553
2554 if (reset_mask & RADEON_RESET_RLC)
2555 srbm_soft_reset |= SOFT_RESET_RLC;
2556
2557 if (reset_mask & RADEON_RESET_SEM)
2558 srbm_soft_reset |= SOFT_RESET_SEM;
2559
2560 if (reset_mask & RADEON_RESET_IH)
2561 srbm_soft_reset |= SOFT_RESET_IH;
2562
2563 if (reset_mask & RADEON_RESET_GRBM)
2564 srbm_soft_reset |= SOFT_RESET_GRBM;
2565
2566 if (reset_mask & RADEON_RESET_VMC)
2567 srbm_soft_reset |= SOFT_RESET_VMC;
2568
24178ec4
AD		 2569 if (!(rdev->flags & RADEON_IS_IGP)) {
2570 if (reset_mask & RADEON_RESET_MC)
2571 srbm_soft_reset |= SOFT_RESET_MC;
2572 }
a65a4369 2573
b7630473
AD		 2574 if (grbm_soft_reset) {
2575 tmp = RREG32(GRBM_SOFT_RESET);
2576 tmp |= grbm_soft_reset;
2577 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2578 WREG32(GRBM_SOFT_RESET, tmp);
2579 tmp = RREG32(GRBM_SOFT_RESET);
2580
2581 udelay(50);
2582
2583 tmp &= ~grbm_soft_reset;
2584 WREG32(GRBM_SOFT_RESET, tmp);
2585 tmp = RREG32(GRBM_SOFT_RESET);
2586 }
2587
2588 if (srbm_soft_reset) {
2589 tmp = RREG32(SRBM_SOFT_RESET);
2590 tmp |= srbm_soft_reset;
2591 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2592 WREG32(SRBM_SOFT_RESET, tmp);
2593 tmp = RREG32(SRBM_SOFT_RESET);
2594
2595 udelay(50);
2596
2597 tmp &= ~srbm_soft_reset;
2598 WREG32(SRBM_SOFT_RESET, tmp);
2599 tmp = RREG32(SRBM_SOFT_RESET);
2600 }
0ecebb9e
AD		 2601
2602 /* Wait a little for things to settle down */
2603 udelay(50);
2604
747943ea 2605 evergreen_mc_resume(rdev, &save);
b7630473
AD		 2606 udelay(50);
2607
b7630473 2608 evergreen_print_gpu_status_regs(rdev);
bcc1c2a1
AD		 2609}
2610
a2d07b74 2611int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2612{
a65a4369
AD		 2613 u32 reset_mask;
2614
2615 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2616
2617 if (reset_mask)
2618 r600_set_bios_scratch_engine_hung(rdev, true);
2619
2620 evergreen_gpu_soft_reset(rdev, reset_mask);
2621
2622 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2623
2624 if (!reset_mask)
2625 r600_set_bios_scratch_engine_hung(rdev, false);
2626
2627 return 0;
747943ea
AD		 2628}
2629
123bc183
AD		 2630/**
2631 * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
2632 *
2633 * @rdev: radeon_device pointer
2634 * @ring: radeon_ring structure holding ring information
2635 *
2636 * Check if the GFX engine is locked up.
2637 * Returns true if the engine appears to be locked up, false if not.
2638 */
2639bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2640{
2641 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2642
2643 if (!(reset_mask & (RADEON_RESET_GFX |
2644 RADEON_RESET_COMPUTE |
2645 RADEON_RESET_CP))) {
2646 radeon_ring_lockup_update(ring);
2647 return false;
2648 }
2649 /* force CP activities */
2650 radeon_ring_force_activity(rdev, ring);
2651 return radeon_ring_test_lockup(rdev, ring);
2652}
2653
2654/**
2655 * evergreen_dma_is_lockup - Check if the DMA engine is locked up
2656 *
2657 * @rdev: radeon_device pointer
2658 * @ring: radeon_ring structure holding ring information
2659 *
2660 * Check if the async DMA engine is locked up.
2661 * Returns true if the engine appears to be locked up, false if not.
2662 */
2663bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2664{
2665 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2666
2667 if (!(reset_mask & RADEON_RESET_DMA)) {
2668 radeon_ring_lockup_update(ring);
2669 return false;
2670 }
2671 /* force ring activities */
2672 radeon_ring_force_activity(rdev, ring);
2673 return radeon_ring_test_lockup(rdev, ring);
2674}
2675
45f9a39b
AD		 2676/* Interrupts */
2677
2678u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2679{
46437057 2680 if (crtc >= rdev->num_crtc)
45f9a39b 2681 return 0;
46437057
AD		 2682 else
2683 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
45f9a39b
AD		 2684}
2685
2686void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2687{
2688 u32 tmp;
2689
1b37078b
AD		 2690 if (rdev->family >= CHIP_CAYMAN) {
2691 cayman_cp_int_cntl_setup(rdev, 0,
2692 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2693 cayman_cp_int_cntl_setup(rdev, 1, 0);
2694 cayman_cp_int_cntl_setup(rdev, 2, 0);
f60cbd11
AD		 2695 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2696 WREG32(CAYMAN_DMA1_CNTL, tmp);
1b37078b
AD		 2697 } else
2698 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
233d1ad5
AD		 2699 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2700 WREG32(DMA_CNTL, tmp);
45f9a39b
AD		 2701 WREG32(GRBM_INT_CNTL, 0);
2702 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2703 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2704 if (rdev->num_crtc >= 4) {
18007401
AD		 2705 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2706 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2707 }
2708 if (rdev->num_crtc >= 6) {
18007401
AD		 2709 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2710 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2711 }
45f9a39b
AD		 2712
2713 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2714 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2715 if (rdev->num_crtc >= 4) {
18007401
AD		 2716 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2717 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2718 }
2719 if (rdev->num_crtc >= 6) {
18007401
AD		 2720 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2721 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2722 }
45f9a39b 2723
05b3ef69
AD		 2724 /* only one DAC on DCE6 */
2725 if (!ASIC_IS_DCE6(rdev))
2726 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
45f9a39b
AD		 2727 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2728
2729 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2730 WREG32(DC_HPD1_INT_CONTROL, tmp);
2731 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2732 WREG32(DC_HPD2_INT_CONTROL, tmp);
2733 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2734 WREG32(DC_HPD3_INT_CONTROL, tmp);
2735 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2736 WREG32(DC_HPD4_INT_CONTROL, tmp);
2737 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2738 WREG32(DC_HPD5_INT_CONTROL, tmp);
2739 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2740 WREG32(DC_HPD6_INT_CONTROL, tmp);
2741
2742}
2743
2744int evergreen_irq_set(struct radeon_device *rdev)
2745{
2746 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 2747 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 2748 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2749 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2750 u32 grbm_int_cntl = 0;
6f34be50 2751 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
f122c610 2752 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
f60cbd11 2753 u32 dma_cntl, dma_cntl1 = 0;
45f9a39b
AD		 2754
2755 if (!rdev->irq.installed) {
fce7d61b 2756 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2757 return -EINVAL;
2758 }
2759 /* don't enable anything if the ih is disabled */
2760 if (!rdev->ih.enabled) {
2761 r600_disable_interrupts(rdev);
2762 /* force the active interrupt state to all disabled */
2763 evergreen_disable_interrupt_state(rdev);
2764 return 0;
2765 }
2766
2767 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2768 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2769 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2770 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2771 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2772 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2773
f122c610
AD		 2774 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2775 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2776 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2777 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2778 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2779 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2780
233d1ad5
AD		 2781 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2782
1b37078b
AD		 2783 if (rdev->family >= CHIP_CAYMAN) {
2784 /* enable CP interrupts on all rings */
736fc37f 2785 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2786 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2787 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2788 }
736fc37f 2789 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
1b37078b
AD		 2790 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2791 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2792 }
736fc37f 2793 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
1b37078b
AD		 2794 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2795 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2796 }
2797 } else {
736fc37f 2798 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2799 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2800 cp_int_cntl |= RB_INT_ENABLE;
2801 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2802 }
45f9a39b 2803 }
1b37078b 2804
233d1ad5
AD		 2805 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
2806 DRM_DEBUG("r600_irq_set: sw int dma\n");
2807 dma_cntl |= TRAP_ENABLE;
2808 }
2809
f60cbd11
AD		 2810 if (rdev->family >= CHIP_CAYMAN) {
2811 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2812 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
2813 DRM_DEBUG("r600_irq_set: sw int dma1\n");
2814 dma_cntl1 |= TRAP_ENABLE;
2815 }
2816 }
2817
6f34be50 2818 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 2819 atomic_read(&rdev->irq.pflip[0])) {
45f9a39b
AD		 2820 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2821 crtc1 |= VBLANK_INT_MASK;
2822 }
6f34be50 2823 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 2824 atomic_read(&rdev->irq.pflip[1])) {
45f9a39b
AD		 2825 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2826 crtc2 |= VBLANK_INT_MASK;
2827 }
6f34be50 2828 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 2829 atomic_read(&rdev->irq.pflip[2])) {
45f9a39b
AD		 2830 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2831 crtc3 |= VBLANK_INT_MASK;
2832 }
6f34be50 2833 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 2834 atomic_read(&rdev->irq.pflip[3])) {
45f9a39b
AD		 2835 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2836 crtc4 |= VBLANK_INT_MASK;
2837 }
6f34be50 2838 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 2839 atomic_read(&rdev->irq.pflip[4])) {
45f9a39b
AD		 2840 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2841 crtc5 |= VBLANK_INT_MASK;
2842 }
6f34be50 2843 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 2844 atomic_read(&rdev->irq.pflip[5])) {
45f9a39b
AD		 2845 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2846 crtc6 |= VBLANK_INT_MASK;
2847 }
2848 if (rdev->irq.hpd[0]) {
2849 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2850 hpd1 |= DC_HPDx_INT_EN;
2851 }
2852 if (rdev->irq.hpd[1]) {
2853 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2854 hpd2 |= DC_HPDx_INT_EN;
2855 }
2856 if (rdev->irq.hpd[2]) {
2857 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2858 hpd3 |= DC_HPDx_INT_EN;
2859 }
2860 if (rdev->irq.hpd[3]) {
2861 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2862 hpd4 |= DC_HPDx_INT_EN;
2863 }
2864 if (rdev->irq.hpd[4]) {
2865 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2866 hpd5 |= DC_HPDx_INT_EN;
2867 }
2868 if (rdev->irq.hpd[5]) {
2869 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2870 hpd6 |= DC_HPDx_INT_EN;
2871 }
f122c610
AD		 2872 if (rdev->irq.afmt[0]) {
2873 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2874 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2875 }
2876 if (rdev->irq.afmt[1]) {
2877 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2878 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2879 }
2880 if (rdev->irq.afmt[2]) {
2881 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2882 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2883 }
2884 if (rdev->irq.afmt[3]) {
2885 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2886 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2887 }
2888 if (rdev->irq.afmt[4]) {
2889 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2890 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2891 }
2892 if (rdev->irq.afmt[5]) {
2893 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2894 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2895 }
45f9a39b 2896
1b37078b
AD		 2897 if (rdev->family >= CHIP_CAYMAN) {
2898 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2899 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2900 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2901 } else
2902 WREG32(CP_INT_CNTL, cp_int_cntl);
233d1ad5
AD		 2903
2904 WREG32(DMA_CNTL, dma_cntl);
2905
f60cbd11
AD		 2906 if (rdev->family >= CHIP_CAYMAN)
2907 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
2908
2031f77c 2909 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2910
2911 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2912 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 2913 if (rdev->num_crtc >= 4) {
18007401
AD		 2914 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2915 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 2916 }
2917 if (rdev->num_crtc >= 6) {
18007401
AD		 2918 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2919 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2920 }
45f9a39b 2921
6f34be50
AD		 2922 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2923 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 2924 if (rdev->num_crtc >= 4) {
2925 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2926 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2927 }
2928 if (rdev->num_crtc >= 6) {
2929 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2930 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2931 }
6f34be50 2932
45f9a39b
AD		 2933 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2934 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2935 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2936 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2937 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2938 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2939
f122c610
AD		 2940 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2941 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2942 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2943 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2944 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2945 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2946
bcc1c2a1
AD		 2947 return 0;
2948}
2949
cbdd4501 2950static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2951{
2952 u32 tmp;
2953
6f34be50
AD		 2954 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2955 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2956 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2957 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2958 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2959 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2960 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2961 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 2962 if (rdev->num_crtc >= 4) {
2963 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2964 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2965 }
2966 if (rdev->num_crtc >= 6) {
2967 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2968 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2969 }
6f34be50 2970
f122c610
AD		 2971 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2972 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2973 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2974 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2975 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2976 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2977
6f34be50
AD		 2978 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2979 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2980 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2981 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 2982 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2983 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2984 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 2985 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 2986 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2987 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2988 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2989 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2990
b7eff394
AD		 2991 if (rdev->num_crtc >= 4) {
2992 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2993 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2994 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2995 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2996 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2997 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2998 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2999 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3000 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3001 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3002 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3003 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3004 }
3005
3006 if (rdev->num_crtc >= 6) {
3007 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3008 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3009 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3010 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3011 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3012 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3013 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3014 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3015 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3016 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3017 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3018 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3019 }
45f9a39b 3020
6f34be50 3021 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 3022 tmp = RREG32(DC_HPD1_INT_CONTROL);
3023 tmp |= DC_HPDx_INT_ACK;
3024 WREG32(DC_HPD1_INT_CONTROL, tmp);
3025 }
6f34be50 3026 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 3027 tmp = RREG32(DC_HPD2_INT_CONTROL);
3028 tmp |= DC_HPDx_INT_ACK;
3029 WREG32(DC_HPD2_INT_CONTROL, tmp);
3030 }
6f34be50 3031 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 3032 tmp = RREG32(DC_HPD3_INT_CONTROL);
3033 tmp |= DC_HPDx_INT_ACK;
3034 WREG32(DC_HPD3_INT_CONTROL, tmp);
3035 }
6f34be50 3036 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 3037 tmp = RREG32(DC_HPD4_INT_CONTROL);
3038 tmp |= DC_HPDx_INT_ACK;
3039 WREG32(DC_HPD4_INT_CONTROL, tmp);
3040 }
6f34be50 3041 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 3042 tmp = RREG32(DC_HPD5_INT_CONTROL);
3043 tmp |= DC_HPDx_INT_ACK;
3044 WREG32(DC_HPD5_INT_CONTROL, tmp);
3045 }
6f34be50 3046 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 3047 tmp = RREG32(DC_HPD5_INT_CONTROL);
3048 tmp |= DC_HPDx_INT_ACK;
3049 WREG32(DC_HPD6_INT_CONTROL, tmp);
3050 }
f122c610
AD		 3051 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3052 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
3053 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3054 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
3055 }
3056 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3057 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
3058 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3059 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
3060 }
3061 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3062 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
3063 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3064 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
3065 }
3066 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3067 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
3068 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3069 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
3070 }
3071 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3072 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
3073 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3074 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
3075 }
3076 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3077 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
3078 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3079 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
3080 }
45f9a39b
AD		 3081}
3082
1109ca09 3083static void evergreen_irq_disable(struct radeon_device *rdev)
45f9a39b 3084{
45f9a39b
AD		 3085 r600_disable_interrupts(rdev);
3086 /* Wait and acknowledge irq */
3087 mdelay(1);
6f34be50 3088 evergreen_irq_ack(rdev);
45f9a39b
AD		 3089 evergreen_disable_interrupt_state(rdev);
3090}
3091
755d819e 3092void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 3093{
3094 evergreen_irq_disable(rdev);
3095 r600_rlc_stop(rdev);
3096}
3097
cbdd4501 3098static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 3099{
3100 u32 wptr, tmp;
3101
724c80e1 3102 if (rdev->wb.enabled)
204ae24d 3103 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3104 else
3105 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 3106
3107 if (wptr & RB_OVERFLOW) {
3108 /* When a ring buffer overflow happen start parsing interrupt
3109 * from the last not overwritten vector (wptr + 16). Hopefully
3110 * this should allow us to catchup.
3111 */
3112 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3113 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3114 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3115 tmp = RREG32(IH_RB_CNTL);
3116 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3117 WREG32(IH_RB_CNTL, tmp);
3118 }
3119 return (wptr & rdev->ih.ptr_mask);
3120}
3121
3122int evergreen_irq_process(struct radeon_device *rdev)
3123{
682f1a54
DA		 3124 u32 wptr;
3125 u32 rptr;
45f9a39b
AD		 3126 u32 src_id, src_data;
3127 u32 ring_index;
45f9a39b 3128 bool queue_hotplug = false;
f122c610 3129 bool queue_hdmi = false;
45f9a39b 3130
682f1a54 3131 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 3132 return IRQ_NONE;
3133
682f1a54 3134 wptr = evergreen_get_ih_wptr(rdev);
c20dc369
CK		 3135
3136restart_ih:
3137 /* is somebody else already processing irqs? */
3138 if (atomic_xchg(&rdev->ih.lock, 1))
3139 return IRQ_NONE;
3140
682f1a54
DA		 3141 rptr = rdev->ih.rptr;
3142 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 3143
964f6645
BH		 3144 /* Order reading of wptr vs. reading of IH ring data */
3145 rmb();
3146
45f9a39b 3147 /* display interrupts */
6f34be50 3148 evergreen_irq_ack(rdev);
45f9a39b 3149
45f9a39b
AD		 3150 while (rptr != wptr) {
3151 /* wptr/rptr are in bytes! */
3152 ring_index = rptr / 4;
0f234f5f
AD		 3153 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3154 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 3155
3156 switch (src_id) {
3157 case 1: /* D1 vblank/vline */
3158 switch (src_data) {
3159 case 0: /* D1 vblank */
6f34be50 3160 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3161 if (rdev->irq.crtc_vblank_int[0]) {
3162 drm_handle_vblank(rdev->ddev, 0);
3163 rdev->pm.vblank_sync = true;
3164 wake_up(&rdev->irq.vblank_queue);
3165 }
736fc37f 3166 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 3167 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3168 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 3169 DRM_DEBUG("IH: D1 vblank\n");
3170 }
3171 break;
3172 case 1: /* D1 vline */
6f34be50
AD		 3173 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3174 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 3175 DRM_DEBUG("IH: D1 vline\n");
3176 }
3177 break;
3178 default:
3179 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3180 break;
3181 }
3182 break;
3183 case 2: /* D2 vblank/vline */
3184 switch (src_data) {
3185 case 0: /* D2 vblank */
6f34be50 3186 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3187 if (rdev->irq.crtc_vblank_int[1]) {
3188 drm_handle_vblank(rdev->ddev, 1);
3189 rdev->pm.vblank_sync = true;
3190 wake_up(&rdev->irq.vblank_queue);
3191 }
736fc37f 3192 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 3193 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3194 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 3195 DRM_DEBUG("IH: D2 vblank\n");
3196 }
3197 break;
3198 case 1: /* D2 vline */
6f34be50
AD		 3199 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3200 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 3201 DRM_DEBUG("IH: D2 vline\n");
3202 }
3203 break;
3204 default:
3205 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3206 break;
3207 }
3208 break;
3209 case 3: /* D3 vblank/vline */
3210 switch (src_data) {
3211 case 0: /* D3 vblank */
6f34be50
AD		 3212 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3213 if (rdev->irq.crtc_vblank_int[2]) {
3214 drm_handle_vblank(rdev->ddev, 2);
3215 rdev->pm.vblank_sync = true;
3216 wake_up(&rdev->irq.vblank_queue);
3217 }
736fc37f 3218 if (atomic_read(&rdev->irq.pflip[2]))
6f34be50
AD		 3219 radeon_crtc_handle_flip(rdev, 2);
3220 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 3221 DRM_DEBUG("IH: D3 vblank\n");
3222 }
3223 break;
3224 case 1: /* D3 vline */
6f34be50
AD		 3225 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3226 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 3227 DRM_DEBUG("IH: D3 vline\n");
3228 }
3229 break;
3230 default:
3231 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3232 break;
3233 }
3234 break;
3235 case 4: /* D4 vblank/vline */
3236 switch (src_data) {
3237 case 0: /* D4 vblank */
6f34be50
AD		 3238 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3239 if (rdev->irq.crtc_vblank_int[3]) {
3240 drm_handle_vblank(rdev->ddev, 3);
3241 rdev->pm.vblank_sync = true;
3242 wake_up(&rdev->irq.vblank_queue);
3243 }
736fc37f 3244 if (atomic_read(&rdev->irq.pflip[3]))
6f34be50
AD		 3245 radeon_crtc_handle_flip(rdev, 3);
3246 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 3247 DRM_DEBUG("IH: D4 vblank\n");
3248 }
3249 break;
3250 case 1: /* D4 vline */
6f34be50
AD		 3251 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3252 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 3253 DRM_DEBUG("IH: D4 vline\n");
3254 }
3255 break;
3256 default:
3257 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3258 break;
3259 }
3260 break;
3261 case 5: /* D5 vblank/vline */
3262 switch (src_data) {
3263 case 0: /* D5 vblank */
6f34be50
AD		 3264 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3265 if (rdev->irq.crtc_vblank_int[4]) {
3266 drm_handle_vblank(rdev->ddev, 4);
3267 rdev->pm.vblank_sync = true;
3268 wake_up(&rdev->irq.vblank_queue);
3269 }
736fc37f 3270 if (atomic_read(&rdev->irq.pflip[4]))
6f34be50
AD		 3271 radeon_crtc_handle_flip(rdev, 4);
3272 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 3273 DRM_DEBUG("IH: D5 vblank\n");
3274 }
3275 break;
3276 case 1: /* D5 vline */
6f34be50
AD		 3277 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3278 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 3279 DRM_DEBUG("IH: D5 vline\n");
3280 }
3281 break;
3282 default:
3283 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3284 break;
3285 }
3286 break;
3287 case 6: /* D6 vblank/vline */
3288 switch (src_data) {
3289 case 0: /* D6 vblank */
6f34be50
AD		 3290 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3291 if (rdev->irq.crtc_vblank_int[5]) {
3292 drm_handle_vblank(rdev->ddev, 5);
3293 rdev->pm.vblank_sync = true;
3294 wake_up(&rdev->irq.vblank_queue);
3295 }
736fc37f 3296 if (atomic_read(&rdev->irq.pflip[5]))
6f34be50
AD		 3297 radeon_crtc_handle_flip(rdev, 5);
3298 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 3299 DRM_DEBUG("IH: D6 vblank\n");
3300 }
3301 break;
3302 case 1: /* D6 vline */
6f34be50
AD		 3303 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3304 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 3305 DRM_DEBUG("IH: D6 vline\n");
3306 }
3307 break;
3308 default:
3309 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3310 break;
3311 }
3312 break;
3313 case 42: /* HPD hotplug */
3314 switch (src_data) {
3315 case 0:
6f34be50
AD		 3316 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3317 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 3318 queue_hotplug = true;
3319 DRM_DEBUG("IH: HPD1\n");
3320 }
3321 break;
3322 case 1:
6f34be50
AD		 3323 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3324 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 3325 queue_hotplug = true;
3326 DRM_DEBUG("IH: HPD2\n");
3327 }
3328 break;
3329 case 2:
6f34be50
AD		 3330 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3331 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 3332 queue_hotplug = true;
3333 DRM_DEBUG("IH: HPD3\n");
3334 }
3335 break;
3336 case 3:
6f34be50
AD		 3337 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3338 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 3339 queue_hotplug = true;
3340 DRM_DEBUG("IH: HPD4\n");
3341 }
3342 break;
3343 case 4:
6f34be50
AD		 3344 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3345 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 3346 queue_hotplug = true;
3347 DRM_DEBUG("IH: HPD5\n");
3348 }
3349 break;
3350 case 5:
6f34be50
AD		 3351 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3352 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 3353 queue_hotplug = true;
3354 DRM_DEBUG("IH: HPD6\n");
3355 }
3356 break;
3357 default:
3358 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3359 break;
3360 }
3361 break;
f122c610
AD		 3362 case 44: /* hdmi */
3363 switch (src_data) {
3364 case 0:
3365 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3366 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3367 queue_hdmi = true;
3368 DRM_DEBUG("IH: HDMI0\n");
3369 }
3370 break;
3371 case 1:
3372 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3373 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3374 queue_hdmi = true;
3375 DRM_DEBUG("IH: HDMI1\n");
3376 }
3377 break;
3378 case 2:
3379 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3380 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3381 queue_hdmi = true;
3382 DRM_DEBUG("IH: HDMI2\n");
3383 }
3384 break;
3385 case 3:
3386 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3387 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3388 queue_hdmi = true;
3389 DRM_DEBUG("IH: HDMI3\n");
3390 }
3391 break;
3392 case 4:
3393 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3394 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3395 queue_hdmi = true;
3396 DRM_DEBUG("IH: HDMI4\n");
3397 }
3398 break;
3399 case 5:
3400 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3401 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3402 queue_hdmi = true;
3403 DRM_DEBUG("IH: HDMI5\n");
3404 }
3405 break;
3406 default:
3407 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3408 break;
3409 }
f2ba57b5
CK		 3410 case 124: /* UVD */
3411 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
3412 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
f122c610 3413 break;
ae133a11
CK		 3414 case 146:
3415 case 147:
3416 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3417 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3418 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3419 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3420 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3421 /* reset addr and status */
3422 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3423 break;
45f9a39b
AD		 3424 case 176: /* CP_INT in ring buffer */
3425 case 177: /* CP_INT in IB1 */
3426 case 178: /* CP_INT in IB2 */
3427 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3428 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 3429 break;
3430 case 181: /* CP EOP event */
3431 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 3432 if (rdev->family >= CHIP_CAYMAN) {
3433 switch (src_data) {
3434 case 0:
3435 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3436 break;
3437 case 1:
3438 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3439 break;
3440 case 2:
3441 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3442 break;
3443 }
3444 } else
3445 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 3446 break;
233d1ad5
AD		 3447 case 224: /* DMA trap event */
3448 DRM_DEBUG("IH: DMA trap\n");
3449 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3450 break;
2031f77c 3451 case 233: /* GUI IDLE */
303c805c 3452 DRM_DEBUG("IH: GUI idle\n");
2031f77c 3453 break;
f60cbd11
AD		 3454 case 244: /* DMA trap event */
3455 if (rdev->family >= CHIP_CAYMAN) {
3456 DRM_DEBUG("IH: DMA1 trap\n");
3457 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
3458 }
3459 break;
45f9a39b
AD		 3460 default:
3461 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3462 break;
3463 }
3464
3465 /* wptr/rptr are in bytes! */
3466 rptr += 16;
3467 rptr &= rdev->ih.ptr_mask;
3468 }
45f9a39b 3469 if (queue_hotplug)
32c87fca 3470 schedule_work(&rdev->hotplug_work);
f122c610
AD		 3471 if (queue_hdmi)
3472 schedule_work(&rdev->audio_work);
45f9a39b
AD		 3473 rdev->ih.rptr = rptr;
3474 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 3475 atomic_set(&rdev->ih.lock, 0);
3476
3477 /* make sure wptr hasn't changed while processing */
3478 wptr = evergreen_get_ih_wptr(rdev);
3479 if (wptr != rptr)
3480 goto restart_ih;
3481
45f9a39b
AD		 3482 return IRQ_HANDLED;
3483}
3484
233d1ad5
AD		 3485/**
3486 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
3487 *
3488 * @rdev: radeon_device pointer
3489 * @fence: radeon fence object
3490 *
3491 * Add a DMA fence packet to the ring to write
3492 * the fence seq number and DMA trap packet to generate
3493 * an interrupt if needed (evergreen-SI).
3494 */
3495void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
3496 struct radeon_fence *fence)
3497{
3498 struct radeon_ring *ring = &rdev->ring[fence->ring];
3499 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3500 /* write the fence */
0fcb6155 3501 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
233d1ad5
AD		 3502 radeon_ring_write(ring, addr & 0xfffffffc);
3503 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3504 radeon_ring_write(ring, fence->seq);
3505 /* generate an interrupt */
0fcb6155 3506 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
233d1ad5 3507 /* flush HDP */
0fcb6155 3508 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
4b681c28 3509 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
233d1ad5
AD		 3510 radeon_ring_write(ring, 1);
3511}
3512
3513/**
3514 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
3515 *
3516 * @rdev: radeon_device pointer
3517 * @ib: IB object to schedule
3518 *
3519 * Schedule an IB in the DMA ring (evergreen).
3520 */
3521void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3522 struct radeon_ib *ib)
3523{
3524 struct radeon_ring *ring = &rdev->ring[ib->ring];
3525
3526 if (rdev->wb.enabled) {
3527 u32 next_rptr = ring->wptr + 4;
3528 while ((next_rptr & 7) != 5)
3529 next_rptr++;
3530 next_rptr += 3;
0fcb6155 3531 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
233d1ad5
AD		 3532 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3533 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3534 radeon_ring_write(ring, next_rptr);
3535 }
3536
3537 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3538 * Pad as necessary with NOPs.
3539 */
3540 while ((ring->wptr & 7) != 5)
0fcb6155
JG		 3541 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3542 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
233d1ad5
AD		 3543 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3544 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3545
3546}
3547
3548/**
3549 * evergreen_copy_dma - copy pages using the DMA engine
3550 *
3551 * @rdev: radeon_device pointer
3552 * @src_offset: src GPU address
3553 * @dst_offset: dst GPU address
3554 * @num_gpu_pages: number of GPU pages to xfer
3555 * @fence: radeon fence object
3556 *
3557 * Copy GPU paging using the DMA engine (evergreen-cayman).
3558 * Used by the radeon ttm implementation to move pages if
3559 * registered as the asic copy callback.
3560 */
3561int evergreen_copy_dma(struct radeon_device *rdev,
3562 uint64_t src_offset, uint64_t dst_offset,
3563 unsigned num_gpu_pages,
3564 struct radeon_fence **fence)
3565{
3566 struct radeon_semaphore *sem = NULL;
3567 int ring_index = rdev->asic->copy.dma_ring_index;
3568 struct radeon_ring *ring = &rdev->ring[ring_index];
3569 u32 size_in_dw, cur_size_in_dw;
3570 int i, num_loops;
3571 int r = 0;
3572
3573 r = radeon_semaphore_create(rdev, &sem);
3574 if (r) {
3575 DRM_ERROR("radeon: moving bo (%d).\n", r);
3576 return r;
3577 }
3578
3579 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3580 num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
3581 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
3582 if (r) {
3583 DRM_ERROR("radeon: moving bo (%d).\n", r);
3584 radeon_semaphore_free(rdev, &sem, NULL);
3585 return r;
3586 }
3587
3588 if (radeon_fence_need_sync(*fence, ring->idx)) {
3589 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3590 ring->idx);
3591 radeon_fence_note_sync(*fence, ring->idx);
3592 } else {
3593 radeon_semaphore_free(rdev, &sem, NULL);
3594 }
3595
3596 for (i = 0; i < num_loops; i++) {
3597 cur_size_in_dw = size_in_dw;
3598 if (cur_size_in_dw > 0xFFFFF)
3599 cur_size_in_dw = 0xFFFFF;
3600 size_in_dw -= cur_size_in_dw;
0fcb6155 3601 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
233d1ad5
AD		 3602 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3603 radeon_ring_write(ring, src_offset & 0xfffffffc);
3604 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3605 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3606 src_offset += cur_size_in_dw * 4;
3607 dst_offset += cur_size_in_dw * 4;
3608 }
3609
3610 r = radeon_fence_emit(rdev, fence, ring->idx);
3611 if (r) {
3612 radeon_ring_unlock_undo(rdev, ring);
3613 return r;
3614 }
3615
3616 radeon_ring_unlock_commit(rdev, ring);
3617 radeon_semaphore_free(rdev, &sem, *fence);
3618
3619 return r;
3620}
3621
bcc1c2a1
AD		 3622static int evergreen_startup(struct radeon_device *rdev)
3623{
f2ba57b5 3624 struct radeon_ring *ring;
bcc1c2a1
AD		 3625 int r;
3626
9e46a48d 3627 /* enable pcie gen2 link */
cd54033a 3628 evergreen_pcie_gen2_enable(rdev);
9e46a48d 3629
0af62b01
AD		 3630 if (ASIC_IS_DCE5(rdev)) {
3631 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3632 r = ni_init_microcode(rdev);
3633 if (r) {
3634 DRM_ERROR("Failed to load firmware!\n");
3635 return r;
3636 }
3637 }
755d819e 3638 r = ni_mc_load_microcode(rdev);
bcc1c2a1 3639 if (r) {
0af62b01 3640 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 3641 return r;
3642 }
0af62b01
AD		 3643 } else {
3644 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3645 r = r600_init_microcode(rdev);
3646 if (r) {
3647 DRM_ERROR("Failed to load firmware!\n");
3648 return r;
3649 }
3650 }
bcc1c2a1 3651 }
fe251e2f 3652
16cdf04d
AD		 3653 r = r600_vram_scratch_init(rdev);
3654 if (r)
3655 return r;
3656
bcc1c2a1 3657 evergreen_mc_program(rdev);
bcc1c2a1 3658 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 3659 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 3660 } else {
3661 r = evergreen_pcie_gart_enable(rdev);
3662 if (r)
3663 return r;
3664 }
bcc1c2a1 3665 evergreen_gpu_init(rdev);
bcc1c2a1 3666
d7ccd8fc 3667 r = evergreen_blit_init(rdev);
bcc1c2a1 3668 if (r) {
fb3d9e97 3669 r600_blit_fini(rdev);
27cd7769 3670 rdev->asic->copy.copy = NULL;
d7ccd8fc 3671 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 3672 }
3673
724c80e1
AD		 3674 /* allocate wb buffer */
3675 r = radeon_wb_init(rdev);
3676 if (r)
3677 return r;
3678
30eb77f4
JG		 3679 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3680 if (r) {
3681 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3682 return r;
3683 }
3684
233d1ad5
AD		 3685 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3686 if (r) {
3687 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3688 return r;
3689 }
3690
f2ba57b5
CK		 3691 r = rv770_uvd_resume(rdev);
3692 if (!r) {
3693 r = radeon_fence_driver_start_ring(rdev,
3694 R600_RING_TYPE_UVD_INDEX);
3695 if (r)
3696 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
3697 }
3698
3699 if (r)
3700 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3701
bcc1c2a1
AD		 3702 /* Enable IRQ */
3703 r = r600_irq_init(rdev);
3704 if (r) {
3705 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3706 radeon_irq_kms_fini(rdev);
3707 return r;
3708 }
45f9a39b 3709 evergreen_irq_set(rdev);
bcc1c2a1 3710
f2ba57b5 3711 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 3712 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 3713 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3714 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 3715 if (r)
3716 return r;
233d1ad5
AD		 3717
3718 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3719 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3720 DMA_RB_RPTR, DMA_RB_WPTR,
0fcb6155 3721 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
233d1ad5
AD		 3722 if (r)
3723 return r;
3724
bcc1c2a1
AD		 3725 r = evergreen_cp_load_microcode(rdev);
3726 if (r)
3727 return r;
fe251e2f 3728 r = evergreen_cp_resume(rdev);
233d1ad5
AD		 3729 if (r)
3730 return r;
3731 r = r600_dma_resume(rdev);
bcc1c2a1
AD		 3732 if (r)
3733 return r;
fe251e2f 3734
f2ba57b5
CK		 3735 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3736 if (ring->ring_size) {
3737 r = radeon_ring_init(rdev, ring, ring->ring_size,
3738 R600_WB_UVD_RPTR_OFFSET,
3739 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
3740 0, 0xfffff, RADEON_CP_PACKET2);
3741 if (!r)
3742 r = r600_uvd_init(rdev);
3743
3744 if (r)
3745 DRM_ERROR("radeon: error initializing UVD (%d).\n", r);
3746 }
3747
2898c348
CK		 3748 r = radeon_ib_pool_init(rdev);
3749 if (r) {
3750 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3751 return r;
2898c348 3752 }
b15ba512 3753
69d2ae57
RM		 3754 r = r600_audio_init(rdev);
3755 if (r) {
3756 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 3757 return r;
3758 }
3759
bcc1c2a1
AD		 3760 return 0;
3761}
3762
3763int evergreen_resume(struct radeon_device *rdev)
3764{
3765 int r;
3766
86f5c9ed
AD		 3767 /* reset the asic, the gfx blocks are often in a bad state
3768 * after the driver is unloaded or after a resume
3769 */
3770 if (radeon_asic_reset(rdev))
3771 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 3772 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3773 * posting will perform necessary task to bring back GPU into good
3774 * shape.
3775 */
3776 /* post card */
3777 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 3778
b15ba512 3779 rdev->accel_working = true;
bcc1c2a1
AD		 3780 r = evergreen_startup(rdev);
3781 if (r) {
755d819e 3782 DRM_ERROR("evergreen startup failed on resume\n");
6b7746e8 3783 rdev->accel_working = false;
bcc1c2a1
AD		 3784 return r;
3785 }
fe251e2f 3786
bcc1c2a1
AD		 3787 return r;
3788
3789}
3790
3791int evergreen_suspend(struct radeon_device *rdev)
3792{
69d2ae57 3793 r600_audio_fini(rdev);
f2ba57b5 3794 radeon_uvd_suspend(rdev);
bcc1c2a1 3795 r700_cp_stop(rdev);
233d1ad5 3796 r600_dma_stop(rdev);
f2ba57b5 3797 r600_uvd_rbc_stop(rdev);
45f9a39b 3798 evergreen_irq_suspend(rdev);
724c80e1 3799 radeon_wb_disable(rdev);
bcc1c2a1 3800 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 3801
3802 return 0;
3803}
3804
bcc1c2a1
AD		 3805/* Plan is to move initialization in that function and use
3806 * helper function so that radeon_device_init pretty much
3807 * do nothing more than calling asic specific function. This
3808 * should also allow to remove a bunch of callback function
3809 * like vram_info.
3810 */
3811int evergreen_init(struct radeon_device *rdev)
3812{
3813 int r;
3814
bcc1c2a1
AD		 3815 /* Read BIOS */
3816 if (!radeon_get_bios(rdev)) {
3817 if (ASIC_IS_AVIVO(rdev))
3818 return -EINVAL;
3819 }
3820 /* Must be an ATOMBIOS */
3821 if (!rdev->is_atom_bios) {
755d819e 3822 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 3823 return -EINVAL;
3824 }
3825 r = radeon_atombios_init(rdev);
3826 if (r)
3827 return r;
86f5c9ed
AD		 3828 /* reset the asic, the gfx blocks are often in a bad state
3829 * after the driver is unloaded or after a resume
3830 */
3831 if (radeon_asic_reset(rdev))
3832 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 3833 /* Post card if necessary */
fd909c37 3834 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 3835 if (!rdev->bios) {
3836 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3837 return -EINVAL;
3838 }
3839 DRM_INFO("GPU not posted. posting now...\n");
3840 atom_asic_init(rdev->mode_info.atom_context);
3841 }
3842 /* Initialize scratch registers */
3843 r600_scratch_init(rdev);
3844 /* Initialize surface registers */
3845 radeon_surface_init(rdev);
3846 /* Initialize clocks */
3847 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 3848 /* Fence driver */
3849 r = radeon_fence_driver_init(rdev);
3850 if (r)
3851 return r;
d594e46a
JG		 3852 /* initialize AGP */
3853 if (rdev->flags & RADEON_IS_AGP) {
3854 r = radeon_agp_init(rdev);
3855 if (r)
3856 radeon_agp_disable(rdev);
3857 }
3858 /* initialize memory controller */
bcc1c2a1
AD		 3859 r = evergreen_mc_init(rdev);
3860 if (r)
3861 return r;
3862 /* Memory manager */
3863 r = radeon_bo_init(rdev);
3864 if (r)
3865 return r;
45f9a39b 3866
bcc1c2a1
AD		 3867 r = radeon_irq_kms_init(rdev);
3868 if (r)
3869 return r;
3870
e32eb50d
CK		 3871 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3872 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1 3873
233d1ad5
AD		 3874 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3875 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3876
f2ba57b5
CK		 3877 r = radeon_uvd_init(rdev);
3878 if (!r) {
3879 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
3880 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
3881 4096);
3882 }
3883
bcc1c2a1
AD		 3884 rdev->ih.ring_obj = NULL;
3885 r600_ih_ring_init(rdev, 64 * 1024);
3886
3887 r = r600_pcie_gart_init(rdev);
3888 if (r)
3889 return r;
0fcdb61e 3890
148a03bc 3891 rdev->accel_working = true;
bcc1c2a1
AD		 3892 r = evergreen_startup(rdev);
3893 if (r) {
fe251e2f
AD		 3894 dev_err(rdev->dev, "disabling GPU acceleration\n");
3895 r700_cp_fini(rdev);
233d1ad5 3896 r600_dma_fini(rdev);
fe251e2f 3897 r600_irq_fini(rdev);
724c80e1 3898 radeon_wb_fini(rdev);
2898c348 3899 radeon_ib_pool_fini(rdev);
fe251e2f 3900 radeon_irq_kms_fini(rdev);
0fcdb61e 3901 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3902 rdev->accel_working = false;
3903 }
77e00f2e
AD		 3904
3905 /* Don't start up if the MC ucode is missing on BTC parts.
3906 * The default clocks and voltages before the MC ucode
3907 * is loaded are not suffient for advanced operations.
3908 */
3909 if (ASIC_IS_DCE5(rdev)) {
3910 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3911 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3912 return -EINVAL;
3913 }
3914 }
3915
bcc1c2a1
AD		 3916 return 0;
3917}
3918
3919void evergreen_fini(struct radeon_device *rdev)
3920{
69d2ae57 3921 r600_audio_fini(rdev);
fb3d9e97 3922 r600_blit_fini(rdev);
45f9a39b 3923 r700_cp_fini(rdev);
233d1ad5 3924 r600_dma_fini(rdev);
bcc1c2a1 3925 r600_irq_fini(rdev);
724c80e1 3926 radeon_wb_fini(rdev);
2898c348 3927 radeon_ib_pool_fini(rdev);
bcc1c2a1 3928 radeon_irq_kms_fini(rdev);
bcc1c2a1 3929 evergreen_pcie_gart_fini(rdev);
f2ba57b5 3930 radeon_uvd_fini(rdev);
16cdf04d 3931 r600_vram_scratch_fini(rdev);
bcc1c2a1
AD		 3932 radeon_gem_fini(rdev);
3933 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3934 radeon_agp_fini(rdev);
3935 radeon_bo_fini(rdev);
3936 radeon_atombios_fini(rdev);
3937 kfree(rdev->bios);
3938 rdev->bios = NULL;
bcc1c2a1 3939}
9e46a48d 3940
b07759bf 3941void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d 3942{
197bbb3d
DA		 3943 u32 link_width_cntl, speed_cntl, mask;
3944 int ret;
9e46a48d 3945
d42dd579
AD		 3946 if (radeon_pcie_gen2 == 0)
3947 return;
3948
9e46a48d
AD		 3949 if (rdev->flags & RADEON_IS_IGP)
3950 return;
3951
3952 if (!(rdev->flags & RADEON_IS_PCIE))
3953 return;
3954
3955 /* x2 cards have a special sequence */
3956 if (ASIC_IS_X2(rdev))
3957 return;
3958
197bbb3d
DA		 3959 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3960 if (ret != 0)
3961 return;
3962
3963 if (!(mask & DRM_PCIE_SPEED_50))
3964 return;
3965
3691feea
AD		 3966 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3967 if (speed_cntl & LC_CURRENT_DATA_RATE) {
3968 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3969 return;
3970 }
3971
197bbb3d
DA		 3972 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3973
9e46a48d
AD		 3974 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3975 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3976
3977 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3978 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3979 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3980
3981 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3982 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3983 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3984
3985 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3986 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3987 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3988
3989 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3990 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3991 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3992
3993 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3994 speed_cntl |= LC_GEN2_EN_STRAP;
3995 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3996
3997 } else {
3998 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3999 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4000 if (1)
4001 link_width_cntl |= LC_UPCONFIGURE_DIS;
4002 else
4003 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4004 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4005 }
4006}
Linux kernel - Deliverables
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