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drm/radeon: properly lock disp in mc_stop/resume for r5xx-r7xx
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
760285e7 27#include <drm/drmP.h>
bcc1c2a1 28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
760285e7 30#include <drm/radeon_drm.h>
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
4a15903d
AD		 40static const u32 crtc_offsets[6] =
41{
42 EVERGREEN_CRTC0_REGISTER_OFFSET,
43 EVERGREEN_CRTC1_REGISTER_OFFSET,
44 EVERGREEN_CRTC2_REGISTER_OFFSET,
45 EVERGREEN_CRTC3_REGISTER_OFFSET,
46 EVERGREEN_CRTC4_REGISTER_OFFSET,
47 EVERGREEN_CRTC5_REGISTER_OFFSET
48};
49
bcc1c2a1
AD		 50static void evergreen_gpu_init(struct radeon_device *rdev);
51void evergreen_fini(struct radeon_device *rdev);
b07759bf 52void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
1b37078b
AD		 53extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54 int ring, u32 cp_int_cntl);
bcc1c2a1 55
285484e2
JG		 56void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57 unsigned *bankh, unsigned *mtaspect,
58 unsigned *tile_split)
59{
60 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
61 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
62 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
63 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
64 switch (*bankw) {
65 default:
66 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
67 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
68 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
69 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
70 }
71 switch (*bankh) {
72 default:
73 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
74 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
75 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
76 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
77 }
78 switch (*mtaspect) {
79 default:
80 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
81 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
82 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
83 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
84 }
85}
86
23d33ba3
AD		 87static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
88 u32 cntl_reg, u32 status_reg)
89{
90 int r, i;
91 struct atom_clock_dividers dividers;
92
93 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
94 clock, false, &dividers);
95 if (r)
96 return r;
97
98 WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
99
100 for (i = 0; i < 100; i++) {
101 if (RREG32(status_reg) & DCLK_STATUS)
102 break;
103 mdelay(10);
104 }
105 if (i == 100)
106 return -ETIMEDOUT;
107
108 return 0;
109}
110
111int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
112{
113 int r = 0;
114 u32 cg_scratch = RREG32(CG_SCRATCH1);
115
116 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
117 if (r)
118 goto done;
119 cg_scratch &= 0xffff0000;
120 cg_scratch |= vclk / 100; /* Mhz */
121
122 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
123 if (r)
124 goto done;
125 cg_scratch &= 0x0000ffff;
126 cg_scratch |= (dclk / 100) << 16; /* Mhz */
127
128done:
129 WREG32(CG_SCRATCH1, cg_scratch);
130
131 return r;
132}
133
a8b4925c
AD		 134static int evergreen_uvd_calc_post_div(unsigned target_freq,
135 unsigned vco_freq,
136 unsigned *div)
137{
138 /* target larger than vco frequency ? */
139 if (vco_freq < target_freq)
140 return -1; /* forget it */
141
142 /* Fclk = Fvco / PDIV */
143 *div = vco_freq / target_freq;
144
145 /* we alway need a frequency less than or equal the target */
146 if ((vco_freq / *div) > target_freq)
147 *div += 1;
148
149 /* dividers above 5 must be even */
150 if (*div > 5 && *div % 2)
151 *div += 1;
152
153 /* out of range ? */
154 if (*div >= 128)
155 return -1; /* forget it */
156
157 return vco_freq / *div;
158}
159
160static int evergreen_uvd_send_upll_ctlreq(struct radeon_device *rdev)
161{
162 unsigned i;
163
164 /* assert UPLL_CTLREQ */
165 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
166
167 /* wait for CTLACK and CTLACK2 to get asserted */
168 for (i = 0; i < 100; ++i) {
169 uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
170 if ((RREG32(CG_UPLL_FUNC_CNTL) & mask) == mask)
171 break;
172 mdelay(10);
173 }
174 if (i == 100)
175 return -ETIMEDOUT;
176
177 /* deassert UPLL_CTLREQ */
178 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK);
179
180 return 0;
181}
182
183int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
184{
185 /* start off with something large */
186 int optimal_diff_score = 0x7FFFFFF;
187 unsigned optimal_fb_div = 0, optimal_vclk_div = 0;
188 unsigned optimal_dclk_div = 0, optimal_vco_freq = 0;
189 unsigned vco_freq;
190 int r;
191
192 /* loop through vco from low to high */
193 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
194 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
195 int calc_clk, diff_score, diff_vclk, diff_dclk;
196 unsigned vclk_div, dclk_div;
197
198 /* fb div out of range ? */
199 if (fb_div > 0x03FFFFFF)
200 break; /* it can oly get worse */
201
202 /* calc vclk with current vco freq. */
203 calc_clk = evergreen_uvd_calc_post_div(vclk, vco_freq, &vclk_div);
204 if (calc_clk == -1)
205 break; /* vco is too big, it has to stop. */
206 diff_vclk = vclk - calc_clk;
207
208 /* calc dclk with current vco freq. */
209 calc_clk = evergreen_uvd_calc_post_div(dclk, vco_freq, &dclk_div);
210 if (calc_clk == -1)
211 break; /* vco is too big, it has to stop. */
212 diff_dclk = dclk - calc_clk;
213
214 /* determine if this vco setting is better than current optimal settings */
215 diff_score = abs(diff_vclk) + abs(diff_dclk);
216 if (diff_score < optimal_diff_score) {
217 optimal_fb_div = fb_div;
218 optimal_vclk_div = vclk_div;
219 optimal_dclk_div = dclk_div;
220 optimal_vco_freq = vco_freq;
221 optimal_diff_score = diff_score;
222 if (optimal_diff_score == 0)
223 break; /* it can't get better than this */
224 }
225 }
226
227 /* set VCO_MODE to 1 */
228 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
229
230 /* toggle UPLL_SLEEP to 1 then back to 0 */
231 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
232 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
233
234 /* deassert UPLL_RESET */
235 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
236
237 mdelay(1);
238
239 /* bypass vclk and dclk with bclk */
240 WREG32_P(CG_UPLL_FUNC_CNTL_2,
241 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
242 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
243
244 /* put PLL in bypass mode */
245 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
246
247 r = evergreen_uvd_send_upll_ctlreq(rdev);
248 if (r)
249 return r;
250
251 /* assert UPLL_RESET again */
252 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
253
254 /* disable spread spectrum. */
255 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
256
257 /* set feedback divider */
258 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(optimal_fb_div), ~UPLL_FB_DIV_MASK);
259
260 /* set ref divider to 0 */
261 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
262
263 if (optimal_vco_freq < 187500)
264 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
265 else
266 WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
267
268 /* set PDIV_A and PDIV_B */
269 WREG32_P(CG_UPLL_FUNC_CNTL_2,
270 UPLL_PDIV_A(optimal_vclk_div) | UPLL_PDIV_B(optimal_dclk_div),
271 ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
272
273 /* give the PLL some time to settle */
274 mdelay(15);
275
276 /* deassert PLL_RESET */
277 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
278
279 mdelay(15);
280
281 /* switch from bypass mode to normal mode */
282 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
283
284 r = evergreen_uvd_send_upll_ctlreq(rdev);
285 if (r)
286 return r;
287
288 /* switch VCLK and DCLK selection */
289 WREG32_P(CG_UPLL_FUNC_CNTL_2,
290 VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
291 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
292
293 mdelay(100);
294
295 return 0;
296}
297
d054ac16
AD		 298void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
299{
300 u16 ctl, v;
32195aec 301 int err;
d054ac16 302
32195aec 303 err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
d054ac16
AD		 304 if (err)
305 return;
306
307 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
308
309 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
310 * to avoid hangs or perfomance issues
311 */
312 if ((v == 0) || (v == 6) || (v == 7)) {
313 ctl &= ~PCI_EXP_DEVCTL_READRQ;
314 ctl |= (2 << 12);
32195aec 315 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
d054ac16
AD		 316 }
317}
318
10257a6d
AD		 319static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
320{
321 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
322 return true;
323 else
324 return false;
325}
326
327static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
328{
329 u32 pos1, pos2;
330
331 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
332 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
333
334 if (pos1 != pos2)
335 return true;
336 else
337 return false;
338}
339
377edc8b
AD		 340/**
341 * dce4_wait_for_vblank - vblank wait asic callback.
342 *
343 * @rdev: radeon_device pointer
344 * @crtc: crtc to wait for vblank on
345 *
346 * Wait for vblank on the requested crtc (evergreen+).
347 */
3ae19b75
AD		 348void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
349{
10257a6d 350 unsigned i = 0;
3ae19b75 351
4a15903d
AD		 352 if (crtc >= rdev->num_crtc)
353 return;
354
10257a6d
AD		 355 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
356 return;
357
358 /* depending on when we hit vblank, we may be close to active; if so,
359 * wait for another frame.
360 */
361 while (dce4_is_in_vblank(rdev, crtc)) {
362 if (i++ % 100 == 0) {
363 if (!dce4_is_counter_moving(rdev, crtc))
3ae19b75 364 break;
3ae19b75 365 }
10257a6d
AD		 366 }
367
368 while (!dce4_is_in_vblank(rdev, crtc)) {
369 if (i++ % 100 == 0) {
370 if (!dce4_is_counter_moving(rdev, crtc))
3ae19b75 371 break;
3ae19b75
AD		 372 }
373 }
374}
375
377edc8b
AD		 376/**
377 * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
378 *
379 * @rdev: radeon_device pointer
380 * @crtc: crtc to prepare for pageflip on
381 *
382 * Pre-pageflip callback (evergreen+).
383 * Enables the pageflip irq (vblank irq).
384 */
6f34be50
AD		 385void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
386{
6f34be50
AD		 387 /* enable the pflip int */
388 radeon_irq_kms_pflip_irq_get(rdev, crtc);
389}
390
377edc8b
AD		 391/**
392 * evergreen_post_page_flip - pos-pageflip callback.
393 *
394 * @rdev: radeon_device pointer
395 * @crtc: crtc to cleanup pageflip on
396 *
397 * Post-pageflip callback (evergreen+).
398 * Disables the pageflip irq (vblank irq).
399 */
6f34be50
AD		 400void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
401{
402 /* disable the pflip int */
403 radeon_irq_kms_pflip_irq_put(rdev, crtc);
404}
405
377edc8b
AD		 406/**
407 * evergreen_page_flip - pageflip callback.
408 *
409 * @rdev: radeon_device pointer
410 * @crtc_id: crtc to cleanup pageflip on
411 * @crtc_base: new address of the crtc (GPU MC address)
412 *
413 * Does the actual pageflip (evergreen+).
414 * During vblank we take the crtc lock and wait for the update_pending
415 * bit to go high, when it does, we release the lock, and allow the
416 * double buffered update to take place.
417 * Returns the current update pending status.
418 */
6f34be50
AD		 419u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
420{
421 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
422 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 423 int i;
6f34be50
AD		 424
425 /* Lock the graphics update lock */
426 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
427 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
428
429 /* update the scanout addresses */
430 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
431 upper_32_bits(crtc_base));
432 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
433 (u32)crtc_base);
434
435 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
436 upper_32_bits(crtc_base));
437 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
438 (u32)crtc_base);
439
440 /* Wait for update_pending to go high. */
f6496479
AD		 441 for (i = 0; i < rdev->usec_timeout; i++) {
442 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
443 break;
444 udelay(1);
445 }
6f34be50
AD		 446 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
447
448 /* Unlock the lock, so double-buffering can take place inside vblank */
449 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
450 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
451
452 /* Return current update_pending status: */
453 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
454}
455
21a8122a 456/* get temperature in millidegrees */
20d391d7 457int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 458{
1c88d74f
AD		 459 u32 temp, toffset;
460 int actual_temp = 0;
67b3f823
AD		 461
462 if (rdev->family == CHIP_JUNIPER) {
463 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
464 TOFFSET_SHIFT;
465 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
466 TS0_ADC_DOUT_SHIFT;
467
468 if (toffset & 0x100)
469 actual_temp = temp / 2 - (0x200 - toffset);
470 else
471 actual_temp = temp / 2 + toffset;
472
473 actual_temp = actual_temp * 1000;
474
475 } else {
476 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
477 ASIC_T_SHIFT;
478
479 if (temp & 0x400)
480 actual_temp = -256;
481 else if (temp & 0x200)
482 actual_temp = 255;
483 else if (temp & 0x100) {
484 actual_temp = temp & 0x1ff;
485 actual_temp |= ~0x1ff;
486 } else
487 actual_temp = temp & 0xff;
488
489 actual_temp = (actual_temp * 1000) / 2;
490 }
21a8122a 491
67b3f823 492 return actual_temp;
21a8122a
AD		 493}
494
20d391d7 495int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 496{
497 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 498 int actual_temp = temp - 49;
e33df25f
AD		 499
500 return actual_temp * 1000;
501}
502
377edc8b
AD		 503/**
504 * sumo_pm_init_profile - Initialize power profiles callback.
505 *
506 * @rdev: radeon_device pointer
507 *
508 * Initialize the power states used in profile mode
509 * (sumo, trinity, SI).
510 * Used for profile mode only.
511 */
a4c9e2ee
AD		 512void sumo_pm_init_profile(struct radeon_device *rdev)
513{
514 int idx;
515
516 /* default */
517 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
518 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
519 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
520 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
521
522 /* low,mid sh/mh */
523 if (rdev->flags & RADEON_IS_MOBILITY)
524 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
525 else
526 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
527
528 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
531 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
532
533 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
534 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
535 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
536 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
537
538 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
539 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
540 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
541 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
542
543 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
544 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
545 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
546 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
547
548 /* high sh/mh */
549 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
550 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
551 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
552 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
553 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
554 rdev->pm.power_state[idx].num_clock_modes - 1;
555
556 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
557 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
558 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
559 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
560 rdev->pm.power_state[idx].num_clock_modes - 1;
561}
562
27810fb2
AD		 563/**
564 * btc_pm_init_profile - Initialize power profiles callback.
565 *
566 * @rdev: radeon_device pointer
567 *
568 * Initialize the power states used in profile mode
569 * (BTC, cayman).
570 * Used for profile mode only.
571 */
572void btc_pm_init_profile(struct radeon_device *rdev)
573{
574 int idx;
575
576 /* default */
577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
579 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
580 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
581 /* starting with BTC, there is one state that is used for both
582 * MH and SH. Difference is that we always use the high clock index for
583 * mclk.
584 */
585 if (rdev->flags & RADEON_IS_MOBILITY)
586 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
587 else
588 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
589 /* low sh */
590 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
591 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
592 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
593 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
594 /* mid sh */
595 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
596 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
597 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
598 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
599 /* high sh */
600 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
601 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
602 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
603 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
604 /* low mh */
605 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
606 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
607 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
608 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
609 /* mid mh */
610 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
611 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
612 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
613 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
614 /* high mh */
615 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
616 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
617 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
618 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
619}
620
377edc8b
AD		 621/**
622 * evergreen_pm_misc - set additional pm hw parameters callback.
623 *
624 * @rdev: radeon_device pointer
625 *
626 * Set non-clock parameters associated with a power state
627 * (voltage, etc.) (evergreen+).
628 */
49e02b73
AD		 629void evergreen_pm_misc(struct radeon_device *rdev)
630{
a081a9d6
RM		 631 int req_ps_idx = rdev->pm.requested_power_state_index;
632 int req_cm_idx = rdev->pm.requested_clock_mode_index;
633 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
634 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 635
2feea49a 636 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 637 /* 0xff01 is a flag rather then an actual voltage */
638 if (voltage->voltage == 0xff01)
639 return;
2feea49a 640 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 641 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 642 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 643 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
644 }
7ae764b1
AD		 645
646 /* starting with BTC, there is one state that is used for both
647 * MH and SH. Difference is that we always use the high clock index for
648 * mclk and vddci.
649 */
650 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
651 (rdev->family >= CHIP_BARTS) &&
652 rdev->pm.active_crtc_count &&
653 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
654 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
655 voltage = &rdev->pm.power_state[req_ps_idx].
656 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
657
a377e187
AD		 658 /* 0xff01 is a flag rather then an actual voltage */
659 if (voltage->vddci == 0xff01)
660 return;
2feea49a
AD		 661 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
662 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
663 rdev->pm.current_vddci = voltage->vddci;
664 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 665 }
666 }
49e02b73
AD		 667}
668
377edc8b
AD		 669/**
670 * evergreen_pm_prepare - pre-power state change callback.
671 *
672 * @rdev: radeon_device pointer
673 *
674 * Prepare for a power state change (evergreen+).
675 */
49e02b73
AD		 676void evergreen_pm_prepare(struct radeon_device *rdev)
677{
678 struct drm_device *ddev = rdev->ddev;
679 struct drm_crtc *crtc;
680 struct radeon_crtc *radeon_crtc;
681 u32 tmp;
682
683 /* disable any active CRTCs */
684 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
685 radeon_crtc = to_radeon_crtc(crtc);
686 if (radeon_crtc->enabled) {
687 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
688 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
689 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
690 }
691 }
692}
693
377edc8b
AD		 694/**
695 * evergreen_pm_finish - post-power state change callback.
696 *
697 * @rdev: radeon_device pointer
698 *
699 * Clean up after a power state change (evergreen+).
700 */
49e02b73
AD		 701void evergreen_pm_finish(struct radeon_device *rdev)
702{
703 struct drm_device *ddev = rdev->ddev;
704 struct drm_crtc *crtc;
705 struct radeon_crtc *radeon_crtc;
706 u32 tmp;
707
708 /* enable any active CRTCs */
709 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
710 radeon_crtc = to_radeon_crtc(crtc);
711 if (radeon_crtc->enabled) {
712 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
713 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
714 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
715 }
716 }
717}
718
377edc8b
AD		 719/**
720 * evergreen_hpd_sense - hpd sense callback.
721 *
722 * @rdev: radeon_device pointer
723 * @hpd: hpd (hotplug detect) pin
724 *
725 * Checks if a digital monitor is connected (evergreen+).
726 * Returns true if connected, false if not connected.
727 */
bcc1c2a1
AD		 728bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
729{
730 bool connected = false;
0ca2ab52
AD		 731
732 switch (hpd) {
733 case RADEON_HPD_1:
734 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
735 connected = true;
736 break;
737 case RADEON_HPD_2:
738 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
739 connected = true;
740 break;
741 case RADEON_HPD_3:
742 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
743 connected = true;
744 break;
745 case RADEON_HPD_4:
746 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
747 connected = true;
748 break;
749 case RADEON_HPD_5:
750 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
751 connected = true;
752 break;
753 case RADEON_HPD_6:
754 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
755 connected = true;
756 break;
757 default:
758 break;
759 }
760
bcc1c2a1
AD		 761 return connected;
762}
763
377edc8b
AD		 764/**
765 * evergreen_hpd_set_polarity - hpd set polarity callback.
766 *
767 * @rdev: radeon_device pointer
768 * @hpd: hpd (hotplug detect) pin
769 *
770 * Set the polarity of the hpd pin (evergreen+).
771 */
bcc1c2a1
AD		 772void evergreen_hpd_set_polarity(struct radeon_device *rdev,
773 enum radeon_hpd_id hpd)
774{
0ca2ab52
AD		 775 u32 tmp;
776 bool connected = evergreen_hpd_sense(rdev, hpd);
777
778 switch (hpd) {
779 case RADEON_HPD_1:
780 tmp = RREG32(DC_HPD1_INT_CONTROL);
781 if (connected)
782 tmp &= ~DC_HPDx_INT_POLARITY;
783 else
784 tmp |= DC_HPDx_INT_POLARITY;
785 WREG32(DC_HPD1_INT_CONTROL, tmp);
786 break;
787 case RADEON_HPD_2:
788 tmp = RREG32(DC_HPD2_INT_CONTROL);
789 if (connected)
790 tmp &= ~DC_HPDx_INT_POLARITY;
791 else
792 tmp |= DC_HPDx_INT_POLARITY;
793 WREG32(DC_HPD2_INT_CONTROL, tmp);
794 break;
795 case RADEON_HPD_3:
796 tmp = RREG32(DC_HPD3_INT_CONTROL);
797 if (connected)
798 tmp &= ~DC_HPDx_INT_POLARITY;
799 else
800 tmp |= DC_HPDx_INT_POLARITY;
801 WREG32(DC_HPD3_INT_CONTROL, tmp);
802 break;
803 case RADEON_HPD_4:
804 tmp = RREG32(DC_HPD4_INT_CONTROL);
805 if (connected)
806 tmp &= ~DC_HPDx_INT_POLARITY;
807 else
808 tmp |= DC_HPDx_INT_POLARITY;
809 WREG32(DC_HPD4_INT_CONTROL, tmp);
810 break;
811 case RADEON_HPD_5:
812 tmp = RREG32(DC_HPD5_INT_CONTROL);
813 if (connected)
814 tmp &= ~DC_HPDx_INT_POLARITY;
815 else
816 tmp |= DC_HPDx_INT_POLARITY;
817 WREG32(DC_HPD5_INT_CONTROL, tmp);
818 break;
819 case RADEON_HPD_6:
820 tmp = RREG32(DC_HPD6_INT_CONTROL);
821 if (connected)
822 tmp &= ~DC_HPDx_INT_POLARITY;
823 else
824 tmp |= DC_HPDx_INT_POLARITY;
825 WREG32(DC_HPD6_INT_CONTROL, tmp);
826 break;
827 default:
828 break;
829 }
bcc1c2a1
AD		 830}
831
377edc8b
AD		 832/**
833 * evergreen_hpd_init - hpd setup callback.
834 *
835 * @rdev: radeon_device pointer
836 *
837 * Setup the hpd pins used by the card (evergreen+).
838 * Enable the pin, set the polarity, and enable the hpd interrupts.
839 */
bcc1c2a1
AD		 840void evergreen_hpd_init(struct radeon_device *rdev)
841{
0ca2ab52
AD		 842 struct drm_device *dev = rdev->ddev;
843 struct drm_connector *connector;
fb98257a 844 unsigned enabled = 0;
0ca2ab52
AD		 845 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
846 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 847
0ca2ab52
AD		 848 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
849 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2e97be73
AD		 850
851 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
852 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
853 /* don't try to enable hpd on eDP or LVDS avoid breaking the
854 * aux dp channel on imac and help (but not completely fix)
855 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
856 * also avoid interrupt storms during dpms.
857 */
858 continue;
859 }
0ca2ab52
AD		 860 switch (radeon_connector->hpd.hpd) {
861 case RADEON_HPD_1:
862 WREG32(DC_HPD1_CONTROL, tmp);
0ca2ab52
AD		 863 break;
864 case RADEON_HPD_2:
865 WREG32(DC_HPD2_CONTROL, tmp);
0ca2ab52
AD		 866 break;
867 case RADEON_HPD_3:
868 WREG32(DC_HPD3_CONTROL, tmp);
0ca2ab52
AD		 869 break;
870 case RADEON_HPD_4:
871 WREG32(DC_HPD4_CONTROL, tmp);
0ca2ab52
AD		 872 break;
873 case RADEON_HPD_5:
874 WREG32(DC_HPD5_CONTROL, tmp);
0ca2ab52
AD		 875 break;
876 case RADEON_HPD_6:
877 WREG32(DC_HPD6_CONTROL, tmp);
0ca2ab52
AD		 878 break;
879 default:
880 break;
881 }
64912e99 882 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
fb98257a 883 enabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 884 }
fb98257a 885 radeon_irq_kms_enable_hpd(rdev, enabled);
bcc1c2a1
AD		 886}
887
377edc8b
AD		 888/**
889 * evergreen_hpd_fini - hpd tear down callback.
890 *
891 * @rdev: radeon_device pointer
892 *
893 * Tear down the hpd pins used by the card (evergreen+).
894 * Disable the hpd interrupts.
895 */
0ca2ab52 896void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 897{
0ca2ab52
AD		 898 struct drm_device *dev = rdev->ddev;
899 struct drm_connector *connector;
fb98257a 900 unsigned disabled = 0;
0ca2ab52
AD		 901
902 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
903 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
904 switch (radeon_connector->hpd.hpd) {
905 case RADEON_HPD_1:
906 WREG32(DC_HPD1_CONTROL, 0);
0ca2ab52
AD		 907 break;
908 case RADEON_HPD_2:
909 WREG32(DC_HPD2_CONTROL, 0);
0ca2ab52
AD		 910 break;
911 case RADEON_HPD_3:
912 WREG32(DC_HPD3_CONTROL, 0);
0ca2ab52
AD		 913 break;
914 case RADEON_HPD_4:
915 WREG32(DC_HPD4_CONTROL, 0);
0ca2ab52
AD		 916 break;
917 case RADEON_HPD_5:
918 WREG32(DC_HPD5_CONTROL, 0);
0ca2ab52
AD		 919 break;
920 case RADEON_HPD_6:
921 WREG32(DC_HPD6_CONTROL, 0);
0ca2ab52
AD		 922 break;
923 default:
924 break;
925 }
fb98257a 926 disabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 927 }
fb98257a 928 radeon_irq_kms_disable_hpd(rdev, disabled);
bcc1c2a1
AD		 929}
930
f9d9c362
AD		 931/* watermark setup */
932
933static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
934 struct radeon_crtc *radeon_crtc,
935 struct drm_display_mode *mode,
936 struct drm_display_mode *other_mode)
937{
12dfc843 938 u32 tmp;
f9d9c362
AD		 939 /*
940 * Line Buffer Setup
941 * There are 3 line buffers, each one shared by 2 display controllers.
942 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
943 * the display controllers. The paritioning is done via one of four
944 * preset allocations specified in bits 2:0:
945 * first display controller
946 * 0 - first half of lb (3840 * 2)
947 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 948 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 949 * 3 - first 1/4 of lb (1920 * 2)
950 * second display controller
951 * 4 - second half of lb (3840 * 2)
952 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 953 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 954 * 7 - last 1/4 of lb (1920 * 2)
955 */
12dfc843
AD		 956 /* this can get tricky if we have two large displays on a paired group
957 * of crtcs. Ideally for multiple large displays we'd assign them to
958 * non-linked crtcs for maximum line buffer allocation.
959 */
960 if (radeon_crtc->base.enabled && mode) {
961 if (other_mode)
f9d9c362 962 tmp = 0; /* 1/2 */
12dfc843
AD		 963 else
964 tmp = 2; /* whole */
965 } else
966 tmp = 0;
f9d9c362
AD		 967
968 /* second controller of the pair uses second half of the lb */
969 if (radeon_crtc->crtc_id % 2)
970 tmp += 4;
971 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
972
12dfc843
AD		 973 if (radeon_crtc->base.enabled && mode) {
974 switch (tmp) {
975 case 0:
976 case 4:
977 default:
978 if (ASIC_IS_DCE5(rdev))
979 return 4096 * 2;
980 else
981 return 3840 * 2;
982 case 1:
983 case 5:
984 if (ASIC_IS_DCE5(rdev))
985 return 6144 * 2;
986 else
987 return 5760 * 2;
988 case 2:
989 case 6:
990 if (ASIC_IS_DCE5(rdev))
991 return 8192 * 2;
992 else
993 return 7680 * 2;
994 case 3:
995 case 7:
996 if (ASIC_IS_DCE5(rdev))
997 return 2048 * 2;
998 else
999 return 1920 * 2;
1000 }
f9d9c362 1001 }
12dfc843
AD		 1002
1003 /* controller not enabled, so no lb used */
1004 return 0;
f9d9c362
AD		 1005}
1006
ca7db22b 1007u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
f9d9c362
AD		 1008{
1009 u32 tmp = RREG32(MC_SHARED_CHMAP);
1010
1011 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1012 case 0:
1013 default:
1014 return 1;
1015 case 1:
1016 return 2;
1017 case 2:
1018 return 4;
1019 case 3:
1020 return 8;
1021 }
1022}
1023
1024struct evergreen_wm_params {
1025 u32 dram_channels; /* number of dram channels */
1026 u32 yclk; /* bandwidth per dram data pin in kHz */
1027 u32 sclk; /* engine clock in kHz */
1028 u32 disp_clk; /* display clock in kHz */
1029 u32 src_width; /* viewport width */
1030 u32 active_time; /* active display time in ns */
1031 u32 blank_time; /* blank time in ns */
1032 bool interlaced; /* mode is interlaced */
1033 fixed20_12 vsc; /* vertical scale ratio */
1034 u32 num_heads; /* number of active crtcs */
1035 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
1036 u32 lb_size; /* line buffer allocated to pipe */
1037 u32 vtaps; /* vertical scaler taps */
1038};
1039
1040static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
1041{
1042 /* Calculate DRAM Bandwidth and the part allocated to display. */
1043 fixed20_12 dram_efficiency; /* 0.7 */
1044 fixed20_12 yclk, dram_channels, bandwidth;
1045 fixed20_12 a;
1046
1047 a.full = dfixed_const(1000);
1048 yclk.full = dfixed_const(wm->yclk);
1049 yclk.full = dfixed_div(yclk, a);
1050 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1051 a.full = dfixed_const(10);
1052 dram_efficiency.full = dfixed_const(7);
1053 dram_efficiency.full = dfixed_div(dram_efficiency, a);
1054 bandwidth.full = dfixed_mul(dram_channels, yclk);
1055 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
1056
1057 return dfixed_trunc(bandwidth);
1058}
1059
1060static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
1061{
1062 /* Calculate DRAM Bandwidth and the part allocated to display. */
1063 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
1064 fixed20_12 yclk, dram_channels, bandwidth;
1065 fixed20_12 a;
1066
1067 a.full = dfixed_const(1000);
1068 yclk.full = dfixed_const(wm->yclk);
1069 yclk.full = dfixed_div(yclk, a);
1070 dram_channels.full = dfixed_const(wm->dram_channels * 4);
1071 a.full = dfixed_const(10);
1072 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
1073 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
1074 bandwidth.full = dfixed_mul(dram_channels, yclk);
1075 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
1076
1077 return dfixed_trunc(bandwidth);
1078}
1079
1080static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
1081{
1082 /* Calculate the display Data return Bandwidth */
1083 fixed20_12 return_efficiency; /* 0.8 */
1084 fixed20_12 sclk, bandwidth;
1085 fixed20_12 a;
1086
1087 a.full = dfixed_const(1000);
1088 sclk.full = dfixed_const(wm->sclk);
1089 sclk.full = dfixed_div(sclk, a);
1090 a.full = dfixed_const(10);
1091 return_efficiency.full = dfixed_const(8);
1092 return_efficiency.full = dfixed_div(return_efficiency, a);
1093 a.full = dfixed_const(32);
1094 bandwidth.full = dfixed_mul(a, sclk);
1095 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
1096
1097 return dfixed_trunc(bandwidth);
1098}
1099
1100static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
1101{
1102 /* Calculate the DMIF Request Bandwidth */
1103 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
1104 fixed20_12 disp_clk, bandwidth;
1105 fixed20_12 a;
1106
1107 a.full = dfixed_const(1000);
1108 disp_clk.full = dfixed_const(wm->disp_clk);
1109 disp_clk.full = dfixed_div(disp_clk, a);
1110 a.full = dfixed_const(10);
1111 disp_clk_request_efficiency.full = dfixed_const(8);
1112 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
1113 a.full = dfixed_const(32);
1114 bandwidth.full = dfixed_mul(a, disp_clk);
1115 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
1116
1117 return dfixed_trunc(bandwidth);
1118}
1119
1120static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
1121{
1122 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
1123 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
1124 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
1125 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
1126
1127 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
1128}
1129
1130static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
1131{
1132 /* Calculate the display mode Average Bandwidth
1133 * DisplayMode should contain the source and destination dimensions,
1134 * timing, etc.
1135 */
1136 fixed20_12 bpp;
1137 fixed20_12 line_time;
1138 fixed20_12 src_width;
1139 fixed20_12 bandwidth;
1140 fixed20_12 a;
1141
1142 a.full = dfixed_const(1000);
1143 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
1144 line_time.full = dfixed_div(line_time, a);
1145 bpp.full = dfixed_const(wm->bytes_per_pixel);
1146 src_width.full = dfixed_const(wm->src_width);
1147 bandwidth.full = dfixed_mul(src_width, bpp);
1148 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
1149 bandwidth.full = dfixed_div(bandwidth, line_time);
1150
1151 return dfixed_trunc(bandwidth);
1152}
1153
1154static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
1155{
1156 /* First calcualte the latency in ns */
1157 u32 mc_latency = 2000; /* 2000 ns. */
1158 u32 available_bandwidth = evergreen_available_bandwidth(wm);
1159 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
1160 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
1161 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
1162 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
1163 (wm->num_heads * cursor_line_pair_return_time);
1164 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
1165 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
1166 fixed20_12 a, b, c;
1167
1168 if (wm->num_heads == 0)
1169 return 0;
1170
1171 a.full = dfixed_const(2);
1172 b.full = dfixed_const(1);
1173 if ((wm->vsc.full > a.full) ||
1174 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
1175 (wm->vtaps >= 5) ||
1176 ((wm->vsc.full >= a.full) && wm->interlaced))
1177 max_src_lines_per_dst_line = 4;
1178 else
1179 max_src_lines_per_dst_line = 2;
1180
1181 a.full = dfixed_const(available_bandwidth);
1182 b.full = dfixed_const(wm->num_heads);
1183 a.full = dfixed_div(a, b);
1184
1185 b.full = dfixed_const(1000);
1186 c.full = dfixed_const(wm->disp_clk);
1187 b.full = dfixed_div(c, b);
1188 c.full = dfixed_const(wm->bytes_per_pixel);
1189 b.full = dfixed_mul(b, c);
1190
1191 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
1192
1193 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
1194 b.full = dfixed_const(1000);
1195 c.full = dfixed_const(lb_fill_bw);
1196 b.full = dfixed_div(c, b);
1197 a.full = dfixed_div(a, b);
1198 line_fill_time = dfixed_trunc(a);
1199
1200 if (line_fill_time < wm->active_time)
1201 return latency;
1202 else
1203 return latency + (line_fill_time - wm->active_time);
1204
1205}
1206
1207static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
1208{
1209 if (evergreen_average_bandwidth(wm) <=
1210 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
1211 return true;
1212 else
1213 return false;
1214};
1215
1216static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
1217{
1218 if (evergreen_average_bandwidth(wm) <=
1219 (evergreen_available_bandwidth(wm) / wm->num_heads))
1220 return true;
1221 else
1222 return false;
1223};
1224
1225static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
1226{
1227 u32 lb_partitions = wm->lb_size / wm->src_width;
1228 u32 line_time = wm->active_time + wm->blank_time;
1229 u32 latency_tolerant_lines;
1230 u32 latency_hiding;
1231 fixed20_12 a;
1232
1233 a.full = dfixed_const(1);
1234 if (wm->vsc.full > a.full)
1235 latency_tolerant_lines = 1;
1236 else {
1237 if (lb_partitions <= (wm->vtaps + 1))
1238 latency_tolerant_lines = 1;
1239 else
1240 latency_tolerant_lines = 2;
1241 }
1242
1243 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1244
1245 if (evergreen_latency_watermark(wm) <= latency_hiding)
1246 return true;
1247 else
1248 return false;
1249}
1250
1251static void evergreen_program_watermarks(struct radeon_device *rdev,
1252 struct radeon_crtc *radeon_crtc,
1253 u32 lb_size, u32 num_heads)
1254{
1255 struct drm_display_mode *mode = &radeon_crtc->base.mode;
1256 struct evergreen_wm_params wm;
1257 u32 pixel_period;
1258 u32 line_time = 0;
1259 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1260 u32 priority_a_mark = 0, priority_b_mark = 0;
1261 u32 priority_a_cnt = PRIORITY_OFF;
1262 u32 priority_b_cnt = PRIORITY_OFF;
1263 u32 pipe_offset = radeon_crtc->crtc_id * 16;
1264 u32 tmp, arb_control3;
1265 fixed20_12 a, b, c;
1266
1267 if (radeon_crtc->base.enabled && num_heads && mode) {
1268 pixel_period = 1000000 / (u32)mode->clock;
1269 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1270 priority_a_cnt = 0;
1271 priority_b_cnt = 0;
1272
1273 wm.yclk = rdev->pm.current_mclk * 10;
1274 wm.sclk = rdev->pm.current_sclk * 10;
1275 wm.disp_clk = mode->clock;
1276 wm.src_width = mode->crtc_hdisplay;
1277 wm.active_time = mode->crtc_hdisplay * pixel_period;
1278 wm.blank_time = line_time - wm.active_time;
1279 wm.interlaced = false;
1280 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1281 wm.interlaced = true;
1282 wm.vsc = radeon_crtc->vsc;
1283 wm.vtaps = 1;
1284 if (radeon_crtc->rmx_type != RMX_OFF)
1285 wm.vtaps = 2;
1286 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1287 wm.lb_size = lb_size;
1288 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1289 wm.num_heads = num_heads;
1290
1291 /* set for high clocks */
1292 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1293 /* set for low clocks */
1294 /* wm.yclk = low clk; wm.sclk = low clk */
1295 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1296
1297 /* possibly force display priority to high */
1298 /* should really do this at mode validation time... */
1299 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1300 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1301 !evergreen_check_latency_hiding(&wm) ||
1302 (rdev->disp_priority == 2)) {
92bdfd4a 1303 DRM_DEBUG_KMS("force priority to high\n");
f9d9c362
AD		 1304 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1305 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1306 }
1307
1308 a.full = dfixed_const(1000);
1309 b.full = dfixed_const(mode->clock);
1310 b.full = dfixed_div(b, a);
1311 c.full = dfixed_const(latency_watermark_a);
1312 c.full = dfixed_mul(c, b);
1313 c.full = dfixed_mul(c, radeon_crtc->hsc);
1314 c.full = dfixed_div(c, a);
1315 a.full = dfixed_const(16);
1316 c.full = dfixed_div(c, a);
1317 priority_a_mark = dfixed_trunc(c);
1318 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1319
1320 a.full = dfixed_const(1000);
1321 b.full = dfixed_const(mode->clock);
1322 b.full = dfixed_div(b, a);
1323 c.full = dfixed_const(latency_watermark_b);
1324 c.full = dfixed_mul(c, b);
1325 c.full = dfixed_mul(c, radeon_crtc->hsc);
1326 c.full = dfixed_div(c, a);
1327 a.full = dfixed_const(16);
1328 c.full = dfixed_div(c, a);
1329 priority_b_mark = dfixed_trunc(c);
1330 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1331 }
1332
1333 /* select wm A */
1334 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1335 tmp = arb_control3;
1336 tmp &= ~LATENCY_WATERMARK_MASK(3);
1337 tmp |= LATENCY_WATERMARK_MASK(1);
1338 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1339 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1340 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1341 LATENCY_HIGH_WATERMARK(line_time)));
1342 /* select wm B */
1343 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1344 tmp &= ~LATENCY_WATERMARK_MASK(3);
1345 tmp |= LATENCY_WATERMARK_MASK(2);
1346 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1347 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1348 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1349 LATENCY_HIGH_WATERMARK(line_time)));
1350 /* restore original selection */
1351 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1352
1353 /* write the priority marks */
1354 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1355 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1356
1357}
1358
377edc8b
AD		 1359/**
1360 * evergreen_bandwidth_update - update display watermarks callback.
1361 *
1362 * @rdev: radeon_device pointer
1363 *
1364 * Update the display watermarks based on the requested mode(s)
1365 * (evergreen+).
1366 */
0ca2ab52 1367void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 1368{
f9d9c362
AD		 1369 struct drm_display_mode *mode0 = NULL;
1370 struct drm_display_mode *mode1 = NULL;
1371 u32 num_heads = 0, lb_size;
1372 int i;
1373
1374 radeon_update_display_priority(rdev);
1375
1376 for (i = 0; i < rdev->num_crtc; i++) {
1377 if (rdev->mode_info.crtcs[i]->base.enabled)
1378 num_heads++;
1379 }
1380 for (i = 0; i < rdev->num_crtc; i += 2) {
1381 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1382 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1383 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1384 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1385 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1386 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1387 }
bcc1c2a1
AD		 1388}
1389
377edc8b
AD		 1390/**
1391 * evergreen_mc_wait_for_idle - wait for MC idle callback.
1392 *
1393 * @rdev: radeon_device pointer
1394 *
1395 * Wait for the MC (memory controller) to be idle.
1396 * (evergreen+).
1397 * Returns 0 if the MC is idle, -1 if not.
1398 */
b9952a8a 1399int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 1400{
1401 unsigned i;
1402 u32 tmp;
1403
1404 for (i = 0; i < rdev->usec_timeout; i++) {
1405 /* read MC_STATUS */
1406 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1407 if (!tmp)
1408 return 0;
1409 udelay(1);
1410 }
1411 return -1;
1412}
1413
1414/*
1415 * GART
1416 */
0fcdb61e
AD		 1417void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1418{
1419 unsigned i;
1420 u32 tmp;
1421
6f2f48a9
AD		 1422 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1423
0fcdb61e
AD		 1424 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1425 for (i = 0; i < rdev->usec_timeout; i++) {
1426 /* read MC_STATUS */
1427 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1428 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1429 if (tmp == 2) {
1430 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1431 return;
1432 }
1433 if (tmp) {
1434 return;
1435 }
1436 udelay(1);
1437 }
1438}
1439
1109ca09 1440static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 1441{
1442 u32 tmp;
0fcdb61e 1443 int r;
bcc1c2a1 1444
c9a1be96 1445 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 1446 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1447 return -EINVAL;
1448 }
1449 r = radeon_gart_table_vram_pin(rdev);
1450 if (r)
1451 return r;
82568565 1452 radeon_gart_restore(rdev);
bcc1c2a1
AD		 1453 /* Setup L2 cache */
1454 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1455 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1456 EFFECTIVE_L2_QUEUE_SIZE(7));
1457 WREG32(VM_L2_CNTL2, 0);
1458 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1459 /* Setup TLB control */
1460 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1461 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1462 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1463 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 1464 if (rdev->flags & RADEON_IS_IGP) {
1465 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1466 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1467 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1468 } else {
1469 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1470 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1471 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 1472 if ((rdev->family == CHIP_JUNIPER) ||
1473 (rdev->family == CHIP_CYPRESS) ||
1474 (rdev->family == CHIP_HEMLOCK) ||
1475 (rdev->family == CHIP_BARTS))
1476 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
8aeb96f8 1477 }
bcc1c2a1
AD		 1478 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1479 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1480 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1481 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1482 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1483 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1484 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1485 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1486 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1487 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1488 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 1489 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 1490
0fcdb61e 1491 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1492 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1493 (unsigned)(rdev->mc.gtt_size >> 20),
1494 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 1495 rdev->gart.ready = true;
1496 return 0;
1497}
1498
1109ca09 1499static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
bcc1c2a1
AD		 1500{
1501 u32 tmp;
bcc1c2a1
AD		 1502
1503 /* Disable all tables */
0fcdb61e
AD		 1504 WREG32(VM_CONTEXT0_CNTL, 0);
1505 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1506
1507 /* Setup L2 cache */
1508 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1509 EFFECTIVE_L2_QUEUE_SIZE(7));
1510 WREG32(VM_L2_CNTL2, 0);
1511 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1512 /* Setup TLB control */
1513 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1514 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1515 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1516 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1517 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1518 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1519 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1520 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 1521 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 1522}
1523
1109ca09 1524static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
bcc1c2a1
AD		 1525{
1526 evergreen_pcie_gart_disable(rdev);
1527 radeon_gart_table_vram_free(rdev);
1528 radeon_gart_fini(rdev);
1529}
1530
1531
1109ca09 1532static void evergreen_agp_enable(struct radeon_device *rdev)
bcc1c2a1
AD		 1533{
1534 u32 tmp;
bcc1c2a1
AD		 1535
1536 /* Setup L2 cache */
1537 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1538 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1539 EFFECTIVE_L2_QUEUE_SIZE(7));
1540 WREG32(VM_L2_CNTL2, 0);
1541 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1542 /* Setup TLB control */
1543 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1544 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1545 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1546 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1547 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1548 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1549 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1550 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1551 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1552 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1553 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 1554 WREG32(VM_CONTEXT0_CNTL, 0);
1555 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1556}
1557
b9952a8a 1558void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 1559{
62444b74
AD		 1560 u32 crtc_enabled, tmp, frame_count, blackout;
1561 int i, j;
1562
bcc1c2a1
AD		 1563 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1564 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
bcc1c2a1 1565
62444b74 1566 /* disable VGA render */
bcc1c2a1 1567 WREG32(VGA_RENDER_CONTROL, 0);
62444b74
AD		 1568 /* blank the display controllers */
1569 for (i = 0; i < rdev->num_crtc; i++) {
1570 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1571 if (crtc_enabled) {
1572 save->crtc_enabled[i] = true;
1573 if (ASIC_IS_DCE6(rdev)) {
1574 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1575 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1576 radeon_wait_for_vblank(rdev, i);
1577 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
bb588820 1578 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1579 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
bb588820 1580 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1581 }
1582 } else {
1583 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1584 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1585 radeon_wait_for_vblank(rdev, i);
1586 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
bb588820 1587 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1588 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
bb588820 1589 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1590 }
1591 }
1592 /* wait for the next frame */
1593 frame_count = radeon_get_vblank_counter(rdev, i);
1594 for (j = 0; j < rdev->usec_timeout; j++) {
1595 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1596 break;
1597 udelay(1);
1598 }
804cc4a0
AD		 1599 } else {
1600 save->crtc_enabled[i] = false;
62444b74 1601 }
18007401 1602 }
bcc1c2a1 1603
62444b74
AD		 1604 radeon_mc_wait_for_idle(rdev);
1605
1606 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1607 if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1608 /* Block CPU access */
1609 WREG32(BIF_FB_EN, 0);
1610 /* blackout the MC */
1611 blackout &= ~BLACKOUT_MODE_MASK;
1612 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
b7eff394 1613 }
ed39fadd
AD		 1614 /* wait for the MC to settle */
1615 udelay(100);
bcc1c2a1
AD		 1616}
1617
b9952a8a 1618void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1 1619{
62444b74
AD		 1620 u32 tmp, frame_count;
1621 int i, j;
18007401 1622
62444b74
AD		 1623 /* update crtc base addresses */
1624 for (i = 0; i < rdev->num_crtc; i++) {
1625 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 1626 upper_32_bits(rdev->mc.vram_start));
62444b74 1627 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
18007401 1628 upper_32_bits(rdev->mc.vram_start));
62444b74 1629 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401 1630 (u32)rdev->mc.vram_start);
62444b74 1631 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
18007401
AD		 1632 (u32)rdev->mc.vram_start);
1633 }
bcc1c2a1
AD		 1634 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1635 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
62444b74
AD		 1636
1637 /* unblackout the MC */
1638 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1639 tmp &= ~BLACKOUT_MODE_MASK;
1640 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1641 /* allow CPU access */
1642 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1643
1644 for (i = 0; i < rdev->num_crtc; i++) {
695ddeb4 1645 if (save->crtc_enabled[i]) {
62444b74
AD		 1646 if (ASIC_IS_DCE6(rdev)) {
1647 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1648 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
bb588820 1649 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1650 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
bb588820 1651 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1652 } else {
1653 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1654 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
bb588820 1655 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
62444b74 1656 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
bb588820 1657 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
62444b74
AD		 1658 }
1659 /* wait for the next frame */
1660 frame_count = radeon_get_vblank_counter(rdev, i);
1661 for (j = 0; j < rdev->usec_timeout; j++) {
1662 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1663 break;
1664 udelay(1);
1665 }
1666 }
1667 }
1668 /* Unlock vga access */
bcc1c2a1
AD		 1669 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1670 mdelay(1);
bcc1c2a1
AD		 1671 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1672}
1673
755d819e 1674void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1675{
1676 struct evergreen_mc_save save;
1677 u32 tmp;
1678 int i, j;
1679
1680 /* Initialize HDP */
1681 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1682 WREG32((0x2c14 + j), 0x00000000);
1683 WREG32((0x2c18 + j), 0x00000000);
1684 WREG32((0x2c1c + j), 0x00000000);
1685 WREG32((0x2c20 + j), 0x00000000);
1686 WREG32((0x2c24 + j), 0x00000000);
1687 }
1688 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1689
1690 evergreen_mc_stop(rdev, &save);
1691 if (evergreen_mc_wait_for_idle(rdev)) {
1692 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1693 }
1694 /* Lockout access through VGA aperture*/
1695 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1696 /* Update configuration */
1697 if (rdev->flags & RADEON_IS_AGP) {
1698 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1699 /* VRAM before AGP */
1700 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1701 rdev->mc.vram_start >> 12);
1702 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1703 rdev->mc.gtt_end >> 12);
1704 } else {
1705 /* VRAM after AGP */
1706 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1707 rdev->mc.gtt_start >> 12);
1708 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1709 rdev->mc.vram_end >> 12);
1710 }
1711 } else {
1712 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1713 rdev->mc.vram_start >> 12);
1714 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1715 rdev->mc.vram_end >> 12);
1716 }
3b9832f6 1717 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
05b3ef69
AD		 1718 /* llano/ontario only */
1719 if ((rdev->family == CHIP_PALM) ||
1720 (rdev->family == CHIP_SUMO) ||
1721 (rdev->family == CHIP_SUMO2)) {
b4183e30
AD		 1722 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1723 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1724 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1725 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1726 }
bcc1c2a1
AD		 1727 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1728 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1729 WREG32(MC_VM_FB_LOCATION, tmp);
1730 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1731 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1732 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1733 if (rdev->flags & RADEON_IS_AGP) {
1734 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1735 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1736 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1737 } else {
1738 WREG32(MC_VM_AGP_BASE, 0);
1739 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1740 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1741 }
1742 if (evergreen_mc_wait_for_idle(rdev)) {
1743 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1744 }
1745 evergreen_mc_resume(rdev, &save);
1746 /* we need to own VRAM, so turn off the VGA renderer here
1747 * to stop it overwriting our objects */
1748 rv515_vga_render_disable(rdev);
1749}
1750
bcc1c2a1
AD		 1751/*
1752 * CP.
1753 */
12920591
AD		 1754void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1755{
876dc9f3 1756 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 1757 u32 next_rptr;
7b1f2485 1758
12920591 1759 /* set to DX10/11 mode */
e32eb50d
CK		 1760 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1761 radeon_ring_write(ring, 1);
45df6803
CK		 1762
1763 if (ring->rptr_save_reg) {
89d35807 1764 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 1765 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1766 radeon_ring_write(ring, ((ring->rptr_save_reg -
1767 PACKET3_SET_CONFIG_REG_START) >> 2));
1768 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1769 } else if (rdev->wb.enabled) {
1770 next_rptr = ring->wptr + 5 + 4;
1771 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1772 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1773 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1774 radeon_ring_write(ring, next_rptr);
1775 radeon_ring_write(ring, 0);
45df6803
CK		 1776 }
1777
e32eb50d
CK		 1778 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1779 radeon_ring_write(ring,
0f234f5f
AD		 1780#ifdef __BIG_ENDIAN
1781 (2 << 0) |
1782#endif
1783 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 1784 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1785 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 1786}
1787
bcc1c2a1
AD		 1788
1789static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1790{
fe251e2f
AD		 1791 const __be32 *fw_data;
1792 int i;
1793
1794 if (!rdev->me_fw || !rdev->pfp_fw)
1795 return -EINVAL;
bcc1c2a1 1796
fe251e2f 1797 r700_cp_stop(rdev);
0f234f5f
AD		 1798 WREG32(CP_RB_CNTL,
1799#ifdef __BIG_ENDIAN
1800 BUF_SWAP_32BIT |
1801#endif
1802 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1803
1804 fw_data = (const __be32 *)rdev->pfp_fw->data;
1805 WREG32(CP_PFP_UCODE_ADDR, 0);
1806 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1807 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1808 WREG32(CP_PFP_UCODE_ADDR, 0);
1809
1810 fw_data = (const __be32 *)rdev->me_fw->data;
1811 WREG32(CP_ME_RAM_WADDR, 0);
1812 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1813 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1814
1815 WREG32(CP_PFP_UCODE_ADDR, 0);
1816 WREG32(CP_ME_RAM_WADDR, 0);
1817 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1818 return 0;
1819}
1820
7e7b41d2
AD		 1821static int evergreen_cp_start(struct radeon_device *rdev)
1822{
e32eb50d 1823 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 1824 int r, i;
7e7b41d2
AD		 1825 uint32_t cp_me;
1826
e32eb50d 1827 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 1828 if (r) {
1829 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1830 return r;
1831 }
e32eb50d
CK		 1832 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1833 radeon_ring_write(ring, 0x1);
1834 radeon_ring_write(ring, 0x0);
1835 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1836 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1837 radeon_ring_write(ring, 0);
1838 radeon_ring_write(ring, 0);
1839 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1840
1841 cp_me = 0xff;
1842 WREG32(CP_ME_CNTL, cp_me);
1843
e32eb50d 1844 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 1845 if (r) {
1846 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1847 return r;
1848 }
2281a378
AD		 1849
1850 /* setup clear context state */
e32eb50d
CK		 1851 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1852 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 1853
1854 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 1855 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 1856
e32eb50d
CK		 1857 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1858 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 1859
1860 /* set clear context state */
e32eb50d
CK		 1861 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1862 radeon_ring_write(ring, 0);
2281a378
AD		 1863
1864 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1865 radeon_ring_write(ring, 0xc0026f00);
1866 radeon_ring_write(ring, 0x00000000);
1867 radeon_ring_write(ring, 0x00000000);
1868 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 1869
1870 /* Clear consts */
e32eb50d
CK		 1871 radeon_ring_write(ring, 0xc0036f00);
1872 radeon_ring_write(ring, 0x00000bc4);
1873 radeon_ring_write(ring, 0xffffffff);
1874 radeon_ring_write(ring, 0xffffffff);
1875 radeon_ring_write(ring, 0xffffffff);
2281a378 1876
e32eb50d
CK		 1877 radeon_ring_write(ring, 0xc0026900);
1878 radeon_ring_write(ring, 0x00000316);
1879 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1880 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 1881
e32eb50d 1882 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1883
1884 return 0;
1885}
1886
1109ca09 1887static int evergreen_cp_resume(struct radeon_device *rdev)
fe251e2f 1888{
e32eb50d 1889 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 1890 u32 tmp;
1891 u32 rb_bufsz;
1892 int r;
1893
1894 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1895 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1896 SOFT_RESET_PA |
1897 SOFT_RESET_SH |
1898 SOFT_RESET_VGT |
a49a50da 1899 SOFT_RESET_SPI |
fe251e2f
AD		 1900 SOFT_RESET_SX));
1901 RREG32(GRBM_SOFT_RESET);
1902 mdelay(15);
1903 WREG32(GRBM_SOFT_RESET, 0);
1904 RREG32(GRBM_SOFT_RESET);
1905
1906 /* Set ring buffer size */
e32eb50d 1907 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 1908 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1909#ifdef __BIG_ENDIAN
1910 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1911#endif
fe251e2f 1912 WREG32(CP_RB_CNTL, tmp);
15d3332f 1913 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1914 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 1915
1916 /* Set the write pointer delay */
1917 WREG32(CP_RB_WPTR_DELAY, 0);
1918
1919 /* Initialize the ring buffer's read and write pointers */
1920 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1921 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1922 ring->wptr = 0;
1923 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1 1924
48fc7f7e 1925 /* set the wb address whether it's enabled or not */
0f234f5f 1926 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 1927 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1928 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1929 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1930
1931 if (rdev->wb.enabled)
1932 WREG32(SCRATCH_UMSK, 0xff);
1933 else {
1934 tmp |= RB_NO_UPDATE;
1935 WREG32(SCRATCH_UMSK, 0);
1936 }
1937
fe251e2f
AD		 1938 mdelay(1);
1939 WREG32(CP_RB_CNTL, tmp);
1940
e32eb50d 1941 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 1942 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1943
e32eb50d 1944 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 1945
7e7b41d2 1946 evergreen_cp_start(rdev);
e32eb50d 1947 ring->ready = true;
f712812e 1948 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
fe251e2f 1949 if (r) {
e32eb50d 1950 ring->ready = false;
fe251e2f
AD		 1951 return r;
1952 }
1953 return 0;
1954}
bcc1c2a1
AD		 1955
1956/*
1957 * Core functions
1958 */
bcc1c2a1
AD		 1959static void evergreen_gpu_init(struct radeon_device *rdev)
1960{
416a2bd2 1961 u32 gb_addr_config;
32fcdbf4 1962 u32 mc_shared_chmap, mc_arb_ramcfg;
32fcdbf4
AD		 1963 u32 sx_debug_1;
1964 u32 smx_dc_ctl0;
1965 u32 sq_config;
1966 u32 sq_lds_resource_mgmt;
1967 u32 sq_gpr_resource_mgmt_1;
1968 u32 sq_gpr_resource_mgmt_2;
1969 u32 sq_gpr_resource_mgmt_3;
1970 u32 sq_thread_resource_mgmt;
1971 u32 sq_thread_resource_mgmt_2;
1972 u32 sq_stack_resource_mgmt_1;
1973 u32 sq_stack_resource_mgmt_2;
1974 u32 sq_stack_resource_mgmt_3;
1975 u32 vgt_cache_invalidation;
f25a5c63 1976 u32 hdp_host_path_cntl, tmp;
416a2bd2 1977 u32 disabled_rb_mask;
32fcdbf4
AD		 1978 int i, j, num_shader_engines, ps_thread_count;
1979
1980 switch (rdev->family) {
1981 case CHIP_CYPRESS:
1982 case CHIP_HEMLOCK:
1983 rdev->config.evergreen.num_ses = 2;
1984 rdev->config.evergreen.max_pipes = 4;
1985 rdev->config.evergreen.max_tile_pipes = 8;
1986 rdev->config.evergreen.max_simds = 10;
1987 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1988 rdev->config.evergreen.max_gprs = 256;
1989 rdev->config.evergreen.max_threads = 248;
1990 rdev->config.evergreen.max_gs_threads = 32;
1991 rdev->config.evergreen.max_stack_entries = 512;
1992 rdev->config.evergreen.sx_num_of_sets = 4;
1993 rdev->config.evergreen.sx_max_export_size = 256;
1994 rdev->config.evergreen.sx_max_export_pos_size = 64;
1995 rdev->config.evergreen.sx_max_export_smx_size = 192;
1996 rdev->config.evergreen.max_hw_contexts = 8;
1997 rdev->config.evergreen.sq_num_cf_insts = 2;
1998
1999 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
2000 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2001 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2002 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 2003 break;
2004 case CHIP_JUNIPER:
2005 rdev->config.evergreen.num_ses = 1;
2006 rdev->config.evergreen.max_pipes = 4;
2007 rdev->config.evergreen.max_tile_pipes = 4;
2008 rdev->config.evergreen.max_simds = 10;
2009 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
2010 rdev->config.evergreen.max_gprs = 256;
2011 rdev->config.evergreen.max_threads = 248;
2012 rdev->config.evergreen.max_gs_threads = 32;
2013 rdev->config.evergreen.max_stack_entries = 512;
2014 rdev->config.evergreen.sx_num_of_sets = 4;
2015 rdev->config.evergreen.sx_max_export_size = 256;
2016 rdev->config.evergreen.sx_max_export_pos_size = 64;
2017 rdev->config.evergreen.sx_max_export_smx_size = 192;
2018 rdev->config.evergreen.max_hw_contexts = 8;
2019 rdev->config.evergreen.sq_num_cf_insts = 2;
2020
2021 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
2022 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2023 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2024 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 2025 break;
2026 case CHIP_REDWOOD:
2027 rdev->config.evergreen.num_ses = 1;
2028 rdev->config.evergreen.max_pipes = 4;
2029 rdev->config.evergreen.max_tile_pipes = 4;
2030 rdev->config.evergreen.max_simds = 5;
2031 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
2032 rdev->config.evergreen.max_gprs = 256;
2033 rdev->config.evergreen.max_threads = 248;
2034 rdev->config.evergreen.max_gs_threads = 32;
2035 rdev->config.evergreen.max_stack_entries = 256;
2036 rdev->config.evergreen.sx_num_of_sets = 4;
2037 rdev->config.evergreen.sx_max_export_size = 256;
2038 rdev->config.evergreen.sx_max_export_pos_size = 64;
2039 rdev->config.evergreen.sx_max_export_smx_size = 192;
2040 rdev->config.evergreen.max_hw_contexts = 8;
2041 rdev->config.evergreen.sq_num_cf_insts = 2;
2042
2043 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
2044 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2045 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2046 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 2047 break;
2048 case CHIP_CEDAR:
2049 default:
2050 rdev->config.evergreen.num_ses = 1;
2051 rdev->config.evergreen.max_pipes = 2;
2052 rdev->config.evergreen.max_tile_pipes = 2;
2053 rdev->config.evergreen.max_simds = 2;
2054 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
2055 rdev->config.evergreen.max_gprs = 256;
2056 rdev->config.evergreen.max_threads = 192;
2057 rdev->config.evergreen.max_gs_threads = 16;
2058 rdev->config.evergreen.max_stack_entries = 256;
2059 rdev->config.evergreen.sx_num_of_sets = 4;
2060 rdev->config.evergreen.sx_max_export_size = 128;
2061 rdev->config.evergreen.sx_max_export_pos_size = 32;
2062 rdev->config.evergreen.sx_max_export_smx_size = 96;
2063 rdev->config.evergreen.max_hw_contexts = 4;
2064 rdev->config.evergreen.sq_num_cf_insts = 1;
2065
d5e455e4
AD		 2066 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
2067 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2068 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2069 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5e455e4
AD		 2070 break;
2071 case CHIP_PALM:
2072 rdev->config.evergreen.num_ses = 1;
2073 rdev->config.evergreen.max_pipes = 2;
2074 rdev->config.evergreen.max_tile_pipes = 2;
2075 rdev->config.evergreen.max_simds = 2;
2076 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
2077 rdev->config.evergreen.max_gprs = 256;
2078 rdev->config.evergreen.max_threads = 192;
2079 rdev->config.evergreen.max_gs_threads = 16;
2080 rdev->config.evergreen.max_stack_entries = 256;
2081 rdev->config.evergreen.sx_num_of_sets = 4;
2082 rdev->config.evergreen.sx_max_export_size = 128;
2083 rdev->config.evergreen.sx_max_export_pos_size = 32;
2084 rdev->config.evergreen.sx_max_export_smx_size = 96;
2085 rdev->config.evergreen.max_hw_contexts = 4;
2086 rdev->config.evergreen.sq_num_cf_insts = 1;
2087
d5c5a72f
AD		 2088 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
2089 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2090 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2091 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 2092 break;
2093 case CHIP_SUMO:
2094 rdev->config.evergreen.num_ses = 1;
2095 rdev->config.evergreen.max_pipes = 4;
bd25f078 2096 rdev->config.evergreen.max_tile_pipes = 4;
d5c5a72f
AD		 2097 if (rdev->pdev->device == 0x9648)
2098 rdev->config.evergreen.max_simds = 3;
2099 else if ((rdev->pdev->device == 0x9647) ||
2100 (rdev->pdev->device == 0x964a))
2101 rdev->config.evergreen.max_simds = 4;
2102 else
2103 rdev->config.evergreen.max_simds = 5;
2104 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
2105 rdev->config.evergreen.max_gprs = 256;
2106 rdev->config.evergreen.max_threads = 248;
2107 rdev->config.evergreen.max_gs_threads = 32;
2108 rdev->config.evergreen.max_stack_entries = 256;
2109 rdev->config.evergreen.sx_num_of_sets = 4;
2110 rdev->config.evergreen.sx_max_export_size = 256;
2111 rdev->config.evergreen.sx_max_export_pos_size = 64;
2112 rdev->config.evergreen.sx_max_export_smx_size = 192;
2113 rdev->config.evergreen.max_hw_contexts = 8;
2114 rdev->config.evergreen.sq_num_cf_insts = 2;
2115
2116 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
2117 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2118 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 2119 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 2120 break;
2121 case CHIP_SUMO2:
2122 rdev->config.evergreen.num_ses = 1;
2123 rdev->config.evergreen.max_pipes = 4;
2124 rdev->config.evergreen.max_tile_pipes = 4;
2125 rdev->config.evergreen.max_simds = 2;
2126 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
2127 rdev->config.evergreen.max_gprs = 256;
2128 rdev->config.evergreen.max_threads = 248;
2129 rdev->config.evergreen.max_gs_threads = 32;
2130 rdev->config.evergreen.max_stack_entries = 512;
2131 rdev->config.evergreen.sx_num_of_sets = 4;
2132 rdev->config.evergreen.sx_max_export_size = 256;
2133 rdev->config.evergreen.sx_max_export_pos_size = 64;
2134 rdev->config.evergreen.sx_max_export_smx_size = 192;
2135 rdev->config.evergreen.max_hw_contexts = 8;
2136 rdev->config.evergreen.sq_num_cf_insts = 2;
2137
adb68fa2
AD		 2138 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
2139 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2140 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
bd25f078 2141 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 2142 break;
2143 case CHIP_BARTS:
2144 rdev->config.evergreen.num_ses = 2;
2145 rdev->config.evergreen.max_pipes = 4;
2146 rdev->config.evergreen.max_tile_pipes = 8;
2147 rdev->config.evergreen.max_simds = 7;
2148 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
2149 rdev->config.evergreen.max_gprs = 256;
2150 rdev->config.evergreen.max_threads = 248;
2151 rdev->config.evergreen.max_gs_threads = 32;
2152 rdev->config.evergreen.max_stack_entries = 512;
2153 rdev->config.evergreen.sx_num_of_sets = 4;
2154 rdev->config.evergreen.sx_max_export_size = 256;
2155 rdev->config.evergreen.sx_max_export_pos_size = 64;
2156 rdev->config.evergreen.sx_max_export_smx_size = 192;
2157 rdev->config.evergreen.max_hw_contexts = 8;
2158 rdev->config.evergreen.sq_num_cf_insts = 2;
2159
2160 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
2161 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2162 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2163 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 2164 break;
2165 case CHIP_TURKS:
2166 rdev->config.evergreen.num_ses = 1;
2167 rdev->config.evergreen.max_pipes = 4;
2168 rdev->config.evergreen.max_tile_pipes = 4;
2169 rdev->config.evergreen.max_simds = 6;
2170 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
2171 rdev->config.evergreen.max_gprs = 256;
2172 rdev->config.evergreen.max_threads = 248;
2173 rdev->config.evergreen.max_gs_threads = 32;
2174 rdev->config.evergreen.max_stack_entries = 256;
2175 rdev->config.evergreen.sx_num_of_sets = 4;
2176 rdev->config.evergreen.sx_max_export_size = 256;
2177 rdev->config.evergreen.sx_max_export_pos_size = 64;
2178 rdev->config.evergreen.sx_max_export_smx_size = 192;
2179 rdev->config.evergreen.max_hw_contexts = 8;
2180 rdev->config.evergreen.sq_num_cf_insts = 2;
2181
2182 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
2183 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2184 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2185 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 2186 break;
2187 case CHIP_CAICOS:
2188 rdev->config.evergreen.num_ses = 1;
bd25f078 2189 rdev->config.evergreen.max_pipes = 2;
adb68fa2
AD		 2190 rdev->config.evergreen.max_tile_pipes = 2;
2191 rdev->config.evergreen.max_simds = 2;
2192 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
2193 rdev->config.evergreen.max_gprs = 256;
2194 rdev->config.evergreen.max_threads = 192;
2195 rdev->config.evergreen.max_gs_threads = 16;
2196 rdev->config.evergreen.max_stack_entries = 256;
2197 rdev->config.evergreen.sx_num_of_sets = 4;
2198 rdev->config.evergreen.sx_max_export_size = 128;
2199 rdev->config.evergreen.sx_max_export_pos_size = 32;
2200 rdev->config.evergreen.sx_max_export_smx_size = 96;
2201 rdev->config.evergreen.max_hw_contexts = 4;
2202 rdev->config.evergreen.sq_num_cf_insts = 1;
2203
32fcdbf4
AD		 2204 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
2205 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
2206 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 2207 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 2208 break;
2209 }
2210
2211 /* Initialize HDP */
2212 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2213 WREG32((0x2c14 + j), 0x00000000);
2214 WREG32((0x2c18 + j), 0x00000000);
2215 WREG32((0x2c1c + j), 0x00000000);
2216 WREG32((0x2c20 + j), 0x00000000);
2217 WREG32((0x2c24 + j), 0x00000000);
2218 }
2219
2220 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
2221
d054ac16
AD		 2222 evergreen_fix_pci_max_read_req_size(rdev);
2223
32fcdbf4 2224 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
05b3ef69
AD		 2225 if ((rdev->family == CHIP_PALM) ||
2226 (rdev->family == CHIP_SUMO) ||
2227 (rdev->family == CHIP_SUMO2))
d9282fca
AD		 2228 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
2229 else
2230 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4 2231
1aa52bd3
AD		 2232 /* setup tiling info dword. gb_addr_config is not adequate since it does
2233 * not have bank info, so create a custom tiling dword.
2234 * bits 3:0 num_pipes
2235 * bits 7:4 num_banks
2236 * bits 11:8 group_size
2237 * bits 15:12 row_size
2238 */
2239 rdev->config.evergreen.tile_config = 0;
2240 switch (rdev->config.evergreen.max_tile_pipes) {
2241 case 1:
2242 default:
2243 rdev->config.evergreen.tile_config |= (0 << 0);
2244 break;
2245 case 2:
2246 rdev->config.evergreen.tile_config |= (1 << 0);
2247 break;
2248 case 4:
2249 rdev->config.evergreen.tile_config |= (2 << 0);
2250 break;
2251 case 8:
2252 rdev->config.evergreen.tile_config |= (3 << 0);
2253 break;
2254 }
d698a34d 2255 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 2256 if (rdev->flags & RADEON_IS_IGP)
d698a34d 2257 rdev->config.evergreen.tile_config |= 1 << 4;
29d65406 2258 else {
c8d15edc
AD		 2259 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
2260 case 0: /* four banks */
29d65406 2261 rdev->config.evergreen.tile_config |= 0 << 4;
c8d15edc
AD		 2262 break;
2263 case 1: /* eight banks */
2264 rdev->config.evergreen.tile_config |= 1 << 4;
2265 break;
2266 case 2: /* sixteen banks */
2267 default:
2268 rdev->config.evergreen.tile_config |= 2 << 4;
2269 break;
2270 }
29d65406 2271 }
416a2bd2 2272 rdev->config.evergreen.tile_config |= 0 << 8;
1aa52bd3
AD		 2273 rdev->config.evergreen.tile_config |=
2274 ((gb_addr_config & 0x30000000) >> 28) << 12;
2275
416a2bd2 2276 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
32fcdbf4 2277
416a2bd2
AD		 2278 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
2279 u32 efuse_straps_4;
2280 u32 efuse_straps_3;
32fcdbf4 2281
416a2bd2
AD		 2282 WREG32(RCU_IND_INDEX, 0x204);
2283 efuse_straps_4 = RREG32(RCU_IND_DATA);
2284 WREG32(RCU_IND_INDEX, 0x203);
2285 efuse_straps_3 = RREG32(RCU_IND_DATA);
2286 tmp = (((efuse_straps_4 & 0xf) << 4) |
2287 ((efuse_straps_3 & 0xf0000000) >> 28));
2288 } else {
2289 tmp = 0;
2290 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2291 u32 rb_disable_bitmap;
2292
2293 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2294 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2295 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2296 tmp <<= 4;
2297 tmp |= rb_disable_bitmap;
32fcdbf4 2298 }
416a2bd2
AD		 2299 }
2300 /* enabled rb are just the one not disabled :) */
2301 disabled_rb_mask = tmp;
cedb655a
AD		 2302 tmp = 0;
2303 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
2304 tmp |= (1 << i);
2305 /* if all the backends are disabled, fix it up here */
2306 if ((disabled_rb_mask & tmp) == tmp) {
2307 for (i = 0; i < rdev->config.evergreen.max_backends; i++)
2308 disabled_rb_mask &= ~(1 << i);
2309 }
32fcdbf4 2310
416a2bd2
AD		 2311 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2312 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
32fcdbf4 2313
416a2bd2
AD		 2314 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2315 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2316 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
233d1ad5 2317 WREG32(DMA_TILING_CONFIG, gb_addr_config);
9a21059d
CK		 2318 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
2319 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2320 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
32fcdbf4 2321
f7eb9730
AD		 2322 if ((rdev->config.evergreen.max_backends == 1) &&
2323 (rdev->flags & RADEON_IS_IGP)) {
2324 if ((disabled_rb_mask & 3) == 1) {
2325 /* RB0 disabled, RB1 enabled */
2326 tmp = 0x11111111;
2327 } else {
2328 /* RB1 disabled, RB0 enabled */
2329 tmp = 0x00000000;
2330 }
2331 } else {
2332 tmp = gb_addr_config & NUM_PIPES_MASK;
2333 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2334 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2335 }
416a2bd2 2336 WREG32(GB_BACKEND_MAP, tmp);
32fcdbf4
AD		 2337
2338 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2339 WREG32(CGTS_TCC_DISABLE, 0);
2340 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2341 WREG32(CGTS_USER_TCC_DISABLE, 0);
2342
2343 /* set HW defaults for 3D engine */
2344 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2345 ROQ_IB2_START(0x2b)));
2346
2347 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2348
2349 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2350 SYNC_GRADIENT |
2351 SYNC_WALKER |
2352 SYNC_ALIGNER));
2353
2354 sx_debug_1 = RREG32(SX_DEBUG_1);
2355 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2356 WREG32(SX_DEBUG_1, sx_debug_1);
2357
2358
2359 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2360 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2361 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2362 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2363
b866d133
AD		 2364 if (rdev->family <= CHIP_SUMO2)
2365 WREG32(SMX_SAR_CTL0, 0x00010000);
2366
32fcdbf4
AD		 2367 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2368 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2369 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2370
2371 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2372 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2373 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2374
2375 WREG32(VGT_NUM_INSTANCES, 1);
2376 WREG32(SPI_CONFIG_CNTL, 0);
2377 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2378 WREG32(CP_PERFMON_CNTL, 0);
2379
2380 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2381 FETCH_FIFO_HIWATER(0x4) |
2382 DONE_FIFO_HIWATER(0xe0) |
2383 ALU_UPDATE_FIFO_HIWATER(0x8)));
2384
2385 sq_config = RREG32(SQ_CONFIG);
2386 sq_config &= ~(PS_PRIO(3) |
2387 VS_PRIO(3) |
2388 GS_PRIO(3) |
2389 ES_PRIO(3));
2390 sq_config |= (VC_ENABLE |
2391 EXPORT_SRC_C |
2392 PS_PRIO(0) |
2393 VS_PRIO(1) |
2394 GS_PRIO(2) |
2395 ES_PRIO(3));
2396
d5e455e4
AD		 2397 switch (rdev->family) {
2398 case CHIP_CEDAR:
2399 case CHIP_PALM:
d5c5a72f
AD		 2400 case CHIP_SUMO:
2401 case CHIP_SUMO2:
adb68fa2 2402 case CHIP_CAICOS:
32fcdbf4
AD		 2403 /* no vertex cache */
2404 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 2405 break;
2406 default:
2407 break;
2408 }
32fcdbf4
AD		 2409
2410 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2411
2412 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2413 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2414 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2415 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2416 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2417 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2418 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2419
d5e455e4
AD		 2420 switch (rdev->family) {
2421 case CHIP_CEDAR:
2422 case CHIP_PALM:
d5c5a72f
AD		 2423 case CHIP_SUMO:
2424 case CHIP_SUMO2:
32fcdbf4 2425 ps_thread_count = 96;
d5e455e4
AD		 2426 break;
2427 default:
32fcdbf4 2428 ps_thread_count = 128;
d5e455e4
AD		 2429 break;
2430 }
32fcdbf4
AD		 2431
2432 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2433 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2434 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2435 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2436 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2437 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2438
2439 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2440 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2441 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2442 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2443 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2444 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2445
2446 WREG32(SQ_CONFIG, sq_config);
2447 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2448 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2449 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2450 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2451 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2452 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2453 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2454 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2455 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2456 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2457
2458 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2459 FORCE_EOV_MAX_REZ_CNT(255)));
2460
d5e455e4
AD		 2461 switch (rdev->family) {
2462 case CHIP_CEDAR:
2463 case CHIP_PALM:
d5c5a72f
AD		 2464 case CHIP_SUMO:
2465 case CHIP_SUMO2:
adb68fa2 2466 case CHIP_CAICOS:
32fcdbf4 2467 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2468 break;
2469 default:
32fcdbf4 2470 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2471 break;
2472 }
32fcdbf4
AD		 2473 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2474 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2475
2476 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2477 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2478 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2479
60a4a3e0
AD		 2480 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2481 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2482
32fcdbf4
AD		 2483 WREG32(CB_PERF_CTR0_SEL_0, 0);
2484 WREG32(CB_PERF_CTR0_SEL_1, 0);
2485 WREG32(CB_PERF_CTR1_SEL_0, 0);
2486 WREG32(CB_PERF_CTR1_SEL_1, 0);
2487 WREG32(CB_PERF_CTR2_SEL_0, 0);
2488 WREG32(CB_PERF_CTR2_SEL_1, 0);
2489 WREG32(CB_PERF_CTR3_SEL_0, 0);
2490 WREG32(CB_PERF_CTR3_SEL_1, 0);
2491
60a4a3e0
AD		 2492 /* clear render buffer base addresses */
2493 WREG32(CB_COLOR0_BASE, 0);
2494 WREG32(CB_COLOR1_BASE, 0);
2495 WREG32(CB_COLOR2_BASE, 0);
2496 WREG32(CB_COLOR3_BASE, 0);
2497 WREG32(CB_COLOR4_BASE, 0);
2498 WREG32(CB_COLOR5_BASE, 0);
2499 WREG32(CB_COLOR6_BASE, 0);
2500 WREG32(CB_COLOR7_BASE, 0);
2501 WREG32(CB_COLOR8_BASE, 0);
2502 WREG32(CB_COLOR9_BASE, 0);
2503 WREG32(CB_COLOR10_BASE, 0);
2504 WREG32(CB_COLOR11_BASE, 0);
2505
2506 /* set the shader const cache sizes to 0 */
2507 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2508 WREG32(i, 0);
2509 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2510 WREG32(i, 0);
2511
f25a5c63
AD		 2512 tmp = RREG32(HDP_MISC_CNTL);
2513 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2514 WREG32(HDP_MISC_CNTL, tmp);
2515
32fcdbf4
AD		 2516 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2517 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2518
2519 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2520
2521 udelay(50);
2522
bcc1c2a1
AD		 2523}
2524
2525int evergreen_mc_init(struct radeon_device *rdev)
2526{
bcc1c2a1
AD		 2527 u32 tmp;
2528 int chansize, numchan;
bcc1c2a1
AD		 2529
2530 /* Get VRAM informations */
2531 rdev->mc.vram_is_ddr = true;
05b3ef69
AD		 2532 if ((rdev->family == CHIP_PALM) ||
2533 (rdev->family == CHIP_SUMO) ||
2534 (rdev->family == CHIP_SUMO2))
8208441b
AD		 2535 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2536 else
2537 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 2538 if (tmp & CHANSIZE_OVERRIDE) {
2539 chansize = 16;
2540 } else if (tmp & CHANSIZE_MASK) {
2541 chansize = 64;
2542 } else {
2543 chansize = 32;
2544 }
2545 tmp = RREG32(MC_SHARED_CHMAP);
2546 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2547 case 0:
2548 default:
2549 numchan = 1;
2550 break;
2551 case 1:
2552 numchan = 2;
2553 break;
2554 case 2:
2555 numchan = 4;
2556 break;
2557 case 3:
2558 numchan = 8;
2559 break;
2560 }
2561 rdev->mc.vram_width = numchan * chansize;
2562 /* Could aper size report 0 ? */
01d73a69
JC		 2563 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2564 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2565 /* Setup GPU memory space */
05b3ef69
AD		 2566 if ((rdev->family == CHIP_PALM) ||
2567 (rdev->family == CHIP_SUMO) ||
2568 (rdev->family == CHIP_SUMO2)) {
6eb18f8b
AD		 2569 /* size in bytes on fusion */
2570 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2571 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2572 } else {
05b3ef69 2573 /* size in MB on evergreen/cayman/tn */
6eb18f8b
AD		 2574 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2575 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2576 }
51e5fcd3 2577 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2578 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2579 radeon_update_bandwidth_info(rdev);
2580
bcc1c2a1
AD		 2581 return 0;
2582}
d594e46a 2583
187e3593 2584void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
bcc1c2a1 2585{
64c56e8c 2586 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
747943ea 2587 RREG32(GRBM_STATUS));
64c56e8c 2588 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
747943ea 2589 RREG32(GRBM_STATUS_SE0));
64c56e8c 2590 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
747943ea 2591 RREG32(GRBM_STATUS_SE1));
64c56e8c 2592 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
747943ea 2593 RREG32(SRBM_STATUS));
a65a4369
AD		 2594 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",
2595 RREG32(SRBM_STATUS2));
440a7cd8
JG		 2596 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2597 RREG32(CP_STALLED_STAT1));
2598 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2599 RREG32(CP_STALLED_STAT2));
2600 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
2601 RREG32(CP_BUSY_STAT));
2602 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2603 RREG32(CP_STAT));
eaaa6983
JG		 2604 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2605 RREG32(DMA_STATUS_REG));
168757ea
AD		 2606 if (rdev->family >= CHIP_CAYMAN) {
2607 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
2608 RREG32(DMA_STATUS_REG + 0x800));
2609 }
0ecebb9e
AD		 2610}
2611
168757ea 2612bool evergreen_is_display_hung(struct radeon_device *rdev)
0ecebb9e 2613{
a65a4369
AD		 2614 u32 crtc_hung = 0;
2615 u32 crtc_status[6];
2616 u32 i, j, tmp;
2617
2618 for (i = 0; i < rdev->num_crtc; i++) {
2619 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
2620 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2621 crtc_hung |= (1 << i);
2622 }
2623 }
2624
2625 for (j = 0; j < 10; j++) {
2626 for (i = 0; i < rdev->num_crtc; i++) {
2627 if (crtc_hung & (1 << i)) {
2628 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2629 if (tmp != crtc_status[i])
2630 crtc_hung &= ~(1 << i);
2631 }
2632 }
2633 if (crtc_hung == 0)
2634 return false;
2635 udelay(100);
2636 }
2637
2638 return true;
2639}
2640
2641static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
2642{
2643 u32 reset_mask = 0;
b7630473 2644 u32 tmp;
0ecebb9e 2645
a65a4369
AD		 2646 /* GRBM_STATUS */
2647 tmp = RREG32(GRBM_STATUS);
2648 if (tmp & (PA_BUSY | SC_BUSY |
2649 SH_BUSY | SX_BUSY |
2650 TA_BUSY | VGT_BUSY |
2651 DB_BUSY | CB_BUSY |
2652 SPI_BUSY | VGT_BUSY_NO_DMA))
2653 reset_mask |= RADEON_RESET_GFX;
2654
2655 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2656 CP_BUSY | CP_COHERENCY_BUSY))
2657 reset_mask |= RADEON_RESET_CP;
2658
2659 if (tmp & GRBM_EE_BUSY)
2660 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
19fc42ed 2661
a65a4369
AD		 2662 /* DMA_STATUS_REG */
2663 tmp = RREG32(DMA_STATUS_REG);
2664 if (!(tmp & DMA_IDLE))
2665 reset_mask |= RADEON_RESET_DMA;
2666
2667 /* SRBM_STATUS2 */
2668 tmp = RREG32(SRBM_STATUS2);
2669 if (tmp & DMA_BUSY)
2670 reset_mask |= RADEON_RESET_DMA;
2671
2672 /* SRBM_STATUS */
2673 tmp = RREG32(SRBM_STATUS);
2674 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2675 reset_mask |= RADEON_RESET_RLC;
2676
2677 if (tmp & IH_BUSY)
2678 reset_mask |= RADEON_RESET_IH;
2679
2680 if (tmp & SEM_BUSY)
2681 reset_mask |= RADEON_RESET_SEM;
2682
2683 if (tmp & GRBM_RQ_PENDING)
2684 reset_mask |= RADEON_RESET_GRBM;
2685
2686 if (tmp & VMC_BUSY)
2687 reset_mask |= RADEON_RESET_VMC;
2688
2689 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2690 MCC_BUSY | MCD_BUSY))
2691 reset_mask |= RADEON_RESET_MC;
2692
2693 if (evergreen_is_display_hung(rdev))
2694 reset_mask |= RADEON_RESET_DISPLAY;
2695
2696 /* VM_L2_STATUS */
2697 tmp = RREG32(VM_L2_STATUS);
2698 if (tmp & L2_BUSY)
2699 reset_mask |= RADEON_RESET_VMC;
2700
d808fc88
AD		 2701 /* Skip MC reset as it's mostly likely not hung, just busy */
2702 if (reset_mask & RADEON_RESET_MC) {
2703 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
2704 reset_mask &= ~RADEON_RESET_MC;
2705 }
2706
a65a4369
AD		 2707 return reset_mask;
2708}
2709
2710static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2711{
2712 struct evergreen_mc_save save;
2713 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2714 u32 tmp;
19fc42ed 2715
0ecebb9e 2716 if (reset_mask == 0)
a65a4369 2717 return;
0ecebb9e
AD		 2718
2719 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2720
b7630473
AD		 2721 evergreen_print_gpu_status_regs(rdev);
2722
b7630473
AD		 2723 /* Disable CP parsing/prefetching */
2724 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2725
2726 if (reset_mask & RADEON_RESET_DMA) {
2727 /* Disable DMA */
2728 tmp = RREG32(DMA_RB_CNTL);
2729 tmp &= ~DMA_RB_ENABLE;
2730 WREG32(DMA_RB_CNTL, tmp);
2731 }
2732
b21b6e7a
AD		 2733 udelay(50);
2734
2735 evergreen_mc_stop(rdev, &save);
2736 if (evergreen_mc_wait_for_idle(rdev)) {
2737 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2738 }
2739
b7630473
AD		 2740 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
2741 grbm_soft_reset |= SOFT_RESET_DB |
2742 SOFT_RESET_CB |
2743 SOFT_RESET_PA |
2744 SOFT_RESET_SC |
2745 SOFT_RESET_SPI |
2746 SOFT_RESET_SX |
2747 SOFT_RESET_SH |
2748 SOFT_RESET_TC |
2749 SOFT_RESET_TA |
2750 SOFT_RESET_VC |
2751 SOFT_RESET_VGT;
2752 }
2753
2754 if (reset_mask & RADEON_RESET_CP) {
2755 grbm_soft_reset |= SOFT_RESET_CP |
2756 SOFT_RESET_VGT;
2757
2758 srbm_soft_reset |= SOFT_RESET_GRBM;
2759 }
0ecebb9e
AD		 2760
2761 if (reset_mask & RADEON_RESET_DMA)
b7630473
AD		 2762 srbm_soft_reset |= SOFT_RESET_DMA;
2763
a65a4369
AD		 2764 if (reset_mask & RADEON_RESET_DISPLAY)
2765 srbm_soft_reset |= SOFT_RESET_DC;
2766
2767 if (reset_mask & RADEON_RESET_RLC)
2768 srbm_soft_reset |= SOFT_RESET_RLC;
2769
2770 if (reset_mask & RADEON_RESET_SEM)
2771 srbm_soft_reset |= SOFT_RESET_SEM;
2772
2773 if (reset_mask & RADEON_RESET_IH)
2774 srbm_soft_reset |= SOFT_RESET_IH;
2775
2776 if (reset_mask & RADEON_RESET_GRBM)
2777 srbm_soft_reset |= SOFT_RESET_GRBM;
2778
2779 if (reset_mask & RADEON_RESET_VMC)
2780 srbm_soft_reset |= SOFT_RESET_VMC;
2781
24178ec4
AD		 2782 if (!(rdev->flags & RADEON_IS_IGP)) {
2783 if (reset_mask & RADEON_RESET_MC)
2784 srbm_soft_reset |= SOFT_RESET_MC;
2785 }
a65a4369 2786
b7630473
AD		 2787 if (grbm_soft_reset) {
2788 tmp = RREG32(GRBM_SOFT_RESET);
2789 tmp |= grbm_soft_reset;
2790 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2791 WREG32(GRBM_SOFT_RESET, tmp);
2792 tmp = RREG32(GRBM_SOFT_RESET);
2793
2794 udelay(50);
2795
2796 tmp &= ~grbm_soft_reset;
2797 WREG32(GRBM_SOFT_RESET, tmp);
2798 tmp = RREG32(GRBM_SOFT_RESET);
2799 }
2800
2801 if (srbm_soft_reset) {
2802 tmp = RREG32(SRBM_SOFT_RESET);
2803 tmp |= srbm_soft_reset;
2804 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2805 WREG32(SRBM_SOFT_RESET, tmp);
2806 tmp = RREG32(SRBM_SOFT_RESET);
2807
2808 udelay(50);
2809
2810 tmp &= ~srbm_soft_reset;
2811 WREG32(SRBM_SOFT_RESET, tmp);
2812 tmp = RREG32(SRBM_SOFT_RESET);
2813 }
0ecebb9e
AD		 2814
2815 /* Wait a little for things to settle down */
2816 udelay(50);
2817
747943ea 2818 evergreen_mc_resume(rdev, &save);
b7630473
AD		 2819 udelay(50);
2820
b7630473 2821 evergreen_print_gpu_status_regs(rdev);
bcc1c2a1
AD		 2822}
2823
a2d07b74 2824int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2825{
a65a4369
AD		 2826 u32 reset_mask;
2827
2828 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2829
2830 if (reset_mask)
2831 r600_set_bios_scratch_engine_hung(rdev, true);
2832
2833 evergreen_gpu_soft_reset(rdev, reset_mask);
2834
2835 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2836
2837 if (!reset_mask)
2838 r600_set_bios_scratch_engine_hung(rdev, false);
2839
2840 return 0;
747943ea
AD		 2841}
2842
123bc183
AD		 2843/**
2844 * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
2845 *
2846 * @rdev: radeon_device pointer
2847 * @ring: radeon_ring structure holding ring information
2848 *
2849 * Check if the GFX engine is locked up.
2850 * Returns true if the engine appears to be locked up, false if not.
2851 */
2852bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2853{
2854 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2855
2856 if (!(reset_mask & (RADEON_RESET_GFX |
2857 RADEON_RESET_COMPUTE |
2858 RADEON_RESET_CP))) {
2859 radeon_ring_lockup_update(ring);
2860 return false;
2861 }
2862 /* force CP activities */
2863 radeon_ring_force_activity(rdev, ring);
2864 return radeon_ring_test_lockup(rdev, ring);
2865}
2866
2867/**
2868 * evergreen_dma_is_lockup - Check if the DMA engine is locked up
2869 *
2870 * @rdev: radeon_device pointer
2871 * @ring: radeon_ring structure holding ring information
2872 *
2873 * Check if the async DMA engine is locked up.
2874 * Returns true if the engine appears to be locked up, false if not.
2875 */
2876bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2877{
2878 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2879
2880 if (!(reset_mask & RADEON_RESET_DMA)) {
2881 radeon_ring_lockup_update(ring);
2882 return false;
2883 }
2884 /* force ring activities */
2885 radeon_ring_force_activity(rdev, ring);
2886 return radeon_ring_test_lockup(rdev, ring);
2887}
2888
45f9a39b
AD		 2889/* Interrupts */
2890
2891u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2892{
46437057 2893 if (crtc >= rdev->num_crtc)
45f9a39b 2894 return 0;
46437057
AD		 2895 else
2896 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
45f9a39b
AD		 2897}
2898
2899void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2900{
2901 u32 tmp;
2902
1b37078b
AD		 2903 if (rdev->family >= CHIP_CAYMAN) {
2904 cayman_cp_int_cntl_setup(rdev, 0,
2905 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2906 cayman_cp_int_cntl_setup(rdev, 1, 0);
2907 cayman_cp_int_cntl_setup(rdev, 2, 0);
f60cbd11
AD		 2908 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2909 WREG32(CAYMAN_DMA1_CNTL, tmp);
1b37078b
AD		 2910 } else
2911 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
233d1ad5
AD		 2912 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2913 WREG32(DMA_CNTL, tmp);
45f9a39b
AD		 2914 WREG32(GRBM_INT_CNTL, 0);
2915 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2916 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2917 if (rdev->num_crtc >= 4) {
18007401
AD		 2918 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2919 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2920 }
2921 if (rdev->num_crtc >= 6) {
18007401
AD		 2922 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2923 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2924 }
45f9a39b
AD		 2925
2926 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2927 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2928 if (rdev->num_crtc >= 4) {
18007401
AD		 2929 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2930 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2931 }
2932 if (rdev->num_crtc >= 6) {
18007401
AD		 2933 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2934 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2935 }
45f9a39b 2936
05b3ef69
AD		 2937 /* only one DAC on DCE6 */
2938 if (!ASIC_IS_DCE6(rdev))
2939 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
45f9a39b
AD		 2940 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2941
2942 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2943 WREG32(DC_HPD1_INT_CONTROL, tmp);
2944 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2945 WREG32(DC_HPD2_INT_CONTROL, tmp);
2946 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2947 WREG32(DC_HPD3_INT_CONTROL, tmp);
2948 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2949 WREG32(DC_HPD4_INT_CONTROL, tmp);
2950 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2951 WREG32(DC_HPD5_INT_CONTROL, tmp);
2952 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2953 WREG32(DC_HPD6_INT_CONTROL, tmp);
2954
2955}
2956
2957int evergreen_irq_set(struct radeon_device *rdev)
2958{
2959 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 2960 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 2961 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2962 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2963 u32 grbm_int_cntl = 0;
6f34be50 2964 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
f122c610 2965 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
f60cbd11 2966 u32 dma_cntl, dma_cntl1 = 0;
45f9a39b
AD		 2967
2968 if (!rdev->irq.installed) {
fce7d61b 2969 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2970 return -EINVAL;
2971 }
2972 /* don't enable anything if the ih is disabled */
2973 if (!rdev->ih.enabled) {
2974 r600_disable_interrupts(rdev);
2975 /* force the active interrupt state to all disabled */
2976 evergreen_disable_interrupt_state(rdev);
2977 return 0;
2978 }
2979
2980 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2981 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2982 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2983 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2984 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2985 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2986
f122c610
AD		 2987 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2988 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2989 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2990 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2991 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2992 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2993
233d1ad5
AD		 2994 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2995
1b37078b
AD		 2996 if (rdev->family >= CHIP_CAYMAN) {
2997 /* enable CP interrupts on all rings */
736fc37f 2998 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2999 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
3000 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3001 }
736fc37f 3002 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
1b37078b
AD		 3003 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
3004 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
3005 }
736fc37f 3006 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
1b37078b
AD		 3007 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
3008 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
3009 }
3010 } else {
736fc37f 3011 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 3012 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
3013 cp_int_cntl |= RB_INT_ENABLE;
3014 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3015 }
45f9a39b 3016 }
1b37078b 3017
233d1ad5
AD		 3018 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3019 DRM_DEBUG("r600_irq_set: sw int dma\n");
3020 dma_cntl |= TRAP_ENABLE;
3021 }
3022
f60cbd11
AD		 3023 if (rdev->family >= CHIP_CAYMAN) {
3024 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
3025 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3026 DRM_DEBUG("r600_irq_set: sw int dma1\n");
3027 dma_cntl1 |= TRAP_ENABLE;
3028 }
3029 }
3030
6f34be50 3031 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 3032 atomic_read(&rdev->irq.pflip[0])) {
45f9a39b
AD		 3033 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
3034 crtc1 |= VBLANK_INT_MASK;
3035 }
6f34be50 3036 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 3037 atomic_read(&rdev->irq.pflip[1])) {
45f9a39b
AD		 3038 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
3039 crtc2 |= VBLANK_INT_MASK;
3040 }
6f34be50 3041 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 3042 atomic_read(&rdev->irq.pflip[2])) {
45f9a39b
AD		 3043 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
3044 crtc3 |= VBLANK_INT_MASK;
3045 }
6f34be50 3046 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 3047 atomic_read(&rdev->irq.pflip[3])) {
45f9a39b
AD		 3048 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
3049 crtc4 |= VBLANK_INT_MASK;
3050 }
6f34be50 3051 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 3052 atomic_read(&rdev->irq.pflip[4])) {
45f9a39b
AD		 3053 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
3054 crtc5 |= VBLANK_INT_MASK;
3055 }
6f34be50 3056 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 3057 atomic_read(&rdev->irq.pflip[5])) {
45f9a39b
AD		 3058 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
3059 crtc6 |= VBLANK_INT_MASK;
3060 }
3061 if (rdev->irq.hpd[0]) {
3062 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
3063 hpd1 |= DC_HPDx_INT_EN;
3064 }
3065 if (rdev->irq.hpd[1]) {
3066 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
3067 hpd2 |= DC_HPDx_INT_EN;
3068 }
3069 if (rdev->irq.hpd[2]) {
3070 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
3071 hpd3 |= DC_HPDx_INT_EN;
3072 }
3073 if (rdev->irq.hpd[3]) {
3074 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
3075 hpd4 |= DC_HPDx_INT_EN;
3076 }
3077 if (rdev->irq.hpd[4]) {
3078 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
3079 hpd5 |= DC_HPDx_INT_EN;
3080 }
3081 if (rdev->irq.hpd[5]) {
3082 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
3083 hpd6 |= DC_HPDx_INT_EN;
3084 }
f122c610
AD		 3085 if (rdev->irq.afmt[0]) {
3086 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
3087 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
3088 }
3089 if (rdev->irq.afmt[1]) {
3090 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
3091 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
3092 }
3093 if (rdev->irq.afmt[2]) {
3094 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
3095 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
3096 }
3097 if (rdev->irq.afmt[3]) {
3098 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
3099 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
3100 }
3101 if (rdev->irq.afmt[4]) {
3102 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
3103 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
3104 }
3105 if (rdev->irq.afmt[5]) {
3106 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
3107 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
3108 }
45f9a39b 3109
1b37078b
AD		 3110 if (rdev->family >= CHIP_CAYMAN) {
3111 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
3112 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
3113 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
3114 } else
3115 WREG32(CP_INT_CNTL, cp_int_cntl);
233d1ad5
AD		 3116
3117 WREG32(DMA_CNTL, dma_cntl);
3118
f60cbd11
AD		 3119 if (rdev->family >= CHIP_CAYMAN)
3120 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
3121
2031f77c 3122 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 3123
3124 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3125 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 3126 if (rdev->num_crtc >= 4) {
18007401
AD		 3127 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3128 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 3129 }
3130 if (rdev->num_crtc >= 6) {
18007401
AD		 3131 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3132 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3133 }
45f9a39b 3134
6f34be50
AD		 3135 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
3136 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 3137 if (rdev->num_crtc >= 4) {
3138 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
3139 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
3140 }
3141 if (rdev->num_crtc >= 6) {
3142 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
3143 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
3144 }
6f34be50 3145
45f9a39b
AD		 3146 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3147 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3148 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3149 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3150 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3151 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3152
f122c610
AD		 3153 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
3154 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
3155 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
3156 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
3157 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
3158 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
3159
bcc1c2a1
AD		 3160 return 0;
3161}
3162
cbdd4501 3163static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 3164{
3165 u32 tmp;
3166
6f34be50
AD		 3167 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3168 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3169 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3170 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3171 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3172 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3173 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3174 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 3175 if (rdev->num_crtc >= 4) {
3176 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3177 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3178 }
3179 if (rdev->num_crtc >= 6) {
3180 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3181 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3182 }
6f34be50 3183
f122c610
AD		 3184 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
3185 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
3186 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
3187 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
3188 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
3189 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
3190
6f34be50
AD		 3191 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
3192 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3193 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
3194 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 3195 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 3196 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 3197 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 3198 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 3199 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 3200 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 3201 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 3202 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3203
b7eff394
AD		 3204 if (rdev->num_crtc >= 4) {
3205 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
3206 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3207 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
3208 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3209 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3210 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3211 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3212 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3213 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3214 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3215 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3216 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3217 }
3218
3219 if (rdev->num_crtc >= 6) {
3220 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
3221 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3222 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
3223 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
3224 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3225 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3226 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3227 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3228 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3229 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3230 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3231 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3232 }
45f9a39b 3233
6f34be50 3234 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 3235 tmp = RREG32(DC_HPD1_INT_CONTROL);
3236 tmp |= DC_HPDx_INT_ACK;
3237 WREG32(DC_HPD1_INT_CONTROL, tmp);
3238 }
6f34be50 3239 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 3240 tmp = RREG32(DC_HPD2_INT_CONTROL);
3241 tmp |= DC_HPDx_INT_ACK;
3242 WREG32(DC_HPD2_INT_CONTROL, tmp);
3243 }
6f34be50 3244 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 3245 tmp = RREG32(DC_HPD3_INT_CONTROL);
3246 tmp |= DC_HPDx_INT_ACK;
3247 WREG32(DC_HPD3_INT_CONTROL, tmp);
3248 }
6f34be50 3249 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 3250 tmp = RREG32(DC_HPD4_INT_CONTROL);
3251 tmp |= DC_HPDx_INT_ACK;
3252 WREG32(DC_HPD4_INT_CONTROL, tmp);
3253 }
6f34be50 3254 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 3255 tmp = RREG32(DC_HPD5_INT_CONTROL);
3256 tmp |= DC_HPDx_INT_ACK;
3257 WREG32(DC_HPD5_INT_CONTROL, tmp);
3258 }
6f34be50 3259 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 3260 tmp = RREG32(DC_HPD5_INT_CONTROL);
3261 tmp |= DC_HPDx_INT_ACK;
3262 WREG32(DC_HPD6_INT_CONTROL, tmp);
3263 }
f122c610
AD		 3264 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3265 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
3266 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3267 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
3268 }
3269 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3270 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
3271 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3272 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
3273 }
3274 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3275 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
3276 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3277 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
3278 }
3279 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3280 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
3281 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3282 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
3283 }
3284 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3285 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
3286 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3287 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
3288 }
3289 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3290 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
3291 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3292 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
3293 }
45f9a39b
AD		 3294}
3295
1109ca09 3296static void evergreen_irq_disable(struct radeon_device *rdev)
45f9a39b 3297{
45f9a39b
AD		 3298 r600_disable_interrupts(rdev);
3299 /* Wait and acknowledge irq */
3300 mdelay(1);
6f34be50 3301 evergreen_irq_ack(rdev);
45f9a39b
AD		 3302 evergreen_disable_interrupt_state(rdev);
3303}
3304
755d819e 3305void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 3306{
3307 evergreen_irq_disable(rdev);
3308 r600_rlc_stop(rdev);
3309}
3310
cbdd4501 3311static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 3312{
3313 u32 wptr, tmp;
3314
724c80e1 3315 if (rdev->wb.enabled)
204ae24d 3316 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 3317 else
3318 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 3319
3320 if (wptr & RB_OVERFLOW) {
3321 /* When a ring buffer overflow happen start parsing interrupt
3322 * from the last not overwritten vector (wptr + 16). Hopefully
3323 * this should allow us to catchup.
3324 */
3325 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3326 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3327 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3328 tmp = RREG32(IH_RB_CNTL);
3329 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3330 WREG32(IH_RB_CNTL, tmp);
3331 }
3332 return (wptr & rdev->ih.ptr_mask);
3333}
3334
3335int evergreen_irq_process(struct radeon_device *rdev)
3336{
682f1a54
DA		 3337 u32 wptr;
3338 u32 rptr;
45f9a39b
AD		 3339 u32 src_id, src_data;
3340 u32 ring_index;
45f9a39b 3341 bool queue_hotplug = false;
f122c610 3342 bool queue_hdmi = false;
45f9a39b 3343
682f1a54 3344 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 3345 return IRQ_NONE;
3346
682f1a54 3347 wptr = evergreen_get_ih_wptr(rdev);
c20dc369
CK		 3348
3349restart_ih:
3350 /* is somebody else already processing irqs? */
3351 if (atomic_xchg(&rdev->ih.lock, 1))
3352 return IRQ_NONE;
3353
682f1a54
DA		 3354 rptr = rdev->ih.rptr;
3355 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 3356
964f6645
BH		 3357 /* Order reading of wptr vs. reading of IH ring data */
3358 rmb();
3359
45f9a39b 3360 /* display interrupts */
6f34be50 3361 evergreen_irq_ack(rdev);
45f9a39b 3362
45f9a39b
AD		 3363 while (rptr != wptr) {
3364 /* wptr/rptr are in bytes! */
3365 ring_index = rptr / 4;
0f234f5f
AD		 3366 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3367 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 3368
3369 switch (src_id) {
3370 case 1: /* D1 vblank/vline */
3371 switch (src_data) {
3372 case 0: /* D1 vblank */
6f34be50 3373 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 3374 if (rdev->irq.crtc_vblank_int[0]) {
3375 drm_handle_vblank(rdev->ddev, 0);
3376 rdev->pm.vblank_sync = true;
3377 wake_up(&rdev->irq.vblank_queue);
3378 }
736fc37f 3379 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 3380 radeon_crtc_handle_flip(rdev, 0);
6f34be50 3381 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 3382 DRM_DEBUG("IH: D1 vblank\n");
3383 }
3384 break;
3385 case 1: /* D1 vline */
6f34be50
AD		 3386 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3387 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 3388 DRM_DEBUG("IH: D1 vline\n");
3389 }
3390 break;
3391 default:
3392 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3393 break;
3394 }
3395 break;
3396 case 2: /* D2 vblank/vline */
3397 switch (src_data) {
3398 case 0: /* D2 vblank */
6f34be50 3399 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 3400 if (rdev->irq.crtc_vblank_int[1]) {
3401 drm_handle_vblank(rdev->ddev, 1);
3402 rdev->pm.vblank_sync = true;
3403 wake_up(&rdev->irq.vblank_queue);
3404 }
736fc37f 3405 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 3406 radeon_crtc_handle_flip(rdev, 1);
6f34be50 3407 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 3408 DRM_DEBUG("IH: D2 vblank\n");
3409 }
3410 break;
3411 case 1: /* D2 vline */
6f34be50
AD		 3412 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3413 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 3414 DRM_DEBUG("IH: D2 vline\n");
3415 }
3416 break;
3417 default:
3418 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3419 break;
3420 }
3421 break;
3422 case 3: /* D3 vblank/vline */
3423 switch (src_data) {
3424 case 0: /* D3 vblank */
6f34be50
AD		 3425 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3426 if (rdev->irq.crtc_vblank_int[2]) {
3427 drm_handle_vblank(rdev->ddev, 2);
3428 rdev->pm.vblank_sync = true;
3429 wake_up(&rdev->irq.vblank_queue);
3430 }
736fc37f 3431 if (atomic_read(&rdev->irq.pflip[2]))
6f34be50
AD		 3432 radeon_crtc_handle_flip(rdev, 2);
3433 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 3434 DRM_DEBUG("IH: D3 vblank\n");
3435 }
3436 break;
3437 case 1: /* D3 vline */
6f34be50
AD		 3438 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3439 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 3440 DRM_DEBUG("IH: D3 vline\n");
3441 }
3442 break;
3443 default:
3444 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3445 break;
3446 }
3447 break;
3448 case 4: /* D4 vblank/vline */
3449 switch (src_data) {
3450 case 0: /* D4 vblank */
6f34be50
AD		 3451 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3452 if (rdev->irq.crtc_vblank_int[3]) {
3453 drm_handle_vblank(rdev->ddev, 3);
3454 rdev->pm.vblank_sync = true;
3455 wake_up(&rdev->irq.vblank_queue);
3456 }
736fc37f 3457 if (atomic_read(&rdev->irq.pflip[3]))
6f34be50
AD		 3458 radeon_crtc_handle_flip(rdev, 3);
3459 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 3460 DRM_DEBUG("IH: D4 vblank\n");
3461 }
3462 break;
3463 case 1: /* D4 vline */
6f34be50
AD		 3464 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3465 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 3466 DRM_DEBUG("IH: D4 vline\n");
3467 }
3468 break;
3469 default:
3470 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3471 break;
3472 }
3473 break;
3474 case 5: /* D5 vblank/vline */
3475 switch (src_data) {
3476 case 0: /* D5 vblank */
6f34be50
AD		 3477 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3478 if (rdev->irq.crtc_vblank_int[4]) {
3479 drm_handle_vblank(rdev->ddev, 4);
3480 rdev->pm.vblank_sync = true;
3481 wake_up(&rdev->irq.vblank_queue);
3482 }
736fc37f 3483 if (atomic_read(&rdev->irq.pflip[4]))
6f34be50
AD		 3484 radeon_crtc_handle_flip(rdev, 4);
3485 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 3486 DRM_DEBUG("IH: D5 vblank\n");
3487 }
3488 break;
3489 case 1: /* D5 vline */
6f34be50
AD		 3490 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3491 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 3492 DRM_DEBUG("IH: D5 vline\n");
3493 }
3494 break;
3495 default:
3496 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3497 break;
3498 }
3499 break;
3500 case 6: /* D6 vblank/vline */
3501 switch (src_data) {
3502 case 0: /* D6 vblank */
6f34be50
AD		 3503 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3504 if (rdev->irq.crtc_vblank_int[5]) {
3505 drm_handle_vblank(rdev->ddev, 5);
3506 rdev->pm.vblank_sync = true;
3507 wake_up(&rdev->irq.vblank_queue);
3508 }
736fc37f 3509 if (atomic_read(&rdev->irq.pflip[5]))
6f34be50
AD		 3510 radeon_crtc_handle_flip(rdev, 5);
3511 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 3512 DRM_DEBUG("IH: D6 vblank\n");
3513 }
3514 break;
3515 case 1: /* D6 vline */
6f34be50
AD		 3516 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3517 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 3518 DRM_DEBUG("IH: D6 vline\n");
3519 }
3520 break;
3521 default:
3522 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3523 break;
3524 }
3525 break;
3526 case 42: /* HPD hotplug */
3527 switch (src_data) {
3528 case 0:
6f34be50
AD		 3529 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3530 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 3531 queue_hotplug = true;
3532 DRM_DEBUG("IH: HPD1\n");
3533 }
3534 break;
3535 case 1:
6f34be50
AD		 3536 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3537 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 3538 queue_hotplug = true;
3539 DRM_DEBUG("IH: HPD2\n");
3540 }
3541 break;
3542 case 2:
6f34be50
AD		 3543 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3544 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 3545 queue_hotplug = true;
3546 DRM_DEBUG("IH: HPD3\n");
3547 }
3548 break;
3549 case 3:
6f34be50
AD		 3550 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3551 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 3552 queue_hotplug = true;
3553 DRM_DEBUG("IH: HPD4\n");
3554 }
3555 break;
3556 case 4:
6f34be50
AD		 3557 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3558 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 3559 queue_hotplug = true;
3560 DRM_DEBUG("IH: HPD5\n");
3561 }
3562 break;
3563 case 5:
6f34be50
AD		 3564 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3565 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 3566 queue_hotplug = true;
3567 DRM_DEBUG("IH: HPD6\n");
3568 }
3569 break;
3570 default:
3571 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3572 break;
3573 }
3574 break;
f122c610
AD		 3575 case 44: /* hdmi */
3576 switch (src_data) {
3577 case 0:
3578 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3579 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3580 queue_hdmi = true;
3581 DRM_DEBUG("IH: HDMI0\n");
3582 }
3583 break;
3584 case 1:
3585 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3586 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3587 queue_hdmi = true;
3588 DRM_DEBUG("IH: HDMI1\n");
3589 }
3590 break;
3591 case 2:
3592 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3593 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3594 queue_hdmi = true;
3595 DRM_DEBUG("IH: HDMI2\n");
3596 }
3597 break;
3598 case 3:
3599 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3600 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3601 queue_hdmi = true;
3602 DRM_DEBUG("IH: HDMI3\n");
3603 }
3604 break;
3605 case 4:
3606 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3607 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3608 queue_hdmi = true;
3609 DRM_DEBUG("IH: HDMI4\n");
3610 }
3611 break;
3612 case 5:
3613 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3614 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3615 queue_hdmi = true;
3616 DRM_DEBUG("IH: HDMI5\n");
3617 }
3618 break;
3619 default:
3620 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3621 break;
3622 }
f2ba57b5
CK		 3623 case 124: /* UVD */
3624 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
3625 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
f122c610 3626 break;
ae133a11
CK		 3627 case 146:
3628 case 147:
3629 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3630 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
3631 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3632 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3633 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3634 /* reset addr and status */
3635 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3636 break;
45f9a39b
AD		 3637 case 176: /* CP_INT in ring buffer */
3638 case 177: /* CP_INT in IB1 */
3639 case 178: /* CP_INT in IB2 */
3640 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3641 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 3642 break;
3643 case 181: /* CP EOP event */
3644 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 3645 if (rdev->family >= CHIP_CAYMAN) {
3646 switch (src_data) {
3647 case 0:
3648 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3649 break;
3650 case 1:
3651 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3652 break;
3653 case 2:
3654 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3655 break;
3656 }
3657 } else
3658 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 3659 break;
233d1ad5
AD		 3660 case 224: /* DMA trap event */
3661 DRM_DEBUG("IH: DMA trap\n");
3662 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3663 break;
2031f77c 3664 case 233: /* GUI IDLE */
303c805c 3665 DRM_DEBUG("IH: GUI idle\n");
2031f77c 3666 break;
f60cbd11
AD		 3667 case 244: /* DMA trap event */
3668 if (rdev->family >= CHIP_CAYMAN) {
3669 DRM_DEBUG("IH: DMA1 trap\n");
3670 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
3671 }
3672 break;
45f9a39b
AD		 3673 default:
3674 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3675 break;
3676 }
3677
3678 /* wptr/rptr are in bytes! */
3679 rptr += 16;
3680 rptr &= rdev->ih.ptr_mask;
3681 }
45f9a39b 3682 if (queue_hotplug)
32c87fca 3683 schedule_work(&rdev->hotplug_work);
f122c610
AD		 3684 if (queue_hdmi)
3685 schedule_work(&rdev->audio_work);
45f9a39b
AD		 3686 rdev->ih.rptr = rptr;
3687 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 3688 atomic_set(&rdev->ih.lock, 0);
3689
3690 /* make sure wptr hasn't changed while processing */
3691 wptr = evergreen_get_ih_wptr(rdev);
3692 if (wptr != rptr)
3693 goto restart_ih;
3694
45f9a39b
AD		 3695 return IRQ_HANDLED;
3696}
3697
233d1ad5
AD		 3698/**
3699 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
3700 *
3701 * @rdev: radeon_device pointer
3702 * @fence: radeon fence object
3703 *
3704 * Add a DMA fence packet to the ring to write
3705 * the fence seq number and DMA trap packet to generate
3706 * an interrupt if needed (evergreen-SI).
3707 */
3708void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
3709 struct radeon_fence *fence)
3710{
3711 struct radeon_ring *ring = &rdev->ring[fence->ring];
3712 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3713 /* write the fence */
0fcb6155 3714 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
233d1ad5
AD		 3715 radeon_ring_write(ring, addr & 0xfffffffc);
3716 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3717 radeon_ring_write(ring, fence->seq);
3718 /* generate an interrupt */
0fcb6155 3719 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
233d1ad5 3720 /* flush HDP */
0fcb6155 3721 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
4b681c28 3722 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
233d1ad5
AD		 3723 radeon_ring_write(ring, 1);
3724}
3725
3726/**
3727 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
3728 *
3729 * @rdev: radeon_device pointer
3730 * @ib: IB object to schedule
3731 *
3732 * Schedule an IB in the DMA ring (evergreen).
3733 */
3734void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3735 struct radeon_ib *ib)
3736{
3737 struct radeon_ring *ring = &rdev->ring[ib->ring];
3738
3739 if (rdev->wb.enabled) {
3740 u32 next_rptr = ring->wptr + 4;
3741 while ((next_rptr & 7) != 5)
3742 next_rptr++;
3743 next_rptr += 3;
0fcb6155 3744 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
233d1ad5
AD		 3745 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3746 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3747 radeon_ring_write(ring, next_rptr);
3748 }
3749
3750 /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3751 * Pad as necessary with NOPs.
3752 */
3753 while ((ring->wptr & 7) != 5)
0fcb6155
JG		 3754 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3755 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
233d1ad5
AD		 3756 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3757 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3758
3759}
3760
3761/**
3762 * evergreen_copy_dma - copy pages using the DMA engine
3763 *
3764 * @rdev: radeon_device pointer
3765 * @src_offset: src GPU address
3766 * @dst_offset: dst GPU address
3767 * @num_gpu_pages: number of GPU pages to xfer
3768 * @fence: radeon fence object
3769 *
3770 * Copy GPU paging using the DMA engine (evergreen-cayman).
3771 * Used by the radeon ttm implementation to move pages if
3772 * registered as the asic copy callback.
3773 */
3774int evergreen_copy_dma(struct radeon_device *rdev,
3775 uint64_t src_offset, uint64_t dst_offset,
3776 unsigned num_gpu_pages,
3777 struct radeon_fence **fence)
3778{
3779 struct radeon_semaphore *sem = NULL;
3780 int ring_index = rdev->asic->copy.dma_ring_index;
3781 struct radeon_ring *ring = &rdev->ring[ring_index];
3782 u32 size_in_dw, cur_size_in_dw;
3783 int i, num_loops;
3784 int r = 0;
3785
3786 r = radeon_semaphore_create(rdev, &sem);
3787 if (r) {
3788 DRM_ERROR("radeon: moving bo (%d).\n", r);
3789 return r;
3790 }
3791
3792 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3793 num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
3794 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
3795 if (r) {
3796 DRM_ERROR("radeon: moving bo (%d).\n", r);
3797 radeon_semaphore_free(rdev, &sem, NULL);
3798 return r;
3799 }
3800
3801 if (radeon_fence_need_sync(*fence, ring->idx)) {
3802 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3803 ring->idx);
3804 radeon_fence_note_sync(*fence, ring->idx);
3805 } else {
3806 radeon_semaphore_free(rdev, &sem, NULL);
3807 }
3808
3809 for (i = 0; i < num_loops; i++) {
3810 cur_size_in_dw = size_in_dw;
3811 if (cur_size_in_dw > 0xFFFFF)
3812 cur_size_in_dw = 0xFFFFF;
3813 size_in_dw -= cur_size_in_dw;
0fcb6155 3814 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
233d1ad5
AD		 3815 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3816 radeon_ring_write(ring, src_offset & 0xfffffffc);
3817 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3818 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3819 src_offset += cur_size_in_dw * 4;
3820 dst_offset += cur_size_in_dw * 4;
3821 }
3822
3823 r = radeon_fence_emit(rdev, fence, ring->idx);
3824 if (r) {
3825 radeon_ring_unlock_undo(rdev, ring);
3826 return r;
3827 }
3828
3829 radeon_ring_unlock_commit(rdev, ring);
3830 radeon_semaphore_free(rdev, &sem, *fence);
3831
3832 return r;
3833}
3834
bcc1c2a1
AD		 3835static int evergreen_startup(struct radeon_device *rdev)
3836{
f2ba57b5 3837 struct radeon_ring *ring;
bcc1c2a1
AD		 3838 int r;
3839
9e46a48d 3840 /* enable pcie gen2 link */
cd54033a 3841 evergreen_pcie_gen2_enable(rdev);
9e46a48d 3842
0af62b01
AD		 3843 if (ASIC_IS_DCE5(rdev)) {
3844 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3845 r = ni_init_microcode(rdev);
3846 if (r) {
3847 DRM_ERROR("Failed to load firmware!\n");
3848 return r;
3849 }
3850 }
755d819e 3851 r = ni_mc_load_microcode(rdev);
bcc1c2a1 3852 if (r) {
0af62b01 3853 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 3854 return r;
3855 }
0af62b01
AD		 3856 } else {
3857 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3858 r = r600_init_microcode(rdev);
3859 if (r) {
3860 DRM_ERROR("Failed to load firmware!\n");
3861 return r;
3862 }
3863 }
bcc1c2a1 3864 }
fe251e2f 3865
16cdf04d
AD		 3866 r = r600_vram_scratch_init(rdev);
3867 if (r)
3868 return r;
3869
bcc1c2a1 3870 evergreen_mc_program(rdev);
bcc1c2a1 3871 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 3872 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 3873 } else {
3874 r = evergreen_pcie_gart_enable(rdev);
3875 if (r)
3876 return r;
3877 }
bcc1c2a1 3878 evergreen_gpu_init(rdev);
bcc1c2a1 3879
d7ccd8fc 3880 r = evergreen_blit_init(rdev);
bcc1c2a1 3881 if (r) {
fb3d9e97 3882 r600_blit_fini(rdev);
27cd7769 3883 rdev->asic->copy.copy = NULL;
d7ccd8fc 3884 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 3885 }
3886
724c80e1
AD		 3887 /* allocate wb buffer */
3888 r = radeon_wb_init(rdev);
3889 if (r)
3890 return r;
3891
30eb77f4
JG		 3892 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3893 if (r) {
3894 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3895 return r;
3896 }
3897
233d1ad5
AD		 3898 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3899 if (r) {
3900 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3901 return r;
3902 }
3903
f2ba57b5
CK		 3904 r = rv770_uvd_resume(rdev);
3905 if (!r) {
3906 r = radeon_fence_driver_start_ring(rdev,
3907 R600_RING_TYPE_UVD_INDEX);
3908 if (r)
3909 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
3910 }
3911
3912 if (r)
3913 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
3914
bcc1c2a1
AD		 3915 /* Enable IRQ */
3916 r = r600_irq_init(rdev);
3917 if (r) {
3918 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3919 radeon_irq_kms_fini(rdev);
3920 return r;
3921 }
45f9a39b 3922 evergreen_irq_set(rdev);
bcc1c2a1 3923
f2ba57b5 3924 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
e32eb50d 3925 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 3926 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3927 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 3928 if (r)
3929 return r;
233d1ad5
AD		 3930
3931 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3932 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3933 DMA_RB_RPTR, DMA_RB_WPTR,
0fcb6155 3934 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
233d1ad5
AD		 3935 if (r)
3936 return r;
3937
bcc1c2a1
AD		 3938 r = evergreen_cp_load_microcode(rdev);
3939 if (r)
3940 return r;
fe251e2f 3941 r = evergreen_cp_resume(rdev);
233d1ad5
AD		 3942 if (r)
3943 return r;
3944 r = r600_dma_resume(rdev);
bcc1c2a1
AD		 3945 if (r)
3946 return r;
fe251e2f 3947
f2ba57b5
CK		 3948 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
3949 if (ring->ring_size) {
3950 r = radeon_ring_init(rdev, ring, ring->ring_size,
3951 R600_WB_UVD_RPTR_OFFSET,
3952 UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
3953 0, 0xfffff, RADEON_CP_PACKET2);
3954 if (!r)
3955 r = r600_uvd_init(rdev);
3956
3957 if (r)
3958 DRM_ERROR("radeon: error initializing UVD (%d).\n", r);
3959 }
3960
2898c348
CK		 3961 r = radeon_ib_pool_init(rdev);
3962 if (r) {
3963 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3964 return r;
2898c348 3965 }
b15ba512 3966
69d2ae57
RM		 3967 r = r600_audio_init(rdev);
3968 if (r) {
3969 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 3970 return r;
3971 }
3972
bcc1c2a1
AD		 3973 return 0;
3974}
3975
3976int evergreen_resume(struct radeon_device *rdev)
3977{
3978 int r;
3979
86f5c9ed
AD		 3980 /* reset the asic, the gfx blocks are often in a bad state
3981 * after the driver is unloaded or after a resume
3982 */
3983 if (radeon_asic_reset(rdev))
3984 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 3985 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3986 * posting will perform necessary task to bring back GPU into good
3987 * shape.
3988 */
3989 /* post card */
3990 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 3991
b15ba512 3992 rdev->accel_working = true;
bcc1c2a1
AD		 3993 r = evergreen_startup(rdev);
3994 if (r) {
755d819e 3995 DRM_ERROR("evergreen startup failed on resume\n");
6b7746e8 3996 rdev->accel_working = false;
bcc1c2a1
AD		 3997 return r;
3998 }
fe251e2f 3999
bcc1c2a1
AD		 4000 return r;
4001
4002}
4003
4004int evergreen_suspend(struct radeon_device *rdev)
4005{
69d2ae57 4006 r600_audio_fini(rdev);
f2ba57b5 4007 radeon_uvd_suspend(rdev);
bcc1c2a1 4008 r700_cp_stop(rdev);
233d1ad5 4009 r600_dma_stop(rdev);
f2ba57b5 4010 r600_uvd_rbc_stop(rdev);
45f9a39b 4011 evergreen_irq_suspend(rdev);
724c80e1 4012 radeon_wb_disable(rdev);
bcc1c2a1 4013 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 4014
4015 return 0;
4016}
4017
bcc1c2a1
AD		 4018/* Plan is to move initialization in that function and use
4019 * helper function so that radeon_device_init pretty much
4020 * do nothing more than calling asic specific function. This
4021 * should also allow to remove a bunch of callback function
4022 * like vram_info.
4023 */
4024int evergreen_init(struct radeon_device *rdev)
4025{
4026 int r;
4027
bcc1c2a1
AD		 4028 /* Read BIOS */
4029 if (!radeon_get_bios(rdev)) {
4030 if (ASIC_IS_AVIVO(rdev))
4031 return -EINVAL;
4032 }
4033 /* Must be an ATOMBIOS */
4034 if (!rdev->is_atom_bios) {
755d819e 4035 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 4036 return -EINVAL;
4037 }
4038 r = radeon_atombios_init(rdev);
4039 if (r)
4040 return r;
86f5c9ed
AD		 4041 /* reset the asic, the gfx blocks are often in a bad state
4042 * after the driver is unloaded or after a resume
4043 */
4044 if (radeon_asic_reset(rdev))
4045 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 4046 /* Post card if necessary */
fd909c37 4047 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 4048 if (!rdev->bios) {
4049 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
4050 return -EINVAL;
4051 }
4052 DRM_INFO("GPU not posted. posting now...\n");
4053 atom_asic_init(rdev->mode_info.atom_context);
4054 }
4055 /* Initialize scratch registers */
4056 r600_scratch_init(rdev);
4057 /* Initialize surface registers */
4058 radeon_surface_init(rdev);
4059 /* Initialize clocks */
4060 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 4061 /* Fence driver */
4062 r = radeon_fence_driver_init(rdev);
4063 if (r)
4064 return r;
d594e46a
JG		 4065 /* initialize AGP */
4066 if (rdev->flags & RADEON_IS_AGP) {
4067 r = radeon_agp_init(rdev);
4068 if (r)
4069 radeon_agp_disable(rdev);
4070 }
4071 /* initialize memory controller */
bcc1c2a1
AD		 4072 r = evergreen_mc_init(rdev);
4073 if (r)
4074 return r;
4075 /* Memory manager */
4076 r = radeon_bo_init(rdev);
4077 if (r)
4078 return r;
45f9a39b 4079
bcc1c2a1
AD		 4080 r = radeon_irq_kms_init(rdev);
4081 if (r)
4082 return r;
4083
e32eb50d
CK		 4084 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
4085 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1 4086
233d1ad5
AD		 4087 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
4088 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
4089
f2ba57b5
CK		 4090 r = radeon_uvd_init(rdev);
4091 if (!r) {
4092 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
4093 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
4094 4096);
4095 }
4096
bcc1c2a1
AD		 4097 rdev->ih.ring_obj = NULL;
4098 r600_ih_ring_init(rdev, 64 * 1024);
4099
4100 r = r600_pcie_gart_init(rdev);
4101 if (r)
4102 return r;
0fcdb61e 4103
148a03bc 4104 rdev->accel_working = true;
bcc1c2a1
AD		 4105 r = evergreen_startup(rdev);
4106 if (r) {
fe251e2f
AD		 4107 dev_err(rdev->dev, "disabling GPU acceleration\n");
4108 r700_cp_fini(rdev);
233d1ad5 4109 r600_dma_fini(rdev);
fe251e2f 4110 r600_irq_fini(rdev);
724c80e1 4111 radeon_wb_fini(rdev);
2898c348 4112 radeon_ib_pool_fini(rdev);
fe251e2f 4113 radeon_irq_kms_fini(rdev);
0fcdb61e 4114 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 4115 rdev->accel_working = false;
4116 }
77e00f2e
AD		 4117
4118 /* Don't start up if the MC ucode is missing on BTC parts.
4119 * The default clocks and voltages before the MC ucode
4120 * is loaded are not suffient for advanced operations.
4121 */
4122 if (ASIC_IS_DCE5(rdev)) {
4123 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
4124 DRM_ERROR("radeon: MC ucode required for NI+.\n");
4125 return -EINVAL;
4126 }
4127 }
4128
bcc1c2a1
AD		 4129 return 0;
4130}
4131
4132void evergreen_fini(struct radeon_device *rdev)
4133{
69d2ae57 4134 r600_audio_fini(rdev);
fb3d9e97 4135 r600_blit_fini(rdev);
45f9a39b 4136 r700_cp_fini(rdev);
233d1ad5 4137 r600_dma_fini(rdev);
bcc1c2a1 4138 r600_irq_fini(rdev);
724c80e1 4139 radeon_wb_fini(rdev);
2898c348 4140 radeon_ib_pool_fini(rdev);
bcc1c2a1 4141 radeon_irq_kms_fini(rdev);
bcc1c2a1 4142 evergreen_pcie_gart_fini(rdev);
f2ba57b5 4143 radeon_uvd_fini(rdev);
16cdf04d 4144 r600_vram_scratch_fini(rdev);
bcc1c2a1
AD		 4145 radeon_gem_fini(rdev);
4146 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 4147 radeon_agp_fini(rdev);
4148 radeon_bo_fini(rdev);
4149 radeon_atombios_fini(rdev);
4150 kfree(rdev->bios);
4151 rdev->bios = NULL;
bcc1c2a1 4152}
9e46a48d 4153
b07759bf 4154void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d 4155{
197bbb3d
DA		 4156 u32 link_width_cntl, speed_cntl, mask;
4157 int ret;
9e46a48d 4158
d42dd579
AD		 4159 if (radeon_pcie_gen2 == 0)
4160 return;
4161
9e46a48d
AD		 4162 if (rdev->flags & RADEON_IS_IGP)
4163 return;
4164
4165 if (!(rdev->flags & RADEON_IS_PCIE))
4166 return;
4167
4168 /* x2 cards have a special sequence */
4169 if (ASIC_IS_X2(rdev))
4170 return;
4171
197bbb3d
DA		 4172 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4173 if (ret != 0)
4174 return;
4175
4176 if (!(mask & DRM_PCIE_SPEED_50))
4177 return;
4178
492d2b61 4179 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3691feea
AD		 4180 if (speed_cntl & LC_CURRENT_DATA_RATE) {
4181 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4182 return;
4183 }
4184
197bbb3d
DA		 4185 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4186
9e46a48d
AD		 4187 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
4188 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4189
492d2b61 4190 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d 4191 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61 4192 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d 4193
492d2b61 4194 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4195 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
492d2b61 4196 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d 4197
492d2b61 4198 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4199 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
492d2b61 4200 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d 4201
492d2b61 4202 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4203 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
492d2b61 4204 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d 4205
492d2b61 4206 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9e46a48d 4207 speed_cntl |= LC_GEN2_EN_STRAP;
492d2b61 4208 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9e46a48d
AD		 4209
4210 } else {
492d2b61 4211 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9e46a48d
AD		 4212 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4213 if (1)
4214 link_width_cntl |= LC_UPCONFIGURE_DIS;
4215 else
4216 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
492d2b61 4217 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
9e46a48d
AD		 4218 }
4219}
Linux kernel - Deliverables
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