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drm/radeon/kms: add llano pci ids
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
9e46a48d 42static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
bcc1c2a1 43
6f34be50
AD		 44void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
45{
6f34be50
AD		 46 /* enable the pflip int */
47 radeon_irq_kms_pflip_irq_get(rdev, crtc);
48}
49
50void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
51{
52 /* disable the pflip int */
53 radeon_irq_kms_pflip_irq_put(rdev, crtc);
54}
55
56u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
57{
58 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
59 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
60
61 /* Lock the graphics update lock */
62 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
63 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
64
65 /* update the scanout addresses */
66 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
67 upper_32_bits(crtc_base));
68 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
69 (u32)crtc_base);
70
71 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
72 upper_32_bits(crtc_base));
73 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
74 (u32)crtc_base);
75
76 /* Wait for update_pending to go high. */
77 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
79
80 /* Unlock the lock, so double-buffering can take place inside vblank */
81 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
82 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
83
84 /* Return current update_pending status: */
85 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
86}
87
21a8122a 88/* get temperature in millidegrees */
20d391d7 89int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 90{
67b3f823
AD		 91 u32 temp, toffset, actual_temp = 0;
92
93 if (rdev->family == CHIP_JUNIPER) {
94 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
95 TOFFSET_SHIFT;
96 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
97 TS0_ADC_DOUT_SHIFT;
98
99 if (toffset & 0x100)
100 actual_temp = temp / 2 - (0x200 - toffset);
101 else
102 actual_temp = temp / 2 + toffset;
103
104 actual_temp = actual_temp * 1000;
105
106 } else {
107 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
108 ASIC_T_SHIFT;
109
110 if (temp & 0x400)
111 actual_temp = -256;
112 else if (temp & 0x200)
113 actual_temp = 255;
114 else if (temp & 0x100) {
115 actual_temp = temp & 0x1ff;
116 actual_temp |= ~0x1ff;
117 } else
118 actual_temp = temp & 0xff;
119
120 actual_temp = (actual_temp * 1000) / 2;
121 }
122
123 return actual_temp;
21a8122a
AD		 124}
125
20d391d7 126int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 127{
128 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 129 int actual_temp = temp - 49;
e33df25f
AD		 130
131 return actual_temp * 1000;
132}
133
49e02b73
AD		 134void evergreen_pm_misc(struct radeon_device *rdev)
135{
a081a9d6
RM		 136 int req_ps_idx = rdev->pm.requested_power_state_index;
137 int req_cm_idx = rdev->pm.requested_clock_mode_index;
138 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
139 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 140
2feea49a
AD		 141 if (voltage->type == VOLTAGE_SW) {
142 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 143 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 144 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 145 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
146 }
147 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
148 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
149 rdev->pm.current_vddci = voltage->vddci;
150 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 151 }
152 }
49e02b73
AD		 153}
154
155void evergreen_pm_prepare(struct radeon_device *rdev)
156{
157 struct drm_device *ddev = rdev->ddev;
158 struct drm_crtc *crtc;
159 struct radeon_crtc *radeon_crtc;
160 u32 tmp;
161
162 /* disable any active CRTCs */
163 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
164 radeon_crtc = to_radeon_crtc(crtc);
165 if (radeon_crtc->enabled) {
166 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
167 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
168 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
169 }
170 }
171}
172
173void evergreen_pm_finish(struct radeon_device *rdev)
174{
175 struct drm_device *ddev = rdev->ddev;
176 struct drm_crtc *crtc;
177 struct radeon_crtc *radeon_crtc;
178 u32 tmp;
179
180 /* enable any active CRTCs */
181 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
182 radeon_crtc = to_radeon_crtc(crtc);
183 if (radeon_crtc->enabled) {
184 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
185 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
186 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
187 }
188 }
189}
190
bcc1c2a1
AD		 191bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
192{
193 bool connected = false;
0ca2ab52
AD		 194
195 switch (hpd) {
196 case RADEON_HPD_1:
197 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
198 connected = true;
199 break;
200 case RADEON_HPD_2:
201 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
202 connected = true;
203 break;
204 case RADEON_HPD_3:
205 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
206 connected = true;
207 break;
208 case RADEON_HPD_4:
209 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
210 connected = true;
211 break;
212 case RADEON_HPD_5:
213 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
214 connected = true;
215 break;
216 case RADEON_HPD_6:
217 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
218 connected = true;
219 break;
220 default:
221 break;
222 }
223
bcc1c2a1
AD		 224 return connected;
225}
226
227void evergreen_hpd_set_polarity(struct radeon_device *rdev,
228 enum radeon_hpd_id hpd)
229{
0ca2ab52
AD		 230 u32 tmp;
231 bool connected = evergreen_hpd_sense(rdev, hpd);
232
233 switch (hpd) {
234 case RADEON_HPD_1:
235 tmp = RREG32(DC_HPD1_INT_CONTROL);
236 if (connected)
237 tmp &= ~DC_HPDx_INT_POLARITY;
238 else
239 tmp |= DC_HPDx_INT_POLARITY;
240 WREG32(DC_HPD1_INT_CONTROL, tmp);
241 break;
242 case RADEON_HPD_2:
243 tmp = RREG32(DC_HPD2_INT_CONTROL);
244 if (connected)
245 tmp &= ~DC_HPDx_INT_POLARITY;
246 else
247 tmp |= DC_HPDx_INT_POLARITY;
248 WREG32(DC_HPD2_INT_CONTROL, tmp);
249 break;
250 case RADEON_HPD_3:
251 tmp = RREG32(DC_HPD3_INT_CONTROL);
252 if (connected)
253 tmp &= ~DC_HPDx_INT_POLARITY;
254 else
255 tmp |= DC_HPDx_INT_POLARITY;
256 WREG32(DC_HPD3_INT_CONTROL, tmp);
257 break;
258 case RADEON_HPD_4:
259 tmp = RREG32(DC_HPD4_INT_CONTROL);
260 if (connected)
261 tmp &= ~DC_HPDx_INT_POLARITY;
262 else
263 tmp |= DC_HPDx_INT_POLARITY;
264 WREG32(DC_HPD4_INT_CONTROL, tmp);
265 break;
266 case RADEON_HPD_5:
267 tmp = RREG32(DC_HPD5_INT_CONTROL);
268 if (connected)
269 tmp &= ~DC_HPDx_INT_POLARITY;
270 else
271 tmp |= DC_HPDx_INT_POLARITY;
272 WREG32(DC_HPD5_INT_CONTROL, tmp);
273 break;
274 case RADEON_HPD_6:
275 tmp = RREG32(DC_HPD6_INT_CONTROL);
276 if (connected)
277 tmp &= ~DC_HPDx_INT_POLARITY;
278 else
279 tmp |= DC_HPDx_INT_POLARITY;
280 WREG32(DC_HPD6_INT_CONTROL, tmp);
281 break;
282 default:
283 break;
284 }
bcc1c2a1
AD		 285}
286
287void evergreen_hpd_init(struct radeon_device *rdev)
288{
0ca2ab52
AD		 289 struct drm_device *dev = rdev->ddev;
290 struct drm_connector *connector;
291 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
292 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 293
0ca2ab52
AD		 294 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
295 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
296 switch (radeon_connector->hpd.hpd) {
297 case RADEON_HPD_1:
298 WREG32(DC_HPD1_CONTROL, tmp);
299 rdev->irq.hpd[0] = true;
300 break;
301 case RADEON_HPD_2:
302 WREG32(DC_HPD2_CONTROL, tmp);
303 rdev->irq.hpd[1] = true;
304 break;
305 case RADEON_HPD_3:
306 WREG32(DC_HPD3_CONTROL, tmp);
307 rdev->irq.hpd[2] = true;
308 break;
309 case RADEON_HPD_4:
310 WREG32(DC_HPD4_CONTROL, tmp);
311 rdev->irq.hpd[3] = true;
312 break;
313 case RADEON_HPD_5:
314 WREG32(DC_HPD5_CONTROL, tmp);
315 rdev->irq.hpd[4] = true;
316 break;
317 case RADEON_HPD_6:
318 WREG32(DC_HPD6_CONTROL, tmp);
319 rdev->irq.hpd[5] = true;
320 break;
321 default:
322 break;
323 }
324 }
325 if (rdev->irq.installed)
326 evergreen_irq_set(rdev);
bcc1c2a1
AD		 327}
328
0ca2ab52 329void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 330{
0ca2ab52
AD		 331 struct drm_device *dev = rdev->ddev;
332 struct drm_connector *connector;
333
334 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
335 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
336 switch (radeon_connector->hpd.hpd) {
337 case RADEON_HPD_1:
338 WREG32(DC_HPD1_CONTROL, 0);
339 rdev->irq.hpd[0] = false;
340 break;
341 case RADEON_HPD_2:
342 WREG32(DC_HPD2_CONTROL, 0);
343 rdev->irq.hpd[1] = false;
344 break;
345 case RADEON_HPD_3:
346 WREG32(DC_HPD3_CONTROL, 0);
347 rdev->irq.hpd[2] = false;
348 break;
349 case RADEON_HPD_4:
350 WREG32(DC_HPD4_CONTROL, 0);
351 rdev->irq.hpd[3] = false;
352 break;
353 case RADEON_HPD_5:
354 WREG32(DC_HPD5_CONTROL, 0);
355 rdev->irq.hpd[4] = false;
356 break;
357 case RADEON_HPD_6:
358 WREG32(DC_HPD6_CONTROL, 0);
359 rdev->irq.hpd[5] = false;
360 break;
361 default:
362 break;
363 }
364 }
bcc1c2a1
AD		 365}
366
f9d9c362
AD		 367/* watermark setup */
368
369static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
370 struct radeon_crtc *radeon_crtc,
371 struct drm_display_mode *mode,
372 struct drm_display_mode *other_mode)
373{
12dfc843 374 u32 tmp;
f9d9c362
AD		 375 /*
376 * Line Buffer Setup
377 * There are 3 line buffers, each one shared by 2 display controllers.
378 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
379 * the display controllers. The paritioning is done via one of four
380 * preset allocations specified in bits 2:0:
381 * first display controller
382 * 0 - first half of lb (3840 * 2)
383 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 384 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 385 * 3 - first 1/4 of lb (1920 * 2)
386 * second display controller
387 * 4 - second half of lb (3840 * 2)
388 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 389 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 390 * 7 - last 1/4 of lb (1920 * 2)
391 */
12dfc843
AD		 392 /* this can get tricky if we have two large displays on a paired group
393 * of crtcs. Ideally for multiple large displays we'd assign them to
394 * non-linked crtcs for maximum line buffer allocation.
395 */
396 if (radeon_crtc->base.enabled && mode) {
397 if (other_mode)
f9d9c362 398 tmp = 0; /* 1/2 */
12dfc843
AD		 399 else
400 tmp = 2; /* whole */
401 } else
402 tmp = 0;
f9d9c362
AD		 403
404 /* second controller of the pair uses second half of the lb */
405 if (radeon_crtc->crtc_id % 2)
406 tmp += 4;
407 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
408
12dfc843
AD		 409 if (radeon_crtc->base.enabled && mode) {
410 switch (tmp) {
411 case 0:
412 case 4:
413 default:
414 if (ASIC_IS_DCE5(rdev))
415 return 4096 * 2;
416 else
417 return 3840 * 2;
418 case 1:
419 case 5:
420 if (ASIC_IS_DCE5(rdev))
421 return 6144 * 2;
422 else
423 return 5760 * 2;
424 case 2:
425 case 6:
426 if (ASIC_IS_DCE5(rdev))
427 return 8192 * 2;
428 else
429 return 7680 * 2;
430 case 3:
431 case 7:
432 if (ASIC_IS_DCE5(rdev))
433 return 2048 * 2;
434 else
435 return 1920 * 2;
436 }
f9d9c362 437 }
12dfc843
AD		 438
439 /* controller not enabled, so no lb used */
440 return 0;
f9d9c362
AD		 441}
442
443static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
444{
445 u32 tmp = RREG32(MC_SHARED_CHMAP);
446
447 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
448 case 0:
449 default:
450 return 1;
451 case 1:
452 return 2;
453 case 2:
454 return 4;
455 case 3:
456 return 8;
457 }
458}
459
460struct evergreen_wm_params {
461 u32 dram_channels; /* number of dram channels */
462 u32 yclk; /* bandwidth per dram data pin in kHz */
463 u32 sclk; /* engine clock in kHz */
464 u32 disp_clk; /* display clock in kHz */
465 u32 src_width; /* viewport width */
466 u32 active_time; /* active display time in ns */
467 u32 blank_time; /* blank time in ns */
468 bool interlaced; /* mode is interlaced */
469 fixed20_12 vsc; /* vertical scale ratio */
470 u32 num_heads; /* number of active crtcs */
471 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
472 u32 lb_size; /* line buffer allocated to pipe */
473 u32 vtaps; /* vertical scaler taps */
474};
475
476static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
477{
478 /* Calculate DRAM Bandwidth and the part allocated to display. */
479 fixed20_12 dram_efficiency; /* 0.7 */
480 fixed20_12 yclk, dram_channels, bandwidth;
481 fixed20_12 a;
482
483 a.full = dfixed_const(1000);
484 yclk.full = dfixed_const(wm->yclk);
485 yclk.full = dfixed_div(yclk, a);
486 dram_channels.full = dfixed_const(wm->dram_channels * 4);
487 a.full = dfixed_const(10);
488 dram_efficiency.full = dfixed_const(7);
489 dram_efficiency.full = dfixed_div(dram_efficiency, a);
490 bandwidth.full = dfixed_mul(dram_channels, yclk);
491 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
492
493 return dfixed_trunc(bandwidth);
494}
495
496static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
497{
498 /* Calculate DRAM Bandwidth and the part allocated to display. */
499 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
500 fixed20_12 yclk, dram_channels, bandwidth;
501 fixed20_12 a;
502
503 a.full = dfixed_const(1000);
504 yclk.full = dfixed_const(wm->yclk);
505 yclk.full = dfixed_div(yclk, a);
506 dram_channels.full = dfixed_const(wm->dram_channels * 4);
507 a.full = dfixed_const(10);
508 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
509 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
510 bandwidth.full = dfixed_mul(dram_channels, yclk);
511 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
512
513 return dfixed_trunc(bandwidth);
514}
515
516static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
517{
518 /* Calculate the display Data return Bandwidth */
519 fixed20_12 return_efficiency; /* 0.8 */
520 fixed20_12 sclk, bandwidth;
521 fixed20_12 a;
522
523 a.full = dfixed_const(1000);
524 sclk.full = dfixed_const(wm->sclk);
525 sclk.full = dfixed_div(sclk, a);
526 a.full = dfixed_const(10);
527 return_efficiency.full = dfixed_const(8);
528 return_efficiency.full = dfixed_div(return_efficiency, a);
529 a.full = dfixed_const(32);
530 bandwidth.full = dfixed_mul(a, sclk);
531 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
532
533 return dfixed_trunc(bandwidth);
534}
535
536static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
537{
538 /* Calculate the DMIF Request Bandwidth */
539 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
540 fixed20_12 disp_clk, bandwidth;
541 fixed20_12 a;
542
543 a.full = dfixed_const(1000);
544 disp_clk.full = dfixed_const(wm->disp_clk);
545 disp_clk.full = dfixed_div(disp_clk, a);
546 a.full = dfixed_const(10);
547 disp_clk_request_efficiency.full = dfixed_const(8);
548 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
549 a.full = dfixed_const(32);
550 bandwidth.full = dfixed_mul(a, disp_clk);
551 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
552
553 return dfixed_trunc(bandwidth);
554}
555
556static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
557{
558 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
559 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
560 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
561 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
562
563 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
564}
565
566static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
567{
568 /* Calculate the display mode Average Bandwidth
569 * DisplayMode should contain the source and destination dimensions,
570 * timing, etc.
571 */
572 fixed20_12 bpp;
573 fixed20_12 line_time;
574 fixed20_12 src_width;
575 fixed20_12 bandwidth;
576 fixed20_12 a;
577
578 a.full = dfixed_const(1000);
579 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
580 line_time.full = dfixed_div(line_time, a);
581 bpp.full = dfixed_const(wm->bytes_per_pixel);
582 src_width.full = dfixed_const(wm->src_width);
583 bandwidth.full = dfixed_mul(src_width, bpp);
584 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
585 bandwidth.full = dfixed_div(bandwidth, line_time);
586
587 return dfixed_trunc(bandwidth);
588}
589
590static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
591{
592 /* First calcualte the latency in ns */
593 u32 mc_latency = 2000; /* 2000 ns. */
594 u32 available_bandwidth = evergreen_available_bandwidth(wm);
595 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
596 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
597 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
598 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
599 (wm->num_heads * cursor_line_pair_return_time);
600 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
601 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
602 fixed20_12 a, b, c;
603
604 if (wm->num_heads == 0)
605 return 0;
606
607 a.full = dfixed_const(2);
608 b.full = dfixed_const(1);
609 if ((wm->vsc.full > a.full) ||
610 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
611 (wm->vtaps >= 5) ||
612 ((wm->vsc.full >= a.full) && wm->interlaced))
613 max_src_lines_per_dst_line = 4;
614 else
615 max_src_lines_per_dst_line = 2;
616
617 a.full = dfixed_const(available_bandwidth);
618 b.full = dfixed_const(wm->num_heads);
619 a.full = dfixed_div(a, b);
620
621 b.full = dfixed_const(1000);
622 c.full = dfixed_const(wm->disp_clk);
623 b.full = dfixed_div(c, b);
624 c.full = dfixed_const(wm->bytes_per_pixel);
625 b.full = dfixed_mul(b, c);
626
627 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
628
629 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
630 b.full = dfixed_const(1000);
631 c.full = dfixed_const(lb_fill_bw);
632 b.full = dfixed_div(c, b);
633 a.full = dfixed_div(a, b);
634 line_fill_time = dfixed_trunc(a);
635
636 if (line_fill_time < wm->active_time)
637 return latency;
638 else
639 return latency + (line_fill_time - wm->active_time);
640
641}
642
643static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
644{
645 if (evergreen_average_bandwidth(wm) <=
646 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
647 return true;
648 else
649 return false;
650};
651
652static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
653{
654 if (evergreen_average_bandwidth(wm) <=
655 (evergreen_available_bandwidth(wm) / wm->num_heads))
656 return true;
657 else
658 return false;
659};
660
661static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
662{
663 u32 lb_partitions = wm->lb_size / wm->src_width;
664 u32 line_time = wm->active_time + wm->blank_time;
665 u32 latency_tolerant_lines;
666 u32 latency_hiding;
667 fixed20_12 a;
668
669 a.full = dfixed_const(1);
670 if (wm->vsc.full > a.full)
671 latency_tolerant_lines = 1;
672 else {
673 if (lb_partitions <= (wm->vtaps + 1))
674 latency_tolerant_lines = 1;
675 else
676 latency_tolerant_lines = 2;
677 }
678
679 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
680
681 if (evergreen_latency_watermark(wm) <= latency_hiding)
682 return true;
683 else
684 return false;
685}
686
687static void evergreen_program_watermarks(struct radeon_device *rdev,
688 struct radeon_crtc *radeon_crtc,
689 u32 lb_size, u32 num_heads)
690{
691 struct drm_display_mode *mode = &radeon_crtc->base.mode;
692 struct evergreen_wm_params wm;
693 u32 pixel_period;
694 u32 line_time = 0;
695 u32 latency_watermark_a = 0, latency_watermark_b = 0;
696 u32 priority_a_mark = 0, priority_b_mark = 0;
697 u32 priority_a_cnt = PRIORITY_OFF;
698 u32 priority_b_cnt = PRIORITY_OFF;
699 u32 pipe_offset = radeon_crtc->crtc_id * 16;
700 u32 tmp, arb_control3;
701 fixed20_12 a, b, c;
702
703 if (radeon_crtc->base.enabled && num_heads && mode) {
704 pixel_period = 1000000 / (u32)mode->clock;
705 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
706 priority_a_cnt = 0;
707 priority_b_cnt = 0;
708
709 wm.yclk = rdev->pm.current_mclk * 10;
710 wm.sclk = rdev->pm.current_sclk * 10;
711 wm.disp_clk = mode->clock;
712 wm.src_width = mode->crtc_hdisplay;
713 wm.active_time = mode->crtc_hdisplay * pixel_period;
714 wm.blank_time = line_time - wm.active_time;
715 wm.interlaced = false;
716 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
717 wm.interlaced = true;
718 wm.vsc = radeon_crtc->vsc;
719 wm.vtaps = 1;
720 if (radeon_crtc->rmx_type != RMX_OFF)
721 wm.vtaps = 2;
722 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
723 wm.lb_size = lb_size;
724 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
725 wm.num_heads = num_heads;
726
727 /* set for high clocks */
728 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
729 /* set for low clocks */
730 /* wm.yclk = low clk; wm.sclk = low clk */
731 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
732
733 /* possibly force display priority to high */
734 /* should really do this at mode validation time... */
735 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
736 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
737 !evergreen_check_latency_hiding(&wm) ||
738 (rdev->disp_priority == 2)) {
739 DRM_INFO("force priority to high\n");
740 priority_a_cnt |= PRIORITY_ALWAYS_ON;
741 priority_b_cnt |= PRIORITY_ALWAYS_ON;
742 }
743
744 a.full = dfixed_const(1000);
745 b.full = dfixed_const(mode->clock);
746 b.full = dfixed_div(b, a);
747 c.full = dfixed_const(latency_watermark_a);
748 c.full = dfixed_mul(c, b);
749 c.full = dfixed_mul(c, radeon_crtc->hsc);
750 c.full = dfixed_div(c, a);
751 a.full = dfixed_const(16);
752 c.full = dfixed_div(c, a);
753 priority_a_mark = dfixed_trunc(c);
754 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
755
756 a.full = dfixed_const(1000);
757 b.full = dfixed_const(mode->clock);
758 b.full = dfixed_div(b, a);
759 c.full = dfixed_const(latency_watermark_b);
760 c.full = dfixed_mul(c, b);
761 c.full = dfixed_mul(c, radeon_crtc->hsc);
762 c.full = dfixed_div(c, a);
763 a.full = dfixed_const(16);
764 c.full = dfixed_div(c, a);
765 priority_b_mark = dfixed_trunc(c);
766 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
767 }
768
769 /* select wm A */
770 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
771 tmp = arb_control3;
772 tmp &= ~LATENCY_WATERMARK_MASK(3);
773 tmp |= LATENCY_WATERMARK_MASK(1);
774 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
775 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
776 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
777 LATENCY_HIGH_WATERMARK(line_time)));
778 /* select wm B */
779 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
780 tmp &= ~LATENCY_WATERMARK_MASK(3);
781 tmp |= LATENCY_WATERMARK_MASK(2);
782 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
783 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
784 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
785 LATENCY_HIGH_WATERMARK(line_time)));
786 /* restore original selection */
787 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
788
789 /* write the priority marks */
790 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
791 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
792
793}
794
0ca2ab52 795void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 796{
f9d9c362
AD		 797 struct drm_display_mode *mode0 = NULL;
798 struct drm_display_mode *mode1 = NULL;
799 u32 num_heads = 0, lb_size;
800 int i;
801
802 radeon_update_display_priority(rdev);
803
804 for (i = 0; i < rdev->num_crtc; i++) {
805 if (rdev->mode_info.crtcs[i]->base.enabled)
806 num_heads++;
807 }
808 for (i = 0; i < rdev->num_crtc; i += 2) {
809 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
810 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
811 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
812 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
813 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
814 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
815 }
bcc1c2a1
AD		 816}
817
b9952a8a 818int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 819{
820 unsigned i;
821 u32 tmp;
822
823 for (i = 0; i < rdev->usec_timeout; i++) {
824 /* read MC_STATUS */
825 tmp = RREG32(SRBM_STATUS) & 0x1F00;
826 if (!tmp)
827 return 0;
828 udelay(1);
829 }
830 return -1;
831}
832
833/*
834 * GART
835 */
0fcdb61e
AD		 836void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
837{
838 unsigned i;
839 u32 tmp;
840
6f2f48a9
AD		 841 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
842
0fcdb61e
AD		 843 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
844 for (i = 0; i < rdev->usec_timeout; i++) {
845 /* read MC_STATUS */
846 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
847 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
848 if (tmp == 2) {
849 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
850 return;
851 }
852 if (tmp) {
853 return;
854 }
855 udelay(1);
856 }
857}
858
bcc1c2a1
AD		 859int evergreen_pcie_gart_enable(struct radeon_device *rdev)
860{
861 u32 tmp;
0fcdb61e 862 int r;
bcc1c2a1
AD		 863
864 if (rdev->gart.table.vram.robj == NULL) {
865 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
866 return -EINVAL;
867 }
868 r = radeon_gart_table_vram_pin(rdev);
869 if (r)
870 return r;
82568565 871 radeon_gart_restore(rdev);
bcc1c2a1
AD		 872 /* Setup L2 cache */
873 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
874 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
875 EFFECTIVE_L2_QUEUE_SIZE(7));
876 WREG32(VM_L2_CNTL2, 0);
877 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
878 /* Setup TLB control */
879 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
880 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
881 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
882 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 883 if (rdev->flags & RADEON_IS_IGP) {
884 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
885 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
886 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
887 } else {
888 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
889 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
890 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
891 }
bcc1c2a1
AD		 892 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
893 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
894 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
895 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
896 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
897 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
898 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
899 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
900 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
901 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
902 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 903 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 904
0fcdb61e 905 evergreen_pcie_gart_tlb_flush(rdev);
bcc1c2a1
AD		 906 rdev->gart.ready = true;
907 return 0;
908}
909
910void evergreen_pcie_gart_disable(struct radeon_device *rdev)
911{
912 u32 tmp;
0fcdb61e 913 int r;
bcc1c2a1
AD		 914
915 /* Disable all tables */
0fcdb61e
AD		 916 WREG32(VM_CONTEXT0_CNTL, 0);
917 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 918
919 /* Setup L2 cache */
920 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
921 EFFECTIVE_L2_QUEUE_SIZE(7));
922 WREG32(VM_L2_CNTL2, 0);
923 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
924 /* Setup TLB control */
925 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
926 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
927 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
928 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
929 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
930 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
931 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
932 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
933 if (rdev->gart.table.vram.robj) {
934 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
935 if (likely(r == 0)) {
936 radeon_bo_kunmap(rdev->gart.table.vram.robj);
937 radeon_bo_unpin(rdev->gart.table.vram.robj);
938 radeon_bo_unreserve(rdev->gart.table.vram.robj);
939 }
940 }
941}
942
943void evergreen_pcie_gart_fini(struct radeon_device *rdev)
944{
945 evergreen_pcie_gart_disable(rdev);
946 radeon_gart_table_vram_free(rdev);
947 radeon_gart_fini(rdev);
948}
949
950
951void evergreen_agp_enable(struct radeon_device *rdev)
952{
953 u32 tmp;
bcc1c2a1
AD		 954
955 /* Setup L2 cache */
956 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
957 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
958 EFFECTIVE_L2_QUEUE_SIZE(7));
959 WREG32(VM_L2_CNTL2, 0);
960 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
961 /* Setup TLB control */
962 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
963 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
964 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
965 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
966 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
967 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
968 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
969 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
970 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
971 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
972 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 973 WREG32(VM_CONTEXT0_CNTL, 0);
974 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 975}
976
b9952a8a 977void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 978{
979 save->vga_control[0] = RREG32(D1VGA_CONTROL);
980 save->vga_control[1] = RREG32(D2VGA_CONTROL);
981 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
982 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
983 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
984 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
985 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
986 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
987 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
988 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
18007401
AD		 989 if (!(rdev->flags & RADEON_IS_IGP)) {
990 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
991 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
992 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
993 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
994 }
bcc1c2a1
AD		 995
996 /* Stop all video */
997 WREG32(VGA_RENDER_CONTROL, 0);
998 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
999 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
18007401
AD		 1000 if (!(rdev->flags & RADEON_IS_IGP)) {
1001 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1002 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1003 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1004 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1005 }
bcc1c2a1
AD		 1006 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1007 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 1008 if (!(rdev->flags & RADEON_IS_IGP)) {
1009 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1010 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1011 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1012 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1013 }
bcc1c2a1
AD		 1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 1016 if (!(rdev->flags & RADEON_IS_IGP)) {
1017 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1018 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1019 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1020 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1021 }
bcc1c2a1
AD		 1022
1023 WREG32(D1VGA_CONTROL, 0);
1024 WREG32(D2VGA_CONTROL, 0);
1025 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1026 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1027 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1028 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1029}
1030
b9952a8a 1031void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1032{
1033 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1034 upper_32_bits(rdev->mc.vram_start));
1035 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1036 upper_32_bits(rdev->mc.vram_start));
1037 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1038 (u32)rdev->mc.vram_start);
1039 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1040 (u32)rdev->mc.vram_start);
1041
1042 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1043 upper_32_bits(rdev->mc.vram_start));
1044 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1045 upper_32_bits(rdev->mc.vram_start));
1046 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1047 (u32)rdev->mc.vram_start);
1048 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1049 (u32)rdev->mc.vram_start);
1050
18007401
AD		 1051 if (!(rdev->flags & RADEON_IS_IGP)) {
1052 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1053 upper_32_bits(rdev->mc.vram_start));
1054 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1055 upper_32_bits(rdev->mc.vram_start));
1056 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1057 (u32)rdev->mc.vram_start);
1058 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1059 (u32)rdev->mc.vram_start);
1060
1061 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1062 upper_32_bits(rdev->mc.vram_start));
1063 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1064 upper_32_bits(rdev->mc.vram_start));
1065 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1066 (u32)rdev->mc.vram_start);
1067 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1068 (u32)rdev->mc.vram_start);
1069
1070 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1071 upper_32_bits(rdev->mc.vram_start));
1072 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1073 upper_32_bits(rdev->mc.vram_start));
1074 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1075 (u32)rdev->mc.vram_start);
1076 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1077 (u32)rdev->mc.vram_start);
1078
1079 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1080 upper_32_bits(rdev->mc.vram_start));
1081 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1082 upper_32_bits(rdev->mc.vram_start));
1083 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1084 (u32)rdev->mc.vram_start);
1085 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1086 (u32)rdev->mc.vram_start);
1087 }
bcc1c2a1
AD		 1088
1089 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1090 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1091 /* Unlock host access */
1092 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1093 mdelay(1);
1094 /* Restore video state */
1095 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1096 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1097 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1098 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1099 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1100 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1101 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1102 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
18007401
AD		 1103 if (!(rdev->flags & RADEON_IS_IGP)) {
1104 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1105 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1106 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1107 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1108 }
bcc1c2a1
AD		 1109 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1110 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
18007401
AD		 1111 if (!(rdev->flags & RADEON_IS_IGP)) {
1112 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1113 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1114 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1115 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1116 }
bcc1c2a1
AD		 1117 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1118 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 1119 if (!(rdev->flags & RADEON_IS_IGP)) {
1120 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1121 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1122 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1123 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1124 }
bcc1c2a1
AD		 1125 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1126}
1127
755d819e 1128void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1129{
1130 struct evergreen_mc_save save;
1131 u32 tmp;
1132 int i, j;
1133
1134 /* Initialize HDP */
1135 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1136 WREG32((0x2c14 + j), 0x00000000);
1137 WREG32((0x2c18 + j), 0x00000000);
1138 WREG32((0x2c1c + j), 0x00000000);
1139 WREG32((0x2c20 + j), 0x00000000);
1140 WREG32((0x2c24 + j), 0x00000000);
1141 }
1142 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1143
1144 evergreen_mc_stop(rdev, &save);
1145 if (evergreen_mc_wait_for_idle(rdev)) {
1146 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1147 }
1148 /* Lockout access through VGA aperture*/
1149 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1150 /* Update configuration */
1151 if (rdev->flags & RADEON_IS_AGP) {
1152 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1153 /* VRAM before AGP */
1154 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1155 rdev->mc.vram_start >> 12);
1156 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1157 rdev->mc.gtt_end >> 12);
1158 } else {
1159 /* VRAM after AGP */
1160 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1161 rdev->mc.gtt_start >> 12);
1162 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1163 rdev->mc.vram_end >> 12);
1164 }
1165 } else {
1166 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1167 rdev->mc.vram_start >> 12);
1168 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1169 rdev->mc.vram_end >> 12);
1170 }
1171 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
b4183e30
AD		 1172 if (rdev->flags & RADEON_IS_IGP) {
1173 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1174 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1175 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1176 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1177 }
bcc1c2a1
AD		 1178 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1179 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1180 WREG32(MC_VM_FB_LOCATION, tmp);
1181 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1182 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1183 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1184 if (rdev->flags & RADEON_IS_AGP) {
1185 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1186 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1187 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1188 } else {
1189 WREG32(MC_VM_AGP_BASE, 0);
1190 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1191 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1192 }
1193 if (evergreen_mc_wait_for_idle(rdev)) {
1194 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1195 }
1196 evergreen_mc_resume(rdev, &save);
1197 /* we need to own VRAM, so turn off the VGA renderer here
1198 * to stop it overwriting our objects */
1199 rv515_vga_render_disable(rdev);
1200}
1201
bcc1c2a1
AD		 1202/*
1203 * CP.
1204 */
12920591
AD		 1205void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1206{
1207 /* set to DX10/11 mode */
1208 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1209 radeon_ring_write(rdev, 1);
1210 /* FIXME: implement */
1211 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
0f234f5f
AD		 1212 radeon_ring_write(rdev,
1213#ifdef __BIG_ENDIAN
1214 (2 << 0) |
1215#endif
1216 (ib->gpu_addr & 0xFFFFFFFC));
12920591
AD		 1217 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1218 radeon_ring_write(rdev, ib->length_dw);
1219}
1220
bcc1c2a1
AD		 1221
1222static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1223{
fe251e2f
AD		 1224 const __be32 *fw_data;
1225 int i;
1226
1227 if (!rdev->me_fw || !rdev->pfp_fw)
1228 return -EINVAL;
bcc1c2a1 1229
fe251e2f 1230 r700_cp_stop(rdev);
0f234f5f
AD		 1231 WREG32(CP_RB_CNTL,
1232#ifdef __BIG_ENDIAN
1233 BUF_SWAP_32BIT |
1234#endif
1235 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1236
1237 fw_data = (const __be32 *)rdev->pfp_fw->data;
1238 WREG32(CP_PFP_UCODE_ADDR, 0);
1239 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1240 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1241 WREG32(CP_PFP_UCODE_ADDR, 0);
1242
1243 fw_data = (const __be32 *)rdev->me_fw->data;
1244 WREG32(CP_ME_RAM_WADDR, 0);
1245 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1246 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1247
1248 WREG32(CP_PFP_UCODE_ADDR, 0);
1249 WREG32(CP_ME_RAM_WADDR, 0);
1250 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1251 return 0;
1252}
1253
7e7b41d2
AD		 1254static int evergreen_cp_start(struct radeon_device *rdev)
1255{
2281a378 1256 int r, i;
7e7b41d2
AD		 1257 uint32_t cp_me;
1258
1259 r = radeon_ring_lock(rdev, 7);
1260 if (r) {
1261 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1262 return r;
1263 }
1264 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1265 radeon_ring_write(rdev, 0x1);
1266 radeon_ring_write(rdev, 0x0);
1267 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1268 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1269 radeon_ring_write(rdev, 0);
1270 radeon_ring_write(rdev, 0);
1271 radeon_ring_unlock_commit(rdev);
1272
1273 cp_me = 0xff;
1274 WREG32(CP_ME_CNTL, cp_me);
1275
18ff84da 1276 r = radeon_ring_lock(rdev, evergreen_default_size + 19);
7e7b41d2
AD		 1277 if (r) {
1278 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1279 return r;
1280 }
2281a378
AD		 1281
1282 /* setup clear context state */
1283 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1284 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1285
1286 for (i = 0; i < evergreen_default_size; i++)
1287 radeon_ring_write(rdev, evergreen_default_state[i]);
1288
1289 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1290 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1291
1292 /* set clear context state */
1293 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1294 radeon_ring_write(rdev, 0);
1295
1296 /* SQ_VTX_BASE_VTX_LOC */
1297 radeon_ring_write(rdev, 0xc0026f00);
1298 radeon_ring_write(rdev, 0x00000000);
1299 radeon_ring_write(rdev, 0x00000000);
1300 radeon_ring_write(rdev, 0x00000000);
1301
1302 /* Clear consts */
1303 radeon_ring_write(rdev, 0xc0036f00);
1304 radeon_ring_write(rdev, 0x00000bc4);
1305 radeon_ring_write(rdev, 0xffffffff);
1306 radeon_ring_write(rdev, 0xffffffff);
1307 radeon_ring_write(rdev, 0xffffffff);
1308
18ff84da
AD		 1309 radeon_ring_write(rdev, 0xc0026900);
1310 radeon_ring_write(rdev, 0x00000316);
1311 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1312 radeon_ring_write(rdev, 0x00000010); /* */
1313
7e7b41d2
AD		 1314 radeon_ring_unlock_commit(rdev);
1315
1316 return 0;
1317}
1318
fe251e2f
AD		 1319int evergreen_cp_resume(struct radeon_device *rdev)
1320{
1321 u32 tmp;
1322 u32 rb_bufsz;
1323 int r;
1324
1325 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1326 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1327 SOFT_RESET_PA |
1328 SOFT_RESET_SH |
1329 SOFT_RESET_VGT |
1330 SOFT_RESET_SX));
1331 RREG32(GRBM_SOFT_RESET);
1332 mdelay(15);
1333 WREG32(GRBM_SOFT_RESET, 0);
1334 RREG32(GRBM_SOFT_RESET);
1335
1336 /* Set ring buffer size */
1337 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 1338 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1339#ifdef __BIG_ENDIAN
1340 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1341#endif
fe251e2f
AD		 1342 WREG32(CP_RB_CNTL, tmp);
1343 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1344
1345 /* Set the write pointer delay */
1346 WREG32(CP_RB_WPTR_DELAY, 0);
1347
1348 /* Initialize the ring buffer's read and write pointers */
1349 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1350 WREG32(CP_RB_RPTR_WR, 0);
1351 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 1352
1353 /* set the wb address wether it's enabled or not */
0f234f5f
AD		 1354 WREG32(CP_RB_RPTR_ADDR,
1355#ifdef __BIG_ENDIAN
1356 RB_RPTR_SWAP(2) |
1357#endif
1358 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1359 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1360 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1361
1362 if (rdev->wb.enabled)
1363 WREG32(SCRATCH_UMSK, 0xff);
1364 else {
1365 tmp |= RB_NO_UPDATE;
1366 WREG32(SCRATCH_UMSK, 0);
1367 }
1368
fe251e2f
AD		 1369 mdelay(1);
1370 WREG32(CP_RB_CNTL, tmp);
1371
1372 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1373 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1374
1375 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1376 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1377
7e7b41d2 1378 evergreen_cp_start(rdev);
fe251e2f
AD		 1379 rdev->cp.ready = true;
1380 r = radeon_ring_test(rdev);
1381 if (r) {
1382 rdev->cp.ready = false;
1383 return r;
1384 }
1385 return 0;
1386}
bcc1c2a1
AD		 1387
1388/*
1389 * Core functions
1390 */
32fcdbf4
AD		 1391static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1392 u32 num_tile_pipes,
bcc1c2a1
AD		 1393 u32 num_backends,
1394 u32 backend_disable_mask)
1395{
1396 u32 backend_map = 0;
32fcdbf4
AD		 1397 u32 enabled_backends_mask = 0;
1398 u32 enabled_backends_count = 0;
1399 u32 cur_pipe;
1400 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1401 u32 cur_backend = 0;
1402 u32 i;
1403 bool force_no_swizzle;
1404
1405 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1406 num_tile_pipes = EVERGREEN_MAX_PIPES;
1407 if (num_tile_pipes < 1)
1408 num_tile_pipes = 1;
1409 if (num_backends > EVERGREEN_MAX_BACKENDS)
1410 num_backends = EVERGREEN_MAX_BACKENDS;
1411 if (num_backends < 1)
1412 num_backends = 1;
1413
1414 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1415 if (((backend_disable_mask >> i) & 1) == 0) {
1416 enabled_backends_mask |= (1 << i);
1417 ++enabled_backends_count;
1418 }
1419 if (enabled_backends_count == num_backends)
1420 break;
1421 }
1422
1423 if (enabled_backends_count == 0) {
1424 enabled_backends_mask = 1;
1425 enabled_backends_count = 1;
1426 }
1427
1428 if (enabled_backends_count != num_backends)
1429 num_backends = enabled_backends_count;
1430
1431 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1432 switch (rdev->family) {
1433 case CHIP_CEDAR:
1434 case CHIP_REDWOOD:
d5e455e4 1435 case CHIP_PALM:
adb68fa2
AD		 1436 case CHIP_TURKS:
1437 case CHIP_CAICOS:
32fcdbf4
AD		 1438 force_no_swizzle = false;
1439 break;
1440 case CHIP_CYPRESS:
1441 case CHIP_HEMLOCK:
1442 case CHIP_JUNIPER:
adb68fa2 1443 case CHIP_BARTS:
32fcdbf4
AD		 1444 default:
1445 force_no_swizzle = true;
1446 break;
1447 }
1448 if (force_no_swizzle) {
1449 bool last_backend_enabled = false;
1450
1451 force_no_swizzle = false;
1452 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1453 if (((enabled_backends_mask >> i) & 1) == 1) {
1454 if (last_backend_enabled)
1455 force_no_swizzle = true;
1456 last_backend_enabled = true;
1457 } else
1458 last_backend_enabled = false;
1459 }
1460 }
1461
1462 switch (num_tile_pipes) {
1463 case 1:
1464 case 3:
1465 case 5:
1466 case 7:
1467 DRM_ERROR("odd number of pipes!\n");
1468 break;
1469 case 2:
1470 swizzle_pipe[0] = 0;
1471 swizzle_pipe[1] = 1;
1472 break;
1473 case 4:
1474 if (force_no_swizzle) {
1475 swizzle_pipe[0] = 0;
1476 swizzle_pipe[1] = 1;
1477 swizzle_pipe[2] = 2;
1478 swizzle_pipe[3] = 3;
1479 } else {
1480 swizzle_pipe[0] = 0;
1481 swizzle_pipe[1] = 2;
1482 swizzle_pipe[2] = 1;
1483 swizzle_pipe[3] = 3;
1484 }
1485 break;
1486 case 6:
1487 if (force_no_swizzle) {
1488 swizzle_pipe[0] = 0;
1489 swizzle_pipe[1] = 1;
1490 swizzle_pipe[2] = 2;
1491 swizzle_pipe[3] = 3;
1492 swizzle_pipe[4] = 4;
1493 swizzle_pipe[5] = 5;
1494 } else {
1495 swizzle_pipe[0] = 0;
1496 swizzle_pipe[1] = 2;
1497 swizzle_pipe[2] = 4;
1498 swizzle_pipe[3] = 1;
1499 swizzle_pipe[4] = 3;
1500 swizzle_pipe[5] = 5;
1501 }
1502 break;
1503 case 8:
1504 if (force_no_swizzle) {
1505 swizzle_pipe[0] = 0;
1506 swizzle_pipe[1] = 1;
1507 swizzle_pipe[2] = 2;
1508 swizzle_pipe[3] = 3;
1509 swizzle_pipe[4] = 4;
1510 swizzle_pipe[5] = 5;
1511 swizzle_pipe[6] = 6;
1512 swizzle_pipe[7] = 7;
1513 } else {
1514 swizzle_pipe[0] = 0;
1515 swizzle_pipe[1] = 2;
1516 swizzle_pipe[2] = 4;
1517 swizzle_pipe[3] = 6;
1518 swizzle_pipe[4] = 1;
1519 swizzle_pipe[5] = 3;
1520 swizzle_pipe[6] = 5;
1521 swizzle_pipe[7] = 7;
1522 }
1523 break;
1524 }
1525
1526 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1527 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1528 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1529
1530 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1531
1532 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1533 }
bcc1c2a1
AD		 1534
1535 return backend_map;
1536}
bcc1c2a1 1537
9535ab73
AD		 1538static void evergreen_program_channel_remap(struct radeon_device *rdev)
1539{
1540 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1541
1542 tmp = RREG32(MC_SHARED_CHMAP);
1543 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1544 case 0:
1545 case 1:
1546 case 2:
1547 case 3:
1548 default:
1549 /* default mapping */
1550 mc_shared_chremap = 0x00fac688;
1551 break;
1552 }
1553
1554 switch (rdev->family) {
1555 case CHIP_HEMLOCK:
1556 case CHIP_CYPRESS:
adb68fa2 1557 case CHIP_BARTS:
9535ab73
AD		 1558 tcp_chan_steer_lo = 0x54763210;
1559 tcp_chan_steer_hi = 0x0000ba98;
1560 break;
1561 case CHIP_JUNIPER:
1562 case CHIP_REDWOOD:
1563 case CHIP_CEDAR:
d5e455e4 1564 case CHIP_PALM:
adb68fa2
AD		 1565 case CHIP_TURKS:
1566 case CHIP_CAICOS:
9535ab73
AD		 1567 default:
1568 tcp_chan_steer_lo = 0x76543210;
1569 tcp_chan_steer_hi = 0x0000ba98;
1570 break;
1571 }
1572
1573 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1574 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1575 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1576}
1577
bcc1c2a1
AD		 1578static void evergreen_gpu_init(struct radeon_device *rdev)
1579{
32fcdbf4
AD		 1580 u32 cc_rb_backend_disable = 0;
1581 u32 cc_gc_shader_pipe_config;
1582 u32 gb_addr_config = 0;
1583 u32 mc_shared_chmap, mc_arb_ramcfg;
1584 u32 gb_backend_map;
1585 u32 grbm_gfx_index;
1586 u32 sx_debug_1;
1587 u32 smx_dc_ctl0;
1588 u32 sq_config;
1589 u32 sq_lds_resource_mgmt;
1590 u32 sq_gpr_resource_mgmt_1;
1591 u32 sq_gpr_resource_mgmt_2;
1592 u32 sq_gpr_resource_mgmt_3;
1593 u32 sq_thread_resource_mgmt;
1594 u32 sq_thread_resource_mgmt_2;
1595 u32 sq_stack_resource_mgmt_1;
1596 u32 sq_stack_resource_mgmt_2;
1597 u32 sq_stack_resource_mgmt_3;
1598 u32 vgt_cache_invalidation;
f25a5c63 1599 u32 hdp_host_path_cntl, tmp;
32fcdbf4
AD		 1600 int i, j, num_shader_engines, ps_thread_count;
1601
1602 switch (rdev->family) {
1603 case CHIP_CYPRESS:
1604 case CHIP_HEMLOCK:
1605 rdev->config.evergreen.num_ses = 2;
1606 rdev->config.evergreen.max_pipes = 4;
1607 rdev->config.evergreen.max_tile_pipes = 8;
1608 rdev->config.evergreen.max_simds = 10;
1609 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1610 rdev->config.evergreen.max_gprs = 256;
1611 rdev->config.evergreen.max_threads = 248;
1612 rdev->config.evergreen.max_gs_threads = 32;
1613 rdev->config.evergreen.max_stack_entries = 512;
1614 rdev->config.evergreen.sx_num_of_sets = 4;
1615 rdev->config.evergreen.sx_max_export_size = 256;
1616 rdev->config.evergreen.sx_max_export_pos_size = 64;
1617 rdev->config.evergreen.sx_max_export_smx_size = 192;
1618 rdev->config.evergreen.max_hw_contexts = 8;
1619 rdev->config.evergreen.sq_num_cf_insts = 2;
1620
1621 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1622 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1623 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1624 break;
1625 case CHIP_JUNIPER:
1626 rdev->config.evergreen.num_ses = 1;
1627 rdev->config.evergreen.max_pipes = 4;
1628 rdev->config.evergreen.max_tile_pipes = 4;
1629 rdev->config.evergreen.max_simds = 10;
1630 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1631 rdev->config.evergreen.max_gprs = 256;
1632 rdev->config.evergreen.max_threads = 248;
1633 rdev->config.evergreen.max_gs_threads = 32;
1634 rdev->config.evergreen.max_stack_entries = 512;
1635 rdev->config.evergreen.sx_num_of_sets = 4;
1636 rdev->config.evergreen.sx_max_export_size = 256;
1637 rdev->config.evergreen.sx_max_export_pos_size = 64;
1638 rdev->config.evergreen.sx_max_export_smx_size = 192;
1639 rdev->config.evergreen.max_hw_contexts = 8;
1640 rdev->config.evergreen.sq_num_cf_insts = 2;
1641
1642 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1643 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1644 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1645 break;
1646 case CHIP_REDWOOD:
1647 rdev->config.evergreen.num_ses = 1;
1648 rdev->config.evergreen.max_pipes = 4;
1649 rdev->config.evergreen.max_tile_pipes = 4;
1650 rdev->config.evergreen.max_simds = 5;
1651 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1652 rdev->config.evergreen.max_gprs = 256;
1653 rdev->config.evergreen.max_threads = 248;
1654 rdev->config.evergreen.max_gs_threads = 32;
1655 rdev->config.evergreen.max_stack_entries = 256;
1656 rdev->config.evergreen.sx_num_of_sets = 4;
1657 rdev->config.evergreen.sx_max_export_size = 256;
1658 rdev->config.evergreen.sx_max_export_pos_size = 64;
1659 rdev->config.evergreen.sx_max_export_smx_size = 192;
1660 rdev->config.evergreen.max_hw_contexts = 8;
1661 rdev->config.evergreen.sq_num_cf_insts = 2;
1662
1663 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1664 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1665 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1666 break;
1667 case CHIP_CEDAR:
1668 default:
1669 rdev->config.evergreen.num_ses = 1;
1670 rdev->config.evergreen.max_pipes = 2;
1671 rdev->config.evergreen.max_tile_pipes = 2;
1672 rdev->config.evergreen.max_simds = 2;
1673 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1674 rdev->config.evergreen.max_gprs = 256;
1675 rdev->config.evergreen.max_threads = 192;
1676 rdev->config.evergreen.max_gs_threads = 16;
1677 rdev->config.evergreen.max_stack_entries = 256;
1678 rdev->config.evergreen.sx_num_of_sets = 4;
1679 rdev->config.evergreen.sx_max_export_size = 128;
1680 rdev->config.evergreen.sx_max_export_pos_size = 32;
1681 rdev->config.evergreen.sx_max_export_smx_size = 96;
1682 rdev->config.evergreen.max_hw_contexts = 4;
1683 rdev->config.evergreen.sq_num_cf_insts = 1;
1684
d5e455e4
AD		 1685 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1686 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1687 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1688 break;
1689 case CHIP_PALM:
1690 rdev->config.evergreen.num_ses = 1;
1691 rdev->config.evergreen.max_pipes = 2;
1692 rdev->config.evergreen.max_tile_pipes = 2;
1693 rdev->config.evergreen.max_simds = 2;
1694 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1695 rdev->config.evergreen.max_gprs = 256;
1696 rdev->config.evergreen.max_threads = 192;
1697 rdev->config.evergreen.max_gs_threads = 16;
1698 rdev->config.evergreen.max_stack_entries = 256;
1699 rdev->config.evergreen.sx_num_of_sets = 4;
1700 rdev->config.evergreen.sx_max_export_size = 128;
1701 rdev->config.evergreen.sx_max_export_pos_size = 32;
1702 rdev->config.evergreen.sx_max_export_smx_size = 96;
1703 rdev->config.evergreen.max_hw_contexts = 4;
1704 rdev->config.evergreen.sq_num_cf_insts = 1;
1705
adb68fa2
AD		 1706 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1707 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1708 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1709 break;
1710 case CHIP_BARTS:
1711 rdev->config.evergreen.num_ses = 2;
1712 rdev->config.evergreen.max_pipes = 4;
1713 rdev->config.evergreen.max_tile_pipes = 8;
1714 rdev->config.evergreen.max_simds = 7;
1715 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1716 rdev->config.evergreen.max_gprs = 256;
1717 rdev->config.evergreen.max_threads = 248;
1718 rdev->config.evergreen.max_gs_threads = 32;
1719 rdev->config.evergreen.max_stack_entries = 512;
1720 rdev->config.evergreen.sx_num_of_sets = 4;
1721 rdev->config.evergreen.sx_max_export_size = 256;
1722 rdev->config.evergreen.sx_max_export_pos_size = 64;
1723 rdev->config.evergreen.sx_max_export_smx_size = 192;
1724 rdev->config.evergreen.max_hw_contexts = 8;
1725 rdev->config.evergreen.sq_num_cf_insts = 2;
1726
1727 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1728 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1729 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1730 break;
1731 case CHIP_TURKS:
1732 rdev->config.evergreen.num_ses = 1;
1733 rdev->config.evergreen.max_pipes = 4;
1734 rdev->config.evergreen.max_tile_pipes = 4;
1735 rdev->config.evergreen.max_simds = 6;
1736 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1737 rdev->config.evergreen.max_gprs = 256;
1738 rdev->config.evergreen.max_threads = 248;
1739 rdev->config.evergreen.max_gs_threads = 32;
1740 rdev->config.evergreen.max_stack_entries = 256;
1741 rdev->config.evergreen.sx_num_of_sets = 4;
1742 rdev->config.evergreen.sx_max_export_size = 256;
1743 rdev->config.evergreen.sx_max_export_pos_size = 64;
1744 rdev->config.evergreen.sx_max_export_smx_size = 192;
1745 rdev->config.evergreen.max_hw_contexts = 8;
1746 rdev->config.evergreen.sq_num_cf_insts = 2;
1747
1748 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1749 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1750 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1751 break;
1752 case CHIP_CAICOS:
1753 rdev->config.evergreen.num_ses = 1;
1754 rdev->config.evergreen.max_pipes = 4;
1755 rdev->config.evergreen.max_tile_pipes = 2;
1756 rdev->config.evergreen.max_simds = 2;
1757 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1758 rdev->config.evergreen.max_gprs = 256;
1759 rdev->config.evergreen.max_threads = 192;
1760 rdev->config.evergreen.max_gs_threads = 16;
1761 rdev->config.evergreen.max_stack_entries = 256;
1762 rdev->config.evergreen.sx_num_of_sets = 4;
1763 rdev->config.evergreen.sx_max_export_size = 128;
1764 rdev->config.evergreen.sx_max_export_pos_size = 32;
1765 rdev->config.evergreen.sx_max_export_smx_size = 96;
1766 rdev->config.evergreen.max_hw_contexts = 4;
1767 rdev->config.evergreen.sq_num_cf_insts = 1;
1768
32fcdbf4
AD		 1769 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1770 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1771 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1772 break;
1773 }
1774
1775 /* Initialize HDP */
1776 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1777 WREG32((0x2c14 + j), 0x00000000);
1778 WREG32((0x2c18 + j), 0x00000000);
1779 WREG32((0x2c1c + j), 0x00000000);
1780 WREG32((0x2c20 + j), 0x00000000);
1781 WREG32((0x2c24 + j), 0x00000000);
1782 }
1783
1784 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1785
1786 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1787
1788 cc_gc_shader_pipe_config |=
1789 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1790 & EVERGREEN_MAX_PIPES_MASK);
1791 cc_gc_shader_pipe_config |=
1792 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1793 & EVERGREEN_MAX_SIMDS_MASK);
1794
1795 cc_rb_backend_disable =
1796 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1797 & EVERGREEN_MAX_BACKENDS_MASK);
1798
1799
1800 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1801 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1802
1803 switch (rdev->config.evergreen.max_tile_pipes) {
1804 case 1:
1805 default:
1806 gb_addr_config |= NUM_PIPES(0);
1807 break;
1808 case 2:
1809 gb_addr_config |= NUM_PIPES(1);
1810 break;
1811 case 4:
1812 gb_addr_config |= NUM_PIPES(2);
1813 break;
1814 case 8:
1815 gb_addr_config |= NUM_PIPES(3);
1816 break;
1817 }
1818
1819 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1820 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1821 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1822 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1823 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1824 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1825
1826 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1827 gb_addr_config |= ROW_SIZE(2);
1828 else
1829 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1830
1831 if (rdev->ddev->pdev->device == 0x689e) {
1832 u32 efuse_straps_4;
1833 u32 efuse_straps_3;
1834 u8 efuse_box_bit_131_124;
1835
1836 WREG32(RCU_IND_INDEX, 0x204);
1837 efuse_straps_4 = RREG32(RCU_IND_DATA);
1838 WREG32(RCU_IND_INDEX, 0x203);
1839 efuse_straps_3 = RREG32(RCU_IND_DATA);
1840 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1841
1842 switch(efuse_box_bit_131_124) {
1843 case 0x00:
1844 gb_backend_map = 0x76543210;
1845 break;
1846 case 0x55:
1847 gb_backend_map = 0x77553311;
1848 break;
1849 case 0x56:
1850 gb_backend_map = 0x77553300;
1851 break;
1852 case 0x59:
1853 gb_backend_map = 0x77552211;
1854 break;
1855 case 0x66:
1856 gb_backend_map = 0x77443300;
1857 break;
1858 case 0x99:
1859 gb_backend_map = 0x66552211;
1860 break;
1861 case 0x5a:
1862 gb_backend_map = 0x77552200;
1863 break;
1864 case 0xaa:
1865 gb_backend_map = 0x66442200;
1866 break;
1867 case 0x95:
1868 gb_backend_map = 0x66553311;
1869 break;
1870 default:
1871 DRM_ERROR("bad backend map, using default\n");
1872 gb_backend_map =
1873 evergreen_get_tile_pipe_to_backend_map(rdev,
1874 rdev->config.evergreen.max_tile_pipes,
1875 rdev->config.evergreen.max_backends,
1876 ((EVERGREEN_MAX_BACKENDS_MASK <<
1877 rdev->config.evergreen.max_backends) &
1878 EVERGREEN_MAX_BACKENDS_MASK));
1879 break;
1880 }
1881 } else if (rdev->ddev->pdev->device == 0x68b9) {
1882 u32 efuse_straps_3;
1883 u8 efuse_box_bit_127_124;
1884
1885 WREG32(RCU_IND_INDEX, 0x203);
1886 efuse_straps_3 = RREG32(RCU_IND_DATA);
d31dba58 1887 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
32fcdbf4
AD		 1888
1889 switch(efuse_box_bit_127_124) {
1890 case 0x0:
1891 gb_backend_map = 0x00003210;
1892 break;
1893 case 0x5:
1894 case 0x6:
1895 case 0x9:
1896 case 0xa:
1897 gb_backend_map = 0x00003311;
1898 break;
1899 default:
1900 DRM_ERROR("bad backend map, using default\n");
1901 gb_backend_map =
1902 evergreen_get_tile_pipe_to_backend_map(rdev,
1903 rdev->config.evergreen.max_tile_pipes,
1904 rdev->config.evergreen.max_backends,
1905 ((EVERGREEN_MAX_BACKENDS_MASK <<
1906 rdev->config.evergreen.max_backends) &
1907 EVERGREEN_MAX_BACKENDS_MASK));
1908 break;
1909 }
b741be82
AD		 1910 } else {
1911 switch (rdev->family) {
1912 case CHIP_CYPRESS:
1913 case CHIP_HEMLOCK:
03f40090 1914 case CHIP_BARTS:
b741be82
AD		 1915 gb_backend_map = 0x66442200;
1916 break;
1917 case CHIP_JUNIPER:
1918 gb_backend_map = 0x00006420;
1919 break;
1920 default:
1921 gb_backend_map =
1922 evergreen_get_tile_pipe_to_backend_map(rdev,
1923 rdev->config.evergreen.max_tile_pipes,
1924 rdev->config.evergreen.max_backends,
1925 ((EVERGREEN_MAX_BACKENDS_MASK <<
1926 rdev->config.evergreen.max_backends) &
1927 EVERGREEN_MAX_BACKENDS_MASK));
1928 }
1929 }
32fcdbf4 1930
1aa52bd3
AD		 1931 /* setup tiling info dword. gb_addr_config is not adequate since it does
1932 * not have bank info, so create a custom tiling dword.
1933 * bits 3:0 num_pipes
1934 * bits 7:4 num_banks
1935 * bits 11:8 group_size
1936 * bits 15:12 row_size
1937 */
1938 rdev->config.evergreen.tile_config = 0;
1939 switch (rdev->config.evergreen.max_tile_pipes) {
1940 case 1:
1941 default:
1942 rdev->config.evergreen.tile_config |= (0 << 0);
1943 break;
1944 case 2:
1945 rdev->config.evergreen.tile_config |= (1 << 0);
1946 break;
1947 case 4:
1948 rdev->config.evergreen.tile_config |= (2 << 0);
1949 break;
1950 case 8:
1951 rdev->config.evergreen.tile_config |= (3 << 0);
1952 break;
1953 }
5bfa4879
AD		 1954 /* num banks is 8 on all fusion asics */
1955 if (rdev->flags & RADEON_IS_IGP)
1956 rdev->config.evergreen.tile_config |= 8 << 4;
1957 else
1958 rdev->config.evergreen.tile_config |=
1959 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1aa52bd3
AD		 1960 rdev->config.evergreen.tile_config |=
1961 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1962 rdev->config.evergreen.tile_config |=
1963 ((gb_addr_config & 0x30000000) >> 28) << 12;
1964
32fcdbf4
AD		 1965 WREG32(GB_BACKEND_MAP, gb_backend_map);
1966 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1967 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1968 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1969
9535ab73
AD		 1970 evergreen_program_channel_remap(rdev);
1971
32fcdbf4
AD		 1972 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1973 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1974
1975 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1976 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1977 u32 sp = cc_gc_shader_pipe_config;
1978 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1979
1980 if (i == num_shader_engines) {
1981 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1982 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1983 }
1984
1985 WREG32(GRBM_GFX_INDEX, gfx);
1986 WREG32(RLC_GFX_INDEX, gfx);
1987
1988 WREG32(CC_RB_BACKEND_DISABLE, rb);
1989 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1990 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1991 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1992 }
1993
1994 grbm_gfx_index |= SE_BROADCAST_WRITES;
1995 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1996 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1997
1998 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1999 WREG32(CGTS_TCC_DISABLE, 0);
2000 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2001 WREG32(CGTS_USER_TCC_DISABLE, 0);
2002
2003 /* set HW defaults for 3D engine */
2004 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2005 ROQ_IB2_START(0x2b)));
2006
2007 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2008
2009 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2010 SYNC_GRADIENT |
2011 SYNC_WALKER |
2012 SYNC_ALIGNER));
2013
2014 sx_debug_1 = RREG32(SX_DEBUG_1);
2015 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2016 WREG32(SX_DEBUG_1, sx_debug_1);
2017
2018
2019 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2020 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2021 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2022 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2023
2024 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2025 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2026 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2027
2028 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2029 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2030 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2031
2032 WREG32(VGT_NUM_INSTANCES, 1);
2033 WREG32(SPI_CONFIG_CNTL, 0);
2034 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2035 WREG32(CP_PERFMON_CNTL, 0);
2036
2037 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2038 FETCH_FIFO_HIWATER(0x4) |
2039 DONE_FIFO_HIWATER(0xe0) |
2040 ALU_UPDATE_FIFO_HIWATER(0x8)));
2041
2042 sq_config = RREG32(SQ_CONFIG);
2043 sq_config &= ~(PS_PRIO(3) |
2044 VS_PRIO(3) |
2045 GS_PRIO(3) |
2046 ES_PRIO(3));
2047 sq_config |= (VC_ENABLE |
2048 EXPORT_SRC_C |
2049 PS_PRIO(0) |
2050 VS_PRIO(1) |
2051 GS_PRIO(2) |
2052 ES_PRIO(3));
2053
d5e455e4
AD		 2054 switch (rdev->family) {
2055 case CHIP_CEDAR:
2056 case CHIP_PALM:
adb68fa2 2057 case CHIP_CAICOS:
32fcdbf4
AD		 2058 /* no vertex cache */
2059 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 2060 break;
2061 default:
2062 break;
2063 }
32fcdbf4
AD		 2064
2065 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2066
2067 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2068 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2069 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2070 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2071 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2072 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2073 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2074
d5e455e4
AD		 2075 switch (rdev->family) {
2076 case CHIP_CEDAR:
2077 case CHIP_PALM:
32fcdbf4 2078 ps_thread_count = 96;
d5e455e4
AD		 2079 break;
2080 default:
32fcdbf4 2081 ps_thread_count = 128;
d5e455e4
AD		 2082 break;
2083 }
32fcdbf4
AD		 2084
2085 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2086 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2087 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2088 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2089 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2090 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2091
2092 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2093 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2094 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2095 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2096 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2097 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2098
2099 WREG32(SQ_CONFIG, sq_config);
2100 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2101 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2102 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2103 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2104 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2105 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2106 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2107 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2108 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2109 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2110
2111 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2112 FORCE_EOV_MAX_REZ_CNT(255)));
2113
d5e455e4
AD		 2114 switch (rdev->family) {
2115 case CHIP_CEDAR:
2116 case CHIP_PALM:
adb68fa2 2117 case CHIP_CAICOS:
32fcdbf4 2118 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2119 break;
2120 default:
32fcdbf4 2121 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2122 break;
2123 }
32fcdbf4
AD		 2124 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2125 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2126
2127 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2128 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2129 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2130
60a4a3e0
AD		 2131 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2132 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2133
32fcdbf4
AD		 2134 WREG32(CB_PERF_CTR0_SEL_0, 0);
2135 WREG32(CB_PERF_CTR0_SEL_1, 0);
2136 WREG32(CB_PERF_CTR1_SEL_0, 0);
2137 WREG32(CB_PERF_CTR1_SEL_1, 0);
2138 WREG32(CB_PERF_CTR2_SEL_0, 0);
2139 WREG32(CB_PERF_CTR2_SEL_1, 0);
2140 WREG32(CB_PERF_CTR3_SEL_0, 0);
2141 WREG32(CB_PERF_CTR3_SEL_1, 0);
2142
60a4a3e0
AD		 2143 /* clear render buffer base addresses */
2144 WREG32(CB_COLOR0_BASE, 0);
2145 WREG32(CB_COLOR1_BASE, 0);
2146 WREG32(CB_COLOR2_BASE, 0);
2147 WREG32(CB_COLOR3_BASE, 0);
2148 WREG32(CB_COLOR4_BASE, 0);
2149 WREG32(CB_COLOR5_BASE, 0);
2150 WREG32(CB_COLOR6_BASE, 0);
2151 WREG32(CB_COLOR7_BASE, 0);
2152 WREG32(CB_COLOR8_BASE, 0);
2153 WREG32(CB_COLOR9_BASE, 0);
2154 WREG32(CB_COLOR10_BASE, 0);
2155 WREG32(CB_COLOR11_BASE, 0);
2156
2157 /* set the shader const cache sizes to 0 */
2158 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2159 WREG32(i, 0);
2160 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2161 WREG32(i, 0);
2162
f25a5c63
AD		 2163 tmp = RREG32(HDP_MISC_CNTL);
2164 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2165 WREG32(HDP_MISC_CNTL, tmp);
2166
32fcdbf4
AD		 2167 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2168 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2169
2170 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2171
2172 udelay(50);
2173
bcc1c2a1
AD		 2174}
2175
2176int evergreen_mc_init(struct radeon_device *rdev)
2177{
bcc1c2a1
AD		 2178 u32 tmp;
2179 int chansize, numchan;
bcc1c2a1
AD		 2180
2181 /* Get VRAM informations */
2182 rdev->mc.vram_is_ddr = true;
2183 tmp = RREG32(MC_ARB_RAMCFG);
2184 if (tmp & CHANSIZE_OVERRIDE) {
2185 chansize = 16;
2186 } else if (tmp & CHANSIZE_MASK) {
2187 chansize = 64;
2188 } else {
2189 chansize = 32;
2190 }
2191 tmp = RREG32(MC_SHARED_CHMAP);
2192 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2193 case 0:
2194 default:
2195 numchan = 1;
2196 break;
2197 case 1:
2198 numchan = 2;
2199 break;
2200 case 2:
2201 numchan = 4;
2202 break;
2203 case 3:
2204 numchan = 8;
2205 break;
2206 }
2207 rdev->mc.vram_width = numchan * chansize;
2208 /* Could aper size report 0 ? */
01d73a69
JC		 2209 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2210 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2211 /* Setup GPU memory space */
6eb18f8b
AD		 2212 if (rdev->flags & RADEON_IS_IGP) {
2213 /* size in bytes on fusion */
2214 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2215 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2216 } else {
2217 /* size in MB on evergreen */
2218 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2219 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2220 }
51e5fcd3 2221 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2222 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2223 radeon_update_bandwidth_info(rdev);
2224
bcc1c2a1
AD		 2225 return 0;
2226}
d594e46a 2227
225758d8
JG		 2228bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2229{
17db7042
AD		 2230 u32 srbm_status;
2231 u32 grbm_status;
2232 u32 grbm_status_se0, grbm_status_se1;
2233 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2234 int r;
2235
2236 srbm_status = RREG32(SRBM_STATUS);
2237 grbm_status = RREG32(GRBM_STATUS);
2238 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2239 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2240 if (!(grbm_status & GUI_ACTIVE)) {
2241 r100_gpu_lockup_update(lockup, &rdev->cp);
2242 return false;
2243 }
2244 /* force CP activities */
2245 r = radeon_ring_lock(rdev, 2);
2246 if (!r) {
2247 /* PACKET2 NOP */
2248 radeon_ring_write(rdev, 0x80000000);
2249 radeon_ring_write(rdev, 0x80000000);
2250 radeon_ring_unlock_commit(rdev);
2251 }
2252 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2253 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
225758d8
JG		 2254}
2255
747943ea 2256static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 2257{
747943ea 2258 struct evergreen_mc_save save;
747943ea
AD		 2259 u32 grbm_reset = 0;
2260
8d96fe93
AD		 2261 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2262 return 0;
2263
747943ea
AD		 2264 dev_info(rdev->dev, "GPU softreset \n");
2265 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2266 RREG32(GRBM_STATUS));
2267 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2268 RREG32(GRBM_STATUS_SE0));
2269 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2270 RREG32(GRBM_STATUS_SE1));
2271 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2272 RREG32(SRBM_STATUS));
2273 evergreen_mc_stop(rdev, &save);
2274 if (evergreen_mc_wait_for_idle(rdev)) {
2275 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2276 }
2277 /* Disable CP parsing/prefetching */
2278 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2279
2280 /* reset all the gfx blocks */
2281 grbm_reset = (SOFT_RESET_CP |
2282 SOFT_RESET_CB |
2283 SOFT_RESET_DB |
2284 SOFT_RESET_PA |
2285 SOFT_RESET_SC |
2286 SOFT_RESET_SPI |
2287 SOFT_RESET_SH |
2288 SOFT_RESET_SX |
2289 SOFT_RESET_TC |
2290 SOFT_RESET_TA |
2291 SOFT_RESET_VC |
2292 SOFT_RESET_VGT);
2293
2294 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2295 WREG32(GRBM_SOFT_RESET, grbm_reset);
2296 (void)RREG32(GRBM_SOFT_RESET);
2297 udelay(50);
2298 WREG32(GRBM_SOFT_RESET, 0);
2299 (void)RREG32(GRBM_SOFT_RESET);
747943ea
AD		 2300 /* Wait a little for things to settle down */
2301 udelay(50);
2302 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2303 RREG32(GRBM_STATUS));
2304 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2305 RREG32(GRBM_STATUS_SE0));
2306 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2307 RREG32(GRBM_STATUS_SE1));
2308 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2309 RREG32(SRBM_STATUS));
747943ea 2310 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2311 return 0;
2312}
2313
a2d07b74 2314int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2315{
747943ea
AD		 2316 return evergreen_gpu_soft_reset(rdev);
2317}
2318
45f9a39b
AD		 2319/* Interrupts */
2320
2321u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2322{
2323 switch (crtc) {
2324 case 0:
2325 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2326 case 1:
2327 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2328 case 2:
2329 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2330 case 3:
2331 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2332 case 4:
2333 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2334 case 5:
2335 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2336 default:
2337 return 0;
2338 }
2339}
2340
2341void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2342{
2343 u32 tmp;
2344
3555e53b 2345 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2346 WREG32(GRBM_INT_CNTL, 0);
2347 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2348 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 2349 if (!(rdev->flags & RADEON_IS_IGP)) {
2350 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2351 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2352 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2353 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2354 }
45f9a39b
AD		 2355
2356 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2357 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 2358 if (!(rdev->flags & RADEON_IS_IGP)) {
2359 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2360 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2361 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2362 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2363 }
45f9a39b
AD		 2364
2365 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2366 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2367
2368 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2369 WREG32(DC_HPD1_INT_CONTROL, tmp);
2370 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2371 WREG32(DC_HPD2_INT_CONTROL, tmp);
2372 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2373 WREG32(DC_HPD3_INT_CONTROL, tmp);
2374 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2375 WREG32(DC_HPD4_INT_CONTROL, tmp);
2376 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2377 WREG32(DC_HPD5_INT_CONTROL, tmp);
2378 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2379 WREG32(DC_HPD6_INT_CONTROL, tmp);
2380
2381}
2382
2383int evergreen_irq_set(struct radeon_device *rdev)
2384{
2385 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2386 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2387 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2388 u32 grbm_int_cntl = 0;
6f34be50 2389 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
45f9a39b
AD		 2390
2391 if (!rdev->irq.installed) {
fce7d61b 2392 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2393 return -EINVAL;
2394 }
2395 /* don't enable anything if the ih is disabled */
2396 if (!rdev->ih.enabled) {
2397 r600_disable_interrupts(rdev);
2398 /* force the active interrupt state to all disabled */
2399 evergreen_disable_interrupt_state(rdev);
2400 return 0;
2401 }
2402
2403 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2404 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2405 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2406 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2407 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2408 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2409
2410 if (rdev->irq.sw_int) {
2411 DRM_DEBUG("evergreen_irq_set: sw int\n");
2412 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 2413 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
45f9a39b 2414 }
6f34be50
AD		 2415 if (rdev->irq.crtc_vblank_int[0] ||
2416 rdev->irq.pflip[0]) {
45f9a39b
AD		 2417 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2418 crtc1 |= VBLANK_INT_MASK;
2419 }
6f34be50
AD		 2420 if (rdev->irq.crtc_vblank_int[1] ||
2421 rdev->irq.pflip[1]) {
45f9a39b
AD		 2422 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2423 crtc2 |= VBLANK_INT_MASK;
2424 }
6f34be50
AD		 2425 if (rdev->irq.crtc_vblank_int[2] ||
2426 rdev->irq.pflip[2]) {
45f9a39b
AD		 2427 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2428 crtc3 |= VBLANK_INT_MASK;
2429 }
6f34be50
AD		 2430 if (rdev->irq.crtc_vblank_int[3] ||
2431 rdev->irq.pflip[3]) {
45f9a39b
AD		 2432 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2433 crtc4 |= VBLANK_INT_MASK;
2434 }
6f34be50
AD		 2435 if (rdev->irq.crtc_vblank_int[4] ||
2436 rdev->irq.pflip[4]) {
45f9a39b
AD		 2437 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2438 crtc5 |= VBLANK_INT_MASK;
2439 }
6f34be50
AD		 2440 if (rdev->irq.crtc_vblank_int[5] ||
2441 rdev->irq.pflip[5]) {
45f9a39b
AD		 2442 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2443 crtc6 |= VBLANK_INT_MASK;
2444 }
2445 if (rdev->irq.hpd[0]) {
2446 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2447 hpd1 |= DC_HPDx_INT_EN;
2448 }
2449 if (rdev->irq.hpd[1]) {
2450 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2451 hpd2 |= DC_HPDx_INT_EN;
2452 }
2453 if (rdev->irq.hpd[2]) {
2454 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2455 hpd3 |= DC_HPDx_INT_EN;
2456 }
2457 if (rdev->irq.hpd[3]) {
2458 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2459 hpd4 |= DC_HPDx_INT_EN;
2460 }
2461 if (rdev->irq.hpd[4]) {
2462 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2463 hpd5 |= DC_HPDx_INT_EN;
2464 }
2465 if (rdev->irq.hpd[5]) {
2466 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2467 hpd6 |= DC_HPDx_INT_EN;
2468 }
2031f77c
AD		 2469 if (rdev->irq.gui_idle) {
2470 DRM_DEBUG("gui idle\n");
2471 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2472 }
45f9a39b
AD		 2473
2474 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2475 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2476
2477 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2478 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
18007401
AD		 2479 if (!(rdev->flags & RADEON_IS_IGP)) {
2480 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2481 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2482 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2483 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2484 }
45f9a39b 2485
6f34be50
AD		 2486 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2487 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2488 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2489 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2490 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2491 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2492
45f9a39b
AD		 2493 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2494 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2495 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2496 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2497 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2498 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2499
bcc1c2a1
AD		 2500 return 0;
2501}
2502
6f34be50 2503static inline void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2504{
2505 u32 tmp;
2506
6f34be50
AD		 2507 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2508 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2509 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2510 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2511 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2512 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2513 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2514 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2515 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2516 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2517 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2518 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2519
2520 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2521 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2522 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2523 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2524 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2525 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2526 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2527 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2528 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2529 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2530 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2531 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2532
2533 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2534 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2535 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b
AD		 2536 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2537
6f34be50 2538 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2539 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2540 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2541 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2542
6f34be50 2543 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
45f9a39b 2544 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2545 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
45f9a39b
AD		 2546 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2547
6f34be50 2548 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
45f9a39b 2549 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2550 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
45f9a39b
AD		 2551 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2552
6f34be50 2553 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
45f9a39b 2554 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2555 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
45f9a39b
AD		 2556 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2557
6f34be50 2558 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
45f9a39b 2559 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2560 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
45f9a39b
AD		 2561 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2562
6f34be50 2563 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2564 tmp = RREG32(DC_HPD1_INT_CONTROL);
2565 tmp |= DC_HPDx_INT_ACK;
2566 WREG32(DC_HPD1_INT_CONTROL, tmp);
2567 }
6f34be50 2568 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2569 tmp = RREG32(DC_HPD2_INT_CONTROL);
2570 tmp |= DC_HPDx_INT_ACK;
2571 WREG32(DC_HPD2_INT_CONTROL, tmp);
2572 }
6f34be50 2573 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2574 tmp = RREG32(DC_HPD3_INT_CONTROL);
2575 tmp |= DC_HPDx_INT_ACK;
2576 WREG32(DC_HPD3_INT_CONTROL, tmp);
2577 }
6f34be50 2578 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2579 tmp = RREG32(DC_HPD4_INT_CONTROL);
2580 tmp |= DC_HPDx_INT_ACK;
2581 WREG32(DC_HPD4_INT_CONTROL, tmp);
2582 }
6f34be50 2583 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2584 tmp = RREG32(DC_HPD5_INT_CONTROL);
2585 tmp |= DC_HPDx_INT_ACK;
2586 WREG32(DC_HPD5_INT_CONTROL, tmp);
2587 }
6f34be50 2588 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2589 tmp = RREG32(DC_HPD5_INT_CONTROL);
2590 tmp |= DC_HPDx_INT_ACK;
2591 WREG32(DC_HPD6_INT_CONTROL, tmp);
2592 }
2593}
2594
2595void evergreen_irq_disable(struct radeon_device *rdev)
2596{
45f9a39b
AD		 2597 r600_disable_interrupts(rdev);
2598 /* Wait and acknowledge irq */
2599 mdelay(1);
6f34be50 2600 evergreen_irq_ack(rdev);
45f9a39b
AD		 2601 evergreen_disable_interrupt_state(rdev);
2602}
2603
755d819e 2604void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 2605{
2606 evergreen_irq_disable(rdev);
2607 r600_rlc_stop(rdev);
2608}
2609
2610static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2611{
2612 u32 wptr, tmp;
2613
724c80e1 2614 if (rdev->wb.enabled)
204ae24d 2615 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 2616 else
2617 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2618
2619 if (wptr & RB_OVERFLOW) {
2620 /* When a ring buffer overflow happen start parsing interrupt
2621 * from the last not overwritten vector (wptr + 16). Hopefully
2622 * this should allow us to catchup.
2623 */
2624 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2625 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2626 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2627 tmp = RREG32(IH_RB_CNTL);
2628 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2629 WREG32(IH_RB_CNTL, tmp);
2630 }
2631 return (wptr & rdev->ih.ptr_mask);
2632}
2633
2634int evergreen_irq_process(struct radeon_device *rdev)
2635{
2636 u32 wptr = evergreen_get_ih_wptr(rdev);
2637 u32 rptr = rdev->ih.rptr;
2638 u32 src_id, src_data;
2639 u32 ring_index;
45f9a39b
AD		 2640 unsigned long flags;
2641 bool queue_hotplug = false;
2642
2643 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2644 if (!rdev->ih.enabled)
2645 return IRQ_NONE;
2646
2647 spin_lock_irqsave(&rdev->ih.lock, flags);
2648
2649 if (rptr == wptr) {
2650 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2651 return IRQ_NONE;
2652 }
2653 if (rdev->shutdown) {
2654 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2655 return IRQ_NONE;
2656 }
2657
2658restart_ih:
2659 /* display interrupts */
6f34be50 2660 evergreen_irq_ack(rdev);
45f9a39b
AD		 2661
2662 rdev->ih.wptr = wptr;
2663 while (rptr != wptr) {
2664 /* wptr/rptr are in bytes! */
2665 ring_index = rptr / 4;
0f234f5f
AD		 2666 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2667 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 2668
2669 switch (src_id) {
2670 case 1: /* D1 vblank/vline */
2671 switch (src_data) {
2672 case 0: /* D1 vblank */
6f34be50 2673 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 2674 if (rdev->irq.crtc_vblank_int[0]) {
2675 drm_handle_vblank(rdev->ddev, 0);
2676 rdev->pm.vblank_sync = true;
2677 wake_up(&rdev->irq.vblank_queue);
2678 }
3e4ea742
MK		 2679 if (rdev->irq.pflip[0])
2680 radeon_crtc_handle_flip(rdev, 0);
6f34be50 2681 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2682 DRM_DEBUG("IH: D1 vblank\n");
2683 }
2684 break;
2685 case 1: /* D1 vline */
6f34be50
AD		 2686 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2687 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 2688 DRM_DEBUG("IH: D1 vline\n");
2689 }
2690 break;
2691 default:
2692 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2693 break;
2694 }
2695 break;
2696 case 2: /* D2 vblank/vline */
2697 switch (src_data) {
2698 case 0: /* D2 vblank */
6f34be50 2699 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 2700 if (rdev->irq.crtc_vblank_int[1]) {
2701 drm_handle_vblank(rdev->ddev, 1);
2702 rdev->pm.vblank_sync = true;
2703 wake_up(&rdev->irq.vblank_queue);
2704 }
3e4ea742
MK		 2705 if (rdev->irq.pflip[1])
2706 radeon_crtc_handle_flip(rdev, 1);
6f34be50 2707 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 2708 DRM_DEBUG("IH: D2 vblank\n");
2709 }
2710 break;
2711 case 1: /* D2 vline */
6f34be50
AD		 2712 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2713 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 2714 DRM_DEBUG("IH: D2 vline\n");
2715 }
2716 break;
2717 default:
2718 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2719 break;
2720 }
2721 break;
2722 case 3: /* D3 vblank/vline */
2723 switch (src_data) {
2724 case 0: /* D3 vblank */
6f34be50
AD		 2725 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2726 if (rdev->irq.crtc_vblank_int[2]) {
2727 drm_handle_vblank(rdev->ddev, 2);
2728 rdev->pm.vblank_sync = true;
2729 wake_up(&rdev->irq.vblank_queue);
2730 }
2731 if (rdev->irq.pflip[2])
2732 radeon_crtc_handle_flip(rdev, 2);
2733 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 2734 DRM_DEBUG("IH: D3 vblank\n");
2735 }
2736 break;
2737 case 1: /* D3 vline */
6f34be50
AD		 2738 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2739 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 2740 DRM_DEBUG("IH: D3 vline\n");
2741 }
2742 break;
2743 default:
2744 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2745 break;
2746 }
2747 break;
2748 case 4: /* D4 vblank/vline */
2749 switch (src_data) {
2750 case 0: /* D4 vblank */
6f34be50
AD		 2751 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2752 if (rdev->irq.crtc_vblank_int[3]) {
2753 drm_handle_vblank(rdev->ddev, 3);
2754 rdev->pm.vblank_sync = true;
2755 wake_up(&rdev->irq.vblank_queue);
2756 }
2757 if (rdev->irq.pflip[3])
2758 radeon_crtc_handle_flip(rdev, 3);
2759 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 2760 DRM_DEBUG("IH: D4 vblank\n");
2761 }
2762 break;
2763 case 1: /* D4 vline */
6f34be50
AD		 2764 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2765 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 2766 DRM_DEBUG("IH: D4 vline\n");
2767 }
2768 break;
2769 default:
2770 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2771 break;
2772 }
2773 break;
2774 case 5: /* D5 vblank/vline */
2775 switch (src_data) {
2776 case 0: /* D5 vblank */
6f34be50
AD		 2777 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2778 if (rdev->irq.crtc_vblank_int[4]) {
2779 drm_handle_vblank(rdev->ddev, 4);
2780 rdev->pm.vblank_sync = true;
2781 wake_up(&rdev->irq.vblank_queue);
2782 }
2783 if (rdev->irq.pflip[4])
2784 radeon_crtc_handle_flip(rdev, 4);
2785 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 2786 DRM_DEBUG("IH: D5 vblank\n");
2787 }
2788 break;
2789 case 1: /* D5 vline */
6f34be50
AD		 2790 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2791 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 2792 DRM_DEBUG("IH: D5 vline\n");
2793 }
2794 break;
2795 default:
2796 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2797 break;
2798 }
2799 break;
2800 case 6: /* D6 vblank/vline */
2801 switch (src_data) {
2802 case 0: /* D6 vblank */
6f34be50
AD		 2803 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2804 if (rdev->irq.crtc_vblank_int[5]) {
2805 drm_handle_vblank(rdev->ddev, 5);
2806 rdev->pm.vblank_sync = true;
2807 wake_up(&rdev->irq.vblank_queue);
2808 }
2809 if (rdev->irq.pflip[5])
2810 radeon_crtc_handle_flip(rdev, 5);
2811 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 2812 DRM_DEBUG("IH: D6 vblank\n");
2813 }
2814 break;
2815 case 1: /* D6 vline */
6f34be50
AD		 2816 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2817 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 2818 DRM_DEBUG("IH: D6 vline\n");
2819 }
2820 break;
2821 default:
2822 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2823 break;
2824 }
2825 break;
2826 case 42: /* HPD hotplug */
2827 switch (src_data) {
2828 case 0:
6f34be50
AD		 2829 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2830 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 2831 queue_hotplug = true;
2832 DRM_DEBUG("IH: HPD1\n");
2833 }
2834 break;
2835 case 1:
6f34be50
AD		 2836 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2837 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 2838 queue_hotplug = true;
2839 DRM_DEBUG("IH: HPD2\n");
2840 }
2841 break;
2842 case 2:
6f34be50
AD		 2843 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2844 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 2845 queue_hotplug = true;
2846 DRM_DEBUG("IH: HPD3\n");
2847 }
2848 break;
2849 case 3:
6f34be50
AD		 2850 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2851 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 2852 queue_hotplug = true;
2853 DRM_DEBUG("IH: HPD4\n");
2854 }
2855 break;
2856 case 4:
6f34be50
AD		 2857 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2858 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 2859 queue_hotplug = true;
2860 DRM_DEBUG("IH: HPD5\n");
2861 }
2862 break;
2863 case 5:
6f34be50
AD		 2864 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2865 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 2866 queue_hotplug = true;
2867 DRM_DEBUG("IH: HPD6\n");
2868 }
2869 break;
2870 default:
2871 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2872 break;
2873 }
2874 break;
2875 case 176: /* CP_INT in ring buffer */
2876 case 177: /* CP_INT in IB1 */
2877 case 178: /* CP_INT in IB2 */
2878 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2879 radeon_fence_process(rdev);
2880 break;
2881 case 181: /* CP EOP event */
2882 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 2883 radeon_fence_process(rdev);
45f9a39b 2884 break;
2031f77c
AD		 2885 case 233: /* GUI IDLE */
2886 DRM_DEBUG("IH: CP EOP\n");
2887 rdev->pm.gui_idle = true;
2888 wake_up(&rdev->irq.idle_queue);
2889 break;
45f9a39b
AD		 2890 default:
2891 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2892 break;
2893 }
2894
2895 /* wptr/rptr are in bytes! */
2896 rptr += 16;
2897 rptr &= rdev->ih.ptr_mask;
2898 }
2899 /* make sure wptr hasn't changed while processing */
2900 wptr = evergreen_get_ih_wptr(rdev);
2901 if (wptr != rdev->ih.wptr)
2902 goto restart_ih;
2903 if (queue_hotplug)
32c87fca 2904 schedule_work(&rdev->hotplug_work);
45f9a39b
AD		 2905 rdev->ih.rptr = rptr;
2906 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2907 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2908 return IRQ_HANDLED;
2909}
2910
bcc1c2a1
AD		 2911static int evergreen_startup(struct radeon_device *rdev)
2912{
bcc1c2a1
AD		 2913 int r;
2914
9e46a48d 2915 /* enable pcie gen2 link */
0d1014a2
AD		 2916 if (!ASIC_IS_DCE5(rdev))
2917 evergreen_pcie_gen2_enable(rdev);
9e46a48d 2918
0af62b01
AD		 2919 if (ASIC_IS_DCE5(rdev)) {
2920 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2921 r = ni_init_microcode(rdev);
2922 if (r) {
2923 DRM_ERROR("Failed to load firmware!\n");
2924 return r;
2925 }
2926 }
755d819e 2927 r = ni_mc_load_microcode(rdev);
bcc1c2a1 2928 if (r) {
0af62b01 2929 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 2930 return r;
2931 }
0af62b01
AD		 2932 } else {
2933 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2934 r = r600_init_microcode(rdev);
2935 if (r) {
2936 DRM_ERROR("Failed to load firmware!\n");
2937 return r;
2938 }
2939 }
bcc1c2a1 2940 }
fe251e2f 2941
bcc1c2a1 2942 evergreen_mc_program(rdev);
bcc1c2a1 2943 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 2944 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 2945 } else {
2946 r = evergreen_pcie_gart_enable(rdev);
2947 if (r)
2948 return r;
2949 }
bcc1c2a1 2950 evergreen_gpu_init(rdev);
bcc1c2a1 2951
d7ccd8fc 2952 r = evergreen_blit_init(rdev);
bcc1c2a1 2953 if (r) {
d7ccd8fc
AD		 2954 evergreen_blit_fini(rdev);
2955 rdev->asic->copy = NULL;
2956 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 2957 }
2958
724c80e1
AD		 2959 /* allocate wb buffer */
2960 r = radeon_wb_init(rdev);
2961 if (r)
2962 return r;
2963
bcc1c2a1
AD		 2964 /* Enable IRQ */
2965 r = r600_irq_init(rdev);
2966 if (r) {
2967 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2968 radeon_irq_kms_fini(rdev);
2969 return r;
2970 }
45f9a39b 2971 evergreen_irq_set(rdev);
bcc1c2a1
AD		 2972
2973 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2974 if (r)
2975 return r;
2976 r = evergreen_cp_load_microcode(rdev);
2977 if (r)
2978 return r;
fe251e2f 2979 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 2980 if (r)
2981 return r;
fe251e2f 2982
bcc1c2a1
AD		 2983 return 0;
2984}
2985
2986int evergreen_resume(struct radeon_device *rdev)
2987{
2988 int r;
2989
86f5c9ed
AD		 2990 /* reset the asic, the gfx blocks are often in a bad state
2991 * after the driver is unloaded or after a resume
2992 */
2993 if (radeon_asic_reset(rdev))
2994 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 2995 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2996 * posting will perform necessary task to bring back GPU into good
2997 * shape.
2998 */
2999 /* post card */
3000 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1
AD		 3001
3002 r = evergreen_startup(rdev);
3003 if (r) {
755d819e 3004 DRM_ERROR("evergreen startup failed on resume\n");
bcc1c2a1
AD		 3005 return r;
3006 }
fe251e2f 3007
bcc1c2a1
AD		 3008 r = r600_ib_test(rdev);
3009 if (r) {
ec4f2ac4 3010 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
bcc1c2a1
AD		 3011 return r;
3012 }
fe251e2f 3013
bcc1c2a1
AD		 3014 return r;
3015
3016}
3017
3018int evergreen_suspend(struct radeon_device *rdev)
3019{
bcc1c2a1 3020 int r;
d7ccd8fc 3021
bcc1c2a1
AD		 3022 /* FIXME: we should wait for ring to be empty */
3023 r700_cp_stop(rdev);
3024 rdev->cp.ready = false;
45f9a39b 3025 evergreen_irq_suspend(rdev);
724c80e1 3026 radeon_wb_disable(rdev);
bcc1c2a1 3027 evergreen_pcie_gart_disable(rdev);
d7ccd8fc 3028
bcc1c2a1
AD		 3029 /* unpin shaders bo */
3030 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
3031 if (likely(r == 0)) {
3032 radeon_bo_unpin(rdev->r600_blit.shader_obj);
3033 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
3034 }
d7ccd8fc
AD		 3035
3036 return 0;
3037}
3038
3039int evergreen_copy_blit(struct radeon_device *rdev,
3040 uint64_t src_offset, uint64_t dst_offset,
3041 unsigned num_pages, struct radeon_fence *fence)
3042{
3043 int r;
3044
3045 mutex_lock(&rdev->r600_blit.mutex);
3046 rdev->r600_blit.vb_ib = NULL;
3047 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
3048 if (r) {
3049 if (rdev->r600_blit.vb_ib)
3050 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3051 mutex_unlock(&rdev->r600_blit.mutex);
3052 return r;
3053 }
3054 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
3055 evergreen_blit_done_copy(rdev, fence);
3056 mutex_unlock(&rdev->r600_blit.mutex);
bcc1c2a1
AD		 3057 return 0;
3058}
3059
bcc1c2a1
AD		 3060/* Plan is to move initialization in that function and use
3061 * helper function so that radeon_device_init pretty much
3062 * do nothing more than calling asic specific function. This
3063 * should also allow to remove a bunch of callback function
3064 * like vram_info.
3065 */
3066int evergreen_init(struct radeon_device *rdev)
3067{
3068 int r;
3069
bcc1c2a1
AD		 3070 /* This don't do much */
3071 r = radeon_gem_init(rdev);
3072 if (r)
3073 return r;
3074 /* Read BIOS */
3075 if (!radeon_get_bios(rdev)) {
3076 if (ASIC_IS_AVIVO(rdev))
3077 return -EINVAL;
3078 }
3079 /* Must be an ATOMBIOS */
3080 if (!rdev->is_atom_bios) {
755d819e 3081 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 3082 return -EINVAL;
3083 }
3084 r = radeon_atombios_init(rdev);
3085 if (r)
3086 return r;
86f5c9ed
AD		 3087 /* reset the asic, the gfx blocks are often in a bad state
3088 * after the driver is unloaded or after a resume
3089 */
3090 if (radeon_asic_reset(rdev))
3091 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 3092 /* Post card if necessary */
fd909c37 3093 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 3094 if (!rdev->bios) {
3095 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3096 return -EINVAL;
3097 }
3098 DRM_INFO("GPU not posted. posting now...\n");
3099 atom_asic_init(rdev->mode_info.atom_context);
3100 }
3101 /* Initialize scratch registers */
3102 r600_scratch_init(rdev);
3103 /* Initialize surface registers */
3104 radeon_surface_init(rdev);
3105 /* Initialize clocks */
3106 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 3107 /* Fence driver */
3108 r = radeon_fence_driver_init(rdev);
3109 if (r)
3110 return r;
d594e46a
JG		 3111 /* initialize AGP */
3112 if (rdev->flags & RADEON_IS_AGP) {
3113 r = radeon_agp_init(rdev);
3114 if (r)
3115 radeon_agp_disable(rdev);
3116 }
3117 /* initialize memory controller */
bcc1c2a1
AD		 3118 r = evergreen_mc_init(rdev);
3119 if (r)
3120 return r;
3121 /* Memory manager */
3122 r = radeon_bo_init(rdev);
3123 if (r)
3124 return r;
45f9a39b 3125
bcc1c2a1
AD		 3126 r = radeon_irq_kms_init(rdev);
3127 if (r)
3128 return r;
3129
3130 rdev->cp.ring_obj = NULL;
3131 r600_ring_init(rdev, 1024 * 1024);
3132
3133 rdev->ih.ring_obj = NULL;
3134 r600_ih_ring_init(rdev, 64 * 1024);
3135
3136 r = r600_pcie_gart_init(rdev);
3137 if (r)
3138 return r;
0fcdb61e 3139
148a03bc 3140 rdev->accel_working = true;
bcc1c2a1
AD		 3141 r = evergreen_startup(rdev);
3142 if (r) {
fe251e2f
AD		 3143 dev_err(rdev->dev, "disabling GPU acceleration\n");
3144 r700_cp_fini(rdev);
fe251e2f 3145 r600_irq_fini(rdev);
724c80e1 3146 radeon_wb_fini(rdev);
fe251e2f 3147 radeon_irq_kms_fini(rdev);
0fcdb61e 3148 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3149 rdev->accel_working = false;
3150 }
3151 if (rdev->accel_working) {
3152 r = radeon_ib_pool_init(rdev);
3153 if (r) {
3154 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3155 rdev->accel_working = false;
3156 }
3157 r = r600_ib_test(rdev);
3158 if (r) {
3159 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3160 rdev->accel_working = false;
3161 }
3162 }
3163 return 0;
3164}
3165
3166void evergreen_fini(struct radeon_device *rdev)
3167{
d7ccd8fc 3168 evergreen_blit_fini(rdev);
45f9a39b 3169 r700_cp_fini(rdev);
bcc1c2a1 3170 r600_irq_fini(rdev);
724c80e1 3171 radeon_wb_fini(rdev);
bcc1c2a1 3172 radeon_irq_kms_fini(rdev);
bcc1c2a1 3173 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3174 radeon_gem_fini(rdev);
3175 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3176 radeon_agp_fini(rdev);
3177 radeon_bo_fini(rdev);
3178 radeon_atombios_fini(rdev);
3179 kfree(rdev->bios);
3180 rdev->bios = NULL;
bcc1c2a1 3181}
9e46a48d
AD		 3182
3183static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3184{
3185 u32 link_width_cntl, speed_cntl;
3186
d42dd579
AD		 3187 if (radeon_pcie_gen2 == 0)
3188 return;
3189
9e46a48d
AD		 3190 if (rdev->flags & RADEON_IS_IGP)
3191 return;
3192
3193 if (!(rdev->flags & RADEON_IS_PCIE))
3194 return;
3195
3196 /* x2 cards have a special sequence */
3197 if (ASIC_IS_X2(rdev))
3198 return;
3199
3200 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3201 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3202 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3203
3204 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3205 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3206 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3207
3208 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3209 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3210 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3211
3212 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3213 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3214 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3215
3216 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3217 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3218 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3219
3220 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3221 speed_cntl |= LC_GEN2_EN_STRAP;
3222 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3223
3224 } else {
3225 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3226 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3227 if (1)
3228 link_width_cntl |= LC_UPCONFIGURE_DIS;
3229 else
3230 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3231 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3232 }
3233}
Linux kernel - Deliverables
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