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drm/radeon: start to document the functions r100.c
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
b07759bf 42void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
1b37078b
AD		 43extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
44 int ring, u32 cp_int_cntl);
bcc1c2a1 45
285484e2
JG		 46void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
47 unsigned *bankh, unsigned *mtaspect,
48 unsigned *tile_split)
49{
50 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
51 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
52 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
53 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
54 switch (*bankw) {
55 default:
56 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
57 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
58 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
59 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
60 }
61 switch (*bankh) {
62 default:
63 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
64 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
65 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
66 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
67 }
68 switch (*mtaspect) {
69 default:
70 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
71 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
72 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
73 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
74 }
75}
76
d054ac16
AD		 77void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
78{
79 u16 ctl, v;
80 int cap, err;
81
82 cap = pci_pcie_cap(rdev->pdev);
83 if (!cap)
84 return;
85
86 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
87 if (err)
88 return;
89
90 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
91
92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
93 * to avoid hangs or perfomance issues
94 */
95 if ((v == 0) || (v == 6) || (v == 7)) {
96 ctl &= ~PCI_EXP_DEVCTL_READRQ;
97 ctl |= (2 << 12);
98 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
99 }
100}
101
3ae19b75
AD		 102void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
103{
104 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
105 int i;
106
107 if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
108 for (i = 0; i < rdev->usec_timeout; i++) {
109 if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
110 break;
111 udelay(1);
112 }
113 for (i = 0; i < rdev->usec_timeout; i++) {
114 if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
115 break;
116 udelay(1);
117 }
118 }
119}
120
6f34be50
AD		 121void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
122{
6f34be50
AD		 123 /* enable the pflip int */
124 radeon_irq_kms_pflip_irq_get(rdev, crtc);
125}
126
127void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
128{
129 /* disable the pflip int */
130 radeon_irq_kms_pflip_irq_put(rdev, crtc);
131}
132
133u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
134{
135 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
136 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 137 int i;
6f34be50
AD		 138
139 /* Lock the graphics update lock */
140 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
141 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
142
143 /* update the scanout addresses */
144 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
145 upper_32_bits(crtc_base));
146 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
147 (u32)crtc_base);
148
149 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
150 upper_32_bits(crtc_base));
151 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
152 (u32)crtc_base);
153
154 /* Wait for update_pending to go high. */
f6496479
AD		 155 for (i = 0; i < rdev->usec_timeout; i++) {
156 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
157 break;
158 udelay(1);
159 }
6f34be50
AD		 160 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
161
162 /* Unlock the lock, so double-buffering can take place inside vblank */
163 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
164 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
165
166 /* Return current update_pending status: */
167 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
168}
169
21a8122a 170/* get temperature in millidegrees */
20d391d7 171int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 172{
1c88d74f
AD		 173 u32 temp, toffset;
174 int actual_temp = 0;
67b3f823
AD		 175
176 if (rdev->family == CHIP_JUNIPER) {
177 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
178 TOFFSET_SHIFT;
179 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
180 TS0_ADC_DOUT_SHIFT;
181
182 if (toffset & 0x100)
183 actual_temp = temp / 2 - (0x200 - toffset);
184 else
185 actual_temp = temp / 2 + toffset;
186
187 actual_temp = actual_temp * 1000;
188
189 } else {
190 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
191 ASIC_T_SHIFT;
192
193 if (temp & 0x400)
194 actual_temp = -256;
195 else if (temp & 0x200)
196 actual_temp = 255;
197 else if (temp & 0x100) {
198 actual_temp = temp & 0x1ff;
199 actual_temp |= ~0x1ff;
200 } else
201 actual_temp = temp & 0xff;
202
203 actual_temp = (actual_temp * 1000) / 2;
204 }
21a8122a 205
67b3f823 206 return actual_temp;
21a8122a
AD		 207}
208
20d391d7 209int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 210{
211 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 212 int actual_temp = temp - 49;
e33df25f
AD		 213
214 return actual_temp * 1000;
215}
216
a4c9e2ee
AD		 217void sumo_pm_init_profile(struct radeon_device *rdev)
218{
219 int idx;
220
221 /* default */
222 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
223 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
224 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
225 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
226
227 /* low,mid sh/mh */
228 if (rdev->flags & RADEON_IS_MOBILITY)
229 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
230 else
231 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
232
233 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
234 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
235 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
236 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
237
238 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
239 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
240 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
241 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
242
243 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
244 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
245 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
246 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
247
248 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
249 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
250 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
251 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
252
253 /* high sh/mh */
254 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
255 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
256 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
257 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
258 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
259 rdev->pm.power_state[idx].num_clock_modes - 1;
260
261 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
262 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
263 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
264 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
265 rdev->pm.power_state[idx].num_clock_modes - 1;
266}
267
49e02b73
AD		 268void evergreen_pm_misc(struct radeon_device *rdev)
269{
a081a9d6
RM		 270 int req_ps_idx = rdev->pm.requested_power_state_index;
271 int req_cm_idx = rdev->pm.requested_clock_mode_index;
272 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
273 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 274
2feea49a 275 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 276 /* 0xff01 is a flag rather then an actual voltage */
277 if (voltage->voltage == 0xff01)
278 return;
2feea49a 279 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 280 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 281 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 282 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
283 }
a377e187
AD		 284 /* 0xff01 is a flag rather then an actual voltage */
285 if (voltage->vddci == 0xff01)
286 return;
2feea49a
AD		 287 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
288 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
289 rdev->pm.current_vddci = voltage->vddci;
290 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 291 }
292 }
49e02b73
AD		 293}
294
295void evergreen_pm_prepare(struct radeon_device *rdev)
296{
297 struct drm_device *ddev = rdev->ddev;
298 struct drm_crtc *crtc;
299 struct radeon_crtc *radeon_crtc;
300 u32 tmp;
301
302 /* disable any active CRTCs */
303 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
304 radeon_crtc = to_radeon_crtc(crtc);
305 if (radeon_crtc->enabled) {
306 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
307 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
308 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
309 }
310 }
311}
312
313void evergreen_pm_finish(struct radeon_device *rdev)
314{
315 struct drm_device *ddev = rdev->ddev;
316 struct drm_crtc *crtc;
317 struct radeon_crtc *radeon_crtc;
318 u32 tmp;
319
320 /* enable any active CRTCs */
321 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
322 radeon_crtc = to_radeon_crtc(crtc);
323 if (radeon_crtc->enabled) {
324 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
325 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
326 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
327 }
328 }
329}
330
bcc1c2a1
AD		 331bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
332{
333 bool connected = false;
0ca2ab52
AD		 334
335 switch (hpd) {
336 case RADEON_HPD_1:
337 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
338 connected = true;
339 break;
340 case RADEON_HPD_2:
341 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
342 connected = true;
343 break;
344 case RADEON_HPD_3:
345 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
346 connected = true;
347 break;
348 case RADEON_HPD_4:
349 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
350 connected = true;
351 break;
352 case RADEON_HPD_5:
353 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
354 connected = true;
355 break;
356 case RADEON_HPD_6:
357 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
358 connected = true;
359 break;
360 default:
361 break;
362 }
363
bcc1c2a1
AD		 364 return connected;
365}
366
367void evergreen_hpd_set_polarity(struct radeon_device *rdev,
368 enum radeon_hpd_id hpd)
369{
0ca2ab52
AD		 370 u32 tmp;
371 bool connected = evergreen_hpd_sense(rdev, hpd);
372
373 switch (hpd) {
374 case RADEON_HPD_1:
375 tmp = RREG32(DC_HPD1_INT_CONTROL);
376 if (connected)
377 tmp &= ~DC_HPDx_INT_POLARITY;
378 else
379 tmp |= DC_HPDx_INT_POLARITY;
380 WREG32(DC_HPD1_INT_CONTROL, tmp);
381 break;
382 case RADEON_HPD_2:
383 tmp = RREG32(DC_HPD2_INT_CONTROL);
384 if (connected)
385 tmp &= ~DC_HPDx_INT_POLARITY;
386 else
387 tmp |= DC_HPDx_INT_POLARITY;
388 WREG32(DC_HPD2_INT_CONTROL, tmp);
389 break;
390 case RADEON_HPD_3:
391 tmp = RREG32(DC_HPD3_INT_CONTROL);
392 if (connected)
393 tmp &= ~DC_HPDx_INT_POLARITY;
394 else
395 tmp |= DC_HPDx_INT_POLARITY;
396 WREG32(DC_HPD3_INT_CONTROL, tmp);
397 break;
398 case RADEON_HPD_4:
399 tmp = RREG32(DC_HPD4_INT_CONTROL);
400 if (connected)
401 tmp &= ~DC_HPDx_INT_POLARITY;
402 else
403 tmp |= DC_HPDx_INT_POLARITY;
404 WREG32(DC_HPD4_INT_CONTROL, tmp);
405 break;
406 case RADEON_HPD_5:
407 tmp = RREG32(DC_HPD5_INT_CONTROL);
408 if (connected)
409 tmp &= ~DC_HPDx_INT_POLARITY;
410 else
411 tmp |= DC_HPDx_INT_POLARITY;
412 WREG32(DC_HPD5_INT_CONTROL, tmp);
413 break;
414 case RADEON_HPD_6:
415 tmp = RREG32(DC_HPD6_INT_CONTROL);
416 if (connected)
417 tmp &= ~DC_HPDx_INT_POLARITY;
418 else
419 tmp |= DC_HPDx_INT_POLARITY;
420 WREG32(DC_HPD6_INT_CONTROL, tmp);
421 break;
422 default:
423 break;
424 }
bcc1c2a1
AD		 425}
426
427void evergreen_hpd_init(struct radeon_device *rdev)
428{
0ca2ab52
AD		 429 struct drm_device *dev = rdev->ddev;
430 struct drm_connector *connector;
fb98257a 431 unsigned enabled = 0;
0ca2ab52
AD		 432 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
433 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 434
0ca2ab52
AD		 435 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
436 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
437 switch (radeon_connector->hpd.hpd) {
438 case RADEON_HPD_1:
439 WREG32(DC_HPD1_CONTROL, tmp);
0ca2ab52
AD		 440 break;
441 case RADEON_HPD_2:
442 WREG32(DC_HPD2_CONTROL, tmp);
0ca2ab52
AD		 443 break;
444 case RADEON_HPD_3:
445 WREG32(DC_HPD3_CONTROL, tmp);
0ca2ab52
AD		 446 break;
447 case RADEON_HPD_4:
448 WREG32(DC_HPD4_CONTROL, tmp);
0ca2ab52
AD		 449 break;
450 case RADEON_HPD_5:
451 WREG32(DC_HPD5_CONTROL, tmp);
0ca2ab52
AD		 452 break;
453 case RADEON_HPD_6:
454 WREG32(DC_HPD6_CONTROL, tmp);
0ca2ab52
AD		 455 break;
456 default:
457 break;
458 }
64912e99 459 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
fb98257a 460 enabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 461 }
fb98257a 462 radeon_irq_kms_enable_hpd(rdev, enabled);
bcc1c2a1
AD		 463}
464
0ca2ab52 465void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 466{
0ca2ab52
AD		 467 struct drm_device *dev = rdev->ddev;
468 struct drm_connector *connector;
fb98257a 469 unsigned disabled = 0;
0ca2ab52
AD		 470
471 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
472 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
473 switch (radeon_connector->hpd.hpd) {
474 case RADEON_HPD_1:
475 WREG32(DC_HPD1_CONTROL, 0);
0ca2ab52
AD		 476 break;
477 case RADEON_HPD_2:
478 WREG32(DC_HPD2_CONTROL, 0);
0ca2ab52
AD		 479 break;
480 case RADEON_HPD_3:
481 WREG32(DC_HPD3_CONTROL, 0);
0ca2ab52
AD		 482 break;
483 case RADEON_HPD_4:
484 WREG32(DC_HPD4_CONTROL, 0);
0ca2ab52
AD		 485 break;
486 case RADEON_HPD_5:
487 WREG32(DC_HPD5_CONTROL, 0);
0ca2ab52
AD		 488 break;
489 case RADEON_HPD_6:
490 WREG32(DC_HPD6_CONTROL, 0);
0ca2ab52
AD		 491 break;
492 default:
493 break;
494 }
fb98257a 495 disabled |= 1 << radeon_connector->hpd.hpd;
0ca2ab52 496 }
fb98257a 497 radeon_irq_kms_disable_hpd(rdev, disabled);
bcc1c2a1
AD		 498}
499
f9d9c362
AD		 500/* watermark setup */
501
502static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
503 struct radeon_crtc *radeon_crtc,
504 struct drm_display_mode *mode,
505 struct drm_display_mode *other_mode)
506{
12dfc843 507 u32 tmp;
f9d9c362
AD		 508 /*
509 * Line Buffer Setup
510 * There are 3 line buffers, each one shared by 2 display controllers.
511 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
512 * the display controllers. The paritioning is done via one of four
513 * preset allocations specified in bits 2:0:
514 * first display controller
515 * 0 - first half of lb (3840 * 2)
516 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 517 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 518 * 3 - first 1/4 of lb (1920 * 2)
519 * second display controller
520 * 4 - second half of lb (3840 * 2)
521 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 522 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 523 * 7 - last 1/4 of lb (1920 * 2)
524 */
12dfc843
AD		 525 /* this can get tricky if we have two large displays on a paired group
526 * of crtcs. Ideally for multiple large displays we'd assign them to
527 * non-linked crtcs for maximum line buffer allocation.
528 */
529 if (radeon_crtc->base.enabled && mode) {
530 if (other_mode)
f9d9c362 531 tmp = 0; /* 1/2 */
12dfc843
AD		 532 else
533 tmp = 2; /* whole */
534 } else
535 tmp = 0;
f9d9c362
AD		 536
537 /* second controller of the pair uses second half of the lb */
538 if (radeon_crtc->crtc_id % 2)
539 tmp += 4;
540 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
541
12dfc843
AD		 542 if (radeon_crtc->base.enabled && mode) {
543 switch (tmp) {
544 case 0:
545 case 4:
546 default:
547 if (ASIC_IS_DCE5(rdev))
548 return 4096 * 2;
549 else
550 return 3840 * 2;
551 case 1:
552 case 5:
553 if (ASIC_IS_DCE5(rdev))
554 return 6144 * 2;
555 else
556 return 5760 * 2;
557 case 2:
558 case 6:
559 if (ASIC_IS_DCE5(rdev))
560 return 8192 * 2;
561 else
562 return 7680 * 2;
563 case 3:
564 case 7:
565 if (ASIC_IS_DCE5(rdev))
566 return 2048 * 2;
567 else
568 return 1920 * 2;
569 }
f9d9c362 570 }
12dfc843
AD		 571
572 /* controller not enabled, so no lb used */
573 return 0;
f9d9c362
AD		 574}
575
ca7db22b 576u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
f9d9c362
AD		 577{
578 u32 tmp = RREG32(MC_SHARED_CHMAP);
579
580 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
581 case 0:
582 default:
583 return 1;
584 case 1:
585 return 2;
586 case 2:
587 return 4;
588 case 3:
589 return 8;
590 }
591}
592
593struct evergreen_wm_params {
594 u32 dram_channels; /* number of dram channels */
595 u32 yclk; /* bandwidth per dram data pin in kHz */
596 u32 sclk; /* engine clock in kHz */
597 u32 disp_clk; /* display clock in kHz */
598 u32 src_width; /* viewport width */
599 u32 active_time; /* active display time in ns */
600 u32 blank_time; /* blank time in ns */
601 bool interlaced; /* mode is interlaced */
602 fixed20_12 vsc; /* vertical scale ratio */
603 u32 num_heads; /* number of active crtcs */
604 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
605 u32 lb_size; /* line buffer allocated to pipe */
606 u32 vtaps; /* vertical scaler taps */
607};
608
609static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
610{
611 /* Calculate DRAM Bandwidth and the part allocated to display. */
612 fixed20_12 dram_efficiency; /* 0.7 */
613 fixed20_12 yclk, dram_channels, bandwidth;
614 fixed20_12 a;
615
616 a.full = dfixed_const(1000);
617 yclk.full = dfixed_const(wm->yclk);
618 yclk.full = dfixed_div(yclk, a);
619 dram_channels.full = dfixed_const(wm->dram_channels * 4);
620 a.full = dfixed_const(10);
621 dram_efficiency.full = dfixed_const(7);
622 dram_efficiency.full = dfixed_div(dram_efficiency, a);
623 bandwidth.full = dfixed_mul(dram_channels, yclk);
624 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
625
626 return dfixed_trunc(bandwidth);
627}
628
629static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
630{
631 /* Calculate DRAM Bandwidth and the part allocated to display. */
632 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
633 fixed20_12 yclk, dram_channels, bandwidth;
634 fixed20_12 a;
635
636 a.full = dfixed_const(1000);
637 yclk.full = dfixed_const(wm->yclk);
638 yclk.full = dfixed_div(yclk, a);
639 dram_channels.full = dfixed_const(wm->dram_channels * 4);
640 a.full = dfixed_const(10);
641 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
642 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
643 bandwidth.full = dfixed_mul(dram_channels, yclk);
644 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
645
646 return dfixed_trunc(bandwidth);
647}
648
649static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
650{
651 /* Calculate the display Data return Bandwidth */
652 fixed20_12 return_efficiency; /* 0.8 */
653 fixed20_12 sclk, bandwidth;
654 fixed20_12 a;
655
656 a.full = dfixed_const(1000);
657 sclk.full = dfixed_const(wm->sclk);
658 sclk.full = dfixed_div(sclk, a);
659 a.full = dfixed_const(10);
660 return_efficiency.full = dfixed_const(8);
661 return_efficiency.full = dfixed_div(return_efficiency, a);
662 a.full = dfixed_const(32);
663 bandwidth.full = dfixed_mul(a, sclk);
664 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
665
666 return dfixed_trunc(bandwidth);
667}
668
669static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
670{
671 /* Calculate the DMIF Request Bandwidth */
672 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
673 fixed20_12 disp_clk, bandwidth;
674 fixed20_12 a;
675
676 a.full = dfixed_const(1000);
677 disp_clk.full = dfixed_const(wm->disp_clk);
678 disp_clk.full = dfixed_div(disp_clk, a);
679 a.full = dfixed_const(10);
680 disp_clk_request_efficiency.full = dfixed_const(8);
681 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
682 a.full = dfixed_const(32);
683 bandwidth.full = dfixed_mul(a, disp_clk);
684 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
685
686 return dfixed_trunc(bandwidth);
687}
688
689static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
690{
691 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
692 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
693 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
694 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
695
696 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
697}
698
699static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
700{
701 /* Calculate the display mode Average Bandwidth
702 * DisplayMode should contain the source and destination dimensions,
703 * timing, etc.
704 */
705 fixed20_12 bpp;
706 fixed20_12 line_time;
707 fixed20_12 src_width;
708 fixed20_12 bandwidth;
709 fixed20_12 a;
710
711 a.full = dfixed_const(1000);
712 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
713 line_time.full = dfixed_div(line_time, a);
714 bpp.full = dfixed_const(wm->bytes_per_pixel);
715 src_width.full = dfixed_const(wm->src_width);
716 bandwidth.full = dfixed_mul(src_width, bpp);
717 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
718 bandwidth.full = dfixed_div(bandwidth, line_time);
719
720 return dfixed_trunc(bandwidth);
721}
722
723static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
724{
725 /* First calcualte the latency in ns */
726 u32 mc_latency = 2000; /* 2000 ns. */
727 u32 available_bandwidth = evergreen_available_bandwidth(wm);
728 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
729 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
730 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
731 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
732 (wm->num_heads * cursor_line_pair_return_time);
733 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
734 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
735 fixed20_12 a, b, c;
736
737 if (wm->num_heads == 0)
738 return 0;
739
740 a.full = dfixed_const(2);
741 b.full = dfixed_const(1);
742 if ((wm->vsc.full > a.full) ||
743 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
744 (wm->vtaps >= 5) ||
745 ((wm->vsc.full >= a.full) && wm->interlaced))
746 max_src_lines_per_dst_line = 4;
747 else
748 max_src_lines_per_dst_line = 2;
749
750 a.full = dfixed_const(available_bandwidth);
751 b.full = dfixed_const(wm->num_heads);
752 a.full = dfixed_div(a, b);
753
754 b.full = dfixed_const(1000);
755 c.full = dfixed_const(wm->disp_clk);
756 b.full = dfixed_div(c, b);
757 c.full = dfixed_const(wm->bytes_per_pixel);
758 b.full = dfixed_mul(b, c);
759
760 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
761
762 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
763 b.full = dfixed_const(1000);
764 c.full = dfixed_const(lb_fill_bw);
765 b.full = dfixed_div(c, b);
766 a.full = dfixed_div(a, b);
767 line_fill_time = dfixed_trunc(a);
768
769 if (line_fill_time < wm->active_time)
770 return latency;
771 else
772 return latency + (line_fill_time - wm->active_time);
773
774}
775
776static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
777{
778 if (evergreen_average_bandwidth(wm) <=
779 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
780 return true;
781 else
782 return false;
783};
784
785static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
786{
787 if (evergreen_average_bandwidth(wm) <=
788 (evergreen_available_bandwidth(wm) / wm->num_heads))
789 return true;
790 else
791 return false;
792};
793
794static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
795{
796 u32 lb_partitions = wm->lb_size / wm->src_width;
797 u32 line_time = wm->active_time + wm->blank_time;
798 u32 latency_tolerant_lines;
799 u32 latency_hiding;
800 fixed20_12 a;
801
802 a.full = dfixed_const(1);
803 if (wm->vsc.full > a.full)
804 latency_tolerant_lines = 1;
805 else {
806 if (lb_partitions <= (wm->vtaps + 1))
807 latency_tolerant_lines = 1;
808 else
809 latency_tolerant_lines = 2;
810 }
811
812 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
813
814 if (evergreen_latency_watermark(wm) <= latency_hiding)
815 return true;
816 else
817 return false;
818}
819
820static void evergreen_program_watermarks(struct radeon_device *rdev,
821 struct radeon_crtc *radeon_crtc,
822 u32 lb_size, u32 num_heads)
823{
824 struct drm_display_mode *mode = &radeon_crtc->base.mode;
825 struct evergreen_wm_params wm;
826 u32 pixel_period;
827 u32 line_time = 0;
828 u32 latency_watermark_a = 0, latency_watermark_b = 0;
829 u32 priority_a_mark = 0, priority_b_mark = 0;
830 u32 priority_a_cnt = PRIORITY_OFF;
831 u32 priority_b_cnt = PRIORITY_OFF;
832 u32 pipe_offset = radeon_crtc->crtc_id * 16;
833 u32 tmp, arb_control3;
834 fixed20_12 a, b, c;
835
836 if (radeon_crtc->base.enabled && num_heads && mode) {
837 pixel_period = 1000000 / (u32)mode->clock;
838 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
839 priority_a_cnt = 0;
840 priority_b_cnt = 0;
841
842 wm.yclk = rdev->pm.current_mclk * 10;
843 wm.sclk = rdev->pm.current_sclk * 10;
844 wm.disp_clk = mode->clock;
845 wm.src_width = mode->crtc_hdisplay;
846 wm.active_time = mode->crtc_hdisplay * pixel_period;
847 wm.blank_time = line_time - wm.active_time;
848 wm.interlaced = false;
849 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
850 wm.interlaced = true;
851 wm.vsc = radeon_crtc->vsc;
852 wm.vtaps = 1;
853 if (radeon_crtc->rmx_type != RMX_OFF)
854 wm.vtaps = 2;
855 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
856 wm.lb_size = lb_size;
857 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
858 wm.num_heads = num_heads;
859
860 /* set for high clocks */
861 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
862 /* set for low clocks */
863 /* wm.yclk = low clk; wm.sclk = low clk */
864 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
865
866 /* possibly force display priority to high */
867 /* should really do this at mode validation time... */
868 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
869 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
870 !evergreen_check_latency_hiding(&wm) ||
871 (rdev->disp_priority == 2)) {
92bdfd4a 872 DRM_DEBUG_KMS("force priority to high\n");
f9d9c362
AD		 873 priority_a_cnt |= PRIORITY_ALWAYS_ON;
874 priority_b_cnt |= PRIORITY_ALWAYS_ON;
875 }
876
877 a.full = dfixed_const(1000);
878 b.full = dfixed_const(mode->clock);
879 b.full = dfixed_div(b, a);
880 c.full = dfixed_const(latency_watermark_a);
881 c.full = dfixed_mul(c, b);
882 c.full = dfixed_mul(c, radeon_crtc->hsc);
883 c.full = dfixed_div(c, a);
884 a.full = dfixed_const(16);
885 c.full = dfixed_div(c, a);
886 priority_a_mark = dfixed_trunc(c);
887 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
888
889 a.full = dfixed_const(1000);
890 b.full = dfixed_const(mode->clock);
891 b.full = dfixed_div(b, a);
892 c.full = dfixed_const(latency_watermark_b);
893 c.full = dfixed_mul(c, b);
894 c.full = dfixed_mul(c, radeon_crtc->hsc);
895 c.full = dfixed_div(c, a);
896 a.full = dfixed_const(16);
897 c.full = dfixed_div(c, a);
898 priority_b_mark = dfixed_trunc(c);
899 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
900 }
901
902 /* select wm A */
903 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
904 tmp = arb_control3;
905 tmp &= ~LATENCY_WATERMARK_MASK(3);
906 tmp |= LATENCY_WATERMARK_MASK(1);
907 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
908 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
909 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
910 LATENCY_HIGH_WATERMARK(line_time)));
911 /* select wm B */
912 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
913 tmp &= ~LATENCY_WATERMARK_MASK(3);
914 tmp |= LATENCY_WATERMARK_MASK(2);
915 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
916 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
917 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
918 LATENCY_HIGH_WATERMARK(line_time)));
919 /* restore original selection */
920 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
921
922 /* write the priority marks */
923 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
924 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
925
926}
927
0ca2ab52 928void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 929{
f9d9c362
AD		 930 struct drm_display_mode *mode0 = NULL;
931 struct drm_display_mode *mode1 = NULL;
932 u32 num_heads = 0, lb_size;
933 int i;
934
935 radeon_update_display_priority(rdev);
936
937 for (i = 0; i < rdev->num_crtc; i++) {
938 if (rdev->mode_info.crtcs[i]->base.enabled)
939 num_heads++;
940 }
941 for (i = 0; i < rdev->num_crtc; i += 2) {
942 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
943 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
944 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
945 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
946 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
947 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
948 }
bcc1c2a1
AD		 949}
950
b9952a8a 951int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 952{
953 unsigned i;
954 u32 tmp;
955
956 for (i = 0; i < rdev->usec_timeout; i++) {
957 /* read MC_STATUS */
958 tmp = RREG32(SRBM_STATUS) & 0x1F00;
959 if (!tmp)
960 return 0;
961 udelay(1);
962 }
963 return -1;
964}
965
966/*
967 * GART
968 */
0fcdb61e
AD		 969void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
970{
971 unsigned i;
972 u32 tmp;
973
6f2f48a9
AD		 974 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
975
0fcdb61e
AD		 976 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
977 for (i = 0; i < rdev->usec_timeout; i++) {
978 /* read MC_STATUS */
979 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
980 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
981 if (tmp == 2) {
982 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
983 return;
984 }
985 if (tmp) {
986 return;
987 }
988 udelay(1);
989 }
990}
991
bcc1c2a1
AD		 992int evergreen_pcie_gart_enable(struct radeon_device *rdev)
993{
994 u32 tmp;
0fcdb61e 995 int r;
bcc1c2a1 996
c9a1be96 997 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 998 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
999 return -EINVAL;
1000 }
1001 r = radeon_gart_table_vram_pin(rdev);
1002 if (r)
1003 return r;
82568565 1004 radeon_gart_restore(rdev);
bcc1c2a1
AD		 1005 /* Setup L2 cache */
1006 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1007 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1008 EFFECTIVE_L2_QUEUE_SIZE(7));
1009 WREG32(VM_L2_CNTL2, 0);
1010 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1011 /* Setup TLB control */
1012 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1013 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1014 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1015 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 1016 if (rdev->flags & RADEON_IS_IGP) {
1017 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1018 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1019 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1020 } else {
1021 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1022 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1023 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
0b8c30bc
AD		 1024 if ((rdev->family == CHIP_JUNIPER) ||
1025 (rdev->family == CHIP_CYPRESS) ||
1026 (rdev->family == CHIP_HEMLOCK) ||
1027 (rdev->family == CHIP_BARTS))
1028 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
8aeb96f8 1029 }
bcc1c2a1
AD		 1030 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1031 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1032 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1033 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1034 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1035 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1036 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1037 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1038 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1039 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1040 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 1041 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 1042
0fcdb61e 1043 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1044 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1045 (unsigned)(rdev->mc.gtt_size >> 20),
1046 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 1047 rdev->gart.ready = true;
1048 return 0;
1049}
1050
1051void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1052{
1053 u32 tmp;
bcc1c2a1
AD		 1054
1055 /* Disable all tables */
0fcdb61e
AD		 1056 WREG32(VM_CONTEXT0_CNTL, 0);
1057 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1058
1059 /* Setup L2 cache */
1060 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1061 EFFECTIVE_L2_QUEUE_SIZE(7));
1062 WREG32(VM_L2_CNTL2, 0);
1063 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1064 /* Setup TLB control */
1065 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1066 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1067 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1068 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1069 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1070 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1071 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1072 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 1073 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 1074}
1075
1076void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1077{
1078 evergreen_pcie_gart_disable(rdev);
1079 radeon_gart_table_vram_free(rdev);
1080 radeon_gart_fini(rdev);
1081}
1082
1083
1084void evergreen_agp_enable(struct radeon_device *rdev)
1085{
1086 u32 tmp;
bcc1c2a1
AD		 1087
1088 /* Setup L2 cache */
1089 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1090 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1091 EFFECTIVE_L2_QUEUE_SIZE(7));
1092 WREG32(VM_L2_CNTL2, 0);
1093 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1094 /* Setup TLB control */
1095 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1096 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1097 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1098 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1099 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1100 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1101 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1102 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1103 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1104 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1105 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 1106 WREG32(VM_CONTEXT0_CNTL, 0);
1107 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1108}
1109
b9952a8a 1110void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1111{
1112 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1113 save->vga_control[1] = RREG32(D2VGA_CONTROL);
bcc1c2a1
AD		 1114 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1115 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1116 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1117 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 1118 if (rdev->num_crtc >= 4) {
1119 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1120 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
18007401
AD		 1121 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1122 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
b7eff394
AD		 1123 }
1124 if (rdev->num_crtc >= 6) {
1125 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1126 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
18007401
AD		 1127 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1128 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1129 }
bcc1c2a1
AD		 1130
1131 /* Stop all video */
1132 WREG32(VGA_RENDER_CONTROL, 0);
1133 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1134 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
b7eff394 1135 if (rdev->num_crtc >= 4) {
18007401
AD		 1136 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1137 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
b7eff394
AD		 1138 }
1139 if (rdev->num_crtc >= 6) {
18007401
AD		 1140 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1141 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1142 }
bcc1c2a1
AD		 1143 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1144 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1145 if (rdev->num_crtc >= 4) {
18007401
AD		 1146 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1147 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1148 }
1149 if (rdev->num_crtc >= 6) {
18007401
AD		 1150 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1151 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1152 }
bcc1c2a1
AD		 1153 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1154 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1155 if (rdev->num_crtc >= 4) {
18007401
AD		 1156 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1157 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1158 }
1159 if (rdev->num_crtc >= 6) {
18007401
AD		 1160 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1161 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1162 }
bcc1c2a1
AD		 1163
1164 WREG32(D1VGA_CONTROL, 0);
1165 WREG32(D2VGA_CONTROL, 0);
b7eff394
AD		 1166 if (rdev->num_crtc >= 4) {
1167 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1168 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1169 }
1170 if (rdev->num_crtc >= 6) {
1171 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1172 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1173 }
bcc1c2a1
AD		 1174}
1175
b9952a8a 1176void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1177{
1178 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1179 upper_32_bits(rdev->mc.vram_start));
1180 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1181 upper_32_bits(rdev->mc.vram_start));
1182 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1183 (u32)rdev->mc.vram_start);
1184 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1185 (u32)rdev->mc.vram_start);
1186
1187 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1188 upper_32_bits(rdev->mc.vram_start));
1189 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1190 upper_32_bits(rdev->mc.vram_start));
1191 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1192 (u32)rdev->mc.vram_start);
1193 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1194 (u32)rdev->mc.vram_start);
1195
b7eff394 1196 if (rdev->num_crtc >= 4) {
18007401
AD		 1197 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1198 upper_32_bits(rdev->mc.vram_start));
1199 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1200 upper_32_bits(rdev->mc.vram_start));
1201 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1202 (u32)rdev->mc.vram_start);
1203 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1204 (u32)rdev->mc.vram_start);
1205
1206 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1207 upper_32_bits(rdev->mc.vram_start));
1208 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1209 upper_32_bits(rdev->mc.vram_start));
1210 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1211 (u32)rdev->mc.vram_start);
1212 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1213 (u32)rdev->mc.vram_start);
b7eff394
AD		 1214 }
1215 if (rdev->num_crtc >= 6) {
18007401
AD		 1216 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1217 upper_32_bits(rdev->mc.vram_start));
1218 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1219 upper_32_bits(rdev->mc.vram_start));
1220 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1221 (u32)rdev->mc.vram_start);
1222 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1223 (u32)rdev->mc.vram_start);
1224
1225 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1226 upper_32_bits(rdev->mc.vram_start));
1227 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1228 upper_32_bits(rdev->mc.vram_start));
1229 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1230 (u32)rdev->mc.vram_start);
1231 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1232 (u32)rdev->mc.vram_start);
1233 }
bcc1c2a1
AD		 1234
1235 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1236 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1237 /* Unlock host access */
1238 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1239 mdelay(1);
1240 /* Restore video state */
1241 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1242 WREG32(D2VGA_CONTROL, save->vga_control[1]);
b7eff394
AD		 1243 if (rdev->num_crtc >= 4) {
1244 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1245 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1246 }
1247 if (rdev->num_crtc >= 6) {
1248 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1249 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1250 }
bcc1c2a1
AD		 1251 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1252 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
b7eff394 1253 if (rdev->num_crtc >= 4) {
18007401
AD		 1254 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1255 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
b7eff394
AD		 1256 }
1257 if (rdev->num_crtc >= 6) {
18007401
AD		 1258 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1259 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1260 }
bcc1c2a1
AD		 1261 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1262 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
b7eff394 1263 if (rdev->num_crtc >= 4) {
18007401
AD		 1264 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1265 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
b7eff394
AD		 1266 }
1267 if (rdev->num_crtc >= 6) {
18007401
AD		 1268 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1269 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1270 }
bcc1c2a1
AD		 1271 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1272 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1273 if (rdev->num_crtc >= 4) {
18007401
AD		 1274 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1275 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1276 }
1277 if (rdev->num_crtc >= 6) {
18007401
AD		 1278 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1279 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1280 }
bcc1c2a1
AD		 1281 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1282}
1283
755d819e 1284void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1285{
1286 struct evergreen_mc_save save;
1287 u32 tmp;
1288 int i, j;
1289
1290 /* Initialize HDP */
1291 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1292 WREG32((0x2c14 + j), 0x00000000);
1293 WREG32((0x2c18 + j), 0x00000000);
1294 WREG32((0x2c1c + j), 0x00000000);
1295 WREG32((0x2c20 + j), 0x00000000);
1296 WREG32((0x2c24 + j), 0x00000000);
1297 }
1298 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1299
1300 evergreen_mc_stop(rdev, &save);
1301 if (evergreen_mc_wait_for_idle(rdev)) {
1302 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1303 }
1304 /* Lockout access through VGA aperture*/
1305 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1306 /* Update configuration */
1307 if (rdev->flags & RADEON_IS_AGP) {
1308 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1309 /* VRAM before AGP */
1310 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1311 rdev->mc.vram_start >> 12);
1312 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1313 rdev->mc.gtt_end >> 12);
1314 } else {
1315 /* VRAM after AGP */
1316 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1317 rdev->mc.gtt_start >> 12);
1318 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1319 rdev->mc.vram_end >> 12);
1320 }
1321 } else {
1322 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1323 rdev->mc.vram_start >> 12);
1324 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1325 rdev->mc.vram_end >> 12);
1326 }
3b9832f6 1327 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
05b3ef69
AD		 1328 /* llano/ontario only */
1329 if ((rdev->family == CHIP_PALM) ||
1330 (rdev->family == CHIP_SUMO) ||
1331 (rdev->family == CHIP_SUMO2)) {
b4183e30
AD		 1332 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1333 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1334 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1335 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1336 }
bcc1c2a1
AD		 1337 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1338 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1339 WREG32(MC_VM_FB_LOCATION, tmp);
1340 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1341 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1342 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1343 if (rdev->flags & RADEON_IS_AGP) {
1344 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1345 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1346 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1347 } else {
1348 WREG32(MC_VM_AGP_BASE, 0);
1349 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1350 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1351 }
1352 if (evergreen_mc_wait_for_idle(rdev)) {
1353 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1354 }
1355 evergreen_mc_resume(rdev, &save);
1356 /* we need to own VRAM, so turn off the VGA renderer here
1357 * to stop it overwriting our objects */
1358 rv515_vga_render_disable(rdev);
1359}
1360
bcc1c2a1
AD		 1361/*
1362 * CP.
1363 */
12920591
AD		 1364void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1365{
876dc9f3 1366 struct radeon_ring *ring = &rdev->ring[ib->ring];
89d35807 1367 u32 next_rptr;
7b1f2485 1368
12920591 1369 /* set to DX10/11 mode */
e32eb50d
CK		 1370 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1371 radeon_ring_write(ring, 1);
45df6803
CK		 1372
1373 if (ring->rptr_save_reg) {
89d35807 1374 next_rptr = ring->wptr + 3 + 4;
45df6803
CK		 1375 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1376 radeon_ring_write(ring, ((ring->rptr_save_reg -
1377 PACKET3_SET_CONFIG_REG_START) >> 2));
1378 radeon_ring_write(ring, next_rptr);
89d35807
AD		 1379 } else if (rdev->wb.enabled) {
1380 next_rptr = ring->wptr + 5 + 4;
1381 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1382 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1383 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1384 radeon_ring_write(ring, next_rptr);
1385 radeon_ring_write(ring, 0);
45df6803
CK		 1386 }
1387
e32eb50d
CK		 1388 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1389 radeon_ring_write(ring,
0f234f5f
AD		 1390#ifdef __BIG_ENDIAN
1391 (2 << 0) |
1392#endif
1393 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 1394 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1395 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 1396}
1397
bcc1c2a1
AD		 1398
1399static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1400{
fe251e2f
AD		 1401 const __be32 *fw_data;
1402 int i;
1403
1404 if (!rdev->me_fw || !rdev->pfp_fw)
1405 return -EINVAL;
bcc1c2a1 1406
fe251e2f 1407 r700_cp_stop(rdev);
0f234f5f
AD		 1408 WREG32(CP_RB_CNTL,
1409#ifdef __BIG_ENDIAN
1410 BUF_SWAP_32BIT |
1411#endif
1412 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1413
1414 fw_data = (const __be32 *)rdev->pfp_fw->data;
1415 WREG32(CP_PFP_UCODE_ADDR, 0);
1416 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1417 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1418 WREG32(CP_PFP_UCODE_ADDR, 0);
1419
1420 fw_data = (const __be32 *)rdev->me_fw->data;
1421 WREG32(CP_ME_RAM_WADDR, 0);
1422 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1423 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1424
1425 WREG32(CP_PFP_UCODE_ADDR, 0);
1426 WREG32(CP_ME_RAM_WADDR, 0);
1427 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1428 return 0;
1429}
1430
7e7b41d2
AD		 1431static int evergreen_cp_start(struct radeon_device *rdev)
1432{
e32eb50d 1433 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 1434 int r, i;
7e7b41d2
AD		 1435 uint32_t cp_me;
1436
e32eb50d 1437 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 1438 if (r) {
1439 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1440 return r;
1441 }
e32eb50d
CK		 1442 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1443 radeon_ring_write(ring, 0x1);
1444 radeon_ring_write(ring, 0x0);
1445 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1446 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1447 radeon_ring_write(ring, 0);
1448 radeon_ring_write(ring, 0);
1449 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1450
1451 cp_me = 0xff;
1452 WREG32(CP_ME_CNTL, cp_me);
1453
e32eb50d 1454 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 1455 if (r) {
1456 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1457 return r;
1458 }
2281a378
AD		 1459
1460 /* setup clear context state */
e32eb50d
CK		 1461 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1462 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 1463
1464 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 1465 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 1466
e32eb50d
CK		 1467 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1468 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 1469
1470 /* set clear context state */
e32eb50d
CK		 1471 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1472 radeon_ring_write(ring, 0);
2281a378
AD		 1473
1474 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1475 radeon_ring_write(ring, 0xc0026f00);
1476 radeon_ring_write(ring, 0x00000000);
1477 radeon_ring_write(ring, 0x00000000);
1478 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 1479
1480 /* Clear consts */
e32eb50d
CK		 1481 radeon_ring_write(ring, 0xc0036f00);
1482 radeon_ring_write(ring, 0x00000bc4);
1483 radeon_ring_write(ring, 0xffffffff);
1484 radeon_ring_write(ring, 0xffffffff);
1485 radeon_ring_write(ring, 0xffffffff);
2281a378 1486
e32eb50d
CK		 1487 radeon_ring_write(ring, 0xc0026900);
1488 radeon_ring_write(ring, 0x00000316);
1489 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1490 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 1491
e32eb50d 1492 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1493
1494 return 0;
1495}
1496
fe251e2f
AD		 1497int evergreen_cp_resume(struct radeon_device *rdev)
1498{
e32eb50d 1499 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 1500 u32 tmp;
1501 u32 rb_bufsz;
1502 int r;
1503
1504 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1505 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1506 SOFT_RESET_PA |
1507 SOFT_RESET_SH |
1508 SOFT_RESET_VGT |
a49a50da 1509 SOFT_RESET_SPI |
fe251e2f
AD		 1510 SOFT_RESET_SX));
1511 RREG32(GRBM_SOFT_RESET);
1512 mdelay(15);
1513 WREG32(GRBM_SOFT_RESET, 0);
1514 RREG32(GRBM_SOFT_RESET);
1515
1516 /* Set ring buffer size */
e32eb50d 1517 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 1518 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1519#ifdef __BIG_ENDIAN
1520 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1521#endif
fe251e2f 1522 WREG32(CP_RB_CNTL, tmp);
15d3332f 1523 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1524 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 1525
1526 /* Set the write pointer delay */
1527 WREG32(CP_RB_WPTR_DELAY, 0);
1528
1529 /* Initialize the ring buffer's read and write pointers */
1530 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1531 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1532 ring->wptr = 0;
1533 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1534
1535 /* set the wb address wether it's enabled or not */
0f234f5f 1536 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 1537 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1538 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1539 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1540
1541 if (rdev->wb.enabled)
1542 WREG32(SCRATCH_UMSK, 0xff);
1543 else {
1544 tmp |= RB_NO_UPDATE;
1545 WREG32(SCRATCH_UMSK, 0);
1546 }
1547
fe251e2f
AD		 1548 mdelay(1);
1549 WREG32(CP_RB_CNTL, tmp);
1550
e32eb50d 1551 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 1552 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1553
e32eb50d 1554 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 1555
7e7b41d2 1556 evergreen_cp_start(rdev);
e32eb50d 1557 ring->ready = true;
f712812e 1558 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
fe251e2f 1559 if (r) {
e32eb50d 1560 ring->ready = false;
fe251e2f
AD		 1561 return r;
1562 }
1563 return 0;
1564}
bcc1c2a1
AD		 1565
1566/*
1567 * Core functions
1568 */
bcc1c2a1
AD		 1569static void evergreen_gpu_init(struct radeon_device *rdev)
1570{
416a2bd2 1571 u32 gb_addr_config;
32fcdbf4 1572 u32 mc_shared_chmap, mc_arb_ramcfg;
32fcdbf4
AD		 1573 u32 sx_debug_1;
1574 u32 smx_dc_ctl0;
1575 u32 sq_config;
1576 u32 sq_lds_resource_mgmt;
1577 u32 sq_gpr_resource_mgmt_1;
1578 u32 sq_gpr_resource_mgmt_2;
1579 u32 sq_gpr_resource_mgmt_3;
1580 u32 sq_thread_resource_mgmt;
1581 u32 sq_thread_resource_mgmt_2;
1582 u32 sq_stack_resource_mgmt_1;
1583 u32 sq_stack_resource_mgmt_2;
1584 u32 sq_stack_resource_mgmt_3;
1585 u32 vgt_cache_invalidation;
f25a5c63 1586 u32 hdp_host_path_cntl, tmp;
416a2bd2 1587 u32 disabled_rb_mask;
32fcdbf4
AD		 1588 int i, j, num_shader_engines, ps_thread_count;
1589
1590 switch (rdev->family) {
1591 case CHIP_CYPRESS:
1592 case CHIP_HEMLOCK:
1593 rdev->config.evergreen.num_ses = 2;
1594 rdev->config.evergreen.max_pipes = 4;
1595 rdev->config.evergreen.max_tile_pipes = 8;
1596 rdev->config.evergreen.max_simds = 10;
1597 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1598 rdev->config.evergreen.max_gprs = 256;
1599 rdev->config.evergreen.max_threads = 248;
1600 rdev->config.evergreen.max_gs_threads = 32;
1601 rdev->config.evergreen.max_stack_entries = 512;
1602 rdev->config.evergreen.sx_num_of_sets = 4;
1603 rdev->config.evergreen.sx_max_export_size = 256;
1604 rdev->config.evergreen.sx_max_export_pos_size = 64;
1605 rdev->config.evergreen.sx_max_export_smx_size = 192;
1606 rdev->config.evergreen.max_hw_contexts = 8;
1607 rdev->config.evergreen.sq_num_cf_insts = 2;
1608
1609 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1610 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1611 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1612 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1613 break;
1614 case CHIP_JUNIPER:
1615 rdev->config.evergreen.num_ses = 1;
1616 rdev->config.evergreen.max_pipes = 4;
1617 rdev->config.evergreen.max_tile_pipes = 4;
1618 rdev->config.evergreen.max_simds = 10;
1619 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1620 rdev->config.evergreen.max_gprs = 256;
1621 rdev->config.evergreen.max_threads = 248;
1622 rdev->config.evergreen.max_gs_threads = 32;
1623 rdev->config.evergreen.max_stack_entries = 512;
1624 rdev->config.evergreen.sx_num_of_sets = 4;
1625 rdev->config.evergreen.sx_max_export_size = 256;
1626 rdev->config.evergreen.sx_max_export_pos_size = 64;
1627 rdev->config.evergreen.sx_max_export_smx_size = 192;
1628 rdev->config.evergreen.max_hw_contexts = 8;
1629 rdev->config.evergreen.sq_num_cf_insts = 2;
1630
1631 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1632 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1633 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1634 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1635 break;
1636 case CHIP_REDWOOD:
1637 rdev->config.evergreen.num_ses = 1;
1638 rdev->config.evergreen.max_pipes = 4;
1639 rdev->config.evergreen.max_tile_pipes = 4;
1640 rdev->config.evergreen.max_simds = 5;
1641 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1642 rdev->config.evergreen.max_gprs = 256;
1643 rdev->config.evergreen.max_threads = 248;
1644 rdev->config.evergreen.max_gs_threads = 32;
1645 rdev->config.evergreen.max_stack_entries = 256;
1646 rdev->config.evergreen.sx_num_of_sets = 4;
1647 rdev->config.evergreen.sx_max_export_size = 256;
1648 rdev->config.evergreen.sx_max_export_pos_size = 64;
1649 rdev->config.evergreen.sx_max_export_smx_size = 192;
1650 rdev->config.evergreen.max_hw_contexts = 8;
1651 rdev->config.evergreen.sq_num_cf_insts = 2;
1652
1653 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1654 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1655 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1656 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1657 break;
1658 case CHIP_CEDAR:
1659 default:
1660 rdev->config.evergreen.num_ses = 1;
1661 rdev->config.evergreen.max_pipes = 2;
1662 rdev->config.evergreen.max_tile_pipes = 2;
1663 rdev->config.evergreen.max_simds = 2;
1664 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1665 rdev->config.evergreen.max_gprs = 256;
1666 rdev->config.evergreen.max_threads = 192;
1667 rdev->config.evergreen.max_gs_threads = 16;
1668 rdev->config.evergreen.max_stack_entries = 256;
1669 rdev->config.evergreen.sx_num_of_sets = 4;
1670 rdev->config.evergreen.sx_max_export_size = 128;
1671 rdev->config.evergreen.sx_max_export_pos_size = 32;
1672 rdev->config.evergreen.sx_max_export_smx_size = 96;
1673 rdev->config.evergreen.max_hw_contexts = 4;
1674 rdev->config.evergreen.sq_num_cf_insts = 1;
1675
d5e455e4
AD		 1676 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1677 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1678 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1679 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5e455e4
AD		 1680 break;
1681 case CHIP_PALM:
1682 rdev->config.evergreen.num_ses = 1;
1683 rdev->config.evergreen.max_pipes = 2;
1684 rdev->config.evergreen.max_tile_pipes = 2;
1685 rdev->config.evergreen.max_simds = 2;
1686 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1687 rdev->config.evergreen.max_gprs = 256;
1688 rdev->config.evergreen.max_threads = 192;
1689 rdev->config.evergreen.max_gs_threads = 16;
1690 rdev->config.evergreen.max_stack_entries = 256;
1691 rdev->config.evergreen.sx_num_of_sets = 4;
1692 rdev->config.evergreen.sx_max_export_size = 128;
1693 rdev->config.evergreen.sx_max_export_pos_size = 32;
1694 rdev->config.evergreen.sx_max_export_smx_size = 96;
1695 rdev->config.evergreen.max_hw_contexts = 4;
1696 rdev->config.evergreen.sq_num_cf_insts = 1;
1697
d5c5a72f
AD		 1698 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1699 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1700 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1701 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 1702 break;
1703 case CHIP_SUMO:
1704 rdev->config.evergreen.num_ses = 1;
1705 rdev->config.evergreen.max_pipes = 4;
1706 rdev->config.evergreen.max_tile_pipes = 2;
1707 if (rdev->pdev->device == 0x9648)
1708 rdev->config.evergreen.max_simds = 3;
1709 else if ((rdev->pdev->device == 0x9647) ||
1710 (rdev->pdev->device == 0x964a))
1711 rdev->config.evergreen.max_simds = 4;
1712 else
1713 rdev->config.evergreen.max_simds = 5;
1714 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1715 rdev->config.evergreen.max_gprs = 256;
1716 rdev->config.evergreen.max_threads = 248;
1717 rdev->config.evergreen.max_gs_threads = 32;
1718 rdev->config.evergreen.max_stack_entries = 256;
1719 rdev->config.evergreen.sx_num_of_sets = 4;
1720 rdev->config.evergreen.sx_max_export_size = 256;
1721 rdev->config.evergreen.sx_max_export_pos_size = 64;
1722 rdev->config.evergreen.sx_max_export_smx_size = 192;
1723 rdev->config.evergreen.max_hw_contexts = 8;
1724 rdev->config.evergreen.sq_num_cf_insts = 2;
1725
1726 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1727 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1728 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1729 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
d5c5a72f
AD		 1730 break;
1731 case CHIP_SUMO2:
1732 rdev->config.evergreen.num_ses = 1;
1733 rdev->config.evergreen.max_pipes = 4;
1734 rdev->config.evergreen.max_tile_pipes = 4;
1735 rdev->config.evergreen.max_simds = 2;
1736 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1737 rdev->config.evergreen.max_gprs = 256;
1738 rdev->config.evergreen.max_threads = 248;
1739 rdev->config.evergreen.max_gs_threads = 32;
1740 rdev->config.evergreen.max_stack_entries = 512;
1741 rdev->config.evergreen.sx_num_of_sets = 4;
1742 rdev->config.evergreen.sx_max_export_size = 256;
1743 rdev->config.evergreen.sx_max_export_pos_size = 64;
1744 rdev->config.evergreen.sx_max_export_smx_size = 192;
1745 rdev->config.evergreen.max_hw_contexts = 8;
1746 rdev->config.evergreen.sq_num_cf_insts = 2;
1747
adb68fa2
AD		 1748 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1749 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1750 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1751 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1752 break;
1753 case CHIP_BARTS:
1754 rdev->config.evergreen.num_ses = 2;
1755 rdev->config.evergreen.max_pipes = 4;
1756 rdev->config.evergreen.max_tile_pipes = 8;
1757 rdev->config.evergreen.max_simds = 7;
1758 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1759 rdev->config.evergreen.max_gprs = 256;
1760 rdev->config.evergreen.max_threads = 248;
1761 rdev->config.evergreen.max_gs_threads = 32;
1762 rdev->config.evergreen.max_stack_entries = 512;
1763 rdev->config.evergreen.sx_num_of_sets = 4;
1764 rdev->config.evergreen.sx_max_export_size = 256;
1765 rdev->config.evergreen.sx_max_export_pos_size = 64;
1766 rdev->config.evergreen.sx_max_export_smx_size = 192;
1767 rdev->config.evergreen.max_hw_contexts = 8;
1768 rdev->config.evergreen.sq_num_cf_insts = 2;
1769
1770 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1771 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1772 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1773 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1774 break;
1775 case CHIP_TURKS:
1776 rdev->config.evergreen.num_ses = 1;
1777 rdev->config.evergreen.max_pipes = 4;
1778 rdev->config.evergreen.max_tile_pipes = 4;
1779 rdev->config.evergreen.max_simds = 6;
1780 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1781 rdev->config.evergreen.max_gprs = 256;
1782 rdev->config.evergreen.max_threads = 248;
1783 rdev->config.evergreen.max_gs_threads = 32;
1784 rdev->config.evergreen.max_stack_entries = 256;
1785 rdev->config.evergreen.sx_num_of_sets = 4;
1786 rdev->config.evergreen.sx_max_export_size = 256;
1787 rdev->config.evergreen.sx_max_export_pos_size = 64;
1788 rdev->config.evergreen.sx_max_export_smx_size = 192;
1789 rdev->config.evergreen.max_hw_contexts = 8;
1790 rdev->config.evergreen.sq_num_cf_insts = 2;
1791
1792 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1793 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1794 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1795 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
adb68fa2
AD		 1796 break;
1797 case CHIP_CAICOS:
1798 rdev->config.evergreen.num_ses = 1;
1799 rdev->config.evergreen.max_pipes = 4;
1800 rdev->config.evergreen.max_tile_pipes = 2;
1801 rdev->config.evergreen.max_simds = 2;
1802 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1803 rdev->config.evergreen.max_gprs = 256;
1804 rdev->config.evergreen.max_threads = 192;
1805 rdev->config.evergreen.max_gs_threads = 16;
1806 rdev->config.evergreen.max_stack_entries = 256;
1807 rdev->config.evergreen.sx_num_of_sets = 4;
1808 rdev->config.evergreen.sx_max_export_size = 128;
1809 rdev->config.evergreen.sx_max_export_pos_size = 32;
1810 rdev->config.evergreen.sx_max_export_smx_size = 96;
1811 rdev->config.evergreen.max_hw_contexts = 4;
1812 rdev->config.evergreen.sq_num_cf_insts = 1;
1813
32fcdbf4
AD		 1814 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1815 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1816 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
416a2bd2 1817 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
32fcdbf4
AD		 1818 break;
1819 }
1820
1821 /* Initialize HDP */
1822 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1823 WREG32((0x2c14 + j), 0x00000000);
1824 WREG32((0x2c18 + j), 0x00000000);
1825 WREG32((0x2c1c + j), 0x00000000);
1826 WREG32((0x2c20 + j), 0x00000000);
1827 WREG32((0x2c24 + j), 0x00000000);
1828 }
1829
1830 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1831
d054ac16
AD		 1832 evergreen_fix_pci_max_read_req_size(rdev);
1833
32fcdbf4 1834 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
05b3ef69
AD		 1835 if ((rdev->family == CHIP_PALM) ||
1836 (rdev->family == CHIP_SUMO) ||
1837 (rdev->family == CHIP_SUMO2))
d9282fca
AD		 1838 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1839 else
1840 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4 1841
1aa52bd3
AD		 1842 /* setup tiling info dword. gb_addr_config is not adequate since it does
1843 * not have bank info, so create a custom tiling dword.
1844 * bits 3:0 num_pipes
1845 * bits 7:4 num_banks
1846 * bits 11:8 group_size
1847 * bits 15:12 row_size
1848 */
1849 rdev->config.evergreen.tile_config = 0;
1850 switch (rdev->config.evergreen.max_tile_pipes) {
1851 case 1:
1852 default:
1853 rdev->config.evergreen.tile_config |= (0 << 0);
1854 break;
1855 case 2:
1856 rdev->config.evergreen.tile_config |= (1 << 0);
1857 break;
1858 case 4:
1859 rdev->config.evergreen.tile_config |= (2 << 0);
1860 break;
1861 case 8:
1862 rdev->config.evergreen.tile_config |= (3 << 0);
1863 break;
1864 }
d698a34d 1865 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 1866 if (rdev->flags & RADEON_IS_IGP)
d698a34d 1867 rdev->config.evergreen.tile_config |= 1 << 4;
29d65406
AD		 1868 else {
1869 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1870 rdev->config.evergreen.tile_config |= 1 << 4;
1871 else
1872 rdev->config.evergreen.tile_config |= 0 << 4;
1873 }
416a2bd2 1874 rdev->config.evergreen.tile_config |= 0 << 8;
1aa52bd3
AD		 1875 rdev->config.evergreen.tile_config |=
1876 ((gb_addr_config & 0x30000000) >> 28) << 12;
1877
416a2bd2 1878 num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
32fcdbf4 1879
416a2bd2
AD		 1880 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
1881 u32 efuse_straps_4;
1882 u32 efuse_straps_3;
32fcdbf4 1883
416a2bd2
AD		 1884 WREG32(RCU_IND_INDEX, 0x204);
1885 efuse_straps_4 = RREG32(RCU_IND_DATA);
1886 WREG32(RCU_IND_INDEX, 0x203);
1887 efuse_straps_3 = RREG32(RCU_IND_DATA);
1888 tmp = (((efuse_straps_4 & 0xf) << 4) |
1889 ((efuse_straps_3 & 0xf0000000) >> 28));
1890 } else {
1891 tmp = 0;
1892 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
1893 u32 rb_disable_bitmap;
1894
1895 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1896 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1897 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1898 tmp <<= 4;
1899 tmp |= rb_disable_bitmap;
32fcdbf4 1900 }
416a2bd2
AD		 1901 }
1902 /* enabled rb are just the one not disabled :) */
1903 disabled_rb_mask = tmp;
32fcdbf4 1904
416a2bd2
AD		 1905 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1906 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
32fcdbf4 1907
416a2bd2
AD		 1908 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1909 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1910 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
32fcdbf4 1911
416a2bd2
AD		 1912 tmp = gb_addr_config & NUM_PIPES_MASK;
1913 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
1914 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
1915 WREG32(GB_BACKEND_MAP, tmp);
32fcdbf4
AD		 1916
1917 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1918 WREG32(CGTS_TCC_DISABLE, 0);
1919 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1920 WREG32(CGTS_USER_TCC_DISABLE, 0);
1921
1922 /* set HW defaults for 3D engine */
1923 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1924 ROQ_IB2_START(0x2b)));
1925
1926 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1927
1928 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1929 SYNC_GRADIENT |
1930 SYNC_WALKER |
1931 SYNC_ALIGNER));
1932
1933 sx_debug_1 = RREG32(SX_DEBUG_1);
1934 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1935 WREG32(SX_DEBUG_1, sx_debug_1);
1936
1937
1938 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1939 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1940 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1941 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1942
b866d133
AD		 1943 if (rdev->family <= CHIP_SUMO2)
1944 WREG32(SMX_SAR_CTL0, 0x00010000);
1945
32fcdbf4
AD		 1946 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1947 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1948 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1949
1950 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1951 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1952 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1953
1954 WREG32(VGT_NUM_INSTANCES, 1);
1955 WREG32(SPI_CONFIG_CNTL, 0);
1956 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1957 WREG32(CP_PERFMON_CNTL, 0);
1958
1959 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1960 FETCH_FIFO_HIWATER(0x4) |
1961 DONE_FIFO_HIWATER(0xe0) |
1962 ALU_UPDATE_FIFO_HIWATER(0x8)));
1963
1964 sq_config = RREG32(SQ_CONFIG);
1965 sq_config &= ~(PS_PRIO(3) |
1966 VS_PRIO(3) |
1967 GS_PRIO(3) |
1968 ES_PRIO(3));
1969 sq_config |= (VC_ENABLE |
1970 EXPORT_SRC_C |
1971 PS_PRIO(0) |
1972 VS_PRIO(1) |
1973 GS_PRIO(2) |
1974 ES_PRIO(3));
1975
d5e455e4
AD		 1976 switch (rdev->family) {
1977 case CHIP_CEDAR:
1978 case CHIP_PALM:
d5c5a72f
AD		 1979 case CHIP_SUMO:
1980 case CHIP_SUMO2:
adb68fa2 1981 case CHIP_CAICOS:
32fcdbf4
AD		 1982 /* no vertex cache */
1983 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 1984 break;
1985 default:
1986 break;
1987 }
32fcdbf4
AD		 1988
1989 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1990
1991 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1992 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1993 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1994 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1995 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1996 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1997 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1998
d5e455e4
AD		 1999 switch (rdev->family) {
2000 case CHIP_CEDAR:
2001 case CHIP_PALM:
d5c5a72f
AD		 2002 case CHIP_SUMO:
2003 case CHIP_SUMO2:
32fcdbf4 2004 ps_thread_count = 96;
d5e455e4
AD		 2005 break;
2006 default:
32fcdbf4 2007 ps_thread_count = 128;
d5e455e4
AD		 2008 break;
2009 }
32fcdbf4
AD		 2010
2011 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2012 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2013 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2014 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2015 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2016 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2017
2018 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2019 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2020 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2021 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2022 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2023 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2024
2025 WREG32(SQ_CONFIG, sq_config);
2026 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2027 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2028 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2029 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2030 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2031 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2032 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2033 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2034 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2035 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2036
2037 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2038 FORCE_EOV_MAX_REZ_CNT(255)));
2039
d5e455e4
AD		 2040 switch (rdev->family) {
2041 case CHIP_CEDAR:
2042 case CHIP_PALM:
d5c5a72f
AD		 2043 case CHIP_SUMO:
2044 case CHIP_SUMO2:
adb68fa2 2045 case CHIP_CAICOS:
32fcdbf4 2046 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2047 break;
2048 default:
32fcdbf4 2049 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2050 break;
2051 }
32fcdbf4
AD		 2052 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2053 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2054
2055 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2056 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2057 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2058
60a4a3e0
AD		 2059 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2060 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2061
32fcdbf4
AD		 2062 WREG32(CB_PERF_CTR0_SEL_0, 0);
2063 WREG32(CB_PERF_CTR0_SEL_1, 0);
2064 WREG32(CB_PERF_CTR1_SEL_0, 0);
2065 WREG32(CB_PERF_CTR1_SEL_1, 0);
2066 WREG32(CB_PERF_CTR2_SEL_0, 0);
2067 WREG32(CB_PERF_CTR2_SEL_1, 0);
2068 WREG32(CB_PERF_CTR3_SEL_0, 0);
2069 WREG32(CB_PERF_CTR3_SEL_1, 0);
2070
60a4a3e0
AD		 2071 /* clear render buffer base addresses */
2072 WREG32(CB_COLOR0_BASE, 0);
2073 WREG32(CB_COLOR1_BASE, 0);
2074 WREG32(CB_COLOR2_BASE, 0);
2075 WREG32(CB_COLOR3_BASE, 0);
2076 WREG32(CB_COLOR4_BASE, 0);
2077 WREG32(CB_COLOR5_BASE, 0);
2078 WREG32(CB_COLOR6_BASE, 0);
2079 WREG32(CB_COLOR7_BASE, 0);
2080 WREG32(CB_COLOR8_BASE, 0);
2081 WREG32(CB_COLOR9_BASE, 0);
2082 WREG32(CB_COLOR10_BASE, 0);
2083 WREG32(CB_COLOR11_BASE, 0);
2084
2085 /* set the shader const cache sizes to 0 */
2086 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2087 WREG32(i, 0);
2088 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2089 WREG32(i, 0);
2090
f25a5c63
AD		 2091 tmp = RREG32(HDP_MISC_CNTL);
2092 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2093 WREG32(HDP_MISC_CNTL, tmp);
2094
32fcdbf4
AD		 2095 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2096 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2097
2098 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2099
2100 udelay(50);
2101
bcc1c2a1
AD		 2102}
2103
2104int evergreen_mc_init(struct radeon_device *rdev)
2105{
bcc1c2a1
AD		 2106 u32 tmp;
2107 int chansize, numchan;
bcc1c2a1
AD		 2108
2109 /* Get VRAM informations */
2110 rdev->mc.vram_is_ddr = true;
05b3ef69
AD		 2111 if ((rdev->family == CHIP_PALM) ||
2112 (rdev->family == CHIP_SUMO) ||
2113 (rdev->family == CHIP_SUMO2))
8208441b
AD		 2114 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2115 else
2116 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 2117 if (tmp & CHANSIZE_OVERRIDE) {
2118 chansize = 16;
2119 } else if (tmp & CHANSIZE_MASK) {
2120 chansize = 64;
2121 } else {
2122 chansize = 32;
2123 }
2124 tmp = RREG32(MC_SHARED_CHMAP);
2125 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2126 case 0:
2127 default:
2128 numchan = 1;
2129 break;
2130 case 1:
2131 numchan = 2;
2132 break;
2133 case 2:
2134 numchan = 4;
2135 break;
2136 case 3:
2137 numchan = 8;
2138 break;
2139 }
2140 rdev->mc.vram_width = numchan * chansize;
2141 /* Could aper size report 0 ? */
01d73a69
JC		 2142 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2143 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2144 /* Setup GPU memory space */
05b3ef69
AD		 2145 if ((rdev->family == CHIP_PALM) ||
2146 (rdev->family == CHIP_SUMO) ||
2147 (rdev->family == CHIP_SUMO2)) {
6eb18f8b
AD		 2148 /* size in bytes on fusion */
2149 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2150 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2151 } else {
05b3ef69 2152 /* size in MB on evergreen/cayman/tn */
6eb18f8b
AD		 2153 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2154 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2155 }
51e5fcd3 2156 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2157 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2158 radeon_update_bandwidth_info(rdev);
2159
bcc1c2a1
AD		 2160 return 0;
2161}
d594e46a 2162
e32eb50d 2163bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 2164{
17db7042
AD		 2165 u32 srbm_status;
2166 u32 grbm_status;
2167 u32 grbm_status_se0, grbm_status_se1;
17db7042
AD		 2168
2169 srbm_status = RREG32(SRBM_STATUS);
2170 grbm_status = RREG32(GRBM_STATUS);
2171 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2172 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2173 if (!(grbm_status & GUI_ACTIVE)) {
069211e5 2174 radeon_ring_lockup_update(ring);
17db7042
AD		 2175 return false;
2176 }
2177 /* force CP activities */
7b9ef16b 2178 radeon_ring_force_activity(rdev, ring);
069211e5 2179 return radeon_ring_test_lockup(rdev, ring);
225758d8
JG		 2180}
2181
747943ea 2182static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 2183{
747943ea 2184 struct evergreen_mc_save save;
747943ea
AD		 2185 u32 grbm_reset = 0;
2186
8d96fe93
AD		 2187 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2188 return 0;
2189
747943ea
AD		 2190 dev_info(rdev->dev, "GPU softreset \n");
2191 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2192 RREG32(GRBM_STATUS));
2193 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2194 RREG32(GRBM_STATUS_SE0));
2195 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2196 RREG32(GRBM_STATUS_SE1));
2197 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2198 RREG32(SRBM_STATUS));
2199 evergreen_mc_stop(rdev, &save);
2200 if (evergreen_mc_wait_for_idle(rdev)) {
2201 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2202 }
2203 /* Disable CP parsing/prefetching */
2204 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2205
2206 /* reset all the gfx blocks */
2207 grbm_reset = (SOFT_RESET_CP |
2208 SOFT_RESET_CB |
2209 SOFT_RESET_DB |
2210 SOFT_RESET_PA |
2211 SOFT_RESET_SC |
2212 SOFT_RESET_SPI |
2213 SOFT_RESET_SH |
2214 SOFT_RESET_SX |
2215 SOFT_RESET_TC |
2216 SOFT_RESET_TA |
2217 SOFT_RESET_VC |
2218 SOFT_RESET_VGT);
2219
2220 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2221 WREG32(GRBM_SOFT_RESET, grbm_reset);
2222 (void)RREG32(GRBM_SOFT_RESET);
2223 udelay(50);
2224 WREG32(GRBM_SOFT_RESET, 0);
2225 (void)RREG32(GRBM_SOFT_RESET);
747943ea
AD		 2226 /* Wait a little for things to settle down */
2227 udelay(50);
2228 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2229 RREG32(GRBM_STATUS));
2230 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2231 RREG32(GRBM_STATUS_SE0));
2232 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2233 RREG32(GRBM_STATUS_SE1));
2234 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2235 RREG32(SRBM_STATUS));
747943ea 2236 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2237 return 0;
2238}
2239
a2d07b74 2240int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2241{
747943ea
AD		 2242 return evergreen_gpu_soft_reset(rdev);
2243}
2244
45f9a39b
AD		 2245/* Interrupts */
2246
2247u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2248{
2249 switch (crtc) {
2250 case 0:
2251 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2252 case 1:
2253 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2254 case 2:
2255 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2256 case 3:
2257 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2258 case 4:
2259 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2260 case 5:
2261 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2262 default:
2263 return 0;
2264 }
2265}
2266
2267void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2268{
2269 u32 tmp;
2270
1b37078b
AD		 2271 if (rdev->family >= CHIP_CAYMAN) {
2272 cayman_cp_int_cntl_setup(rdev, 0,
2273 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2274 cayman_cp_int_cntl_setup(rdev, 1, 0);
2275 cayman_cp_int_cntl_setup(rdev, 2, 0);
2276 } else
2277 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2278 WREG32(GRBM_INT_CNTL, 0);
2279 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2280 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2281 if (rdev->num_crtc >= 4) {
18007401
AD		 2282 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2283 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2284 }
2285 if (rdev->num_crtc >= 6) {
18007401
AD		 2286 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2287 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2288 }
45f9a39b
AD		 2289
2290 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2291 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2292 if (rdev->num_crtc >= 4) {
18007401
AD		 2293 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2294 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2295 }
2296 if (rdev->num_crtc >= 6) {
18007401
AD		 2297 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2298 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2299 }
45f9a39b 2300
05b3ef69
AD		 2301 /* only one DAC on DCE6 */
2302 if (!ASIC_IS_DCE6(rdev))
2303 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
45f9a39b
AD		 2304 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2305
2306 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2307 WREG32(DC_HPD1_INT_CONTROL, tmp);
2308 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2309 WREG32(DC_HPD2_INT_CONTROL, tmp);
2310 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2311 WREG32(DC_HPD3_INT_CONTROL, tmp);
2312 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2313 WREG32(DC_HPD4_INT_CONTROL, tmp);
2314 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2315 WREG32(DC_HPD5_INT_CONTROL, tmp);
2316 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2317 WREG32(DC_HPD6_INT_CONTROL, tmp);
2318
2319}
2320
2321int evergreen_irq_set(struct radeon_device *rdev)
2322{
2323 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 2324 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 2325 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2326 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2327 u32 grbm_int_cntl = 0;
6f34be50 2328 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
f122c610 2329 u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
45f9a39b
AD		 2330
2331 if (!rdev->irq.installed) {
fce7d61b 2332 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2333 return -EINVAL;
2334 }
2335 /* don't enable anything if the ih is disabled */
2336 if (!rdev->ih.enabled) {
2337 r600_disable_interrupts(rdev);
2338 /* force the active interrupt state to all disabled */
2339 evergreen_disable_interrupt_state(rdev);
2340 return 0;
2341 }
2342
2343 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2344 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2345 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2346 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2347 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2348 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2349
f122c610
AD		 2350 afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2351 afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2352 afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2353 afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2354 afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2355 afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2356
1b37078b
AD		 2357 if (rdev->family >= CHIP_CAYMAN) {
2358 /* enable CP interrupts on all rings */
736fc37f 2359 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2360 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2361 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2362 }
736fc37f 2363 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
1b37078b
AD		 2364 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2365 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2366 }
736fc37f 2367 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
1b37078b
AD		 2368 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2369 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2370 }
2371 } else {
736fc37f 2372 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
1b37078b
AD		 2373 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2374 cp_int_cntl |= RB_INT_ENABLE;
2375 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2376 }
45f9a39b 2377 }
1b37078b 2378
6f34be50 2379 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 2380 atomic_read(&rdev->irq.pflip[0])) {
45f9a39b
AD		 2381 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2382 crtc1 |= VBLANK_INT_MASK;
2383 }
6f34be50 2384 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 2385 atomic_read(&rdev->irq.pflip[1])) {
45f9a39b
AD		 2386 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2387 crtc2 |= VBLANK_INT_MASK;
2388 }
6f34be50 2389 if (rdev->irq.crtc_vblank_int[2] ||
736fc37f 2390 atomic_read(&rdev->irq.pflip[2])) {
45f9a39b
AD		 2391 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2392 crtc3 |= VBLANK_INT_MASK;
2393 }
6f34be50 2394 if (rdev->irq.crtc_vblank_int[3] ||
736fc37f 2395 atomic_read(&rdev->irq.pflip[3])) {
45f9a39b
AD		 2396 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2397 crtc4 |= VBLANK_INT_MASK;
2398 }
6f34be50 2399 if (rdev->irq.crtc_vblank_int[4] ||
736fc37f 2400 atomic_read(&rdev->irq.pflip[4])) {
45f9a39b
AD		 2401 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2402 crtc5 |= VBLANK_INT_MASK;
2403 }
6f34be50 2404 if (rdev->irq.crtc_vblank_int[5] ||
736fc37f 2405 atomic_read(&rdev->irq.pflip[5])) {
45f9a39b
AD		 2406 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2407 crtc6 |= VBLANK_INT_MASK;
2408 }
2409 if (rdev->irq.hpd[0]) {
2410 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2411 hpd1 |= DC_HPDx_INT_EN;
2412 }
2413 if (rdev->irq.hpd[1]) {
2414 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2415 hpd2 |= DC_HPDx_INT_EN;
2416 }
2417 if (rdev->irq.hpd[2]) {
2418 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2419 hpd3 |= DC_HPDx_INT_EN;
2420 }
2421 if (rdev->irq.hpd[3]) {
2422 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2423 hpd4 |= DC_HPDx_INT_EN;
2424 }
2425 if (rdev->irq.hpd[4]) {
2426 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2427 hpd5 |= DC_HPDx_INT_EN;
2428 }
2429 if (rdev->irq.hpd[5]) {
2430 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2431 hpd6 |= DC_HPDx_INT_EN;
2432 }
f122c610
AD		 2433 if (rdev->irq.afmt[0]) {
2434 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2435 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2436 }
2437 if (rdev->irq.afmt[1]) {
2438 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2439 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2440 }
2441 if (rdev->irq.afmt[2]) {
2442 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2443 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2444 }
2445 if (rdev->irq.afmt[3]) {
2446 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2447 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2448 }
2449 if (rdev->irq.afmt[4]) {
2450 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2451 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2452 }
2453 if (rdev->irq.afmt[5]) {
2454 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2455 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2456 }
2031f77c
AD		 2457 if (rdev->irq.gui_idle) {
2458 DRM_DEBUG("gui idle\n");
2459 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2460 }
45f9a39b 2461
1b37078b
AD		 2462 if (rdev->family >= CHIP_CAYMAN) {
2463 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2464 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2465 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2466 } else
2467 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2468 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2469
2470 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2471 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 2472 if (rdev->num_crtc >= 4) {
18007401
AD		 2473 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2474 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 2475 }
2476 if (rdev->num_crtc >= 6) {
18007401
AD		 2477 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2478 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2479 }
45f9a39b 2480
6f34be50
AD		 2481 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2482 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 2483 if (rdev->num_crtc >= 4) {
2484 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2485 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2486 }
2487 if (rdev->num_crtc >= 6) {
2488 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2489 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2490 }
6f34be50 2491
45f9a39b
AD		 2492 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2493 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2494 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2495 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2496 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2497 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2498
f122c610
AD		 2499 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2500 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2501 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2502 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2503 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2504 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2505
bcc1c2a1
AD		 2506 return 0;
2507}
2508
cbdd4501 2509static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2510{
2511 u32 tmp;
2512
6f34be50
AD		 2513 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2514 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2515 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2516 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2517 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2518 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2519 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2520 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 2521 if (rdev->num_crtc >= 4) {
2522 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2523 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2524 }
2525 if (rdev->num_crtc >= 6) {
2526 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2527 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2528 }
6f34be50 2529
f122c610
AD		 2530 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2531 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2532 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2533 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2534 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2535 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2536
6f34be50
AD		 2537 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2538 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2539 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2540 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 2541 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2542 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2543 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 2544 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 2545 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2546 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2547 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2548 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2549
b7eff394
AD		 2550 if (rdev->num_crtc >= 4) {
2551 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2552 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2553 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2554 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2555 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2556 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2557 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2558 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2559 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2560 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2561 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2562 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2563 }
2564
2565 if (rdev->num_crtc >= 6) {
2566 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2567 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2568 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2569 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2570 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2571 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2572 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2573 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2574 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2575 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2576 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2577 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2578 }
45f9a39b 2579
6f34be50 2580 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2581 tmp = RREG32(DC_HPD1_INT_CONTROL);
2582 tmp |= DC_HPDx_INT_ACK;
2583 WREG32(DC_HPD1_INT_CONTROL, tmp);
2584 }
6f34be50 2585 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2586 tmp = RREG32(DC_HPD2_INT_CONTROL);
2587 tmp |= DC_HPDx_INT_ACK;
2588 WREG32(DC_HPD2_INT_CONTROL, tmp);
2589 }
6f34be50 2590 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2591 tmp = RREG32(DC_HPD3_INT_CONTROL);
2592 tmp |= DC_HPDx_INT_ACK;
2593 WREG32(DC_HPD3_INT_CONTROL, tmp);
2594 }
6f34be50 2595 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2596 tmp = RREG32(DC_HPD4_INT_CONTROL);
2597 tmp |= DC_HPDx_INT_ACK;
2598 WREG32(DC_HPD4_INT_CONTROL, tmp);
2599 }
6f34be50 2600 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2601 tmp = RREG32(DC_HPD5_INT_CONTROL);
2602 tmp |= DC_HPDx_INT_ACK;
2603 WREG32(DC_HPD5_INT_CONTROL, tmp);
2604 }
6f34be50 2605 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2606 tmp = RREG32(DC_HPD5_INT_CONTROL);
2607 tmp |= DC_HPDx_INT_ACK;
2608 WREG32(DC_HPD6_INT_CONTROL, tmp);
2609 }
f122c610
AD		 2610 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2611 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2612 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2613 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2614 }
2615 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2616 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2617 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2618 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2619 }
2620 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2621 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2622 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2623 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2624 }
2625 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2626 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2627 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2628 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2629 }
2630 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2631 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2632 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2633 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2634 }
2635 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2636 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2637 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2638 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2639 }
45f9a39b
AD		 2640}
2641
2642void evergreen_irq_disable(struct radeon_device *rdev)
2643{
45f9a39b
AD		 2644 r600_disable_interrupts(rdev);
2645 /* Wait and acknowledge irq */
2646 mdelay(1);
6f34be50 2647 evergreen_irq_ack(rdev);
45f9a39b
AD		 2648 evergreen_disable_interrupt_state(rdev);
2649}
2650
755d819e 2651void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 2652{
2653 evergreen_irq_disable(rdev);
2654 r600_rlc_stop(rdev);
2655}
2656
cbdd4501 2657static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 2658{
2659 u32 wptr, tmp;
2660
724c80e1 2661 if (rdev->wb.enabled)
204ae24d 2662 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 2663 else
2664 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2665
2666 if (wptr & RB_OVERFLOW) {
2667 /* When a ring buffer overflow happen start parsing interrupt
2668 * from the last not overwritten vector (wptr + 16). Hopefully
2669 * this should allow us to catchup.
2670 */
2671 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2672 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2673 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2674 tmp = RREG32(IH_RB_CNTL);
2675 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2676 WREG32(IH_RB_CNTL, tmp);
2677 }
2678 return (wptr & rdev->ih.ptr_mask);
2679}
2680
2681int evergreen_irq_process(struct radeon_device *rdev)
2682{
682f1a54
DA		 2683 u32 wptr;
2684 u32 rptr;
45f9a39b
AD		 2685 u32 src_id, src_data;
2686 u32 ring_index;
45f9a39b 2687 bool queue_hotplug = false;
f122c610 2688 bool queue_hdmi = false;
45f9a39b 2689
682f1a54 2690 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 2691 return IRQ_NONE;
2692
682f1a54 2693 wptr = evergreen_get_ih_wptr(rdev);
c20dc369
CK		 2694
2695restart_ih:
2696 /* is somebody else already processing irqs? */
2697 if (atomic_xchg(&rdev->ih.lock, 1))
2698 return IRQ_NONE;
2699
682f1a54
DA		 2700 rptr = rdev->ih.rptr;
2701 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 2702
964f6645
BH		 2703 /* Order reading of wptr vs. reading of IH ring data */
2704 rmb();
2705
45f9a39b 2706 /* display interrupts */
6f34be50 2707 evergreen_irq_ack(rdev);
45f9a39b 2708
45f9a39b
AD		 2709 while (rptr != wptr) {
2710 /* wptr/rptr are in bytes! */
2711 ring_index = rptr / 4;
0f234f5f
AD		 2712 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2713 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 2714
2715 switch (src_id) {
2716 case 1: /* D1 vblank/vline */
2717 switch (src_data) {
2718 case 0: /* D1 vblank */
6f34be50 2719 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 2720 if (rdev->irq.crtc_vblank_int[0]) {
2721 drm_handle_vblank(rdev->ddev, 0);
2722 rdev->pm.vblank_sync = true;
2723 wake_up(&rdev->irq.vblank_queue);
2724 }
736fc37f 2725 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 2726 radeon_crtc_handle_flip(rdev, 0);
6f34be50 2727 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2728 DRM_DEBUG("IH: D1 vblank\n");
2729 }
2730 break;
2731 case 1: /* D1 vline */
6f34be50
AD		 2732 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2733 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 2734 DRM_DEBUG("IH: D1 vline\n");
2735 }
2736 break;
2737 default:
2738 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2739 break;
2740 }
2741 break;
2742 case 2: /* D2 vblank/vline */
2743 switch (src_data) {
2744 case 0: /* D2 vblank */
6f34be50 2745 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 2746 if (rdev->irq.crtc_vblank_int[1]) {
2747 drm_handle_vblank(rdev->ddev, 1);
2748 rdev->pm.vblank_sync = true;
2749 wake_up(&rdev->irq.vblank_queue);
2750 }
736fc37f 2751 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 2752 radeon_crtc_handle_flip(rdev, 1);
6f34be50 2753 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 2754 DRM_DEBUG("IH: D2 vblank\n");
2755 }
2756 break;
2757 case 1: /* D2 vline */
6f34be50
AD		 2758 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2759 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 2760 DRM_DEBUG("IH: D2 vline\n");
2761 }
2762 break;
2763 default:
2764 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2765 break;
2766 }
2767 break;
2768 case 3: /* D3 vblank/vline */
2769 switch (src_data) {
2770 case 0: /* D3 vblank */
6f34be50
AD		 2771 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2772 if (rdev->irq.crtc_vblank_int[2]) {
2773 drm_handle_vblank(rdev->ddev, 2);
2774 rdev->pm.vblank_sync = true;
2775 wake_up(&rdev->irq.vblank_queue);
2776 }
736fc37f 2777 if (atomic_read(&rdev->irq.pflip[2]))
6f34be50
AD		 2778 radeon_crtc_handle_flip(rdev, 2);
2779 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 2780 DRM_DEBUG("IH: D3 vblank\n");
2781 }
2782 break;
2783 case 1: /* D3 vline */
6f34be50
AD		 2784 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2785 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 2786 DRM_DEBUG("IH: D3 vline\n");
2787 }
2788 break;
2789 default:
2790 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2791 break;
2792 }
2793 break;
2794 case 4: /* D4 vblank/vline */
2795 switch (src_data) {
2796 case 0: /* D4 vblank */
6f34be50
AD		 2797 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2798 if (rdev->irq.crtc_vblank_int[3]) {
2799 drm_handle_vblank(rdev->ddev, 3);
2800 rdev->pm.vblank_sync = true;
2801 wake_up(&rdev->irq.vblank_queue);
2802 }
736fc37f 2803 if (atomic_read(&rdev->irq.pflip[3]))
6f34be50
AD		 2804 radeon_crtc_handle_flip(rdev, 3);
2805 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 2806 DRM_DEBUG("IH: D4 vblank\n");
2807 }
2808 break;
2809 case 1: /* D4 vline */
6f34be50
AD		 2810 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2811 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 2812 DRM_DEBUG("IH: D4 vline\n");
2813 }
2814 break;
2815 default:
2816 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2817 break;
2818 }
2819 break;
2820 case 5: /* D5 vblank/vline */
2821 switch (src_data) {
2822 case 0: /* D5 vblank */
6f34be50
AD		 2823 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2824 if (rdev->irq.crtc_vblank_int[4]) {
2825 drm_handle_vblank(rdev->ddev, 4);
2826 rdev->pm.vblank_sync = true;
2827 wake_up(&rdev->irq.vblank_queue);
2828 }
736fc37f 2829 if (atomic_read(&rdev->irq.pflip[4]))
6f34be50
AD		 2830 radeon_crtc_handle_flip(rdev, 4);
2831 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 2832 DRM_DEBUG("IH: D5 vblank\n");
2833 }
2834 break;
2835 case 1: /* D5 vline */
6f34be50
AD		 2836 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2837 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 2838 DRM_DEBUG("IH: D5 vline\n");
2839 }
2840 break;
2841 default:
2842 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2843 break;
2844 }
2845 break;
2846 case 6: /* D6 vblank/vline */
2847 switch (src_data) {
2848 case 0: /* D6 vblank */
6f34be50
AD		 2849 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2850 if (rdev->irq.crtc_vblank_int[5]) {
2851 drm_handle_vblank(rdev->ddev, 5);
2852 rdev->pm.vblank_sync = true;
2853 wake_up(&rdev->irq.vblank_queue);
2854 }
736fc37f 2855 if (atomic_read(&rdev->irq.pflip[5]))
6f34be50
AD		 2856 radeon_crtc_handle_flip(rdev, 5);
2857 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 2858 DRM_DEBUG("IH: D6 vblank\n");
2859 }
2860 break;
2861 case 1: /* D6 vline */
6f34be50
AD		 2862 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2863 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 2864 DRM_DEBUG("IH: D6 vline\n");
2865 }
2866 break;
2867 default:
2868 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2869 break;
2870 }
2871 break;
2872 case 42: /* HPD hotplug */
2873 switch (src_data) {
2874 case 0:
6f34be50
AD		 2875 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2876 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 2877 queue_hotplug = true;
2878 DRM_DEBUG("IH: HPD1\n");
2879 }
2880 break;
2881 case 1:
6f34be50
AD		 2882 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2883 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 2884 queue_hotplug = true;
2885 DRM_DEBUG("IH: HPD2\n");
2886 }
2887 break;
2888 case 2:
6f34be50
AD		 2889 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2890 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 2891 queue_hotplug = true;
2892 DRM_DEBUG("IH: HPD3\n");
2893 }
2894 break;
2895 case 3:
6f34be50
AD		 2896 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2897 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 2898 queue_hotplug = true;
2899 DRM_DEBUG("IH: HPD4\n");
2900 }
2901 break;
2902 case 4:
6f34be50
AD		 2903 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2904 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 2905 queue_hotplug = true;
2906 DRM_DEBUG("IH: HPD5\n");
2907 }
2908 break;
2909 case 5:
6f34be50
AD		 2910 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2911 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 2912 queue_hotplug = true;
2913 DRM_DEBUG("IH: HPD6\n");
2914 }
2915 break;
2916 default:
2917 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2918 break;
2919 }
2920 break;
f122c610
AD		 2921 case 44: /* hdmi */
2922 switch (src_data) {
2923 case 0:
2924 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2925 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
2926 queue_hdmi = true;
2927 DRM_DEBUG("IH: HDMI0\n");
2928 }
2929 break;
2930 case 1:
2931 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2932 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
2933 queue_hdmi = true;
2934 DRM_DEBUG("IH: HDMI1\n");
2935 }
2936 break;
2937 case 2:
2938 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2939 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
2940 queue_hdmi = true;
2941 DRM_DEBUG("IH: HDMI2\n");
2942 }
2943 break;
2944 case 3:
2945 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2946 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
2947 queue_hdmi = true;
2948 DRM_DEBUG("IH: HDMI3\n");
2949 }
2950 break;
2951 case 4:
2952 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2953 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
2954 queue_hdmi = true;
2955 DRM_DEBUG("IH: HDMI4\n");
2956 }
2957 break;
2958 case 5:
2959 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2960 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
2961 queue_hdmi = true;
2962 DRM_DEBUG("IH: HDMI5\n");
2963 }
2964 break;
2965 default:
2966 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
2967 break;
2968 }
2969 break;
45f9a39b
AD		 2970 case 176: /* CP_INT in ring buffer */
2971 case 177: /* CP_INT in IB1 */
2972 case 178: /* CP_INT in IB2 */
2973 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 2974 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 2975 break;
2976 case 181: /* CP EOP event */
2977 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 2978 if (rdev->family >= CHIP_CAYMAN) {
2979 switch (src_data) {
2980 case 0:
2981 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
2982 break;
2983 case 1:
2984 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2985 break;
2986 case 2:
2987 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2988 break;
2989 }
2990 } else
2991 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 2992 break;
2031f77c 2993 case 233: /* GUI IDLE */
303c805c 2994 DRM_DEBUG("IH: GUI idle\n");
2031f77c
AD		 2995 wake_up(&rdev->irq.idle_queue);
2996 break;
45f9a39b
AD		 2997 default:
2998 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2999 break;
3000 }
3001
3002 /* wptr/rptr are in bytes! */
3003 rptr += 16;
3004 rptr &= rdev->ih.ptr_mask;
3005 }
45f9a39b 3006 if (queue_hotplug)
32c87fca 3007 schedule_work(&rdev->hotplug_work);
f122c610
AD		 3008 if (queue_hdmi)
3009 schedule_work(&rdev->audio_work);
45f9a39b
AD		 3010 rdev->ih.rptr = rptr;
3011 WREG32(IH_RB_RPTR, rdev->ih.rptr);
c20dc369
CK		 3012 atomic_set(&rdev->ih.lock, 0);
3013
3014 /* make sure wptr hasn't changed while processing */
3015 wptr = evergreen_get_ih_wptr(rdev);
3016 if (wptr != rptr)
3017 goto restart_ih;
3018
45f9a39b
AD		 3019 return IRQ_HANDLED;
3020}
3021
bcc1c2a1
AD		 3022static int evergreen_startup(struct radeon_device *rdev)
3023{
e32eb50d 3024 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
bcc1c2a1
AD		 3025 int r;
3026
9e46a48d 3027 /* enable pcie gen2 link */
cd54033a 3028 evergreen_pcie_gen2_enable(rdev);
9e46a48d 3029
0af62b01
AD		 3030 if (ASIC_IS_DCE5(rdev)) {
3031 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3032 r = ni_init_microcode(rdev);
3033 if (r) {
3034 DRM_ERROR("Failed to load firmware!\n");
3035 return r;
3036 }
3037 }
755d819e 3038 r = ni_mc_load_microcode(rdev);
bcc1c2a1 3039 if (r) {
0af62b01 3040 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 3041 return r;
3042 }
0af62b01
AD		 3043 } else {
3044 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3045 r = r600_init_microcode(rdev);
3046 if (r) {
3047 DRM_ERROR("Failed to load firmware!\n");
3048 return r;
3049 }
3050 }
bcc1c2a1 3051 }
fe251e2f 3052
16cdf04d
AD		 3053 r = r600_vram_scratch_init(rdev);
3054 if (r)
3055 return r;
3056
bcc1c2a1 3057 evergreen_mc_program(rdev);
bcc1c2a1 3058 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 3059 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 3060 } else {
3061 r = evergreen_pcie_gart_enable(rdev);
3062 if (r)
3063 return r;
3064 }
bcc1c2a1 3065 evergreen_gpu_init(rdev);
bcc1c2a1 3066
d7ccd8fc 3067 r = evergreen_blit_init(rdev);
bcc1c2a1 3068 if (r) {
fb3d9e97 3069 r600_blit_fini(rdev);
27cd7769 3070 rdev->asic->copy.copy = NULL;
d7ccd8fc 3071 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 3072 }
3073
724c80e1
AD		 3074 /* allocate wb buffer */
3075 r = radeon_wb_init(rdev);
3076 if (r)
3077 return r;
3078
30eb77f4
JG		 3079 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3080 if (r) {
3081 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3082 return r;
3083 }
3084
bcc1c2a1
AD		 3085 /* Enable IRQ */
3086 r = r600_irq_init(rdev);
3087 if (r) {
3088 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3089 radeon_irq_kms_fini(rdev);
3090 return r;
3091 }
45f9a39b 3092 evergreen_irq_set(rdev);
bcc1c2a1 3093
e32eb50d 3094 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 3095 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3096 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 3097 if (r)
3098 return r;
3099 r = evergreen_cp_load_microcode(rdev);
3100 if (r)
3101 return r;
fe251e2f 3102 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 3103 if (r)
3104 return r;
fe251e2f 3105
2898c348
CK		 3106 r = radeon_ib_pool_init(rdev);
3107 if (r) {
3108 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3109 return r;
2898c348 3110 }
b15ba512 3111
69d2ae57
RM		 3112 r = r600_audio_init(rdev);
3113 if (r) {
3114 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 3115 return r;
3116 }
3117
bcc1c2a1
AD		 3118 return 0;
3119}
3120
3121int evergreen_resume(struct radeon_device *rdev)
3122{
3123 int r;
3124
86f5c9ed
AD		 3125 /* reset the asic, the gfx blocks are often in a bad state
3126 * after the driver is unloaded or after a resume
3127 */
3128 if (radeon_asic_reset(rdev))
3129 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 3130 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3131 * posting will perform necessary task to bring back GPU into good
3132 * shape.
3133 */
3134 /* post card */
3135 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 3136
b15ba512 3137 rdev->accel_working = true;
bcc1c2a1
AD		 3138 r = evergreen_startup(rdev);
3139 if (r) {
755d819e 3140 DRM_ERROR("evergreen startup failed on resume\n");
6b7746e8 3141 rdev->accel_working = false;
bcc1c2a1
AD		 3142 return r;
3143 }
fe251e2f 3144
bcc1c2a1
AD		 3145 return r;
3146
3147}
3148
3149int evergreen_suspend(struct radeon_device *rdev)
3150{
e32eb50d 3151 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3152
69d2ae57 3153 r600_audio_fini(rdev);
bcc1c2a1 3154 r700_cp_stop(rdev);
e32eb50d 3155 ring->ready = false;
45f9a39b 3156 evergreen_irq_suspend(rdev);
724c80e1 3157 radeon_wb_disable(rdev);
bcc1c2a1 3158 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 3159
3160 return 0;
3161}
3162
bcc1c2a1
AD		 3163/* Plan is to move initialization in that function and use
3164 * helper function so that radeon_device_init pretty much
3165 * do nothing more than calling asic specific function. This
3166 * should also allow to remove a bunch of callback function
3167 * like vram_info.
3168 */
3169int evergreen_init(struct radeon_device *rdev)
3170{
3171 int r;
3172
bcc1c2a1
AD		 3173 /* Read BIOS */
3174 if (!radeon_get_bios(rdev)) {
3175 if (ASIC_IS_AVIVO(rdev))
3176 return -EINVAL;
3177 }
3178 /* Must be an ATOMBIOS */
3179 if (!rdev->is_atom_bios) {
755d819e 3180 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 3181 return -EINVAL;
3182 }
3183 r = radeon_atombios_init(rdev);
3184 if (r)
3185 return r;
86f5c9ed
AD		 3186 /* reset the asic, the gfx blocks are often in a bad state
3187 * after the driver is unloaded or after a resume
3188 */
3189 if (radeon_asic_reset(rdev))
3190 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 3191 /* Post card if necessary */
fd909c37 3192 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 3193 if (!rdev->bios) {
3194 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3195 return -EINVAL;
3196 }
3197 DRM_INFO("GPU not posted. posting now...\n");
3198 atom_asic_init(rdev->mode_info.atom_context);
3199 }
3200 /* Initialize scratch registers */
3201 r600_scratch_init(rdev);
3202 /* Initialize surface registers */
3203 radeon_surface_init(rdev);
3204 /* Initialize clocks */
3205 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 3206 /* Fence driver */
3207 r = radeon_fence_driver_init(rdev);
3208 if (r)
3209 return r;
d594e46a
JG		 3210 /* initialize AGP */
3211 if (rdev->flags & RADEON_IS_AGP) {
3212 r = radeon_agp_init(rdev);
3213 if (r)
3214 radeon_agp_disable(rdev);
3215 }
3216 /* initialize memory controller */
bcc1c2a1
AD		 3217 r = evergreen_mc_init(rdev);
3218 if (r)
3219 return r;
3220 /* Memory manager */
3221 r = radeon_bo_init(rdev);
3222 if (r)
3223 return r;
45f9a39b 3224
bcc1c2a1
AD		 3225 r = radeon_irq_kms_init(rdev);
3226 if (r)
3227 return r;
3228
e32eb50d
CK		 3229 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3230 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1
AD		 3231
3232 rdev->ih.ring_obj = NULL;
3233 r600_ih_ring_init(rdev, 64 * 1024);
3234
3235 r = r600_pcie_gart_init(rdev);
3236 if (r)
3237 return r;
0fcdb61e 3238
148a03bc 3239 rdev->accel_working = true;
bcc1c2a1
AD		 3240 r = evergreen_startup(rdev);
3241 if (r) {
fe251e2f
AD		 3242 dev_err(rdev->dev, "disabling GPU acceleration\n");
3243 r700_cp_fini(rdev);
fe251e2f 3244 r600_irq_fini(rdev);
724c80e1 3245 radeon_wb_fini(rdev);
2898c348 3246 radeon_ib_pool_fini(rdev);
fe251e2f 3247 radeon_irq_kms_fini(rdev);
0fcdb61e 3248 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3249 rdev->accel_working = false;
3250 }
77e00f2e
AD		 3251
3252 /* Don't start up if the MC ucode is missing on BTC parts.
3253 * The default clocks and voltages before the MC ucode
3254 * is loaded are not suffient for advanced operations.
3255 */
3256 if (ASIC_IS_DCE5(rdev)) {
3257 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3258 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3259 return -EINVAL;
3260 }
3261 }
3262
bcc1c2a1
AD		 3263 return 0;
3264}
3265
3266void evergreen_fini(struct radeon_device *rdev)
3267{
69d2ae57 3268 r600_audio_fini(rdev);
fb3d9e97 3269 r600_blit_fini(rdev);
45f9a39b 3270 r700_cp_fini(rdev);
bcc1c2a1 3271 r600_irq_fini(rdev);
724c80e1 3272 radeon_wb_fini(rdev);
2898c348 3273 radeon_ib_pool_fini(rdev);
bcc1c2a1 3274 radeon_irq_kms_fini(rdev);
bcc1c2a1 3275 evergreen_pcie_gart_fini(rdev);
16cdf04d 3276 r600_vram_scratch_fini(rdev);
bcc1c2a1
AD		 3277 radeon_gem_fini(rdev);
3278 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3279 radeon_agp_fini(rdev);
3280 radeon_bo_fini(rdev);
3281 radeon_atombios_fini(rdev);
3282 kfree(rdev->bios);
3283 rdev->bios = NULL;
bcc1c2a1 3284}
9e46a48d 3285
b07759bf 3286void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d
AD		 3287{
3288 u32 link_width_cntl, speed_cntl;
3289
d42dd579
AD		 3290 if (radeon_pcie_gen2 == 0)
3291 return;
3292
9e46a48d
AD		 3293 if (rdev->flags & RADEON_IS_IGP)
3294 return;
3295
3296 if (!(rdev->flags & RADEON_IS_PCIE))
3297 return;
3298
3299 /* x2 cards have a special sequence */
3300 if (ASIC_IS_X2(rdev))
3301 return;
3302
3303 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3304 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3305 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3306
3307 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3308 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3309 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3310
3311 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3312 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3313 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3314
3315 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3316 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3317 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3318
3319 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3320 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3321 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3322
3323 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3324 speed_cntl |= LC_GEN2_EN_STRAP;
3325 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3326
3327 } else {
3328 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3329 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3330 if (1)
3331 link_width_cntl |= LC_UPCONFIGURE_DIS;
3332 else
3333 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3334 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3335 }
3336}
Linux kernel - Deliverables
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