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Merge remote branch 'nouveau/drm-nouveau-next' of ../drm-nouveau-next into drm-core...
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
42
6f34be50
AD		 43void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
44{
45 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
46 u32 tmp;
47
48 /* make sure flip is at vb rather than hb */
49 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
50 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
51 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
52
53 /* set pageflip to happen anywhere in vblank interval */
54 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
55
56 /* enable the pflip int */
57 radeon_irq_kms_pflip_irq_get(rdev, crtc);
58}
59
60void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
61{
62 /* disable the pflip int */
63 radeon_irq_kms_pflip_irq_put(rdev, crtc);
64}
65
66u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
67{
68 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
69 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
70
71 /* Lock the graphics update lock */
72 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
73 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
74
75 /* update the scanout addresses */
76 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
77 upper_32_bits(crtc_base));
78 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
79 (u32)crtc_base);
80
81 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
82 upper_32_bits(crtc_base));
83 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
84 (u32)crtc_base);
85
86 /* Wait for update_pending to go high. */
87 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
88 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
89
90 /* Unlock the lock, so double-buffering can take place inside vblank */
91 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
92 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
93
94 /* Return current update_pending status: */
95 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
96}
97
21a8122a
AD		 98/* get temperature in millidegrees */
99u32 evergreen_get_temp(struct radeon_device *rdev)
100{
101 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
102 ASIC_T_SHIFT;
103 u32 actual_temp = 0;
104
105 if ((temp >> 10) & 1)
106 actual_temp = 0;
107 else if ((temp >> 9) & 1)
108 actual_temp = 255;
109 else
110 actual_temp = (temp >> 1) & 0xff;
111
112 return actual_temp * 1000;
113}
114
e33df25f
AD		 115u32 sumo_get_temp(struct radeon_device *rdev)
116{
117 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
118 u32 actual_temp = (temp >> 1) & 0xff;
119
120 return actual_temp * 1000;
121}
122
49e02b73
AD		 123void evergreen_pm_misc(struct radeon_device *rdev)
124{
a081a9d6
RM		 125 int req_ps_idx = rdev->pm.requested_power_state_index;
126 int req_cm_idx = rdev->pm.requested_clock_mode_index;
127 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
128 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 129
4d60173f
AD		 130 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
131 if (voltage->voltage != rdev->pm.current_vddc) {
132 radeon_atom_set_voltage(rdev, voltage->voltage);
133 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 134 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 135 }
136 }
49e02b73
AD		 137}
138
139void evergreen_pm_prepare(struct radeon_device *rdev)
140{
141 struct drm_device *ddev = rdev->ddev;
142 struct drm_crtc *crtc;
143 struct radeon_crtc *radeon_crtc;
144 u32 tmp;
145
146 /* disable any active CRTCs */
147 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
148 radeon_crtc = to_radeon_crtc(crtc);
149 if (radeon_crtc->enabled) {
150 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
151 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
152 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
153 }
154 }
155}
156
157void evergreen_pm_finish(struct radeon_device *rdev)
158{
159 struct drm_device *ddev = rdev->ddev;
160 struct drm_crtc *crtc;
161 struct radeon_crtc *radeon_crtc;
162 u32 tmp;
163
164 /* enable any active CRTCs */
165 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
166 radeon_crtc = to_radeon_crtc(crtc);
167 if (radeon_crtc->enabled) {
168 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
169 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
170 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
171 }
172 }
173}
174
bcc1c2a1
AD		 175bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
176{
177 bool connected = false;
0ca2ab52
AD		 178
179 switch (hpd) {
180 case RADEON_HPD_1:
181 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
182 connected = true;
183 break;
184 case RADEON_HPD_2:
185 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
186 connected = true;
187 break;
188 case RADEON_HPD_3:
189 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
190 connected = true;
191 break;
192 case RADEON_HPD_4:
193 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
194 connected = true;
195 break;
196 case RADEON_HPD_5:
197 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
198 connected = true;
199 break;
200 case RADEON_HPD_6:
201 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
202 connected = true;
203 break;
204 default:
205 break;
206 }
207
bcc1c2a1
AD		 208 return connected;
209}
210
211void evergreen_hpd_set_polarity(struct radeon_device *rdev,
212 enum radeon_hpd_id hpd)
213{
0ca2ab52
AD		 214 u32 tmp;
215 bool connected = evergreen_hpd_sense(rdev, hpd);
216
217 switch (hpd) {
218 case RADEON_HPD_1:
219 tmp = RREG32(DC_HPD1_INT_CONTROL);
220 if (connected)
221 tmp &= ~DC_HPDx_INT_POLARITY;
222 else
223 tmp |= DC_HPDx_INT_POLARITY;
224 WREG32(DC_HPD1_INT_CONTROL, tmp);
225 break;
226 case RADEON_HPD_2:
227 tmp = RREG32(DC_HPD2_INT_CONTROL);
228 if (connected)
229 tmp &= ~DC_HPDx_INT_POLARITY;
230 else
231 tmp |= DC_HPDx_INT_POLARITY;
232 WREG32(DC_HPD2_INT_CONTROL, tmp);
233 break;
234 case RADEON_HPD_3:
235 tmp = RREG32(DC_HPD3_INT_CONTROL);
236 if (connected)
237 tmp &= ~DC_HPDx_INT_POLARITY;
238 else
239 tmp |= DC_HPDx_INT_POLARITY;
240 WREG32(DC_HPD3_INT_CONTROL, tmp);
241 break;
242 case RADEON_HPD_4:
243 tmp = RREG32(DC_HPD4_INT_CONTROL);
244 if (connected)
245 tmp &= ~DC_HPDx_INT_POLARITY;
246 else
247 tmp |= DC_HPDx_INT_POLARITY;
248 WREG32(DC_HPD4_INT_CONTROL, tmp);
249 break;
250 case RADEON_HPD_5:
251 tmp = RREG32(DC_HPD5_INT_CONTROL);
252 if (connected)
253 tmp &= ~DC_HPDx_INT_POLARITY;
254 else
255 tmp |= DC_HPDx_INT_POLARITY;
256 WREG32(DC_HPD5_INT_CONTROL, tmp);
257 break;
258 case RADEON_HPD_6:
259 tmp = RREG32(DC_HPD6_INT_CONTROL);
260 if (connected)
261 tmp &= ~DC_HPDx_INT_POLARITY;
262 else
263 tmp |= DC_HPDx_INT_POLARITY;
264 WREG32(DC_HPD6_INT_CONTROL, tmp);
265 break;
266 default:
267 break;
268 }
bcc1c2a1
AD		 269}
270
271void evergreen_hpd_init(struct radeon_device *rdev)
272{
0ca2ab52
AD		 273 struct drm_device *dev = rdev->ddev;
274 struct drm_connector *connector;
275 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
276 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 277
0ca2ab52
AD		 278 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
279 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
280 switch (radeon_connector->hpd.hpd) {
281 case RADEON_HPD_1:
282 WREG32(DC_HPD1_CONTROL, tmp);
283 rdev->irq.hpd[0] = true;
284 break;
285 case RADEON_HPD_2:
286 WREG32(DC_HPD2_CONTROL, tmp);
287 rdev->irq.hpd[1] = true;
288 break;
289 case RADEON_HPD_3:
290 WREG32(DC_HPD3_CONTROL, tmp);
291 rdev->irq.hpd[2] = true;
292 break;
293 case RADEON_HPD_4:
294 WREG32(DC_HPD4_CONTROL, tmp);
295 rdev->irq.hpd[3] = true;
296 break;
297 case RADEON_HPD_5:
298 WREG32(DC_HPD5_CONTROL, tmp);
299 rdev->irq.hpd[4] = true;
300 break;
301 case RADEON_HPD_6:
302 WREG32(DC_HPD6_CONTROL, tmp);
303 rdev->irq.hpd[5] = true;
304 break;
305 default:
306 break;
307 }
308 }
309 if (rdev->irq.installed)
310 evergreen_irq_set(rdev);
bcc1c2a1
AD		 311}
312
0ca2ab52 313void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 314{
0ca2ab52
AD		 315 struct drm_device *dev = rdev->ddev;
316 struct drm_connector *connector;
317
318 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
319 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
320 switch (radeon_connector->hpd.hpd) {
321 case RADEON_HPD_1:
322 WREG32(DC_HPD1_CONTROL, 0);
323 rdev->irq.hpd[0] = false;
324 break;
325 case RADEON_HPD_2:
326 WREG32(DC_HPD2_CONTROL, 0);
327 rdev->irq.hpd[1] = false;
328 break;
329 case RADEON_HPD_3:
330 WREG32(DC_HPD3_CONTROL, 0);
331 rdev->irq.hpd[2] = false;
332 break;
333 case RADEON_HPD_4:
334 WREG32(DC_HPD4_CONTROL, 0);
335 rdev->irq.hpd[3] = false;
336 break;
337 case RADEON_HPD_5:
338 WREG32(DC_HPD5_CONTROL, 0);
339 rdev->irq.hpd[4] = false;
340 break;
341 case RADEON_HPD_6:
342 WREG32(DC_HPD6_CONTROL, 0);
343 rdev->irq.hpd[5] = false;
344 break;
345 default:
346 break;
347 }
348 }
bcc1c2a1
AD		 349}
350
f9d9c362
AD		 351/* watermark setup */
352
353static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
354 struct radeon_crtc *radeon_crtc,
355 struct drm_display_mode *mode,
356 struct drm_display_mode *other_mode)
357{
358 u32 tmp = 0;
359 /*
360 * Line Buffer Setup
361 * There are 3 line buffers, each one shared by 2 display controllers.
362 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
363 * the display controllers. The paritioning is done via one of four
364 * preset allocations specified in bits 2:0:
365 * first display controller
366 * 0 - first half of lb (3840 * 2)
367 * 1 - first 3/4 of lb (5760 * 2)
368 * 2 - whole lb (7680 * 2)
369 * 3 - first 1/4 of lb (1920 * 2)
370 * second display controller
371 * 4 - second half of lb (3840 * 2)
372 * 5 - second 3/4 of lb (5760 * 2)
373 * 6 - whole lb (7680 * 2)
374 * 7 - last 1/4 of lb (1920 * 2)
375 */
376 if (mode && other_mode) {
377 if (mode->hdisplay > other_mode->hdisplay) {
378 if (mode->hdisplay > 2560)
379 tmp = 1; /* 3/4 */
380 else
381 tmp = 0; /* 1/2 */
382 } else if (other_mode->hdisplay > mode->hdisplay) {
383 if (other_mode->hdisplay > 2560)
384 tmp = 3; /* 1/4 */
385 else
386 tmp = 0; /* 1/2 */
387 } else
388 tmp = 0; /* 1/2 */
389 } else if (mode)
390 tmp = 2; /* whole */
391 else if (other_mode)
392 tmp = 3; /* 1/4 */
393
394 /* second controller of the pair uses second half of the lb */
395 if (radeon_crtc->crtc_id % 2)
396 tmp += 4;
397 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
398
399 switch (tmp) {
400 case 0:
401 case 4:
402 default:
403 return 3840 * 2;
404 case 1:
405 case 5:
406 return 5760 * 2;
407 case 2:
408 case 6:
409 return 7680 * 2;
410 case 3:
411 case 7:
412 return 1920 * 2;
413 }
414}
415
416static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
417{
418 u32 tmp = RREG32(MC_SHARED_CHMAP);
419
420 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
421 case 0:
422 default:
423 return 1;
424 case 1:
425 return 2;
426 case 2:
427 return 4;
428 case 3:
429 return 8;
430 }
431}
432
433struct evergreen_wm_params {
434 u32 dram_channels; /* number of dram channels */
435 u32 yclk; /* bandwidth per dram data pin in kHz */
436 u32 sclk; /* engine clock in kHz */
437 u32 disp_clk; /* display clock in kHz */
438 u32 src_width; /* viewport width */
439 u32 active_time; /* active display time in ns */
440 u32 blank_time; /* blank time in ns */
441 bool interlaced; /* mode is interlaced */
442 fixed20_12 vsc; /* vertical scale ratio */
443 u32 num_heads; /* number of active crtcs */
444 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
445 u32 lb_size; /* line buffer allocated to pipe */
446 u32 vtaps; /* vertical scaler taps */
447};
448
449static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
450{
451 /* Calculate DRAM Bandwidth and the part allocated to display. */
452 fixed20_12 dram_efficiency; /* 0.7 */
453 fixed20_12 yclk, dram_channels, bandwidth;
454 fixed20_12 a;
455
456 a.full = dfixed_const(1000);
457 yclk.full = dfixed_const(wm->yclk);
458 yclk.full = dfixed_div(yclk, a);
459 dram_channels.full = dfixed_const(wm->dram_channels * 4);
460 a.full = dfixed_const(10);
461 dram_efficiency.full = dfixed_const(7);
462 dram_efficiency.full = dfixed_div(dram_efficiency, a);
463 bandwidth.full = dfixed_mul(dram_channels, yclk);
464 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
465
466 return dfixed_trunc(bandwidth);
467}
468
469static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
470{
471 /* Calculate DRAM Bandwidth and the part allocated to display. */
472 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
473 fixed20_12 yclk, dram_channels, bandwidth;
474 fixed20_12 a;
475
476 a.full = dfixed_const(1000);
477 yclk.full = dfixed_const(wm->yclk);
478 yclk.full = dfixed_div(yclk, a);
479 dram_channels.full = dfixed_const(wm->dram_channels * 4);
480 a.full = dfixed_const(10);
481 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
482 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
483 bandwidth.full = dfixed_mul(dram_channels, yclk);
484 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
485
486 return dfixed_trunc(bandwidth);
487}
488
489static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
490{
491 /* Calculate the display Data return Bandwidth */
492 fixed20_12 return_efficiency; /* 0.8 */
493 fixed20_12 sclk, bandwidth;
494 fixed20_12 a;
495
496 a.full = dfixed_const(1000);
497 sclk.full = dfixed_const(wm->sclk);
498 sclk.full = dfixed_div(sclk, a);
499 a.full = dfixed_const(10);
500 return_efficiency.full = dfixed_const(8);
501 return_efficiency.full = dfixed_div(return_efficiency, a);
502 a.full = dfixed_const(32);
503 bandwidth.full = dfixed_mul(a, sclk);
504 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
505
506 return dfixed_trunc(bandwidth);
507}
508
509static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
510{
511 /* Calculate the DMIF Request Bandwidth */
512 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
513 fixed20_12 disp_clk, bandwidth;
514 fixed20_12 a;
515
516 a.full = dfixed_const(1000);
517 disp_clk.full = dfixed_const(wm->disp_clk);
518 disp_clk.full = dfixed_div(disp_clk, a);
519 a.full = dfixed_const(10);
520 disp_clk_request_efficiency.full = dfixed_const(8);
521 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
522 a.full = dfixed_const(32);
523 bandwidth.full = dfixed_mul(a, disp_clk);
524 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
525
526 return dfixed_trunc(bandwidth);
527}
528
529static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
530{
531 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
532 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
533 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
534 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
535
536 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
537}
538
539static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
540{
541 /* Calculate the display mode Average Bandwidth
542 * DisplayMode should contain the source and destination dimensions,
543 * timing, etc.
544 */
545 fixed20_12 bpp;
546 fixed20_12 line_time;
547 fixed20_12 src_width;
548 fixed20_12 bandwidth;
549 fixed20_12 a;
550
551 a.full = dfixed_const(1000);
552 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
553 line_time.full = dfixed_div(line_time, a);
554 bpp.full = dfixed_const(wm->bytes_per_pixel);
555 src_width.full = dfixed_const(wm->src_width);
556 bandwidth.full = dfixed_mul(src_width, bpp);
557 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
558 bandwidth.full = dfixed_div(bandwidth, line_time);
559
560 return dfixed_trunc(bandwidth);
561}
562
563static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
564{
565 /* First calcualte the latency in ns */
566 u32 mc_latency = 2000; /* 2000 ns. */
567 u32 available_bandwidth = evergreen_available_bandwidth(wm);
568 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
569 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
570 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
571 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
572 (wm->num_heads * cursor_line_pair_return_time);
573 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
574 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
575 fixed20_12 a, b, c;
576
577 if (wm->num_heads == 0)
578 return 0;
579
580 a.full = dfixed_const(2);
581 b.full = dfixed_const(1);
582 if ((wm->vsc.full > a.full) ||
583 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
584 (wm->vtaps >= 5) ||
585 ((wm->vsc.full >= a.full) && wm->interlaced))
586 max_src_lines_per_dst_line = 4;
587 else
588 max_src_lines_per_dst_line = 2;
589
590 a.full = dfixed_const(available_bandwidth);
591 b.full = dfixed_const(wm->num_heads);
592 a.full = dfixed_div(a, b);
593
594 b.full = dfixed_const(1000);
595 c.full = dfixed_const(wm->disp_clk);
596 b.full = dfixed_div(c, b);
597 c.full = dfixed_const(wm->bytes_per_pixel);
598 b.full = dfixed_mul(b, c);
599
600 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
601
602 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
603 b.full = dfixed_const(1000);
604 c.full = dfixed_const(lb_fill_bw);
605 b.full = dfixed_div(c, b);
606 a.full = dfixed_div(a, b);
607 line_fill_time = dfixed_trunc(a);
608
609 if (line_fill_time < wm->active_time)
610 return latency;
611 else
612 return latency + (line_fill_time - wm->active_time);
613
614}
615
616static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
617{
618 if (evergreen_average_bandwidth(wm) <=
619 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
620 return true;
621 else
622 return false;
623};
624
625static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
626{
627 if (evergreen_average_bandwidth(wm) <=
628 (evergreen_available_bandwidth(wm) / wm->num_heads))
629 return true;
630 else
631 return false;
632};
633
634static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
635{
636 u32 lb_partitions = wm->lb_size / wm->src_width;
637 u32 line_time = wm->active_time + wm->blank_time;
638 u32 latency_tolerant_lines;
639 u32 latency_hiding;
640 fixed20_12 a;
641
642 a.full = dfixed_const(1);
643 if (wm->vsc.full > a.full)
644 latency_tolerant_lines = 1;
645 else {
646 if (lb_partitions <= (wm->vtaps + 1))
647 latency_tolerant_lines = 1;
648 else
649 latency_tolerant_lines = 2;
650 }
651
652 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
653
654 if (evergreen_latency_watermark(wm) <= latency_hiding)
655 return true;
656 else
657 return false;
658}
659
660static void evergreen_program_watermarks(struct radeon_device *rdev,
661 struct radeon_crtc *radeon_crtc,
662 u32 lb_size, u32 num_heads)
663{
664 struct drm_display_mode *mode = &radeon_crtc->base.mode;
665 struct evergreen_wm_params wm;
666 u32 pixel_period;
667 u32 line_time = 0;
668 u32 latency_watermark_a = 0, latency_watermark_b = 0;
669 u32 priority_a_mark = 0, priority_b_mark = 0;
670 u32 priority_a_cnt = PRIORITY_OFF;
671 u32 priority_b_cnt = PRIORITY_OFF;
672 u32 pipe_offset = radeon_crtc->crtc_id * 16;
673 u32 tmp, arb_control3;
674 fixed20_12 a, b, c;
675
676 if (radeon_crtc->base.enabled && num_heads && mode) {
677 pixel_period = 1000000 / (u32)mode->clock;
678 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
679 priority_a_cnt = 0;
680 priority_b_cnt = 0;
681
682 wm.yclk = rdev->pm.current_mclk * 10;
683 wm.sclk = rdev->pm.current_sclk * 10;
684 wm.disp_clk = mode->clock;
685 wm.src_width = mode->crtc_hdisplay;
686 wm.active_time = mode->crtc_hdisplay * pixel_period;
687 wm.blank_time = line_time - wm.active_time;
688 wm.interlaced = false;
689 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
690 wm.interlaced = true;
691 wm.vsc = radeon_crtc->vsc;
692 wm.vtaps = 1;
693 if (radeon_crtc->rmx_type != RMX_OFF)
694 wm.vtaps = 2;
695 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
696 wm.lb_size = lb_size;
697 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
698 wm.num_heads = num_heads;
699
700 /* set for high clocks */
701 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
702 /* set for low clocks */
703 /* wm.yclk = low clk; wm.sclk = low clk */
704 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
705
706 /* possibly force display priority to high */
707 /* should really do this at mode validation time... */
708 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
709 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
710 !evergreen_check_latency_hiding(&wm) ||
711 (rdev->disp_priority == 2)) {
712 DRM_INFO("force priority to high\n");
713 priority_a_cnt |= PRIORITY_ALWAYS_ON;
714 priority_b_cnt |= PRIORITY_ALWAYS_ON;
715 }
716
717 a.full = dfixed_const(1000);
718 b.full = dfixed_const(mode->clock);
719 b.full = dfixed_div(b, a);
720 c.full = dfixed_const(latency_watermark_a);
721 c.full = dfixed_mul(c, b);
722 c.full = dfixed_mul(c, radeon_crtc->hsc);
723 c.full = dfixed_div(c, a);
724 a.full = dfixed_const(16);
725 c.full = dfixed_div(c, a);
726 priority_a_mark = dfixed_trunc(c);
727 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
728
729 a.full = dfixed_const(1000);
730 b.full = dfixed_const(mode->clock);
731 b.full = dfixed_div(b, a);
732 c.full = dfixed_const(latency_watermark_b);
733 c.full = dfixed_mul(c, b);
734 c.full = dfixed_mul(c, radeon_crtc->hsc);
735 c.full = dfixed_div(c, a);
736 a.full = dfixed_const(16);
737 c.full = dfixed_div(c, a);
738 priority_b_mark = dfixed_trunc(c);
739 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
740 }
741
742 /* select wm A */
743 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
744 tmp = arb_control3;
745 tmp &= ~LATENCY_WATERMARK_MASK(3);
746 tmp |= LATENCY_WATERMARK_MASK(1);
747 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
748 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
749 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
750 LATENCY_HIGH_WATERMARK(line_time)));
751 /* select wm B */
752 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
753 tmp &= ~LATENCY_WATERMARK_MASK(3);
754 tmp |= LATENCY_WATERMARK_MASK(2);
755 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
756 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
757 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
758 LATENCY_HIGH_WATERMARK(line_time)));
759 /* restore original selection */
760 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
761
762 /* write the priority marks */
763 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
764 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
765
766}
767
0ca2ab52 768void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 769{
f9d9c362
AD		 770 struct drm_display_mode *mode0 = NULL;
771 struct drm_display_mode *mode1 = NULL;
772 u32 num_heads = 0, lb_size;
773 int i;
774
775 radeon_update_display_priority(rdev);
776
777 for (i = 0; i < rdev->num_crtc; i++) {
778 if (rdev->mode_info.crtcs[i]->base.enabled)
779 num_heads++;
780 }
781 for (i = 0; i < rdev->num_crtc; i += 2) {
782 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
783 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
784 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
785 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
786 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
787 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
788 }
bcc1c2a1
AD		 789}
790
791static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
792{
793 unsigned i;
794 u32 tmp;
795
796 for (i = 0; i < rdev->usec_timeout; i++) {
797 /* read MC_STATUS */
798 tmp = RREG32(SRBM_STATUS) & 0x1F00;
799 if (!tmp)
800 return 0;
801 udelay(1);
802 }
803 return -1;
804}
805
806/*
807 * GART
808 */
0fcdb61e
AD		 809void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
810{
811 unsigned i;
812 u32 tmp;
813
814 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
815 for (i = 0; i < rdev->usec_timeout; i++) {
816 /* read MC_STATUS */
817 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
818 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
819 if (tmp == 2) {
820 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
821 return;
822 }
823 if (tmp) {
824 return;
825 }
826 udelay(1);
827 }
828}
829
bcc1c2a1
AD		 830int evergreen_pcie_gart_enable(struct radeon_device *rdev)
831{
832 u32 tmp;
0fcdb61e 833 int r;
bcc1c2a1
AD		 834
835 if (rdev->gart.table.vram.robj == NULL) {
836 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
837 return -EINVAL;
838 }
839 r = radeon_gart_table_vram_pin(rdev);
840 if (r)
841 return r;
82568565 842 radeon_gart_restore(rdev);
bcc1c2a1
AD		 843 /* Setup L2 cache */
844 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
845 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
846 EFFECTIVE_L2_QUEUE_SIZE(7));
847 WREG32(VM_L2_CNTL2, 0);
848 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
849 /* Setup TLB control */
850 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
851 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
852 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
853 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
854 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
855 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
856 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
857 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
858 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
859 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
860 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
861 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
862 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
863 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
864 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
865 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
866 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
867 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 868 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 869
0fcdb61e 870 evergreen_pcie_gart_tlb_flush(rdev);
bcc1c2a1
AD		 871 rdev->gart.ready = true;
872 return 0;
873}
874
875void evergreen_pcie_gart_disable(struct radeon_device *rdev)
876{
877 u32 tmp;
0fcdb61e 878 int r;
bcc1c2a1
AD		 879
880 /* Disable all tables */
0fcdb61e
AD		 881 WREG32(VM_CONTEXT0_CNTL, 0);
882 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 883
884 /* Setup L2 cache */
885 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
886 EFFECTIVE_L2_QUEUE_SIZE(7));
887 WREG32(VM_L2_CNTL2, 0);
888 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
889 /* Setup TLB control */
890 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
891 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
892 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
893 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
894 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
895 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
896 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
897 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
898 if (rdev->gart.table.vram.robj) {
899 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
900 if (likely(r == 0)) {
901 radeon_bo_kunmap(rdev->gart.table.vram.robj);
902 radeon_bo_unpin(rdev->gart.table.vram.robj);
903 radeon_bo_unreserve(rdev->gart.table.vram.robj);
904 }
905 }
906}
907
908void evergreen_pcie_gart_fini(struct radeon_device *rdev)
909{
910 evergreen_pcie_gart_disable(rdev);
911 radeon_gart_table_vram_free(rdev);
912 radeon_gart_fini(rdev);
913}
914
915
916void evergreen_agp_enable(struct radeon_device *rdev)
917{
918 u32 tmp;
bcc1c2a1
AD		 919
920 /* Setup L2 cache */
921 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
922 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
923 EFFECTIVE_L2_QUEUE_SIZE(7));
924 WREG32(VM_L2_CNTL2, 0);
925 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
926 /* Setup TLB control */
927 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
928 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
929 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
930 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
931 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
932 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
933 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
934 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
935 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
936 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
937 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 938 WREG32(VM_CONTEXT0_CNTL, 0);
939 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 940}
941
942static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
943{
944 save->vga_control[0] = RREG32(D1VGA_CONTROL);
945 save->vga_control[1] = RREG32(D2VGA_CONTROL);
946 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
947 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
948 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
949 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
950 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
951 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
952 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
953 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
18007401
AD		 954 if (!(rdev->flags & RADEON_IS_IGP)) {
955 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
956 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
957 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
958 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
959 }
bcc1c2a1
AD		 960
961 /* Stop all video */
962 WREG32(VGA_RENDER_CONTROL, 0);
963 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
964 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
18007401
AD		 965 if (!(rdev->flags & RADEON_IS_IGP)) {
966 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
967 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
968 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
969 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
970 }
bcc1c2a1
AD		 971 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
972 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 973 if (!(rdev->flags & RADEON_IS_IGP)) {
974 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
975 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
976 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
977 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
978 }
bcc1c2a1
AD		 979 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
980 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 981 if (!(rdev->flags & RADEON_IS_IGP)) {
982 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
983 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
984 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
985 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
986 }
bcc1c2a1
AD		 987
988 WREG32(D1VGA_CONTROL, 0);
989 WREG32(D2VGA_CONTROL, 0);
990 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
991 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
992 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
993 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
994}
995
996static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
997{
998 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
999 upper_32_bits(rdev->mc.vram_start));
1000 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1001 upper_32_bits(rdev->mc.vram_start));
1002 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1003 (u32)rdev->mc.vram_start);
1004 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1005 (u32)rdev->mc.vram_start);
1006
1007 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1008 upper_32_bits(rdev->mc.vram_start));
1009 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1010 upper_32_bits(rdev->mc.vram_start));
1011 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1012 (u32)rdev->mc.vram_start);
1013 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1014 (u32)rdev->mc.vram_start);
1015
18007401
AD		 1016 if (!(rdev->flags & RADEON_IS_IGP)) {
1017 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1018 upper_32_bits(rdev->mc.vram_start));
1019 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1020 upper_32_bits(rdev->mc.vram_start));
1021 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1022 (u32)rdev->mc.vram_start);
1023 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1024 (u32)rdev->mc.vram_start);
1025
1026 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1027 upper_32_bits(rdev->mc.vram_start));
1028 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1029 upper_32_bits(rdev->mc.vram_start));
1030 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1031 (u32)rdev->mc.vram_start);
1032 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1033 (u32)rdev->mc.vram_start);
1034
1035 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1036 upper_32_bits(rdev->mc.vram_start));
1037 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1038 upper_32_bits(rdev->mc.vram_start));
1039 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1040 (u32)rdev->mc.vram_start);
1041 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1042 (u32)rdev->mc.vram_start);
1043
1044 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1045 upper_32_bits(rdev->mc.vram_start));
1046 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1047 upper_32_bits(rdev->mc.vram_start));
1048 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1049 (u32)rdev->mc.vram_start);
1050 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1051 (u32)rdev->mc.vram_start);
1052 }
bcc1c2a1
AD		 1053
1054 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1055 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1056 /* Unlock host access */
1057 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1058 mdelay(1);
1059 /* Restore video state */
1060 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1061 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1062 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1063 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1064 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1065 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1066 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1067 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
18007401
AD		 1068 if (!(rdev->flags & RADEON_IS_IGP)) {
1069 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1070 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1071 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1072 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1073 }
bcc1c2a1
AD		 1074 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1075 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
18007401
AD		 1076 if (!(rdev->flags & RADEON_IS_IGP)) {
1077 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1078 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1079 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1080 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1081 }
bcc1c2a1
AD		 1082 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1083 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 1084 if (!(rdev->flags & RADEON_IS_IGP)) {
1085 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1086 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1087 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1088 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1089 }
bcc1c2a1
AD		 1090 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1091}
1092
1093static void evergreen_mc_program(struct radeon_device *rdev)
1094{
1095 struct evergreen_mc_save save;
1096 u32 tmp;
1097 int i, j;
1098
1099 /* Initialize HDP */
1100 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1101 WREG32((0x2c14 + j), 0x00000000);
1102 WREG32((0x2c18 + j), 0x00000000);
1103 WREG32((0x2c1c + j), 0x00000000);
1104 WREG32((0x2c20 + j), 0x00000000);
1105 WREG32((0x2c24 + j), 0x00000000);
1106 }
1107 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1108
1109 evergreen_mc_stop(rdev, &save);
1110 if (evergreen_mc_wait_for_idle(rdev)) {
1111 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1112 }
1113 /* Lockout access through VGA aperture*/
1114 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1115 /* Update configuration */
1116 if (rdev->flags & RADEON_IS_AGP) {
1117 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1118 /* VRAM before AGP */
1119 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1120 rdev->mc.vram_start >> 12);
1121 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1122 rdev->mc.gtt_end >> 12);
1123 } else {
1124 /* VRAM after AGP */
1125 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1126 rdev->mc.gtt_start >> 12);
1127 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1128 rdev->mc.vram_end >> 12);
1129 }
1130 } else {
1131 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1132 rdev->mc.vram_start >> 12);
1133 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1134 rdev->mc.vram_end >> 12);
1135 }
1136 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1137 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1138 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1139 WREG32(MC_VM_FB_LOCATION, tmp);
1140 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1141 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1142 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1143 if (rdev->flags & RADEON_IS_AGP) {
1144 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1145 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1146 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1147 } else {
1148 WREG32(MC_VM_AGP_BASE, 0);
1149 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1150 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1151 }
1152 if (evergreen_mc_wait_for_idle(rdev)) {
1153 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1154 }
1155 evergreen_mc_resume(rdev, &save);
1156 /* we need to own VRAM, so turn off the VGA renderer here
1157 * to stop it overwriting our objects */
1158 rv515_vga_render_disable(rdev);
1159}
1160
bcc1c2a1
AD		 1161/*
1162 * CP.
1163 */
bcc1c2a1
AD		 1164
1165static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1166{
fe251e2f
AD		 1167 const __be32 *fw_data;
1168 int i;
1169
1170 if (!rdev->me_fw || !rdev->pfp_fw)
1171 return -EINVAL;
bcc1c2a1 1172
fe251e2f
AD		 1173 r700_cp_stop(rdev);
1174 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1175
1176 fw_data = (const __be32 *)rdev->pfp_fw->data;
1177 WREG32(CP_PFP_UCODE_ADDR, 0);
1178 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1179 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1180 WREG32(CP_PFP_UCODE_ADDR, 0);
1181
1182 fw_data = (const __be32 *)rdev->me_fw->data;
1183 WREG32(CP_ME_RAM_WADDR, 0);
1184 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1185 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1186
1187 WREG32(CP_PFP_UCODE_ADDR, 0);
1188 WREG32(CP_ME_RAM_WADDR, 0);
1189 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1190 return 0;
1191}
1192
7e7b41d2
AD		 1193static int evergreen_cp_start(struct radeon_device *rdev)
1194{
2281a378 1195 int r, i;
7e7b41d2
AD		 1196 uint32_t cp_me;
1197
1198 r = radeon_ring_lock(rdev, 7);
1199 if (r) {
1200 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1201 return r;
1202 }
1203 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1204 radeon_ring_write(rdev, 0x1);
1205 radeon_ring_write(rdev, 0x0);
1206 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1207 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1208 radeon_ring_write(rdev, 0);
1209 radeon_ring_write(rdev, 0);
1210 radeon_ring_unlock_commit(rdev);
1211
1212 cp_me = 0xff;
1213 WREG32(CP_ME_CNTL, cp_me);
1214
2281a378 1215 r = radeon_ring_lock(rdev, evergreen_default_size + 15);
7e7b41d2
AD		 1216 if (r) {
1217 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1218 return r;
1219 }
2281a378
AD		 1220
1221 /* setup clear context state */
1222 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1223 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1224
1225 for (i = 0; i < evergreen_default_size; i++)
1226 radeon_ring_write(rdev, evergreen_default_state[i]);
1227
1228 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1229 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1230
1231 /* set clear context state */
1232 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1233 radeon_ring_write(rdev, 0);
1234
1235 /* SQ_VTX_BASE_VTX_LOC */
1236 radeon_ring_write(rdev, 0xc0026f00);
1237 radeon_ring_write(rdev, 0x00000000);
1238 radeon_ring_write(rdev, 0x00000000);
1239 radeon_ring_write(rdev, 0x00000000);
1240
1241 /* Clear consts */
1242 radeon_ring_write(rdev, 0xc0036f00);
1243 radeon_ring_write(rdev, 0x00000bc4);
1244 radeon_ring_write(rdev, 0xffffffff);
1245 radeon_ring_write(rdev, 0xffffffff);
1246 radeon_ring_write(rdev, 0xffffffff);
1247
7e7b41d2
AD		 1248 radeon_ring_unlock_commit(rdev);
1249
1250 return 0;
1251}
1252
fe251e2f
AD		 1253int evergreen_cp_resume(struct radeon_device *rdev)
1254{
1255 u32 tmp;
1256 u32 rb_bufsz;
1257 int r;
1258
1259 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1260 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1261 SOFT_RESET_PA |
1262 SOFT_RESET_SH |
1263 SOFT_RESET_VGT |
1264 SOFT_RESET_SX));
1265 RREG32(GRBM_SOFT_RESET);
1266 mdelay(15);
1267 WREG32(GRBM_SOFT_RESET, 0);
1268 RREG32(GRBM_SOFT_RESET);
1269
1270 /* Set ring buffer size */
1271 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 1272 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1273#ifdef __BIG_ENDIAN
1274 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1275#endif
fe251e2f
AD		 1276 WREG32(CP_RB_CNTL, tmp);
1277 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1278
1279 /* Set the write pointer delay */
1280 WREG32(CP_RB_WPTR_DELAY, 0);
1281
1282 /* Initialize the ring buffer's read and write pointers */
1283 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1284 WREG32(CP_RB_RPTR_WR, 0);
1285 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 1286
1287 /* set the wb address wether it's enabled or not */
1288 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1289 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1290 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1291
1292 if (rdev->wb.enabled)
1293 WREG32(SCRATCH_UMSK, 0xff);
1294 else {
1295 tmp |= RB_NO_UPDATE;
1296 WREG32(SCRATCH_UMSK, 0);
1297 }
1298
fe251e2f
AD		 1299 mdelay(1);
1300 WREG32(CP_RB_CNTL, tmp);
1301
1302 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1303 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1304
1305 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1306 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1307
7e7b41d2 1308 evergreen_cp_start(rdev);
fe251e2f
AD		 1309 rdev->cp.ready = true;
1310 r = radeon_ring_test(rdev);
1311 if (r) {
1312 rdev->cp.ready = false;
1313 return r;
1314 }
1315 return 0;
1316}
bcc1c2a1
AD		 1317
1318/*
1319 * Core functions
1320 */
32fcdbf4
AD		 1321static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1322 u32 num_tile_pipes,
bcc1c2a1
AD		 1323 u32 num_backends,
1324 u32 backend_disable_mask)
1325{
1326 u32 backend_map = 0;
32fcdbf4
AD		 1327 u32 enabled_backends_mask = 0;
1328 u32 enabled_backends_count = 0;
1329 u32 cur_pipe;
1330 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1331 u32 cur_backend = 0;
1332 u32 i;
1333 bool force_no_swizzle;
1334
1335 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1336 num_tile_pipes = EVERGREEN_MAX_PIPES;
1337 if (num_tile_pipes < 1)
1338 num_tile_pipes = 1;
1339 if (num_backends > EVERGREEN_MAX_BACKENDS)
1340 num_backends = EVERGREEN_MAX_BACKENDS;
1341 if (num_backends < 1)
1342 num_backends = 1;
1343
1344 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1345 if (((backend_disable_mask >> i) & 1) == 0) {
1346 enabled_backends_mask |= (1 << i);
1347 ++enabled_backends_count;
1348 }
1349 if (enabled_backends_count == num_backends)
1350 break;
1351 }
1352
1353 if (enabled_backends_count == 0) {
1354 enabled_backends_mask = 1;
1355 enabled_backends_count = 1;
1356 }
1357
1358 if (enabled_backends_count != num_backends)
1359 num_backends = enabled_backends_count;
1360
1361 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1362 switch (rdev->family) {
1363 case CHIP_CEDAR:
1364 case CHIP_REDWOOD:
d5e455e4 1365 case CHIP_PALM:
32fcdbf4
AD		 1366 force_no_swizzle = false;
1367 break;
1368 case CHIP_CYPRESS:
1369 case CHIP_HEMLOCK:
1370 case CHIP_JUNIPER:
1371 default:
1372 force_no_swizzle = true;
1373 break;
1374 }
1375 if (force_no_swizzle) {
1376 bool last_backend_enabled = false;
1377
1378 force_no_swizzle = false;
1379 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1380 if (((enabled_backends_mask >> i) & 1) == 1) {
1381 if (last_backend_enabled)
1382 force_no_swizzle = true;
1383 last_backend_enabled = true;
1384 } else
1385 last_backend_enabled = false;
1386 }
1387 }
1388
1389 switch (num_tile_pipes) {
1390 case 1:
1391 case 3:
1392 case 5:
1393 case 7:
1394 DRM_ERROR("odd number of pipes!\n");
1395 break;
1396 case 2:
1397 swizzle_pipe[0] = 0;
1398 swizzle_pipe[1] = 1;
1399 break;
1400 case 4:
1401 if (force_no_swizzle) {
1402 swizzle_pipe[0] = 0;
1403 swizzle_pipe[1] = 1;
1404 swizzle_pipe[2] = 2;
1405 swizzle_pipe[3] = 3;
1406 } else {
1407 swizzle_pipe[0] = 0;
1408 swizzle_pipe[1] = 2;
1409 swizzle_pipe[2] = 1;
1410 swizzle_pipe[3] = 3;
1411 }
1412 break;
1413 case 6:
1414 if (force_no_swizzle) {
1415 swizzle_pipe[0] = 0;
1416 swizzle_pipe[1] = 1;
1417 swizzle_pipe[2] = 2;
1418 swizzle_pipe[3] = 3;
1419 swizzle_pipe[4] = 4;
1420 swizzle_pipe[5] = 5;
1421 } else {
1422 swizzle_pipe[0] = 0;
1423 swizzle_pipe[1] = 2;
1424 swizzle_pipe[2] = 4;
1425 swizzle_pipe[3] = 1;
1426 swizzle_pipe[4] = 3;
1427 swizzle_pipe[5] = 5;
1428 }
1429 break;
1430 case 8:
1431 if (force_no_swizzle) {
1432 swizzle_pipe[0] = 0;
1433 swizzle_pipe[1] = 1;
1434 swizzle_pipe[2] = 2;
1435 swizzle_pipe[3] = 3;
1436 swizzle_pipe[4] = 4;
1437 swizzle_pipe[5] = 5;
1438 swizzle_pipe[6] = 6;
1439 swizzle_pipe[7] = 7;
1440 } else {
1441 swizzle_pipe[0] = 0;
1442 swizzle_pipe[1] = 2;
1443 swizzle_pipe[2] = 4;
1444 swizzle_pipe[3] = 6;
1445 swizzle_pipe[4] = 1;
1446 swizzle_pipe[5] = 3;
1447 swizzle_pipe[6] = 5;
1448 swizzle_pipe[7] = 7;
1449 }
1450 break;
1451 }
1452
1453 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1454 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1455 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1456
1457 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1458
1459 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1460 }
bcc1c2a1
AD		 1461
1462 return backend_map;
1463}
bcc1c2a1 1464
9535ab73
AD		 1465static void evergreen_program_channel_remap(struct radeon_device *rdev)
1466{
1467 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1468
1469 tmp = RREG32(MC_SHARED_CHMAP);
1470 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1471 case 0:
1472 case 1:
1473 case 2:
1474 case 3:
1475 default:
1476 /* default mapping */
1477 mc_shared_chremap = 0x00fac688;
1478 break;
1479 }
1480
1481 switch (rdev->family) {
1482 case CHIP_HEMLOCK:
1483 case CHIP_CYPRESS:
1484 tcp_chan_steer_lo = 0x54763210;
1485 tcp_chan_steer_hi = 0x0000ba98;
1486 break;
1487 case CHIP_JUNIPER:
1488 case CHIP_REDWOOD:
1489 case CHIP_CEDAR:
d5e455e4 1490 case CHIP_PALM:
9535ab73
AD		 1491 default:
1492 tcp_chan_steer_lo = 0x76543210;
1493 tcp_chan_steer_hi = 0x0000ba98;
1494 break;
1495 }
1496
1497 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1498 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1499 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1500}
1501
bcc1c2a1
AD		 1502static void evergreen_gpu_init(struct radeon_device *rdev)
1503{
32fcdbf4
AD		 1504 u32 cc_rb_backend_disable = 0;
1505 u32 cc_gc_shader_pipe_config;
1506 u32 gb_addr_config = 0;
1507 u32 mc_shared_chmap, mc_arb_ramcfg;
1508 u32 gb_backend_map;
1509 u32 grbm_gfx_index;
1510 u32 sx_debug_1;
1511 u32 smx_dc_ctl0;
1512 u32 sq_config;
1513 u32 sq_lds_resource_mgmt;
1514 u32 sq_gpr_resource_mgmt_1;
1515 u32 sq_gpr_resource_mgmt_2;
1516 u32 sq_gpr_resource_mgmt_3;
1517 u32 sq_thread_resource_mgmt;
1518 u32 sq_thread_resource_mgmt_2;
1519 u32 sq_stack_resource_mgmt_1;
1520 u32 sq_stack_resource_mgmt_2;
1521 u32 sq_stack_resource_mgmt_3;
1522 u32 vgt_cache_invalidation;
1523 u32 hdp_host_path_cntl;
1524 int i, j, num_shader_engines, ps_thread_count;
1525
1526 switch (rdev->family) {
1527 case CHIP_CYPRESS:
1528 case CHIP_HEMLOCK:
1529 rdev->config.evergreen.num_ses = 2;
1530 rdev->config.evergreen.max_pipes = 4;
1531 rdev->config.evergreen.max_tile_pipes = 8;
1532 rdev->config.evergreen.max_simds = 10;
1533 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1534 rdev->config.evergreen.max_gprs = 256;
1535 rdev->config.evergreen.max_threads = 248;
1536 rdev->config.evergreen.max_gs_threads = 32;
1537 rdev->config.evergreen.max_stack_entries = 512;
1538 rdev->config.evergreen.sx_num_of_sets = 4;
1539 rdev->config.evergreen.sx_max_export_size = 256;
1540 rdev->config.evergreen.sx_max_export_pos_size = 64;
1541 rdev->config.evergreen.sx_max_export_smx_size = 192;
1542 rdev->config.evergreen.max_hw_contexts = 8;
1543 rdev->config.evergreen.sq_num_cf_insts = 2;
1544
1545 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1546 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1547 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1548 break;
1549 case CHIP_JUNIPER:
1550 rdev->config.evergreen.num_ses = 1;
1551 rdev->config.evergreen.max_pipes = 4;
1552 rdev->config.evergreen.max_tile_pipes = 4;
1553 rdev->config.evergreen.max_simds = 10;
1554 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1555 rdev->config.evergreen.max_gprs = 256;
1556 rdev->config.evergreen.max_threads = 248;
1557 rdev->config.evergreen.max_gs_threads = 32;
1558 rdev->config.evergreen.max_stack_entries = 512;
1559 rdev->config.evergreen.sx_num_of_sets = 4;
1560 rdev->config.evergreen.sx_max_export_size = 256;
1561 rdev->config.evergreen.sx_max_export_pos_size = 64;
1562 rdev->config.evergreen.sx_max_export_smx_size = 192;
1563 rdev->config.evergreen.max_hw_contexts = 8;
1564 rdev->config.evergreen.sq_num_cf_insts = 2;
1565
1566 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1567 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1568 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1569 break;
1570 case CHIP_REDWOOD:
1571 rdev->config.evergreen.num_ses = 1;
1572 rdev->config.evergreen.max_pipes = 4;
1573 rdev->config.evergreen.max_tile_pipes = 4;
1574 rdev->config.evergreen.max_simds = 5;
1575 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1576 rdev->config.evergreen.max_gprs = 256;
1577 rdev->config.evergreen.max_threads = 248;
1578 rdev->config.evergreen.max_gs_threads = 32;
1579 rdev->config.evergreen.max_stack_entries = 256;
1580 rdev->config.evergreen.sx_num_of_sets = 4;
1581 rdev->config.evergreen.sx_max_export_size = 256;
1582 rdev->config.evergreen.sx_max_export_pos_size = 64;
1583 rdev->config.evergreen.sx_max_export_smx_size = 192;
1584 rdev->config.evergreen.max_hw_contexts = 8;
1585 rdev->config.evergreen.sq_num_cf_insts = 2;
1586
1587 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1588 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1589 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1590 break;
1591 case CHIP_CEDAR:
1592 default:
1593 rdev->config.evergreen.num_ses = 1;
1594 rdev->config.evergreen.max_pipes = 2;
1595 rdev->config.evergreen.max_tile_pipes = 2;
1596 rdev->config.evergreen.max_simds = 2;
1597 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1598 rdev->config.evergreen.max_gprs = 256;
1599 rdev->config.evergreen.max_threads = 192;
1600 rdev->config.evergreen.max_gs_threads = 16;
1601 rdev->config.evergreen.max_stack_entries = 256;
1602 rdev->config.evergreen.sx_num_of_sets = 4;
1603 rdev->config.evergreen.sx_max_export_size = 128;
1604 rdev->config.evergreen.sx_max_export_pos_size = 32;
1605 rdev->config.evergreen.sx_max_export_smx_size = 96;
1606 rdev->config.evergreen.max_hw_contexts = 4;
1607 rdev->config.evergreen.sq_num_cf_insts = 1;
1608
d5e455e4
AD		 1609 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1610 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1611 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1612 break;
1613 case CHIP_PALM:
1614 rdev->config.evergreen.num_ses = 1;
1615 rdev->config.evergreen.max_pipes = 2;
1616 rdev->config.evergreen.max_tile_pipes = 2;
1617 rdev->config.evergreen.max_simds = 2;
1618 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1619 rdev->config.evergreen.max_gprs = 256;
1620 rdev->config.evergreen.max_threads = 192;
1621 rdev->config.evergreen.max_gs_threads = 16;
1622 rdev->config.evergreen.max_stack_entries = 256;
1623 rdev->config.evergreen.sx_num_of_sets = 4;
1624 rdev->config.evergreen.sx_max_export_size = 128;
1625 rdev->config.evergreen.sx_max_export_pos_size = 32;
1626 rdev->config.evergreen.sx_max_export_smx_size = 96;
1627 rdev->config.evergreen.max_hw_contexts = 4;
1628 rdev->config.evergreen.sq_num_cf_insts = 1;
1629
32fcdbf4
AD		 1630 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1631 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1632 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1633 break;
1634 }
1635
1636 /* Initialize HDP */
1637 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1638 WREG32((0x2c14 + j), 0x00000000);
1639 WREG32((0x2c18 + j), 0x00000000);
1640 WREG32((0x2c1c + j), 0x00000000);
1641 WREG32((0x2c20 + j), 0x00000000);
1642 WREG32((0x2c24 + j), 0x00000000);
1643 }
1644
1645 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1646
1647 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1648
1649 cc_gc_shader_pipe_config |=
1650 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1651 & EVERGREEN_MAX_PIPES_MASK);
1652 cc_gc_shader_pipe_config |=
1653 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1654 & EVERGREEN_MAX_SIMDS_MASK);
1655
1656 cc_rb_backend_disable =
1657 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1658 & EVERGREEN_MAX_BACKENDS_MASK);
1659
1660
1661 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1662 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1663
1664 switch (rdev->config.evergreen.max_tile_pipes) {
1665 case 1:
1666 default:
1667 gb_addr_config |= NUM_PIPES(0);
1668 break;
1669 case 2:
1670 gb_addr_config |= NUM_PIPES(1);
1671 break;
1672 case 4:
1673 gb_addr_config |= NUM_PIPES(2);
1674 break;
1675 case 8:
1676 gb_addr_config |= NUM_PIPES(3);
1677 break;
1678 }
1679
1680 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1681 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1682 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1683 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1684 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1685 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1686
1687 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1688 gb_addr_config |= ROW_SIZE(2);
1689 else
1690 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1691
1692 if (rdev->ddev->pdev->device == 0x689e) {
1693 u32 efuse_straps_4;
1694 u32 efuse_straps_3;
1695 u8 efuse_box_bit_131_124;
1696
1697 WREG32(RCU_IND_INDEX, 0x204);
1698 efuse_straps_4 = RREG32(RCU_IND_DATA);
1699 WREG32(RCU_IND_INDEX, 0x203);
1700 efuse_straps_3 = RREG32(RCU_IND_DATA);
1701 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1702
1703 switch(efuse_box_bit_131_124) {
1704 case 0x00:
1705 gb_backend_map = 0x76543210;
1706 break;
1707 case 0x55:
1708 gb_backend_map = 0x77553311;
1709 break;
1710 case 0x56:
1711 gb_backend_map = 0x77553300;
1712 break;
1713 case 0x59:
1714 gb_backend_map = 0x77552211;
1715 break;
1716 case 0x66:
1717 gb_backend_map = 0x77443300;
1718 break;
1719 case 0x99:
1720 gb_backend_map = 0x66552211;
1721 break;
1722 case 0x5a:
1723 gb_backend_map = 0x77552200;
1724 break;
1725 case 0xaa:
1726 gb_backend_map = 0x66442200;
1727 break;
1728 case 0x95:
1729 gb_backend_map = 0x66553311;
1730 break;
1731 default:
1732 DRM_ERROR("bad backend map, using default\n");
1733 gb_backend_map =
1734 evergreen_get_tile_pipe_to_backend_map(rdev,
1735 rdev->config.evergreen.max_tile_pipes,
1736 rdev->config.evergreen.max_backends,
1737 ((EVERGREEN_MAX_BACKENDS_MASK <<
1738 rdev->config.evergreen.max_backends) &
1739 EVERGREEN_MAX_BACKENDS_MASK));
1740 break;
1741 }
1742 } else if (rdev->ddev->pdev->device == 0x68b9) {
1743 u32 efuse_straps_3;
1744 u8 efuse_box_bit_127_124;
1745
1746 WREG32(RCU_IND_INDEX, 0x203);
1747 efuse_straps_3 = RREG32(RCU_IND_DATA);
d31dba58 1748 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
32fcdbf4
AD		 1749
1750 switch(efuse_box_bit_127_124) {
1751 case 0x0:
1752 gb_backend_map = 0x00003210;
1753 break;
1754 case 0x5:
1755 case 0x6:
1756 case 0x9:
1757 case 0xa:
1758 gb_backend_map = 0x00003311;
1759 break;
1760 default:
1761 DRM_ERROR("bad backend map, using default\n");
1762 gb_backend_map =
1763 evergreen_get_tile_pipe_to_backend_map(rdev,
1764 rdev->config.evergreen.max_tile_pipes,
1765 rdev->config.evergreen.max_backends,
1766 ((EVERGREEN_MAX_BACKENDS_MASK <<
1767 rdev->config.evergreen.max_backends) &
1768 EVERGREEN_MAX_BACKENDS_MASK));
1769 break;
1770 }
b741be82
AD		 1771 } else {
1772 switch (rdev->family) {
1773 case CHIP_CYPRESS:
1774 case CHIP_HEMLOCK:
1775 gb_backend_map = 0x66442200;
1776 break;
1777 case CHIP_JUNIPER:
1778 gb_backend_map = 0x00006420;
1779 break;
1780 default:
1781 gb_backend_map =
1782 evergreen_get_tile_pipe_to_backend_map(rdev,
1783 rdev->config.evergreen.max_tile_pipes,
1784 rdev->config.evergreen.max_backends,
1785 ((EVERGREEN_MAX_BACKENDS_MASK <<
1786 rdev->config.evergreen.max_backends) &
1787 EVERGREEN_MAX_BACKENDS_MASK));
1788 }
1789 }
32fcdbf4 1790
1aa52bd3
AD		 1791 /* setup tiling info dword. gb_addr_config is not adequate since it does
1792 * not have bank info, so create a custom tiling dword.
1793 * bits 3:0 num_pipes
1794 * bits 7:4 num_banks
1795 * bits 11:8 group_size
1796 * bits 15:12 row_size
1797 */
1798 rdev->config.evergreen.tile_config = 0;
1799 switch (rdev->config.evergreen.max_tile_pipes) {
1800 case 1:
1801 default:
1802 rdev->config.evergreen.tile_config |= (0 << 0);
1803 break;
1804 case 2:
1805 rdev->config.evergreen.tile_config |= (1 << 0);
1806 break;
1807 case 4:
1808 rdev->config.evergreen.tile_config |= (2 << 0);
1809 break;
1810 case 8:
1811 rdev->config.evergreen.tile_config |= (3 << 0);
1812 break;
1813 }
1814 rdev->config.evergreen.tile_config |=
1815 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1816 rdev->config.evergreen.tile_config |=
1817 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1818 rdev->config.evergreen.tile_config |=
1819 ((gb_addr_config & 0x30000000) >> 28) << 12;
1820
32fcdbf4
AD		 1821 WREG32(GB_BACKEND_MAP, gb_backend_map);
1822 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1823 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1824 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1825
9535ab73
AD		 1826 evergreen_program_channel_remap(rdev);
1827
32fcdbf4
AD		 1828 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1829 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1830
1831 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1832 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1833 u32 sp = cc_gc_shader_pipe_config;
1834 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1835
1836 if (i == num_shader_engines) {
1837 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1838 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1839 }
1840
1841 WREG32(GRBM_GFX_INDEX, gfx);
1842 WREG32(RLC_GFX_INDEX, gfx);
1843
1844 WREG32(CC_RB_BACKEND_DISABLE, rb);
1845 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1846 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1847 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1848 }
1849
1850 grbm_gfx_index |= SE_BROADCAST_WRITES;
1851 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1852 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1853
1854 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1855 WREG32(CGTS_TCC_DISABLE, 0);
1856 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1857 WREG32(CGTS_USER_TCC_DISABLE, 0);
1858
1859 /* set HW defaults for 3D engine */
1860 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1861 ROQ_IB2_START(0x2b)));
1862
1863 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1864
1865 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1866 SYNC_GRADIENT |
1867 SYNC_WALKER |
1868 SYNC_ALIGNER));
1869
1870 sx_debug_1 = RREG32(SX_DEBUG_1);
1871 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1872 WREG32(SX_DEBUG_1, sx_debug_1);
1873
1874
1875 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1876 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1877 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1878 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1879
1880 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1881 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1882 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1883
1884 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1885 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1886 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1887
1888 WREG32(VGT_NUM_INSTANCES, 1);
1889 WREG32(SPI_CONFIG_CNTL, 0);
1890 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1891 WREG32(CP_PERFMON_CNTL, 0);
1892
1893 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1894 FETCH_FIFO_HIWATER(0x4) |
1895 DONE_FIFO_HIWATER(0xe0) |
1896 ALU_UPDATE_FIFO_HIWATER(0x8)));
1897
1898 sq_config = RREG32(SQ_CONFIG);
1899 sq_config &= ~(PS_PRIO(3) |
1900 VS_PRIO(3) |
1901 GS_PRIO(3) |
1902 ES_PRIO(3));
1903 sq_config |= (VC_ENABLE |
1904 EXPORT_SRC_C |
1905 PS_PRIO(0) |
1906 VS_PRIO(1) |
1907 GS_PRIO(2) |
1908 ES_PRIO(3));
1909
d5e455e4
AD		 1910 switch (rdev->family) {
1911 case CHIP_CEDAR:
1912 case CHIP_PALM:
32fcdbf4
AD		 1913 /* no vertex cache */
1914 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 1915 break;
1916 default:
1917 break;
1918 }
32fcdbf4
AD		 1919
1920 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1921
1922 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1923 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1924 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1925 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1926 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1927 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1928 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1929
d5e455e4
AD		 1930 switch (rdev->family) {
1931 case CHIP_CEDAR:
1932 case CHIP_PALM:
32fcdbf4 1933 ps_thread_count = 96;
d5e455e4
AD		 1934 break;
1935 default:
32fcdbf4 1936 ps_thread_count = 128;
d5e455e4
AD		 1937 break;
1938 }
32fcdbf4
AD		 1939
1940 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 1941 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1942 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1943 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1944 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1945 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 1946
1947 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1948 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1949 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1950 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1951 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1952 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1953
1954 WREG32(SQ_CONFIG, sq_config);
1955 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1956 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1957 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1958 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1959 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1960 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1961 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1962 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1963 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1964 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1965
1966 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1967 FORCE_EOV_MAX_REZ_CNT(255)));
1968
d5e455e4
AD		 1969 switch (rdev->family) {
1970 case CHIP_CEDAR:
1971 case CHIP_PALM:
32fcdbf4 1972 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 1973 break;
1974 default:
32fcdbf4 1975 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 1976 break;
1977 }
32fcdbf4
AD		 1978 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1979 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1980
1981 WREG32(VGT_GS_VERTEX_REUSE, 16);
1982 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1983
60a4a3e0
AD		 1984 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1985 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1986
32fcdbf4
AD		 1987 WREG32(CB_PERF_CTR0_SEL_0, 0);
1988 WREG32(CB_PERF_CTR0_SEL_1, 0);
1989 WREG32(CB_PERF_CTR1_SEL_0, 0);
1990 WREG32(CB_PERF_CTR1_SEL_1, 0);
1991 WREG32(CB_PERF_CTR2_SEL_0, 0);
1992 WREG32(CB_PERF_CTR2_SEL_1, 0);
1993 WREG32(CB_PERF_CTR3_SEL_0, 0);
1994 WREG32(CB_PERF_CTR3_SEL_1, 0);
1995
60a4a3e0
AD		 1996 /* clear render buffer base addresses */
1997 WREG32(CB_COLOR0_BASE, 0);
1998 WREG32(CB_COLOR1_BASE, 0);
1999 WREG32(CB_COLOR2_BASE, 0);
2000 WREG32(CB_COLOR3_BASE, 0);
2001 WREG32(CB_COLOR4_BASE, 0);
2002 WREG32(CB_COLOR5_BASE, 0);
2003 WREG32(CB_COLOR6_BASE, 0);
2004 WREG32(CB_COLOR7_BASE, 0);
2005 WREG32(CB_COLOR8_BASE, 0);
2006 WREG32(CB_COLOR9_BASE, 0);
2007 WREG32(CB_COLOR10_BASE, 0);
2008 WREG32(CB_COLOR11_BASE, 0);
2009
2010 /* set the shader const cache sizes to 0 */
2011 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2012 WREG32(i, 0);
2013 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2014 WREG32(i, 0);
2015
32fcdbf4
AD		 2016 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2017 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2018
2019 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2020
2021 udelay(50);
2022
bcc1c2a1
AD		 2023}
2024
2025int evergreen_mc_init(struct radeon_device *rdev)
2026{
bcc1c2a1
AD		 2027 u32 tmp;
2028 int chansize, numchan;
bcc1c2a1
AD		 2029
2030 /* Get VRAM informations */
2031 rdev->mc.vram_is_ddr = true;
2032 tmp = RREG32(MC_ARB_RAMCFG);
2033 if (tmp & CHANSIZE_OVERRIDE) {
2034 chansize = 16;
2035 } else if (tmp & CHANSIZE_MASK) {
2036 chansize = 64;
2037 } else {
2038 chansize = 32;
2039 }
2040 tmp = RREG32(MC_SHARED_CHMAP);
2041 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2042 case 0:
2043 default:
2044 numchan = 1;
2045 break;
2046 case 1:
2047 numchan = 2;
2048 break;
2049 case 2:
2050 numchan = 4;
2051 break;
2052 case 3:
2053 numchan = 8;
2054 break;
2055 }
2056 rdev->mc.vram_width = numchan * chansize;
2057 /* Could aper size report 0 ? */
01d73a69
JC		 2058 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2059 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2060 /* Setup GPU memory space */
6eb18f8b
AD		 2061 if (rdev->flags & RADEON_IS_IGP) {
2062 /* size in bytes on fusion */
2063 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2064 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2065 } else {
2066 /* size in MB on evergreen */
2067 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2068 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2069 }
51e5fcd3 2070 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 2071 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
0ef0c1f7 2072 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2073 radeon_update_bandwidth_info(rdev);
2074
bcc1c2a1
AD		 2075 return 0;
2076}
d594e46a 2077
225758d8
JG		 2078bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2079{
2080 /* FIXME: implement for evergreen */
2081 return false;
2082}
2083
747943ea 2084static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 2085{
747943ea
AD		 2086 struct evergreen_mc_save save;
2087 u32 srbm_reset = 0;
2088 u32 grbm_reset = 0;
2089
2090 dev_info(rdev->dev, "GPU softreset \n");
2091 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2092 RREG32(GRBM_STATUS));
2093 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2094 RREG32(GRBM_STATUS_SE0));
2095 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2096 RREG32(GRBM_STATUS_SE1));
2097 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2098 RREG32(SRBM_STATUS));
2099 evergreen_mc_stop(rdev, &save);
2100 if (evergreen_mc_wait_for_idle(rdev)) {
2101 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2102 }
2103 /* Disable CP parsing/prefetching */
2104 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2105
2106 /* reset all the gfx blocks */
2107 grbm_reset = (SOFT_RESET_CP |
2108 SOFT_RESET_CB |
2109 SOFT_RESET_DB |
2110 SOFT_RESET_PA |
2111 SOFT_RESET_SC |
2112 SOFT_RESET_SPI |
2113 SOFT_RESET_SH |
2114 SOFT_RESET_SX |
2115 SOFT_RESET_TC |
2116 SOFT_RESET_TA |
2117 SOFT_RESET_VC |
2118 SOFT_RESET_VGT);
2119
2120 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2121 WREG32(GRBM_SOFT_RESET, grbm_reset);
2122 (void)RREG32(GRBM_SOFT_RESET);
2123 udelay(50);
2124 WREG32(GRBM_SOFT_RESET, 0);
2125 (void)RREG32(GRBM_SOFT_RESET);
2126
2127 /* reset all the system blocks */
2128 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
2129
2130 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
2131 WREG32(SRBM_SOFT_RESET, srbm_reset);
2132 (void)RREG32(SRBM_SOFT_RESET);
2133 udelay(50);
2134 WREG32(SRBM_SOFT_RESET, 0);
2135 (void)RREG32(SRBM_SOFT_RESET);
2136 /* Wait a little for things to settle down */
2137 udelay(50);
2138 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2139 RREG32(GRBM_STATUS));
2140 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2141 RREG32(GRBM_STATUS_SE0));
2142 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2143 RREG32(GRBM_STATUS_SE1));
2144 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2145 RREG32(SRBM_STATUS));
2146 /* After reset we need to reinit the asic as GPU often endup in an
2147 * incoherent state.
2148 */
2149 atom_asic_init(rdev->mode_info.atom_context);
2150 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2151 return 0;
2152}
2153
a2d07b74 2154int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2155{
747943ea
AD		 2156 return evergreen_gpu_soft_reset(rdev);
2157}
2158
45f9a39b
AD		 2159/* Interrupts */
2160
2161u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2162{
2163 switch (crtc) {
2164 case 0:
2165 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2166 case 1:
2167 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2168 case 2:
2169 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2170 case 3:
2171 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2172 case 4:
2173 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2174 case 5:
2175 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2176 default:
2177 return 0;
2178 }
2179}
2180
2181void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2182{
2183 u32 tmp;
2184
3555e53b 2185 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2186 WREG32(GRBM_INT_CNTL, 0);
2187 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2188 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 2189 if (!(rdev->flags & RADEON_IS_IGP)) {
2190 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2191 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2192 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2193 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2194 }
45f9a39b
AD		 2195
2196 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2197 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 2198 if (!(rdev->flags & RADEON_IS_IGP)) {
2199 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2200 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2201 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2202 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2203 }
45f9a39b
AD		 2204
2205 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2206 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2207
2208 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2209 WREG32(DC_HPD1_INT_CONTROL, tmp);
2210 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2211 WREG32(DC_HPD2_INT_CONTROL, tmp);
2212 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2213 WREG32(DC_HPD3_INT_CONTROL, tmp);
2214 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2215 WREG32(DC_HPD4_INT_CONTROL, tmp);
2216 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2217 WREG32(DC_HPD5_INT_CONTROL, tmp);
2218 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2219 WREG32(DC_HPD6_INT_CONTROL, tmp);
2220
2221}
2222
2223int evergreen_irq_set(struct radeon_device *rdev)
2224{
2225 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2226 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2227 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2228 u32 grbm_int_cntl = 0;
6f34be50 2229 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
45f9a39b
AD		 2230
2231 if (!rdev->irq.installed) {
fce7d61b 2232 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2233 return -EINVAL;
2234 }
2235 /* don't enable anything if the ih is disabled */
2236 if (!rdev->ih.enabled) {
2237 r600_disable_interrupts(rdev);
2238 /* force the active interrupt state to all disabled */
2239 evergreen_disable_interrupt_state(rdev);
2240 return 0;
2241 }
2242
2243 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2244 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2245 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2246 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2247 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2248 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2249
2250 if (rdev->irq.sw_int) {
2251 DRM_DEBUG("evergreen_irq_set: sw int\n");
2252 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 2253 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
45f9a39b 2254 }
6f34be50
AD		 2255 if (rdev->irq.crtc_vblank_int[0] ||
2256 rdev->irq.pflip[0]) {
45f9a39b
AD		 2257 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2258 crtc1 |= VBLANK_INT_MASK;
2259 }
6f34be50
AD		 2260 if (rdev->irq.crtc_vblank_int[1] ||
2261 rdev->irq.pflip[1]) {
45f9a39b
AD		 2262 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2263 crtc2 |= VBLANK_INT_MASK;
2264 }
6f34be50
AD		 2265 if (rdev->irq.crtc_vblank_int[2] ||
2266 rdev->irq.pflip[2]) {
45f9a39b
AD		 2267 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2268 crtc3 |= VBLANK_INT_MASK;
2269 }
6f34be50
AD		 2270 if (rdev->irq.crtc_vblank_int[3] ||
2271 rdev->irq.pflip[3]) {
45f9a39b
AD		 2272 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2273 crtc4 |= VBLANK_INT_MASK;
2274 }
6f34be50
AD		 2275 if (rdev->irq.crtc_vblank_int[4] ||
2276 rdev->irq.pflip[4]) {
45f9a39b
AD		 2277 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2278 crtc5 |= VBLANK_INT_MASK;
2279 }
6f34be50
AD		 2280 if (rdev->irq.crtc_vblank_int[5] ||
2281 rdev->irq.pflip[5]) {
45f9a39b
AD		 2282 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2283 crtc6 |= VBLANK_INT_MASK;
2284 }
2285 if (rdev->irq.hpd[0]) {
2286 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2287 hpd1 |= DC_HPDx_INT_EN;
2288 }
2289 if (rdev->irq.hpd[1]) {
2290 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2291 hpd2 |= DC_HPDx_INT_EN;
2292 }
2293 if (rdev->irq.hpd[2]) {
2294 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2295 hpd3 |= DC_HPDx_INT_EN;
2296 }
2297 if (rdev->irq.hpd[3]) {
2298 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2299 hpd4 |= DC_HPDx_INT_EN;
2300 }
2301 if (rdev->irq.hpd[4]) {
2302 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2303 hpd5 |= DC_HPDx_INT_EN;
2304 }
2305 if (rdev->irq.hpd[5]) {
2306 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2307 hpd6 |= DC_HPDx_INT_EN;
2308 }
2031f77c
AD		 2309 if (rdev->irq.gui_idle) {
2310 DRM_DEBUG("gui idle\n");
2311 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2312 }
45f9a39b
AD		 2313
2314 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2315 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2316
2317 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2318 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
18007401
AD		 2319 if (!(rdev->flags & RADEON_IS_IGP)) {
2320 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2321 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2322 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2323 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2324 }
45f9a39b 2325
6f34be50
AD		 2326 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2327 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2328 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2329 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2330 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2331 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2332
45f9a39b
AD		 2333 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2334 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2335 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2336 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2337 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2338 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2339
bcc1c2a1
AD		 2340 return 0;
2341}
2342
6f34be50 2343static inline void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2344{
2345 u32 tmp;
2346
6f34be50
AD		 2347 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2348 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2349 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2350 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2351 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2352 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2353 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2354 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2355 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2356 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2357 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2358 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2359
2360 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2361 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2362 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2363 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2364 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2365 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2366 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2367 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2368 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2369 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2370 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2371 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2372
2373 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2374 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2375 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b
AD		 2376 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2377
6f34be50 2378 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2379 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2380 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2381 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2382
6f34be50 2383 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
45f9a39b 2384 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2385 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
45f9a39b
AD		 2386 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2387
6f34be50 2388 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
45f9a39b 2389 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2390 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
45f9a39b
AD		 2391 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2392
6f34be50 2393 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
45f9a39b 2394 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2395 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
45f9a39b
AD		 2396 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2397
6f34be50 2398 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
45f9a39b 2399 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2400 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
45f9a39b
AD		 2401 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2402
6f34be50 2403 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2404 tmp = RREG32(DC_HPD1_INT_CONTROL);
2405 tmp |= DC_HPDx_INT_ACK;
2406 WREG32(DC_HPD1_INT_CONTROL, tmp);
2407 }
6f34be50 2408 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2409 tmp = RREG32(DC_HPD2_INT_CONTROL);
2410 tmp |= DC_HPDx_INT_ACK;
2411 WREG32(DC_HPD2_INT_CONTROL, tmp);
2412 }
6f34be50 2413 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2414 tmp = RREG32(DC_HPD3_INT_CONTROL);
2415 tmp |= DC_HPDx_INT_ACK;
2416 WREG32(DC_HPD3_INT_CONTROL, tmp);
2417 }
6f34be50 2418 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2419 tmp = RREG32(DC_HPD4_INT_CONTROL);
2420 tmp |= DC_HPDx_INT_ACK;
2421 WREG32(DC_HPD4_INT_CONTROL, tmp);
2422 }
6f34be50 2423 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2424 tmp = RREG32(DC_HPD5_INT_CONTROL);
2425 tmp |= DC_HPDx_INT_ACK;
2426 WREG32(DC_HPD5_INT_CONTROL, tmp);
2427 }
6f34be50 2428 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2429 tmp = RREG32(DC_HPD5_INT_CONTROL);
2430 tmp |= DC_HPDx_INT_ACK;
2431 WREG32(DC_HPD6_INT_CONTROL, tmp);
2432 }
2433}
2434
2435void evergreen_irq_disable(struct radeon_device *rdev)
2436{
45f9a39b
AD		 2437 r600_disable_interrupts(rdev);
2438 /* Wait and acknowledge irq */
2439 mdelay(1);
6f34be50 2440 evergreen_irq_ack(rdev);
45f9a39b
AD		 2441 evergreen_disable_interrupt_state(rdev);
2442}
2443
2444static void evergreen_irq_suspend(struct radeon_device *rdev)
2445{
2446 evergreen_irq_disable(rdev);
2447 r600_rlc_stop(rdev);
2448}
2449
2450static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2451{
2452 u32 wptr, tmp;
2453
724c80e1
AD		 2454 if (rdev->wb.enabled)
2455 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2456 else
2457 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2458
2459 if (wptr & RB_OVERFLOW) {
2460 /* When a ring buffer overflow happen start parsing interrupt
2461 * from the last not overwritten vector (wptr + 16). Hopefully
2462 * this should allow us to catchup.
2463 */
2464 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2465 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2466 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2467 tmp = RREG32(IH_RB_CNTL);
2468 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2469 WREG32(IH_RB_CNTL, tmp);
2470 }
2471 return (wptr & rdev->ih.ptr_mask);
2472}
2473
2474int evergreen_irq_process(struct radeon_device *rdev)
2475{
2476 u32 wptr = evergreen_get_ih_wptr(rdev);
2477 u32 rptr = rdev->ih.rptr;
2478 u32 src_id, src_data;
2479 u32 ring_index;
45f9a39b
AD		 2480 unsigned long flags;
2481 bool queue_hotplug = false;
2482
2483 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2484 if (!rdev->ih.enabled)
2485 return IRQ_NONE;
2486
2487 spin_lock_irqsave(&rdev->ih.lock, flags);
2488
2489 if (rptr == wptr) {
2490 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2491 return IRQ_NONE;
2492 }
2493 if (rdev->shutdown) {
2494 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2495 return IRQ_NONE;
2496 }
2497
2498restart_ih:
2499 /* display interrupts */
6f34be50 2500 evergreen_irq_ack(rdev);
45f9a39b
AD		 2501
2502 rdev->ih.wptr = wptr;
2503 while (rptr != wptr) {
2504 /* wptr/rptr are in bytes! */
2505 ring_index = rptr / 4;
2506 src_id = rdev->ih.ring[ring_index] & 0xff;
2507 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2508
2509 switch (src_id) {
2510 case 1: /* D1 vblank/vline */
2511 switch (src_data) {
2512 case 0: /* D1 vblank */
6f34be50 2513 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 2514 if (rdev->irq.crtc_vblank_int[0]) {
2515 drm_handle_vblank(rdev->ddev, 0);
2516 rdev->pm.vblank_sync = true;
2517 wake_up(&rdev->irq.vblank_queue);
2518 }
3e4ea742
MK		 2519 if (rdev->irq.pflip[0])
2520 radeon_crtc_handle_flip(rdev, 0);
6f34be50 2521 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2522 DRM_DEBUG("IH: D1 vblank\n");
2523 }
2524 break;
2525 case 1: /* D1 vline */
6f34be50
AD		 2526 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2527 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 2528 DRM_DEBUG("IH: D1 vline\n");
2529 }
2530 break;
2531 default:
2532 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2533 break;
2534 }
2535 break;
2536 case 2: /* D2 vblank/vline */
2537 switch (src_data) {
2538 case 0: /* D2 vblank */
6f34be50 2539 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 2540 if (rdev->irq.crtc_vblank_int[1]) {
2541 drm_handle_vblank(rdev->ddev, 1);
2542 rdev->pm.vblank_sync = true;
2543 wake_up(&rdev->irq.vblank_queue);
2544 }
3e4ea742
MK		 2545 if (rdev->irq.pflip[1])
2546 radeon_crtc_handle_flip(rdev, 1);
6f34be50 2547 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 2548 DRM_DEBUG("IH: D2 vblank\n");
2549 }
2550 break;
2551 case 1: /* D2 vline */
6f34be50
AD		 2552 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2553 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 2554 DRM_DEBUG("IH: D2 vline\n");
2555 }
2556 break;
2557 default:
2558 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2559 break;
2560 }
2561 break;
2562 case 3: /* D3 vblank/vline */
2563 switch (src_data) {
2564 case 0: /* D3 vblank */
6f34be50
AD		 2565 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2566 if (rdev->irq.crtc_vblank_int[2]) {
2567 drm_handle_vblank(rdev->ddev, 2);
2568 rdev->pm.vblank_sync = true;
2569 wake_up(&rdev->irq.vblank_queue);
2570 }
2571 if (rdev->irq.pflip[2])
2572 radeon_crtc_handle_flip(rdev, 2);
2573 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 2574 DRM_DEBUG("IH: D3 vblank\n");
2575 }
2576 break;
2577 case 1: /* D3 vline */
6f34be50
AD		 2578 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2579 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 2580 DRM_DEBUG("IH: D3 vline\n");
2581 }
2582 break;
2583 default:
2584 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2585 break;
2586 }
2587 break;
2588 case 4: /* D4 vblank/vline */
2589 switch (src_data) {
2590 case 0: /* D4 vblank */
6f34be50
AD		 2591 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2592 if (rdev->irq.crtc_vblank_int[3]) {
2593 drm_handle_vblank(rdev->ddev, 3);
2594 rdev->pm.vblank_sync = true;
2595 wake_up(&rdev->irq.vblank_queue);
2596 }
2597 if (rdev->irq.pflip[3])
2598 radeon_crtc_handle_flip(rdev, 3);
2599 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 2600 DRM_DEBUG("IH: D4 vblank\n");
2601 }
2602 break;
2603 case 1: /* D4 vline */
6f34be50
AD		 2604 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2605 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 2606 DRM_DEBUG("IH: D4 vline\n");
2607 }
2608 break;
2609 default:
2610 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2611 break;
2612 }
2613 break;
2614 case 5: /* D5 vblank/vline */
2615 switch (src_data) {
2616 case 0: /* D5 vblank */
6f34be50
AD		 2617 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2618 if (rdev->irq.crtc_vblank_int[4]) {
2619 drm_handle_vblank(rdev->ddev, 4);
2620 rdev->pm.vblank_sync = true;
2621 wake_up(&rdev->irq.vblank_queue);
2622 }
2623 if (rdev->irq.pflip[4])
2624 radeon_crtc_handle_flip(rdev, 4);
2625 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 2626 DRM_DEBUG("IH: D5 vblank\n");
2627 }
2628 break;
2629 case 1: /* D5 vline */
6f34be50
AD		 2630 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2631 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 2632 DRM_DEBUG("IH: D5 vline\n");
2633 }
2634 break;
2635 default:
2636 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2637 break;
2638 }
2639 break;
2640 case 6: /* D6 vblank/vline */
2641 switch (src_data) {
2642 case 0: /* D6 vblank */
6f34be50
AD		 2643 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2644 if (rdev->irq.crtc_vblank_int[5]) {
2645 drm_handle_vblank(rdev->ddev, 5);
2646 rdev->pm.vblank_sync = true;
2647 wake_up(&rdev->irq.vblank_queue);
2648 }
2649 if (rdev->irq.pflip[5])
2650 radeon_crtc_handle_flip(rdev, 5);
2651 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 2652 DRM_DEBUG("IH: D6 vblank\n");
2653 }
2654 break;
2655 case 1: /* D6 vline */
6f34be50
AD		 2656 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2657 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 2658 DRM_DEBUG("IH: D6 vline\n");
2659 }
2660 break;
2661 default:
2662 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2663 break;
2664 }
2665 break;
2666 case 42: /* HPD hotplug */
2667 switch (src_data) {
2668 case 0:
6f34be50
AD		 2669 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2670 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 2671 queue_hotplug = true;
2672 DRM_DEBUG("IH: HPD1\n");
2673 }
2674 break;
2675 case 1:
6f34be50
AD		 2676 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2677 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 2678 queue_hotplug = true;
2679 DRM_DEBUG("IH: HPD2\n");
2680 }
2681 break;
2682 case 2:
6f34be50
AD		 2683 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2684 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 2685 queue_hotplug = true;
2686 DRM_DEBUG("IH: HPD3\n");
2687 }
2688 break;
2689 case 3:
6f34be50
AD		 2690 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2691 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 2692 queue_hotplug = true;
2693 DRM_DEBUG("IH: HPD4\n");
2694 }
2695 break;
2696 case 4:
6f34be50
AD		 2697 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2698 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 2699 queue_hotplug = true;
2700 DRM_DEBUG("IH: HPD5\n");
2701 }
2702 break;
2703 case 5:
6f34be50
AD		 2704 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2705 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 2706 queue_hotplug = true;
2707 DRM_DEBUG("IH: HPD6\n");
2708 }
2709 break;
2710 default:
2711 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2712 break;
2713 }
2714 break;
2715 case 176: /* CP_INT in ring buffer */
2716 case 177: /* CP_INT in IB1 */
2717 case 178: /* CP_INT in IB2 */
2718 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2719 radeon_fence_process(rdev);
2720 break;
2721 case 181: /* CP EOP event */
2722 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 2723 radeon_fence_process(rdev);
45f9a39b 2724 break;
2031f77c
AD		 2725 case 233: /* GUI IDLE */
2726 DRM_DEBUG("IH: CP EOP\n");
2727 rdev->pm.gui_idle = true;
2728 wake_up(&rdev->irq.idle_queue);
2729 break;
45f9a39b
AD		 2730 default:
2731 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2732 break;
2733 }
2734
2735 /* wptr/rptr are in bytes! */
2736 rptr += 16;
2737 rptr &= rdev->ih.ptr_mask;
2738 }
2739 /* make sure wptr hasn't changed while processing */
2740 wptr = evergreen_get_ih_wptr(rdev);
2741 if (wptr != rdev->ih.wptr)
2742 goto restart_ih;
2743 if (queue_hotplug)
2744 queue_work(rdev->wq, &rdev->hotplug_work);
2745 rdev->ih.rptr = rptr;
2746 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2747 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2748 return IRQ_HANDLED;
2749}
2750
bcc1c2a1
AD		 2751static int evergreen_startup(struct radeon_device *rdev)
2752{
bcc1c2a1
AD		 2753 int r;
2754
2755 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2756 r = r600_init_microcode(rdev);
2757 if (r) {
2758 DRM_ERROR("Failed to load firmware!\n");
2759 return r;
2760 }
2761 }
fe251e2f 2762
bcc1c2a1 2763 evergreen_mc_program(rdev);
bcc1c2a1 2764 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 2765 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 2766 } else {
2767 r = evergreen_pcie_gart_enable(rdev);
2768 if (r)
2769 return r;
2770 }
bcc1c2a1 2771 evergreen_gpu_init(rdev);
bcc1c2a1 2772
d7ccd8fc 2773 r = evergreen_blit_init(rdev);
bcc1c2a1 2774 if (r) {
d7ccd8fc
AD		 2775 evergreen_blit_fini(rdev);
2776 rdev->asic->copy = NULL;
2777 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 2778 }
2779
724c80e1
AD		 2780 /* allocate wb buffer */
2781 r = radeon_wb_init(rdev);
2782 if (r)
2783 return r;
2784
bcc1c2a1
AD		 2785 /* Enable IRQ */
2786 r = r600_irq_init(rdev);
2787 if (r) {
2788 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2789 radeon_irq_kms_fini(rdev);
2790 return r;
2791 }
45f9a39b 2792 evergreen_irq_set(rdev);
bcc1c2a1
AD		 2793
2794 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2795 if (r)
2796 return r;
2797 r = evergreen_cp_load_microcode(rdev);
2798 if (r)
2799 return r;
fe251e2f 2800 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 2801 if (r)
2802 return r;
fe251e2f 2803
bcc1c2a1
AD		 2804 return 0;
2805}
2806
2807int evergreen_resume(struct radeon_device *rdev)
2808{
2809 int r;
2810
2811 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2812 * posting will perform necessary task to bring back GPU into good
2813 * shape.
2814 */
2815 /* post card */
2816 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1
AD		 2817
2818 r = evergreen_startup(rdev);
2819 if (r) {
2820 DRM_ERROR("r600 startup failed on resume\n");
2821 return r;
2822 }
fe251e2f 2823
bcc1c2a1
AD		 2824 r = r600_ib_test(rdev);
2825 if (r) {
2826 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2827 return r;
2828 }
fe251e2f 2829
bcc1c2a1
AD		 2830 return r;
2831
2832}
2833
2834int evergreen_suspend(struct radeon_device *rdev)
2835{
bcc1c2a1 2836 int r;
d7ccd8fc 2837
bcc1c2a1
AD		 2838 /* FIXME: we should wait for ring to be empty */
2839 r700_cp_stop(rdev);
2840 rdev->cp.ready = false;
45f9a39b 2841 evergreen_irq_suspend(rdev);
724c80e1 2842 radeon_wb_disable(rdev);
bcc1c2a1 2843 evergreen_pcie_gart_disable(rdev);
d7ccd8fc 2844
bcc1c2a1
AD		 2845 /* unpin shaders bo */
2846 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2847 if (likely(r == 0)) {
2848 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2849 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2850 }
d7ccd8fc
AD		 2851
2852 return 0;
2853}
2854
2855int evergreen_copy_blit(struct radeon_device *rdev,
2856 uint64_t src_offset, uint64_t dst_offset,
2857 unsigned num_pages, struct radeon_fence *fence)
2858{
2859 int r;
2860
2861 mutex_lock(&rdev->r600_blit.mutex);
2862 rdev->r600_blit.vb_ib = NULL;
2863 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2864 if (r) {
2865 if (rdev->r600_blit.vb_ib)
2866 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2867 mutex_unlock(&rdev->r600_blit.mutex);
2868 return r;
2869 }
2870 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2871 evergreen_blit_done_copy(rdev, fence);
2872 mutex_unlock(&rdev->r600_blit.mutex);
bcc1c2a1
AD		 2873 return 0;
2874}
2875
2876static bool evergreen_card_posted(struct radeon_device *rdev)
2877{
2878 u32 reg;
2879
2880 /* first check CRTCs */
18007401
AD		 2881 if (rdev->flags & RADEON_IS_IGP)
2882 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2883 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2884 else
2885 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2886 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2887 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2888 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2889 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2890 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
bcc1c2a1
AD		 2891 if (reg & EVERGREEN_CRTC_MASTER_EN)
2892 return true;
2893
2894 /* then check MEM_SIZE, in case the crtcs are off */
2895 if (RREG32(CONFIG_MEMSIZE))
2896 return true;
2897
2898 return false;
2899}
2900
2901/* Plan is to move initialization in that function and use
2902 * helper function so that radeon_device_init pretty much
2903 * do nothing more than calling asic specific function. This
2904 * should also allow to remove a bunch of callback function
2905 * like vram_info.
2906 */
2907int evergreen_init(struct radeon_device *rdev)
2908{
2909 int r;
2910
2911 r = radeon_dummy_page_init(rdev);
2912 if (r)
2913 return r;
2914 /* This don't do much */
2915 r = radeon_gem_init(rdev);
2916 if (r)
2917 return r;
2918 /* Read BIOS */
2919 if (!radeon_get_bios(rdev)) {
2920 if (ASIC_IS_AVIVO(rdev))
2921 return -EINVAL;
2922 }
2923 /* Must be an ATOMBIOS */
2924 if (!rdev->is_atom_bios) {
2925 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2926 return -EINVAL;
2927 }
2928 r = radeon_atombios_init(rdev);
2929 if (r)
2930 return r;
2931 /* Post card if necessary */
2932 if (!evergreen_card_posted(rdev)) {
2933 if (!rdev->bios) {
2934 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2935 return -EINVAL;
2936 }
2937 DRM_INFO("GPU not posted. posting now...\n");
2938 atom_asic_init(rdev->mode_info.atom_context);
2939 }
2940 /* Initialize scratch registers */
2941 r600_scratch_init(rdev);
2942 /* Initialize surface registers */
2943 radeon_surface_init(rdev);
2944 /* Initialize clocks */
2945 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 2946 /* Fence driver */
2947 r = radeon_fence_driver_init(rdev);
2948 if (r)
2949 return r;
d594e46a
JG		 2950 /* initialize AGP */
2951 if (rdev->flags & RADEON_IS_AGP) {
2952 r = radeon_agp_init(rdev);
2953 if (r)
2954 radeon_agp_disable(rdev);
2955 }
2956 /* initialize memory controller */
bcc1c2a1
AD		 2957 r = evergreen_mc_init(rdev);
2958 if (r)
2959 return r;
2960 /* Memory manager */
2961 r = radeon_bo_init(rdev);
2962 if (r)
2963 return r;
45f9a39b 2964
bcc1c2a1
AD		 2965 r = radeon_irq_kms_init(rdev);
2966 if (r)
2967 return r;
2968
2969 rdev->cp.ring_obj = NULL;
2970 r600_ring_init(rdev, 1024 * 1024);
2971
2972 rdev->ih.ring_obj = NULL;
2973 r600_ih_ring_init(rdev, 64 * 1024);
2974
2975 r = r600_pcie_gart_init(rdev);
2976 if (r)
2977 return r;
0fcdb61e 2978
148a03bc 2979 rdev->accel_working = true;
bcc1c2a1
AD		 2980 r = evergreen_startup(rdev);
2981 if (r) {
fe251e2f
AD		 2982 dev_err(rdev->dev, "disabling GPU acceleration\n");
2983 r700_cp_fini(rdev);
fe251e2f 2984 r600_irq_fini(rdev);
724c80e1 2985 radeon_wb_fini(rdev);
fe251e2f 2986 radeon_irq_kms_fini(rdev);
0fcdb61e 2987 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2988 rdev->accel_working = false;
2989 }
2990 if (rdev->accel_working) {
2991 r = radeon_ib_pool_init(rdev);
2992 if (r) {
2993 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2994 rdev->accel_working = false;
2995 }
2996 r = r600_ib_test(rdev);
2997 if (r) {
2998 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2999 rdev->accel_working = false;
3000 }
3001 }
3002 return 0;
3003}
3004
3005void evergreen_fini(struct radeon_device *rdev)
3006{
d7ccd8fc 3007 evergreen_blit_fini(rdev);
45f9a39b 3008 r700_cp_fini(rdev);
bcc1c2a1 3009 r600_irq_fini(rdev);
724c80e1 3010 radeon_wb_fini(rdev);
bcc1c2a1 3011 radeon_irq_kms_fini(rdev);
bcc1c2a1 3012 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3013 radeon_gem_fini(rdev);
3014 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3015 radeon_agp_fini(rdev);
3016 radeon_bo_fini(rdev);
3017 radeon_atombios_fini(rdev);
3018 kfree(rdev->bios);
3019 rdev->bios = NULL;
3020 radeon_dummy_page_fini(rdev);
3021}
Linux kernel - Deliverables
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