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drm/radeon/kms: fill in GPU init for AMD Ontario Fusion APUs
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
42
21a8122a
AD		 43/* get temperature in millidegrees */
44u32 evergreen_get_temp(struct radeon_device *rdev)
45{
46 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
47 ASIC_T_SHIFT;
48 u32 actual_temp = 0;
49
50 if ((temp >> 10) & 1)
51 actual_temp = 0;
52 else if ((temp >> 9) & 1)
53 actual_temp = 255;
54 else
55 actual_temp = (temp >> 1) & 0xff;
56
57 return actual_temp * 1000;
58}
59
49e02b73
AD		 60void evergreen_pm_misc(struct radeon_device *rdev)
61{
a081a9d6
RM		 62 int req_ps_idx = rdev->pm.requested_power_state_index;
63 int req_cm_idx = rdev->pm.requested_clock_mode_index;
64 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
65 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 66
4d60173f
AD		 67 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
68 if (voltage->voltage != rdev->pm.current_vddc) {
69 radeon_atom_set_voltage(rdev, voltage->voltage);
70 rdev->pm.current_vddc = voltage->voltage;
0fcbe947 71 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
4d60173f
AD		 72 }
73 }
49e02b73
AD		 74}
75
76void evergreen_pm_prepare(struct radeon_device *rdev)
77{
78 struct drm_device *ddev = rdev->ddev;
79 struct drm_crtc *crtc;
80 struct radeon_crtc *radeon_crtc;
81 u32 tmp;
82
83 /* disable any active CRTCs */
84 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
85 radeon_crtc = to_radeon_crtc(crtc);
86 if (radeon_crtc->enabled) {
87 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
88 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
89 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
90 }
91 }
92}
93
94void evergreen_pm_finish(struct radeon_device *rdev)
95{
96 struct drm_device *ddev = rdev->ddev;
97 struct drm_crtc *crtc;
98 struct radeon_crtc *radeon_crtc;
99 u32 tmp;
100
101 /* enable any active CRTCs */
102 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
103 radeon_crtc = to_radeon_crtc(crtc);
104 if (radeon_crtc->enabled) {
105 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
106 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
107 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
108 }
109 }
110}
111
bcc1c2a1
AD		 112bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
113{
114 bool connected = false;
0ca2ab52
AD		 115
116 switch (hpd) {
117 case RADEON_HPD_1:
118 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
119 connected = true;
120 break;
121 case RADEON_HPD_2:
122 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
123 connected = true;
124 break;
125 case RADEON_HPD_3:
126 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
127 connected = true;
128 break;
129 case RADEON_HPD_4:
130 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
131 connected = true;
132 break;
133 case RADEON_HPD_5:
134 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
135 connected = true;
136 break;
137 case RADEON_HPD_6:
138 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
139 connected = true;
140 break;
141 default:
142 break;
143 }
144
bcc1c2a1
AD		 145 return connected;
146}
147
148void evergreen_hpd_set_polarity(struct radeon_device *rdev,
149 enum radeon_hpd_id hpd)
150{
0ca2ab52
AD		 151 u32 tmp;
152 bool connected = evergreen_hpd_sense(rdev, hpd);
153
154 switch (hpd) {
155 case RADEON_HPD_1:
156 tmp = RREG32(DC_HPD1_INT_CONTROL);
157 if (connected)
158 tmp &= ~DC_HPDx_INT_POLARITY;
159 else
160 tmp |= DC_HPDx_INT_POLARITY;
161 WREG32(DC_HPD1_INT_CONTROL, tmp);
162 break;
163 case RADEON_HPD_2:
164 tmp = RREG32(DC_HPD2_INT_CONTROL);
165 if (connected)
166 tmp &= ~DC_HPDx_INT_POLARITY;
167 else
168 tmp |= DC_HPDx_INT_POLARITY;
169 WREG32(DC_HPD2_INT_CONTROL, tmp);
170 break;
171 case RADEON_HPD_3:
172 tmp = RREG32(DC_HPD3_INT_CONTROL);
173 if (connected)
174 tmp &= ~DC_HPDx_INT_POLARITY;
175 else
176 tmp |= DC_HPDx_INT_POLARITY;
177 WREG32(DC_HPD3_INT_CONTROL, tmp);
178 break;
179 case RADEON_HPD_4:
180 tmp = RREG32(DC_HPD4_INT_CONTROL);
181 if (connected)
182 tmp &= ~DC_HPDx_INT_POLARITY;
183 else
184 tmp |= DC_HPDx_INT_POLARITY;
185 WREG32(DC_HPD4_INT_CONTROL, tmp);
186 break;
187 case RADEON_HPD_5:
188 tmp = RREG32(DC_HPD5_INT_CONTROL);
189 if (connected)
190 tmp &= ~DC_HPDx_INT_POLARITY;
191 else
192 tmp |= DC_HPDx_INT_POLARITY;
193 WREG32(DC_HPD5_INT_CONTROL, tmp);
194 break;
195 case RADEON_HPD_6:
196 tmp = RREG32(DC_HPD6_INT_CONTROL);
197 if (connected)
198 tmp &= ~DC_HPDx_INT_POLARITY;
199 else
200 tmp |= DC_HPDx_INT_POLARITY;
201 WREG32(DC_HPD6_INT_CONTROL, tmp);
202 break;
203 default:
204 break;
205 }
bcc1c2a1
AD		 206}
207
208void evergreen_hpd_init(struct radeon_device *rdev)
209{
0ca2ab52
AD		 210 struct drm_device *dev = rdev->ddev;
211 struct drm_connector *connector;
212 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
213 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 214
0ca2ab52
AD		 215 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
216 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
217 switch (radeon_connector->hpd.hpd) {
218 case RADEON_HPD_1:
219 WREG32(DC_HPD1_CONTROL, tmp);
220 rdev->irq.hpd[0] = true;
221 break;
222 case RADEON_HPD_2:
223 WREG32(DC_HPD2_CONTROL, tmp);
224 rdev->irq.hpd[1] = true;
225 break;
226 case RADEON_HPD_3:
227 WREG32(DC_HPD3_CONTROL, tmp);
228 rdev->irq.hpd[2] = true;
229 break;
230 case RADEON_HPD_4:
231 WREG32(DC_HPD4_CONTROL, tmp);
232 rdev->irq.hpd[3] = true;
233 break;
234 case RADEON_HPD_5:
235 WREG32(DC_HPD5_CONTROL, tmp);
236 rdev->irq.hpd[4] = true;
237 break;
238 case RADEON_HPD_6:
239 WREG32(DC_HPD6_CONTROL, tmp);
240 rdev->irq.hpd[5] = true;
241 break;
242 default:
243 break;
244 }
245 }
246 if (rdev->irq.installed)
247 evergreen_irq_set(rdev);
bcc1c2a1
AD		 248}
249
0ca2ab52 250void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 251{
0ca2ab52
AD		 252 struct drm_device *dev = rdev->ddev;
253 struct drm_connector *connector;
254
255 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
256 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
257 switch (radeon_connector->hpd.hpd) {
258 case RADEON_HPD_1:
259 WREG32(DC_HPD1_CONTROL, 0);
260 rdev->irq.hpd[0] = false;
261 break;
262 case RADEON_HPD_2:
263 WREG32(DC_HPD2_CONTROL, 0);
264 rdev->irq.hpd[1] = false;
265 break;
266 case RADEON_HPD_3:
267 WREG32(DC_HPD3_CONTROL, 0);
268 rdev->irq.hpd[2] = false;
269 break;
270 case RADEON_HPD_4:
271 WREG32(DC_HPD4_CONTROL, 0);
272 rdev->irq.hpd[3] = false;
273 break;
274 case RADEON_HPD_5:
275 WREG32(DC_HPD5_CONTROL, 0);
276 rdev->irq.hpd[4] = false;
277 break;
278 case RADEON_HPD_6:
279 WREG32(DC_HPD6_CONTROL, 0);
280 rdev->irq.hpd[5] = false;
281 break;
282 default:
283 break;
284 }
285 }
bcc1c2a1
AD		 286}
287
f9d9c362
AD		 288/* watermark setup */
289
290static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
291 struct radeon_crtc *radeon_crtc,
292 struct drm_display_mode *mode,
293 struct drm_display_mode *other_mode)
294{
295 u32 tmp = 0;
296 /*
297 * Line Buffer Setup
298 * There are 3 line buffers, each one shared by 2 display controllers.
299 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
300 * the display controllers. The paritioning is done via one of four
301 * preset allocations specified in bits 2:0:
302 * first display controller
303 * 0 - first half of lb (3840 * 2)
304 * 1 - first 3/4 of lb (5760 * 2)
305 * 2 - whole lb (7680 * 2)
306 * 3 - first 1/4 of lb (1920 * 2)
307 * second display controller
308 * 4 - second half of lb (3840 * 2)
309 * 5 - second 3/4 of lb (5760 * 2)
310 * 6 - whole lb (7680 * 2)
311 * 7 - last 1/4 of lb (1920 * 2)
312 */
313 if (mode && other_mode) {
314 if (mode->hdisplay > other_mode->hdisplay) {
315 if (mode->hdisplay > 2560)
316 tmp = 1; /* 3/4 */
317 else
318 tmp = 0; /* 1/2 */
319 } else if (other_mode->hdisplay > mode->hdisplay) {
320 if (other_mode->hdisplay > 2560)
321 tmp = 3; /* 1/4 */
322 else
323 tmp = 0; /* 1/2 */
324 } else
325 tmp = 0; /* 1/2 */
326 } else if (mode)
327 tmp = 2; /* whole */
328 else if (other_mode)
329 tmp = 3; /* 1/4 */
330
331 /* second controller of the pair uses second half of the lb */
332 if (radeon_crtc->crtc_id % 2)
333 tmp += 4;
334 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
335
336 switch (tmp) {
337 case 0:
338 case 4:
339 default:
340 return 3840 * 2;
341 case 1:
342 case 5:
343 return 5760 * 2;
344 case 2:
345 case 6:
346 return 7680 * 2;
347 case 3:
348 case 7:
349 return 1920 * 2;
350 }
351}
352
353static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
354{
355 u32 tmp = RREG32(MC_SHARED_CHMAP);
356
357 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
358 case 0:
359 default:
360 return 1;
361 case 1:
362 return 2;
363 case 2:
364 return 4;
365 case 3:
366 return 8;
367 }
368}
369
370struct evergreen_wm_params {
371 u32 dram_channels; /* number of dram channels */
372 u32 yclk; /* bandwidth per dram data pin in kHz */
373 u32 sclk; /* engine clock in kHz */
374 u32 disp_clk; /* display clock in kHz */
375 u32 src_width; /* viewport width */
376 u32 active_time; /* active display time in ns */
377 u32 blank_time; /* blank time in ns */
378 bool interlaced; /* mode is interlaced */
379 fixed20_12 vsc; /* vertical scale ratio */
380 u32 num_heads; /* number of active crtcs */
381 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
382 u32 lb_size; /* line buffer allocated to pipe */
383 u32 vtaps; /* vertical scaler taps */
384};
385
386static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
387{
388 /* Calculate DRAM Bandwidth and the part allocated to display. */
389 fixed20_12 dram_efficiency; /* 0.7 */
390 fixed20_12 yclk, dram_channels, bandwidth;
391 fixed20_12 a;
392
393 a.full = dfixed_const(1000);
394 yclk.full = dfixed_const(wm->yclk);
395 yclk.full = dfixed_div(yclk, a);
396 dram_channels.full = dfixed_const(wm->dram_channels * 4);
397 a.full = dfixed_const(10);
398 dram_efficiency.full = dfixed_const(7);
399 dram_efficiency.full = dfixed_div(dram_efficiency, a);
400 bandwidth.full = dfixed_mul(dram_channels, yclk);
401 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
402
403 return dfixed_trunc(bandwidth);
404}
405
406static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
407{
408 /* Calculate DRAM Bandwidth and the part allocated to display. */
409 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
410 fixed20_12 yclk, dram_channels, bandwidth;
411 fixed20_12 a;
412
413 a.full = dfixed_const(1000);
414 yclk.full = dfixed_const(wm->yclk);
415 yclk.full = dfixed_div(yclk, a);
416 dram_channels.full = dfixed_const(wm->dram_channels * 4);
417 a.full = dfixed_const(10);
418 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
419 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
420 bandwidth.full = dfixed_mul(dram_channels, yclk);
421 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
422
423 return dfixed_trunc(bandwidth);
424}
425
426static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
427{
428 /* Calculate the display Data return Bandwidth */
429 fixed20_12 return_efficiency; /* 0.8 */
430 fixed20_12 sclk, bandwidth;
431 fixed20_12 a;
432
433 a.full = dfixed_const(1000);
434 sclk.full = dfixed_const(wm->sclk);
435 sclk.full = dfixed_div(sclk, a);
436 a.full = dfixed_const(10);
437 return_efficiency.full = dfixed_const(8);
438 return_efficiency.full = dfixed_div(return_efficiency, a);
439 a.full = dfixed_const(32);
440 bandwidth.full = dfixed_mul(a, sclk);
441 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
442
443 return dfixed_trunc(bandwidth);
444}
445
446static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
447{
448 /* Calculate the DMIF Request Bandwidth */
449 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
450 fixed20_12 disp_clk, bandwidth;
451 fixed20_12 a;
452
453 a.full = dfixed_const(1000);
454 disp_clk.full = dfixed_const(wm->disp_clk);
455 disp_clk.full = dfixed_div(disp_clk, a);
456 a.full = dfixed_const(10);
457 disp_clk_request_efficiency.full = dfixed_const(8);
458 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
459 a.full = dfixed_const(32);
460 bandwidth.full = dfixed_mul(a, disp_clk);
461 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
462
463 return dfixed_trunc(bandwidth);
464}
465
466static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
467{
468 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
469 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
470 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
471 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
472
473 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
474}
475
476static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
477{
478 /* Calculate the display mode Average Bandwidth
479 * DisplayMode should contain the source and destination dimensions,
480 * timing, etc.
481 */
482 fixed20_12 bpp;
483 fixed20_12 line_time;
484 fixed20_12 src_width;
485 fixed20_12 bandwidth;
486 fixed20_12 a;
487
488 a.full = dfixed_const(1000);
489 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
490 line_time.full = dfixed_div(line_time, a);
491 bpp.full = dfixed_const(wm->bytes_per_pixel);
492 src_width.full = dfixed_const(wm->src_width);
493 bandwidth.full = dfixed_mul(src_width, bpp);
494 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
495 bandwidth.full = dfixed_div(bandwidth, line_time);
496
497 return dfixed_trunc(bandwidth);
498}
499
500static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
501{
502 /* First calcualte the latency in ns */
503 u32 mc_latency = 2000; /* 2000 ns. */
504 u32 available_bandwidth = evergreen_available_bandwidth(wm);
505 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
506 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
507 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
508 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
509 (wm->num_heads * cursor_line_pair_return_time);
510 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
511 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
512 fixed20_12 a, b, c;
513
514 if (wm->num_heads == 0)
515 return 0;
516
517 a.full = dfixed_const(2);
518 b.full = dfixed_const(1);
519 if ((wm->vsc.full > a.full) ||
520 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
521 (wm->vtaps >= 5) ||
522 ((wm->vsc.full >= a.full) && wm->interlaced))
523 max_src_lines_per_dst_line = 4;
524 else
525 max_src_lines_per_dst_line = 2;
526
527 a.full = dfixed_const(available_bandwidth);
528 b.full = dfixed_const(wm->num_heads);
529 a.full = dfixed_div(a, b);
530
531 b.full = dfixed_const(1000);
532 c.full = dfixed_const(wm->disp_clk);
533 b.full = dfixed_div(c, b);
534 c.full = dfixed_const(wm->bytes_per_pixel);
535 b.full = dfixed_mul(b, c);
536
537 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
538
539 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
540 b.full = dfixed_const(1000);
541 c.full = dfixed_const(lb_fill_bw);
542 b.full = dfixed_div(c, b);
543 a.full = dfixed_div(a, b);
544 line_fill_time = dfixed_trunc(a);
545
546 if (line_fill_time < wm->active_time)
547 return latency;
548 else
549 return latency + (line_fill_time - wm->active_time);
550
551}
552
553static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
554{
555 if (evergreen_average_bandwidth(wm) <=
556 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
557 return true;
558 else
559 return false;
560};
561
562static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
563{
564 if (evergreen_average_bandwidth(wm) <=
565 (evergreen_available_bandwidth(wm) / wm->num_heads))
566 return true;
567 else
568 return false;
569};
570
571static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
572{
573 u32 lb_partitions = wm->lb_size / wm->src_width;
574 u32 line_time = wm->active_time + wm->blank_time;
575 u32 latency_tolerant_lines;
576 u32 latency_hiding;
577 fixed20_12 a;
578
579 a.full = dfixed_const(1);
580 if (wm->vsc.full > a.full)
581 latency_tolerant_lines = 1;
582 else {
583 if (lb_partitions <= (wm->vtaps + 1))
584 latency_tolerant_lines = 1;
585 else
586 latency_tolerant_lines = 2;
587 }
588
589 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
590
591 if (evergreen_latency_watermark(wm) <= latency_hiding)
592 return true;
593 else
594 return false;
595}
596
597static void evergreen_program_watermarks(struct radeon_device *rdev,
598 struct radeon_crtc *radeon_crtc,
599 u32 lb_size, u32 num_heads)
600{
601 struct drm_display_mode *mode = &radeon_crtc->base.mode;
602 struct evergreen_wm_params wm;
603 u32 pixel_period;
604 u32 line_time = 0;
605 u32 latency_watermark_a = 0, latency_watermark_b = 0;
606 u32 priority_a_mark = 0, priority_b_mark = 0;
607 u32 priority_a_cnt = PRIORITY_OFF;
608 u32 priority_b_cnt = PRIORITY_OFF;
609 u32 pipe_offset = radeon_crtc->crtc_id * 16;
610 u32 tmp, arb_control3;
611 fixed20_12 a, b, c;
612
613 if (radeon_crtc->base.enabled && num_heads && mode) {
614 pixel_period = 1000000 / (u32)mode->clock;
615 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
616 priority_a_cnt = 0;
617 priority_b_cnt = 0;
618
619 wm.yclk = rdev->pm.current_mclk * 10;
620 wm.sclk = rdev->pm.current_sclk * 10;
621 wm.disp_clk = mode->clock;
622 wm.src_width = mode->crtc_hdisplay;
623 wm.active_time = mode->crtc_hdisplay * pixel_period;
624 wm.blank_time = line_time - wm.active_time;
625 wm.interlaced = false;
626 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
627 wm.interlaced = true;
628 wm.vsc = radeon_crtc->vsc;
629 wm.vtaps = 1;
630 if (radeon_crtc->rmx_type != RMX_OFF)
631 wm.vtaps = 2;
632 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
633 wm.lb_size = lb_size;
634 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
635 wm.num_heads = num_heads;
636
637 /* set for high clocks */
638 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
639 /* set for low clocks */
640 /* wm.yclk = low clk; wm.sclk = low clk */
641 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
642
643 /* possibly force display priority to high */
644 /* should really do this at mode validation time... */
645 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
646 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
647 !evergreen_check_latency_hiding(&wm) ||
648 (rdev->disp_priority == 2)) {
649 DRM_INFO("force priority to high\n");
650 priority_a_cnt |= PRIORITY_ALWAYS_ON;
651 priority_b_cnt |= PRIORITY_ALWAYS_ON;
652 }
653
654 a.full = dfixed_const(1000);
655 b.full = dfixed_const(mode->clock);
656 b.full = dfixed_div(b, a);
657 c.full = dfixed_const(latency_watermark_a);
658 c.full = dfixed_mul(c, b);
659 c.full = dfixed_mul(c, radeon_crtc->hsc);
660 c.full = dfixed_div(c, a);
661 a.full = dfixed_const(16);
662 c.full = dfixed_div(c, a);
663 priority_a_mark = dfixed_trunc(c);
664 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
665
666 a.full = dfixed_const(1000);
667 b.full = dfixed_const(mode->clock);
668 b.full = dfixed_div(b, a);
669 c.full = dfixed_const(latency_watermark_b);
670 c.full = dfixed_mul(c, b);
671 c.full = dfixed_mul(c, radeon_crtc->hsc);
672 c.full = dfixed_div(c, a);
673 a.full = dfixed_const(16);
674 c.full = dfixed_div(c, a);
675 priority_b_mark = dfixed_trunc(c);
676 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
677 }
678
679 /* select wm A */
680 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
681 tmp = arb_control3;
682 tmp &= ~LATENCY_WATERMARK_MASK(3);
683 tmp |= LATENCY_WATERMARK_MASK(1);
684 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
685 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
686 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
687 LATENCY_HIGH_WATERMARK(line_time)));
688 /* select wm B */
689 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
690 tmp &= ~LATENCY_WATERMARK_MASK(3);
691 tmp |= LATENCY_WATERMARK_MASK(2);
692 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
693 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
694 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
695 LATENCY_HIGH_WATERMARK(line_time)));
696 /* restore original selection */
697 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
698
699 /* write the priority marks */
700 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
701 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
702
703}
704
0ca2ab52 705void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 706{
f9d9c362
AD		 707 struct drm_display_mode *mode0 = NULL;
708 struct drm_display_mode *mode1 = NULL;
709 u32 num_heads = 0, lb_size;
710 int i;
711
712 radeon_update_display_priority(rdev);
713
714 for (i = 0; i < rdev->num_crtc; i++) {
715 if (rdev->mode_info.crtcs[i]->base.enabled)
716 num_heads++;
717 }
718 for (i = 0; i < rdev->num_crtc; i += 2) {
719 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
720 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
721 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
722 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
723 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
724 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
725 }
bcc1c2a1
AD		 726}
727
728static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
729{
730 unsigned i;
731 u32 tmp;
732
733 for (i = 0; i < rdev->usec_timeout; i++) {
734 /* read MC_STATUS */
735 tmp = RREG32(SRBM_STATUS) & 0x1F00;
736 if (!tmp)
737 return 0;
738 udelay(1);
739 }
740 return -1;
741}
742
743/*
744 * GART
745 */
0fcdb61e
AD		 746void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
747{
748 unsigned i;
749 u32 tmp;
750
751 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
752 for (i = 0; i < rdev->usec_timeout; i++) {
753 /* read MC_STATUS */
754 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
755 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
756 if (tmp == 2) {
757 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
758 return;
759 }
760 if (tmp) {
761 return;
762 }
763 udelay(1);
764 }
765}
766
bcc1c2a1
AD		 767int evergreen_pcie_gart_enable(struct radeon_device *rdev)
768{
769 u32 tmp;
0fcdb61e 770 int r;
bcc1c2a1
AD		 771
772 if (rdev->gart.table.vram.robj == NULL) {
773 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
774 return -EINVAL;
775 }
776 r = radeon_gart_table_vram_pin(rdev);
777 if (r)
778 return r;
82568565 779 radeon_gart_restore(rdev);
bcc1c2a1
AD		 780 /* Setup L2 cache */
781 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
782 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
783 EFFECTIVE_L2_QUEUE_SIZE(7));
784 WREG32(VM_L2_CNTL2, 0);
785 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
786 /* Setup TLB control */
787 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
788 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
789 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
790 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
791 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
792 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
793 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
794 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
795 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
796 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
797 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
798 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
799 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
800 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
801 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
802 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
803 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
804 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 805 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 806
0fcdb61e 807 evergreen_pcie_gart_tlb_flush(rdev);
bcc1c2a1
AD		 808 rdev->gart.ready = true;
809 return 0;
810}
811
812void evergreen_pcie_gart_disable(struct radeon_device *rdev)
813{
814 u32 tmp;
0fcdb61e 815 int r;
bcc1c2a1
AD		 816
817 /* Disable all tables */
0fcdb61e
AD		 818 WREG32(VM_CONTEXT0_CNTL, 0);
819 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 820
821 /* Setup L2 cache */
822 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
823 EFFECTIVE_L2_QUEUE_SIZE(7));
824 WREG32(VM_L2_CNTL2, 0);
825 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
826 /* Setup TLB control */
827 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
828 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
829 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
830 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
831 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
832 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
833 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
834 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
835 if (rdev->gart.table.vram.robj) {
836 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
837 if (likely(r == 0)) {
838 radeon_bo_kunmap(rdev->gart.table.vram.robj);
839 radeon_bo_unpin(rdev->gart.table.vram.robj);
840 radeon_bo_unreserve(rdev->gart.table.vram.robj);
841 }
842 }
843}
844
845void evergreen_pcie_gart_fini(struct radeon_device *rdev)
846{
847 evergreen_pcie_gart_disable(rdev);
848 radeon_gart_table_vram_free(rdev);
849 radeon_gart_fini(rdev);
850}
851
852
853void evergreen_agp_enable(struct radeon_device *rdev)
854{
855 u32 tmp;
bcc1c2a1
AD		 856
857 /* Setup L2 cache */
858 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
859 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
860 EFFECTIVE_L2_QUEUE_SIZE(7));
861 WREG32(VM_L2_CNTL2, 0);
862 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
863 /* Setup TLB control */
864 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
865 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
866 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
867 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
868 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
869 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
870 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
871 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
872 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
873 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
874 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 875 WREG32(VM_CONTEXT0_CNTL, 0);
876 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 877}
878
879static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
880{
881 save->vga_control[0] = RREG32(D1VGA_CONTROL);
882 save->vga_control[1] = RREG32(D2VGA_CONTROL);
883 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
884 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
885 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
886 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
887 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
888 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
889 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
890 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
18007401
AD		 891 if (!(rdev->flags & RADEON_IS_IGP)) {
892 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
893 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
894 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
895 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
896 }
bcc1c2a1
AD		 897
898 /* Stop all video */
899 WREG32(VGA_RENDER_CONTROL, 0);
900 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
901 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
18007401
AD		 902 if (!(rdev->flags & RADEON_IS_IGP)) {
903 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
904 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
905 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
906 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
907 }
bcc1c2a1
AD		 908 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
909 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 910 if (!(rdev->flags & RADEON_IS_IGP)) {
911 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
912 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
913 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
914 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
915 }
bcc1c2a1
AD		 916 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
917 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 918 if (!(rdev->flags & RADEON_IS_IGP)) {
919 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
920 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
921 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
922 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
923 }
bcc1c2a1
AD		 924
925 WREG32(D1VGA_CONTROL, 0);
926 WREG32(D2VGA_CONTROL, 0);
927 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
928 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
929 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
930 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
931}
932
933static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
934{
935 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
936 upper_32_bits(rdev->mc.vram_start));
937 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
938 upper_32_bits(rdev->mc.vram_start));
939 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
940 (u32)rdev->mc.vram_start);
941 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
942 (u32)rdev->mc.vram_start);
943
944 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
945 upper_32_bits(rdev->mc.vram_start));
946 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
947 upper_32_bits(rdev->mc.vram_start));
948 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
949 (u32)rdev->mc.vram_start);
950 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
951 (u32)rdev->mc.vram_start);
952
18007401
AD		 953 if (!(rdev->flags & RADEON_IS_IGP)) {
954 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
955 upper_32_bits(rdev->mc.vram_start));
956 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
957 upper_32_bits(rdev->mc.vram_start));
958 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
959 (u32)rdev->mc.vram_start);
960 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
961 (u32)rdev->mc.vram_start);
962
963 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
964 upper_32_bits(rdev->mc.vram_start));
965 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
966 upper_32_bits(rdev->mc.vram_start));
967 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
968 (u32)rdev->mc.vram_start);
969 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
970 (u32)rdev->mc.vram_start);
971
972 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
973 upper_32_bits(rdev->mc.vram_start));
974 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
975 upper_32_bits(rdev->mc.vram_start));
976 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
977 (u32)rdev->mc.vram_start);
978 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
979 (u32)rdev->mc.vram_start);
980
981 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
982 upper_32_bits(rdev->mc.vram_start));
983 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
984 upper_32_bits(rdev->mc.vram_start));
985 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
986 (u32)rdev->mc.vram_start);
987 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
988 (u32)rdev->mc.vram_start);
989 }
bcc1c2a1
AD		 990
991 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
992 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
993 /* Unlock host access */
994 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
995 mdelay(1);
996 /* Restore video state */
997 WREG32(D1VGA_CONTROL, save->vga_control[0]);
998 WREG32(D2VGA_CONTROL, save->vga_control[1]);
999 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1000 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1001 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1002 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1003 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1004 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
18007401
AD		 1005 if (!(rdev->flags & RADEON_IS_IGP)) {
1006 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1009 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1010 }
bcc1c2a1
AD		 1011 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1012 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
18007401
AD		 1013 if (!(rdev->flags & RADEON_IS_IGP)) {
1014 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1015 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1016 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1017 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1018 }
bcc1c2a1
AD		 1019 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1020 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 1021 if (!(rdev->flags & RADEON_IS_IGP)) {
1022 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1023 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1024 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1025 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1026 }
bcc1c2a1
AD		 1027 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1028}
1029
1030static void evergreen_mc_program(struct radeon_device *rdev)
1031{
1032 struct evergreen_mc_save save;
1033 u32 tmp;
1034 int i, j;
1035
1036 /* Initialize HDP */
1037 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1038 WREG32((0x2c14 + j), 0x00000000);
1039 WREG32((0x2c18 + j), 0x00000000);
1040 WREG32((0x2c1c + j), 0x00000000);
1041 WREG32((0x2c20 + j), 0x00000000);
1042 WREG32((0x2c24 + j), 0x00000000);
1043 }
1044 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1045
1046 evergreen_mc_stop(rdev, &save);
1047 if (evergreen_mc_wait_for_idle(rdev)) {
1048 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1049 }
1050 /* Lockout access through VGA aperture*/
1051 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1052 /* Update configuration */
1053 if (rdev->flags & RADEON_IS_AGP) {
1054 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1055 /* VRAM before AGP */
1056 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1057 rdev->mc.vram_start >> 12);
1058 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059 rdev->mc.gtt_end >> 12);
1060 } else {
1061 /* VRAM after AGP */
1062 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063 rdev->mc.gtt_start >> 12);
1064 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065 rdev->mc.vram_end >> 12);
1066 }
1067 } else {
1068 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1069 rdev->mc.vram_start >> 12);
1070 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1071 rdev->mc.vram_end >> 12);
1072 }
1073 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1074 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1075 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1076 WREG32(MC_VM_FB_LOCATION, tmp);
1077 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1078 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
46fcd2b3 1079 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1080 if (rdev->flags & RADEON_IS_AGP) {
1081 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1082 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1083 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1084 } else {
1085 WREG32(MC_VM_AGP_BASE, 0);
1086 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1087 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1088 }
1089 if (evergreen_mc_wait_for_idle(rdev)) {
1090 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1091 }
1092 evergreen_mc_resume(rdev, &save);
1093 /* we need to own VRAM, so turn off the VGA renderer here
1094 * to stop it overwriting our objects */
1095 rv515_vga_render_disable(rdev);
1096}
1097
bcc1c2a1
AD		 1098/*
1099 * CP.
1100 */
bcc1c2a1
AD		 1101
1102static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1103{
fe251e2f
AD		 1104 const __be32 *fw_data;
1105 int i;
1106
1107 if (!rdev->me_fw || !rdev->pfp_fw)
1108 return -EINVAL;
bcc1c2a1 1109
fe251e2f
AD		 1110 r700_cp_stop(rdev);
1111 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1112
1113 fw_data = (const __be32 *)rdev->pfp_fw->data;
1114 WREG32(CP_PFP_UCODE_ADDR, 0);
1115 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1116 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1117 WREG32(CP_PFP_UCODE_ADDR, 0);
1118
1119 fw_data = (const __be32 *)rdev->me_fw->data;
1120 WREG32(CP_ME_RAM_WADDR, 0);
1121 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1122 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1123
1124 WREG32(CP_PFP_UCODE_ADDR, 0);
1125 WREG32(CP_ME_RAM_WADDR, 0);
1126 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1127 return 0;
1128}
1129
7e7b41d2
AD		 1130static int evergreen_cp_start(struct radeon_device *rdev)
1131{
2281a378 1132 int r, i;
7e7b41d2
AD		 1133 uint32_t cp_me;
1134
1135 r = radeon_ring_lock(rdev, 7);
1136 if (r) {
1137 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1138 return r;
1139 }
1140 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1141 radeon_ring_write(rdev, 0x1);
1142 radeon_ring_write(rdev, 0x0);
1143 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1144 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1145 radeon_ring_write(rdev, 0);
1146 radeon_ring_write(rdev, 0);
1147 radeon_ring_unlock_commit(rdev);
1148
1149 cp_me = 0xff;
1150 WREG32(CP_ME_CNTL, cp_me);
1151
2281a378 1152 r = radeon_ring_lock(rdev, evergreen_default_size + 15);
7e7b41d2
AD		 1153 if (r) {
1154 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1155 return r;
1156 }
2281a378
AD		 1157
1158 /* setup clear context state */
1159 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1160 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1161
1162 for (i = 0; i < evergreen_default_size; i++)
1163 radeon_ring_write(rdev, evergreen_default_state[i]);
1164
1165 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1166 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1167
1168 /* set clear context state */
1169 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1170 radeon_ring_write(rdev, 0);
1171
1172 /* SQ_VTX_BASE_VTX_LOC */
1173 radeon_ring_write(rdev, 0xc0026f00);
1174 radeon_ring_write(rdev, 0x00000000);
1175 radeon_ring_write(rdev, 0x00000000);
1176 radeon_ring_write(rdev, 0x00000000);
1177
1178 /* Clear consts */
1179 radeon_ring_write(rdev, 0xc0036f00);
1180 radeon_ring_write(rdev, 0x00000bc4);
1181 radeon_ring_write(rdev, 0xffffffff);
1182 radeon_ring_write(rdev, 0xffffffff);
1183 radeon_ring_write(rdev, 0xffffffff);
1184
7e7b41d2
AD		 1185 radeon_ring_unlock_commit(rdev);
1186
1187 return 0;
1188}
1189
fe251e2f
AD		 1190int evergreen_cp_resume(struct radeon_device *rdev)
1191{
1192 u32 tmp;
1193 u32 rb_bufsz;
1194 int r;
1195
1196 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1197 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1198 SOFT_RESET_PA |
1199 SOFT_RESET_SH |
1200 SOFT_RESET_VGT |
1201 SOFT_RESET_SX));
1202 RREG32(GRBM_SOFT_RESET);
1203 mdelay(15);
1204 WREG32(GRBM_SOFT_RESET, 0);
1205 RREG32(GRBM_SOFT_RESET);
1206
1207 /* Set ring buffer size */
1208 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
724c80e1 1209 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1210#ifdef __BIG_ENDIAN
1211 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1212#endif
fe251e2f
AD		 1213 WREG32(CP_RB_CNTL, tmp);
1214 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1215
1216 /* Set the write pointer delay */
1217 WREG32(CP_RB_WPTR_DELAY, 0);
1218
1219 /* Initialize the ring buffer's read and write pointers */
1220 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1221 WREG32(CP_RB_RPTR_WR, 0);
1222 WREG32(CP_RB_WPTR, 0);
724c80e1
AD		 1223
1224 /* set the wb address wether it's enabled or not */
1225 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1226 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1227 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1228
1229 if (rdev->wb.enabled)
1230 WREG32(SCRATCH_UMSK, 0xff);
1231 else {
1232 tmp |= RB_NO_UPDATE;
1233 WREG32(SCRATCH_UMSK, 0);
1234 }
1235
fe251e2f
AD		 1236 mdelay(1);
1237 WREG32(CP_RB_CNTL, tmp);
1238
1239 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1240 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1241
1242 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1243 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1244
7e7b41d2 1245 evergreen_cp_start(rdev);
fe251e2f
AD		 1246 rdev->cp.ready = true;
1247 r = radeon_ring_test(rdev);
1248 if (r) {
1249 rdev->cp.ready = false;
1250 return r;
1251 }
1252 return 0;
1253}
bcc1c2a1
AD		 1254
1255/*
1256 * Core functions
1257 */
32fcdbf4
AD		 1258static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1259 u32 num_tile_pipes,
bcc1c2a1
AD		 1260 u32 num_backends,
1261 u32 backend_disable_mask)
1262{
1263 u32 backend_map = 0;
32fcdbf4
AD		 1264 u32 enabled_backends_mask = 0;
1265 u32 enabled_backends_count = 0;
1266 u32 cur_pipe;
1267 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1268 u32 cur_backend = 0;
1269 u32 i;
1270 bool force_no_swizzle;
1271
1272 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1273 num_tile_pipes = EVERGREEN_MAX_PIPES;
1274 if (num_tile_pipes < 1)
1275 num_tile_pipes = 1;
1276 if (num_backends > EVERGREEN_MAX_BACKENDS)
1277 num_backends = EVERGREEN_MAX_BACKENDS;
1278 if (num_backends < 1)
1279 num_backends = 1;
1280
1281 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1282 if (((backend_disable_mask >> i) & 1) == 0) {
1283 enabled_backends_mask |= (1 << i);
1284 ++enabled_backends_count;
1285 }
1286 if (enabled_backends_count == num_backends)
1287 break;
1288 }
1289
1290 if (enabled_backends_count == 0) {
1291 enabled_backends_mask = 1;
1292 enabled_backends_count = 1;
1293 }
1294
1295 if (enabled_backends_count != num_backends)
1296 num_backends = enabled_backends_count;
1297
1298 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1299 switch (rdev->family) {
1300 case CHIP_CEDAR:
1301 case CHIP_REDWOOD:
d5e455e4 1302 case CHIP_PALM:
32fcdbf4
AD		 1303 force_no_swizzle = false;
1304 break;
1305 case CHIP_CYPRESS:
1306 case CHIP_HEMLOCK:
1307 case CHIP_JUNIPER:
1308 default:
1309 force_no_swizzle = true;
1310 break;
1311 }
1312 if (force_no_swizzle) {
1313 bool last_backend_enabled = false;
1314
1315 force_no_swizzle = false;
1316 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1317 if (((enabled_backends_mask >> i) & 1) == 1) {
1318 if (last_backend_enabled)
1319 force_no_swizzle = true;
1320 last_backend_enabled = true;
1321 } else
1322 last_backend_enabled = false;
1323 }
1324 }
1325
1326 switch (num_tile_pipes) {
1327 case 1:
1328 case 3:
1329 case 5:
1330 case 7:
1331 DRM_ERROR("odd number of pipes!\n");
1332 break;
1333 case 2:
1334 swizzle_pipe[0] = 0;
1335 swizzle_pipe[1] = 1;
1336 break;
1337 case 4:
1338 if (force_no_swizzle) {
1339 swizzle_pipe[0] = 0;
1340 swizzle_pipe[1] = 1;
1341 swizzle_pipe[2] = 2;
1342 swizzle_pipe[3] = 3;
1343 } else {
1344 swizzle_pipe[0] = 0;
1345 swizzle_pipe[1] = 2;
1346 swizzle_pipe[2] = 1;
1347 swizzle_pipe[3] = 3;
1348 }
1349 break;
1350 case 6:
1351 if (force_no_swizzle) {
1352 swizzle_pipe[0] = 0;
1353 swizzle_pipe[1] = 1;
1354 swizzle_pipe[2] = 2;
1355 swizzle_pipe[3] = 3;
1356 swizzle_pipe[4] = 4;
1357 swizzle_pipe[5] = 5;
1358 } else {
1359 swizzle_pipe[0] = 0;
1360 swizzle_pipe[1] = 2;
1361 swizzle_pipe[2] = 4;
1362 swizzle_pipe[3] = 1;
1363 swizzle_pipe[4] = 3;
1364 swizzle_pipe[5] = 5;
1365 }
1366 break;
1367 case 8:
1368 if (force_no_swizzle) {
1369 swizzle_pipe[0] = 0;
1370 swizzle_pipe[1] = 1;
1371 swizzle_pipe[2] = 2;
1372 swizzle_pipe[3] = 3;
1373 swizzle_pipe[4] = 4;
1374 swizzle_pipe[5] = 5;
1375 swizzle_pipe[6] = 6;
1376 swizzle_pipe[7] = 7;
1377 } else {
1378 swizzle_pipe[0] = 0;
1379 swizzle_pipe[1] = 2;
1380 swizzle_pipe[2] = 4;
1381 swizzle_pipe[3] = 6;
1382 swizzle_pipe[4] = 1;
1383 swizzle_pipe[5] = 3;
1384 swizzle_pipe[6] = 5;
1385 swizzle_pipe[7] = 7;
1386 }
1387 break;
1388 }
1389
1390 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1391 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1392 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1393
1394 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1395
1396 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1397 }
bcc1c2a1
AD		 1398
1399 return backend_map;
1400}
bcc1c2a1 1401
9535ab73
AD		 1402static void evergreen_program_channel_remap(struct radeon_device *rdev)
1403{
1404 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1405
1406 tmp = RREG32(MC_SHARED_CHMAP);
1407 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1408 case 0:
1409 case 1:
1410 case 2:
1411 case 3:
1412 default:
1413 /* default mapping */
1414 mc_shared_chremap = 0x00fac688;
1415 break;
1416 }
1417
1418 switch (rdev->family) {
1419 case CHIP_HEMLOCK:
1420 case CHIP_CYPRESS:
1421 tcp_chan_steer_lo = 0x54763210;
1422 tcp_chan_steer_hi = 0x0000ba98;
1423 break;
1424 case CHIP_JUNIPER:
1425 case CHIP_REDWOOD:
1426 case CHIP_CEDAR:
d5e455e4 1427 case CHIP_PALM:
9535ab73
AD		 1428 default:
1429 tcp_chan_steer_lo = 0x76543210;
1430 tcp_chan_steer_hi = 0x0000ba98;
1431 break;
1432 }
1433
1434 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1435 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1436 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1437}
1438
bcc1c2a1
AD		 1439static void evergreen_gpu_init(struct radeon_device *rdev)
1440{
32fcdbf4
AD		 1441 u32 cc_rb_backend_disable = 0;
1442 u32 cc_gc_shader_pipe_config;
1443 u32 gb_addr_config = 0;
1444 u32 mc_shared_chmap, mc_arb_ramcfg;
1445 u32 gb_backend_map;
1446 u32 grbm_gfx_index;
1447 u32 sx_debug_1;
1448 u32 smx_dc_ctl0;
1449 u32 sq_config;
1450 u32 sq_lds_resource_mgmt;
1451 u32 sq_gpr_resource_mgmt_1;
1452 u32 sq_gpr_resource_mgmt_2;
1453 u32 sq_gpr_resource_mgmt_3;
1454 u32 sq_thread_resource_mgmt;
1455 u32 sq_thread_resource_mgmt_2;
1456 u32 sq_stack_resource_mgmt_1;
1457 u32 sq_stack_resource_mgmt_2;
1458 u32 sq_stack_resource_mgmt_3;
1459 u32 vgt_cache_invalidation;
1460 u32 hdp_host_path_cntl;
1461 int i, j, num_shader_engines, ps_thread_count;
1462
1463 switch (rdev->family) {
1464 case CHIP_CYPRESS:
1465 case CHIP_HEMLOCK:
1466 rdev->config.evergreen.num_ses = 2;
1467 rdev->config.evergreen.max_pipes = 4;
1468 rdev->config.evergreen.max_tile_pipes = 8;
1469 rdev->config.evergreen.max_simds = 10;
1470 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1471 rdev->config.evergreen.max_gprs = 256;
1472 rdev->config.evergreen.max_threads = 248;
1473 rdev->config.evergreen.max_gs_threads = 32;
1474 rdev->config.evergreen.max_stack_entries = 512;
1475 rdev->config.evergreen.sx_num_of_sets = 4;
1476 rdev->config.evergreen.sx_max_export_size = 256;
1477 rdev->config.evergreen.sx_max_export_pos_size = 64;
1478 rdev->config.evergreen.sx_max_export_smx_size = 192;
1479 rdev->config.evergreen.max_hw_contexts = 8;
1480 rdev->config.evergreen.sq_num_cf_insts = 2;
1481
1482 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1483 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1484 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1485 break;
1486 case CHIP_JUNIPER:
1487 rdev->config.evergreen.num_ses = 1;
1488 rdev->config.evergreen.max_pipes = 4;
1489 rdev->config.evergreen.max_tile_pipes = 4;
1490 rdev->config.evergreen.max_simds = 10;
1491 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1492 rdev->config.evergreen.max_gprs = 256;
1493 rdev->config.evergreen.max_threads = 248;
1494 rdev->config.evergreen.max_gs_threads = 32;
1495 rdev->config.evergreen.max_stack_entries = 512;
1496 rdev->config.evergreen.sx_num_of_sets = 4;
1497 rdev->config.evergreen.sx_max_export_size = 256;
1498 rdev->config.evergreen.sx_max_export_pos_size = 64;
1499 rdev->config.evergreen.sx_max_export_smx_size = 192;
1500 rdev->config.evergreen.max_hw_contexts = 8;
1501 rdev->config.evergreen.sq_num_cf_insts = 2;
1502
1503 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1504 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1505 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1506 break;
1507 case CHIP_REDWOOD:
1508 rdev->config.evergreen.num_ses = 1;
1509 rdev->config.evergreen.max_pipes = 4;
1510 rdev->config.evergreen.max_tile_pipes = 4;
1511 rdev->config.evergreen.max_simds = 5;
1512 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1513 rdev->config.evergreen.max_gprs = 256;
1514 rdev->config.evergreen.max_threads = 248;
1515 rdev->config.evergreen.max_gs_threads = 32;
1516 rdev->config.evergreen.max_stack_entries = 256;
1517 rdev->config.evergreen.sx_num_of_sets = 4;
1518 rdev->config.evergreen.sx_max_export_size = 256;
1519 rdev->config.evergreen.sx_max_export_pos_size = 64;
1520 rdev->config.evergreen.sx_max_export_smx_size = 192;
1521 rdev->config.evergreen.max_hw_contexts = 8;
1522 rdev->config.evergreen.sq_num_cf_insts = 2;
1523
1524 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1525 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1526 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1527 break;
1528 case CHIP_CEDAR:
1529 default:
1530 rdev->config.evergreen.num_ses = 1;
1531 rdev->config.evergreen.max_pipes = 2;
1532 rdev->config.evergreen.max_tile_pipes = 2;
1533 rdev->config.evergreen.max_simds = 2;
1534 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1535 rdev->config.evergreen.max_gprs = 256;
1536 rdev->config.evergreen.max_threads = 192;
1537 rdev->config.evergreen.max_gs_threads = 16;
1538 rdev->config.evergreen.max_stack_entries = 256;
1539 rdev->config.evergreen.sx_num_of_sets = 4;
1540 rdev->config.evergreen.sx_max_export_size = 128;
1541 rdev->config.evergreen.sx_max_export_pos_size = 32;
1542 rdev->config.evergreen.sx_max_export_smx_size = 96;
1543 rdev->config.evergreen.max_hw_contexts = 4;
1544 rdev->config.evergreen.sq_num_cf_insts = 1;
1545
d5e455e4
AD		 1546 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1547 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1548 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1549 break;
1550 case CHIP_PALM:
1551 rdev->config.evergreen.num_ses = 1;
1552 rdev->config.evergreen.max_pipes = 2;
1553 rdev->config.evergreen.max_tile_pipes = 2;
1554 rdev->config.evergreen.max_simds = 2;
1555 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1556 rdev->config.evergreen.max_gprs = 256;
1557 rdev->config.evergreen.max_threads = 192;
1558 rdev->config.evergreen.max_gs_threads = 16;
1559 rdev->config.evergreen.max_stack_entries = 256;
1560 rdev->config.evergreen.sx_num_of_sets = 4;
1561 rdev->config.evergreen.sx_max_export_size = 128;
1562 rdev->config.evergreen.sx_max_export_pos_size = 32;
1563 rdev->config.evergreen.sx_max_export_smx_size = 96;
1564 rdev->config.evergreen.max_hw_contexts = 4;
1565 rdev->config.evergreen.sq_num_cf_insts = 1;
1566
32fcdbf4
AD		 1567 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1568 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1569 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1570 break;
1571 }
1572
1573 /* Initialize HDP */
1574 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1575 WREG32((0x2c14 + j), 0x00000000);
1576 WREG32((0x2c18 + j), 0x00000000);
1577 WREG32((0x2c1c + j), 0x00000000);
1578 WREG32((0x2c20 + j), 0x00000000);
1579 WREG32((0x2c24 + j), 0x00000000);
1580 }
1581
1582 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1583
1584 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1585
1586 cc_gc_shader_pipe_config |=
1587 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1588 & EVERGREEN_MAX_PIPES_MASK);
1589 cc_gc_shader_pipe_config |=
1590 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1591 & EVERGREEN_MAX_SIMDS_MASK);
1592
1593 cc_rb_backend_disable =
1594 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1595 & EVERGREEN_MAX_BACKENDS_MASK);
1596
1597
1598 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1599 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1600
1601 switch (rdev->config.evergreen.max_tile_pipes) {
1602 case 1:
1603 default:
1604 gb_addr_config |= NUM_PIPES(0);
1605 break;
1606 case 2:
1607 gb_addr_config |= NUM_PIPES(1);
1608 break;
1609 case 4:
1610 gb_addr_config |= NUM_PIPES(2);
1611 break;
1612 case 8:
1613 gb_addr_config |= NUM_PIPES(3);
1614 break;
1615 }
1616
1617 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1618 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1619 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1620 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1621 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1622 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1623
1624 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1625 gb_addr_config |= ROW_SIZE(2);
1626 else
1627 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1628
1629 if (rdev->ddev->pdev->device == 0x689e) {
1630 u32 efuse_straps_4;
1631 u32 efuse_straps_3;
1632 u8 efuse_box_bit_131_124;
1633
1634 WREG32(RCU_IND_INDEX, 0x204);
1635 efuse_straps_4 = RREG32(RCU_IND_DATA);
1636 WREG32(RCU_IND_INDEX, 0x203);
1637 efuse_straps_3 = RREG32(RCU_IND_DATA);
1638 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1639
1640 switch(efuse_box_bit_131_124) {
1641 case 0x00:
1642 gb_backend_map = 0x76543210;
1643 break;
1644 case 0x55:
1645 gb_backend_map = 0x77553311;
1646 break;
1647 case 0x56:
1648 gb_backend_map = 0x77553300;
1649 break;
1650 case 0x59:
1651 gb_backend_map = 0x77552211;
1652 break;
1653 case 0x66:
1654 gb_backend_map = 0x77443300;
1655 break;
1656 case 0x99:
1657 gb_backend_map = 0x66552211;
1658 break;
1659 case 0x5a:
1660 gb_backend_map = 0x77552200;
1661 break;
1662 case 0xaa:
1663 gb_backend_map = 0x66442200;
1664 break;
1665 case 0x95:
1666 gb_backend_map = 0x66553311;
1667 break;
1668 default:
1669 DRM_ERROR("bad backend map, using default\n");
1670 gb_backend_map =
1671 evergreen_get_tile_pipe_to_backend_map(rdev,
1672 rdev->config.evergreen.max_tile_pipes,
1673 rdev->config.evergreen.max_backends,
1674 ((EVERGREEN_MAX_BACKENDS_MASK <<
1675 rdev->config.evergreen.max_backends) &
1676 EVERGREEN_MAX_BACKENDS_MASK));
1677 break;
1678 }
1679 } else if (rdev->ddev->pdev->device == 0x68b9) {
1680 u32 efuse_straps_3;
1681 u8 efuse_box_bit_127_124;
1682
1683 WREG32(RCU_IND_INDEX, 0x203);
1684 efuse_straps_3 = RREG32(RCU_IND_DATA);
d31dba58 1685 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
32fcdbf4
AD		 1686
1687 switch(efuse_box_bit_127_124) {
1688 case 0x0:
1689 gb_backend_map = 0x00003210;
1690 break;
1691 case 0x5:
1692 case 0x6:
1693 case 0x9:
1694 case 0xa:
1695 gb_backend_map = 0x00003311;
1696 break;
1697 default:
1698 DRM_ERROR("bad backend map, using default\n");
1699 gb_backend_map =
1700 evergreen_get_tile_pipe_to_backend_map(rdev,
1701 rdev->config.evergreen.max_tile_pipes,
1702 rdev->config.evergreen.max_backends,
1703 ((EVERGREEN_MAX_BACKENDS_MASK <<
1704 rdev->config.evergreen.max_backends) &
1705 EVERGREEN_MAX_BACKENDS_MASK));
1706 break;
1707 }
b741be82
AD		 1708 } else {
1709 switch (rdev->family) {
1710 case CHIP_CYPRESS:
1711 case CHIP_HEMLOCK:
1712 gb_backend_map = 0x66442200;
1713 break;
1714 case CHIP_JUNIPER:
1715 gb_backend_map = 0x00006420;
1716 break;
1717 default:
1718 gb_backend_map =
1719 evergreen_get_tile_pipe_to_backend_map(rdev,
1720 rdev->config.evergreen.max_tile_pipes,
1721 rdev->config.evergreen.max_backends,
1722 ((EVERGREEN_MAX_BACKENDS_MASK <<
1723 rdev->config.evergreen.max_backends) &
1724 EVERGREEN_MAX_BACKENDS_MASK));
1725 }
1726 }
32fcdbf4 1727
1aa52bd3
AD		 1728 /* setup tiling info dword. gb_addr_config is not adequate since it does
1729 * not have bank info, so create a custom tiling dword.
1730 * bits 3:0 num_pipes
1731 * bits 7:4 num_banks
1732 * bits 11:8 group_size
1733 * bits 15:12 row_size
1734 */
1735 rdev->config.evergreen.tile_config = 0;
1736 switch (rdev->config.evergreen.max_tile_pipes) {
1737 case 1:
1738 default:
1739 rdev->config.evergreen.tile_config |= (0 << 0);
1740 break;
1741 case 2:
1742 rdev->config.evergreen.tile_config |= (1 << 0);
1743 break;
1744 case 4:
1745 rdev->config.evergreen.tile_config |= (2 << 0);
1746 break;
1747 case 8:
1748 rdev->config.evergreen.tile_config |= (3 << 0);
1749 break;
1750 }
1751 rdev->config.evergreen.tile_config |=
1752 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1753 rdev->config.evergreen.tile_config |=
1754 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1755 rdev->config.evergreen.tile_config |=
1756 ((gb_addr_config & 0x30000000) >> 28) << 12;
1757
32fcdbf4
AD		 1758 WREG32(GB_BACKEND_MAP, gb_backend_map);
1759 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1760 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1761 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1762
9535ab73
AD		 1763 evergreen_program_channel_remap(rdev);
1764
32fcdbf4
AD		 1765 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1766 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1767
1768 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1769 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1770 u32 sp = cc_gc_shader_pipe_config;
1771 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1772
1773 if (i == num_shader_engines) {
1774 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1775 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1776 }
1777
1778 WREG32(GRBM_GFX_INDEX, gfx);
1779 WREG32(RLC_GFX_INDEX, gfx);
1780
1781 WREG32(CC_RB_BACKEND_DISABLE, rb);
1782 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1783 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1784 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1785 }
1786
1787 grbm_gfx_index |= SE_BROADCAST_WRITES;
1788 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1789 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1790
1791 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1792 WREG32(CGTS_TCC_DISABLE, 0);
1793 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1794 WREG32(CGTS_USER_TCC_DISABLE, 0);
1795
1796 /* set HW defaults for 3D engine */
1797 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1798 ROQ_IB2_START(0x2b)));
1799
1800 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1801
1802 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1803 SYNC_GRADIENT |
1804 SYNC_WALKER |
1805 SYNC_ALIGNER));
1806
1807 sx_debug_1 = RREG32(SX_DEBUG_1);
1808 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1809 WREG32(SX_DEBUG_1, sx_debug_1);
1810
1811
1812 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1813 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1814 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1815 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1816
1817 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1818 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1819 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1820
1821 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1822 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1823 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1824
1825 WREG32(VGT_NUM_INSTANCES, 1);
1826 WREG32(SPI_CONFIG_CNTL, 0);
1827 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1828 WREG32(CP_PERFMON_CNTL, 0);
1829
1830 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1831 FETCH_FIFO_HIWATER(0x4) |
1832 DONE_FIFO_HIWATER(0xe0) |
1833 ALU_UPDATE_FIFO_HIWATER(0x8)));
1834
1835 sq_config = RREG32(SQ_CONFIG);
1836 sq_config &= ~(PS_PRIO(3) |
1837 VS_PRIO(3) |
1838 GS_PRIO(3) |
1839 ES_PRIO(3));
1840 sq_config |= (VC_ENABLE |
1841 EXPORT_SRC_C |
1842 PS_PRIO(0) |
1843 VS_PRIO(1) |
1844 GS_PRIO(2) |
1845 ES_PRIO(3));
1846
d5e455e4
AD		 1847 switch (rdev->family) {
1848 case CHIP_CEDAR:
1849 case CHIP_PALM:
32fcdbf4
AD		 1850 /* no vertex cache */
1851 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 1852 break;
1853 default:
1854 break;
1855 }
32fcdbf4
AD		 1856
1857 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1858
1859 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1860 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1861 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1862 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1863 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1864 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1865 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1866
d5e455e4
AD		 1867 switch (rdev->family) {
1868 case CHIP_CEDAR:
1869 case CHIP_PALM:
32fcdbf4 1870 ps_thread_count = 96;
d5e455e4
AD		 1871 break;
1872 default:
32fcdbf4 1873 ps_thread_count = 128;
d5e455e4
AD		 1874 break;
1875 }
32fcdbf4
AD		 1876
1877 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 1878 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1879 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1880 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1881 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1882 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 1883
1884 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1885 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1886 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1887 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1888 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1889 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1890
1891 WREG32(SQ_CONFIG, sq_config);
1892 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1893 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1894 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1895 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1896 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1897 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1898 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1899 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1900 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1901 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1902
1903 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1904 FORCE_EOV_MAX_REZ_CNT(255)));
1905
d5e455e4
AD		 1906 switch (rdev->family) {
1907 case CHIP_CEDAR:
1908 case CHIP_PALM:
32fcdbf4 1909 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 1910 break;
1911 default:
32fcdbf4 1912 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 1913 break;
1914 }
32fcdbf4
AD		 1915 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1916 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1917
1918 WREG32(VGT_GS_VERTEX_REUSE, 16);
1919 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1920
60a4a3e0
AD		 1921 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1922 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1923
32fcdbf4
AD		 1924 WREG32(CB_PERF_CTR0_SEL_0, 0);
1925 WREG32(CB_PERF_CTR0_SEL_1, 0);
1926 WREG32(CB_PERF_CTR1_SEL_0, 0);
1927 WREG32(CB_PERF_CTR1_SEL_1, 0);
1928 WREG32(CB_PERF_CTR2_SEL_0, 0);
1929 WREG32(CB_PERF_CTR2_SEL_1, 0);
1930 WREG32(CB_PERF_CTR3_SEL_0, 0);
1931 WREG32(CB_PERF_CTR3_SEL_1, 0);
1932
60a4a3e0
AD		 1933 /* clear render buffer base addresses */
1934 WREG32(CB_COLOR0_BASE, 0);
1935 WREG32(CB_COLOR1_BASE, 0);
1936 WREG32(CB_COLOR2_BASE, 0);
1937 WREG32(CB_COLOR3_BASE, 0);
1938 WREG32(CB_COLOR4_BASE, 0);
1939 WREG32(CB_COLOR5_BASE, 0);
1940 WREG32(CB_COLOR6_BASE, 0);
1941 WREG32(CB_COLOR7_BASE, 0);
1942 WREG32(CB_COLOR8_BASE, 0);
1943 WREG32(CB_COLOR9_BASE, 0);
1944 WREG32(CB_COLOR10_BASE, 0);
1945 WREG32(CB_COLOR11_BASE, 0);
1946
1947 /* set the shader const cache sizes to 0 */
1948 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
1949 WREG32(i, 0);
1950 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
1951 WREG32(i, 0);
1952
32fcdbf4
AD		 1953 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1954 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1955
1956 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1957
1958 udelay(50);
1959
bcc1c2a1
AD		 1960}
1961
1962int evergreen_mc_init(struct radeon_device *rdev)
1963{
bcc1c2a1
AD		 1964 u32 tmp;
1965 int chansize, numchan;
bcc1c2a1
AD		 1966
1967 /* Get VRAM informations */
1968 rdev->mc.vram_is_ddr = true;
1969 tmp = RREG32(MC_ARB_RAMCFG);
1970 if (tmp & CHANSIZE_OVERRIDE) {
1971 chansize = 16;
1972 } else if (tmp & CHANSIZE_MASK) {
1973 chansize = 64;
1974 } else {
1975 chansize = 32;
1976 }
1977 tmp = RREG32(MC_SHARED_CHMAP);
1978 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1979 case 0:
1980 default:
1981 numchan = 1;
1982 break;
1983 case 1:
1984 numchan = 2;
1985 break;
1986 case 2:
1987 numchan = 4;
1988 break;
1989 case 3:
1990 numchan = 8;
1991 break;
1992 }
1993 rdev->mc.vram_width = numchan * chansize;
1994 /* Could aper size report 0 ? */
01d73a69
JC		 1995 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1996 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 1997 /* Setup GPU memory space */
6eb18f8b
AD		 1998 if (rdev->flags & RADEON_IS_IGP) {
1999 /* size in bytes on fusion */
2000 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2001 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2002 } else {
2003 /* size in MB on evergreen */
2004 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2005 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2006 }
51e5fcd3 2007 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 2008 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
0ef0c1f7 2009 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2010 radeon_update_bandwidth_info(rdev);
2011
bcc1c2a1
AD		 2012 return 0;
2013}
d594e46a 2014
225758d8
JG		 2015bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2016{
2017 /* FIXME: implement for evergreen */
2018 return false;
2019}
2020
747943ea 2021static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 2022{
747943ea
AD		 2023 struct evergreen_mc_save save;
2024 u32 srbm_reset = 0;
2025 u32 grbm_reset = 0;
2026
2027 dev_info(rdev->dev, "GPU softreset \n");
2028 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2029 RREG32(GRBM_STATUS));
2030 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2031 RREG32(GRBM_STATUS_SE0));
2032 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2033 RREG32(GRBM_STATUS_SE1));
2034 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2035 RREG32(SRBM_STATUS));
2036 evergreen_mc_stop(rdev, &save);
2037 if (evergreen_mc_wait_for_idle(rdev)) {
2038 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2039 }
2040 /* Disable CP parsing/prefetching */
2041 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2042
2043 /* reset all the gfx blocks */
2044 grbm_reset = (SOFT_RESET_CP |
2045 SOFT_RESET_CB |
2046 SOFT_RESET_DB |
2047 SOFT_RESET_PA |
2048 SOFT_RESET_SC |
2049 SOFT_RESET_SPI |
2050 SOFT_RESET_SH |
2051 SOFT_RESET_SX |
2052 SOFT_RESET_TC |
2053 SOFT_RESET_TA |
2054 SOFT_RESET_VC |
2055 SOFT_RESET_VGT);
2056
2057 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2058 WREG32(GRBM_SOFT_RESET, grbm_reset);
2059 (void)RREG32(GRBM_SOFT_RESET);
2060 udelay(50);
2061 WREG32(GRBM_SOFT_RESET, 0);
2062 (void)RREG32(GRBM_SOFT_RESET);
2063
2064 /* reset all the system blocks */
2065 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
2066
2067 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
2068 WREG32(SRBM_SOFT_RESET, srbm_reset);
2069 (void)RREG32(SRBM_SOFT_RESET);
2070 udelay(50);
2071 WREG32(SRBM_SOFT_RESET, 0);
2072 (void)RREG32(SRBM_SOFT_RESET);
2073 /* Wait a little for things to settle down */
2074 udelay(50);
2075 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2076 RREG32(GRBM_STATUS));
2077 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2078 RREG32(GRBM_STATUS_SE0));
2079 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2080 RREG32(GRBM_STATUS_SE1));
2081 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2082 RREG32(SRBM_STATUS));
2083 /* After reset we need to reinit the asic as GPU often endup in an
2084 * incoherent state.
2085 */
2086 atom_asic_init(rdev->mode_info.atom_context);
2087 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2088 return 0;
2089}
2090
a2d07b74 2091int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2092{
747943ea
AD		 2093 return evergreen_gpu_soft_reset(rdev);
2094}
2095
45f9a39b
AD		 2096/* Interrupts */
2097
2098u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2099{
2100 switch (crtc) {
2101 case 0:
2102 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2103 case 1:
2104 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2105 case 2:
2106 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2107 case 3:
2108 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2109 case 4:
2110 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2111 case 5:
2112 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2113 default:
2114 return 0;
2115 }
2116}
2117
2118void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2119{
2120 u32 tmp;
2121
3555e53b 2122 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2123 WREG32(GRBM_INT_CNTL, 0);
2124 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2125 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 2126 if (!(rdev->flags & RADEON_IS_IGP)) {
2127 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2128 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2129 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2130 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2131 }
45f9a39b
AD		 2132
2133 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2134 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
18007401
AD		 2135 if (!(rdev->flags & RADEON_IS_IGP)) {
2136 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2137 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2138 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2139 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2140 }
45f9a39b
AD		 2141
2142 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2143 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2144
2145 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2146 WREG32(DC_HPD1_INT_CONTROL, tmp);
2147 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2148 WREG32(DC_HPD2_INT_CONTROL, tmp);
2149 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2150 WREG32(DC_HPD3_INT_CONTROL, tmp);
2151 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2152 WREG32(DC_HPD4_INT_CONTROL, tmp);
2153 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2154 WREG32(DC_HPD5_INT_CONTROL, tmp);
2155 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2156 WREG32(DC_HPD6_INT_CONTROL, tmp);
2157
2158}
2159
2160int evergreen_irq_set(struct radeon_device *rdev)
2161{
2162 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2163 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2164 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2165 u32 grbm_int_cntl = 0;
45f9a39b
AD		 2166
2167 if (!rdev->irq.installed) {
fce7d61b 2168 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2169 return -EINVAL;
2170 }
2171 /* don't enable anything if the ih is disabled */
2172 if (!rdev->ih.enabled) {
2173 r600_disable_interrupts(rdev);
2174 /* force the active interrupt state to all disabled */
2175 evergreen_disable_interrupt_state(rdev);
2176 return 0;
2177 }
2178
2179 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2180 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2181 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2182 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2183 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2184 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2185
2186 if (rdev->irq.sw_int) {
2187 DRM_DEBUG("evergreen_irq_set: sw int\n");
2188 cp_int_cntl |= RB_INT_ENABLE;
d0f8a854 2189 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
45f9a39b
AD		 2190 }
2191 if (rdev->irq.crtc_vblank_int[0]) {
2192 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2193 crtc1 |= VBLANK_INT_MASK;
2194 }
2195 if (rdev->irq.crtc_vblank_int[1]) {
2196 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2197 crtc2 |= VBLANK_INT_MASK;
2198 }
2199 if (rdev->irq.crtc_vblank_int[2]) {
2200 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2201 crtc3 |= VBLANK_INT_MASK;
2202 }
2203 if (rdev->irq.crtc_vblank_int[3]) {
2204 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2205 crtc4 |= VBLANK_INT_MASK;
2206 }
2207 if (rdev->irq.crtc_vblank_int[4]) {
2208 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2209 crtc5 |= VBLANK_INT_MASK;
2210 }
2211 if (rdev->irq.crtc_vblank_int[5]) {
2212 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2213 crtc6 |= VBLANK_INT_MASK;
2214 }
2215 if (rdev->irq.hpd[0]) {
2216 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2217 hpd1 |= DC_HPDx_INT_EN;
2218 }
2219 if (rdev->irq.hpd[1]) {
2220 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2221 hpd2 |= DC_HPDx_INT_EN;
2222 }
2223 if (rdev->irq.hpd[2]) {
2224 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2225 hpd3 |= DC_HPDx_INT_EN;
2226 }
2227 if (rdev->irq.hpd[3]) {
2228 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2229 hpd4 |= DC_HPDx_INT_EN;
2230 }
2231 if (rdev->irq.hpd[4]) {
2232 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2233 hpd5 |= DC_HPDx_INT_EN;
2234 }
2235 if (rdev->irq.hpd[5]) {
2236 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2237 hpd6 |= DC_HPDx_INT_EN;
2238 }
2031f77c
AD		 2239 if (rdev->irq.gui_idle) {
2240 DRM_DEBUG("gui idle\n");
2241 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2242 }
45f9a39b
AD		 2243
2244 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2245 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2246
2247 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2248 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
18007401
AD		 2249 if (!(rdev->flags & RADEON_IS_IGP)) {
2250 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2251 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2252 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2253 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2254 }
45f9a39b
AD		 2255
2256 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2257 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2258 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2259 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2260 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2261 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2262
bcc1c2a1
AD		 2263 return 0;
2264}
2265
45f9a39b
AD		 2266static inline void evergreen_irq_ack(struct radeon_device *rdev,
2267 u32 *disp_int,
2268 u32 *disp_int_cont,
2269 u32 *disp_int_cont2,
2270 u32 *disp_int_cont3,
2271 u32 *disp_int_cont4,
2272 u32 *disp_int_cont5)
2273{
2274 u32 tmp;
2275
2276 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2277 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2278 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2279 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2280 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2281 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2282
2283 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2284 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2285 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2286 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2287
2288 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2289 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2290 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
2291 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2292
2293 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2294 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2295 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2296 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2297
2298 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2299 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2300 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2301 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2302
2303 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2304 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2305 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2306 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2307
2308 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2309 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2310 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2311 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2312
2313 if (*disp_int & DC_HPD1_INTERRUPT) {
2314 tmp = RREG32(DC_HPD1_INT_CONTROL);
2315 tmp |= DC_HPDx_INT_ACK;
2316 WREG32(DC_HPD1_INT_CONTROL, tmp);
2317 }
2318 if (*disp_int_cont & DC_HPD2_INTERRUPT) {
2319 tmp = RREG32(DC_HPD2_INT_CONTROL);
2320 tmp |= DC_HPDx_INT_ACK;
2321 WREG32(DC_HPD2_INT_CONTROL, tmp);
2322 }
2323 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
2324 tmp = RREG32(DC_HPD3_INT_CONTROL);
2325 tmp |= DC_HPDx_INT_ACK;
2326 WREG32(DC_HPD3_INT_CONTROL, tmp);
2327 }
2328 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
2329 tmp = RREG32(DC_HPD4_INT_CONTROL);
2330 tmp |= DC_HPDx_INT_ACK;
2331 WREG32(DC_HPD4_INT_CONTROL, tmp);
2332 }
2333 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
2334 tmp = RREG32(DC_HPD5_INT_CONTROL);
2335 tmp |= DC_HPDx_INT_ACK;
2336 WREG32(DC_HPD5_INT_CONTROL, tmp);
2337 }
2338 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
2339 tmp = RREG32(DC_HPD5_INT_CONTROL);
2340 tmp |= DC_HPDx_INT_ACK;
2341 WREG32(DC_HPD6_INT_CONTROL, tmp);
2342 }
2343}
2344
2345void evergreen_irq_disable(struct radeon_device *rdev)
2346{
2347 u32 disp_int, disp_int_cont, disp_int_cont2;
2348 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2349
2350 r600_disable_interrupts(rdev);
2351 /* Wait and acknowledge irq */
2352 mdelay(1);
2353 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2354 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2355 evergreen_disable_interrupt_state(rdev);
2356}
2357
2358static void evergreen_irq_suspend(struct radeon_device *rdev)
2359{
2360 evergreen_irq_disable(rdev);
2361 r600_rlc_stop(rdev);
2362}
2363
2364static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2365{
2366 u32 wptr, tmp;
2367
724c80e1
AD		 2368 if (rdev->wb.enabled)
2369 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2370 else
2371 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2372
2373 if (wptr & RB_OVERFLOW) {
2374 /* When a ring buffer overflow happen start parsing interrupt
2375 * from the last not overwritten vector (wptr + 16). Hopefully
2376 * this should allow us to catchup.
2377 */
2378 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2379 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2380 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2381 tmp = RREG32(IH_RB_CNTL);
2382 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2383 WREG32(IH_RB_CNTL, tmp);
2384 }
2385 return (wptr & rdev->ih.ptr_mask);
2386}
2387
2388int evergreen_irq_process(struct radeon_device *rdev)
2389{
2390 u32 wptr = evergreen_get_ih_wptr(rdev);
2391 u32 rptr = rdev->ih.rptr;
2392 u32 src_id, src_data;
2393 u32 ring_index;
2394 u32 disp_int, disp_int_cont, disp_int_cont2;
2395 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2396 unsigned long flags;
2397 bool queue_hotplug = false;
2398
2399 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2400 if (!rdev->ih.enabled)
2401 return IRQ_NONE;
2402
2403 spin_lock_irqsave(&rdev->ih.lock, flags);
2404
2405 if (rptr == wptr) {
2406 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2407 return IRQ_NONE;
2408 }
2409 if (rdev->shutdown) {
2410 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2411 return IRQ_NONE;
2412 }
2413
2414restart_ih:
2415 /* display interrupts */
2416 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2417 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2418
2419 rdev->ih.wptr = wptr;
2420 while (rptr != wptr) {
2421 /* wptr/rptr are in bytes! */
2422 ring_index = rptr / 4;
2423 src_id = rdev->ih.ring[ring_index] & 0xff;
2424 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2425
2426 switch (src_id) {
2427 case 1: /* D1 vblank/vline */
2428 switch (src_data) {
2429 case 0: /* D1 vblank */
2430 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2431 drm_handle_vblank(rdev->ddev, 0);
f5d8e0eb 2432 rdev->pm.vblank_sync = true;
45f9a39b
AD		 2433 wake_up(&rdev->irq.vblank_queue);
2434 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2435 DRM_DEBUG("IH: D1 vblank\n");
2436 }
2437 break;
2438 case 1: /* D1 vline */
2439 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2440 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2441 DRM_DEBUG("IH: D1 vline\n");
2442 }
2443 break;
2444 default:
2445 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2446 break;
2447 }
2448 break;
2449 case 2: /* D2 vblank/vline */
2450 switch (src_data) {
2451 case 0: /* D2 vblank */
2452 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2453 drm_handle_vblank(rdev->ddev, 1);
f5d8e0eb 2454 rdev->pm.vblank_sync = true;
45f9a39b
AD		 2455 wake_up(&rdev->irq.vblank_queue);
2456 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2457 DRM_DEBUG("IH: D2 vblank\n");
2458 }
2459 break;
2460 case 1: /* D2 vline */
2461 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2462 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2463 DRM_DEBUG("IH: D2 vline\n");
2464 }
2465 break;
2466 default:
2467 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2468 break;
2469 }
2470 break;
2471 case 3: /* D3 vblank/vline */
2472 switch (src_data) {
2473 case 0: /* D3 vblank */
2474 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2475 drm_handle_vblank(rdev->ddev, 2);
f5d8e0eb 2476 rdev->pm.vblank_sync = true;
45f9a39b
AD		 2477 wake_up(&rdev->irq.vblank_queue);
2478 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2479 DRM_DEBUG("IH: D3 vblank\n");
2480 }
2481 break;
2482 case 1: /* D3 vline */
2483 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2484 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2485 DRM_DEBUG("IH: D3 vline\n");
2486 }
2487 break;
2488 default:
2489 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2490 break;
2491 }
2492 break;
2493 case 4: /* D4 vblank/vline */
2494 switch (src_data) {
2495 case 0: /* D4 vblank */
2496 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2497 drm_handle_vblank(rdev->ddev, 3);
f5d8e0eb 2498 rdev->pm.vblank_sync = true;
45f9a39b
AD		 2499 wake_up(&rdev->irq.vblank_queue);
2500 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2501 DRM_DEBUG("IH: D4 vblank\n");
2502 }
2503 break;
2504 case 1: /* D4 vline */
2505 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2506 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2507 DRM_DEBUG("IH: D4 vline\n");
2508 }
2509 break;
2510 default:
2511 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2512 break;
2513 }
2514 break;
2515 case 5: /* D5 vblank/vline */
2516 switch (src_data) {
2517 case 0: /* D5 vblank */
2518 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2519 drm_handle_vblank(rdev->ddev, 4);
f5d8e0eb 2520 rdev->pm.vblank_sync = true;
45f9a39b
AD		 2521 wake_up(&rdev->irq.vblank_queue);
2522 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2523 DRM_DEBUG("IH: D5 vblank\n");
2524 }
2525 break;
2526 case 1: /* D5 vline */
2527 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2528 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2529 DRM_DEBUG("IH: D5 vline\n");
2530 }
2531 break;
2532 default:
2533 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2534 break;
2535 }
2536 break;
2537 case 6: /* D6 vblank/vline */
2538 switch (src_data) {
2539 case 0: /* D6 vblank */
2540 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2541 drm_handle_vblank(rdev->ddev, 5);
f5d8e0eb 2542 rdev->pm.vblank_sync = true;
45f9a39b
AD		 2543 wake_up(&rdev->irq.vblank_queue);
2544 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2545 DRM_DEBUG("IH: D6 vblank\n");
2546 }
2547 break;
2548 case 1: /* D6 vline */
2549 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2550 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2551 DRM_DEBUG("IH: D6 vline\n");
2552 }
2553 break;
2554 default:
2555 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2556 break;
2557 }
2558 break;
2559 case 42: /* HPD hotplug */
2560 switch (src_data) {
2561 case 0:
2562 if (disp_int & DC_HPD1_INTERRUPT) {
2563 disp_int &= ~DC_HPD1_INTERRUPT;
2564 queue_hotplug = true;
2565 DRM_DEBUG("IH: HPD1\n");
2566 }
2567 break;
2568 case 1:
2569 if (disp_int_cont & DC_HPD2_INTERRUPT) {
2570 disp_int_cont &= ~DC_HPD2_INTERRUPT;
2571 queue_hotplug = true;
2572 DRM_DEBUG("IH: HPD2\n");
2573 }
2574 break;
2575 case 2:
2576 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
2577 disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2578 queue_hotplug = true;
2579 DRM_DEBUG("IH: HPD3\n");
2580 }
2581 break;
2582 case 3:
2583 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
2584 disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2585 queue_hotplug = true;
2586 DRM_DEBUG("IH: HPD4\n");
2587 }
2588 break;
2589 case 4:
2590 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
2591 disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2592 queue_hotplug = true;
2593 DRM_DEBUG("IH: HPD5\n");
2594 }
2595 break;
2596 case 5:
2597 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
2598 disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2599 queue_hotplug = true;
2600 DRM_DEBUG("IH: HPD6\n");
2601 }
2602 break;
2603 default:
2604 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2605 break;
2606 }
2607 break;
2608 case 176: /* CP_INT in ring buffer */
2609 case 177: /* CP_INT in IB1 */
2610 case 178: /* CP_INT in IB2 */
2611 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2612 radeon_fence_process(rdev);
2613 break;
2614 case 181: /* CP EOP event */
2615 DRM_DEBUG("IH: CP EOP\n");
d0f8a854 2616 radeon_fence_process(rdev);
45f9a39b 2617 break;
2031f77c
AD		 2618 case 233: /* GUI IDLE */
2619 DRM_DEBUG("IH: CP EOP\n");
2620 rdev->pm.gui_idle = true;
2621 wake_up(&rdev->irq.idle_queue);
2622 break;
45f9a39b
AD		 2623 default:
2624 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2625 break;
2626 }
2627
2628 /* wptr/rptr are in bytes! */
2629 rptr += 16;
2630 rptr &= rdev->ih.ptr_mask;
2631 }
2632 /* make sure wptr hasn't changed while processing */
2633 wptr = evergreen_get_ih_wptr(rdev);
2634 if (wptr != rdev->ih.wptr)
2635 goto restart_ih;
2636 if (queue_hotplug)
2637 queue_work(rdev->wq, &rdev->hotplug_work);
2638 rdev->ih.rptr = rptr;
2639 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2640 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2641 return IRQ_HANDLED;
2642}
2643
bcc1c2a1
AD		 2644static int evergreen_startup(struct radeon_device *rdev)
2645{
bcc1c2a1
AD		 2646 int r;
2647
2648 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2649 r = r600_init_microcode(rdev);
2650 if (r) {
2651 DRM_ERROR("Failed to load firmware!\n");
2652 return r;
2653 }
2654 }
fe251e2f 2655
bcc1c2a1 2656 evergreen_mc_program(rdev);
bcc1c2a1 2657 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 2658 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 2659 } else {
2660 r = evergreen_pcie_gart_enable(rdev);
2661 if (r)
2662 return r;
2663 }
bcc1c2a1 2664 evergreen_gpu_init(rdev);
bcc1c2a1 2665
d7ccd8fc 2666 r = evergreen_blit_init(rdev);
bcc1c2a1 2667 if (r) {
d7ccd8fc
AD		 2668 evergreen_blit_fini(rdev);
2669 rdev->asic->copy = NULL;
2670 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 2671 }
2672
724c80e1
AD		 2673 /* allocate wb buffer */
2674 r = radeon_wb_init(rdev);
2675 if (r)
2676 return r;
2677
bcc1c2a1
AD		 2678 /* Enable IRQ */
2679 r = r600_irq_init(rdev);
2680 if (r) {
2681 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2682 radeon_irq_kms_fini(rdev);
2683 return r;
2684 }
45f9a39b 2685 evergreen_irq_set(rdev);
bcc1c2a1
AD		 2686
2687 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2688 if (r)
2689 return r;
2690 r = evergreen_cp_load_microcode(rdev);
2691 if (r)
2692 return r;
fe251e2f 2693 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 2694 if (r)
2695 return r;
fe251e2f 2696
bcc1c2a1
AD		 2697 return 0;
2698}
2699
2700int evergreen_resume(struct radeon_device *rdev)
2701{
2702 int r;
2703
2704 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2705 * posting will perform necessary task to bring back GPU into good
2706 * shape.
2707 */
2708 /* post card */
2709 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1
AD		 2710
2711 r = evergreen_startup(rdev);
2712 if (r) {
2713 DRM_ERROR("r600 startup failed on resume\n");
2714 return r;
2715 }
fe251e2f 2716
bcc1c2a1
AD		 2717 r = r600_ib_test(rdev);
2718 if (r) {
2719 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2720 return r;
2721 }
fe251e2f 2722
bcc1c2a1
AD		 2723 return r;
2724
2725}
2726
2727int evergreen_suspend(struct radeon_device *rdev)
2728{
bcc1c2a1 2729 int r;
d7ccd8fc 2730
bcc1c2a1
AD		 2731 /* FIXME: we should wait for ring to be empty */
2732 r700_cp_stop(rdev);
2733 rdev->cp.ready = false;
45f9a39b 2734 evergreen_irq_suspend(rdev);
724c80e1 2735 radeon_wb_disable(rdev);
bcc1c2a1 2736 evergreen_pcie_gart_disable(rdev);
d7ccd8fc 2737
bcc1c2a1
AD		 2738 /* unpin shaders bo */
2739 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2740 if (likely(r == 0)) {
2741 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2742 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2743 }
d7ccd8fc
AD		 2744
2745 return 0;
2746}
2747
2748int evergreen_copy_blit(struct radeon_device *rdev,
2749 uint64_t src_offset, uint64_t dst_offset,
2750 unsigned num_pages, struct radeon_fence *fence)
2751{
2752 int r;
2753
2754 mutex_lock(&rdev->r600_blit.mutex);
2755 rdev->r600_blit.vb_ib = NULL;
2756 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2757 if (r) {
2758 if (rdev->r600_blit.vb_ib)
2759 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2760 mutex_unlock(&rdev->r600_blit.mutex);
2761 return r;
2762 }
2763 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2764 evergreen_blit_done_copy(rdev, fence);
2765 mutex_unlock(&rdev->r600_blit.mutex);
bcc1c2a1
AD		 2766 return 0;
2767}
2768
2769static bool evergreen_card_posted(struct radeon_device *rdev)
2770{
2771 u32 reg;
2772
2773 /* first check CRTCs */
18007401
AD		 2774 if (rdev->flags & RADEON_IS_IGP)
2775 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2776 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2777 else
2778 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2779 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2780 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2781 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2782 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2783 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
bcc1c2a1
AD		 2784 if (reg & EVERGREEN_CRTC_MASTER_EN)
2785 return true;
2786
2787 /* then check MEM_SIZE, in case the crtcs are off */
2788 if (RREG32(CONFIG_MEMSIZE))
2789 return true;
2790
2791 return false;
2792}
2793
2794/* Plan is to move initialization in that function and use
2795 * helper function so that radeon_device_init pretty much
2796 * do nothing more than calling asic specific function. This
2797 * should also allow to remove a bunch of callback function
2798 * like vram_info.
2799 */
2800int evergreen_init(struct radeon_device *rdev)
2801{
2802 int r;
2803
2804 r = radeon_dummy_page_init(rdev);
2805 if (r)
2806 return r;
2807 /* This don't do much */
2808 r = radeon_gem_init(rdev);
2809 if (r)
2810 return r;
2811 /* Read BIOS */
2812 if (!radeon_get_bios(rdev)) {
2813 if (ASIC_IS_AVIVO(rdev))
2814 return -EINVAL;
2815 }
2816 /* Must be an ATOMBIOS */
2817 if (!rdev->is_atom_bios) {
2818 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2819 return -EINVAL;
2820 }
2821 r = radeon_atombios_init(rdev);
2822 if (r)
2823 return r;
2824 /* Post card if necessary */
2825 if (!evergreen_card_posted(rdev)) {
2826 if (!rdev->bios) {
2827 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2828 return -EINVAL;
2829 }
2830 DRM_INFO("GPU not posted. posting now...\n");
2831 atom_asic_init(rdev->mode_info.atom_context);
2832 }
2833 /* Initialize scratch registers */
2834 r600_scratch_init(rdev);
2835 /* Initialize surface registers */
2836 radeon_surface_init(rdev);
2837 /* Initialize clocks */
2838 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 2839 /* Fence driver */
2840 r = radeon_fence_driver_init(rdev);
2841 if (r)
2842 return r;
d594e46a
JG		 2843 /* initialize AGP */
2844 if (rdev->flags & RADEON_IS_AGP) {
2845 r = radeon_agp_init(rdev);
2846 if (r)
2847 radeon_agp_disable(rdev);
2848 }
2849 /* initialize memory controller */
bcc1c2a1
AD		 2850 r = evergreen_mc_init(rdev);
2851 if (r)
2852 return r;
2853 /* Memory manager */
2854 r = radeon_bo_init(rdev);
2855 if (r)
2856 return r;
45f9a39b 2857
bcc1c2a1
AD		 2858 r = radeon_irq_kms_init(rdev);
2859 if (r)
2860 return r;
2861
2862 rdev->cp.ring_obj = NULL;
2863 r600_ring_init(rdev, 1024 * 1024);
2864
2865 rdev->ih.ring_obj = NULL;
2866 r600_ih_ring_init(rdev, 64 * 1024);
2867
2868 r = r600_pcie_gart_init(rdev);
2869 if (r)
2870 return r;
0fcdb61e 2871
148a03bc 2872 rdev->accel_working = true;
bcc1c2a1
AD		 2873 r = evergreen_startup(rdev);
2874 if (r) {
fe251e2f
AD		 2875 dev_err(rdev->dev, "disabling GPU acceleration\n");
2876 r700_cp_fini(rdev);
fe251e2f 2877 r600_irq_fini(rdev);
724c80e1 2878 radeon_wb_fini(rdev);
fe251e2f 2879 radeon_irq_kms_fini(rdev);
0fcdb61e 2880 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2881 rdev->accel_working = false;
2882 }
2883 if (rdev->accel_working) {
2884 r = radeon_ib_pool_init(rdev);
2885 if (r) {
2886 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2887 rdev->accel_working = false;
2888 }
2889 r = r600_ib_test(rdev);
2890 if (r) {
2891 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2892 rdev->accel_working = false;
2893 }
2894 }
2895 return 0;
2896}
2897
2898void evergreen_fini(struct radeon_device *rdev)
2899{
d7ccd8fc 2900 evergreen_blit_fini(rdev);
45f9a39b 2901 r700_cp_fini(rdev);
bcc1c2a1 2902 r600_irq_fini(rdev);
724c80e1 2903 radeon_wb_fini(rdev);
bcc1c2a1 2904 radeon_irq_kms_fini(rdev);
bcc1c2a1 2905 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 2906 radeon_gem_fini(rdev);
2907 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 2908 radeon_agp_fini(rdev);
2909 radeon_bo_fini(rdev);
2910 radeon_atombios_fini(rdev);
2911 kfree(rdev->bios);
2912 rdev->bios = NULL;
2913 radeon_dummy_page_fini(rdev);
2914}
Linux kernel - Deliverables
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