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drm/radeon/kms: remove unused cp callbacks from radeon_asic
[deliverable/linux.git] / drivers / gpu / drm / radeon / evergreen.c
CommitLineData
bcc1c2a1
AD		 1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/platform_device.h>
5a0e3ad6 26#include <linux/slab.h>
bcc1c2a1
AD		 27#include "drmP.h"
28#include "radeon.h"
e6990375 29#include "radeon_asic.h"
bcc1c2a1 30#include "radeon_drm.h"
0fcdb61e 31#include "evergreend.h"
bcc1c2a1
AD		 32#include "atom.h"
33#include "avivod.h"
34#include "evergreen_reg.h"
2281a378 35#include "evergreen_blit_shaders.h"
bcc1c2a1 36
fe251e2f
AD		 37#define EVERGREEN_PFP_UCODE_SIZE 1120
38#define EVERGREEN_PM4_UCODE_SIZE 1376
39
bcc1c2a1
AD		 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev);
b07759bf 42void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
1b37078b
AD		 43extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
44 int ring, u32 cp_int_cntl);
bcc1c2a1 45
285484e2
JG		 46void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
47 unsigned *bankh, unsigned *mtaspect,
48 unsigned *tile_split)
49{
50 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
51 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
52 *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
53 *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
54 switch (*bankw) {
55 default:
56 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
57 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
58 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
59 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
60 }
61 switch (*bankh) {
62 default:
63 case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
64 case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
65 case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
66 case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
67 }
68 switch (*mtaspect) {
69 default:
70 case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
71 case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
72 case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
73 case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
74 }
75}
76
d054ac16
AD		 77void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
78{
79 u16 ctl, v;
80 int cap, err;
81
82 cap = pci_pcie_cap(rdev->pdev);
83 if (!cap)
84 return;
85
86 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
87 if (err)
88 return;
89
90 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
91
92 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
93 * to avoid hangs or perfomance issues
94 */
95 if ((v == 0) || (v == 6) || (v == 7)) {
96 ctl &= ~PCI_EXP_DEVCTL_READRQ;
97 ctl |= (2 << 12);
98 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
99 }
100}
101
3ae19b75
AD		 102void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
103{
104 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
105 int i;
106
107 if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
108 for (i = 0; i < rdev->usec_timeout; i++) {
109 if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
110 break;
111 udelay(1);
112 }
113 for (i = 0; i < rdev->usec_timeout; i++) {
114 if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
115 break;
116 udelay(1);
117 }
118 }
119}
120
6f34be50
AD		 121void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
122{
6f34be50
AD		 123 /* enable the pflip int */
124 radeon_irq_kms_pflip_irq_get(rdev, crtc);
125}
126
127void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
128{
129 /* disable the pflip int */
130 radeon_irq_kms_pflip_irq_put(rdev, crtc);
131}
132
133u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
134{
135 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
136 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
f6496479 137 int i;
6f34be50
AD		 138
139 /* Lock the graphics update lock */
140 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
141 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
142
143 /* update the scanout addresses */
144 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
145 upper_32_bits(crtc_base));
146 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
147 (u32)crtc_base);
148
149 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
150 upper_32_bits(crtc_base));
151 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
152 (u32)crtc_base);
153
154 /* Wait for update_pending to go high. */
f6496479
AD		 155 for (i = 0; i < rdev->usec_timeout; i++) {
156 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
157 break;
158 udelay(1);
159 }
6f34be50
AD		 160 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
161
162 /* Unlock the lock, so double-buffering can take place inside vblank */
163 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
164 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
165
166 /* Return current update_pending status: */
167 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
168}
169
21a8122a 170/* get temperature in millidegrees */
20d391d7 171int evergreen_get_temp(struct radeon_device *rdev)
21a8122a 172{
1c88d74f
AD		 173 u32 temp, toffset;
174 int actual_temp = 0;
67b3f823
AD		 175
176 if (rdev->family == CHIP_JUNIPER) {
177 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
178 TOFFSET_SHIFT;
179 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
180 TS0_ADC_DOUT_SHIFT;
181
182 if (toffset & 0x100)
183 actual_temp = temp / 2 - (0x200 - toffset);
184 else
185 actual_temp = temp / 2 + toffset;
186
187 actual_temp = actual_temp * 1000;
188
189 } else {
190 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
191 ASIC_T_SHIFT;
192
193 if (temp & 0x400)
194 actual_temp = -256;
195 else if (temp & 0x200)
196 actual_temp = 255;
197 else if (temp & 0x100) {
198 actual_temp = temp & 0x1ff;
199 actual_temp |= ~0x1ff;
200 } else
201 actual_temp = temp & 0xff;
202
203 actual_temp = (actual_temp * 1000) / 2;
204 }
21a8122a 205
67b3f823 206 return actual_temp;
21a8122a
AD		 207}
208
20d391d7 209int sumo_get_temp(struct radeon_device *rdev)
e33df25f
AD		 210{
211 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
20d391d7 212 int actual_temp = temp - 49;
e33df25f
AD		 213
214 return actual_temp * 1000;
215}
216
a4c9e2ee
AD		 217void sumo_pm_init_profile(struct radeon_device *rdev)
218{
219 int idx;
220
221 /* default */
222 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
223 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
224 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
225 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
226
227 /* low,mid sh/mh */
228 if (rdev->flags & RADEON_IS_MOBILITY)
229 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
230 else
231 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
232
233 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
234 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
235 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
236 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
237
238 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
239 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
240 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
241 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
242
243 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
244 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
245 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
246 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
247
248 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
249 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
250 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
251 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
252
253 /* high sh/mh */
254 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
255 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
256 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
257 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
258 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
259 rdev->pm.power_state[idx].num_clock_modes - 1;
260
261 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
262 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
263 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
264 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
265 rdev->pm.power_state[idx].num_clock_modes - 1;
266}
267
49e02b73
AD		 268void evergreen_pm_misc(struct radeon_device *rdev)
269{
a081a9d6
RM		 270 int req_ps_idx = rdev->pm.requested_power_state_index;
271 int req_cm_idx = rdev->pm.requested_clock_mode_index;
272 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
273 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
49e02b73 274
2feea49a 275 if (voltage->type == VOLTAGE_SW) {
a377e187
AD		 276 /* 0xff01 is a flag rather then an actual voltage */
277 if (voltage->voltage == 0xff01)
278 return;
2feea49a 279 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
8a83ec5e 280 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
4d60173f 281 rdev->pm.current_vddc = voltage->voltage;
2feea49a
AD		 282 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
283 }
a377e187
AD		 284 /* 0xff01 is a flag rather then an actual voltage */
285 if (voltage->vddci == 0xff01)
286 return;
2feea49a
AD		 287 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
288 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
289 rdev->pm.current_vddci = voltage->vddci;
290 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
4d60173f
AD		 291 }
292 }
49e02b73
AD		 293}
294
295void evergreen_pm_prepare(struct radeon_device *rdev)
296{
297 struct drm_device *ddev = rdev->ddev;
298 struct drm_crtc *crtc;
299 struct radeon_crtc *radeon_crtc;
300 u32 tmp;
301
302 /* disable any active CRTCs */
303 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
304 radeon_crtc = to_radeon_crtc(crtc);
305 if (radeon_crtc->enabled) {
306 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
307 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
308 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
309 }
310 }
311}
312
313void evergreen_pm_finish(struct radeon_device *rdev)
314{
315 struct drm_device *ddev = rdev->ddev;
316 struct drm_crtc *crtc;
317 struct radeon_crtc *radeon_crtc;
318 u32 tmp;
319
320 /* enable any active CRTCs */
321 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
322 radeon_crtc = to_radeon_crtc(crtc);
323 if (radeon_crtc->enabled) {
324 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
325 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
326 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
327 }
328 }
329}
330
bcc1c2a1
AD		 331bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
332{
333 bool connected = false;
0ca2ab52
AD		 334
335 switch (hpd) {
336 case RADEON_HPD_1:
337 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
338 connected = true;
339 break;
340 case RADEON_HPD_2:
341 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
342 connected = true;
343 break;
344 case RADEON_HPD_3:
345 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
346 connected = true;
347 break;
348 case RADEON_HPD_4:
349 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
350 connected = true;
351 break;
352 case RADEON_HPD_5:
353 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
354 connected = true;
355 break;
356 case RADEON_HPD_6:
357 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
358 connected = true;
359 break;
360 default:
361 break;
362 }
363
bcc1c2a1
AD		 364 return connected;
365}
366
367void evergreen_hpd_set_polarity(struct radeon_device *rdev,
368 enum radeon_hpd_id hpd)
369{
0ca2ab52
AD		 370 u32 tmp;
371 bool connected = evergreen_hpd_sense(rdev, hpd);
372
373 switch (hpd) {
374 case RADEON_HPD_1:
375 tmp = RREG32(DC_HPD1_INT_CONTROL);
376 if (connected)
377 tmp &= ~DC_HPDx_INT_POLARITY;
378 else
379 tmp |= DC_HPDx_INT_POLARITY;
380 WREG32(DC_HPD1_INT_CONTROL, tmp);
381 break;
382 case RADEON_HPD_2:
383 tmp = RREG32(DC_HPD2_INT_CONTROL);
384 if (connected)
385 tmp &= ~DC_HPDx_INT_POLARITY;
386 else
387 tmp |= DC_HPDx_INT_POLARITY;
388 WREG32(DC_HPD2_INT_CONTROL, tmp);
389 break;
390 case RADEON_HPD_3:
391 tmp = RREG32(DC_HPD3_INT_CONTROL);
392 if (connected)
393 tmp &= ~DC_HPDx_INT_POLARITY;
394 else
395 tmp |= DC_HPDx_INT_POLARITY;
396 WREG32(DC_HPD3_INT_CONTROL, tmp);
397 break;
398 case RADEON_HPD_4:
399 tmp = RREG32(DC_HPD4_INT_CONTROL);
400 if (connected)
401 tmp &= ~DC_HPDx_INT_POLARITY;
402 else
403 tmp |= DC_HPDx_INT_POLARITY;
404 WREG32(DC_HPD4_INT_CONTROL, tmp);
405 break;
406 case RADEON_HPD_5:
407 tmp = RREG32(DC_HPD5_INT_CONTROL);
408 if (connected)
409 tmp &= ~DC_HPDx_INT_POLARITY;
410 else
411 tmp |= DC_HPDx_INT_POLARITY;
412 WREG32(DC_HPD5_INT_CONTROL, tmp);
413 break;
414 case RADEON_HPD_6:
415 tmp = RREG32(DC_HPD6_INT_CONTROL);
416 if (connected)
417 tmp &= ~DC_HPDx_INT_POLARITY;
418 else
419 tmp |= DC_HPDx_INT_POLARITY;
420 WREG32(DC_HPD6_INT_CONTROL, tmp);
421 break;
422 default:
423 break;
424 }
bcc1c2a1
AD		 425}
426
427void evergreen_hpd_init(struct radeon_device *rdev)
428{
0ca2ab52
AD		 429 struct drm_device *dev = rdev->ddev;
430 struct drm_connector *connector;
431 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
432 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
bcc1c2a1 433
0ca2ab52
AD		 434 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
435 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
436 switch (radeon_connector->hpd.hpd) {
437 case RADEON_HPD_1:
438 WREG32(DC_HPD1_CONTROL, tmp);
439 rdev->irq.hpd[0] = true;
440 break;
441 case RADEON_HPD_2:
442 WREG32(DC_HPD2_CONTROL, tmp);
443 rdev->irq.hpd[1] = true;
444 break;
445 case RADEON_HPD_3:
446 WREG32(DC_HPD3_CONTROL, tmp);
447 rdev->irq.hpd[2] = true;
448 break;
449 case RADEON_HPD_4:
450 WREG32(DC_HPD4_CONTROL, tmp);
451 rdev->irq.hpd[3] = true;
452 break;
453 case RADEON_HPD_5:
454 WREG32(DC_HPD5_CONTROL, tmp);
455 rdev->irq.hpd[4] = true;
456 break;
457 case RADEON_HPD_6:
458 WREG32(DC_HPD6_CONTROL, tmp);
459 rdev->irq.hpd[5] = true;
460 break;
461 default:
462 break;
463 }
64912e99 464 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
0ca2ab52
AD		 465 }
466 if (rdev->irq.installed)
467 evergreen_irq_set(rdev);
bcc1c2a1
AD		 468}
469
0ca2ab52 470void evergreen_hpd_fini(struct radeon_device *rdev)
bcc1c2a1 471{
0ca2ab52
AD		 472 struct drm_device *dev = rdev->ddev;
473 struct drm_connector *connector;
474
475 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
476 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
477 switch (radeon_connector->hpd.hpd) {
478 case RADEON_HPD_1:
479 WREG32(DC_HPD1_CONTROL, 0);
480 rdev->irq.hpd[0] = false;
481 break;
482 case RADEON_HPD_2:
483 WREG32(DC_HPD2_CONTROL, 0);
484 rdev->irq.hpd[1] = false;
485 break;
486 case RADEON_HPD_3:
487 WREG32(DC_HPD3_CONTROL, 0);
488 rdev->irq.hpd[2] = false;
489 break;
490 case RADEON_HPD_4:
491 WREG32(DC_HPD4_CONTROL, 0);
492 rdev->irq.hpd[3] = false;
493 break;
494 case RADEON_HPD_5:
495 WREG32(DC_HPD5_CONTROL, 0);
496 rdev->irq.hpd[4] = false;
497 break;
498 case RADEON_HPD_6:
499 WREG32(DC_HPD6_CONTROL, 0);
500 rdev->irq.hpd[5] = false;
501 break;
502 default:
503 break;
504 }
505 }
bcc1c2a1
AD		 506}
507
f9d9c362
AD		 508/* watermark setup */
509
510static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
511 struct radeon_crtc *radeon_crtc,
512 struct drm_display_mode *mode,
513 struct drm_display_mode *other_mode)
514{
12dfc843 515 u32 tmp;
f9d9c362
AD		 516 /*
517 * Line Buffer Setup
518 * There are 3 line buffers, each one shared by 2 display controllers.
519 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
520 * the display controllers. The paritioning is done via one of four
521 * preset allocations specified in bits 2:0:
522 * first display controller
523 * 0 - first half of lb (3840 * 2)
524 * 1 - first 3/4 of lb (5760 * 2)
12dfc843 525 * 2 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 526 * 3 - first 1/4 of lb (1920 * 2)
527 * second display controller
528 * 4 - second half of lb (3840 * 2)
529 * 5 - second 3/4 of lb (5760 * 2)
12dfc843 530 * 6 - whole lb (7680 * 2), other crtc must be disabled
f9d9c362
AD		 531 * 7 - last 1/4 of lb (1920 * 2)
532 */
12dfc843
AD		 533 /* this can get tricky if we have two large displays on a paired group
534 * of crtcs. Ideally for multiple large displays we'd assign them to
535 * non-linked crtcs for maximum line buffer allocation.
536 */
537 if (radeon_crtc->base.enabled && mode) {
538 if (other_mode)
f9d9c362 539 tmp = 0; /* 1/2 */
12dfc843
AD		 540 else
541 tmp = 2; /* whole */
542 } else
543 tmp = 0;
f9d9c362
AD		 544
545 /* second controller of the pair uses second half of the lb */
546 if (radeon_crtc->crtc_id % 2)
547 tmp += 4;
548 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
549
12dfc843
AD		 550 if (radeon_crtc->base.enabled && mode) {
551 switch (tmp) {
552 case 0:
553 case 4:
554 default:
555 if (ASIC_IS_DCE5(rdev))
556 return 4096 * 2;
557 else
558 return 3840 * 2;
559 case 1:
560 case 5:
561 if (ASIC_IS_DCE5(rdev))
562 return 6144 * 2;
563 else
564 return 5760 * 2;
565 case 2:
566 case 6:
567 if (ASIC_IS_DCE5(rdev))
568 return 8192 * 2;
569 else
570 return 7680 * 2;
571 case 3:
572 case 7:
573 if (ASIC_IS_DCE5(rdev))
574 return 2048 * 2;
575 else
576 return 1920 * 2;
577 }
f9d9c362 578 }
12dfc843
AD		 579
580 /* controller not enabled, so no lb used */
581 return 0;
f9d9c362
AD		 582}
583
584static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
585{
586 u32 tmp = RREG32(MC_SHARED_CHMAP);
587
588 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
589 case 0:
590 default:
591 return 1;
592 case 1:
593 return 2;
594 case 2:
595 return 4;
596 case 3:
597 return 8;
598 }
599}
600
601struct evergreen_wm_params {
602 u32 dram_channels; /* number of dram channels */
603 u32 yclk; /* bandwidth per dram data pin in kHz */
604 u32 sclk; /* engine clock in kHz */
605 u32 disp_clk; /* display clock in kHz */
606 u32 src_width; /* viewport width */
607 u32 active_time; /* active display time in ns */
608 u32 blank_time; /* blank time in ns */
609 bool interlaced; /* mode is interlaced */
610 fixed20_12 vsc; /* vertical scale ratio */
611 u32 num_heads; /* number of active crtcs */
612 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
613 u32 lb_size; /* line buffer allocated to pipe */
614 u32 vtaps; /* vertical scaler taps */
615};
616
617static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
618{
619 /* Calculate DRAM Bandwidth and the part allocated to display. */
620 fixed20_12 dram_efficiency; /* 0.7 */
621 fixed20_12 yclk, dram_channels, bandwidth;
622 fixed20_12 a;
623
624 a.full = dfixed_const(1000);
625 yclk.full = dfixed_const(wm->yclk);
626 yclk.full = dfixed_div(yclk, a);
627 dram_channels.full = dfixed_const(wm->dram_channels * 4);
628 a.full = dfixed_const(10);
629 dram_efficiency.full = dfixed_const(7);
630 dram_efficiency.full = dfixed_div(dram_efficiency, a);
631 bandwidth.full = dfixed_mul(dram_channels, yclk);
632 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
633
634 return dfixed_trunc(bandwidth);
635}
636
637static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
638{
639 /* Calculate DRAM Bandwidth and the part allocated to display. */
640 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
641 fixed20_12 yclk, dram_channels, bandwidth;
642 fixed20_12 a;
643
644 a.full = dfixed_const(1000);
645 yclk.full = dfixed_const(wm->yclk);
646 yclk.full = dfixed_div(yclk, a);
647 dram_channels.full = dfixed_const(wm->dram_channels * 4);
648 a.full = dfixed_const(10);
649 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
650 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
651 bandwidth.full = dfixed_mul(dram_channels, yclk);
652 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
653
654 return dfixed_trunc(bandwidth);
655}
656
657static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
658{
659 /* Calculate the display Data return Bandwidth */
660 fixed20_12 return_efficiency; /* 0.8 */
661 fixed20_12 sclk, bandwidth;
662 fixed20_12 a;
663
664 a.full = dfixed_const(1000);
665 sclk.full = dfixed_const(wm->sclk);
666 sclk.full = dfixed_div(sclk, a);
667 a.full = dfixed_const(10);
668 return_efficiency.full = dfixed_const(8);
669 return_efficiency.full = dfixed_div(return_efficiency, a);
670 a.full = dfixed_const(32);
671 bandwidth.full = dfixed_mul(a, sclk);
672 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
673
674 return dfixed_trunc(bandwidth);
675}
676
677static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
678{
679 /* Calculate the DMIF Request Bandwidth */
680 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
681 fixed20_12 disp_clk, bandwidth;
682 fixed20_12 a;
683
684 a.full = dfixed_const(1000);
685 disp_clk.full = dfixed_const(wm->disp_clk);
686 disp_clk.full = dfixed_div(disp_clk, a);
687 a.full = dfixed_const(10);
688 disp_clk_request_efficiency.full = dfixed_const(8);
689 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
690 a.full = dfixed_const(32);
691 bandwidth.full = dfixed_mul(a, disp_clk);
692 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
693
694 return dfixed_trunc(bandwidth);
695}
696
697static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
698{
699 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
700 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
701 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
702 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
703
704 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
705}
706
707static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
708{
709 /* Calculate the display mode Average Bandwidth
710 * DisplayMode should contain the source and destination dimensions,
711 * timing, etc.
712 */
713 fixed20_12 bpp;
714 fixed20_12 line_time;
715 fixed20_12 src_width;
716 fixed20_12 bandwidth;
717 fixed20_12 a;
718
719 a.full = dfixed_const(1000);
720 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
721 line_time.full = dfixed_div(line_time, a);
722 bpp.full = dfixed_const(wm->bytes_per_pixel);
723 src_width.full = dfixed_const(wm->src_width);
724 bandwidth.full = dfixed_mul(src_width, bpp);
725 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
726 bandwidth.full = dfixed_div(bandwidth, line_time);
727
728 return dfixed_trunc(bandwidth);
729}
730
731static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
732{
733 /* First calcualte the latency in ns */
734 u32 mc_latency = 2000; /* 2000 ns. */
735 u32 available_bandwidth = evergreen_available_bandwidth(wm);
736 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
737 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
738 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
739 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
740 (wm->num_heads * cursor_line_pair_return_time);
741 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
742 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
743 fixed20_12 a, b, c;
744
745 if (wm->num_heads == 0)
746 return 0;
747
748 a.full = dfixed_const(2);
749 b.full = dfixed_const(1);
750 if ((wm->vsc.full > a.full) ||
751 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
752 (wm->vtaps >= 5) ||
753 ((wm->vsc.full >= a.full) && wm->interlaced))
754 max_src_lines_per_dst_line = 4;
755 else
756 max_src_lines_per_dst_line = 2;
757
758 a.full = dfixed_const(available_bandwidth);
759 b.full = dfixed_const(wm->num_heads);
760 a.full = dfixed_div(a, b);
761
762 b.full = dfixed_const(1000);
763 c.full = dfixed_const(wm->disp_clk);
764 b.full = dfixed_div(c, b);
765 c.full = dfixed_const(wm->bytes_per_pixel);
766 b.full = dfixed_mul(b, c);
767
768 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
769
770 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
771 b.full = dfixed_const(1000);
772 c.full = dfixed_const(lb_fill_bw);
773 b.full = dfixed_div(c, b);
774 a.full = dfixed_div(a, b);
775 line_fill_time = dfixed_trunc(a);
776
777 if (line_fill_time < wm->active_time)
778 return latency;
779 else
780 return latency + (line_fill_time - wm->active_time);
781
782}
783
784static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
785{
786 if (evergreen_average_bandwidth(wm) <=
787 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
788 return true;
789 else
790 return false;
791};
792
793static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
794{
795 if (evergreen_average_bandwidth(wm) <=
796 (evergreen_available_bandwidth(wm) / wm->num_heads))
797 return true;
798 else
799 return false;
800};
801
802static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
803{
804 u32 lb_partitions = wm->lb_size / wm->src_width;
805 u32 line_time = wm->active_time + wm->blank_time;
806 u32 latency_tolerant_lines;
807 u32 latency_hiding;
808 fixed20_12 a;
809
810 a.full = dfixed_const(1);
811 if (wm->vsc.full > a.full)
812 latency_tolerant_lines = 1;
813 else {
814 if (lb_partitions <= (wm->vtaps + 1))
815 latency_tolerant_lines = 1;
816 else
817 latency_tolerant_lines = 2;
818 }
819
820 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
821
822 if (evergreen_latency_watermark(wm) <= latency_hiding)
823 return true;
824 else
825 return false;
826}
827
828static void evergreen_program_watermarks(struct radeon_device *rdev,
829 struct radeon_crtc *radeon_crtc,
830 u32 lb_size, u32 num_heads)
831{
832 struct drm_display_mode *mode = &radeon_crtc->base.mode;
833 struct evergreen_wm_params wm;
834 u32 pixel_period;
835 u32 line_time = 0;
836 u32 latency_watermark_a = 0, latency_watermark_b = 0;
837 u32 priority_a_mark = 0, priority_b_mark = 0;
838 u32 priority_a_cnt = PRIORITY_OFF;
839 u32 priority_b_cnt = PRIORITY_OFF;
840 u32 pipe_offset = radeon_crtc->crtc_id * 16;
841 u32 tmp, arb_control3;
842 fixed20_12 a, b, c;
843
844 if (radeon_crtc->base.enabled && num_heads && mode) {
845 pixel_period = 1000000 / (u32)mode->clock;
846 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
847 priority_a_cnt = 0;
848 priority_b_cnt = 0;
849
850 wm.yclk = rdev->pm.current_mclk * 10;
851 wm.sclk = rdev->pm.current_sclk * 10;
852 wm.disp_clk = mode->clock;
853 wm.src_width = mode->crtc_hdisplay;
854 wm.active_time = mode->crtc_hdisplay * pixel_period;
855 wm.blank_time = line_time - wm.active_time;
856 wm.interlaced = false;
857 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
858 wm.interlaced = true;
859 wm.vsc = radeon_crtc->vsc;
860 wm.vtaps = 1;
861 if (radeon_crtc->rmx_type != RMX_OFF)
862 wm.vtaps = 2;
863 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
864 wm.lb_size = lb_size;
865 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
866 wm.num_heads = num_heads;
867
868 /* set for high clocks */
869 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
870 /* set for low clocks */
871 /* wm.yclk = low clk; wm.sclk = low clk */
872 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
873
874 /* possibly force display priority to high */
875 /* should really do this at mode validation time... */
876 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
877 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
878 !evergreen_check_latency_hiding(&wm) ||
879 (rdev->disp_priority == 2)) {
92bdfd4a 880 DRM_DEBUG_KMS("force priority to high\n");
f9d9c362
AD		 881 priority_a_cnt |= PRIORITY_ALWAYS_ON;
882 priority_b_cnt |= PRIORITY_ALWAYS_ON;
883 }
884
885 a.full = dfixed_const(1000);
886 b.full = dfixed_const(mode->clock);
887 b.full = dfixed_div(b, a);
888 c.full = dfixed_const(latency_watermark_a);
889 c.full = dfixed_mul(c, b);
890 c.full = dfixed_mul(c, radeon_crtc->hsc);
891 c.full = dfixed_div(c, a);
892 a.full = dfixed_const(16);
893 c.full = dfixed_div(c, a);
894 priority_a_mark = dfixed_trunc(c);
895 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
896
897 a.full = dfixed_const(1000);
898 b.full = dfixed_const(mode->clock);
899 b.full = dfixed_div(b, a);
900 c.full = dfixed_const(latency_watermark_b);
901 c.full = dfixed_mul(c, b);
902 c.full = dfixed_mul(c, radeon_crtc->hsc);
903 c.full = dfixed_div(c, a);
904 a.full = dfixed_const(16);
905 c.full = dfixed_div(c, a);
906 priority_b_mark = dfixed_trunc(c);
907 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
908 }
909
910 /* select wm A */
911 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
912 tmp = arb_control3;
913 tmp &= ~LATENCY_WATERMARK_MASK(3);
914 tmp |= LATENCY_WATERMARK_MASK(1);
915 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
916 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
917 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
918 LATENCY_HIGH_WATERMARK(line_time)));
919 /* select wm B */
920 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
921 tmp &= ~LATENCY_WATERMARK_MASK(3);
922 tmp |= LATENCY_WATERMARK_MASK(2);
923 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
924 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
925 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
926 LATENCY_HIGH_WATERMARK(line_time)));
927 /* restore original selection */
928 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
929
930 /* write the priority marks */
931 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
932 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
933
934}
935
0ca2ab52 936void evergreen_bandwidth_update(struct radeon_device *rdev)
bcc1c2a1 937{
f9d9c362
AD		 938 struct drm_display_mode *mode0 = NULL;
939 struct drm_display_mode *mode1 = NULL;
940 u32 num_heads = 0, lb_size;
941 int i;
942
943 radeon_update_display_priority(rdev);
944
945 for (i = 0; i < rdev->num_crtc; i++) {
946 if (rdev->mode_info.crtcs[i]->base.enabled)
947 num_heads++;
948 }
949 for (i = 0; i < rdev->num_crtc; i += 2) {
950 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
951 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
952 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
953 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
954 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
955 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
956 }
bcc1c2a1
AD		 957}
958
b9952a8a 959int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
bcc1c2a1
AD		 960{
961 unsigned i;
962 u32 tmp;
963
964 for (i = 0; i < rdev->usec_timeout; i++) {
965 /* read MC_STATUS */
966 tmp = RREG32(SRBM_STATUS) & 0x1F00;
967 if (!tmp)
968 return 0;
969 udelay(1);
970 }
971 return -1;
972}
973
974/*
975 * GART
976 */
0fcdb61e
AD		 977void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
978{
979 unsigned i;
980 u32 tmp;
981
6f2f48a9
AD		 982 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
983
0fcdb61e
AD		 984 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
985 for (i = 0; i < rdev->usec_timeout; i++) {
986 /* read MC_STATUS */
987 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
988 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
989 if (tmp == 2) {
990 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
991 return;
992 }
993 if (tmp) {
994 return;
995 }
996 udelay(1);
997 }
998}
999
bcc1c2a1
AD		 1000int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1001{
1002 u32 tmp;
0fcdb61e 1003 int r;
bcc1c2a1 1004
c9a1be96 1005 if (rdev->gart.robj == NULL) {
bcc1c2a1
AD		 1006 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1007 return -EINVAL;
1008 }
1009 r = radeon_gart_table_vram_pin(rdev);
1010 if (r)
1011 return r;
82568565 1012 radeon_gart_restore(rdev);
bcc1c2a1
AD		 1013 /* Setup L2 cache */
1014 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1015 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1016 EFFECTIVE_L2_QUEUE_SIZE(7));
1017 WREG32(VM_L2_CNTL2, 0);
1018 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1019 /* Setup TLB control */
1020 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1021 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1022 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1023 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
8aeb96f8
AD		 1024 if (rdev->flags & RADEON_IS_IGP) {
1025 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1026 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1027 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1028 } else {
1029 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1030 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1031 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1032 }
bcc1c2a1
AD		 1033 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1034 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1035 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1036 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1037 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1038 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1039 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1040 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1041 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1042 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1043 (u32)(rdev->dummy_page.addr >> 12));
0fcdb61e 1044 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1 1045
0fcdb61e 1046 evergreen_pcie_gart_tlb_flush(rdev);
fcf4de5a
TV		 1047 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1048 (unsigned)(rdev->mc.gtt_size >> 20),
1049 (unsigned long long)rdev->gart.table_addr);
bcc1c2a1
AD		 1050 rdev->gart.ready = true;
1051 return 0;
1052}
1053
1054void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1055{
1056 u32 tmp;
bcc1c2a1
AD		 1057
1058 /* Disable all tables */
0fcdb61e
AD		 1059 WREG32(VM_CONTEXT0_CNTL, 0);
1060 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1061
1062 /* Setup L2 cache */
1063 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1064 EFFECTIVE_L2_QUEUE_SIZE(7));
1065 WREG32(VM_L2_CNTL2, 0);
1066 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1067 /* Setup TLB control */
1068 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1069 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1070 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1071 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1072 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1073 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1074 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1075 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
c9a1be96 1076 radeon_gart_table_vram_unpin(rdev);
bcc1c2a1
AD		 1077}
1078
1079void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1080{
1081 evergreen_pcie_gart_disable(rdev);
1082 radeon_gart_table_vram_free(rdev);
1083 radeon_gart_fini(rdev);
1084}
1085
1086
1087void evergreen_agp_enable(struct radeon_device *rdev)
1088{
1089 u32 tmp;
bcc1c2a1
AD		 1090
1091 /* Setup L2 cache */
1092 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1093 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1094 EFFECTIVE_L2_QUEUE_SIZE(7));
1095 WREG32(VM_L2_CNTL2, 0);
1096 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1097 /* Setup TLB control */
1098 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1099 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1100 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1101 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1102 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1103 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1104 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1105 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1106 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1107 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1108 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
0fcdb61e
AD		 1109 WREG32(VM_CONTEXT0_CNTL, 0);
1110 WREG32(VM_CONTEXT1_CNTL, 0);
bcc1c2a1
AD		 1111}
1112
b9952a8a 1113void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1114{
1115 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1116 save->vga_control[1] = RREG32(D2VGA_CONTROL);
bcc1c2a1
AD		 1117 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1118 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1119 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1120 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 1121 if (rdev->num_crtc >= 4) {
1122 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1123 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
18007401
AD		 1124 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1125 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
b7eff394
AD		 1126 }
1127 if (rdev->num_crtc >= 6) {
1128 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1129 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
18007401
AD		 1130 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1131 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1132 }
bcc1c2a1
AD		 1133
1134 /* Stop all video */
1135 WREG32(VGA_RENDER_CONTROL, 0);
1136 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1137 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
b7eff394 1138 if (rdev->num_crtc >= 4) {
18007401
AD		 1139 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1140 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
b7eff394
AD		 1141 }
1142 if (rdev->num_crtc >= 6) {
18007401
AD		 1143 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1144 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1145 }
bcc1c2a1
AD		 1146 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1147 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1148 if (rdev->num_crtc >= 4) {
18007401
AD		 1149 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1150 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1151 }
1152 if (rdev->num_crtc >= 6) {
18007401
AD		 1153 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1154 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1155 }
bcc1c2a1
AD		 1156 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1157 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1158 if (rdev->num_crtc >= 4) {
18007401
AD		 1159 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1160 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1161 }
1162 if (rdev->num_crtc >= 6) {
18007401
AD		 1163 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1164 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1165 }
bcc1c2a1
AD		 1166
1167 WREG32(D1VGA_CONTROL, 0);
1168 WREG32(D2VGA_CONTROL, 0);
b7eff394
AD		 1169 if (rdev->num_crtc >= 4) {
1170 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1171 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1172 }
1173 if (rdev->num_crtc >= 6) {
1174 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1175 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1176 }
bcc1c2a1
AD		 1177}
1178
b9952a8a 1179void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
bcc1c2a1
AD		 1180{
1181 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1182 upper_32_bits(rdev->mc.vram_start));
1183 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1184 upper_32_bits(rdev->mc.vram_start));
1185 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1186 (u32)rdev->mc.vram_start);
1187 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1188 (u32)rdev->mc.vram_start);
1189
1190 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1191 upper_32_bits(rdev->mc.vram_start));
1192 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1193 upper_32_bits(rdev->mc.vram_start));
1194 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1195 (u32)rdev->mc.vram_start);
1196 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1197 (u32)rdev->mc.vram_start);
1198
b7eff394 1199 if (rdev->num_crtc >= 4) {
18007401
AD		 1200 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1201 upper_32_bits(rdev->mc.vram_start));
1202 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1203 upper_32_bits(rdev->mc.vram_start));
1204 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1205 (u32)rdev->mc.vram_start);
1206 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1207 (u32)rdev->mc.vram_start);
1208
1209 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1210 upper_32_bits(rdev->mc.vram_start));
1211 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1212 upper_32_bits(rdev->mc.vram_start));
1213 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1214 (u32)rdev->mc.vram_start);
1215 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1216 (u32)rdev->mc.vram_start);
b7eff394
AD		 1217 }
1218 if (rdev->num_crtc >= 6) {
18007401
AD		 1219 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1220 upper_32_bits(rdev->mc.vram_start));
1221 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1222 upper_32_bits(rdev->mc.vram_start));
1223 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1224 (u32)rdev->mc.vram_start);
1225 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1226 (u32)rdev->mc.vram_start);
1227
1228 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1229 upper_32_bits(rdev->mc.vram_start));
1230 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1231 upper_32_bits(rdev->mc.vram_start));
1232 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1233 (u32)rdev->mc.vram_start);
1234 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1235 (u32)rdev->mc.vram_start);
1236 }
bcc1c2a1
AD		 1237
1238 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1239 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1240 /* Unlock host access */
1241 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1242 mdelay(1);
1243 /* Restore video state */
1244 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1245 WREG32(D2VGA_CONTROL, save->vga_control[1]);
b7eff394
AD		 1246 if (rdev->num_crtc >= 4) {
1247 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1248 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1249 }
1250 if (rdev->num_crtc >= 6) {
1251 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1252 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1253 }
bcc1c2a1
AD		 1254 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1255 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
b7eff394 1256 if (rdev->num_crtc >= 4) {
18007401
AD		 1257 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1258 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
b7eff394
AD		 1259 }
1260 if (rdev->num_crtc >= 6) {
18007401
AD		 1261 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1262 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1263 }
bcc1c2a1
AD		 1264 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1265 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
b7eff394 1266 if (rdev->num_crtc >= 4) {
18007401
AD		 1267 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1268 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
b7eff394
AD		 1269 }
1270 if (rdev->num_crtc >= 6) {
18007401
AD		 1271 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1272 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1273 }
bcc1c2a1
AD		 1274 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1275 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 1276 if (rdev->num_crtc >= 4) {
18007401
AD		 1277 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1278 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 1279 }
1280 if (rdev->num_crtc >= 6) {
18007401
AD		 1281 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1282 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1283 }
bcc1c2a1
AD		 1284 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1285}
1286
755d819e 1287void evergreen_mc_program(struct radeon_device *rdev)
bcc1c2a1
AD		 1288{
1289 struct evergreen_mc_save save;
1290 u32 tmp;
1291 int i, j;
1292
1293 /* Initialize HDP */
1294 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1295 WREG32((0x2c14 + j), 0x00000000);
1296 WREG32((0x2c18 + j), 0x00000000);
1297 WREG32((0x2c1c + j), 0x00000000);
1298 WREG32((0x2c20 + j), 0x00000000);
1299 WREG32((0x2c24 + j), 0x00000000);
1300 }
1301 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1302
1303 evergreen_mc_stop(rdev, &save);
1304 if (evergreen_mc_wait_for_idle(rdev)) {
1305 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1306 }
1307 /* Lockout access through VGA aperture*/
1308 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1309 /* Update configuration */
1310 if (rdev->flags & RADEON_IS_AGP) {
1311 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1312 /* VRAM before AGP */
1313 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1314 rdev->mc.vram_start >> 12);
1315 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1316 rdev->mc.gtt_end >> 12);
1317 } else {
1318 /* VRAM after AGP */
1319 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1320 rdev->mc.gtt_start >> 12);
1321 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1322 rdev->mc.vram_end >> 12);
1323 }
1324 } else {
1325 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1326 rdev->mc.vram_start >> 12);
1327 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1328 rdev->mc.vram_end >> 12);
1329 }
3b9832f6 1330 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
b4183e30
AD		 1331 if (rdev->flags & RADEON_IS_IGP) {
1332 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1333 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1334 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1335 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1336 }
bcc1c2a1
AD		 1337 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1338 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1339 WREG32(MC_VM_FB_LOCATION, tmp);
1340 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
c46cb4da 1341 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
46fcd2b3 1342 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
bcc1c2a1
AD		 1343 if (rdev->flags & RADEON_IS_AGP) {
1344 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1345 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1346 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1347 } else {
1348 WREG32(MC_VM_AGP_BASE, 0);
1349 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1350 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1351 }
1352 if (evergreen_mc_wait_for_idle(rdev)) {
1353 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1354 }
1355 evergreen_mc_resume(rdev, &save);
1356 /* we need to own VRAM, so turn off the VGA renderer here
1357 * to stop it overwriting our objects */
1358 rv515_vga_render_disable(rdev);
1359}
1360
bcc1c2a1
AD		 1361/*
1362 * CP.
1363 */
12920591
AD		 1364void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1365{
e32eb50d 1366 struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
7b1f2485 1367
12920591 1368 /* set to DX10/11 mode */
e32eb50d
CK		 1369 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1370 radeon_ring_write(ring, 1);
12920591 1371 /* FIXME: implement */
e32eb50d
CK		 1372 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1373 radeon_ring_write(ring,
0f234f5f
AD		 1374#ifdef __BIG_ENDIAN
1375 (2 << 0) |
1376#endif
1377 (ib->gpu_addr & 0xFFFFFFFC));
e32eb50d
CK		 1378 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1379 radeon_ring_write(ring, ib->length_dw);
12920591
AD		 1380}
1381
bcc1c2a1
AD		 1382
1383static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1384{
fe251e2f
AD		 1385 const __be32 *fw_data;
1386 int i;
1387
1388 if (!rdev->me_fw || !rdev->pfp_fw)
1389 return -EINVAL;
bcc1c2a1 1390
fe251e2f 1391 r700_cp_stop(rdev);
0f234f5f
AD		 1392 WREG32(CP_RB_CNTL,
1393#ifdef __BIG_ENDIAN
1394 BUF_SWAP_32BIT |
1395#endif
1396 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
fe251e2f
AD		 1397
1398 fw_data = (const __be32 *)rdev->pfp_fw->data;
1399 WREG32(CP_PFP_UCODE_ADDR, 0);
1400 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1401 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1402 WREG32(CP_PFP_UCODE_ADDR, 0);
1403
1404 fw_data = (const __be32 *)rdev->me_fw->data;
1405 WREG32(CP_ME_RAM_WADDR, 0);
1406 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1407 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1408
1409 WREG32(CP_PFP_UCODE_ADDR, 0);
1410 WREG32(CP_ME_RAM_WADDR, 0);
1411 WREG32(CP_ME_RAM_RADDR, 0);
bcc1c2a1
AD		 1412 return 0;
1413}
1414
7e7b41d2
AD		 1415static int evergreen_cp_start(struct radeon_device *rdev)
1416{
e32eb50d 1417 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2281a378 1418 int r, i;
7e7b41d2
AD		 1419 uint32_t cp_me;
1420
e32eb50d 1421 r = radeon_ring_lock(rdev, ring, 7);
7e7b41d2
AD		 1422 if (r) {
1423 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1424 return r;
1425 }
e32eb50d
CK		 1426 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1427 radeon_ring_write(ring, 0x1);
1428 radeon_ring_write(ring, 0x0);
1429 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1430 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1431 radeon_ring_write(ring, 0);
1432 radeon_ring_write(ring, 0);
1433 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1434
1435 cp_me = 0xff;
1436 WREG32(CP_ME_CNTL, cp_me);
1437
e32eb50d 1438 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
7e7b41d2
AD		 1439 if (r) {
1440 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1441 return r;
1442 }
2281a378
AD		 1443
1444 /* setup clear context state */
e32eb50d
CK		 1445 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1446 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2281a378
AD		 1447
1448 for (i = 0; i < evergreen_default_size; i++)
e32eb50d 1449 radeon_ring_write(ring, evergreen_default_state[i]);
2281a378 1450
e32eb50d
CK		 1451 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1452 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2281a378
AD		 1453
1454 /* set clear context state */
e32eb50d
CK		 1455 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1456 radeon_ring_write(ring, 0);
2281a378
AD		 1457
1458 /* SQ_VTX_BASE_VTX_LOC */
e32eb50d
CK		 1459 radeon_ring_write(ring, 0xc0026f00);
1460 radeon_ring_write(ring, 0x00000000);
1461 radeon_ring_write(ring, 0x00000000);
1462 radeon_ring_write(ring, 0x00000000);
2281a378
AD		 1463
1464 /* Clear consts */
e32eb50d
CK		 1465 radeon_ring_write(ring, 0xc0036f00);
1466 radeon_ring_write(ring, 0x00000bc4);
1467 radeon_ring_write(ring, 0xffffffff);
1468 radeon_ring_write(ring, 0xffffffff);
1469 radeon_ring_write(ring, 0xffffffff);
2281a378 1470
e32eb50d
CK		 1471 radeon_ring_write(ring, 0xc0026900);
1472 radeon_ring_write(ring, 0x00000316);
1473 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1474 radeon_ring_write(ring, 0x00000010); /* */
18ff84da 1475
e32eb50d 1476 radeon_ring_unlock_commit(rdev, ring);
7e7b41d2
AD		 1477
1478 return 0;
1479}
1480
fe251e2f
AD		 1481int evergreen_cp_resume(struct radeon_device *rdev)
1482{
e32eb50d 1483 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
fe251e2f
AD		 1484 u32 tmp;
1485 u32 rb_bufsz;
1486 int r;
1487
1488 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1489 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1490 SOFT_RESET_PA |
1491 SOFT_RESET_SH |
1492 SOFT_RESET_VGT |
a49a50da 1493 SOFT_RESET_SPI |
fe251e2f
AD		 1494 SOFT_RESET_SX));
1495 RREG32(GRBM_SOFT_RESET);
1496 mdelay(15);
1497 WREG32(GRBM_SOFT_RESET, 0);
1498 RREG32(GRBM_SOFT_RESET);
1499
1500 /* Set ring buffer size */
e32eb50d 1501 rb_bufsz = drm_order(ring->ring_size / 8);
724c80e1 1502 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
fe251e2f
AD		 1503#ifdef __BIG_ENDIAN
1504 tmp |= BUF_SWAP_32BIT;
32fcdbf4 1505#endif
fe251e2f 1506 WREG32(CP_RB_CNTL, tmp);
15d3332f 1507 WREG32(CP_SEM_WAIT_TIMER, 0x0);
11ef3f1f 1508 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
fe251e2f
AD		 1509
1510 /* Set the write pointer delay */
1511 WREG32(CP_RB_WPTR_DELAY, 0);
1512
1513 /* Initialize the ring buffer's read and write pointers */
1514 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1515 WREG32(CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1516 ring->wptr = 0;
1517 WREG32(CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1518
1519 /* set the wb address wether it's enabled or not */
0f234f5f 1520 WREG32(CP_RB_RPTR_ADDR,
0f234f5f 1521 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
724c80e1
AD		 1522 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1523 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1524
1525 if (rdev->wb.enabled)
1526 WREG32(SCRATCH_UMSK, 0xff);
1527 else {
1528 tmp |= RB_NO_UPDATE;
1529 WREG32(SCRATCH_UMSK, 0);
1530 }
1531
fe251e2f
AD		 1532 mdelay(1);
1533 WREG32(CP_RB_CNTL, tmp);
1534
e32eb50d 1535 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
fe251e2f
AD		 1536 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1537
e32eb50d 1538 ring->rptr = RREG32(CP_RB_RPTR);
fe251e2f 1539
7e7b41d2 1540 evergreen_cp_start(rdev);
e32eb50d
CK		 1541 ring->ready = true;
1542 r = radeon_ring_test(rdev, ring);
fe251e2f 1543 if (r) {
e32eb50d 1544 ring->ready = false;
fe251e2f
AD		 1545 return r;
1546 }
1547 return 0;
1548}
bcc1c2a1
AD		 1549
1550/*
1551 * Core functions
1552 */
32fcdbf4
AD		 1553static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1554 u32 num_tile_pipes,
bcc1c2a1
AD		 1555 u32 num_backends,
1556 u32 backend_disable_mask)
1557{
1558 u32 backend_map = 0;
32fcdbf4
AD		 1559 u32 enabled_backends_mask = 0;
1560 u32 enabled_backends_count = 0;
1561 u32 cur_pipe;
1562 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1563 u32 cur_backend = 0;
1564 u32 i;
1565 bool force_no_swizzle;
1566
1567 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1568 num_tile_pipes = EVERGREEN_MAX_PIPES;
1569 if (num_tile_pipes < 1)
1570 num_tile_pipes = 1;
1571 if (num_backends > EVERGREEN_MAX_BACKENDS)
1572 num_backends = EVERGREEN_MAX_BACKENDS;
1573 if (num_backends < 1)
1574 num_backends = 1;
1575
1576 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1577 if (((backend_disable_mask >> i) & 1) == 0) {
1578 enabled_backends_mask |= (1 << i);
1579 ++enabled_backends_count;
1580 }
1581 if (enabled_backends_count == num_backends)
1582 break;
1583 }
1584
1585 if (enabled_backends_count == 0) {
1586 enabled_backends_mask = 1;
1587 enabled_backends_count = 1;
1588 }
1589
1590 if (enabled_backends_count != num_backends)
1591 num_backends = enabled_backends_count;
1592
1593 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1594 switch (rdev->family) {
1595 case CHIP_CEDAR:
1596 case CHIP_REDWOOD:
d5e455e4 1597 case CHIP_PALM:
d5c5a72f
AD		 1598 case CHIP_SUMO:
1599 case CHIP_SUMO2:
adb68fa2
AD		 1600 case CHIP_TURKS:
1601 case CHIP_CAICOS:
32fcdbf4
AD		 1602 force_no_swizzle = false;
1603 break;
1604 case CHIP_CYPRESS:
1605 case CHIP_HEMLOCK:
1606 case CHIP_JUNIPER:
adb68fa2 1607 case CHIP_BARTS:
32fcdbf4
AD		 1608 default:
1609 force_no_swizzle = true;
1610 break;
1611 }
1612 if (force_no_swizzle) {
1613 bool last_backend_enabled = false;
1614
1615 force_no_swizzle = false;
1616 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1617 if (((enabled_backends_mask >> i) & 1) == 1) {
1618 if (last_backend_enabled)
1619 force_no_swizzle = true;
1620 last_backend_enabled = true;
1621 } else
1622 last_backend_enabled = false;
1623 }
1624 }
1625
1626 switch (num_tile_pipes) {
1627 case 1:
1628 case 3:
1629 case 5:
1630 case 7:
1631 DRM_ERROR("odd number of pipes!\n");
1632 break;
1633 case 2:
1634 swizzle_pipe[0] = 0;
1635 swizzle_pipe[1] = 1;
1636 break;
1637 case 4:
1638 if (force_no_swizzle) {
1639 swizzle_pipe[0] = 0;
1640 swizzle_pipe[1] = 1;
1641 swizzle_pipe[2] = 2;
1642 swizzle_pipe[3] = 3;
1643 } else {
1644 swizzle_pipe[0] = 0;
1645 swizzle_pipe[1] = 2;
1646 swizzle_pipe[2] = 1;
1647 swizzle_pipe[3] = 3;
1648 }
1649 break;
1650 case 6:
1651 if (force_no_swizzle) {
1652 swizzle_pipe[0] = 0;
1653 swizzle_pipe[1] = 1;
1654 swizzle_pipe[2] = 2;
1655 swizzle_pipe[3] = 3;
1656 swizzle_pipe[4] = 4;
1657 swizzle_pipe[5] = 5;
1658 } else {
1659 swizzle_pipe[0] = 0;
1660 swizzle_pipe[1] = 2;
1661 swizzle_pipe[2] = 4;
1662 swizzle_pipe[3] = 1;
1663 swizzle_pipe[4] = 3;
1664 swizzle_pipe[5] = 5;
1665 }
1666 break;
1667 case 8:
1668 if (force_no_swizzle) {
1669 swizzle_pipe[0] = 0;
1670 swizzle_pipe[1] = 1;
1671 swizzle_pipe[2] = 2;
1672 swizzle_pipe[3] = 3;
1673 swizzle_pipe[4] = 4;
1674 swizzle_pipe[5] = 5;
1675 swizzle_pipe[6] = 6;
1676 swizzle_pipe[7] = 7;
1677 } else {
1678 swizzle_pipe[0] = 0;
1679 swizzle_pipe[1] = 2;
1680 swizzle_pipe[2] = 4;
1681 swizzle_pipe[3] = 6;
1682 swizzle_pipe[4] = 1;
1683 swizzle_pipe[5] = 3;
1684 swizzle_pipe[6] = 5;
1685 swizzle_pipe[7] = 7;
1686 }
1687 break;
1688 }
1689
1690 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1691 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1692 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1693
1694 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1695
1696 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1697 }
bcc1c2a1
AD		 1698
1699 return backend_map;
1700}
bcc1c2a1
AD		 1701
1702static void evergreen_gpu_init(struct radeon_device *rdev)
1703{
32fcdbf4
AD		 1704 u32 cc_rb_backend_disable = 0;
1705 u32 cc_gc_shader_pipe_config;
1706 u32 gb_addr_config = 0;
1707 u32 mc_shared_chmap, mc_arb_ramcfg;
1708 u32 gb_backend_map;
1709 u32 grbm_gfx_index;
1710 u32 sx_debug_1;
1711 u32 smx_dc_ctl0;
1712 u32 sq_config;
1713 u32 sq_lds_resource_mgmt;
1714 u32 sq_gpr_resource_mgmt_1;
1715 u32 sq_gpr_resource_mgmt_2;
1716 u32 sq_gpr_resource_mgmt_3;
1717 u32 sq_thread_resource_mgmt;
1718 u32 sq_thread_resource_mgmt_2;
1719 u32 sq_stack_resource_mgmt_1;
1720 u32 sq_stack_resource_mgmt_2;
1721 u32 sq_stack_resource_mgmt_3;
1722 u32 vgt_cache_invalidation;
f25a5c63 1723 u32 hdp_host_path_cntl, tmp;
32fcdbf4
AD		 1724 int i, j, num_shader_engines, ps_thread_count;
1725
1726 switch (rdev->family) {
1727 case CHIP_CYPRESS:
1728 case CHIP_HEMLOCK:
1729 rdev->config.evergreen.num_ses = 2;
1730 rdev->config.evergreen.max_pipes = 4;
1731 rdev->config.evergreen.max_tile_pipes = 8;
1732 rdev->config.evergreen.max_simds = 10;
1733 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1734 rdev->config.evergreen.max_gprs = 256;
1735 rdev->config.evergreen.max_threads = 248;
1736 rdev->config.evergreen.max_gs_threads = 32;
1737 rdev->config.evergreen.max_stack_entries = 512;
1738 rdev->config.evergreen.sx_num_of_sets = 4;
1739 rdev->config.evergreen.sx_max_export_size = 256;
1740 rdev->config.evergreen.sx_max_export_pos_size = 64;
1741 rdev->config.evergreen.sx_max_export_smx_size = 192;
1742 rdev->config.evergreen.max_hw_contexts = 8;
1743 rdev->config.evergreen.sq_num_cf_insts = 2;
1744
1745 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1746 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1747 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1748 break;
1749 case CHIP_JUNIPER:
1750 rdev->config.evergreen.num_ses = 1;
1751 rdev->config.evergreen.max_pipes = 4;
1752 rdev->config.evergreen.max_tile_pipes = 4;
1753 rdev->config.evergreen.max_simds = 10;
1754 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1755 rdev->config.evergreen.max_gprs = 256;
1756 rdev->config.evergreen.max_threads = 248;
1757 rdev->config.evergreen.max_gs_threads = 32;
1758 rdev->config.evergreen.max_stack_entries = 512;
1759 rdev->config.evergreen.sx_num_of_sets = 4;
1760 rdev->config.evergreen.sx_max_export_size = 256;
1761 rdev->config.evergreen.sx_max_export_pos_size = 64;
1762 rdev->config.evergreen.sx_max_export_smx_size = 192;
1763 rdev->config.evergreen.max_hw_contexts = 8;
1764 rdev->config.evergreen.sq_num_cf_insts = 2;
1765
1766 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1767 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1768 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1769 break;
1770 case CHIP_REDWOOD:
1771 rdev->config.evergreen.num_ses = 1;
1772 rdev->config.evergreen.max_pipes = 4;
1773 rdev->config.evergreen.max_tile_pipes = 4;
1774 rdev->config.evergreen.max_simds = 5;
1775 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1776 rdev->config.evergreen.max_gprs = 256;
1777 rdev->config.evergreen.max_threads = 248;
1778 rdev->config.evergreen.max_gs_threads = 32;
1779 rdev->config.evergreen.max_stack_entries = 256;
1780 rdev->config.evergreen.sx_num_of_sets = 4;
1781 rdev->config.evergreen.sx_max_export_size = 256;
1782 rdev->config.evergreen.sx_max_export_pos_size = 64;
1783 rdev->config.evergreen.sx_max_export_smx_size = 192;
1784 rdev->config.evergreen.max_hw_contexts = 8;
1785 rdev->config.evergreen.sq_num_cf_insts = 2;
1786
1787 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1788 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1789 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1790 break;
1791 case CHIP_CEDAR:
1792 default:
1793 rdev->config.evergreen.num_ses = 1;
1794 rdev->config.evergreen.max_pipes = 2;
1795 rdev->config.evergreen.max_tile_pipes = 2;
1796 rdev->config.evergreen.max_simds = 2;
1797 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1798 rdev->config.evergreen.max_gprs = 256;
1799 rdev->config.evergreen.max_threads = 192;
1800 rdev->config.evergreen.max_gs_threads = 16;
1801 rdev->config.evergreen.max_stack_entries = 256;
1802 rdev->config.evergreen.sx_num_of_sets = 4;
1803 rdev->config.evergreen.sx_max_export_size = 128;
1804 rdev->config.evergreen.sx_max_export_pos_size = 32;
1805 rdev->config.evergreen.sx_max_export_smx_size = 96;
1806 rdev->config.evergreen.max_hw_contexts = 4;
1807 rdev->config.evergreen.sq_num_cf_insts = 1;
1808
d5e455e4
AD		 1809 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1810 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1811 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1812 break;
1813 case CHIP_PALM:
1814 rdev->config.evergreen.num_ses = 1;
1815 rdev->config.evergreen.max_pipes = 2;
1816 rdev->config.evergreen.max_tile_pipes = 2;
1817 rdev->config.evergreen.max_simds = 2;
1818 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1819 rdev->config.evergreen.max_gprs = 256;
1820 rdev->config.evergreen.max_threads = 192;
1821 rdev->config.evergreen.max_gs_threads = 16;
1822 rdev->config.evergreen.max_stack_entries = 256;
1823 rdev->config.evergreen.sx_num_of_sets = 4;
1824 rdev->config.evergreen.sx_max_export_size = 128;
1825 rdev->config.evergreen.sx_max_export_pos_size = 32;
1826 rdev->config.evergreen.sx_max_export_smx_size = 96;
1827 rdev->config.evergreen.max_hw_contexts = 4;
1828 rdev->config.evergreen.sq_num_cf_insts = 1;
1829
d5c5a72f
AD		 1830 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1831 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1832 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1833 break;
1834 case CHIP_SUMO:
1835 rdev->config.evergreen.num_ses = 1;
1836 rdev->config.evergreen.max_pipes = 4;
1837 rdev->config.evergreen.max_tile_pipes = 2;
1838 if (rdev->pdev->device == 0x9648)
1839 rdev->config.evergreen.max_simds = 3;
1840 else if ((rdev->pdev->device == 0x9647) ||
1841 (rdev->pdev->device == 0x964a))
1842 rdev->config.evergreen.max_simds = 4;
1843 else
1844 rdev->config.evergreen.max_simds = 5;
1845 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1846 rdev->config.evergreen.max_gprs = 256;
1847 rdev->config.evergreen.max_threads = 248;
1848 rdev->config.evergreen.max_gs_threads = 32;
1849 rdev->config.evergreen.max_stack_entries = 256;
1850 rdev->config.evergreen.sx_num_of_sets = 4;
1851 rdev->config.evergreen.sx_max_export_size = 256;
1852 rdev->config.evergreen.sx_max_export_pos_size = 64;
1853 rdev->config.evergreen.sx_max_export_smx_size = 192;
1854 rdev->config.evergreen.max_hw_contexts = 8;
1855 rdev->config.evergreen.sq_num_cf_insts = 2;
1856
1857 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1858 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1859 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1860 break;
1861 case CHIP_SUMO2:
1862 rdev->config.evergreen.num_ses = 1;
1863 rdev->config.evergreen.max_pipes = 4;
1864 rdev->config.evergreen.max_tile_pipes = 4;
1865 rdev->config.evergreen.max_simds = 2;
1866 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1867 rdev->config.evergreen.max_gprs = 256;
1868 rdev->config.evergreen.max_threads = 248;
1869 rdev->config.evergreen.max_gs_threads = 32;
1870 rdev->config.evergreen.max_stack_entries = 512;
1871 rdev->config.evergreen.sx_num_of_sets = 4;
1872 rdev->config.evergreen.sx_max_export_size = 256;
1873 rdev->config.evergreen.sx_max_export_pos_size = 64;
1874 rdev->config.evergreen.sx_max_export_smx_size = 192;
1875 rdev->config.evergreen.max_hw_contexts = 8;
1876 rdev->config.evergreen.sq_num_cf_insts = 2;
1877
adb68fa2
AD		 1878 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1879 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1880 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1881 break;
1882 case CHIP_BARTS:
1883 rdev->config.evergreen.num_ses = 2;
1884 rdev->config.evergreen.max_pipes = 4;
1885 rdev->config.evergreen.max_tile_pipes = 8;
1886 rdev->config.evergreen.max_simds = 7;
1887 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1888 rdev->config.evergreen.max_gprs = 256;
1889 rdev->config.evergreen.max_threads = 248;
1890 rdev->config.evergreen.max_gs_threads = 32;
1891 rdev->config.evergreen.max_stack_entries = 512;
1892 rdev->config.evergreen.sx_num_of_sets = 4;
1893 rdev->config.evergreen.sx_max_export_size = 256;
1894 rdev->config.evergreen.sx_max_export_pos_size = 64;
1895 rdev->config.evergreen.sx_max_export_smx_size = 192;
1896 rdev->config.evergreen.max_hw_contexts = 8;
1897 rdev->config.evergreen.sq_num_cf_insts = 2;
1898
1899 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1900 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1901 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1902 break;
1903 case CHIP_TURKS:
1904 rdev->config.evergreen.num_ses = 1;
1905 rdev->config.evergreen.max_pipes = 4;
1906 rdev->config.evergreen.max_tile_pipes = 4;
1907 rdev->config.evergreen.max_simds = 6;
1908 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1909 rdev->config.evergreen.max_gprs = 256;
1910 rdev->config.evergreen.max_threads = 248;
1911 rdev->config.evergreen.max_gs_threads = 32;
1912 rdev->config.evergreen.max_stack_entries = 256;
1913 rdev->config.evergreen.sx_num_of_sets = 4;
1914 rdev->config.evergreen.sx_max_export_size = 256;
1915 rdev->config.evergreen.sx_max_export_pos_size = 64;
1916 rdev->config.evergreen.sx_max_export_smx_size = 192;
1917 rdev->config.evergreen.max_hw_contexts = 8;
1918 rdev->config.evergreen.sq_num_cf_insts = 2;
1919
1920 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1921 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1922 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1923 break;
1924 case CHIP_CAICOS:
1925 rdev->config.evergreen.num_ses = 1;
1926 rdev->config.evergreen.max_pipes = 4;
1927 rdev->config.evergreen.max_tile_pipes = 2;
1928 rdev->config.evergreen.max_simds = 2;
1929 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1930 rdev->config.evergreen.max_gprs = 256;
1931 rdev->config.evergreen.max_threads = 192;
1932 rdev->config.evergreen.max_gs_threads = 16;
1933 rdev->config.evergreen.max_stack_entries = 256;
1934 rdev->config.evergreen.sx_num_of_sets = 4;
1935 rdev->config.evergreen.sx_max_export_size = 128;
1936 rdev->config.evergreen.sx_max_export_pos_size = 32;
1937 rdev->config.evergreen.sx_max_export_smx_size = 96;
1938 rdev->config.evergreen.max_hw_contexts = 4;
1939 rdev->config.evergreen.sq_num_cf_insts = 1;
1940
32fcdbf4
AD		 1941 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1942 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1943 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1944 break;
1945 }
1946
1947 /* Initialize HDP */
1948 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1949 WREG32((0x2c14 + j), 0x00000000);
1950 WREG32((0x2c18 + j), 0x00000000);
1951 WREG32((0x2c1c + j), 0x00000000);
1952 WREG32((0x2c20 + j), 0x00000000);
1953 WREG32((0x2c24 + j), 0x00000000);
1954 }
1955
1956 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1957
d054ac16
AD		 1958 evergreen_fix_pci_max_read_req_size(rdev);
1959
32fcdbf4
AD		 1960 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1961
1962 cc_gc_shader_pipe_config |=
1963 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1964 & EVERGREEN_MAX_PIPES_MASK);
1965 cc_gc_shader_pipe_config |=
1966 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1967 & EVERGREEN_MAX_SIMDS_MASK);
1968
1969 cc_rb_backend_disable =
1970 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1971 & EVERGREEN_MAX_BACKENDS_MASK);
1972
1973
1974 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
d9282fca
AD		 1975 if (rdev->flags & RADEON_IS_IGP)
1976 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1977 else
1978 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
32fcdbf4
AD		 1979
1980 switch (rdev->config.evergreen.max_tile_pipes) {
1981 case 1:
1982 default:
1983 gb_addr_config |= NUM_PIPES(0);
1984 break;
1985 case 2:
1986 gb_addr_config |= NUM_PIPES(1);
1987 break;
1988 case 4:
1989 gb_addr_config |= NUM_PIPES(2);
1990 break;
1991 case 8:
1992 gb_addr_config |= NUM_PIPES(3);
1993 break;
1994 }
1995
1996 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1997 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1998 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1999 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
2000 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
2001 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
2002
2003 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
2004 gb_addr_config |= ROW_SIZE(2);
2005 else
2006 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
2007
2008 if (rdev->ddev->pdev->device == 0x689e) {
2009 u32 efuse_straps_4;
2010 u32 efuse_straps_3;
2011 u8 efuse_box_bit_131_124;
2012
2013 WREG32(RCU_IND_INDEX, 0x204);
2014 efuse_straps_4 = RREG32(RCU_IND_DATA);
2015 WREG32(RCU_IND_INDEX, 0x203);
2016 efuse_straps_3 = RREG32(RCU_IND_DATA);
2017 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
2018
2019 switch(efuse_box_bit_131_124) {
2020 case 0x00:
2021 gb_backend_map = 0x76543210;
2022 break;
2023 case 0x55:
2024 gb_backend_map = 0x77553311;
2025 break;
2026 case 0x56:
2027 gb_backend_map = 0x77553300;
2028 break;
2029 case 0x59:
2030 gb_backend_map = 0x77552211;
2031 break;
2032 case 0x66:
2033 gb_backend_map = 0x77443300;
2034 break;
2035 case 0x99:
2036 gb_backend_map = 0x66552211;
2037 break;
2038 case 0x5a:
2039 gb_backend_map = 0x77552200;
2040 break;
2041 case 0xaa:
2042 gb_backend_map = 0x66442200;
2043 break;
2044 case 0x95:
2045 gb_backend_map = 0x66553311;
2046 break;
2047 default:
2048 DRM_ERROR("bad backend map, using default\n");
2049 gb_backend_map =
2050 evergreen_get_tile_pipe_to_backend_map(rdev,
2051 rdev->config.evergreen.max_tile_pipes,
2052 rdev->config.evergreen.max_backends,
2053 ((EVERGREEN_MAX_BACKENDS_MASK <<
2054 rdev->config.evergreen.max_backends) &
2055 EVERGREEN_MAX_BACKENDS_MASK));
2056 break;
2057 }
2058 } else if (rdev->ddev->pdev->device == 0x68b9) {
2059 u32 efuse_straps_3;
2060 u8 efuse_box_bit_127_124;
2061
2062 WREG32(RCU_IND_INDEX, 0x203);
2063 efuse_straps_3 = RREG32(RCU_IND_DATA);
d31dba58 2064 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
32fcdbf4
AD		 2065
2066 switch(efuse_box_bit_127_124) {
2067 case 0x0:
2068 gb_backend_map = 0x00003210;
2069 break;
2070 case 0x5:
2071 case 0x6:
2072 case 0x9:
2073 case 0xa:
2074 gb_backend_map = 0x00003311;
2075 break;
2076 default:
2077 DRM_ERROR("bad backend map, using default\n");
2078 gb_backend_map =
2079 evergreen_get_tile_pipe_to_backend_map(rdev,
2080 rdev->config.evergreen.max_tile_pipes,
2081 rdev->config.evergreen.max_backends,
2082 ((EVERGREEN_MAX_BACKENDS_MASK <<
2083 rdev->config.evergreen.max_backends) &
2084 EVERGREEN_MAX_BACKENDS_MASK));
2085 break;
2086 }
b741be82
AD		 2087 } else {
2088 switch (rdev->family) {
2089 case CHIP_CYPRESS:
2090 case CHIP_HEMLOCK:
03f40090 2091 case CHIP_BARTS:
b741be82
AD		 2092 gb_backend_map = 0x66442200;
2093 break;
2094 case CHIP_JUNIPER:
9a4a0b9c 2095 gb_backend_map = 0x00002200;
b741be82
AD		 2096 break;
2097 default:
2098 gb_backend_map =
2099 evergreen_get_tile_pipe_to_backend_map(rdev,
2100 rdev->config.evergreen.max_tile_pipes,
2101 rdev->config.evergreen.max_backends,
2102 ((EVERGREEN_MAX_BACKENDS_MASK <<
2103 rdev->config.evergreen.max_backends) &
2104 EVERGREEN_MAX_BACKENDS_MASK));
2105 }
2106 }
32fcdbf4 2107
1aa52bd3
AD		 2108 /* setup tiling info dword. gb_addr_config is not adequate since it does
2109 * not have bank info, so create a custom tiling dword.
2110 * bits 3:0 num_pipes
2111 * bits 7:4 num_banks
2112 * bits 11:8 group_size
2113 * bits 15:12 row_size
2114 */
2115 rdev->config.evergreen.tile_config = 0;
2116 switch (rdev->config.evergreen.max_tile_pipes) {
2117 case 1:
2118 default:
2119 rdev->config.evergreen.tile_config |= (0 << 0);
2120 break;
2121 case 2:
2122 rdev->config.evergreen.tile_config |= (1 << 0);
2123 break;
2124 case 4:
2125 rdev->config.evergreen.tile_config |= (2 << 0);
2126 break;
2127 case 8:
2128 rdev->config.evergreen.tile_config |= (3 << 0);
2129 break;
2130 }
d698a34d 2131 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
5bfa4879 2132 if (rdev->flags & RADEON_IS_IGP)
d698a34d 2133 rdev->config.evergreen.tile_config |= 1 << 4;
5bfa4879
AD		 2134 else
2135 rdev->config.evergreen.tile_config |=
2136 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1aa52bd3
AD		 2137 rdev->config.evergreen.tile_config |=
2138 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2139 rdev->config.evergreen.tile_config |=
2140 ((gb_addr_config & 0x30000000) >> 28) << 12;
2141
e55b9422 2142 rdev->config.evergreen.backend_map = gb_backend_map;
32fcdbf4
AD		 2143 WREG32(GB_BACKEND_MAP, gb_backend_map);
2144 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2145 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2146 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2147
2148 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2149 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2150
2151 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2152 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2153 u32 sp = cc_gc_shader_pipe_config;
2154 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2155
2156 if (i == num_shader_engines) {
2157 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2158 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2159 }
2160
2161 WREG32(GRBM_GFX_INDEX, gfx);
2162 WREG32(RLC_GFX_INDEX, gfx);
2163
2164 WREG32(CC_RB_BACKEND_DISABLE, rb);
2165 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2166 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2167 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2168 }
2169
2170 grbm_gfx_index |= SE_BROADCAST_WRITES;
2171 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2172 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2173
2174 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2175 WREG32(CGTS_TCC_DISABLE, 0);
2176 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2177 WREG32(CGTS_USER_TCC_DISABLE, 0);
2178
2179 /* set HW defaults for 3D engine */
2180 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2181 ROQ_IB2_START(0x2b)));
2182
2183 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2184
2185 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2186 SYNC_GRADIENT |
2187 SYNC_WALKER |
2188 SYNC_ALIGNER));
2189
2190 sx_debug_1 = RREG32(SX_DEBUG_1);
2191 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2192 WREG32(SX_DEBUG_1, sx_debug_1);
2193
2194
2195 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2196 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2197 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2198 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2199
2200 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2201 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2202 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2203
2204 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2205 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2206 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2207
2208 WREG32(VGT_NUM_INSTANCES, 1);
2209 WREG32(SPI_CONFIG_CNTL, 0);
2210 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2211 WREG32(CP_PERFMON_CNTL, 0);
2212
2213 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2214 FETCH_FIFO_HIWATER(0x4) |
2215 DONE_FIFO_HIWATER(0xe0) |
2216 ALU_UPDATE_FIFO_HIWATER(0x8)));
2217
2218 sq_config = RREG32(SQ_CONFIG);
2219 sq_config &= ~(PS_PRIO(3) |
2220 VS_PRIO(3) |
2221 GS_PRIO(3) |
2222 ES_PRIO(3));
2223 sq_config |= (VC_ENABLE |
2224 EXPORT_SRC_C |
2225 PS_PRIO(0) |
2226 VS_PRIO(1) |
2227 GS_PRIO(2) |
2228 ES_PRIO(3));
2229
d5e455e4
AD		 2230 switch (rdev->family) {
2231 case CHIP_CEDAR:
2232 case CHIP_PALM:
d5c5a72f
AD		 2233 case CHIP_SUMO:
2234 case CHIP_SUMO2:
adb68fa2 2235 case CHIP_CAICOS:
32fcdbf4
AD		 2236 /* no vertex cache */
2237 sq_config &= ~VC_ENABLE;
d5e455e4
AD		 2238 break;
2239 default:
2240 break;
2241 }
32fcdbf4
AD		 2242
2243 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2244
2245 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2246 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2247 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2248 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2249 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2250 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2251 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2252
d5e455e4
AD		 2253 switch (rdev->family) {
2254 case CHIP_CEDAR:
2255 case CHIP_PALM:
d5c5a72f
AD		 2256 case CHIP_SUMO:
2257 case CHIP_SUMO2:
32fcdbf4 2258 ps_thread_count = 96;
d5e455e4
AD		 2259 break;
2260 default:
32fcdbf4 2261 ps_thread_count = 128;
d5e455e4
AD		 2262 break;
2263 }
32fcdbf4
AD		 2264
2265 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
f96b35cd
AD		 2266 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2267 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2268 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2269 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2270 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
32fcdbf4
AD		 2271
2272 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2273 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2274 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2275 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2276 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2277 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2278
2279 WREG32(SQ_CONFIG, sq_config);
2280 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2281 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2282 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2283 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2284 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2285 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2286 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2287 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2288 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2289 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2290
2291 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2292 FORCE_EOV_MAX_REZ_CNT(255)));
2293
d5e455e4
AD		 2294 switch (rdev->family) {
2295 case CHIP_CEDAR:
2296 case CHIP_PALM:
d5c5a72f
AD		 2297 case CHIP_SUMO:
2298 case CHIP_SUMO2:
adb68fa2 2299 case CHIP_CAICOS:
32fcdbf4 2300 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
d5e455e4
AD		 2301 break;
2302 default:
32fcdbf4 2303 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
d5e455e4
AD		 2304 break;
2305 }
32fcdbf4
AD		 2306 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2307 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2308
2309 WREG32(VGT_GS_VERTEX_REUSE, 16);
12920591 2310 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
32fcdbf4
AD		 2311 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2312
60a4a3e0
AD		 2313 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2314 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2315
32fcdbf4
AD		 2316 WREG32(CB_PERF_CTR0_SEL_0, 0);
2317 WREG32(CB_PERF_CTR0_SEL_1, 0);
2318 WREG32(CB_PERF_CTR1_SEL_0, 0);
2319 WREG32(CB_PERF_CTR1_SEL_1, 0);
2320 WREG32(CB_PERF_CTR2_SEL_0, 0);
2321 WREG32(CB_PERF_CTR2_SEL_1, 0);
2322 WREG32(CB_PERF_CTR3_SEL_0, 0);
2323 WREG32(CB_PERF_CTR3_SEL_1, 0);
2324
60a4a3e0
AD		 2325 /* clear render buffer base addresses */
2326 WREG32(CB_COLOR0_BASE, 0);
2327 WREG32(CB_COLOR1_BASE, 0);
2328 WREG32(CB_COLOR2_BASE, 0);
2329 WREG32(CB_COLOR3_BASE, 0);
2330 WREG32(CB_COLOR4_BASE, 0);
2331 WREG32(CB_COLOR5_BASE, 0);
2332 WREG32(CB_COLOR6_BASE, 0);
2333 WREG32(CB_COLOR7_BASE, 0);
2334 WREG32(CB_COLOR8_BASE, 0);
2335 WREG32(CB_COLOR9_BASE, 0);
2336 WREG32(CB_COLOR10_BASE, 0);
2337 WREG32(CB_COLOR11_BASE, 0);
2338
2339 /* set the shader const cache sizes to 0 */
2340 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2341 WREG32(i, 0);
2342 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2343 WREG32(i, 0);
2344
f25a5c63
AD		 2345 tmp = RREG32(HDP_MISC_CNTL);
2346 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2347 WREG32(HDP_MISC_CNTL, tmp);
2348
32fcdbf4
AD		 2349 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2350 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2351
2352 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2353
2354 udelay(50);
2355
bcc1c2a1
AD		 2356}
2357
2358int evergreen_mc_init(struct radeon_device *rdev)
2359{
bcc1c2a1
AD		 2360 u32 tmp;
2361 int chansize, numchan;
bcc1c2a1
AD		 2362
2363 /* Get VRAM informations */
2364 rdev->mc.vram_is_ddr = true;
8208441b
AD		 2365 if (rdev->flags & RADEON_IS_IGP)
2366 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2367 else
2368 tmp = RREG32(MC_ARB_RAMCFG);
bcc1c2a1
AD		 2369 if (tmp & CHANSIZE_OVERRIDE) {
2370 chansize = 16;
2371 } else if (tmp & CHANSIZE_MASK) {
2372 chansize = 64;
2373 } else {
2374 chansize = 32;
2375 }
2376 tmp = RREG32(MC_SHARED_CHMAP);
2377 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2378 case 0:
2379 default:
2380 numchan = 1;
2381 break;
2382 case 1:
2383 numchan = 2;
2384 break;
2385 case 2:
2386 numchan = 4;
2387 break;
2388 case 3:
2389 numchan = 8;
2390 break;
2391 }
2392 rdev->mc.vram_width = numchan * chansize;
2393 /* Could aper size report 0 ? */
01d73a69
JC		 2394 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2395 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
bcc1c2a1 2396 /* Setup GPU memory space */
6eb18f8b
AD		 2397 if (rdev->flags & RADEON_IS_IGP) {
2398 /* size in bytes on fusion */
2399 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2400 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2401 } else {
2402 /* size in MB on evergreen */
2403 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2404 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2405 }
51e5fcd3 2406 rdev->mc.visible_vram_size = rdev->mc.aper_size;
0ef0c1f7 2407 r700_vram_gtt_location(rdev, &rdev->mc);
f47299c5
AD		 2408 radeon_update_bandwidth_info(rdev);
2409
bcc1c2a1
AD		 2410 return 0;
2411}
d594e46a 2412
e32eb50d 2413bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
225758d8 2414{
17db7042
AD		 2415 u32 srbm_status;
2416 u32 grbm_status;
2417 u32 grbm_status_se0, grbm_status_se1;
2418 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2419 int r;
2420
2421 srbm_status = RREG32(SRBM_STATUS);
2422 grbm_status = RREG32(GRBM_STATUS);
2423 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2424 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2425 if (!(grbm_status & GUI_ACTIVE)) {
e32eb50d 2426 r100_gpu_lockup_update(lockup, ring);
17db7042
AD		 2427 return false;
2428 }
2429 /* force CP activities */
e32eb50d 2430 r = radeon_ring_lock(rdev, ring, 2);
17db7042
AD		 2431 if (!r) {
2432 /* PACKET2 NOP */
e32eb50d
CK		 2433 radeon_ring_write(ring, 0x80000000);
2434 radeon_ring_write(ring, 0x80000000);
2435 radeon_ring_unlock_commit(rdev, ring);
17db7042 2436 }
e32eb50d
CK		 2437 ring->rptr = RREG32(CP_RB_RPTR);
2438 return r100_gpu_cp_is_lockup(rdev, lockup, ring);
225758d8
JG		 2439}
2440
747943ea 2441static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
bcc1c2a1 2442{
747943ea 2443 struct evergreen_mc_save save;
747943ea
AD		 2444 u32 grbm_reset = 0;
2445
8d96fe93
AD		 2446 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2447 return 0;
2448
747943ea
AD		 2449 dev_info(rdev->dev, "GPU softreset \n");
2450 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2451 RREG32(GRBM_STATUS));
2452 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2453 RREG32(GRBM_STATUS_SE0));
2454 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2455 RREG32(GRBM_STATUS_SE1));
2456 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2457 RREG32(SRBM_STATUS));
2458 evergreen_mc_stop(rdev, &save);
2459 if (evergreen_mc_wait_for_idle(rdev)) {
2460 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2461 }
2462 /* Disable CP parsing/prefetching */
2463 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2464
2465 /* reset all the gfx blocks */
2466 grbm_reset = (SOFT_RESET_CP |
2467 SOFT_RESET_CB |
2468 SOFT_RESET_DB |
2469 SOFT_RESET_PA |
2470 SOFT_RESET_SC |
2471 SOFT_RESET_SPI |
2472 SOFT_RESET_SH |
2473 SOFT_RESET_SX |
2474 SOFT_RESET_TC |
2475 SOFT_RESET_TA |
2476 SOFT_RESET_VC |
2477 SOFT_RESET_VGT);
2478
2479 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2480 WREG32(GRBM_SOFT_RESET, grbm_reset);
2481 (void)RREG32(GRBM_SOFT_RESET);
2482 udelay(50);
2483 WREG32(GRBM_SOFT_RESET, 0);
2484 (void)RREG32(GRBM_SOFT_RESET);
747943ea
AD		 2485 /* Wait a little for things to settle down */
2486 udelay(50);
2487 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2488 RREG32(GRBM_STATUS));
2489 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2490 RREG32(GRBM_STATUS_SE0));
2491 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2492 RREG32(GRBM_STATUS_SE1));
2493 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2494 RREG32(SRBM_STATUS));
747943ea 2495 evergreen_mc_resume(rdev, &save);
bcc1c2a1
AD		 2496 return 0;
2497}
2498
a2d07b74 2499int evergreen_asic_reset(struct radeon_device *rdev)
bcc1c2a1 2500{
747943ea
AD		 2501 return evergreen_gpu_soft_reset(rdev);
2502}
2503
45f9a39b
AD		 2504/* Interrupts */
2505
2506u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2507{
2508 switch (crtc) {
2509 case 0:
2510 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2511 case 1:
2512 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2513 case 2:
2514 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2515 case 3:
2516 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2517 case 4:
2518 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2519 case 5:
2520 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2521 default:
2522 return 0;
2523 }
2524}
2525
2526void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2527{
2528 u32 tmp;
2529
1b37078b
AD		 2530 if (rdev->family >= CHIP_CAYMAN) {
2531 cayman_cp_int_cntl_setup(rdev, 0,
2532 CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2533 cayman_cp_int_cntl_setup(rdev, 1, 0);
2534 cayman_cp_int_cntl_setup(rdev, 2, 0);
2535 } else
2536 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
45f9a39b
AD		 2537 WREG32(GRBM_INT_CNTL, 0);
2538 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2539 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2540 if (rdev->num_crtc >= 4) {
18007401
AD		 2541 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2542 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2543 }
2544 if (rdev->num_crtc >= 6) {
18007401
AD		 2545 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2546 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2547 }
45f9a39b
AD		 2548
2549 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2550 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
b7eff394 2551 if (rdev->num_crtc >= 4) {
18007401
AD		 2552 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2553 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
b7eff394
AD		 2554 }
2555 if (rdev->num_crtc >= 6) {
18007401
AD		 2556 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2557 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2558 }
45f9a39b
AD		 2559
2560 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2561 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2562
2563 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2564 WREG32(DC_HPD1_INT_CONTROL, tmp);
2565 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2566 WREG32(DC_HPD2_INT_CONTROL, tmp);
2567 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2568 WREG32(DC_HPD3_INT_CONTROL, tmp);
2569 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2570 WREG32(DC_HPD4_INT_CONTROL, tmp);
2571 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2572 WREG32(DC_HPD5_INT_CONTROL, tmp);
2573 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2574 WREG32(DC_HPD6_INT_CONTROL, tmp);
2575
2576}
2577
2578int evergreen_irq_set(struct radeon_device *rdev)
2579{
2580 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1b37078b 2581 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
45f9a39b
AD		 2582 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2583 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2031f77c 2584 u32 grbm_int_cntl = 0;
6f34be50 2585 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
45f9a39b
AD		 2586
2587 if (!rdev->irq.installed) {
fce7d61b 2588 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
45f9a39b
AD		 2589 return -EINVAL;
2590 }
2591 /* don't enable anything if the ih is disabled */
2592 if (!rdev->ih.enabled) {
2593 r600_disable_interrupts(rdev);
2594 /* force the active interrupt state to all disabled */
2595 evergreen_disable_interrupt_state(rdev);
2596 return 0;
2597 }
2598
2599 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2600 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2601 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2602 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2603 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2604 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2605
1b37078b
AD		 2606 if (rdev->family >= CHIP_CAYMAN) {
2607 /* enable CP interrupts on all rings */
2608 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2609 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2610 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2611 }
2612 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
2613 DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2614 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2615 }
2616 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
2617 DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2618 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2619 }
2620 } else {
2621 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2622 DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2623 cp_int_cntl |= RB_INT_ENABLE;
2624 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2625 }
45f9a39b 2626 }
1b37078b 2627
6f34be50
AD		 2628 if (rdev->irq.crtc_vblank_int[0] ||
2629 rdev->irq.pflip[0]) {
45f9a39b
AD		 2630 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2631 crtc1 |= VBLANK_INT_MASK;
2632 }
6f34be50
AD		 2633 if (rdev->irq.crtc_vblank_int[1] ||
2634 rdev->irq.pflip[1]) {
45f9a39b
AD		 2635 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2636 crtc2 |= VBLANK_INT_MASK;
2637 }
6f34be50
AD		 2638 if (rdev->irq.crtc_vblank_int[2] ||
2639 rdev->irq.pflip[2]) {
45f9a39b
AD		 2640 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2641 crtc3 |= VBLANK_INT_MASK;
2642 }
6f34be50
AD		 2643 if (rdev->irq.crtc_vblank_int[3] ||
2644 rdev->irq.pflip[3]) {
45f9a39b
AD		 2645 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2646 crtc4 |= VBLANK_INT_MASK;
2647 }
6f34be50
AD		 2648 if (rdev->irq.crtc_vblank_int[4] ||
2649 rdev->irq.pflip[4]) {
45f9a39b
AD		 2650 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2651 crtc5 |= VBLANK_INT_MASK;
2652 }
6f34be50
AD		 2653 if (rdev->irq.crtc_vblank_int[5] ||
2654 rdev->irq.pflip[5]) {
45f9a39b
AD		 2655 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2656 crtc6 |= VBLANK_INT_MASK;
2657 }
2658 if (rdev->irq.hpd[0]) {
2659 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2660 hpd1 |= DC_HPDx_INT_EN;
2661 }
2662 if (rdev->irq.hpd[1]) {
2663 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2664 hpd2 |= DC_HPDx_INT_EN;
2665 }
2666 if (rdev->irq.hpd[2]) {
2667 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2668 hpd3 |= DC_HPDx_INT_EN;
2669 }
2670 if (rdev->irq.hpd[3]) {
2671 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2672 hpd4 |= DC_HPDx_INT_EN;
2673 }
2674 if (rdev->irq.hpd[4]) {
2675 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2676 hpd5 |= DC_HPDx_INT_EN;
2677 }
2678 if (rdev->irq.hpd[5]) {
2679 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2680 hpd6 |= DC_HPDx_INT_EN;
2681 }
2031f77c
AD		 2682 if (rdev->irq.gui_idle) {
2683 DRM_DEBUG("gui idle\n");
2684 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2685 }
45f9a39b 2686
1b37078b
AD		 2687 if (rdev->family >= CHIP_CAYMAN) {
2688 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2689 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2690 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2691 } else
2692 WREG32(CP_INT_CNTL, cp_int_cntl);
2031f77c 2693 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
45f9a39b
AD		 2694
2695 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2696 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
b7eff394 2697 if (rdev->num_crtc >= 4) {
18007401
AD		 2698 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2699 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
b7eff394
AD		 2700 }
2701 if (rdev->num_crtc >= 6) {
18007401
AD		 2702 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2703 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2704 }
45f9a39b 2705
6f34be50
AD		 2706 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2707 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
b7eff394
AD		 2708 if (rdev->num_crtc >= 4) {
2709 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2710 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2711 }
2712 if (rdev->num_crtc >= 6) {
2713 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2714 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2715 }
6f34be50 2716
45f9a39b
AD		 2717 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2718 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2719 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2720 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2721 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2722 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2723
bcc1c2a1
AD		 2724 return 0;
2725}
2726
cbdd4501 2727static void evergreen_irq_ack(struct radeon_device *rdev)
45f9a39b
AD		 2728{
2729 u32 tmp;
2730
6f34be50
AD		 2731 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2732 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2733 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2734 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2735 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2736 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2737 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2738 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
b7eff394
AD		 2739 if (rdev->num_crtc >= 4) {
2740 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2741 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2742 }
2743 if (rdev->num_crtc >= 6) {
2744 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2745 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2746 }
6f34be50
AD		 2747
2748 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2749 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2750 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2751 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
6f34be50 2752 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
45f9a39b 2753 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2754 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
45f9a39b 2755 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
6f34be50 2756 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
45f9a39b 2757 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
6f34be50 2758 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
45f9a39b
AD		 2759 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2760
b7eff394
AD		 2761 if (rdev->num_crtc >= 4) {
2762 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2763 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2764 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2765 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2766 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2767 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2768 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2769 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2770 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2771 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2772 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2773 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2774 }
2775
2776 if (rdev->num_crtc >= 6) {
2777 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2778 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2779 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2780 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2781 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2782 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2783 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2784 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2785 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2786 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2787 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2788 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2789 }
45f9a39b 2790
6f34be50 2791 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
45f9a39b
AD		 2792 tmp = RREG32(DC_HPD1_INT_CONTROL);
2793 tmp |= DC_HPDx_INT_ACK;
2794 WREG32(DC_HPD1_INT_CONTROL, tmp);
2795 }
6f34be50 2796 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
45f9a39b
AD		 2797 tmp = RREG32(DC_HPD2_INT_CONTROL);
2798 tmp |= DC_HPDx_INT_ACK;
2799 WREG32(DC_HPD2_INT_CONTROL, tmp);
2800 }
6f34be50 2801 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
45f9a39b
AD		 2802 tmp = RREG32(DC_HPD3_INT_CONTROL);
2803 tmp |= DC_HPDx_INT_ACK;
2804 WREG32(DC_HPD3_INT_CONTROL, tmp);
2805 }
6f34be50 2806 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
45f9a39b
AD		 2807 tmp = RREG32(DC_HPD4_INT_CONTROL);
2808 tmp |= DC_HPDx_INT_ACK;
2809 WREG32(DC_HPD4_INT_CONTROL, tmp);
2810 }
6f34be50 2811 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
45f9a39b
AD		 2812 tmp = RREG32(DC_HPD5_INT_CONTROL);
2813 tmp |= DC_HPDx_INT_ACK;
2814 WREG32(DC_HPD5_INT_CONTROL, tmp);
2815 }
6f34be50 2816 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
45f9a39b
AD		 2817 tmp = RREG32(DC_HPD5_INT_CONTROL);
2818 tmp |= DC_HPDx_INT_ACK;
2819 WREG32(DC_HPD6_INT_CONTROL, tmp);
2820 }
2821}
2822
2823void evergreen_irq_disable(struct radeon_device *rdev)
2824{
45f9a39b
AD		 2825 r600_disable_interrupts(rdev);
2826 /* Wait and acknowledge irq */
2827 mdelay(1);
6f34be50 2828 evergreen_irq_ack(rdev);
45f9a39b
AD		 2829 evergreen_disable_interrupt_state(rdev);
2830}
2831
755d819e 2832void evergreen_irq_suspend(struct radeon_device *rdev)
45f9a39b
AD		 2833{
2834 evergreen_irq_disable(rdev);
2835 r600_rlc_stop(rdev);
2836}
2837
cbdd4501 2838static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
45f9a39b
AD		 2839{
2840 u32 wptr, tmp;
2841
724c80e1 2842 if (rdev->wb.enabled)
204ae24d 2843 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
724c80e1
AD		 2844 else
2845 wptr = RREG32(IH_RB_WPTR);
45f9a39b
AD		 2846
2847 if (wptr & RB_OVERFLOW) {
2848 /* When a ring buffer overflow happen start parsing interrupt
2849 * from the last not overwritten vector (wptr + 16). Hopefully
2850 * this should allow us to catchup.
2851 */
2852 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2853 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2854 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2855 tmp = RREG32(IH_RB_CNTL);
2856 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2857 WREG32(IH_RB_CNTL, tmp);
2858 }
2859 return (wptr & rdev->ih.ptr_mask);
2860}
2861
2862int evergreen_irq_process(struct radeon_device *rdev)
2863{
682f1a54
DA		 2864 u32 wptr;
2865 u32 rptr;
45f9a39b
AD		 2866 u32 src_id, src_data;
2867 u32 ring_index;
45f9a39b
AD		 2868 unsigned long flags;
2869 bool queue_hotplug = false;
2870
682f1a54 2871 if (!rdev->ih.enabled || rdev->shutdown)
45f9a39b
AD		 2872 return IRQ_NONE;
2873
682f1a54
DA		 2874 wptr = evergreen_get_ih_wptr(rdev);
2875 rptr = rdev->ih.rptr;
2876 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
45f9a39b 2877
682f1a54 2878 spin_lock_irqsave(&rdev->ih.lock, flags);
45f9a39b
AD		 2879 if (rptr == wptr) {
2880 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2881 return IRQ_NONE;
2882 }
45f9a39b 2883restart_ih:
964f6645
BH		 2884 /* Order reading of wptr vs. reading of IH ring data */
2885 rmb();
2886
45f9a39b 2887 /* display interrupts */
6f34be50 2888 evergreen_irq_ack(rdev);
45f9a39b
AD		 2889
2890 rdev->ih.wptr = wptr;
2891 while (rptr != wptr) {
2892 /* wptr/rptr are in bytes! */
2893 ring_index = rptr / 4;
0f234f5f
AD		 2894 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2895 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
45f9a39b
AD		 2896
2897 switch (src_id) {
2898 case 1: /* D1 vblank/vline */
2899 switch (src_data) {
2900 case 0: /* D1 vblank */
6f34be50 2901 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
6f34be50
AD		 2902 if (rdev->irq.crtc_vblank_int[0]) {
2903 drm_handle_vblank(rdev->ddev, 0);
2904 rdev->pm.vblank_sync = true;
2905 wake_up(&rdev->irq.vblank_queue);
2906 }
3e4ea742
MK		 2907 if (rdev->irq.pflip[0])
2908 radeon_crtc_handle_flip(rdev, 0);
6f34be50 2909 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
45f9a39b
AD		 2910 DRM_DEBUG("IH: D1 vblank\n");
2911 }
2912 break;
2913 case 1: /* D1 vline */
6f34be50
AD		 2914 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2915 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
45f9a39b
AD		 2916 DRM_DEBUG("IH: D1 vline\n");
2917 }
2918 break;
2919 default:
2920 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2921 break;
2922 }
2923 break;
2924 case 2: /* D2 vblank/vline */
2925 switch (src_data) {
2926 case 0: /* D2 vblank */
6f34be50 2927 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
6f34be50
AD		 2928 if (rdev->irq.crtc_vblank_int[1]) {
2929 drm_handle_vblank(rdev->ddev, 1);
2930 rdev->pm.vblank_sync = true;
2931 wake_up(&rdev->irq.vblank_queue);
2932 }
3e4ea742
MK		 2933 if (rdev->irq.pflip[1])
2934 radeon_crtc_handle_flip(rdev, 1);
6f34be50 2935 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
45f9a39b
AD		 2936 DRM_DEBUG("IH: D2 vblank\n");
2937 }
2938 break;
2939 case 1: /* D2 vline */
6f34be50
AD		 2940 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2941 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
45f9a39b
AD		 2942 DRM_DEBUG("IH: D2 vline\n");
2943 }
2944 break;
2945 default:
2946 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2947 break;
2948 }
2949 break;
2950 case 3: /* D3 vblank/vline */
2951 switch (src_data) {
2952 case 0: /* D3 vblank */
6f34be50
AD		 2953 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2954 if (rdev->irq.crtc_vblank_int[2]) {
2955 drm_handle_vblank(rdev->ddev, 2);
2956 rdev->pm.vblank_sync = true;
2957 wake_up(&rdev->irq.vblank_queue);
2958 }
2959 if (rdev->irq.pflip[2])
2960 radeon_crtc_handle_flip(rdev, 2);
2961 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
45f9a39b
AD		 2962 DRM_DEBUG("IH: D3 vblank\n");
2963 }
2964 break;
2965 case 1: /* D3 vline */
6f34be50
AD		 2966 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2967 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
45f9a39b
AD		 2968 DRM_DEBUG("IH: D3 vline\n");
2969 }
2970 break;
2971 default:
2972 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2973 break;
2974 }
2975 break;
2976 case 4: /* D4 vblank/vline */
2977 switch (src_data) {
2978 case 0: /* D4 vblank */
6f34be50
AD		 2979 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2980 if (rdev->irq.crtc_vblank_int[3]) {
2981 drm_handle_vblank(rdev->ddev, 3);
2982 rdev->pm.vblank_sync = true;
2983 wake_up(&rdev->irq.vblank_queue);
2984 }
2985 if (rdev->irq.pflip[3])
2986 radeon_crtc_handle_flip(rdev, 3);
2987 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
45f9a39b
AD		 2988 DRM_DEBUG("IH: D4 vblank\n");
2989 }
2990 break;
2991 case 1: /* D4 vline */
6f34be50
AD		 2992 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2993 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
45f9a39b
AD		 2994 DRM_DEBUG("IH: D4 vline\n");
2995 }
2996 break;
2997 default:
2998 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2999 break;
3000 }
3001 break;
3002 case 5: /* D5 vblank/vline */
3003 switch (src_data) {
3004 case 0: /* D5 vblank */
6f34be50
AD		 3005 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3006 if (rdev->irq.crtc_vblank_int[4]) {
3007 drm_handle_vblank(rdev->ddev, 4);
3008 rdev->pm.vblank_sync = true;
3009 wake_up(&rdev->irq.vblank_queue);
3010 }
3011 if (rdev->irq.pflip[4])
3012 radeon_crtc_handle_flip(rdev, 4);
3013 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
45f9a39b
AD		 3014 DRM_DEBUG("IH: D5 vblank\n");
3015 }
3016 break;
3017 case 1: /* D5 vline */
6f34be50
AD		 3018 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3019 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
45f9a39b
AD		 3020 DRM_DEBUG("IH: D5 vline\n");
3021 }
3022 break;
3023 default:
3024 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3025 break;
3026 }
3027 break;
3028 case 6: /* D6 vblank/vline */
3029 switch (src_data) {
3030 case 0: /* D6 vblank */
6f34be50
AD		 3031 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3032 if (rdev->irq.crtc_vblank_int[5]) {
3033 drm_handle_vblank(rdev->ddev, 5);
3034 rdev->pm.vblank_sync = true;
3035 wake_up(&rdev->irq.vblank_queue);
3036 }
3037 if (rdev->irq.pflip[5])
3038 radeon_crtc_handle_flip(rdev, 5);
3039 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
45f9a39b
AD		 3040 DRM_DEBUG("IH: D6 vblank\n");
3041 }
3042 break;
3043 case 1: /* D6 vline */
6f34be50
AD		 3044 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3045 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
45f9a39b
AD		 3046 DRM_DEBUG("IH: D6 vline\n");
3047 }
3048 break;
3049 default:
3050 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3051 break;
3052 }
3053 break;
3054 case 42: /* HPD hotplug */
3055 switch (src_data) {
3056 case 0:
6f34be50
AD		 3057 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3058 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
45f9a39b
AD		 3059 queue_hotplug = true;
3060 DRM_DEBUG("IH: HPD1\n");
3061 }
3062 break;
3063 case 1:
6f34be50
AD		 3064 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3065 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
45f9a39b
AD		 3066 queue_hotplug = true;
3067 DRM_DEBUG("IH: HPD2\n");
3068 }
3069 break;
3070 case 2:
6f34be50
AD		 3071 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3072 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
45f9a39b
AD		 3073 queue_hotplug = true;
3074 DRM_DEBUG("IH: HPD3\n");
3075 }
3076 break;
3077 case 3:
6f34be50
AD		 3078 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3079 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
45f9a39b
AD		 3080 queue_hotplug = true;
3081 DRM_DEBUG("IH: HPD4\n");
3082 }
3083 break;
3084 case 4:
6f34be50
AD		 3085 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3086 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
45f9a39b
AD		 3087 queue_hotplug = true;
3088 DRM_DEBUG("IH: HPD5\n");
3089 }
3090 break;
3091 case 5:
6f34be50
AD		 3092 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3093 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
45f9a39b
AD		 3094 queue_hotplug = true;
3095 DRM_DEBUG("IH: HPD6\n");
3096 }
3097 break;
3098 default:
3099 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3100 break;
3101 }
3102 break;
3103 case 176: /* CP_INT in ring buffer */
3104 case 177: /* CP_INT in IB1 */
3105 case 178: /* CP_INT in IB2 */
3106 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
7465280c 3107 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b
AD		 3108 break;
3109 case 181: /* CP EOP event */
3110 DRM_DEBUG("IH: CP EOP\n");
1b37078b
AD		 3111 if (rdev->family >= CHIP_CAYMAN) {
3112 switch (src_data) {
3113 case 0:
3114 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3115 break;
3116 case 1:
3117 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3118 break;
3119 case 2:
3120 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3121 break;
3122 }
3123 } else
3124 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
45f9a39b 3125 break;
2031f77c 3126 case 233: /* GUI IDLE */
303c805c 3127 DRM_DEBUG("IH: GUI idle\n");
2031f77c
AD		 3128 rdev->pm.gui_idle = true;
3129 wake_up(&rdev->irq.idle_queue);
3130 break;
45f9a39b
AD		 3131 default:
3132 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3133 break;
3134 }
3135
3136 /* wptr/rptr are in bytes! */
3137 rptr += 16;
3138 rptr &= rdev->ih.ptr_mask;
3139 }
3140 /* make sure wptr hasn't changed while processing */
3141 wptr = evergreen_get_ih_wptr(rdev);
3142 if (wptr != rdev->ih.wptr)
3143 goto restart_ih;
3144 if (queue_hotplug)
32c87fca 3145 schedule_work(&rdev->hotplug_work);
45f9a39b
AD		 3146 rdev->ih.rptr = rptr;
3147 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3148 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3149 return IRQ_HANDLED;
3150}
3151
bcc1c2a1
AD		 3152static int evergreen_startup(struct radeon_device *rdev)
3153{
e32eb50d 3154 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
bcc1c2a1
AD		 3155 int r;
3156
9e46a48d 3157 /* enable pcie gen2 link */
cd54033a 3158 evergreen_pcie_gen2_enable(rdev);
9e46a48d 3159
0af62b01
AD		 3160 if (ASIC_IS_DCE5(rdev)) {
3161 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3162 r = ni_init_microcode(rdev);
3163 if (r) {
3164 DRM_ERROR("Failed to load firmware!\n");
3165 return r;
3166 }
3167 }
755d819e 3168 r = ni_mc_load_microcode(rdev);
bcc1c2a1 3169 if (r) {
0af62b01 3170 DRM_ERROR("Failed to load MC firmware!\n");
bcc1c2a1
AD		 3171 return r;
3172 }
0af62b01
AD		 3173 } else {
3174 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3175 r = r600_init_microcode(rdev);
3176 if (r) {
3177 DRM_ERROR("Failed to load firmware!\n");
3178 return r;
3179 }
3180 }
bcc1c2a1 3181 }
fe251e2f 3182
16cdf04d
AD		 3183 r = r600_vram_scratch_init(rdev);
3184 if (r)
3185 return r;
3186
bcc1c2a1 3187 evergreen_mc_program(rdev);
bcc1c2a1 3188 if (rdev->flags & RADEON_IS_AGP) {
0fcdb61e 3189 evergreen_agp_enable(rdev);
bcc1c2a1
AD		 3190 } else {
3191 r = evergreen_pcie_gart_enable(rdev);
3192 if (r)
3193 return r;
3194 }
bcc1c2a1 3195 evergreen_gpu_init(rdev);
bcc1c2a1 3196
d7ccd8fc 3197 r = evergreen_blit_init(rdev);
bcc1c2a1 3198 if (r) {
fb3d9e97 3199 r600_blit_fini(rdev);
27cd7769 3200 rdev->asic->copy.copy = NULL;
d7ccd8fc 3201 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
bcc1c2a1
AD		 3202 }
3203
724c80e1
AD		 3204 /* allocate wb buffer */
3205 r = radeon_wb_init(rdev);
3206 if (r)
3207 return r;
3208
30eb77f4
JG		 3209 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3210 if (r) {
3211 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3212 return r;
3213 }
3214
bcc1c2a1
AD		 3215 /* Enable IRQ */
3216 r = r600_irq_init(rdev);
3217 if (r) {
3218 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3219 radeon_irq_kms_fini(rdev);
3220 return r;
3221 }
45f9a39b 3222 evergreen_irq_set(rdev);
bcc1c2a1 3223
e32eb50d 3224 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 3225 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3226 0, 0xfffff, RADEON_CP_PACKET2);
bcc1c2a1
AD		 3227 if (r)
3228 return r;
3229 r = evergreen_cp_load_microcode(rdev);
3230 if (r)
3231 return r;
fe251e2f 3232 r = evergreen_cp_resume(rdev);
bcc1c2a1
AD		 3233 if (r)
3234 return r;
fe251e2f 3235
b15ba512
JG		 3236 r = radeon_ib_pool_start(rdev);
3237 if (r)
3238 return r;
3239
3240 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
3241 if (r) {
3242 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3243 rdev->accel_working = false;
3fe89a0c 3244 return r;
7a7e8734
DA		 3245 }
3246
69d2ae57
RM		 3247 r = r600_audio_init(rdev);
3248 if (r) {
3249 DRM_ERROR("radeon: audio init failed\n");
b15ba512
JG		 3250 return r;
3251 }
3252
bcc1c2a1
AD		 3253 return 0;
3254}
3255
3256int evergreen_resume(struct radeon_device *rdev)
3257{
3258 int r;
3259
86f5c9ed
AD		 3260 /* reset the asic, the gfx blocks are often in a bad state
3261 * after the driver is unloaded or after a resume
3262 */
3263 if (radeon_asic_reset(rdev))
3264 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1
AD		 3265 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3266 * posting will perform necessary task to bring back GPU into good
3267 * shape.
3268 */
3269 /* post card */
3270 atom_asic_init(rdev->mode_info.atom_context);
bcc1c2a1 3271
b15ba512 3272 rdev->accel_working = true;
bcc1c2a1
AD		 3273 r = evergreen_startup(rdev);
3274 if (r) {
755d819e 3275 DRM_ERROR("evergreen startup failed on resume\n");
bcc1c2a1
AD		 3276 return r;
3277 }
fe251e2f 3278
bcc1c2a1
AD		 3279 return r;
3280
3281}
3282
3283int evergreen_suspend(struct radeon_device *rdev)
3284{
e32eb50d 3285 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3286
69d2ae57 3287 r600_audio_fini(rdev);
bcc1c2a1 3288 /* FIXME: we should wait for ring to be empty */
b15ba512
JG		 3289 radeon_ib_pool_suspend(rdev);
3290 r600_blit_suspend(rdev);
bcc1c2a1 3291 r700_cp_stop(rdev);
e32eb50d 3292 ring->ready = false;
45f9a39b 3293 evergreen_irq_suspend(rdev);
724c80e1 3294 radeon_wb_disable(rdev);
bcc1c2a1 3295 evergreen_pcie_gart_disable(rdev);
d7ccd8fc
AD		 3296
3297 return 0;
3298}
3299
bcc1c2a1
AD		 3300/* Plan is to move initialization in that function and use
3301 * helper function so that radeon_device_init pretty much
3302 * do nothing more than calling asic specific function. This
3303 * should also allow to remove a bunch of callback function
3304 * like vram_info.
3305 */
3306int evergreen_init(struct radeon_device *rdev)
3307{
3308 int r;
3309
bcc1c2a1
AD		 3310 /* This don't do much */
3311 r = radeon_gem_init(rdev);
3312 if (r)
3313 return r;
3314 /* Read BIOS */
3315 if (!radeon_get_bios(rdev)) {
3316 if (ASIC_IS_AVIVO(rdev))
3317 return -EINVAL;
3318 }
3319 /* Must be an ATOMBIOS */
3320 if (!rdev->is_atom_bios) {
755d819e 3321 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
bcc1c2a1
AD		 3322 return -EINVAL;
3323 }
3324 r = radeon_atombios_init(rdev);
3325 if (r)
3326 return r;
86f5c9ed
AD		 3327 /* reset the asic, the gfx blocks are often in a bad state
3328 * after the driver is unloaded or after a resume
3329 */
3330 if (radeon_asic_reset(rdev))
3331 dev_warn(rdev->dev, "GPU reset failed !\n");
bcc1c2a1 3332 /* Post card if necessary */
fd909c37 3333 if (!radeon_card_posted(rdev)) {
bcc1c2a1
AD		 3334 if (!rdev->bios) {
3335 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3336 return -EINVAL;
3337 }
3338 DRM_INFO("GPU not posted. posting now...\n");
3339 atom_asic_init(rdev->mode_info.atom_context);
3340 }
3341 /* Initialize scratch registers */
3342 r600_scratch_init(rdev);
3343 /* Initialize surface registers */
3344 radeon_surface_init(rdev);
3345 /* Initialize clocks */
3346 radeon_get_clock_info(rdev->ddev);
bcc1c2a1
AD		 3347 /* Fence driver */
3348 r = radeon_fence_driver_init(rdev);
3349 if (r)
3350 return r;
d594e46a
JG		 3351 /* initialize AGP */
3352 if (rdev->flags & RADEON_IS_AGP) {
3353 r = radeon_agp_init(rdev);
3354 if (r)
3355 radeon_agp_disable(rdev);
3356 }
3357 /* initialize memory controller */
bcc1c2a1
AD		 3358 r = evergreen_mc_init(rdev);
3359 if (r)
3360 return r;
3361 /* Memory manager */
3362 r = radeon_bo_init(rdev);
3363 if (r)
3364 return r;
45f9a39b 3365
bcc1c2a1
AD		 3366 r = radeon_irq_kms_init(rdev);
3367 if (r)
3368 return r;
3369
e32eb50d
CK		 3370 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3371 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
bcc1c2a1
AD		 3372
3373 rdev->ih.ring_obj = NULL;
3374 r600_ih_ring_init(rdev, 64 * 1024);
3375
3376 r = r600_pcie_gart_init(rdev);
3377 if (r)
3378 return r;
0fcdb61e 3379
b15ba512 3380 r = radeon_ib_pool_init(rdev);
148a03bc 3381 rdev->accel_working = true;
b15ba512
JG		 3382 if (r) {
3383 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3384 rdev->accel_working = false;
3385 }
3386
bcc1c2a1
AD		 3387 r = evergreen_startup(rdev);
3388 if (r) {
fe251e2f
AD		 3389 dev_err(rdev->dev, "disabling GPU acceleration\n");
3390 r700_cp_fini(rdev);
fe251e2f 3391 r600_irq_fini(rdev);
724c80e1 3392 radeon_wb_fini(rdev);
b15ba512 3393 r100_ib_fini(rdev);
fe251e2f 3394 radeon_irq_kms_fini(rdev);
0fcdb61e 3395 evergreen_pcie_gart_fini(rdev);
bcc1c2a1
AD		 3396 rdev->accel_working = false;
3397 }
77e00f2e
AD		 3398
3399 /* Don't start up if the MC ucode is missing on BTC parts.
3400 * The default clocks and voltages before the MC ucode
3401 * is loaded are not suffient for advanced operations.
3402 */
3403 if (ASIC_IS_DCE5(rdev)) {
3404 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3405 DRM_ERROR("radeon: MC ucode required for NI+.\n");
3406 return -EINVAL;
3407 }
3408 }
3409
bcc1c2a1
AD		 3410 return 0;
3411}
3412
3413void evergreen_fini(struct radeon_device *rdev)
3414{
69d2ae57 3415 r600_audio_fini(rdev);
fb3d9e97 3416 r600_blit_fini(rdev);
45f9a39b 3417 r700_cp_fini(rdev);
bcc1c2a1 3418 r600_irq_fini(rdev);
724c80e1 3419 radeon_wb_fini(rdev);
b15ba512 3420 r100_ib_fini(rdev);
bcc1c2a1 3421 radeon_irq_kms_fini(rdev);
bcc1c2a1 3422 evergreen_pcie_gart_fini(rdev);
16cdf04d 3423 r600_vram_scratch_fini(rdev);
bcc1c2a1 3424 radeon_gem_fini(rdev);
15d3332f 3425 radeon_semaphore_driver_fini(rdev);
bcc1c2a1 3426 radeon_fence_driver_fini(rdev);
bcc1c2a1
AD		 3427 radeon_agp_fini(rdev);
3428 radeon_bo_fini(rdev);
3429 radeon_atombios_fini(rdev);
3430 kfree(rdev->bios);
3431 rdev->bios = NULL;
bcc1c2a1 3432}
9e46a48d 3433
b07759bf 3434void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
9e46a48d
AD		 3435{
3436 u32 link_width_cntl, speed_cntl;
3437
d42dd579
AD		 3438 if (radeon_pcie_gen2 == 0)
3439 return;
3440
9e46a48d
AD		 3441 if (rdev->flags & RADEON_IS_IGP)
3442 return;
3443
3444 if (!(rdev->flags & RADEON_IS_PCIE))
3445 return;
3446
3447 /* x2 cards have a special sequence */
3448 if (ASIC_IS_X2(rdev))
3449 return;
3450
3451 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3452 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3453 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3454
3455 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3456 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3457 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3458
3459 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3460 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3461 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3462
3463 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3464 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3465 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3466
3467 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3468 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3469 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3470
3471 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3472 speed_cntl |= LC_GEN2_EN_STRAP;
3473 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3474
3475 } else {
3476 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3477 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3478 if (1)
3479 link_width_cntl |= LC_UPCONFIGURE_DIS;
3480 else
3481 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3482 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3483 }
3484}
Linux kernel - Deliverables
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