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Merge remote-tracking branch 'selinux/next'
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon.h
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
771fe6b9
JG		 31/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
d39c3b89
JG		 45/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
60063497 63#include <linux/atomic.h>
771fe6b9
JG		 64#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
0aea5e4a 67#include <linux/interval_tree.h>
341cb9e4 68#include <linux/hashtable.h>
954605ca 69#include <linux/fence.h>
771fe6b9 70
4c788679
JG		 71#include <ttm/ttm_bo_api.h>
72#include <ttm/ttm_bo_driver.h>
73#include <ttm/ttm_placement.h>
74#include <ttm/ttm_module.h>
147666fb 75#include <ttm/ttm_execbuf_util.h>
4c788679 76
d9fc9413
DV		 77#include <drm/drm_gem.h>
78
c2142715 79#include "radeon_family.h"
771fe6b9
JG		 80#include "radeon_mode.h"
81#include "radeon_reg.h"
771fe6b9
JG		 82
83/*
84 * Modules parameters.
85 */
86extern int radeon_no_wb;
87extern int radeon_modeset;
88extern int radeon_dynclks;
89extern int radeon_r4xx_atom;
90extern int radeon_agpmode;
91extern int radeon_vram_limit;
92extern int radeon_gart_size;
93extern int radeon_benchmarking;
ecc0b326 94extern int radeon_testing;
771fe6b9 95extern int radeon_connector_table;
4ce001ab 96extern int radeon_tv;
dafc3bd5 97extern int radeon_audio;
f46c0120 98extern int radeon_disp_priority;
e2b0a8e1 99extern int radeon_hw_i2c;
d42dd579 100extern int radeon_pcie_gen2;
a18cee15 101extern int radeon_msi;
3368ff0c 102extern int radeon_lockup_timeout;
a0a53aa8 103extern int radeon_fastfb;
da321c8a 104extern int radeon_dpm;
1294d4a3 105extern int radeon_aspm;
10ebc0bc 106extern int radeon_runtime_pm;
363eb0b4 107extern int radeon_hard_reset;
c1c44132 108extern int radeon_vm_size;
4510fb98 109extern int radeon_vm_block_size;
a624f429 110extern int radeon_deep_color;
39dc5454 111extern int radeon_use_pflipirq;
6e909f74 112extern int radeon_bapm;
bc13018b 113extern int radeon_backlight;
875711f0 114extern int radeon_auxch;
9843ead0 115extern int radeon_mst;
f1a0a67a 116extern int radeon_uvd;
fabb5935 117extern int radeon_vce;
771fe6b9
JG		 118
119/*
120 * Copy from radeon_drv.h so we don't have to include both and have conflicting
121 * symbol;
122 */
bb635567
JG		 123#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
124#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
04db4caf 125#define RADEON_USEC_IB_TEST_TIMEOUT 1000000 /* 1s */
e821767b 126/* RADEON_IB_POOL_SIZE must be a power of 2 */
bb635567
JG		 127#define RADEON_IB_POOL_SIZE 16
128#define RADEON_DEBUGFS_MAX_COMPONENTS 32
129#define RADEONFB_CONN_LIMIT 4
130#define RADEON_BIOS_NUM_SCRATCH 8
771fe6b9 131
1b37078b
AD		 132/* internal ring indices */
133/* r1xx+ has gfx CP ring */
d93f7937 134#define RADEON_RING_TYPE_GFX_INDEX 0
1b37078b
AD		 135
136/* cayman has 2 compute CP rings */
d93f7937
CK		 137#define CAYMAN_RING_TYPE_CP1_INDEX 1
138#define CAYMAN_RING_TYPE_CP2_INDEX 2
1b37078b 139
4d75658b
AD		 140/* R600+ has an async dma ring */
141#define R600_RING_TYPE_DMA_INDEX 3
f60cbd11
AD		 142/* cayman add a second async dma ring */
143#define CAYMAN_RING_TYPE_DMA1_INDEX 4
4d75658b 144
f2ba57b5 145/* R600+ */
d93f7937
CK		 146#define R600_RING_TYPE_UVD_INDEX 5
147
148/* TN+ */
149#define TN_RING_TYPE_VCE1_INDEX 6
150#define TN_RING_TYPE_VCE2_INDEX 7
151
152/* max number of rings */
153#define RADEON_NUM_RINGS 8
f2ba57b5 154
1c61eae4
CK		 155/* number of hw syncs before falling back on blocking */
156#define RADEON_NUM_SYNCS 4
f2ba57b5 157
721604a1 158/* hardcode those limit for now */
ca19f21e 159#define RADEON_VA_IB_OFFSET (1 << 20)
bb635567
JG		 160#define RADEON_VA_RESERVED_SIZE (8 << 20)
161#define RADEON_IB_VM_MAX_SIZE (64 << 10)
721604a1 162
1a0041b8
AD		 163/* hard reset data */
164#define RADEON_ASIC_RESET_DATA 0x39d5e86b
165
ec46c76d
AD		 166/* reset flags */
167#define RADEON_RESET_GFX (1 << 0)
168#define RADEON_RESET_COMPUTE (1 << 1)
169#define RADEON_RESET_DMA (1 << 2)
9ff0744c
AD		 170#define RADEON_RESET_CP (1 << 3)
171#define RADEON_RESET_GRBM (1 << 4)
172#define RADEON_RESET_DMA1 (1 << 5)
173#define RADEON_RESET_RLC (1 << 6)
174#define RADEON_RESET_SEM (1 << 7)
175#define RADEON_RESET_IH (1 << 8)
176#define RADEON_RESET_VMC (1 << 9)
177#define RADEON_RESET_MC (1 << 10)
178#define RADEON_RESET_DISPLAY (1 << 11)
ec46c76d 179
22c775ce
AD		 180/* CG block flags */
181#define RADEON_CG_BLOCK_GFX (1 << 0)
182#define RADEON_CG_BLOCK_MC (1 << 1)
183#define RADEON_CG_BLOCK_SDMA (1 << 2)
184#define RADEON_CG_BLOCK_UVD (1 << 3)
185#define RADEON_CG_BLOCK_VCE (1 << 4)
186#define RADEON_CG_BLOCK_HDP (1 << 5)
e16866ec 187#define RADEON_CG_BLOCK_BIF (1 << 6)
22c775ce 188
64d8a728
AD		 189/* CG flags */
190#define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
191#define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
192#define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
193#define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
194#define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
195#define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
196#define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
197#define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
198#define RADEON_CG_SUPPORT_MC_LS (1 << 8)
199#define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
200#define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
201#define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
202#define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
203#define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
204#define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
205#define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
206#define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
207
208/* PG flags */
2b19d17f 209#define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
64d8a728
AD		 210#define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
211#define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
212#define RADEON_PG_SUPPORT_UVD (1 << 3)
213#define RADEON_PG_SUPPORT_VCE (1 << 4)
214#define RADEON_PG_SUPPORT_CP (1 << 5)
215#define RADEON_PG_SUPPORT_GDS (1 << 6)
216#define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
217#define RADEON_PG_SUPPORT_SDMA (1 << 8)
218#define RADEON_PG_SUPPORT_ACP (1 << 9)
219#define RADEON_PG_SUPPORT_SAMU (1 << 10)
220
9e05fa1d
AD		 221/* max cursor sizes (in pixels) */
222#define CURSOR_WIDTH 64
223#define CURSOR_HEIGHT 64
224
225#define CIK_CURSOR_WIDTH 128
226#define CIK_CURSOR_HEIGHT 128
227
771fe6b9
JG		 228/*
229 * Errata workarounds.
230 */
231enum radeon_pll_errata {
232 CHIP_ERRATA_R300_CG = 0x00000001,
233 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
234 CHIP_ERRATA_PLL_DELAY = 0x00000004
235};
236
237
238struct radeon_device;
239
240
241/*
242 * BIOS.
243 */
244bool radeon_get_bios(struct radeon_device *rdev);
245
246/*
3ce0a23d 247 * Dummy page
771fe6b9 248 */
3ce0a23d 249struct radeon_dummy_page {
cb658906 250 uint64_t entry;
3ce0a23d
JG		 251 struct page *page;
252 dma_addr_t addr;
253};
254int radeon_dummy_page_init(struct radeon_device *rdev);
255void radeon_dummy_page_fini(struct radeon_device *rdev);
256
771fe6b9 257
3ce0a23d
JG		 258/*
259 * Clocks
260 */
771fe6b9
JG		 261struct radeon_clock {
262 struct radeon_pll p1pll;
263 struct radeon_pll p2pll;
bcc1c2a1 264 struct radeon_pll dcpll;
771fe6b9
JG		 265 struct radeon_pll spll;
266 struct radeon_pll mpll;
267 /* 10 Khz units */
268 uint32_t default_mclk;
269 uint32_t default_sclk;
bcc1c2a1 270 uint32_t default_dispclk;
4489cd62 271 uint32_t current_dispclk;
bcc1c2a1 272 uint32_t dp_extclk;
b20f9bef 273 uint32_t max_pixel_clock;
c9a392ea 274 uint32_t vco_freq;
771fe6b9
JG		 275};
276
7433874e
RM		 277/*
278 * Power management
279 */
280int radeon_pm_init(struct radeon_device *rdev);
914a8987 281int radeon_pm_late_init(struct radeon_device *rdev);
29fb52ca 282void radeon_pm_fini(struct radeon_device *rdev);
c913e23a 283void radeon_pm_compute_clocks(struct radeon_device *rdev);
ce8f5370
AD		 284void radeon_pm_suspend(struct radeon_device *rdev);
285void radeon_pm_resume(struct radeon_device *rdev);
56278a8e
AD		 286void radeon_combios_get_power_modes(struct radeon_device *rdev);
287void radeon_atombios_get_power_modes(struct radeon_device *rdev);
7062ab67
CK		 288int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
289 u8 clock_type,
290 u32 clock,
291 bool strobe_mode,
292 struct atom_clock_dividers *dividers);
eaa778af
AD		 293int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
294 u32 clock,
295 bool strobe_mode,
296 struct atom_mpll_param *mpll_param);
8a83ec5e 297void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
ae5b0abb
AD		 298int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
299 u16 voltage_level, u8 voltage_type,
300 u32 *gpio_value, u32 *gpio_mask);
301void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
302 u32 eng_clock, u32 mem_clock);
303int radeon_atom_get_voltage_step(struct radeon_device *rdev,
304 u8 voltage_type, u16 *voltage_step);
4a6369e9
AD		 305int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
306 u16 voltage_id, u16 *voltage);
beb79f40
AD		 307int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
308 u16 *voltage,
309 u16 leakage_idx);
cc8dbbb4
AD		 310int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
311 u16 *leakage_id);
312int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
313 u16 *vddc, u16 *vddci,
314 u16 virtual_voltage_id,
315 u16 vbios_voltage_id);
e9f274b2
AD		 316int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
317 u16 virtual_voltage_id,
318 u16 *voltage);
ae5b0abb
AD		 319int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
320 u8 voltage_type,
321 u16 nominal_voltage,
322 u16 *true_voltage);
323int radeon_atom_get_min_voltage(struct radeon_device *rdev,
324 u8 voltage_type, u16 *min_voltage);
325int radeon_atom_get_max_voltage(struct radeon_device *rdev,
326 u8 voltage_type, u16 *max_voltage);
327int radeon_atom_get_voltage_table(struct radeon_device *rdev,
65171944 328 u8 voltage_type, u8 voltage_mode,
ae5b0abb 329 struct atom_voltage_table *voltage_table);
58653abd
AD		 330bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
331 u8 voltage_type, u8 voltage_mode);
636e2582
AD		 332int radeon_atom_get_svi2_info(struct radeon_device *rdev,
333 u8 voltage_type,
334 u8 *svd_gpio_id, u8 *svc_gpio_id);
ae5b0abb
AD		 335void radeon_atom_update_memory_dll(struct radeon_device *rdev,
336 u32 mem_clock);
337void radeon_atom_set_ac_timing(struct radeon_device *rdev,
338 u32 mem_clock);
339int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
340 u8 module_index,
341 struct atom_mc_reg_table *reg_table);
342int radeon_atom_get_memory_info(struct radeon_device *rdev,
343 u8 module_index, struct atom_memory_info *mem_info);
344int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
345 bool gddr5, u8 module_index,
346 struct atom_memory_clock_range_table *mclk_range_table);
347int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
348 u16 voltage_id, u16 *voltage);
f892034a 349void rs690_pm_info(struct radeon_device *rdev);
285484e2
JG		 350extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
351 unsigned *bankh, unsigned *mtaspect,
352 unsigned *tile_split);
3ce0a23d 353
771fe6b9
JG		 354/*
355 * Fences.
356 */
357struct radeon_fence_driver {
0bfa4b41 358 struct radeon_device *rdev;
771fe6b9 359 uint32_t scratch_reg;
30eb77f4
JG		 360 uint64_t gpu_addr;
361 volatile uint32_t *cpu_addr;
68e250b7
CK		 362 /* sync_seq is protected by ring emission lock */
363 uint64_t sync_seq[RADEON_NUM_RINGS];
bb635567 364 atomic64_t last_seq;
954605ca 365 bool initialized, delayed_irq;
0bfa4b41 366 struct delayed_work lockup_work;
771fe6b9
JG		 367};
368
369struct radeon_fence {
ad1a58a4 370 struct fence base;
954605ca 371
ad1a58a4
CK		 372 struct radeon_device *rdev;
373 uint64_t seq;
7465280c 374 /* RB, DMA, etc. */
ad1a58a4
CK		 375 unsigned ring;
376 bool is_vm_update;
954605ca 377
ad1a58a4 378 wait_queue_t fence_wake;
771fe6b9
JG		 379};
380
30eb77f4
JG		 381int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
382int radeon_fence_driver_init(struct radeon_device *rdev);
771fe6b9 383void radeon_fence_driver_fini(struct radeon_device *rdev);
eb98c709 384void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring);
876dc9f3 385int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
7465280c 386void radeon_fence_process(struct radeon_device *rdev, int ring);
771fe6b9 387bool radeon_fence_signaled(struct radeon_fence *fence);
04db4caf 388long radeon_fence_wait_timeout(struct radeon_fence *fence, bool interruptible, long timeout);
771fe6b9 389int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
37615527
CK		 390int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
391int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
0085c950
JG		 392int radeon_fence_wait_any(struct radeon_device *rdev,
393 struct radeon_fence **fences,
394 bool intr);
771fe6b9
JG		 395struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
396void radeon_fence_unref(struct radeon_fence **fence);
3b7a2b24 397unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
68e250b7
CK		 398bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
399void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
400static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
401 struct radeon_fence *b)
402{
403 if (!a) {
404 return b;
405 }
406
407 if (!b) {
408 return a;
409 }
410
411 BUG_ON(a->ring != b->ring);
412
413 if (a->seq > b->seq) {
414 return a;
415 } else {
416 return b;
417 }
418}
771fe6b9 419
ee60e29f
CK		 420static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
421 struct radeon_fence *b)
422{
423 if (!a) {
424 return false;
425 }
426
427 if (!b) {
428 return true;
429 }
430
431 BUG_ON(a->ring != b->ring);
432
433 return a->seq < b->seq;
434}
435
e024e110
DA		 436/*
437 * Tiling registers
438 */
439struct radeon_surface_reg {
4c788679 440 struct radeon_bo *bo;
e024e110
DA		 441};
442
443#define RADEON_GEM_MAX_SURFACES 8
771fe6b9
JG		 444
445/*
4c788679 446 * TTM.
771fe6b9 447 */
4c788679
JG		 448struct radeon_mman {
449 struct ttm_bo_global_ref bo_global_ref;
ba4420c2 450 struct drm_global_reference mem_global_ref;
4c788679 451 struct ttm_bo_device bdev;
0a0c7596
JG		 452 bool mem_global_referenced;
453 bool initialized;
2014b569
CK		 454
455#if defined(CONFIG_DEBUG_FS)
456 struct dentry *vram;
dd66d20e 457 struct dentry *gtt;
2014b569 458#endif
4c788679
JG		 459};
460
1d0c0942
CK		 461struct radeon_bo_list {
462 struct radeon_bo *robj;
463 struct ttm_validate_buffer tv;
464 uint64_t gpu_offset;
465 unsigned prefered_domains;
466 unsigned allowed_domains;
467 uint32_t tiling_flags;
468};
469
721604a1
JG		 470/* bo virtual address in a specific vm */
471struct radeon_bo_va {
e971bd5e 472 /* protected by bo being reserved */
721604a1 473 struct list_head bo_list;
721604a1 474 uint32_t flags;
94214635 475 struct radeon_fence *last_pt_update;
e971bd5e
CK		 476 unsigned ref_count;
477
478 /* protected by vm mutex */
0aea5e4a 479 struct interval_tree_node it;
036bf46a 480 struct list_head vm_status;
e971bd5e
CK		 481
482 /* constant after initialization */
483 struct radeon_vm *vm;
484 struct radeon_bo *bo;
721604a1
JG		 485};
486
4c788679
JG		 487struct radeon_bo {
488 /* Protected by gem.mutex */
489 struct list_head list;
490 /* Protected by tbo.reserved */
bda72d58 491 u32 initial_domain;
c9da4a4b 492 struct ttm_place placements[4];
312ea8da 493 struct ttm_placement placement;
4c788679
JG		 494 struct ttm_buffer_object tbo;
495 struct ttm_bo_kmap_obj kmap;
02376d82 496 u32 flags;
4c788679
JG		 497 unsigned pin_count;
498 void *kptr;
499 u32 tiling_flags;
500 u32 pitch;
501 int surface_reg;
721604a1
JG		 502 /* list of all virtual address to which this bo
503 * is associated to
504 */
505 struct list_head va;
4c788679
JG		 506 /* Constant after initialization */
507 struct radeon_device *rdev;
441921d5 508 struct drm_gem_object gem_base;
63bc620b 509
409851f4
JG		 510 struct ttm_bo_kmap_obj dma_buf_vmap;
511 pid_t pid;
341cb9e4
CK		 512
513 struct radeon_mn *mn;
49ecb10e 514 struct list_head mn_list;
4c788679 515};
7e4d15d9 516#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
771fe6b9 517
409851f4
JG		 518int radeon_gem_debugfs_init(struct radeon_device *rdev);
519
b15ba512
JG		 520/* sub-allocation manager, it has to be protected by another lock.
521 * By conception this is an helper for other part of the driver
522 * like the indirect buffer or semaphore, which both have their
523 * locking.
524 *
525 * Principe is simple, we keep a list of sub allocation in offset
526 * order (first entry has offset == 0, last entry has the highest
527 * offset).
528 *
529 * When allocating new object we first check if there is room at
530 * the end total_size - (last_object_offset + last_object_size) >=
531 * alloc_size. If so we allocate new object there.
532 *
533 * When there is not enough room at the end, we start waiting for
534 * each sub object until we reach object_offset+object_size >=
535 * alloc_size, this object then become the sub object we return.
536 *
537 * Alignment can't be bigger than page size.
538 *
539 * Hole are not considered for allocation to keep things simple.
540 * Assumption is that there won't be hole (all object on same
541 * alignment).
542 */
543struct radeon_sa_manager {
bfb38d35 544 wait_queue_head_t wq;
b15ba512 545 struct radeon_bo *bo;
c3b7fe8b
CK		 546 struct list_head *hole;
547 struct list_head flist[RADEON_NUM_RINGS];
548 struct list_head olist;
b15ba512
JG		 549 unsigned size;
550 uint64_t gpu_addr;
551 void *cpu_ptr;
552 uint32_t domain;
6c4f978b 553 uint32_t align;
b15ba512
JG		 554};
555
556struct radeon_sa_bo;
557
558/* sub-allocation buffer */
559struct radeon_sa_bo {
c3b7fe8b
CK		 560 struct list_head olist;
561 struct list_head flist;
b15ba512 562 struct radeon_sa_manager *manager;
e6661a96
CK		 563 unsigned soffset;
564 unsigned eoffset;
557017a0 565 struct radeon_fence *fence;
b15ba512
JG		 566};
567
771fe6b9
JG		 568/*
569 * GEM objects.
570 */
571struct radeon_gem {
4c788679 572 struct mutex mutex;
771fe6b9
JG		 573 struct list_head objects;
574};
575
576int radeon_gem_init(struct radeon_device *rdev);
577void radeon_gem_fini(struct radeon_device *rdev);
391bfec3 578int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
4c788679 579 int alignment, int initial_domain,
ed5cb43f 580 u32 flags, bool kernel,
4c788679 581 struct drm_gem_object **obj);
771fe6b9 582
ff72145b
DA		 583int radeon_mode_dumb_create(struct drm_file *file_priv,
584 struct drm_device *dev,
585 struct drm_mode_create_dumb *args);
586int radeon_mode_dumb_mmap(struct drm_file *filp,
587 struct drm_device *dev,
588 uint32_t handle, uint64_t *offset_p);
771fe6b9 589
c1341e52
JG		 590/*
591 * Semaphores.
592 */
c1341e52 593struct radeon_semaphore {
975700d2
CK		 594 struct radeon_sa_bo *sa_bo;
595 signed waiters;
596 uint64_t gpu_addr;
c1341e52
JG		 597};
598
c1341e52
JG		 599int radeon_semaphore_create(struct radeon_device *rdev,
600 struct radeon_semaphore **semaphore);
1654b817 601bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
c1341e52 602 struct radeon_semaphore *semaphore);
1654b817 603bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
c1341e52
JG		 604 struct radeon_semaphore *semaphore);
605void radeon_semaphore_free(struct radeon_device *rdev,
220907d9 606 struct radeon_semaphore **semaphore,
a8c05940 607 struct radeon_fence *fence);
c1341e52 608
975700d2
CK		 609/*
610 * Synchronization
611 */
612struct radeon_sync {
613 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
614 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
ad1a58a4 615 struct radeon_fence *last_vm_update;
975700d2
CK		 616};
617
618void radeon_sync_create(struct radeon_sync *sync);
619void radeon_sync_fence(struct radeon_sync *sync,
620 struct radeon_fence *fence);
621int radeon_sync_resv(struct radeon_device *rdev,
622 struct radeon_sync *sync,
623 struct reservation_object *resv,
624 bool shared);
625int radeon_sync_rings(struct radeon_device *rdev,
626 struct radeon_sync *sync,
627 int waiting_ring);
628void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
629 struct radeon_fence *fence);
630
771fe6b9
JG		 631/*
632 * GART structures, functions & helpers
633 */
634struct radeon_mc;
635
a77f1718 636#define RADEON_GPU_PAGE_SIZE 4096
d594e46a 637#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
003cefe0 638#define RADEON_GPU_PAGE_SHIFT 12
721604a1 639#define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
a77f1718 640
77497f27
MD		 641#define RADEON_GART_PAGE_DUMMY 0
642#define RADEON_GART_PAGE_VALID (1 << 0)
643#define RADEON_GART_PAGE_READ (1 << 1)
644#define RADEON_GART_PAGE_WRITE (1 << 2)
645#define RADEON_GART_PAGE_SNOOP (1 << 3)
646
771fe6b9
JG		 647struct radeon_gart {
648 dma_addr_t table_addr;
c9a1be96
JG		 649 struct radeon_bo *robj;
650 void *ptr;
771fe6b9
JG		 651 unsigned num_gpu_pages;
652 unsigned num_cpu_pages;
653 unsigned table_size;
771fe6b9 654 struct page **pages;
cb658906 655 uint64_t *pages_entry;
771fe6b9
JG		 656 bool ready;
657};
658
659int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
660void radeon_gart_table_ram_free(struct radeon_device *rdev);
661int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
662void radeon_gart_table_vram_free(struct radeon_device *rdev);
c9a1be96
JG		 663int radeon_gart_table_vram_pin(struct radeon_device *rdev);
664void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
771fe6b9
JG		 665int radeon_gart_init(struct radeon_device *rdev);
666void radeon_gart_fini(struct radeon_device *rdev);
667void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
668 int pages);
669int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
c39d3516 670 int pages, struct page **pagelist,
77497f27 671 dma_addr_t *dma_addr, uint32_t flags);
771fe6b9
JG		 672
673
674/*
675 * GPU MC structures, functions & helpers
676 */
677struct radeon_mc {
678 resource_size_t aper_size;
679 resource_size_t aper_base;
680 resource_size_t agp_base;
7a50f01a
DA		 681 /* for some chips with <= 32MB we need to lie
682 * about vram size near mc fb location */
3ce0a23d 683 u64 mc_vram_size;
d594e46a 684 u64 visible_vram_size;
3ce0a23d
JG		 685 u64 gtt_size;
686 u64 gtt_start;
687 u64 gtt_end;
3ce0a23d
JG		 688 u64 vram_start;
689 u64 vram_end;
771fe6b9 690 unsigned vram_width;
3ce0a23d 691 u64 real_vram_size;
771fe6b9
JG		 692 int vram_mtrr;
693 bool vram_is_ddr;
d594e46a 694 bool igp_sideport_enabled;
8d369bb1 695 u64 gtt_base_align;
9ed8b1f9 696 u64 mc_mask;
771fe6b9
JG		 697};
698
06b6476d
AD		 699bool radeon_combios_sideport_present(struct radeon_device *rdev);
700bool radeon_atombios_sideport_present(struct radeon_device *rdev);
771fe6b9
JG		 701
702/*
703 * GPU scratch registers structures, functions & helpers
704 */
705struct radeon_scratch {
706 unsigned num_reg;
724c80e1 707 uint32_t reg_base;
771fe6b9
JG		 708 bool free[32];
709 uint32_t reg[32];
710};
711
712int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
713void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
714
75efdee1
AD		 715/*
716 * GPU doorbell structures, functions & helpers
717 */
d5754ab8
AL		 718#define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
719
75efdee1 720struct radeon_doorbell {
75efdee1 721 /* doorbell mmio */
d5754ab8
AL		 722 resource_size_t base;
723 resource_size_t size;
724 u32 __iomem *ptr;
725 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
a10e04f4 726 DECLARE_BITMAP(used, RADEON_MAX_DOORBELLS);
75efdee1
AD		 727};
728
729int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
730void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
ebff8453
OG		 731void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
732 phys_addr_t *aperture_base,
733 size_t *aperture_size,
734 size_t *start_offset);
771fe6b9
JG		 735
736/*
737 * IRQS.
738 */
6f34be50 739
fa7f517c
CK		 740struct radeon_flip_work {
741 struct work_struct flip_work;
742 struct work_struct unpin_work;
743 struct radeon_device *rdev;
744 int crtc_id;
b8fc75cf 745 u32 target_vblank;
c60381bd 746 uint64_t base;
6f34be50 747 struct drm_pending_vblank_event *event;
fa7f517c 748 struct radeon_bo *old_rbo;
a0e84764 749 struct fence *fence;
c63dd758 750 bool async;
6f34be50
AD		 751};
752
753struct r500_irq_stat_regs {
754 u32 disp_int;
f122c610 755 u32 hdmi0_status;
6f34be50
AD		 756};
757
758struct r600_irq_stat_regs {
759 u32 disp_int;
760 u32 disp_int_cont;
761 u32 disp_int_cont2;
762 u32 d1grph_int;
763 u32 d2grph_int;
f122c610
AD		 764 u32 hdmi0_status;
765 u32 hdmi1_status;
6f34be50
AD		 766};
767
768struct evergreen_irq_stat_regs {
769 u32 disp_int;
770 u32 disp_int_cont;
771 u32 disp_int_cont2;
772 u32 disp_int_cont3;
773 u32 disp_int_cont4;
774 u32 disp_int_cont5;
775 u32 d1grph_int;
776 u32 d2grph_int;
777 u32 d3grph_int;
778 u32 d4grph_int;
779 u32 d5grph_int;
780 u32 d6grph_int;
f122c610
AD		 781 u32 afmt_status1;
782 u32 afmt_status2;
783 u32 afmt_status3;
784 u32 afmt_status4;
785 u32 afmt_status5;
786 u32 afmt_status6;
6f34be50
AD		 787};
788
a59781bb
AD		 789struct cik_irq_stat_regs {
790 u32 disp_int;
791 u32 disp_int_cont;
792 u32 disp_int_cont2;
793 u32 disp_int_cont3;
794 u32 disp_int_cont4;
795 u32 disp_int_cont5;
796 u32 disp_int_cont6;
f5d636d2
CK		 797 u32 d1grph_int;
798 u32 d2grph_int;
799 u32 d3grph_int;
800 u32 d4grph_int;
801 u32 d5grph_int;
802 u32 d6grph_int;
a59781bb
AD		 803};
804
6f34be50
AD		 805union radeon_irq_stat_regs {
806 struct r500_irq_stat_regs r500;
807 struct r600_irq_stat_regs r600;
808 struct evergreen_irq_stat_regs evergreen;
a59781bb 809 struct cik_irq_stat_regs cik;
6f34be50
AD		 810};
811
771fe6b9 812struct radeon_irq {
fb98257a
CK		 813 bool installed;
814 spinlock_t lock;
736fc37f 815 atomic_t ring_int[RADEON_NUM_RINGS];
fb98257a 816 bool crtc_vblank_int[RADEON_MAX_CRTCS];
736fc37f 817 atomic_t pflip[RADEON_MAX_CRTCS];
fb98257a
CK		 818 wait_queue_head_t vblank_queue;
819 bool hpd[RADEON_MAX_HPD_PINS];
fb98257a
CK		 820 bool afmt[RADEON_MAX_AFMT_BLOCKS];
821 union radeon_irq_stat_regs stat_regs;
4a6369e9 822 bool dpm_thermal;
771fe6b9
JG		 823};
824
825int radeon_irq_kms_init(struct radeon_device *rdev);
826void radeon_irq_kms_fini(struct radeon_device *rdev);
1b37078b 827void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
954605ca 828bool radeon_irq_kms_sw_irq_get_delayed(struct radeon_device *rdev, int ring);
1b37078b 829void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
6f34be50
AD		 830void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
831void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
fb98257a
CK		 832void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
833void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
834void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
835void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
771fe6b9
JG		 836
837/*
e32eb50d 838 * CP & rings.
771fe6b9 839 */
7465280c 840
771fe6b9 841struct radeon_ib {
68470ae7
JG		 842 struct radeon_sa_bo *sa_bo;
843 uint32_t length_dw;
844 uint64_t gpu_addr;
845 uint32_t *ptr;
876dc9f3 846 int ring;
68470ae7 847 struct radeon_fence *fence;
4bf3dd92 848 struct radeon_vm *vm;
68470ae7 849 bool is_const_ib;
975700d2 850 struct radeon_sync sync;
771fe6b9
JG		 851};
852
e32eb50d 853struct radeon_ring {
4c788679 854 struct radeon_bo *ring_obj;
771fe6b9 855 volatile uint32_t *ring;
5596a9db 856 unsigned rptr_offs;
45df6803 857 unsigned rptr_save_reg;
89d35807
AD		 858 u64 next_rptr_gpu_addr;
859 volatile u32 *next_rptr_cpu_addr;
771fe6b9
JG		 860 unsigned wptr;
861 unsigned wptr_old;
862 unsigned ring_size;
863 unsigned ring_free_dw;
864 int count_dw;
aee4aa73
CK		 865 atomic_t last_rptr;
866 atomic64_t last_activity;
771fe6b9
JG		 867 uint64_t gpu_addr;
868 uint32_t align_mask;
869 uint32_t ptr_mask;
771fe6b9 870 bool ready;
78c5560a 871 u32 nop;
8b25ed34 872 u32 idx;
5f0839c1
JG		 873 u64 last_semaphore_signal_addr;
874 u64 last_semaphore_wait_addr;
963e81f9
AD		 875 /* for CIK queues */
876 u32 me;
877 u32 pipe;
878 u32 queue;
879 struct radeon_bo *mqd_obj;
d5754ab8 880 u32 doorbell_index;
963e81f9
AD		 881 unsigned wptr_offs;
882};
883
884struct radeon_mec {
885 struct radeon_bo *hpd_eop_obj;
886 u64 hpd_eop_gpu_addr;
887 u32 num_pipe;
888 u32 num_mec;
889 u32 num_queue;
771fe6b9
JG		 890};
891
721604a1
JG		 892/*
893 * VM
894 */
ee60e29f 895
fa87e62d 896/* maximum number of VMIDs */
ee60e29f
CK		 897#define RADEON_NUM_VM 16
898
fa87e62d 899/* number of entries in page table */
4510fb98 900#define RADEON_VM_PTE_COUNT (1 << radeon_vm_block_size)
fa87e62d 901
1c01103c
AD		 902/* PTBs (Page Table Blocks) need to be aligned to 32K */
903#define RADEON_VM_PTB_ALIGN_SIZE 32768
904#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
905#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
906
24c16439
CK		 907#define R600_PTE_VALID (1 << 0)
908#define R600_PTE_SYSTEM (1 << 1)
909#define R600_PTE_SNOOPED (1 << 2)
910#define R600_PTE_READABLE (1 << 5)
911#define R600_PTE_WRITEABLE (1 << 6)
912
ec3dbbcb
CK		 913/* PTE (Page Table Entry) fragment field for different page sizes */
914#define R600_PTE_FRAG_4KB (0 << 7)
915#define R600_PTE_FRAG_64KB (4 << 7)
916#define R600_PTE_FRAG_256KB (6 << 7)
917
33fa9fe3
CK		 918/* flags needed to be set so we can copy directly from the GART table */
919#define R600_PTE_GART_MASK ( R600_PTE_READABLE | R600_PTE_WRITEABLE | \
920 R600_PTE_SYSTEM | R600_PTE_VALID )
0e97703c 921
6d2f2944
CK		 922struct radeon_vm_pt {
923 struct radeon_bo *bo;
924 uint64_t addr;
925};
926
7c42bc1a
CK		 927struct radeon_vm_id {
928 unsigned id;
929 uint64_t pd_gpu_addr;
930 /* last flushed PD/PT update */
931 struct radeon_fence *flushed_updates;
932 /* last use of vmid */
933 struct radeon_fence *last_id_use;
934};
935
721604a1 936struct radeon_vm {
94214635
CK		 937 struct mutex mutex;
938
7c42bc1a 939 struct rb_root va;
90a51a32 940
f7a3db75
CK		 941 /* protecting invalidated and freed */
942 spinlock_t status_lock;
943
e31ad969 944 /* BOs moved, but not yet updated in the PT */
7c42bc1a 945 struct list_head invalidated;
e31ad969 946
036bf46a 947 /* BOs freed, but not yet updated in the PT */
7c42bc1a 948 struct list_head freed;
036bf46a 949
161ab658
CK		 950 /* BOs cleared in the PT */
951 struct list_head cleared;
952
90a51a32 953 /* contains the page directory */
7c42bc1a
CK		 954 struct radeon_bo *page_directory;
955 unsigned max_pde_used;
90a51a32
CK		 956
957 /* array of page tables, one for each page directory entry */
7c42bc1a 958 struct radeon_vm_pt *page_tables;
90a51a32 959
7c42bc1a 960 struct radeon_bo_va *ib_bo_va;
cc9e67e3 961
7c42bc1a
CK		 962 /* for id and flush management per ring */
963 struct radeon_vm_id ids[RADEON_NUM_RINGS];
721604a1
JG		 964};
965
721604a1 966struct radeon_vm_manager {
ee60e29f 967 struct radeon_fence *active[RADEON_NUM_VM];
721604a1 968 uint32_t max_pfn;
721604a1
JG		 969 /* number of VMIDs */
970 unsigned nvm;
971 /* vram base address for page table entry */
972 u64 vram_base_offset;
67e915e4
AD		 973 /* is vm enabled? */
974 bool enabled;
054e01d6
CK		 975 /* for hw to save the PD addr on suspend/resume */
976 uint32_t saved_table_addr[RADEON_NUM_VM];
721604a1
JG		 977};
978
979/*
980 * file private structure
981 */
982struct radeon_fpriv {
983 struct radeon_vm vm;
984};
985
d8f60cfc
AD		 986/*
987 * R6xx+ IH ring
988 */
989struct r600_ih {
4c788679 990 struct radeon_bo *ring_obj;
d8f60cfc
AD		 991 volatile uint32_t *ring;
992 unsigned rptr;
d8f60cfc
AD		 993 unsigned ring_size;
994 uint64_t gpu_addr;
d8f60cfc 995 uint32_t ptr_mask;
c20dc369 996 atomic_t lock;
d8f60cfc
AD		 997 bool enabled;
998};
999
347e7592 1000/*
2948f5e6 1001 * RLC stuff
347e7592 1002 */
2948f5e6
AD		 1003#include "clearstate_defs.h"
1004
1005struct radeon_rlc {
347e7592
AD		 1006 /* for power gating */
1007 struct radeon_bo *save_restore_obj;
1008 uint64_t save_restore_gpu_addr;
2948f5e6 1009 volatile uint32_t *sr_ptr;
1fd11777 1010 const u32 *reg_list;
2948f5e6 1011 u32 reg_list_size;
347e7592
AD		 1012 /* for clear state */
1013 struct radeon_bo *clear_state_obj;
1014 uint64_t clear_state_gpu_addr;
2948f5e6 1015 volatile uint32_t *cs_ptr;
1fd11777 1016 const struct cs_section_def *cs_data;
22c775ce
AD		 1017 u32 clear_state_size;
1018 /* for cp tables */
1019 struct radeon_bo *cp_table_obj;
1020 uint64_t cp_table_gpu_addr;
1021 volatile uint32_t *cp_table_ptr;
1022 u32 cp_table_size;
347e7592
AD		 1023};
1024
69e130a6 1025int radeon_ib_get(struct radeon_device *rdev, int ring,
4bf3dd92
CK		 1026 struct radeon_ib *ib, struct radeon_vm *vm,
1027 unsigned size);
f2e39221 1028void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
4ef72566 1029int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
1538a9e0 1030 struct radeon_ib *const_ib, bool hdp_flush);
771fe6b9
JG		 1031int radeon_ib_pool_init(struct radeon_device *rdev);
1032void radeon_ib_pool_fini(struct radeon_device *rdev);
7bd560e8 1033int radeon_ib_ring_tests(struct radeon_device *rdev);
771fe6b9 1034/* Ring access between begin & end cannot sleep */
89d35807
AD		 1035bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
1036 struct radeon_ring *ring);
e32eb50d
CK		 1037void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1038int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1039int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1538a9e0
MD		 1040void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1041 bool hdp_flush);
1042void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp,
1043 bool hdp_flush);
d6999bc7 1044void radeon_ring_undo(struct radeon_ring *ring);
e32eb50d
CK		 1045void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1046int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
ff212f25
CK		 1047void radeon_ring_lockup_update(struct radeon_device *rdev,
1048 struct radeon_ring *ring);
069211e5 1049bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
55d7c221
CK		 1050unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1051 uint32_t **data);
1052int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1053 unsigned size, uint32_t *data);
e32eb50d 1054int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
ea31bf69 1055 unsigned rptr_offs, u32 nop);
e32eb50d 1056void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
771fe6b9
JG		 1057
1058
4d75658b
AD		 1059/* r600 async dma */
1060void r600_dma_stop(struct radeon_device *rdev);
1061int r600_dma_resume(struct radeon_device *rdev);
1062void r600_dma_fini(struct radeon_device *rdev);
1063
8c5fd7ef
AD		 1064void cayman_dma_stop(struct radeon_device *rdev);
1065int cayman_dma_resume(struct radeon_device *rdev);
1066void cayman_dma_fini(struct radeon_device *rdev);
1067
771fe6b9
JG		 1068/*
1069 * CS.
1070 */
771fe6b9 1071struct radeon_cs_chunk {
771fe6b9
JG		 1072 uint32_t length_dw;
1073 uint32_t *kdata;
721604a1 1074 void __user *user_ptr;
771fe6b9
JG		 1075};
1076
1077struct radeon_cs_parser {
c8c15ff1 1078 struct device *dev;
771fe6b9
JG		 1079 struct radeon_device *rdev;
1080 struct drm_file *filp;
1081 /* chunks */
1082 unsigned nchunks;
1083 struct radeon_cs_chunk *chunks;
1084 uint64_t *chunks_array;
1085 /* IB */
1086 unsigned idx;
1087 /* relocations */
1088 unsigned nrelocs;
1d0c0942 1089 struct radeon_bo_list *relocs;
1d0c0942 1090 struct radeon_bo_list *vm_bos;
771fe6b9 1091 struct list_head validated;
cf4ccd01 1092 unsigned dma_reloc_idx;
771fe6b9 1093 /* indices of various chunks */
6d2d13dd
CK		 1094 struct radeon_cs_chunk *chunk_ib;
1095 struct radeon_cs_chunk *chunk_relocs;
1096 struct radeon_cs_chunk *chunk_flags;
1097 struct radeon_cs_chunk *chunk_const_ib;
f2e39221
JG		 1098 struct radeon_ib ib;
1099 struct radeon_ib const_ib;
771fe6b9 1100 void *track;
3ce0a23d 1101 unsigned family;
e70f224c 1102 int parser_error;
721604a1
JG		 1103 u32 cs_flags;
1104 u32 ring;
1105 s32 priority;
ecff665f 1106 struct ww_acquire_ctx ticket;
771fe6b9
JG		 1107};
1108
28a326c5
ML		 1109static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1110{
6d2d13dd 1111 struct radeon_cs_chunk *ibc = p->chunk_ib;
28a326c5
ML		 1112
1113 if (ibc->kdata)
1114 return ibc->kdata[idx];
1115 return p->ib.ptr[idx];
1116}
1117
513bcb46 1118
771fe6b9
JG		 1119struct radeon_cs_packet {
1120 unsigned idx;
1121 unsigned type;
1122 unsigned reg;
1123 unsigned opcode;
1124 int count;
1125 unsigned one_reg_wr;
1126};
1127
1128typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1129 struct radeon_cs_packet *pkt,
1130 unsigned idx, unsigned reg);
1131typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1132 struct radeon_cs_packet *pkt);
1133
1134
1135/*
1136 * AGP
1137 */
1138int radeon_agp_init(struct radeon_device *rdev);
0ebf1717 1139void radeon_agp_resume(struct radeon_device *rdev);
10b06122 1140void radeon_agp_suspend(struct radeon_device *rdev);
771fe6b9
JG		 1141void radeon_agp_fini(struct radeon_device *rdev);
1142
1143
1144/*
1145 * Writeback
1146 */
1147struct radeon_wb {
4c788679 1148 struct radeon_bo *wb_obj;
771fe6b9
JG		 1149 volatile uint32_t *wb;
1150 uint64_t gpu_addr;
724c80e1 1151 bool enabled;
d0f8a854 1152 bool use_event;
771fe6b9
JG		 1153};
1154
724c80e1 1155#define RADEON_WB_SCRATCH_OFFSET 0
89d35807 1156#define RADEON_WB_RING0_NEXT_RPTR 256
724c80e1 1157#define RADEON_WB_CP_RPTR_OFFSET 1024
0c88a02e
AD		 1158#define RADEON_WB_CP1_RPTR_OFFSET 1280
1159#define RADEON_WB_CP2_RPTR_OFFSET 1536
4d75658b 1160#define R600_WB_DMA_RPTR_OFFSET 1792
724c80e1 1161#define R600_WB_IH_WPTR_OFFSET 2048
f60cbd11 1162#define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
d0f8a854 1163#define R600_WB_EVENT_OFFSET 3072
963e81f9
AD		 1164#define CIK_WB_CP1_WPTR_OFFSET 3328
1165#define CIK_WB_CP2_WPTR_OFFSET 3584
adfed2b0
AD		 1166#define R600_WB_DMA_RING_TEST_OFFSET 3588
1167#define CAYMAN_WB_DMA1_RING_TEST_OFFSET 3592
724c80e1 1168
c93bb85b
JG		 1169/**
1170 * struct radeon_pm - power management datas
1171 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1172 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1173 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1174 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1175 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1176 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1177 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1178 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1179 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
25985edc 1180 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
c93bb85b
JG		 1181 * @needed_bandwidth: current bandwidth needs
1182 *
1183 * It keeps track of various data needed to take powermanagement decision.
25985edc 1184 * Bandwidth need is used to determine minimun clock of the GPU and memory.
c93bb85b
JG		 1185 * Equation between gpu/memory clock and available bandwidth is hw dependent
1186 * (type of memory, bus size, efficiency, ...)
1187 */
ce8f5370
AD		 1188
1189enum radeon_pm_method {
1190 PM_METHOD_PROFILE,
1191 PM_METHOD_DYNPM,
da321c8a 1192 PM_METHOD_DPM,
ce8f5370
AD		 1193};
1194
1195enum radeon_dynpm_state {
1196 DYNPM_STATE_DISABLED,
1197 DYNPM_STATE_MINIMUM,
1198 DYNPM_STATE_PAUSED,
3f53eb6f
RW		 1199 DYNPM_STATE_ACTIVE,
1200 DYNPM_STATE_SUSPENDED,
c913e23a 1201};
ce8f5370
AD		 1202enum radeon_dynpm_action {
1203 DYNPM_ACTION_NONE,
1204 DYNPM_ACTION_MINIMUM,
1205 DYNPM_ACTION_DOWNCLOCK,
1206 DYNPM_ACTION_UPCLOCK,
1207 DYNPM_ACTION_DEFAULT
c913e23a 1208};
56278a8e
AD		 1209
1210enum radeon_voltage_type {
1211 VOLTAGE_NONE = 0,
1212 VOLTAGE_GPIO,
1213 VOLTAGE_VDDC,
1214 VOLTAGE_SW
1215};
1216
0ec0e74f 1217enum radeon_pm_state_type {
da321c8a 1218 /* not used for dpm */
0ec0e74f
AD		 1219 POWER_STATE_TYPE_DEFAULT,
1220 POWER_STATE_TYPE_POWERSAVE,
da321c8a 1221 /* user selectable states */
0ec0e74f
AD		 1222 POWER_STATE_TYPE_BATTERY,
1223 POWER_STATE_TYPE_BALANCED,
1224 POWER_STATE_TYPE_PERFORMANCE,
da321c8a
AD		 1225 /* internal states */
1226 POWER_STATE_TYPE_INTERNAL_UVD,
1227 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1228 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1229 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1230 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1231 POWER_STATE_TYPE_INTERNAL_BOOT,
1232 POWER_STATE_TYPE_INTERNAL_THERMAL,
1233 POWER_STATE_TYPE_INTERNAL_ACPI,
1234 POWER_STATE_TYPE_INTERNAL_ULV,
edcaa5b1 1235 POWER_STATE_TYPE_INTERNAL_3DPERF,
0ec0e74f
AD		 1236};
1237
ce8f5370
AD		 1238enum radeon_pm_profile_type {
1239 PM_PROFILE_DEFAULT,
1240 PM_PROFILE_AUTO,
1241 PM_PROFILE_LOW,
c9e75b21 1242 PM_PROFILE_MID,
ce8f5370
AD		 1243 PM_PROFILE_HIGH,
1244};
1245
1246#define PM_PROFILE_DEFAULT_IDX 0
1247#define PM_PROFILE_LOW_SH_IDX 1
c9e75b21
AD		 1248#define PM_PROFILE_MID_SH_IDX 2
1249#define PM_PROFILE_HIGH_SH_IDX 3
1250#define PM_PROFILE_LOW_MH_IDX 4
1251#define PM_PROFILE_MID_MH_IDX 5
1252#define PM_PROFILE_HIGH_MH_IDX 6
1253#define PM_PROFILE_MAX 7
ce8f5370
AD		 1254
1255struct radeon_pm_profile {
1256 int dpms_off_ps_idx;
1257 int dpms_on_ps_idx;
1258 int dpms_off_cm_idx;
1259 int dpms_on_cm_idx;
516d0e46
AD		 1260};
1261
21a8122a
AD		 1262enum radeon_int_thermal_type {
1263 THERMAL_TYPE_NONE,
da321c8a
AD		 1264 THERMAL_TYPE_EXTERNAL,
1265 THERMAL_TYPE_EXTERNAL_GPIO,
21a8122a
AD		 1266 THERMAL_TYPE_RV6XX,
1267 THERMAL_TYPE_RV770,
da321c8a 1268 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
21a8122a 1269 THERMAL_TYPE_EVERGREEN,
e33df25f 1270 THERMAL_TYPE_SUMO,
4fddba1f 1271 THERMAL_TYPE_NI,
14607d08 1272 THERMAL_TYPE_SI,
da321c8a 1273 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
51150207 1274 THERMAL_TYPE_CI,
16fbe00d 1275 THERMAL_TYPE_KV,
21a8122a
AD		 1276};
1277
56278a8e
AD		 1278struct radeon_voltage {
1279 enum radeon_voltage_type type;
1280 /* gpio voltage */
1281 struct radeon_gpio_rec gpio;
1282 u32 delay; /* delay in usec from voltage drop to sclk change */
1283 bool active_high; /* voltage drop is active when bit is high */
1284 /* VDDC voltage */
1285 u8 vddc_id; /* index into vddc voltage table */
1286 u8 vddci_id; /* index into vddci voltage table */
1287 bool vddci_enabled;
1288 /* r6xx+ sw */
2feea49a
AD		 1289 u16 voltage;
1290 /* evergreen+ vddci */
1291 u16 vddci;
56278a8e
AD		 1292};
1293
d7311171
AD		 1294/* clock mode flags */
1295#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1296
56278a8e
AD		 1297struct radeon_pm_clock_info {
1298 /* memory clock */
1299 u32 mclk;
1300 /* engine clock */
1301 u32 sclk;
1302 /* voltage info */
1303 struct radeon_voltage voltage;
d7311171 1304 /* standardized clock flags */
56278a8e
AD		 1305 u32 flags;
1306};
1307
a48b9b4e 1308/* state flags */
d7311171 1309#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
a48b9b4e 1310
56278a8e 1311struct radeon_power_state {
0ec0e74f 1312 enum radeon_pm_state_type type;
8f3f1c9a 1313 struct radeon_pm_clock_info *clock_info;
56278a8e
AD		 1314 /* number of valid clock modes in this power state */
1315 int num_clock_modes;
56278a8e 1316 struct radeon_pm_clock_info *default_clock_mode;
a48b9b4e
AD		 1317 /* standardized state flags */
1318 u32 flags;
79daedc9
AD		 1319 u32 misc; /* vbios specific flags */
1320 u32 misc2; /* vbios specific flags */
1321 int pcie_lanes; /* pcie lanes */
56278a8e
AD		 1322};
1323
27459324
RM		 1324/*
1325 * Some modes are overclocked by very low value, accept them
1326 */
1327#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1328
2e9d4c05
AD		 1329enum radeon_dpm_auto_throttle_src {
1330 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1331 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1332};
1333
1334enum radeon_dpm_event_src {
1335 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1336 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1337 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1338 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1339 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1340};
1341
58bd2a88
AD		 1342#define RADEON_MAX_VCE_LEVELS 6
1343
b62d628b
AD		 1344enum radeon_vce_level {
1345 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1346 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1347 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1348 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1349 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1350 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1351};
1352
da321c8a
AD		 1353struct radeon_ps {
1354 u32 caps; /* vbios flags */
1355 u32 class; /* vbios flags */
1356 u32 class2; /* vbios flags */
1357 /* UVD clocks */
1358 u32 vclk;
1359 u32 dclk;
c4453e66
AD		 1360 /* VCE clocks */
1361 u32 evclk;
1362 u32 ecclk;
b62d628b
AD		 1363 bool vce_active;
1364 enum radeon_vce_level vce_level;
da321c8a
AD		 1365 /* asic priv */
1366 void *ps_priv;
1367};
1368
1369struct radeon_dpm_thermal {
1370 /* thermal interrupt work */
1371 struct work_struct work;
1372 /* low temperature threshold */
1373 int min_temp;
1374 /* high temperature threshold */
1375 int max_temp;
1376 /* was interrupt low to high or high to low */
1377 bool high_to_low;
1378};
1379
d22b7e40
AD		 1380enum radeon_clk_action
1381{
1382 RADEON_SCLK_UP = 1,
1383 RADEON_SCLK_DOWN
1384};
1385
1386struct radeon_blacklist_clocks
1387{
1388 u32 sclk;
1389 u32 mclk;
1390 enum radeon_clk_action action;
1391};
1392
61b7d601
AD		 1393struct radeon_clock_and_voltage_limits {
1394 u32 sclk;
1395 u32 mclk;
cdf6e805
AD		 1396 u16 vddc;
1397 u16 vddci;
61b7d601
AD		 1398};
1399
1400struct radeon_clock_array {
1401 u32 count;
1402 u32 *values;
1403};
1404
1405struct radeon_clock_voltage_dependency_entry {
1406 u32 clk;
1407 u16 v;
1408};
1409
1410struct radeon_clock_voltage_dependency_table {
1411 u32 count;
1412 struct radeon_clock_voltage_dependency_entry *entries;
1413};
1414
ef976ec4
AD		 1415union radeon_cac_leakage_entry {
1416 struct {
1417 u16 vddc;
1418 u32 leakage;
1419 };
1420 struct {
1421 u16 vddc1;
1422 u16 vddc2;
1423 u16 vddc3;
1424 };
61b7d601
AD		 1425};
1426
1427struct radeon_cac_leakage_table {
1428 u32 count;
ef976ec4 1429 union radeon_cac_leakage_entry *entries;
61b7d601
AD		 1430};
1431
929ee7a8
AD		 1432struct radeon_phase_shedding_limits_entry {
1433 u16 voltage;
1434 u32 sclk;
1435 u32 mclk;
1436};
1437
1438struct radeon_phase_shedding_limits_table {
1439 u32 count;
1440 struct radeon_phase_shedding_limits_entry *entries;
1441};
1442
84a9d9ee
AD		 1443struct radeon_uvd_clock_voltage_dependency_entry {
1444 u32 vclk;
1445 u32 dclk;
1446 u16 v;
1447};
1448
1449struct radeon_uvd_clock_voltage_dependency_table {
1450 u8 count;
1451 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1452};
1453
d29f013b
AD		 1454struct radeon_vce_clock_voltage_dependency_entry {
1455 u32 ecclk;
1456 u32 evclk;
1457 u16 v;
1458};
1459
1460struct radeon_vce_clock_voltage_dependency_table {
1461 u8 count;
1462 struct radeon_vce_clock_voltage_dependency_entry *entries;
1463};
1464
a5cb318e
AD		 1465struct radeon_ppm_table {
1466 u8 ppm_design;
1467 u16 cpu_core_number;
1468 u32 platform_tdp;
1469 u32 small_ac_platform_tdp;
1470 u32 platform_tdc;
1471 u32 small_ac_platform_tdc;
1472 u32 apu_tdp;
1473 u32 dgpu_tdp;
1474 u32 dgpu_ulv_power;
1475 u32 tj_max;
1476};
1477
58cb7632
AD		 1478struct radeon_cac_tdp_table {
1479 u16 tdp;
1480 u16 configurable_tdp;
1481 u16 tdc;
1482 u16 battery_power_limit;
1483 u16 small_power_limit;
1484 u16 low_cac_leakage;
1485 u16 high_cac_leakage;
1486 u16 maximum_power_delivery_limit;
1487};
1488
61b7d601
AD		 1489struct radeon_dpm_dynamic_state {
1490 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1491 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1492 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
dd621a22 1493 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
4489cd62 1494 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
84a9d9ee 1495 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
d29f013b 1496 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
94a914f5
AD		 1497 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1498 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
61b7d601
AD		 1499 struct radeon_clock_array valid_sclk_values;
1500 struct radeon_clock_array valid_mclk_values;
1501 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1502 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1503 u32 mclk_sclk_ratio;
1504 u32 sclk_mclk_delta;
1505 u16 vddc_vddci_delta;
1506 u16 min_vddc_for_pcie_gen2;
1507 struct radeon_cac_leakage_table cac_leakage_table;
929ee7a8 1508 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
a5cb318e 1509 struct radeon_ppm_table *ppm_table;
58cb7632 1510 struct radeon_cac_tdp_table *cac_tdp_table;
61b7d601
AD		 1511};
1512
1513struct radeon_dpm_fan {
1514 u16 t_min;
1515 u16 t_med;
1516 u16 t_high;
1517 u16 pwm_min;
1518 u16 pwm_med;
1519 u16 pwm_high;
1520 u8 t_hyst;
1521 u32 cycle_delay;
1522 u16 t_max;
e03cea36
AD		 1523 u8 control_mode;
1524 u16 default_max_fan_pwm;
1525 u16 default_fan_output_sensitivity;
1526 u16 fan_output_sensitivity;
61b7d601
AD		 1527 bool ucode_fan_control;
1528};
1529
32ce4652
AD		 1530enum radeon_pcie_gen {
1531 RADEON_PCIE_GEN1 = 0,
1532 RADEON_PCIE_GEN2 = 1,
1533 RADEON_PCIE_GEN3 = 2,
1534 RADEON_PCIE_GEN_INVALID = 0xffff
1535};
1536
70d01a5e
AD		 1537enum radeon_dpm_forced_level {
1538 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1539 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1540 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1541};
1542
58bd2a88
AD		 1543struct radeon_vce_state {
1544 /* vce clocks */
1545 u32 evclk;
1546 u32 ecclk;
1547 /* gpu clocks */
1548 u32 sclk;
1549 u32 mclk;
1550 u8 clk_idx;
1551 u8 pstate;
1552};
1553
da321c8a
AD		 1554struct radeon_dpm {
1555 struct radeon_ps *ps;
1556 /* number of valid power states */
1557 int num_ps;
1558 /* current power state that is active */
1559 struct radeon_ps *current_ps;
1560 /* requested power state */
1561 struct radeon_ps *requested_ps;
1562 /* boot up power state */
1563 struct radeon_ps *boot_ps;
1564 /* default uvd power state */
1565 struct radeon_ps *uvd_ps;
58bd2a88
AD		 1566 /* vce requirements */
1567 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1568 enum radeon_vce_level vce_level;
da321c8a
AD		 1569 enum radeon_pm_state_type state;
1570 enum radeon_pm_state_type user_state;
1571 u32 platform_caps;
1572 u32 voltage_response_time;
1573 u32 backbias_response_time;
1574 void *priv;
1575 u32 new_active_crtcs;
1576 int new_active_crtc_count;
1577 u32 current_active_crtcs;
1578 int current_active_crtc_count;
3899ca84 1579 bool single_display;
61b7d601
AD		 1580 struct radeon_dpm_dynamic_state dyn_state;
1581 struct radeon_dpm_fan fan;
1582 u32 tdp_limit;
1583 u32 near_tdp_limit;
a9e61410 1584 u32 near_tdp_limit_adjusted;
61b7d601
AD		 1585 u32 sq_ramping_threshold;
1586 u32 cac_leakage;
1587 u16 tdp_od_limit;
1588 u32 tdp_adjustment;
1589 u16 load_line_slope;
1590 bool power_control;
5ca302f7 1591 bool ac_power;
da321c8a
AD		 1592 /* special states active */
1593 bool thermal_active;
8a227555 1594 bool uvd_active;
b62d628b 1595 bool vce_active;
da321c8a
AD		 1596 /* thermal handling */
1597 struct radeon_dpm_thermal thermal;
70d01a5e
AD		 1598 /* forced levels */
1599 enum radeon_dpm_forced_level forced_level;
ce3537d5
AD		 1600 /* track UVD streams */
1601 unsigned sd;
1602 unsigned hd;
da321c8a
AD		 1603};
1604
ce3537d5 1605void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
03afe6f6 1606void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
da321c8a 1607
c93bb85b 1608struct radeon_pm {
c913e23a 1609 struct mutex mutex;
db7fce39
CK		 1610 /* write locked while reprogramming mclk */
1611 struct rw_semaphore mclk_lock;
a48b9b4e
AD		 1612 u32 active_crtcs;
1613 int active_crtc_count;
c913e23a 1614 int req_vblank;
839461d3 1615 bool vblank_sync;
c93bb85b
JG		 1616 fixed20_12 max_bandwidth;
1617 fixed20_12 igp_sideport_mclk;
1618 fixed20_12 igp_system_mclk;
1619 fixed20_12 igp_ht_link_clk;
1620 fixed20_12 igp_ht_link_width;
1621 fixed20_12 k8_bandwidth;
1622 fixed20_12 sideport_bandwidth;
1623 fixed20_12 ht_bandwidth;
1624 fixed20_12 core_bandwidth;
1625 fixed20_12 sclk;
f47299c5 1626 fixed20_12 mclk;
c93bb85b 1627 fixed20_12 needed_bandwidth;
0975b162 1628 struct radeon_power_state *power_state;
56278a8e
AD		 1629 /* number of valid power states */
1630 int num_power_states;
a48b9b4e
AD		 1631 int current_power_state_index;
1632 int current_clock_mode_index;
1633 int requested_power_state_index;
1634 int requested_clock_mode_index;
1635 int default_power_state_index;
1636 u32 current_sclk;
1637 u32 current_mclk;
2feea49a
AD		 1638 u16 current_vddc;
1639 u16 current_vddci;
9ace9f7b
AD		 1640 u32 default_sclk;
1641 u32 default_mclk;
2feea49a
AD		 1642 u16 default_vddc;
1643 u16 default_vddci;
29fb52ca 1644 struct radeon_i2c_chan *i2c_bus;
ce8f5370
AD		 1645 /* selected pm method */
1646 enum radeon_pm_method pm_method;
1647 /* dynpm power management */
1648 struct delayed_work dynpm_idle_work;
1649 enum radeon_dynpm_state dynpm_state;
1650 enum radeon_dynpm_action dynpm_planned_action;
1651 unsigned long dynpm_action_timeout;
1652 bool dynpm_can_upclock;
1653 bool dynpm_can_downclock;
1654 /* profile-based power management */
1655 enum radeon_pm_profile_type profile;
1656 int profile_index;
1657 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
21a8122a
AD		 1658 /* internal thermal controller on rv6xx+ */
1659 enum radeon_int_thermal_type int_thermal_type;
1660 struct device *int_hwmon_dev;
9b92d1ec
AD		 1661 /* fan control parameters */
1662 bool no_fan;
1663 u8 fan_pulses_per_revolution;
1664 u8 fan_min_rpm;
1665 u8 fan_max_rpm;
da321c8a
AD		 1666 /* dpm */
1667 bool dpm_enabled;
49abb266 1668 bool sysfs_initialized;
da321c8a 1669 struct radeon_dpm dpm;
c93bb85b
JG		 1670};
1671
a4c9e2ee
AD		 1672int radeon_pm_get_type_index(struct radeon_device *rdev,
1673 enum radeon_pm_state_type ps_type,
1674 int instance);
f2ba57b5
CK		 1675/*
1676 * UVD
1677 */
8b2cf4f5
AN		 1678#define RADEON_DEFAULT_UVD_HANDLES 10
1679#define RADEON_MAX_UVD_HANDLES 30
1680#define RADEON_UVD_STACK_SIZE (200*1024)
1681#define RADEON_UVD_HEAP_SIZE (256*1024)
1682#define RADEON_UVD_SESSION_SIZE (50*1024)
f2ba57b5
CK		 1683
1684struct radeon_uvd {
7050c6ef 1685 bool fw_header_present;
f2ba57b5
CK		 1686 struct radeon_bo *vcpu_bo;
1687 void *cpu_addr;
1688 uint64_t gpu_addr;
8b2cf4f5 1689 unsigned max_handles;
f2ba57b5
CK		 1690 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1691 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
85a129ca 1692 unsigned img_size[RADEON_MAX_UVD_HANDLES];
55b51c88 1693 struct delayed_work idle_work;
f2ba57b5
CK		 1694};
1695
1696int radeon_uvd_init(struct radeon_device *rdev);
1697void radeon_uvd_fini(struct radeon_device *rdev);
1698int radeon_uvd_suspend(struct radeon_device *rdev);
1699int radeon_uvd_resume(struct radeon_device *rdev);
1700int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1701 uint32_t handle, struct radeon_fence **fence);
1702int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1703 uint32_t handle, struct radeon_fence **fence);
3852752c
CK		 1704void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo,
1705 uint32_t allowed_domains);
f2ba57b5
CK		 1706void radeon_uvd_free_handles(struct radeon_device *rdev,
1707 struct drm_file *filp);
1708int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
55b51c88 1709void radeon_uvd_note_usage(struct radeon_device *rdev);
facd112d
CK		 1710int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1711 unsigned vclk, unsigned dclk,
1712 unsigned vco_min, unsigned vco_max,
1713 unsigned fb_factor, unsigned fb_mask,
1714 unsigned pd_min, unsigned pd_max,
1715 unsigned pd_even,
1716 unsigned *optimal_fb_div,
1717 unsigned *optimal_vclk_div,
1718 unsigned *optimal_dclk_div);
1719int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1720 unsigned cg_upll_func_cntl);
771fe6b9 1721
d93f7937
CK		 1722/*
1723 * VCE
1724 */
1725#define RADEON_MAX_VCE_HANDLES 16
d93f7937
CK		 1726
1727struct radeon_vce {
1728 struct radeon_bo *vcpu_bo;
d93f7937 1729 uint64_t gpu_addr;
98ccc291
CK		 1730 unsigned fw_version;
1731 unsigned fb_version;
d93f7937
CK		 1732 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1733 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
2fc5703a 1734 unsigned img_size[RADEON_MAX_VCE_HANDLES];
03afe6f6 1735 struct delayed_work idle_work;
a918efab 1736 uint32_t keyselect;
d93f7937
CK		 1737};
1738
1739int radeon_vce_init(struct radeon_device *rdev);
1740void radeon_vce_fini(struct radeon_device *rdev);
1741int radeon_vce_suspend(struct radeon_device *rdev);
1742int radeon_vce_resume(struct radeon_device *rdev);
1743int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1744 uint32_t handle, struct radeon_fence **fence);
1745int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1746 uint32_t handle, struct radeon_fence **fence);
1747void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
03afe6f6 1748void radeon_vce_note_usage(struct radeon_device *rdev);
2fc5703a 1749int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
d93f7937
CK		 1750int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1751bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1752 struct radeon_ring *ring,
1753 struct radeon_semaphore *semaphore,
1754 bool emit_wait);
1755void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1756void radeon_vce_fence_emit(struct radeon_device *rdev,
1757 struct radeon_fence *fence);
1758int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1759int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1760
b530602f 1761struct r600_audio_pin {
a92553ab
RM		 1762 int channels;
1763 int rate;
1764 int bits_per_sample;
1765 u8 status_bits;
1766 u8 category_code;
b530602f
AD		 1767 u32 offset;
1768 bool connected;
1769 u32 id;
1770};
1771
1772struct r600_audio {
1773 bool enabled;
1774 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1775 int num_pins;
1a626b68
SG		 1776 struct radeon_audio_funcs *hdmi_funcs;
1777 struct radeon_audio_funcs *dp_funcs;
1778 struct radeon_audio_basic_funcs *funcs;
a92553ab
RM		 1779};
1780
771fe6b9
JG		 1781/*
1782 * Benchmarking
1783 */
638dd7db 1784void radeon_benchmark(struct radeon_device *rdev, int test_number);
771fe6b9
JG		 1785
1786
ecc0b326
MD		 1787/*
1788 * Testing
1789 */
1790void radeon_test_moves(struct radeon_device *rdev);
60a7e396 1791void radeon_test_ring_sync(struct radeon_device *rdev,
e32eb50d
CK		 1792 struct radeon_ring *cpA,
1793 struct radeon_ring *cpB);
60a7e396 1794void radeon_test_syncing(struct radeon_device *rdev);
ecc0b326 1795
341cb9e4
CK		 1796/*
1797 * MMU Notifier
1798 */
5a1aa4b4 1799#if defined(CONFIG_MMU_NOTIFIER)
341cb9e4
CK		 1800int radeon_mn_register(struct radeon_bo *bo, unsigned long addr);
1801void radeon_mn_unregister(struct radeon_bo *bo);
5a1aa4b4
RC		 1802#else
1803static inline int radeon_mn_register(struct radeon_bo *bo, unsigned long addr)
1804{
1805 return -ENODEV;
1806}
1807static inline void radeon_mn_unregister(struct radeon_bo *bo) {}
1808#endif
ecc0b326 1809
771fe6b9
JG		 1810/*
1811 * Debugfs
1812 */
4d8bf9ae
CK		 1813struct radeon_debugfs {
1814 struct drm_info_list *files;
1815 unsigned num_files;
1816};
1817
771fe6b9
JG		 1818int radeon_debugfs_add_files(struct radeon_device *rdev,
1819 struct drm_info_list *files,
1820 unsigned nfiles);
1821int radeon_debugfs_fence_init(struct radeon_device *rdev);
771fe6b9 1822
76a0df85
CK		 1823/*
1824 * ASIC ring specific functions.
1825 */
1826struct radeon_asic_ring {
1827 /* ring read/write ptr handling */
1828 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1829 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1830 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1831
1832 /* validating and patching of IBs */
1833 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1834 int (*cs_parse)(struct radeon_cs_parser *p);
1835
1836 /* command emmit functions */
1837 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1838 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
72a9987e 1839 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1654b817 1840 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
76a0df85 1841 struct radeon_semaphore *semaphore, bool emit_wait);
faffaf62
CK		 1842 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1843 unsigned vm_id, uint64_t pd_addr);
76a0df85
CK		 1844
1845 /* testing functions */
1846 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1847 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1848 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1849
1850 /* deprecated */
1851 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1852};
771fe6b9
JG		 1853
1854/*
1855 * ASIC specific functions.
1856 */
1857struct radeon_asic {
068a117c 1858 int (*init)(struct radeon_device *rdev);
3ce0a23d
JG		 1859 void (*fini)(struct radeon_device *rdev);
1860 int (*resume)(struct radeon_device *rdev);
1861 int (*suspend)(struct radeon_device *rdev);
28d52043 1862 void (*vga_set_state)(struct radeon_device *rdev, bool state);
71fe2899 1863 int (*asic_reset)(struct radeon_device *rdev, bool hard);
124764f1
MD		 1864 /* Flush the HDP cache via MMIO */
1865 void (*mmio_hdp_flush)(struct radeon_device *rdev);
54e88e06
AD		 1866 /* check if 3D engine is idle */
1867 bool (*gui_idle)(struct radeon_device *rdev);
1868 /* wait for mc_idle */
1869 int (*mc_wait_for_idle)(struct radeon_device *rdev);
454d2e2a
AD		 1870 /* get the reference clock */
1871 u32 (*get_xclk)(struct radeon_device *rdev);
d0418894
AD		 1872 /* get the gpu clock counter */
1873 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
4ce4728b
AD		 1874 /* get register for info ioctl */
1875 int (*get_allowed_info_register)(struct radeon_device *rdev, u32 reg, u32 *val);
54e88e06 1876 /* gart */
c5b3b850
AD		 1877 struct {
1878 void (*tlb_flush)(struct radeon_device *rdev);
cb658906 1879 uint64_t (*get_page_entry)(uint64_t addr, uint32_t flags);
7f90fc96 1880 void (*set_page)(struct radeon_device *rdev, unsigned i,
cb658906 1881 uint64_t entry);
c5b3b850 1882 } gart;
05b07147
CK		 1883 struct {
1884 int (*init)(struct radeon_device *rdev);
1885 void (*fini)(struct radeon_device *rdev);
03f62abd
CK		 1886 void (*copy_pages)(struct radeon_device *rdev,
1887 struct radeon_ib *ib,
1888 uint64_t pe, uint64_t src,
1889 unsigned count);
1890 void (*write_pages)(struct radeon_device *rdev,
1891 struct radeon_ib *ib,
1892 uint64_t pe,
1893 uint64_t addr, unsigned count,
1894 uint32_t incr, uint32_t flags);
1895 void (*set_pages)(struct radeon_device *rdev,
1896 struct radeon_ib *ib,
1897 uint64_t pe,
1898 uint64_t addr, unsigned count,
1899 uint32_t incr, uint32_t flags);
1900 void (*pad_ib)(struct radeon_ib *ib);
05b07147 1901 } vm;
54e88e06 1902 /* ring specific callbacks */
d26678da 1903 const struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
54e88e06 1904 /* irqs */
b35ea4ab
AD		 1905 struct {
1906 int (*set)(struct radeon_device *rdev);
1907 int (*process)(struct radeon_device *rdev);
1908 } irq;
54e88e06 1909 /* displays */
c79a49ca
AD		 1910 struct {
1911 /* display watermarks */
1912 void (*bandwidth_update)(struct radeon_device *rdev);
1913 /* get frame count */
1914 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1915 /* wait for vblank */
1916 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
37e9b6a6
AD		 1917 /* set backlight level */
1918 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
6d92f81d
AD		 1919 /* get backlight level */
1920 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
a973bea1
AD		 1921 /* audio callbacks */
1922 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1923 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
c79a49ca 1924 } display;
54e88e06 1925 /* copy functions for bo handling */
27cd7769 1926 struct {
57d20a43
CK		 1927 struct radeon_fence *(*blit)(struct radeon_device *rdev,
1928 uint64_t src_offset,
1929 uint64_t dst_offset,
1930 unsigned num_gpu_pages,
1931 struct reservation_object *resv);
27cd7769 1932 u32 blit_ring_index;
57d20a43
CK		 1933 struct radeon_fence *(*dma)(struct radeon_device *rdev,
1934 uint64_t src_offset,
1935 uint64_t dst_offset,
1936 unsigned num_gpu_pages,
1937 struct reservation_object *resv);
27cd7769
AD		 1938 u32 dma_ring_index;
1939 /* method used for bo copy */
57d20a43
CK		 1940 struct radeon_fence *(*copy)(struct radeon_device *rdev,
1941 uint64_t src_offset,
1942 uint64_t dst_offset,
1943 unsigned num_gpu_pages,
1944 struct reservation_object *resv);
27cd7769
AD		 1945 /* ring used for bo copies */
1946 u32 copy_ring_index;
1947 } copy;
54e88e06 1948 /* surfaces */
9e6f3d02
AD		 1949 struct {
1950 int (*set_reg)(struct radeon_device *rdev, int reg,
1951 uint32_t tiling_flags, uint32_t pitch,
1952 uint32_t offset, uint32_t obj_size);
1953 void (*clear_reg)(struct radeon_device *rdev, int reg);
1954 } surface;
54e88e06 1955 /* hotplug detect */
901ea57d
AD		 1956 struct {
1957 void (*init)(struct radeon_device *rdev);
1958 void (*fini)(struct radeon_device *rdev);
1959 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1960 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1961 } hpd;
da321c8a 1962 /* static power management */
a02fa397
AD		 1963 struct {
1964 void (*misc)(struct radeon_device *rdev);
1965 void (*prepare)(struct radeon_device *rdev);
1966 void (*finish)(struct radeon_device *rdev);
1967 void (*init_profile)(struct radeon_device *rdev);
1968 void (*get_dynpm_state)(struct radeon_device *rdev);
798bcf73
AD		 1969 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1970 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1971 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1972 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1973 int (*get_pcie_lanes)(struct radeon_device *rdev);
1974 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1975 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
73afc70d 1976 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
b59b7333 1977 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
6bd1c385 1978 int (*get_temperature)(struct radeon_device *rdev);
a02fa397 1979 } pm;
da321c8a
AD		 1980 /* dynamic power management */
1981 struct {
1982 int (*init)(struct radeon_device *rdev);
1983 void (*setup_asic)(struct radeon_device *rdev);
1984 int (*enable)(struct radeon_device *rdev);
914a8987 1985 int (*late_enable)(struct radeon_device *rdev);
da321c8a 1986 void (*disable)(struct radeon_device *rdev);
84dd1928 1987 int (*pre_set_power_state)(struct radeon_device *rdev);
da321c8a 1988 int (*set_power_state)(struct radeon_device *rdev);
84dd1928 1989 void (*post_set_power_state)(struct radeon_device *rdev);
da321c8a
AD		 1990 void (*display_configuration_changed)(struct radeon_device *rdev);
1991 void (*fini)(struct radeon_device *rdev);
1992 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1993 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1994 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1316b792 1995 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
70d01a5e 1996 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
48783069 1997 bool (*vblank_too_short)(struct radeon_device *rdev);
9e9d9762 1998 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1c71bda0 1999 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
a35a4b2b
OC		 2000 void (*fan_ctrl_set_mode)(struct radeon_device *rdev, u32 mode);
2001 u32 (*fan_ctrl_get_mode)(struct radeon_device *rdev);
2002 int (*set_fan_speed_percent)(struct radeon_device *rdev, u32 speed);
2003 int (*get_fan_speed_percent)(struct radeon_device *rdev, u32 *speed);
d7dbce09
AD		 2004 u32 (*get_current_sclk)(struct radeon_device *rdev);
2005 u32 (*get_current_mclk)(struct radeon_device *rdev);
da321c8a 2006 } dpm;
6f34be50 2007 /* pageflipping */
0f9e006c 2008 struct {
c63dd758 2009 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base, bool async);
157fa14d 2010 bool (*page_flip_pending)(struct radeon_device *rdev, int crtc);
0f9e006c 2011 } pflip;
771fe6b9
JG		 2012};
2013
21f9a437
JG		 2014/*
2015 * Asic structures
2016 */
551ebd83 2017struct r100_asic {
225758d8
JG		 2018 const unsigned *reg_safe_bm;
2019 unsigned reg_safe_bm_size;
2020 u32 hdp_cntl;
551ebd83
DA		 2021};
2022
21f9a437 2023struct r300_asic {
225758d8
JG		 2024 const unsigned *reg_safe_bm;
2025 unsigned reg_safe_bm_size;
2026 u32 resync_scratch;
2027 u32 hdp_cntl;
21f9a437
JG		 2028};
2029
2030struct r600_asic {
225758d8
JG		 2031 unsigned max_pipes;
2032 unsigned max_tile_pipes;
2033 unsigned max_simds;
2034 unsigned max_backends;
2035 unsigned max_gprs;
2036 unsigned max_threads;
2037 unsigned max_stack_entries;
2038 unsigned max_hw_contexts;
2039 unsigned max_gs_threads;
2040 unsigned sx_max_export_size;
2041 unsigned sx_max_export_pos_size;
2042 unsigned sx_max_export_smx_size;
2043 unsigned sq_num_cf_insts;
2044 unsigned tiling_nbanks;
2045 unsigned tiling_npipes;
2046 unsigned tiling_group_size;
e7aeeba6 2047 unsigned tile_config;
e55b9422 2048 unsigned backend_map;
65fcf668 2049 unsigned active_simds;
21f9a437
JG		 2050};
2051
2052struct rv770_asic {
225758d8
JG		 2053 unsigned max_pipes;
2054 unsigned max_tile_pipes;
2055 unsigned max_simds;
2056 unsigned max_backends;
2057 unsigned max_gprs;
2058 unsigned max_threads;
2059 unsigned max_stack_entries;
2060 unsigned max_hw_contexts;
2061 unsigned max_gs_threads;
2062 unsigned sx_max_export_size;
2063 unsigned sx_max_export_pos_size;
2064 unsigned sx_max_export_smx_size;
2065 unsigned sq_num_cf_insts;
2066 unsigned sx_num_of_sets;
2067 unsigned sc_prim_fifo_size;
2068 unsigned sc_hiz_tile_fifo_size;
2069 unsigned sc_earlyz_tile_fifo_fize;
2070 unsigned tiling_nbanks;
2071 unsigned tiling_npipes;
2072 unsigned tiling_group_size;
e7aeeba6 2073 unsigned tile_config;
e55b9422 2074 unsigned backend_map;
65fcf668 2075 unsigned active_simds;
21f9a437
JG		 2076};
2077
32fcdbf4
AD		 2078struct evergreen_asic {
2079 unsigned num_ses;
2080 unsigned max_pipes;
2081 unsigned max_tile_pipes;
2082 unsigned max_simds;
2083 unsigned max_backends;
2084 unsigned max_gprs;
2085 unsigned max_threads;
2086 unsigned max_stack_entries;
2087 unsigned max_hw_contexts;
2088 unsigned max_gs_threads;
2089 unsigned sx_max_export_size;
2090 unsigned sx_max_export_pos_size;
2091 unsigned sx_max_export_smx_size;
2092 unsigned sq_num_cf_insts;
2093 unsigned sx_num_of_sets;
2094 unsigned sc_prim_fifo_size;
2095 unsigned sc_hiz_tile_fifo_size;
2096 unsigned sc_earlyz_tile_fifo_size;
2097 unsigned tiling_nbanks;
2098 unsigned tiling_npipes;
2099 unsigned tiling_group_size;
e7aeeba6 2100 unsigned tile_config;
e55b9422 2101 unsigned backend_map;
65fcf668 2102 unsigned active_simds;
32fcdbf4
AD		 2103};
2104
fecf1d07
AD		 2105struct cayman_asic {
2106 unsigned max_shader_engines;
2107 unsigned max_pipes_per_simd;
2108 unsigned max_tile_pipes;
2109 unsigned max_simds_per_se;
2110 unsigned max_backends_per_se;
2111 unsigned max_texture_channel_caches;
2112 unsigned max_gprs;
2113 unsigned max_threads;
2114 unsigned max_gs_threads;
2115 unsigned max_stack_entries;
2116 unsigned sx_num_of_sets;
2117 unsigned sx_max_export_size;
2118 unsigned sx_max_export_pos_size;
2119 unsigned sx_max_export_smx_size;
2120 unsigned max_hw_contexts;
2121 unsigned sq_num_cf_insts;
2122 unsigned sc_prim_fifo_size;
2123 unsigned sc_hiz_tile_fifo_size;
2124 unsigned sc_earlyz_tile_fifo_size;
2125
2126 unsigned num_shader_engines;
2127 unsigned num_shader_pipes_per_simd;
2128 unsigned num_tile_pipes;
2129 unsigned num_simds_per_se;
2130 unsigned num_backends_per_se;
2131 unsigned backend_disable_mask_per_asic;
2132 unsigned backend_map;
2133 unsigned num_texture_channel_caches;
2134 unsigned mem_max_burst_length_bytes;
2135 unsigned mem_row_size_in_kb;
2136 unsigned shader_engine_tile_size;
2137 unsigned num_gpus;
2138 unsigned multi_gpu_tile_size;
2139
2140 unsigned tile_config;
65fcf668 2141 unsigned active_simds;
fecf1d07
AD		 2142};
2143
0a96d72b
AD		 2144struct si_asic {
2145 unsigned max_shader_engines;
0a96d72b 2146 unsigned max_tile_pipes;
1a8ca750
AD		 2147 unsigned max_cu_per_sh;
2148 unsigned max_sh_per_se;
0a96d72b
AD		 2149 unsigned max_backends_per_se;
2150 unsigned max_texture_channel_caches;
2151 unsigned max_gprs;
2152 unsigned max_gs_threads;
2153 unsigned max_hw_contexts;
2154 unsigned sc_prim_fifo_size_frontend;
2155 unsigned sc_prim_fifo_size_backend;
2156 unsigned sc_hiz_tile_fifo_size;
2157 unsigned sc_earlyz_tile_fifo_size;
2158
0a96d72b 2159 unsigned num_tile_pipes;
439a1cff 2160 unsigned backend_enable_mask;
0a96d72b
AD		 2161 unsigned backend_disable_mask_per_asic;
2162 unsigned backend_map;
2163 unsigned num_texture_channel_caches;
2164 unsigned mem_max_burst_length_bytes;
2165 unsigned mem_row_size_in_kb;
2166 unsigned shader_engine_tile_size;
2167 unsigned num_gpus;
2168 unsigned multi_gpu_tile_size;
2169
2170 unsigned tile_config;
64d7b8be 2171 uint32_t tile_mode_array[32];
65fcf668 2172 uint32_t active_cus;
0a96d72b
AD		 2173};
2174
8cc1a532
AD		 2175struct cik_asic {
2176 unsigned max_shader_engines;
2177 unsigned max_tile_pipes;
2178 unsigned max_cu_per_sh;
2179 unsigned max_sh_per_se;
2180 unsigned max_backends_per_se;
2181 unsigned max_texture_channel_caches;
2182 unsigned max_gprs;
2183 unsigned max_gs_threads;
2184 unsigned max_hw_contexts;
2185 unsigned sc_prim_fifo_size_frontend;
2186 unsigned sc_prim_fifo_size_backend;
2187 unsigned sc_hiz_tile_fifo_size;
2188 unsigned sc_earlyz_tile_fifo_size;
2189
2190 unsigned num_tile_pipes;
439a1cff 2191 unsigned backend_enable_mask;
8cc1a532
AD		 2192 unsigned backend_disable_mask_per_asic;
2193 unsigned backend_map;
2194 unsigned num_texture_channel_caches;
2195 unsigned mem_max_burst_length_bytes;
2196 unsigned mem_row_size_in_kb;
2197 unsigned shader_engine_tile_size;
2198 unsigned num_gpus;
2199 unsigned multi_gpu_tile_size;
2200
2201 unsigned tile_config;
39aee490 2202 uint32_t tile_mode_array[32];
32f79a8a 2203 uint32_t macrotile_mode_array[16];
65fcf668 2204 uint32_t active_cus;
8cc1a532
AD		 2205};
2206
068a117c
JG		 2207union radeon_asic_config {
2208 struct r300_asic r300;
551ebd83 2209 struct r100_asic r100;
3ce0a23d
JG		 2210 struct r600_asic r600;
2211 struct rv770_asic rv770;
32fcdbf4 2212 struct evergreen_asic evergreen;
fecf1d07 2213 struct cayman_asic cayman;
0a96d72b 2214 struct si_asic si;
8cc1a532 2215 struct cik_asic cik;
068a117c
JG		 2216};
2217
0a10c851
DV		 2218/*
2219 * asic initizalization from radeon_asic.c
2220 */
2221void radeon_agp_disable(struct radeon_device *rdev);
2222int radeon_asic_init(struct radeon_device *rdev);
2223
771fe6b9
JG		 2224
2225/*
2226 * IOCTL.
2227 */
2228int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2229 struct drm_file *filp);
2230int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2231 struct drm_file *filp);
f72a113a
CK		 2232int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
2233 struct drm_file *filp);
771fe6b9
JG		 2234int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2235 struct drm_file *file_priv);
2236int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2237 struct drm_file *file_priv);
2238int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2239 struct drm_file *file_priv);
2240int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2241 struct drm_file *file_priv);
2242int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2243 struct drm_file *filp);
2244int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2245 struct drm_file *filp);
2246int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2247 struct drm_file *filp);
2248int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2249 struct drm_file *filp);
721604a1
JG		 2250int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2251 struct drm_file *filp);
bda72d58
MO		 2252int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2253 struct drm_file *filp);
771fe6b9 2254int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
e024e110
DA		 2255int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2256 struct drm_file *filp);
2257int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2258 struct drm_file *filp);
771fe6b9 2259
16cdf04d
AD		 2260/* VRAM scratch page for HDP bug, default vram page */
2261struct r600_vram_scratch {
87cbf8f2
AD		 2262 struct radeon_bo *robj;
2263 volatile uint32_t *ptr;
16cdf04d 2264 u64 gpu_addr;
87cbf8f2 2265};
771fe6b9 2266
fd64ca8a
LT		 2267/*
2268 * ACPI
2269 */
2270struct radeon_atif_notification_cfg {
2271 bool enabled;
2272 int command_code;
2273};
2274
2275struct radeon_atif_notifications {
2276 bool display_switch;
2277 bool expansion_mode_change;
2278 bool thermal_state;
2279 bool forced_power_state;
2280 bool system_power_state;
2281 bool display_conf_change;
2282 bool px_gfx_switch;
2283 bool brightness_change;
2284 bool dgpu_display_event;
2285};
2286
2287struct radeon_atif_functions {
2288 bool system_params;
2289 bool sbios_requests;
2290 bool select_active_disp;
2291 bool lid_state;
2292 bool get_tv_standard;
2293 bool set_tv_standard;
2294 bool get_panel_expansion_mode;
2295 bool set_panel_expansion_mode;
2296 bool temperature_change;
2297 bool graphics_device_types;
2298};
2299
2300struct radeon_atif {
2301 struct radeon_atif_notifications notifications;
2302 struct radeon_atif_functions functions;
2303 struct radeon_atif_notification_cfg notification_cfg;
37e9b6a6 2304 struct radeon_encoder *encoder_for_bl;
fd64ca8a 2305};
7a1619b9 2306
e3a15920
AD		 2307struct radeon_atcs_functions {
2308 bool get_ext_state;
2309 bool pcie_perf_req;
2310 bool pcie_dev_rdy;
2311 bool pcie_bus_width;
2312};
2313
2314struct radeon_atcs {
2315 struct radeon_atcs_functions functions;
2316};
2317
771fe6b9
JG		 2318/*
2319 * Core structure, functions and helpers.
2320 */
2321typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2322typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2323
2324struct radeon_device {
9f022ddf 2325 struct device *dev;
771fe6b9
JG		 2326 struct drm_device *ddev;
2327 struct pci_dev *pdev;
dee53e7f 2328 struct rw_semaphore exclusive_lock;
771fe6b9 2329 /* ASIC */
068a117c 2330 union radeon_asic_config config;
771fe6b9
JG		 2331 enum radeon_family family;
2332 unsigned long flags;
2333 int usec_timeout;
2334 enum radeon_pll_errata pll_errata;
2335 int num_gb_pipes;
f779b3e5 2336 int num_z_pipes;
771fe6b9
JG		 2337 int disp_priority;
2338 /* BIOS */
2339 uint8_t *bios;
2340 bool is_atom_bios;
2341 uint16_t bios_header_start;
4c788679 2342 struct radeon_bo *stollen_vga_memory;
771fe6b9 2343 /* Register mmio */
4c9bc75c
DA		 2344 resource_size_t rmmio_base;
2345 resource_size_t rmmio_size;
2c385151
DV		 2346 /* protects concurrent MM_INDEX/DATA based register access */
2347 spinlock_t mmio_idx_lock;
fe78118c
AD		 2348 /* protects concurrent SMC based register access */
2349 spinlock_t smc_idx_lock;
0a5b7b0b
AD		 2350 /* protects concurrent PLL register access */
2351 spinlock_t pll_idx_lock;
2352 /* protects concurrent MC register access */
2353 spinlock_t mc_idx_lock;
2354 /* protects concurrent PCIE register access */
2355 spinlock_t pcie_idx_lock;
2356 /* protects concurrent PCIE_PORT register access */
2357 spinlock_t pciep_idx_lock;
2358 /* protects concurrent PIF register access */
2359 spinlock_t pif_idx_lock;
2360 /* protects concurrent CG register access */
2361 spinlock_t cg_idx_lock;
2362 /* protects concurrent UVD register access */
2363 spinlock_t uvd_idx_lock;
2364 /* protects concurrent RCU register access */
2365 spinlock_t rcu_idx_lock;
2366 /* protects concurrent DIDT register access */
2367 spinlock_t didt_idx_lock;
2368 /* protects concurrent ENDPOINT (audio) register access */
2369 spinlock_t end_idx_lock;
a0533fbf 2370 void __iomem *rmmio;
771fe6b9
JG		 2371 radeon_rreg_t mc_rreg;
2372 radeon_wreg_t mc_wreg;
2373 radeon_rreg_t pll_rreg;
2374 radeon_wreg_t pll_wreg;
de1b2898 2375 uint32_t pcie_reg_mask;
771fe6b9
JG		 2376 radeon_rreg_t pciep_rreg;
2377 radeon_wreg_t pciep_wreg;
351a52a2
AD		 2378 /* io port */
2379 void __iomem *rio_mem;
2380 resource_size_t rio_mem_size;
771fe6b9
JG		 2381 struct radeon_clock clock;
2382 struct radeon_mc mc;
2383 struct radeon_gart gart;
2384 struct radeon_mode_info mode_info;
2385 struct radeon_scratch scratch;
75efdee1 2386 struct radeon_doorbell doorbell;
771fe6b9 2387 struct radeon_mman mman;
7465280c 2388 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
0085c950 2389 wait_queue_head_t fence_queue;
76bf0db5 2390 u64 fence_context;
d6999bc7 2391 struct mutex ring_lock;
e32eb50d 2392 struct radeon_ring ring[RADEON_NUM_RINGS];
c507f7ef
JG		 2393 bool ib_pool_ready;
2394 struct radeon_sa_manager ring_tmp_bo;
771fe6b9
JG		 2395 struct radeon_irq irq;
2396 struct radeon_asic *asic;
2397 struct radeon_gem gem;
c93bb85b 2398 struct radeon_pm pm;
f2ba57b5 2399 struct radeon_uvd uvd;
d93f7937 2400 struct radeon_vce vce;
f657c2a7 2401 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
771fe6b9 2402 struct radeon_wb wb;
3ce0a23d 2403 struct radeon_dummy_page dummy_page;
771fe6b9 2404 bool shutdown;
ad49f501 2405 bool need_dma32;
733289c2 2406 bool accel_working;
a0a53aa8 2407 bool fastfb_working; /* IGP feature*/
9bb39ff4 2408 bool needs_reset, in_reset;
e024e110 2409 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
3ce0a23d
JG		 2410 const struct firmware *me_fw; /* all family ME firmware */
2411 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
d8f60cfc 2412 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
0af62b01 2413 const struct firmware *mc_fw; /* NI MC firmware */
0f0de06c 2414 const struct firmware *ce_fw; /* SI CE firmware */
02c81327 2415 const struct firmware *mec_fw; /* CIK MEC firmware */
f2c6b0f4 2416 const struct firmware *mec2_fw; /* KV MEC2 firmware */
21a93e13 2417 const struct firmware *sdma_fw; /* CIK SDMA firmware */
66229b20 2418 const struct firmware *smc_fw; /* SMC firmware */
4ad9c1c7 2419 const struct firmware *uvd_fw; /* UVD firmware */
d93f7937 2420 const struct firmware *vce_fw; /* VCE firmware */
629bd33c 2421 bool new_fw;
16cdf04d 2422 struct r600_vram_scratch vram_scratch;
3e5cb98d 2423 int msi_enabled; /* msi enabled */
d8f60cfc 2424 struct r600_ih ih; /* r6/700 interrupt ring */
2948f5e6 2425 struct radeon_rlc rlc;
963e81f9 2426 struct radeon_mec mec;
cb5d4166 2427 struct delayed_work hotplug_work;
de6284aa 2428 struct work_struct dp_work;
f122c610 2429 struct work_struct audio_work;
18917b60 2430 int num_crtc; /* number of crtcs */
40bacf16 2431 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
948bee3f 2432 bool has_uvd;
e3ebfcfa 2433 bool has_vce;
b530602f 2434 struct r600_audio audio; /* audio stuff */
ce8f5370 2435 struct notifier_block acpi_nb;
9eba4a93 2436 /* only one userspace can use Hyperz features or CMASK at a time */
ab9e1f59 2437 struct drm_file *hyperz_filp;
9eba4a93 2438 struct drm_file *cmask_filp;
f376b94f
AD		 2439 /* i2c buses */
2440 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
4d8bf9ae
CK		 2441 /* debugfs */
2442 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2443 unsigned debugfs_count;
721604a1
JG		 2444 /* virtual memory */
2445 struct radeon_vm_manager vm_manager;
6759a0a7 2446 struct mutex gpu_clock_mutex;
67e8e3f9
MO		 2447 /* memory stats */
2448 atomic64_t vram_usage;
2449 atomic64_t gtt_usage;
2450 atomic64_t num_bytes_moved;
72b9076b 2451 atomic_t gpu_reset_counter;
fd64ca8a
LT		 2452 /* ACPI interface */
2453 struct radeon_atif atif;
e3a15920 2454 struct radeon_atcs atcs;
f61d5b46
AD		 2455 /* srbm instance registers */
2456 struct mutex srbm_mutex;
1c0a4625
OG		 2457 /* GRBM index mutex. Protects concurrents access to GRBM index */
2458 struct mutex grbm_idx_mutex;
64d8a728
AD		 2459 /* clock, powergating flags */
2460 u32 cg_flags;
2461 u32 pg_flags;
10ebc0bc
DA		 2462
2463 struct dev_pm_domain vga_pm_domain;
2464 bool have_disp_power_ref;
4807c5a8 2465 u32 px_quirk_flags;
71ecc97e
AD		 2466
2467 /* tracking pinned memory */
2468 u64 vram_pin_size;
2469 u64 gart_pin_size;
341cb9e4 2470
e28740ec
OG		 2471 /* amdkfd interface */
2472 struct kfd_dev *kfd;
e28740ec 2473
341cb9e4
CK		 2474 struct mutex mn_lock;
2475 DECLARE_HASHTABLE(mn_hash, 7);
771fe6b9
JG		 2476};
2477
90c4cde9 2478bool radeon_is_px(struct drm_device *dev);
771fe6b9
JG		 2479int radeon_device_init(struct radeon_device *rdev,
2480 struct drm_device *ddev,
2481 struct pci_dev *pdev,
2482 uint32_t flags);
2483void radeon_device_fini(struct radeon_device *rdev);
2484int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2485
59bc1d89
LK		 2486#define RADEON_MIN_MMIO_SIZE 0x10000
2487
9e5acbc2
DV		 2488uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg);
2489void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v);
59bc1d89
LK		 2490static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2491 bool always_indirect)
2492{
2493 /* The mmio size is 64kb at minimum. Allows the if to be optimized out. */
2494 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2495 return readl(((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2496 else
2497 return r100_mm_rreg_slow(rdev, reg);
59bc1d89 2498}
59bc1d89
LK		 2499static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2500 bool always_indirect)
2501{
2502 if ((reg < rdev->rmmio_size || reg < RADEON_MIN_MMIO_SIZE) && !always_indirect)
2503 writel(v, ((void __iomem *)rdev->rmmio) + reg);
9e5acbc2
DV		 2504 else
2505 r100_mm_wreg_slow(rdev, reg, v);
59bc1d89
LK		 2506}
2507
6fcbef7a
AK		 2508u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2509void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
351a52a2 2510
d5754ab8
AL		 2511u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2512void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
75efdee1 2513
4c788679
JG		 2514/*
2515 * Cast helper
2516 */
954605ca
ML		 2517extern const struct fence_ops radeon_fence_ops;
2518
2519static inline struct radeon_fence *to_radeon_fence(struct fence *f)
2520{
2521 struct radeon_fence *__f = container_of(f, struct radeon_fence, base);
2522
2523 if (__f->base.ops == &radeon_fence_ops)
2524 return __f;
2525
2526 return NULL;
2527}
771fe6b9
JG		 2528
2529/*
2530 * Registers read & write functions.
2531 */
a0533fbf
BH		 2532#define RREG8(reg) readb((rdev->rmmio) + (reg))
2533#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2534#define RREG16(reg) readw((rdev->rmmio) + (reg))
2535#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2ef9bdfe
DV		 2536#define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2537#define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2538#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2539#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2540#define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
771fe6b9
JG		 2541#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2542#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2543#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2544#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2545#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2546#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
de1b2898
DA		 2547#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2548#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
492d2b61
AD		 2549#define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2550#define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1d5d0c34
AD		 2551#define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2552#define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
ff82bbc4
AD		 2553#define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2554#define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
46f9564a
AD		 2555#define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2556#define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
792edd69
AD		 2557#define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2558#define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2559#define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2560#define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
93656cdd
AD		 2561#define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2562#define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
1d58234d
AD		 2563#define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2564#define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
771fe6b9
JG		 2565#define WREG32_P(reg, val, mask) \
2566 do { \
2567 uint32_t tmp_ = RREG32(reg); \
2568 tmp_ &= (mask); \
2569 tmp_ |= ((val) & ~(mask)); \
2570 WREG32(reg, tmp_); \
2571 } while (0)
d5169fc4 2572#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
d43a93c8 2573#define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
771fe6b9
JG		 2574#define WREG32_PLL_P(reg, val, mask) \
2575 do { \
2576 uint32_t tmp_ = RREG32_PLL(reg); \
2577 tmp_ &= (mask); \
2578 tmp_ |= ((val) & ~(mask)); \
2579 WREG32_PLL(reg, tmp_); \
2580 } while (0)
b7af630c
CK		 2581#define WREG32_SMC_P(reg, val, mask) \
2582 do { \
2583 uint32_t tmp_ = RREG32_SMC(reg); \
2584 tmp_ &= (mask); \
2585 tmp_ |= ((val) & ~(mask)); \
2586 WREG32_SMC(reg, tmp_); \
2587 } while (0)
2ef9bdfe 2588#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
351a52a2
AD		 2589#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2590#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
771fe6b9 2591
d5754ab8
AL		 2592#define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2593#define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
75efdee1 2594
de1b2898 2595/*
9e5acbc2
DV		 2596 * Indirect registers accessors.
2597 * They used to be inlined, but this increases code size by ~65 kbytes.
2598 * Since each performs a pair of MMIO ops
2599 * within a spin_lock_irqsave/spin_unlock_irqrestore region,
2600 * the cost of call+ret is almost negligible. MMIO and locking
2601 * costs several dozens of cycles each at best, call+ret is ~5 cycles.
de1b2898 2602 */
9e5acbc2
DV		 2603uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
2604void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
2605u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg);
2606void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2607u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg);
2608void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2609u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg);
2610void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2611u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg);
2612void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2613u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg);
2614void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2615u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg);
2616void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2617u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg);
2618void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1d58234d 2619
771fe6b9
JG		 2620void r100_pll_errata_after_index(struct radeon_device *rdev);
2621
2622
2623/*
2624 * ASICs helpers.
2625 */
b995e433
DA		 2626#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2627 (rdev->pdev->device == 0x5969))
771fe6b9
JG		 2628#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2629 (rdev->family == CHIP_RV200) || \
2630 (rdev->family == CHIP_RS100) || \
2631 (rdev->family == CHIP_RS200) || \
2632 (rdev->family == CHIP_RV250) || \
2633 (rdev->family == CHIP_RV280) || \
2634 (rdev->family == CHIP_RS300))
2635#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2636 (rdev->family == CHIP_RV350) || \
2637 (rdev->family == CHIP_R350) || \
2638 (rdev->family == CHIP_RV380) || \
2639 (rdev->family == CHIP_R420) || \
2640 (rdev->family == CHIP_R423) || \
2641 (rdev->family == CHIP_RV410) || \
2642 (rdev->family == CHIP_RS400) || \
2643 (rdev->family == CHIP_RS480))
3313e3d4
AD		 2644#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2645 (rdev->ddev->pdev->device == 0x9443) || \
2646 (rdev->ddev->pdev->device == 0x944B) || \
2647 (rdev->ddev->pdev->device == 0x9506) || \
2648 (rdev->ddev->pdev->device == 0x9509) || \
2649 (rdev->ddev->pdev->device == 0x950F) || \
2650 (rdev->ddev->pdev->device == 0x689C) || \
2651 (rdev->ddev->pdev->device == 0x689D))
771fe6b9 2652#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
99999aaa
AD		 2653#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2654 (rdev->family == CHIP_RS690) || \
2655 (rdev->family == CHIP_RS740) || \
2656 (rdev->family >= CHIP_R600))
771fe6b9
JG		 2657#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2658#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
bcc1c2a1 2659#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
633b9164
AD		 2660#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2661 (rdev->flags & RADEON_IS_IGP))
1fe18305 2662#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
8848f759
AD		 2663#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2664#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2665 (rdev->flags & RADEON_IS_IGP))
624d3524 2666#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
b5d9d726 2667#define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
e282917c 2668#define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
be0949f5
AD		 2669#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2670#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
89d2618d
AD		 2671#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2672 (rdev->family == CHIP_MULLINS))
771fe6b9 2673
dc50ba7f
AD		 2674#define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2675 (rdev->ddev->pdev->device == 0x6850) || \
2676 (rdev->ddev->pdev->device == 0x6858) || \
2677 (rdev->ddev->pdev->device == 0x6859) || \
2678 (rdev->ddev->pdev->device == 0x6840) || \
2679 (rdev->ddev->pdev->device == 0x6841) || \
2680 (rdev->ddev->pdev->device == 0x6842) || \
2681 (rdev->ddev->pdev->device == 0x6843))
2682
771fe6b9
JG		 2683/*
2684 * BIOS helpers.
2685 */
2686#define RBIOS8(i) (rdev->bios[i])
2687#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2688#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2689
2690int radeon_combios_init(struct radeon_device *rdev);
2691void radeon_combios_fini(struct radeon_device *rdev);
2692int radeon_atombios_init(struct radeon_device *rdev);
2693void radeon_atombios_fini(struct radeon_device *rdev);
2694
2695
2696/*
2697 * RING helpers.
2698 */
edf0ac7c
DH		 2699
2700/**
2701 * radeon_ring_write - write a value to the ring
2702 *
2703 * @ring: radeon_ring structure holding ring information
2704 * @v: dword (dw) value to write
2705 *
2706 * Write a value to the requested ring buffer (all asics).
2707 */
e32eb50d 2708static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
771fe6b9 2709{
edf0ac7c
DH		 2710 if (ring->count_dw <= 0)
2711 DRM_ERROR("radeon: writing more dwords to the ring than expected!\n");
2712
e32eb50d
CK		 2713 ring->ring[ring->wptr++] = v;
2714 ring->wptr &= ring->ptr_mask;
2715 ring->count_dw--;
2716 ring->ring_free_dw--;
771fe6b9 2717}
771fe6b9
JG		 2718
2719/*
2720 * ASICs macro.
2721 */
068a117c 2722#define radeon_init(rdev) (rdev)->asic->init((rdev))
3ce0a23d
JG		 2723#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2724#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2725#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
76a0df85 2726#define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
28d52043 2727#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
71fe2899 2728#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev), false)
c5b3b850 2729#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
cb658906
MD		 2730#define radeon_gart_get_page_entry(a, f) (rdev)->asic->gart.get_page_entry((a), (f))
2731#define radeon_gart_set_page(rdev, i, e) (rdev)->asic->gart.set_page((rdev), (i), (e))
05b07147
CK		 2732#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2733#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
03f62abd
CK		 2734#define radeon_asic_vm_copy_pages(rdev, ib, pe, src, count) ((rdev)->asic->vm.copy_pages((rdev), (ib), (pe), (src), (count)))
2735#define radeon_asic_vm_write_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.write_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2736#define radeon_asic_vm_set_pages(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_pages((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2737#define radeon_asic_vm_pad_ib(rdev, ib) ((rdev)->asic->vm.pad_ib((ib)))
76a0df85
CK		 2738#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2739#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2740#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2741#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2742#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2743#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
faffaf62 2744#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
76a0df85
CK		 2745#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2746#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2747#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
b35ea4ab
AD		 2748#define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2749#define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
c79a49ca 2750#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
37e9b6a6 2751#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
6d92f81d 2752#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
a973bea1
AD		 2753#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2754#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
76a0df85
CK		 2755#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2756#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
57d20a43
CK		 2757#define radeon_copy_blit(rdev, s, d, np, resv) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (resv))
2758#define radeon_copy_dma(rdev, s, d, np, resv) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (resv))
2759#define radeon_copy(rdev, s, d, np, resv) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (resv))
27cd7769
AD		 2760#define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2761#define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2762#define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
798bcf73
AD		 2763#define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2764#define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2765#define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2766#define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2767#define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2768#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2769#define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
73afc70d 2770#define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
b59b7333 2771#define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
6bd1c385 2772#define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
9e6f3d02
AD		 2773#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2774#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
c79a49ca 2775#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
901ea57d
AD		 2776#define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2777#define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2778#define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2779#define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
def9ba9c 2780#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
a02fa397
AD		 2781#define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2782#define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2783#define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2784#define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2785#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
c63dd758 2786#define radeon_page_flip(rdev, crtc, base, async) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base), (async))
157fa14d 2787#define radeon_page_flip_pending(rdev, crtc) (rdev)->asic->pflip.page_flip_pending((rdev), (crtc))
69b62ad8
AD		 2788#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2789#define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
454d2e2a 2790#define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
d0418894 2791#define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
4ce4728b 2792#define radeon_get_allowed_info_register(rdev, r, v) (rdev)->asic->get_allowed_info_register((rdev), (r), (v))
da321c8a
AD		 2793#define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2794#define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2795#define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
914a8987 2796#define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
da321c8a 2797#define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
84dd1928 2798#define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
da321c8a 2799#define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
84dd1928 2800#define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
da321c8a
AD		 2801#define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2802#define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2803#define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2804#define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2805#define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
1316b792 2806#define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
70d01a5e 2807#define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
48783069 2808#define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
9e9d9762 2809#define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
1c71bda0 2810#define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
d7dbce09
AD		 2811#define radeon_dpm_get_current_sclk(rdev) rdev->asic->dpm.get_current_sclk((rdev))
2812#define radeon_dpm_get_current_mclk(rdev) rdev->asic->dpm.get_current_mclk((rdev))
771fe6b9 2813
6cf8a3f5 2814/* Common functions */
700a0cc0 2815/* AGP */
90aca4d2 2816extern int radeon_gpu_reset(struct radeon_device *rdev);
1a0041b8 2817extern void radeon_pci_config_reset(struct radeon_device *rdev);
410a3418 2818extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
700a0cc0 2819extern void radeon_agp_disable(struct radeon_device *rdev);
21f9a437
JG		 2820extern int radeon_modeset_init(struct radeon_device *rdev);
2821extern void radeon_modeset_fini(struct radeon_device *rdev);
9f022ddf 2822extern bool radeon_card_posted(struct radeon_device *rdev);
f47299c5 2823extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
f46c0120 2824extern void radeon_update_display_priority(struct radeon_device *rdev);
72542d77 2825extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
21f9a437 2826extern void radeon_scratch_init(struct radeon_device *rdev);
724c80e1
AD		 2827extern void radeon_wb_fini(struct radeon_device *rdev);
2828extern int radeon_wb_init(struct radeon_device *rdev);
2829extern void radeon_wb_disable(struct radeon_device *rdev);
21f9a437
JG		 2830extern void radeon_surface_init(struct radeon_device *rdev);
2831extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
ca6ffc64 2832extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
d39c3b89 2833extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
312ea8da 2834extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
d03d8589 2835extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
f72a113a
CK		 2836extern int radeon_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2837 uint32_t flags);
2838extern bool radeon_ttm_tt_has_userptr(struct ttm_tt *ttm);
2839extern bool radeon_ttm_tt_is_readonly(struct ttm_tt *ttm);
d594e46a
JG		 2840extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2841extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
10ebc0bc 2842extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
274ad65c
JG		 2843extern int radeon_suspend_kms(struct drm_device *dev, bool suspend,
2844 bool fbcon, bool freeze);
53595338 2845extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2e1b65f9
AD		 2846extern void radeon_program_register_sequence(struct radeon_device *rdev,
2847 const u32 *registers,
2848 const u32 array_size);
6cf8a3f5 2849
721604a1
JG		 2850/*
2851 * vm
2852 */
2853int radeon_vm_manager_init(struct radeon_device *rdev);
2854void radeon_vm_manager_fini(struct radeon_device *rdev);
6d2f2944 2855int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
721604a1 2856void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
1d0c0942 2857struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
df0af440
CK		 2858 struct radeon_vm *vm,
2859 struct list_head *head);
ee60e29f
CK		 2860struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2861 struct radeon_vm *vm, int ring);
fa688343
CK		 2862void radeon_vm_flush(struct radeon_device *rdev,
2863 struct radeon_vm *vm,
ad1a58a4 2864 int ring, struct radeon_fence *fence);
ee60e29f
CK		 2865void radeon_vm_fence(struct radeon_device *rdev,
2866 struct radeon_vm *vm,
2867 struct radeon_fence *fence);
dce34bfd 2868uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
6d2f2944
CK		 2869int radeon_vm_update_page_directory(struct radeon_device *rdev,
2870 struct radeon_vm *vm);
036bf46a
CK		 2871int radeon_vm_clear_freed(struct radeon_device *rdev,
2872 struct radeon_vm *vm);
e31ad969
CK		 2873int radeon_vm_clear_invalids(struct radeon_device *rdev,
2874 struct radeon_vm *vm);
9c57a6bd 2875int radeon_vm_bo_update(struct radeon_device *rdev,
036bf46a 2876 struct radeon_bo_va *bo_va,
9c57a6bd 2877 struct ttm_mem_reg *mem);
721604a1
JG		 2878void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2879 struct radeon_bo *bo);
421ca7ab
CK		 2880struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2881 struct radeon_bo *bo);
e971bd5e
CK		 2882struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2883 struct radeon_vm *vm,
2884 struct radeon_bo *bo);
2885int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2886 struct radeon_bo_va *bo_va,
2887 uint64_t offset,
2888 uint32_t flags);
036bf46a
CK		 2889void radeon_vm_bo_rmv(struct radeon_device *rdev,
2890 struct radeon_bo_va *bo_va);
721604a1 2891
f122c610
AD		 2892/* audio */
2893void r600_audio_update_hdmi(struct work_struct *work);
b530602f
AD		 2894struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2895struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
832eafaf
AD		 2896void r600_audio_enable(struct radeon_device *rdev,
2897 struct r600_audio_pin *pin,
d3d8c141 2898 u8 enable_mask);
832eafaf
AD		 2899void dce6_audio_enable(struct radeon_device *rdev,
2900 struct r600_audio_pin *pin,
d3d8c141 2901 u8 enable_mask);
721604a1 2902
16cdf04d
AD		 2903/*
2904 * R600 vram scratch functions
2905 */
2906int r600_vram_scratch_init(struct radeon_device *rdev);
2907void r600_vram_scratch_fini(struct radeon_device *rdev);
2908
285484e2
JG		 2909/*
2910 * r600 cs checking helper
2911 */
2912unsigned r600_mip_minify(unsigned size, unsigned level);
2913bool r600_fmt_is_valid_color(u32 format);
2914bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2915int r600_fmt_get_blocksize(u32 format);
2916int r600_fmt_get_nblocksx(u32 format, u32 w);
2917int r600_fmt_get_nblocksy(u32 format, u32 h);
2918
3574dda4
DV		 2919/*
2920 * r600 functions used by radeon_encoder.c
2921 */
1b688d08
RM		 2922struct radeon_hdmi_acr {
2923 u32 clock;
2924
2925 int n_32khz;
2926 int cts_32khz;
2927
2928 int n_44_1khz;
2929 int cts_44_1khz;
2930
2931 int n_48khz;
2932 int cts_48khz;
2933
2934};
2935
e55d3e6c
RM		 2936extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2937
416a2bd2
AD		 2938extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2939 u32 tiling_pipe_num,
2940 u32 max_rb_num,
2941 u32 total_max_rb_num,
2942 u32 enabled_rb_mask);
fe251e2f 2943
e55d3e6c
RM		 2944/*
2945 * evergreen functions used by radeon_encoder.c
2946 */
2947
0af62b01 2948extern int ni_init_microcode(struct radeon_device *rdev);
755d819e 2949extern int ni_mc_load_microcode(struct radeon_device *rdev);
0af62b01 2950
c4917074
AD		 2951/* radeon_acpi.c */
2952#if defined(CONFIG_ACPI)
2953extern int radeon_acpi_init(struct radeon_device *rdev);
2954extern void radeon_acpi_fini(struct radeon_device *rdev);
dc50ba7f
AD		 2955extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2956extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
e37e6a0e 2957 u8 perf_req, bool advertise);
dc50ba7f 2958extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
c4917074
AD		 2959#else
2960static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
2961static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2962#endif
d7a2952f 2963
c38f34b5
IH		 2964int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2965 struct radeon_cs_packet *pkt,
2966 unsigned idx);
9ffb7a6d 2967bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
c3ad63af
IH		 2968void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2969 struct radeon_cs_packet *pkt);
e9716993 2970int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1d0c0942 2971 struct radeon_bo_list **cs_reloc,
e9716993 2972 int nomm);
40592a17
IH		 2973int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
2974 uint32_t *vline_start_end,
2975 uint32_t *vline_status);
c38f34b5 2976
4c788679
JG		 2977#include "radeon_object.h"
2978
771fe6b9 2979#endif
Linux kernel - Deliverables
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