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Merge remote-tracking branch 'vfio/next'
[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_drv.c
CommitLineData
1da177e4
LT		 1/**
2 * \file radeon_drv.c
3 * ATI Radeon driver
4 *
5 * \author Gareth Hughes <gareth@valinux.com>
6 */
7
8/*
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
1da177e4
LT		 34#include "radeon_drv.h"
35
760285e7 36#include <drm/drm_pciids.h>
771fe6b9 37#include <linux/console.h>
e0cd3608 38#include <linux/module.h>
10ebc0bc
DA		 39#include <linux/pm_runtime.h>
40#include <linux/vga_switcheroo.h>
d9fc9413 41#include <drm/drm_gem.h>
44adece5 42#include <drm/drm_fb_helper.h>
d9fc9413 43
10ebc0bc 44#include "drm_crtc_helper.h"
e28740ec
OG		 45#include "radeon_kfd.h"
46
771fe6b9
JG		 47/*
48 * KMS wrapper.
0de1a57b
DA		 49 * - 2.0.0 - initial interface
50 * - 2.1.0 - add square tiling interface
fdb43528 51 * - 2.2.0 - add r6xx/r7xx const buffer support
cae94b0a 52 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
bc35afdb 53 * - 2.4.0 - add crtc id query
148a03bc 54 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
ab9e1f59 55 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
71901cc4 56 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
58bbf018 57 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
486af189 58 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
b8709894
AD		 59 * 2.10.0 - fusion 2D tiling
60 * 2.11.0 - backend map, initial compute support for the CS checker
e70f224c 61 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
dd220a00 62 * 2.13.0 - virtual memory support, streamout
285484e2 63 * 2.14.0 - add evergreen tiling informations
609c1e15 64 * 2.15.0 - add max_pipes query
d2609875 65 * 2.16.0 - fix evergreen 2D tiled surface calculation
7c77bf2a 66 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
0f457e48 67 * 2.18.0 - r600-eg: allow "invalid" DB formats
b51ad12a 68 * 2.19.0 - r600-eg: MSAA textures
6759a0a7 69 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
c116cc94 70 * 2.21.0 - r600-r700: FMASK and CMASK
523885de 71 * 2.22.0 - r600 only: RESOLVE_BOX allowed
46fc8781 72 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
61051afd 73 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
71bfe916 74 * 2.25.0 - eg+: new info request for num SE and num SH
4ac0533a 75 * 2.26.0 - r600-eg: fix htile size computation
8696e33f 76 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
4613ca14 77 * 2.28.0 - r600-eg: Add MEM_WRITE packet support
c18b1170 78 * 2.29.0 - R500 FP16 color clear registers
774c389f 79 * 2.30.0 - fix for FMASK texturing
a0a53aa8 80 * 2.31.0 - Add fastfb support for rs690
902aaef6 81 * 2.32.0 - new info request for rings working
64d7b8be 82 * 2.33.0 - Add SI tiling mode array query
39aee490 83 * 2.34.0 - Add CIK tiling mode array query
32f79a8a 84 * 2.35.0 - Add CIK macrotile mode array query
9482d0d3 85 * 2.36.0 - Fix CIK DCE tiling setup
7c4c62a0 86 * 2.37.0 - allow GS ring setup on r6xx/r7xx
020ff546
MO		 87 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
88 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
65fcf668 89 * 2.39.0 - Add INFO query for number of active CUs
72a9987e 90 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
897eba82 91 * CS to GPU on >= r600
16613743 92 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
1957d6be 93 * 2.42.0 - Add VCE/VUI (Video Usability Information) support
72b9076b 94 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
8c4f2bbd 95 * 2.44.0 - SET_APPEND_CNT packet3 support
3d02b7fe 96 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI
662ce7bc 97 * 2.46.0 - Add PFP_SYNC_ME support on evergreen
4d6bdbad 98 * 2.47.0 - Add UVD_NO_OP register support
771fe6b9
JG		 99 */
100#define KMS_DRIVER_MAJOR 2
4d6bdbad 101#define KMS_DRIVER_MINOR 47
771fe6b9
JG		 102#define KMS_DRIVER_PATCHLEVEL 0
103int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
104int radeon_driver_unload_kms(struct drm_device *dev);
771fe6b9
JG		 105void radeon_driver_lastclose_kms(struct drm_device *dev);
106int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
107void radeon_driver_postclose_kms(struct drm_device *dev,
108 struct drm_file *file_priv);
109void radeon_driver_preclose_kms(struct drm_device *dev,
110 struct drm_file *file_priv);
274ad65c
JG		 111int radeon_suspend_kms(struct drm_device *dev, bool suspend,
112 bool fbcon, bool freeze);
10ebc0bc 113int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
88e72717
TR		 114u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
115int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
116void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
117int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
f5a80209
MK		 118 int *max_error,
119 struct timeval *vblank_time,
120 unsigned flags);
771fe6b9
JG		 121void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
122int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
123void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
e9f0d76f 124irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
771fe6b9 125void radeon_gem_object_free(struct drm_gem_object *obj);
721604a1
JG		 126int radeon_gem_object_open(struct drm_gem_object *obj,
127 struct drm_file *file_priv);
128void radeon_gem_object_close(struct drm_gem_object *obj,
129 struct drm_file *file_priv);
f72a113a
CK		 130struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
131 struct drm_gem_object *gobj,
132 int flags);
88e72717
TR		 133extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
134 unsigned int flags, int *vpos, int *hpos,
3bb403bf
VS		 135 ktime_t *stime, ktime_t *etime,
136 const struct drm_display_mode *mode);
90c4cde9 137extern bool radeon_is_px(struct drm_device *dev);
baa70943 138extern const struct drm_ioctl_desc radeon_ioctls_kms[];
771fe6b9
JG		 139extern int radeon_max_kms_ioctl;
140int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
ff72145b
DA		 141int radeon_mode_dumb_mmap(struct drm_file *filp,
142 struct drm_device *dev,
143 uint32_t handle, uint64_t *offset_p);
144int radeon_mode_dumb_create(struct drm_file *file_priv,
145 struct drm_device *dev,
146 struct drm_mode_create_dumb *args);
1e6d17a5
AP		 147struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
148struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
b5e9c1a2 149 struct dma_buf_attachment *,
1e6d17a5
AP		 150 struct sg_table *sg);
151int radeon_gem_prime_pin(struct drm_gem_object *obj);
280cf211 152void radeon_gem_prime_unpin(struct drm_gem_object *obj);
3aac4502 153struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
1e6d17a5
AP		 154void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
155void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
14adc892
CK		 156extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
157 unsigned long arg);
ff72145b 158
771fe6b9
JG		 159#if defined(CONFIG_DEBUG_FS)
160int radeon_debugfs_init(struct drm_minor *minor);
161void radeon_debugfs_cleanup(struct drm_minor *minor);
162#endif
771fe6b9 163
14adc892
CK		 164/* atpx handler */
165#if defined(CONFIG_VGA_SWITCHEROO)
166void radeon_register_atpx_handler(void);
167void radeon_unregister_atpx_handler(void);
e1052b35 168bool radeon_has_atpx_dgpu_power_cntl(void);
b8c9fd5a 169bool radeon_is_atpx_hybrid(void);
14adc892
CK		 170#else
171static inline void radeon_register_atpx_handler(void) {}
172static inline void radeon_unregister_atpx_handler(void) {}
e1052b35 173static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
b8c9fd5a 174static inline bool radeon_is_atpx_hybrid(void) { return false; }
14adc892 175#endif
1da177e4 176
689b9d74 177int radeon_no_wb;
e9ced8e0 178int radeon_modeset = -1;
771fe6b9
JG		 179int radeon_dynclks = -1;
180int radeon_r4xx_atom = 0;
181int radeon_agpmode = 0;
182int radeon_vram_limit = 0;
edcd26e8 183int radeon_gart_size = -1; /* auto */
771fe6b9 184int radeon_benchmarking = 0;
ecc0b326 185int radeon_testing = 0;
771fe6b9 186int radeon_connector_table = 0;
4ce001ab 187int radeon_tv = 1;
108dc8e8 188int radeon_audio = -1;
f46c0120 189int radeon_disp_priority = 0;
e2b0a8e1 190int radeon_hw_i2c = 0;
197bbb3d 191int radeon_pcie_gen2 = -1;
a18cee15 192int radeon_msi = -1;
3368ff0c 193int radeon_lockup_timeout = 10000;
a0a53aa8 194int radeon_fastfb = 0;
da321c8a 195int radeon_dpm = -1;
1294d4a3 196int radeon_aspm = -1;
10ebc0bc 197int radeon_runtime_pm = -1;
363eb0b4 198int radeon_hard_reset = 0;
dfc230f9
CK		 199int radeon_vm_size = 8;
200int radeon_vm_block_size = -1;
a624f429 201int radeon_deep_color = 0;
39dc5454 202int radeon_use_pflipirq = 2;
6e909f74 203int radeon_bapm = -1;
bc13018b 204int radeon_backlight = -1;
875711f0 205int radeon_auxch = -1;
9843ead0 206int radeon_mst = 0;
f1a0a67a 207int radeon_uvd = 1;
fabb5935 208int radeon_vce = 1;
689b9d74 209
61a2d07d 210MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
689b9d74
DA		 211module_param_named(no_wb, radeon_no_wb, int, 0444);
212
771fe6b9
JG		 213MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
214module_param_named(modeset, radeon_modeset, int, 0400);
215
216MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
217module_param_named(dynclks, radeon_dynclks, int, 0444);
218
219MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
220module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
221
8902e6f2 222MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
771fe6b9
JG		 223module_param_named(vramlimit, radeon_vram_limit, int, 0600);
224
225MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
226module_param_named(agpmode, radeon_agpmode, int, 0444);
227
edcd26e8 228MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
771fe6b9
JG		 229module_param_named(gartsize, radeon_gart_size, int, 0600);
230
231MODULE_PARM_DESC(benchmark, "Run benchmark");
232module_param_named(benchmark, radeon_benchmarking, int, 0444);
233
ecc0b326
MD		 234MODULE_PARM_DESC(test, "Run tests");
235module_param_named(test, radeon_testing, int, 0444);
236
771fe6b9
JG		 237MODULE_PARM_DESC(connector_table, "Force connector table");
238module_param_named(connector_table, radeon_connector_table, int, 0444);
4ce001ab
DA		 239
240MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
241module_param_named(tv, radeon_tv, int, 0444);
771fe6b9 242
108dc8e8 243MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
dafc3bd5
CK		 244module_param_named(audio, radeon_audio, int, 0444);
245
f46c0120
AD		 246MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
247module_param_named(disp_priority, radeon_disp_priority, int, 0444);
248
e2b0a8e1
AD		 249MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
250module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
251
197bbb3d 252MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
d42dd579
AD		 253module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
254
a18cee15
AD		 255MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
256module_param_named(msi, radeon_msi, int, 0444);
257
b5c9ecab 258MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
3368ff0c
CK		 259module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
260
a0a53aa8
SL		 261MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
262module_param_named(fastfb, radeon_fastfb, int, 0444);
263
da321c8a
AD		 264MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
265module_param_named(dpm, radeon_dpm, int, 0444);
266
1294d4a3
AD		 267MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
268module_param_named(aspm, radeon_aspm, int, 0444);
269
10ebc0bc
DA		 270MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
271module_param_named(runpm, radeon_runtime_pm, int, 0444);
272
363eb0b4
AD		 273MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
274module_param_named(hard_reset, radeon_hard_reset, int, 0444);
275
20b2656d 276MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
c1c44132
CK		 277module_param_named(vm_size, radeon_vm_size, int, 0444);
278
dfc230f9 279MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
4510fb98
CK		 280module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
281
a624f429
AD		 282MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
283module_param_named(deep_color, radeon_deep_color, int, 0444);
284
39dc5454
MK		 285MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
286module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
287
6e909f74
AD		 288MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
289module_param_named(bapm, radeon_bapm, int, 0444);
290
bc13018b
AD		 291MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
292module_param_named(backlight, radeon_backlight, int, 0444);
293
875711f0
DA		 294MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
295module_param_named(auxch, radeon_auxch, int, 0444);
296
9843ead0
DA		 297MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
298module_param_named(mst, radeon_mst, int, 0444);
299
f1a0a67a
JG		 300MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
301module_param_named(uvd, radeon_uvd, int, 0444);
302
fabb5935
JG		 303MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
304module_param_named(vce, radeon_vce, int, 0444);
305
14adc892
CK		 306static struct pci_device_id pciidlist[] = {
307 radeon_PCI_IDS
308};
309
310MODULE_DEVICE_TABLE(pci, pciidlist);
311
771fe6b9
JG		 312static struct drm_driver kms_driver;
313
30238151 314static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
a56f7428
BH		 315{
316 struct apertures_struct *ap;
317 bool primary = false;
318
319 ap = alloc_apertures(1);
30238151
TR		 320 if (!ap)
321 return -ENOMEM;
322
a56f7428
BH		 323 ap->ranges[0].base = pci_resource_start(pdev, 0);
324 ap->ranges[0].size = pci_resource_len(pdev, 0);
325
326#ifdef CONFIG_X86
327 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
328#endif
44adece5 329 drm_fb_helper_remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
a56f7428 330 kfree(ap);
30238151
TR		 331
332 return 0;
a56f7428
BH		 333}
334
56550d94
GKH		 335static int radeon_pci_probe(struct pci_dev *pdev,
336 const struct pci_device_id *ent)
771fe6b9 337{
30238151
TR		 338 int ret;
339
412c8f7d
OG		 340 /*
341 * Initialize amdkfd before starting radeon. If it was not loaded yet,
342 * defer radeon probing
343 */
344 ret = radeon_kfd_init();
345 if (ret == -EPROBE_DEFER)
346 return ret;
347
b00e5334 348 if (vga_switcheroo_client_probe_defer(pdev))
14d20001
LW		 349 return -EPROBE_DEFER;
350
a56f7428 351 /* Get rid of things like offb */
30238151
TR		 352 ret = radeon_kick_out_firmware_fb(pdev);
353 if (ret)
354 return ret;
a56f7428 355
dcdb1674 356 return drm_get_pci_dev(pdev, ent, &kms_driver);
771fe6b9
JG		 357}
358
359static void
360radeon_pci_remove(struct pci_dev *pdev)
361{
362 struct drm_device *dev = pci_get_drvdata(pdev);
363
364 drm_put_dev(dev);
365}
366
7473e830 367static int radeon_pmops_suspend(struct device *dev)
771fe6b9 368{
7473e830
DA		 369 struct pci_dev *pdev = to_pci_dev(dev);
370 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 371 return radeon_suspend_kms(drm_dev, true, true, false);
771fe6b9
JG		 372}
373
7473e830 374static int radeon_pmops_resume(struct device *dev)
771fe6b9 375{
7473e830
DA		 376 struct pci_dev *pdev = to_pci_dev(dev);
377 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc 378 return radeon_resume_kms(drm_dev, true, true);
7473e830
DA		 379}
380
381static int radeon_pmops_freeze(struct device *dev)
382{
383 struct pci_dev *pdev = to_pci_dev(dev);
384 struct drm_device *drm_dev = pci_get_drvdata(pdev);
274ad65c 385 return radeon_suspend_kms(drm_dev, false, true, true);
771fe6b9
JG		 386}
387
7473e830
DA		 388static int radeon_pmops_thaw(struct device *dev)
389{
390 struct pci_dev *pdev = to_pci_dev(dev);
391 struct drm_device *drm_dev = pci_get_drvdata(pdev);
10ebc0bc
DA		 392 return radeon_resume_kms(drm_dev, false, true);
393}
394
395static int radeon_pmops_runtime_suspend(struct device *dev)
396{
397 struct pci_dev *pdev = to_pci_dev(dev);
398 struct drm_device *drm_dev = pci_get_drvdata(pdev);
399 int ret;
400
90c4cde9 401 if (!radeon_is_px(drm_dev)) {
1d8eec8b
DA		 402 pm_runtime_forbid(dev);
403 return -EBUSY;
404 }
9babd35a 405
10ebc0bc
DA		 406 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
407 drm_kms_helper_poll_disable(drm_dev);
408 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
409
274ad65c 410 ret = radeon_suspend_kms(drm_dev, false, false, false);
10ebc0bc
DA		 411 pci_save_state(pdev);
412 pci_disable_device(pdev);
b440bde7 413 pci_ignore_hotplug(pdev);
31764c1e
AD		 414 if (radeon_is_atpx_hybrid())
415 pci_set_power_state(pdev, PCI_D3cold);
84919992 416 else if (!radeon_has_atpx_dgpu_power_cntl())
f7ea4189 417 pci_set_power_state(pdev, PCI_D3hot);
10ebc0bc
DA		 418 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
419
420 return 0;
421}
422
423static int radeon_pmops_runtime_resume(struct device *dev)
424{
425 struct pci_dev *pdev = to_pci_dev(dev);
426 struct drm_device *drm_dev = pci_get_drvdata(pdev);
427 int ret;
428
90c4cde9 429 if (!radeon_is_px(drm_dev))
9babd35a
AD		 430 return -EINVAL;
431
10ebc0bc
DA		 432 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
433
84919992
AD		 434 if (radeon_is_atpx_hybrid() ||
435 !radeon_has_atpx_dgpu_power_cntl())
436 pci_set_power_state(pdev, PCI_D0);
10ebc0bc
DA		 437 pci_restore_state(pdev);
438 ret = pci_enable_device(pdev);
439 if (ret)
440 return ret;
441 pci_set_master(pdev);
442
443 ret = radeon_resume_kms(drm_dev, false, false);
444 drm_kms_helper_poll_enable(drm_dev);
445 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
446 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
447 return 0;
448}
449
450static int radeon_pmops_runtime_idle(struct device *dev)
451{
452 struct pci_dev *pdev = to_pci_dev(dev);
453 struct drm_device *drm_dev = pci_get_drvdata(pdev);
454 struct drm_crtc *crtc;
455
90c4cde9 456 if (!radeon_is_px(drm_dev)) {
1d8eec8b 457 pm_runtime_forbid(dev);
10ebc0bc
DA		 458 return -EBUSY;
459 }
460
461 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
462 if (crtc->enabled) {
463 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
464 return -EBUSY;
465 }
466 }
467
468 pm_runtime_mark_last_busy(dev);
469 pm_runtime_autosuspend(dev);
470 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
471 return 1;
472}
473
474long radeon_drm_ioctl(struct file *filp,
475 unsigned int cmd, unsigned long arg)
476{
477 struct drm_file *file_priv = filp->private_data;
478 struct drm_device *dev;
479 long ret;
480 dev = file_priv->minor->dev;
481 ret = pm_runtime_get_sync(dev->dev);
482 if (ret < 0)
483 return ret;
484
485 ret = drm_ioctl(filp, cmd, arg);
486
487 pm_runtime_mark_last_busy(dev->dev);
488 pm_runtime_put_autosuspend(dev->dev);
489 return ret;
7473e830
DA		 490}
491
492static const struct dev_pm_ops radeon_pm_ops = {
493 .suspend = radeon_pmops_suspend,
494 .resume = radeon_pmops_resume,
495 .freeze = radeon_pmops_freeze,
496 .thaw = radeon_pmops_thaw,
497 .poweroff = radeon_pmops_freeze,
498 .restore = radeon_pmops_resume,
10ebc0bc
DA		 499 .runtime_suspend = radeon_pmops_runtime_suspend,
500 .runtime_resume = radeon_pmops_runtime_resume,
501 .runtime_idle = radeon_pmops_runtime_idle,
7473e830
DA		 502};
503
e08e96de
AV		 504static const struct file_operations radeon_driver_kms_fops = {
505 .owner = THIS_MODULE,
506 .open = drm_open,
507 .release = drm_release,
10ebc0bc 508 .unlocked_ioctl = radeon_drm_ioctl,
e08e96de
AV		 509 .mmap = radeon_mmap,
510 .poll = drm_poll,
e08e96de
AV		 511 .read = drm_read,
512#ifdef CONFIG_COMPAT
513 .compat_ioctl = radeon_kms_compat_ioctl,
514#endif
515};
516
771fe6b9
JG		 517static struct drm_driver kms_driver = {
518 .driver_features =
28185647 519 DRIVER_USE_AGP |
81e95697 520 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
f33bcab9 521 DRIVER_PRIME | DRIVER_RENDER,
771fe6b9 522 .load = radeon_driver_load_kms,
771fe6b9
JG		 523 .open = radeon_driver_open_kms,
524 .preclose = radeon_driver_preclose_kms,
525 .postclose = radeon_driver_postclose_kms,
526 .lastclose = radeon_driver_lastclose_kms,
915b4d11 527 .set_busid = drm_pci_set_busid,
771fe6b9 528 .unload = radeon_driver_unload_kms,
771fe6b9
JG		 529 .get_vblank_counter = radeon_get_vblank_counter_kms,
530 .enable_vblank = radeon_enable_vblank_kms,
531 .disable_vblank = radeon_disable_vblank_kms,
f5a80209
MK		 532 .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
533 .get_scanout_position = radeon_get_crtc_scanoutpos,
771fe6b9
JG		 534#if defined(CONFIG_DEBUG_FS)
535 .debugfs_init = radeon_debugfs_init,
536 .debugfs_cleanup = radeon_debugfs_cleanup,
537#endif
538 .irq_preinstall = radeon_driver_irq_preinstall_kms,
539 .irq_postinstall = radeon_driver_irq_postinstall_kms,
540 .irq_uninstall = radeon_driver_irq_uninstall_kms,
541 .irq_handler = radeon_driver_irq_handler_kms,
771fe6b9 542 .ioctls = radeon_ioctls_kms,
71cbf451 543 .gem_free_object_unlocked = radeon_gem_object_free,
721604a1
JG		 544 .gem_open_object = radeon_gem_object_open,
545 .gem_close_object = radeon_gem_object_close,
ff72145b
DA		 546 .dumb_create = radeon_mode_dumb_create,
547 .dumb_map_offset = radeon_mode_dumb_mmap,
43387b37 548 .dumb_destroy = drm_gem_dumb_destroy,
e08e96de 549 .fops = &radeon_driver_kms_fops,
40f5cf99
AD		 550
551 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
552 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
f72a113a 553 .gem_prime_export = radeon_gem_prime_export,
1e6d17a5
AP		 554 .gem_prime_import = drm_gem_prime_import,
555 .gem_prime_pin = radeon_gem_prime_pin,
280cf211 556 .gem_prime_unpin = radeon_gem_prime_unpin,
3aac4502 557 .gem_prime_res_obj = radeon_gem_prime_res_obj,
1e6d17a5
AP		 558 .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
559 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
560 .gem_prime_vmap = radeon_gem_prime_vmap,
561 .gem_prime_vunmap = radeon_gem_prime_vunmap,
40f5cf99 562
771fe6b9
JG		 563 .name = DRIVER_NAME,
564 .desc = DRIVER_DESC,
565 .date = DRIVER_DATE,
566 .major = KMS_DRIVER_MAJOR,
567 .minor = KMS_DRIVER_MINOR,
568 .patchlevel = KMS_DRIVER_PATCHLEVEL,
569};
771fe6b9
JG		 570
571static struct drm_driver *driver;
8410ea3b
DA		 572static struct pci_driver *pdriver;
573
8410ea3b
DA		 574static struct pci_driver radeon_kms_pci_driver = {
575 .name = DRIVER_NAME,
576 .id_table = pciidlist,
577 .probe = radeon_pci_probe,
578 .remove = radeon_pci_remove,
7473e830 579 .driver.pm = &radeon_pm_ops,
8410ea3b 580};
771fe6b9 581
1da177e4
LT		 582static int __init radeon_init(void)
583{
e9ced8e0
DA		 584 if (vgacon_text_force() && radeon_modeset == -1) {
585 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
586 radeon_modeset = 0;
587 }
e9ced8e0
DA		 588 /* set to modesetting by default if not nomodeset */
589 if (radeon_modeset == -1)
590 radeon_modeset = 1;
591
771fe6b9
JG		 592 if (radeon_modeset == 1) {
593 DRM_INFO("radeon kernel modesetting enabled.\n");
594 driver = &kms_driver;
8410ea3b 595 pdriver = &radeon_kms_pci_driver;
771fe6b9
JG		 596 driver->driver_features |= DRIVER_MODESET;
597 driver->num_ioctls = radeon_max_kms_ioctl;
6a9ee8af 598 radeon_register_atpx_handler();
14adc892
CK		 599
600 } else {
14adc892
CK		 601 DRM_ERROR("No UMS support in radeon module!\n");
602 return -EINVAL;
771fe6b9 603 }
14adc892
CK		 604
605 /* let modprobe override vga console setting */
8410ea3b 606 return drm_pci_init(driver, pdriver);
1da177e4
LT		 607}
608
609static void __exit radeon_exit(void)
610{
e28740ec 611 radeon_kfd_fini();
8410ea3b 612 drm_pci_exit(driver, pdriver);
6a9ee8af 613 radeon_unregister_atpx_handler();
1da177e4
LT		 614}
615
176f613e 616module_init(radeon_init);
1da177e4
LT		 617module_exit(radeon_exit);
618
b5e89ed5
DA		 619MODULE_AUTHOR(DRIVER_AUTHOR);
620MODULE_DESCRIPTION(DRIVER_DESC);
1da177e4 621MODULE_LICENSE("GPL and additional rights");
Linux kernel - Deliverables
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