[deliverable/linux.git] / drivers / gpu / drm / radeon / radeon_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */
#include <linux/module.h>
#include <linux/slab.h>

#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/radeon_drm.h>
#include "radeon.h"

#include <drm/drm_fb_helper.h>

#include <linux/vga_switcheroo.h>

/* object hierarchy -
 * this contains a helper + a radeon fb
 * the helper contains a pointer to radeon framebuffer baseclass.
 */
struct radeon_fbdev {
	struct drm_fb_helper helper;
	struct radeon_framebuffer rfb;
	struct radeon_device *rdev;
};

static struct fb_ops radeonfb_ops = {
	.owner = THIS_MODULE,
	.fb_check_var = drm_fb_helper_check_var,
	.fb_set_par = drm_fb_helper_set_par,
	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	.fb_imageblit = drm_fb_helper_cfb_imageblit,
	.fb_pan_display = drm_fb_helper_pan_display,
	.fb_blank = drm_fb_helper_blank,
	.fb_setcmap = drm_fb_helper_setcmap,
	.fb_debug_enter = drm_fb_helper_debug_enter,
	.fb_debug_leave = drm_fb_helper_debug_leave,
};


int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
{
	int aligned = width;
	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
	int pitch_mask = 0;

	switch (bpp / 8) {
	case 1:
		pitch_mask = align_large ? 255 : 127;
		break;
	case 2:
		pitch_mask = align_large ? 127 : 31;
		break;
	case 3:
	case 4:
		pitch_mask = align_large ? 63 : 15;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned;
}

static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
	int ret;

	ret = radeon_bo_reserve(rbo, false);
	if (likely(ret == 0)) {
		radeon_bo_kunmap(rbo);
		radeon_bo_unpin(rbo);
		radeon_bo_unreserve(rbo);
	}
	drm_gem_object_unreference_unlocked(gobj);
}

static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
					 struct drm_mode_fb_cmd2 *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	struct radeon_device *rdev = rfbdev->rdev;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0;
	int ret;
	int aligned_size, size;
	int height = mode_cmd->height;
	u32 bpp, depth;

	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);

	/* need to align pitch with crtc limits */
	mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
						  fb_tiled) * ((bpp + 1) / 8);

	if (rdev->family >= CHIP_R600)
		height = ALIGN(mode_cmd->height, 8);
	size = mode_cmd->pitches[0] * height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = radeon_gem_object_create(rdev, aligned_size, 0,
				       RADEON_GEM_DOMAIN_VRAM,
				       0, true, &gobj);
	if (ret) {
		printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
		       aligned_size);
		return -ENOMEM;
	}
	rbo = gem_to_radeon_bo(gobj);

	if (fb_tiled)
		tiling_flags = RADEON_TILING_MACRO;

#ifdef __BIG_ENDIAN
	switch (bpp) {
	case 32:
		tiling_flags |= RADEON_TILING_SWAP_32BIT;
		break;
	case 16:
		tiling_flags |= RADEON_TILING_SWAP_16BIT;
	default:
		break;
	}
#endif

	if (tiling_flags) {
		ret = radeon_bo_set_tiling_flags(rbo,
						 tiling_flags | RADEON_TILING_SURFACE,
						 mode_cmd->pitches[0]);
		if (ret)
			dev_err(rdev->dev, "FB failed to set tiling flags\n");
	}


	ret = radeon_bo_reserve(rbo, false);
	if (unlikely(ret != 0))
		goto out_unref;
	/* Only 27 bit offset for legacy CRTC */
	ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
				       ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
				       NULL);
	if (ret) {
		radeon_bo_unreserve(rbo);
		goto out_unref;
	}
	if (fb_tiled)
		radeon_bo_check_tiling(rbo, 0, 0);
	ret = radeon_bo_kmap(rbo, NULL);
	radeon_bo_unreserve(rbo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	radeonfb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int radeonfb_create(struct drm_fb_helper *helper,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct radeon_fbdev *rfbdev =
		container_of(helper, struct radeon_fbdev, helper);
	struct radeon_device *rdev = rfbdev->rdev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd2 mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct radeon_bo *rbo = NULL;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	/* avivo can't scanout real 24bpp */
	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
		sizes->surface_bpp = 32;

	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
							  sizes->surface_depth);

	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	if (ret) {
		DRM_ERROR("failed to create fbcon object %d\n", ret);
		return ret;
	}

	rbo = gem_to_radeon_bo(gobj);

	/* okay we have an object now allocate the framebuffer */
	info = drm_fb_helper_alloc_fbi(helper);
	if (IS_ERR(info)) {
		ret = PTR_ERR(info);
		goto out_unref;
	}

	info->par = rfbdev;
	info->skip_vt_switch = true;

	ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
	if (ret) {
		DRM_ERROR("failed to initialize framebuffer %d\n", ret);
		goto out_destroy_fbi;
	}

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;

	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));

	strcpy(info->fix.id, "radeondrmfb");

	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);

	info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT;
	info->fbops = &radeonfb_ops;

	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
	info->fix.smem_start = rdev->mc.aper_base + tmp;
	info->fix.smem_len = radeon_bo_size(rbo);
	info->screen_base = rbo->kptr;
	info->screen_size = radeon_bo_size(rbo);

	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);

	/* setup aperture base/size for vesafb takeover */
	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = rdev->mc.aper_size;

	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out_destroy_fbi;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)rdev->mc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
	DRM_INFO("fb depth is %d\n", fb->depth);
	DRM_INFO("   pitch is %d\n", fb->pitches[0]);

	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
	return 0;

out_destroy_fbi:
	drm_fb_helper_release_fbi(helper);
out_unref:
	if (rbo) {

	}
	if (fb && ret) {
		drm_gem_object_unreference_unlocked(gobj);
		drm_framebuffer_unregister_private(fb);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

void radeon_fb_output_poll_changed(struct radeon_device *rdev)
{
	if (rdev->mode_info.rfbdev)
		drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
}

static int radeon_fbdev_destroy(struct drm_device *dev, struct radeon_fbdev *rfbdev)
{
	struct radeon_framebuffer *rfb = &rfbdev->rfb;

	drm_fb_helper_unregister_fbi(&rfbdev->helper);
	drm_fb_helper_release_fbi(&rfbdev->helper);

	if (rfb->obj) {
		radeonfb_destroy_pinned_object(rfb->obj);
		rfb->obj = NULL;
	}
	drm_fb_helper_fini(&rfbdev->helper);
	drm_framebuffer_unregister_private(&rfb->base);
	drm_framebuffer_cleanup(&rfb->base);

	return 0;
}

static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
	.gamma_set = radeon_crtc_fb_gamma_set,
	.gamma_get = radeon_crtc_fb_gamma_get,
	.fb_probe = radeonfb_create,
};

int radeon_fbdev_init(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* don't enable fbdev if no connectors */
	if (list_empty(&rdev->ddev->mode_config.connector_list))
		return 0;

	/* select 8 bpp console on RN50 or 16MB cards */
	if (ASIC_IS_RN50(rdev) || rdev->mc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->rdev = rdev;
	rdev->mode_info.rfbdev = rfbdev;

	drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper,
			      &radeon_fb_helper_funcs);

	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
				 rdev->num_crtc,
				 RADEONFB_CONN_LIMIT);
	if (ret)
		goto free;

	ret = drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	if (ret)
		goto fini;

	/* disable all the possible outputs/crtcs before entering KMS mode */
	drm_helper_disable_unused_functions(rdev->ddev);

	ret = drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	if (ret)
		goto fini;

	return 0;

fini:
	drm_fb_helper_fini(&rfbdev->helper);
free:
	kfree(rfbdev);
	return ret;
}

void radeon_fbdev_fini(struct radeon_device *rdev)
{
	if (!rdev->mode_info.rfbdev)
		return;

	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
	kfree(rdev->mode_info.rfbdev);
	rdev->mode_info.rfbdev = NULL;
}

void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
{
	if (rdev->mode_info.rfbdev)
		drm_fb_helper_set_suspend(&rdev->mode_info.rfbdev->helper, state);
}

bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj)
{
	if (!rdev->mode_info.rfbdev)
		return false;

	if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj))
		return true;
	return false;
}

void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector)
{
	if (rdev->mode_info.rfbdev)
		drm_fb_helper_add_one_connector(&rdev->mode_info.rfbdev->helper, connector);
}

void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector)
{
	if (rdev->mode_info.rfbdev)
		drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector);
}

void radeon_fbdev_restore_mode(struct radeon_device *rdev)
{
	struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev;
	struct drm_fb_helper *fb_helper;
	int ret;

	if (!rfbdev)
		return;

	fb_helper = &rfbdev->helper;

	ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
	if (ret)
		DRM_DEBUG("failed to restore crtc mode\n");
}
Commit	Line	Data
771fe6b9 JG	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
771fe6b9	26	#include <linux/module.h>
5a0e3ad6	27	#include <linux/slab.h>
771fe6b9	28
760285e7 DH	29	#include <drm/drmP.h>
	30	#include <drm/drm_crtc.h>
	31	#include <drm/drm_crtc_helper.h>
	32	#include <drm/radeon_drm.h>
771fe6b9 JG	33	#include "radeon.h"
771fe6b9 JG	34
760285e7	35	#include <drm/drm_fb_helper.h>
785b93ef	36
6a9ee8af DA	37	#include <linux/vga_switcheroo.h>
6a9ee8af DA	38
38651674	39	/* object hierarchy -
3cf8bb1a JG	40	* this contains a helper + a radeon fb
	41	* the helper contains a pointer to radeon framebuffer baseclass.
	42	*/
8be48d92	43	struct radeon_fbdev {
785b93ef	44	struct drm_fb_helper helper;
38651674	45	struct radeon_framebuffer rfb;
38651674	46	struct radeon_device *rdev;
771fe6b9 JG	47	};
771fe6b9 JG	48
771fe6b9 JG	49	static struct fb_ops radeonfb_ops = {
771fe6b9 JG	50	.owner = THIS_MODULE,
c88f9f0c	51	.fb_check_var = drm_fb_helper_check_var,
0c6dadbe	52	.fb_set_par = drm_fb_helper_set_par,
00450052 AT	53	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	54	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	55	.fb_imageblit = drm_fb_helper_cfb_imageblit,
785b93ef DA	56	.fb_pan_display = drm_fb_helper_pan_display,
785b93ef DA	57	.fb_blank = drm_fb_helper_blank,
068143d3	58	.fb_setcmap = drm_fb_helper_setcmap,
4dd19b0d CB	59	.fb_debug_enter = drm_fb_helper_debug_enter,
4dd19b0d CB	60	.fb_debug_leave = drm_fb_helper_debug_leave,
771fe6b9 JG	61	};
771fe6b9 JG	62
771fe6b9	63
ff72145b	64	int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled)
771fe6b9 JG	65	{
771fe6b9 JG	66	int aligned = width;
e024e110	67	int align_large = (ASIC_IS_AVIVO(rdev)) \|\| tiled;
771fe6b9 JG	68	int pitch_mask = 0;
	69
	70	switch (bpp / 8) {
	71	case 1:
	72	pitch_mask = align_large ? 255 : 127;
	73	break;
	74	case 2:
	75	pitch_mask = align_large ? 127 : 31;
	76	break;
	77	case 3:
	78	case 4:
	79	pitch_mask = align_large ? 63 : 15;
	80	break;
	81	}
	82
	83	aligned += pitch_mask;
	84	aligned &= ~pitch_mask;
	85	return aligned;
	86	}
	87
8be48d92	88	static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
771fe6b9	89	{
7e4d15d9	90	struct radeon_bo *rbo = gem_to_radeon_bo(gobj);
8be48d92 DA	91	int ret;
	92
	93	ret = radeon_bo_reserve(rbo, false);
	94	if (likely(ret == 0)) {
	95	radeon_bo_kunmap(rbo);
29d08b3e	96	radeon_bo_unpin(rbo);
8be48d92 DA	97	radeon_bo_unreserve(rbo);
	98	}
	99	drm_gem_object_unreference_unlocked(gobj);
	100	}
785b93ef	101
8be48d92	102	static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
308e5bcb	103	struct drm_mode_fb_cmd2 *mode_cmd,
8be48d92	104	struct drm_gem_object **gobj_p)
771fe6b9	105	{
8be48d92	106	struct radeon_device *rdev = rfbdev->rdev;
771fe6b9	107	struct drm_gem_object *gobj = NULL;
4c788679	108	struct radeon_bo *rbo = NULL;
e024e110	109	bool fb_tiled = false; /* useful for testing */
c88f9f0c	110	u32 tiling_flags = 0;
8be48d92 DA	111	int ret;
8be48d92 DA	112	int aligned_size, size;
e40b6fc8	113	int height = mode_cmd->height;
308e5bcb JB	114	u32 bpp, depth;
308e5bcb JB	115
248dbc23	116	drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
771fe6b9	117
771fe6b9	118	/* need to align pitch with crtc limits */
308e5bcb JB	119	mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
308e5bcb JB	120	fb_tiled) * ((bpp + 1) / 8);
771fe6b9	121
e40b6fc8 DA	122	if (rdev->family >= CHIP_R600)
e40b6fc8 DA	123	height = ALIGN(mode_cmd->height, 8);
308e5bcb	124	size = mode_cmd->pitches[0] * height;
771fe6b9	125	aligned_size = ALIGN(size, PAGE_SIZE);
771fe6b9	126	ret = radeon_gem_object_create(rdev, aligned_size, 0,
8be48d92	127	RADEON_GEM_DOMAIN_VRAM,
ed5cb43f	128	0, true, &gobj);
771fe6b9	129	if (ret) {
8be48d92 DA	130	printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
	131	aligned_size);
	132	return -ENOMEM;
771fe6b9	133	}
7e4d15d9	134	rbo = gem_to_radeon_bo(gobj);
771fe6b9	135
e024e110	136	if (fb_tiled)
c88f9f0c MD	137	tiling_flags = RADEON_TILING_MACRO;
	138
	139	#ifdef __BIG_ENDIAN
435ddd92	140	switch (bpp) {
c88f9f0c MD	141	case 32:
	142	tiling_flags \|= RADEON_TILING_SWAP_32BIT;
	143	break;
	144	case 16:
	145	tiling_flags \|= RADEON_TILING_SWAP_16BIT;
	146	default:
	147	break;
	148	}
	149	#endif
	150
4c788679 JG	151	if (tiling_flags) {
4c788679 JG	152	ret = radeon_bo_set_tiling_flags(rbo,
8be48d92	153	tiling_flags \| RADEON_TILING_SURFACE,
308e5bcb	154	mode_cmd->pitches[0]);
4c788679 JG	155	if (ret)
	156	dev_err(rdev->dev, "FB failed to set tiling flags\n");
	157	}
8be48d92	158
38651674	159
4c788679 JG	160	ret = radeon_bo_reserve(rbo, false);
	161	if (unlikely(ret != 0))
	162	goto out_unref;
0349af70 MD	163	/* Only 27 bit offset for legacy CRTC */
	164	ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
	165	ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
	166	NULL);
4c788679 JG	167	if (ret) {
	168	radeon_bo_unreserve(rbo);
	169	goto out_unref;
	170	}
	171	if (fb_tiled)
	172	radeon_bo_check_tiling(rbo, 0, 0);
8be48d92	173	ret = radeon_bo_kmap(rbo, NULL);
4c788679	174	radeon_bo_unreserve(rbo);
f92e93eb	175	if (ret) {
f92e93eb JG	176	goto out_unref;
f92e93eb JG	177	}
771fe6b9	178
8be48d92 DA	179	*gobj_p = gobj;
	180	return 0;
	181	out_unref:
	182	radeonfb_destroy_pinned_object(gobj);
	183	*gobj_p = NULL;
	184	return ret;
	185	}
	186
cd5428a5	187	static int radeonfb_create(struct drm_fb_helper *helper,
8be48d92 DA	188	struct drm_fb_helper_surface_size *sizes)
8be48d92 DA	189	{
a1d0280e FF	190	struct radeon_fbdev *rfbdev =
a1d0280e FF	191	container_of(helper, struct radeon_fbdev, helper);
8be48d92 DA	192	struct radeon_device *rdev = rfbdev->rdev;
	193	struct fb_info *info;
	194	struct drm_framebuffer *fb = NULL;
308e5bcb	195	struct drm_mode_fb_cmd2 mode_cmd;
8be48d92 DA	196	struct drm_gem_object *gobj = NULL;
8be48d92 DA	197	struct radeon_bo *rbo = NULL;
8be48d92 DA	198	int ret;
	199	unsigned long tmp;
	200
	201	mode_cmd.width = sizes->surface_width;
	202	mode_cmd.height = sizes->surface_height;
	203
	204	/* avivo can't scanout real 24bpp */
	205	if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
	206	sizes->surface_bpp = 32;
	207
308e5bcb JB	208	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
308e5bcb JB	209	sizes->surface_depth);
771fe6b9	210
8be48d92	211	ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
aaefcd42 DA	212	if (ret) {
	213	DRM_ERROR("failed to create fbcon object %d\n", ret);
	214	return ret;
	215	}
	216
7e4d15d9	217	rbo = gem_to_radeon_bo(gobj);
771fe6b9	218
8be48d92	219	/* okay we have an object now allocate the framebuffer */
00450052 AT	220	info = drm_fb_helper_alloc_fbi(helper);
	221	if (IS_ERR(info)) {
	222	ret = PTR_ERR(info);
771fe6b9 JG	223	goto out_unref;
771fe6b9 JG	224	}
785b93ef	225
8be48d92	226	info->par = rfbdev;
d57c0edf	227	info->skip_vt_switch = true;
771fe6b9	228
aaefcd42 DA	229	ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
aaefcd42 DA	230	if (ret) {
8b513d0c	231	DRM_ERROR("failed to initialize framebuffer %d\n", ret);
00450052	232	goto out_destroy_fbi;
aaefcd42	233	}
8be48d92	234
38651674 DA	235	fb = &rfbdev->rfb.base;
	236
	237	/* setup helper */
	238	rfbdev->helper.fb = fb;
38651674	239
8be48d92	240	memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo));
bf8e828b	241
771fe6b9	242	strcpy(info->fix.id, "radeondrmfb");
785b93ef	243
01f2c773	244	drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth);
3632ef89	245
8fd4bd22	246	info->flags = FBINFO_DEFAULT \| FBINFO_CAN_FORCE_OUTPUT;
771fe6b9	247	info->fbops = &radeonfb_ops;
785b93ef	248
8be48d92	249	tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start;
f92e93eb	250	info->fix.smem_start = rdev->mc.aper_base + tmp;
8be48d92 DA	251	info->fix.smem_len = radeon_bo_size(rbo);
	252	info->screen_base = rbo->kptr;
	253	info->screen_size = radeon_bo_size(rbo);
785b93ef	254
38651674	255	drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
ed8f0d9e DA	256
ed8f0d9e DA	257	/* setup aperture base/size for vesafb takeover */
1471ca9a	258	info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base;
68d30596	259	info->apertures->ranges[0].size = rdev->mc.aper_size;
ed8f0d9e	260
fb2a99e1	261	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
4abe3520	262
771fe6b9 JG	263	if (info->screen_base == NULL) {
771fe6b9 JG	264	ret = -ENOSPC;
00450052	265	goto out_destroy_fbi;
4abe3520 DA	266	}
4abe3520 DA	267
771fe6b9 JG	268	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
771fe6b9 JG	269	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base);
8be48d92	270	DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo));
771fe6b9	271	DRM_INFO("fb depth is %d\n", fb->depth);
01f2c773	272	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
771fe6b9	273
6a9ee8af	274	vga_switcheroo_client_fb_set(rdev->ddev->pdev, info);
771fe6b9 JG	275	return 0;
771fe6b9 JG	276
00450052 AT	277	out_destroy_fbi:
00450052 AT	278	drm_fb_helper_release_fbi(helper);
771fe6b9	279	out_unref:
4c788679	280	if (rbo) {
8be48d92	281
771fe6b9	282	}
f92e93eb	283	if (fb && ret) {
623fc3b7	284	drm_gem_object_unreference_unlocked(gobj);
36206361	285	drm_framebuffer_unregister_private(fb);
771fe6b9 JG	286	drm_framebuffer_cleanup(fb);
	287	kfree(fb);
	288	}
771fe6b9 JG	289	return ret;
	290	}
	291
eb1f8e4f	292	void radeon_fb_output_poll_changed(struct radeon_device *rdev)
771fe6b9	293	{
e5f243bd AD	294	if (rdev->mode_info.rfbdev)
e5f243bd AD	295	drm_fb_helper_hotplug_event(&rdev->mode_info.rfbdev->helper);
771fe6b9	296	}
771fe6b9	297
8be48d92	298	static int radeon_fbdev_destroy(struct drm_device dev, struct radeon_fbdev rfbdev)
771fe6b9	299	{
38651674	300	struct radeon_framebuffer *rfb = &rfbdev->rfb;
771fe6b9	301
00450052 AT	302	drm_fb_helper_unregister_fbi(&rfbdev->helper);
00450052 AT	303	drm_fb_helper_release_fbi(&rfbdev->helper);
771fe6b9	304
8be48d92	305	if (rfb->obj) {
29d08b3e DA	306	radeonfb_destroy_pinned_object(rfb->obj);
29d08b3e DA	307	rfb->obj = NULL;
771fe6b9	308	}
4abe3520	309	drm_fb_helper_fini(&rfbdev->helper);
36206361	310	drm_framebuffer_unregister_private(&rfb->base);
38651674	311	drm_framebuffer_cleanup(&rfb->base);
771fe6b9	312
771fe6b9 JG	313	return 0;
771fe6b9 JG	314	}
785b93ef	315
3a493879	316	static const struct drm_fb_helper_funcs radeon_fb_helper_funcs = {
4abe3520 DA	317	.gamma_set = radeon_crtc_fb_gamma_set,
4abe3520 DA	318	.gamma_get = radeon_crtc_fb_gamma_get,
cd5428a5	319	.fb_probe = radeonfb_create,
4abe3520	320	};
38651674 DA	321
	322	int radeon_fbdev_init(struct radeon_device *rdev)
	323	{
8be48d92	324	struct radeon_fbdev *rfbdev;
4abe3520	325	int bpp_sel = 32;
5a79395b	326	int ret;
4abe3520	327
e5f243bd AD	328	/* don't enable fbdev if no connectors */
	329	if (list_empty(&rdev->ddev->mode_config.connector_list))
	330	return 0;
	331
4abe3520 DA	332	/* select 8 bpp console on RN50 or 16MB cards */
	333	if (ASIC_IS_RN50(rdev) \|\| rdev->mc.real_vram_size <= (3210241024))
	334	bpp_sel = 8;
8be48d92 DA	335
	336	rfbdev = kzalloc(sizeof(struct radeon_fbdev), GFP_KERNEL);
	337	if (!rfbdev)
	338	return -ENOMEM;
	339
	340	rfbdev->rdev = rdev;
	341	rdev->mode_info.rfbdev = rfbdev;
10a23102 TR	342
	343	drm_fb_helper_prepare(rdev->ddev, &rfbdev->helper,
	344	&radeon_fb_helper_funcs);
8be48d92	345
5a79395b CW	346	ret = drm_fb_helper_init(rdev->ddev, &rfbdev->helper,
	347	rdev->num_crtc,
	348	RADEONFB_CONN_LIMIT);
01934c2a TR	349	if (ret)
01934c2a TR	350	goto free;
5a79395b	351
01934c2a TR	352	ret = drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
	353	if (ret)
	354	goto fini;
76a39dbf DV	355
	356	/* disable all the possible outputs/crtcs before entering KMS mode */
	357	drm_helper_disable_unused_functions(rdev->ddev);
	358
01934c2a TR	359	ret = drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	360	if (ret)
	361	goto fini;
	362
771fe6b9	363	return 0;
01934c2a TR	364
	365	fini:
	366	drm_fb_helper_fini(&rfbdev->helper);
	367	free:
	368	kfree(rfbdev);
	369	return ret;
38651674 DA	370	}
	371
	372	void radeon_fbdev_fini(struct radeon_device *rdev)
	373	{
8be48d92 DA	374	if (!rdev->mode_info.rfbdev)
	375	return;
	376
38651674	377	radeon_fbdev_destroy(rdev->ddev, rdev->mode_info.rfbdev);
8be48d92	378	kfree(rdev->mode_info.rfbdev);
38651674 DA	379	rdev->mode_info.rfbdev = NULL;
	380	}
	381
	382	void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state)
	383	{
e5f243bd	384	if (rdev->mode_info.rfbdev)
9db7d2b2	385	drm_fb_helper_set_suspend(&rdev->mode_info.rfbdev->helper, state);
38651674 DA	386	}
38651674 DA	387
38651674 DA	388	bool radeon_fbdev_robj_is_fb(struct radeon_device rdev, struct radeon_bo robj)
38651674 DA	389	{
e5f243bd AD	390	if (!rdev->mode_info.rfbdev)
	391	return false;
	392
7e4d15d9	393	if (robj == gem_to_radeon_bo(rdev->mode_info.rfbdev->rfb.obj))
38651674 DA	394	return true;
38651674 DA	395	return false;
771fe6b9	396	}
bb26270e DA	397
	398	void radeon_fb_add_connector(struct radeon_device rdev, struct drm_connector connector)
	399	{
e5f243bd AD	400	if (rdev->mode_info.rfbdev)
e5f243bd AD	401	drm_fb_helper_add_one_connector(&rdev->mode_info.rfbdev->helper, connector);
bb26270e DA	402	}
	403
	404	void radeon_fb_remove_connector(struct radeon_device rdev, struct drm_connector connector)
	405	{
e5f243bd AD	406	if (rdev->mode_info.rfbdev)
e5f243bd AD	407	drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector);
bb26270e	408	}
8c70e1cd AD	409
	410	void radeon_fbdev_restore_mode(struct radeon_device *rdev)
	411	{
	412	struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev;
	413	struct drm_fb_helper *fb_helper;
	414	int ret;
	415
	416	if (!rfbdev)
	417	return;
	418
	419	fb_helper = &rfbdev->helper;
	420
	421	ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
	422	if (ret)
	423	DRM_DEBUG("failed to restore crtc mode\n");
	424	}