[deliverable/linux.git] / drivers / gpu / drm / rockchip / analogix_dp-rockchip.c

/*
 * Rockchip SoC DP (Display Port) interface driver.
 *
 * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
 * Author: Andy Yan <andy.yan@rock-chips.com>
 *         Yakir Yang <ykk@rock-chips.com>
 *         Jeff Chen <jeff.chen@rock-chips.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/component.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/clk.h>

#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_dp_helper.h>
#include <drm/drm_of.h>
#include <drm/drm_panel.h>

#include <video/of_videomode.h>
#include <video/videomode.h>

#include <drm/bridge/analogix_dp.h>

#include "rockchip_drm_drv.h"
#include "rockchip_drm_psr.h"
#include "rockchip_drm_vop.h"

#define RK3288_GRF_SOC_CON6		0x25c
#define RK3288_EDP_LCDC_SEL		BIT(5)
#define RK3399_GRF_SOC_CON20		0x6250
#define RK3399_EDP_LCDC_SEL		BIT(5)

#define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)

#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS	100

#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)

/**
 * struct rockchip_dp_chip_data - splite the grf setting of kind of chips
 * @lcdsel_grf_reg: grf register offset of lcdc select
 * @lcdsel_big: reg value of selecting vop big for eDP
 * @lcdsel_lit: reg value of selecting vop little for eDP
 * @chip_type: specific chip type
 */
struct rockchip_dp_chip_data {
	u32	lcdsel_grf_reg;
	u32	lcdsel_big;
	u32	lcdsel_lit;
	u32	chip_type;
};

struct rockchip_dp_device {
	struct drm_device        *drm_dev;
	struct device            *dev;
	struct drm_encoder       encoder;
	struct drm_display_mode  mode;

	struct clk               *pclk;
	struct clk               *grfclk;
	struct regmap            *grf;
	struct reset_control     *rst;

	struct work_struct	 psr_work;
	spinlock_t		 psr_lock;
	unsigned int             psr_state;

	const struct rockchip_dp_chip_data *data;

	struct analogix_dp_plat_data plat_data;
};

static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
{
	struct rockchip_dp_device *dp = to_dp(encoder);
	unsigned long flags;

	dev_dbg(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");

	spin_lock_irqsave(&dp->psr_lock, flags);
	if (enabled)
		dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
	else
		dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;

	schedule_work(&dp->psr_work);
	spin_unlock_irqrestore(&dp->psr_lock, flags);
}

static void analogix_dp_psr_work(struct work_struct *work)
{
	struct rockchip_dp_device *dp =
				container_of(work, typeof(*dp), psr_work);
	struct drm_crtc *crtc = dp->encoder.crtc;
	int psr_state = dp->psr_state;
	int vact_end;
	int ret;
	unsigned long flags;

	if (!crtc)
		return;

	vact_end = crtc->mode.vtotal - crtc->mode.vsync_start + crtc->mode.vdisplay;

	ret = rockchip_drm_wait_line_flag(dp->encoder.crtc, vact_end,
					  PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
	if (ret) {
		dev_err(dp->dev, "line flag interrupt did not arrive\n");
		return;
	}

	spin_lock_irqsave(&dp->psr_lock, flags);
	if (psr_state == EDP_VSC_PSR_STATE_ACTIVE)
		analogix_dp_enable_psr(dp->dev);
	else
		analogix_dp_disable_psr(dp->dev);
	spin_unlock_irqrestore(&dp->psr_lock, flags);
}

static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
{
	reset_control_assert(dp->rst);
	usleep_range(10, 20);
	reset_control_deassert(dp->rst);

	return 0;
}

static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = to_dp(plat_data);
	int ret;

	cancel_work_sync(&dp->psr_work);

	ret = clk_prepare_enable(dp->pclk);
	if (ret < 0) {
		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
		return ret;
	}

	ret = rockchip_dp_pre_init(dp);
	if (ret < 0) {
		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
		clk_disable_unprepare(dp->pclk);
		return ret;
	}

	return 0;
}

static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
{
	struct rockchip_dp_device *dp = to_dp(plat_data);

	clk_disable_unprepare(dp->pclk);

	return 0;
}

static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
				 struct drm_connector *connector)
{
	struct drm_display_info *di = &connector->display_info;
	/* VOP couldn't output YUV video format for eDP rightly */
	u32 mask = DRM_COLOR_FORMAT_YCRCB444 | DRM_COLOR_FORMAT_YCRCB422;

	if ((di->color_formats & mask)) {
		DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
		di->color_formats &= ~mask;
		di->color_formats |= DRM_COLOR_FORMAT_RGB444;
		di->bpc = 8;
	}

	return 0;
}

static bool
rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
				   const struct drm_display_mode *mode,
				   struct drm_display_mode *adjusted_mode)
{
	/* do nothing */
	return true;
}

static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
					     struct drm_display_mode *mode,
					     struct drm_display_mode *adjusted)
{
	/* do nothing */
}

static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
{
	struct rockchip_dp_device *dp = to_dp(encoder);
	int ret;
	u32 val;

	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
	if (ret < 0)
		return;

	if (ret)
		val = dp->data->lcdsel_lit;
	else
		val = dp->data->lcdsel_big;

	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");

	ret = clk_prepare_enable(dp->grfclk);
	if (ret < 0) {
		dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
		return;
	}

	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	if (ret != 0)
		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);

	clk_disable_unprepare(dp->grfclk);
}

static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
{
	/* do nothing */
}

static int
rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
				      struct drm_crtc_state *crtc_state,
				      struct drm_connector_state *conn_state)
{
	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
	struct rockchip_dp_device *dp = to_dp(encoder);
	int ret;

	/*
	 * The hardware IC designed that VOP must output the RGB10 video
	 * format to eDP controller, and if eDP panel only support RGB8,
	 * then eDP controller should cut down the video data, not via VOP
	 * controller, that's why we need to hardcode the VOP output mode
	 * to RGA10 here.
	 */

	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
	s->output_type = DRM_MODE_CONNECTOR_eDP;
	if (dp->data->chip_type == RK3399_EDP) {
		/*
		 * For RK3399, VOP Lit must code the out mode to RGB888,
		 * VOP Big must code the out mode to RGB10.
		 */
		ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
							encoder);
		if (ret > 0)
			s->output_mode = ROCKCHIP_OUT_MODE_P888;
	}

	return 0;
}

static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
	.mode_set = rockchip_dp_drm_encoder_mode_set,
	.enable = rockchip_dp_drm_encoder_enable,
	.disable = rockchip_dp_drm_encoder_nop,
	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
};

static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
{
	drm_encoder_cleanup(encoder);
}

static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
	.destroy = rockchip_dp_drm_encoder_destroy,
};

static int rockchip_dp_init(struct rockchip_dp_device *dp)
{
	struct device *dev = dp->dev;
	struct device_node *np = dev->of_node;
	int ret;

	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	if (IS_ERR(dp->grf)) {
		dev_err(dev, "failed to get rockchip,grf property\n");
		return PTR_ERR(dp->grf);
	}

	dp->grfclk = devm_clk_get(dev, "grf");
	if (PTR_ERR(dp->grfclk) == -ENOENT) {
		dp->grfclk = NULL;
	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
		return -EPROBE_DEFER;
	} else if (IS_ERR(dp->grfclk)) {
		dev_err(dev, "failed to get grf clock\n");
		return PTR_ERR(dp->grfclk);
	}

	dp->pclk = devm_clk_get(dev, "pclk");
	if (IS_ERR(dp->pclk)) {
		dev_err(dev, "failed to get pclk property\n");
		return PTR_ERR(dp->pclk);
	}

	dp->rst = devm_reset_control_get(dev, "dp");
	if (IS_ERR(dp->rst)) {
		dev_err(dev, "failed to get dp reset control\n");
		return PTR_ERR(dp->rst);
	}

	ret = clk_prepare_enable(dp->pclk);
	if (ret < 0) {
		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
		return ret;
	}

	ret = rockchip_dp_pre_init(dp);
	if (ret < 0) {
		dev_err(dp->dev, "failed to pre init %d\n", ret);
		clk_disable_unprepare(dp->pclk);
		return ret;
	}

	return 0;
}

static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
{
	struct drm_encoder *encoder = &dp->encoder;
	struct drm_device *drm_dev = dp->drm_dev;
	struct device *dev = dp->dev;
	int ret;

	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
							     dev->of_node);
	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);

	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
			       DRM_MODE_ENCODER_TMDS, NULL);
	if (ret) {
		DRM_ERROR("failed to initialize encoder with drm\n");
		return ret;
	}

	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);

	return 0;
}

static int rockchip_dp_bind(struct device *dev, struct device *master,
			    void *data)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	const struct rockchip_dp_chip_data *dp_data;
	struct drm_device *drm_dev = data;
	int ret;

	/*
	 * Just like the probe function said, we don't need the
	 * device drvrate anymore, we should leave the charge to
	 * analogix dp driver, set the device drvdata to NULL.
	 */
	dev_set_drvdata(dev, NULL);

	dp_data = of_device_get_match_data(dev);
	if (!dp_data)
		return -ENODEV;

	ret = rockchip_dp_init(dp);
	if (ret < 0)
		return ret;

	dp->data = dp_data;
	dp->drm_dev = drm_dev;

	ret = rockchip_dp_drm_create_encoder(dp);
	if (ret) {
		DRM_ERROR("failed to create drm encoder\n");
		return ret;
	}

	dp->plat_data.encoder = &dp->encoder;

	dp->plat_data.dev_type = dp->data->chip_type;
	dp->plat_data.power_on = rockchip_dp_poweron;
	dp->plat_data.power_off = rockchip_dp_powerdown;
	dp->plat_data.get_modes = rockchip_dp_get_modes;

	spin_lock_init(&dp->psr_lock);
	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
	INIT_WORK(&dp->psr_work, analogix_dp_psr_work);

	rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);

	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
}

static void rockchip_dp_unbind(struct device *dev, struct device *master,
			       void *data)
{
	struct rockchip_dp_device *dp = dev_get_drvdata(dev);

	rockchip_drm_psr_unregister(&dp->encoder);

	return analogix_dp_unbind(dev, master, data);
}

static const struct component_ops rockchip_dp_component_ops = {
	.bind = rockchip_dp_bind,
	.unbind = rockchip_dp_unbind,
};

static int rockchip_dp_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *panel_node, *port, *endpoint;
	struct drm_panel *panel = NULL;
	struct rockchip_dp_device *dp;

	port = of_graph_get_port_by_id(dev->of_node, 1);
	if (port) {
		endpoint = of_get_child_by_name(port, "endpoint");
		of_node_put(port);
		if (!endpoint) {
			dev_err(dev, "no output endpoint found\n");
			return -EINVAL;
		}

		panel_node = of_graph_get_remote_port_parent(endpoint);
		of_node_put(endpoint);
		if (!panel_node) {
			dev_err(dev, "no output node found\n");
			return -EINVAL;
		}

		panel = of_drm_find_panel(panel_node);
		of_node_put(panel_node);
		if (!panel)
			return -EPROBE_DEFER;
	}

	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
	if (!dp)
		return -ENOMEM;

	dp->dev = dev;

	dp->plat_data.panel = panel;

	/*
	 * We just use the drvdata until driver run into component
	 * add function, and then we would set drvdata to null, so
	 * that analogix dp driver could take charge of the drvdata.
	 */
	platform_set_drvdata(pdev, dp);

	return component_add(dev, &rockchip_dp_component_ops);
}

static int rockchip_dp_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &rockchip_dp_component_ops);

	return 0;
}

static const struct dev_pm_ops rockchip_dp_pm_ops = {
#ifdef CONFIG_PM_SLEEP
	.suspend = analogix_dp_suspend,
	.resume_early = analogix_dp_resume,
#endif
};

static const struct rockchip_dp_chip_data rk3399_edp = {
	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
	.chip_type = RK3399_EDP,
};

static const struct rockchip_dp_chip_data rk3288_dp = {
	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
	.chip_type = RK3288_DP,
};

static const struct of_device_id rockchip_dp_dt_ids[] = {
	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
	{}
};
MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);

static struct platform_driver rockchip_dp_driver = {
	.probe = rockchip_dp_probe,
	.remove = rockchip_dp_remove,
	.driver = {
		   .name = "rockchip-dp",
		   .pm = &rockchip_dp_pm_ops,
		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
	},
};

module_platform_driver(rockchip_dp_driver);

MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9e32e16e YY	1	/*
	2	* Rockchip SoC DP (Display Port) interface driver.
	3	*
	4	* Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
	5	* Author: Andy Yan <andy.yan@rock-chips.com>
	6	* Yakir Yang <ykk@rock-chips.com>
	7	* Jeff Chen <jeff.chen@rock-chips.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License as published by the
	11	* Free Software Foundation; either version 2 of the License, or (at your
	12	* option) any later version.
	13	*/
	14
	15	#include <linux/component.h>
	16	#include <linux/mfd/syscon.h>
d9c900b0	17	#include <linux/of_device.h>
9e32e16e YY	18	#include <linux/of_graph.h>
	19	#include <linux/regmap.h>
	20	#include <linux/reset.h>
	21	#include <linux/clk.h>
	22
	23	#include <drm/drmP.h>
	24	#include <drm/drm_crtc_helper.h>
	25	#include <drm/drm_dp_helper.h>
	26	#include <drm/drm_of.h>
	27	#include <drm/drm_panel.h>
	28
	29	#include <video/of_videomode.h>
	30	#include <video/videomode.h>
	31
	32	#include <drm/bridge/analogix_dp.h>
	33
	34	#include "rockchip_drm_drv.h"
8f0ac5c4	35	#include "rockchip_drm_psr.h"
9e32e16e YY	36	#include "rockchip_drm_vop.h"
9e32e16e YY	37
d9c900b0 YY	38	#define RK3288_GRF_SOC_CON6 0x25c
d9c900b0 YY	39	#define RK3288_EDP_LCDC_SEL BIT(5)
82872e42 YY	40	#define RK3399_GRF_SOC_CON20 0x6250
82872e42 YY	41	#define RK3399_EDP_LCDC_SEL BIT(5)
d9c900b0 YY	42
	43	#define HIWORD_UPDATE(val, mask) (val \| (mask) << 16)
	44
8f0ac5c4 YY	45	#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
8f0ac5c4 YY	46
9e32e16e YY	47	#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
9e32e16e YY	48
d9c900b0 YY	49	/**
	50	* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
	51	* @lcdsel_grf_reg: grf register offset of lcdc select
	52	* @lcdsel_big: reg value of selecting vop big for eDP
	53	* @lcdsel_lit: reg value of selecting vop little for eDP
	54	* @chip_type: specific chip type
	55	*/
	56	struct rockchip_dp_chip_data {
	57	u32 lcdsel_grf_reg;
	58	u32 lcdsel_big;
	59	u32 lcdsel_lit;
	60	u32 chip_type;
	61	};
9e32e16e YY	62
	63	struct rockchip_dp_device {
	64	struct drm_device *drm_dev;
	65	struct device *dev;
	66	struct drm_encoder encoder;
	67	struct drm_display_mode mode;
	68
	69	struct clk *pclk;
dc1c93be	70	struct clk *grfclk;
9e32e16e YY	71	struct regmap *grf;
	72	struct reset_control *rst;
	73
d761b2df SP	74	struct work_struct psr_work;
d761b2df SP	75	spinlock_t psr_lock;
8f0ac5c4 YY	76	unsigned int psr_state;
8f0ac5c4 YY	77
d9c900b0 YY	78	const struct rockchip_dp_chip_data *data;
d9c900b0 YY	79
9e32e16e YY	80	struct analogix_dp_plat_data plat_data;
	81	};
	82
8f0ac5c4 YY	83	static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
	84	{
	85	struct rockchip_dp_device *dp = to_dp(encoder);
d761b2df	86	unsigned long flags;
8f0ac5c4 YY	87
	88	dev_dbg(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
	89
d761b2df	90	spin_lock_irqsave(&dp->psr_lock, flags);
8f0ac5c4 YY	91	if (enabled)
	92	dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
	93	else
	94	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
	95
d761b2df SP	96	schedule_work(&dp->psr_work);
d761b2df SP	97	spin_unlock_irqrestore(&dp->psr_lock, flags);
8f0ac5c4 YY	98	}
	99
	100	static void analogix_dp_psr_work(struct work_struct *work)
	101	{
	102	struct rockchip_dp_device *dp =
d761b2df	103	container_of(work, typeof(*dp), psr_work);
8f0ac5c4 YY	104	struct drm_crtc *crtc = dp->encoder.crtc;
	105	int psr_state = dp->psr_state;
	106	int vact_end;
	107	int ret;
d761b2df	108	unsigned long flags;
8f0ac5c4 YY	109
	110	if (!crtc)
	111	return;
	112
	113	vact_end = crtc->mode.vtotal - crtc->mode.vsync_start + crtc->mode.vdisplay;
	114
	115	ret = rockchip_drm_wait_line_flag(dp->encoder.crtc, vact_end,
	116	PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
	117	if (ret) {
	118	dev_err(dp->dev, "line flag interrupt did not arrive\n");
	119	return;
	120	}
	121
d761b2df	122	spin_lock_irqsave(&dp->psr_lock, flags);
8f0ac5c4 YY	123	if (psr_state == EDP_VSC_PSR_STATE_ACTIVE)
	124	analogix_dp_enable_psr(dp->dev);
	125	else
	126	analogix_dp_disable_psr(dp->dev);
d761b2df	127	spin_unlock_irqrestore(&dp->psr_lock, flags);
8f0ac5c4 YY	128	}
8f0ac5c4 YY	129
9e32e16e YY	130	static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
	131	{
	132	reset_control_assert(dp->rst);
	133	usleep_range(10, 20);
	134	reset_control_deassert(dp->rst);
	135
	136	return 0;
	137	}
	138
	139	static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
	140	{
	141	struct rockchip_dp_device *dp = to_dp(plat_data);
	142	int ret;
	143
d761b2df SP	144	cancel_work_sync(&dp->psr_work);
d761b2df SP	145
9e32e16e YY	146	ret = clk_prepare_enable(dp->pclk);
	147	if (ret < 0) {
	148	dev_err(dp->dev, "failed to enable pclk %d\n", ret);
	149	return ret;
	150	}
	151
	152	ret = rockchip_dp_pre_init(dp);
	153	if (ret < 0) {
	154	dev_err(dp->dev, "failed to dp pre init %d\n", ret);
3694c5c3	155	clk_disable_unprepare(dp->pclk);
9e32e16e YY	156	return ret;
	157	}
	158
	159	return 0;
	160	}
	161
	162	static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
	163	{
	164	struct rockchip_dp_device *dp = to_dp(plat_data);
	165
	166	clk_disable_unprepare(dp->pclk);
	167
	168	return 0;
	169	}
	170
db8a9aed YY	171	static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
	172	struct drm_connector *connector)
	173	{
	174	struct drm_display_info *di = &connector->display_info;
	175	/* VOP couldn't output YUV video format for eDP rightly */
	176	u32 mask = DRM_COLOR_FORMAT_YCRCB444 \| DRM_COLOR_FORMAT_YCRCB422;
	177
	178	if ((di->color_formats & mask)) {
	179	DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
	180	di->color_formats &= ~mask;
	181	di->color_formats \|= DRM_COLOR_FORMAT_RGB444;
	182	di->bpc = 8;
	183	}
	184
	185	return 0;
	186	}
	187
9e32e16e YY	188	static bool
	189	rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
	190	const struct drm_display_mode *mode,
	191	struct drm_display_mode *adjusted_mode)
	192	{
	193	/* do nothing */
	194	return true;
	195	}
	196
	197	static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
	198	struct drm_display_mode *mode,
	199	struct drm_display_mode *adjusted)
	200	{
	201	/* do nothing */
	202	}
	203
	204	static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
	205	{
	206	struct rockchip_dp_device *dp = to_dp(encoder);
	207	int ret;
	208	u32 val;
	209
9e32e16e YY	210	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
	211	if (ret < 0)
	212	return;
	213
	214	if (ret)
d9c900b0	215	val = dp->data->lcdsel_lit;
9e32e16e	216	else
d9c900b0	217	val = dp->data->lcdsel_big;
9e32e16e YY	218
	219	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
	220
dc1c93be YY	221	ret = clk_prepare_enable(dp->grfclk);
	222	if (ret < 0) {
	223	dev_err(dp->dev, "failed to enable grfclk %d\n", ret);
9e32e16e YY	224	return;
9e32e16e YY	225	}
dc1c93be YY	226
	227	ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	228	if (ret != 0)
	229	dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
	230
	231	clk_disable_unprepare(dp->grfclk);
9e32e16e YY	232	}
	233
	234	static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
	235	{
	236	/* do nothing */
	237	}
	238
4e257d9e MY	239	static int
	240	rockchip_dp_drm_encoder_atomic_check(struct drm_encoder *encoder,
	241	struct drm_crtc_state *crtc_state,
	242	struct drm_connector_state *conn_state)
	243	{
	244	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
82872e42 YY	245	struct rockchip_dp_device *dp = to_dp(encoder);
82872e42 YY	246	int ret;
4e257d9e MY	247
4e257d9e MY	248	/*
d698f0eb YY	249	* The hardware IC designed that VOP must output the RGB10 video
	250	* format to eDP controller, and if eDP panel only support RGB8,
	251	* then eDP controller should cut down the video data, not via VOP
	252	* controller, that's why we need to hardcode the VOP output mode
	253	* to RGA10 here.
4e257d9e	254	*/
82872e42	255
4e257d9e MY	256	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
4e257d9e MY	257	s->output_type = DRM_MODE_CONNECTOR_eDP;
82872e42 YY	258	if (dp->data->chip_type == RK3399_EDP) {
	259	/*
	260	* For RK3399, VOP Lit must code the out mode to RGB888,
	261	* VOP Big must code the out mode to RGB10.
	262	*/
	263	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node,
	264	encoder);
	265	if (ret > 0)
	266	s->output_mode = ROCKCHIP_OUT_MODE_P888;
	267	}
4e257d9e MY	268
	269	return 0;
	270	}
	271
9e32e16e YY	272	static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
	273	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
	274	.mode_set = rockchip_dp_drm_encoder_mode_set,
	275	.enable = rockchip_dp_drm_encoder_enable,
	276	.disable = rockchip_dp_drm_encoder_nop,
4e257d9e	277	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
9e32e16e YY	278	};
	279
	280	static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
	281	{
	282	drm_encoder_cleanup(encoder);
	283	}
	284
	285	static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
	286	.destroy = rockchip_dp_drm_encoder_destroy,
	287	};
	288
	289	static int rockchip_dp_init(struct rockchip_dp_device *dp)
	290	{
	291	struct device *dev = dp->dev;
	292	struct device_node *np = dev->of_node;
	293	int ret;
	294
	295	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
	296	if (IS_ERR(dp->grf)) {
	297	dev_err(dev, "failed to get rockchip,grf property\n");
	298	return PTR_ERR(dp->grf);
	299	}
	300
dc1c93be YY	301	dp->grfclk = devm_clk_get(dev, "grf");
	302	if (PTR_ERR(dp->grfclk) == -ENOENT) {
	303	dp->grfclk = NULL;
	304	} else if (PTR_ERR(dp->grfclk) == -EPROBE_DEFER) {
	305	return -EPROBE_DEFER;
	306	} else if (IS_ERR(dp->grfclk)) {
	307	dev_err(dev, "failed to get grf clock\n");
	308	return PTR_ERR(dp->grfclk);
	309	}
	310
9e32e16e YY	311	dp->pclk = devm_clk_get(dev, "pclk");
	312	if (IS_ERR(dp->pclk)) {
	313	dev_err(dev, "failed to get pclk property\n");
	314	return PTR_ERR(dp->pclk);
	315	}
	316
	317	dp->rst = devm_reset_control_get(dev, "dp");
	318	if (IS_ERR(dp->rst)) {
	319	dev_err(dev, "failed to get dp reset control\n");
	320	return PTR_ERR(dp->rst);
	321	}
	322
	323	ret = clk_prepare_enable(dp->pclk);
	324	if (ret < 0) {
	325	dev_err(dp->dev, "failed to enable pclk %d\n", ret);
	326	return ret;
	327	}
	328
	329	ret = rockchip_dp_pre_init(dp);
	330	if (ret < 0) {
	331	dev_err(dp->dev, "failed to pre init %d\n", ret);
3694c5c3	332	clk_disable_unprepare(dp->pclk);
9e32e16e YY	333	return ret;
	334	}
	335
	336	return 0;
	337	}
	338
	339	static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
	340	{
	341	struct drm_encoder *encoder = &dp->encoder;
	342	struct drm_device *drm_dev = dp->drm_dev;
	343	struct device *dev = dp->dev;
	344	int ret;
	345
	346	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
	347	dev->of_node);
	348	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
	349
	350	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
	351	DRM_MODE_ENCODER_TMDS, NULL);
	352	if (ret) {
	353	DRM_ERROR("failed to initialize encoder with drm\n");
	354	return ret;
	355	}
	356
	357	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
	358
	359	return 0;
	360	}
	361
	362	static int rockchip_dp_bind(struct device dev, struct device master,
	363	void *data)
	364	{
	365	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
d9c900b0	366	const struct rockchip_dp_chip_data *dp_data;
9e32e16e YY	367	struct drm_device *drm_dev = data;
	368	int ret;
	369
	370	/*
	371	* Just like the probe function said, we don't need the
	372	* device drvrate anymore, we should leave the charge to
	373	* analogix dp driver, set the device drvdata to NULL.
	374	*/
	375	dev_set_drvdata(dev, NULL);
	376
d9c900b0 YY	377	dp_data = of_device_get_match_data(dev);
	378	if (!dp_data)
	379	return -ENODEV;
	380
9e32e16e YY	381	ret = rockchip_dp_init(dp);
	382	if (ret < 0)
	383	return ret;
	384
d9c900b0	385	dp->data = dp_data;
9e32e16e YY	386	dp->drm_dev = drm_dev;
	387
	388	ret = rockchip_dp_drm_create_encoder(dp);
	389	if (ret) {
	390	DRM_ERROR("failed to create drm encoder\n");
	391	return ret;
	392	}
	393
	394	dp->plat_data.encoder = &dp->encoder;
	395
d9c900b0	396	dp->plat_data.dev_type = dp->data->chip_type;
9e32e16e YY	397	dp->plat_data.power_on = rockchip_dp_poweron;
9e32e16e YY	398	dp->plat_data.power_off = rockchip_dp_powerdown;
db8a9aed	399	dp->plat_data.get_modes = rockchip_dp_get_modes;
9e32e16e	400
d761b2df	401	spin_lock_init(&dp->psr_lock);
8f0ac5c4	402	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
d761b2df	403	INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
8f0ac5c4 YY	404
	405	rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
	406
9e32e16e YY	407	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
	408	}
	409
	410	static void rockchip_dp_unbind(struct device dev, struct device master,
	411	void *data)
	412	{
8f0ac5c4 YY	413	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	414
	415	rockchip_drm_psr_unregister(&dp->encoder);
	416
9e32e16e YY	417	return analogix_dp_unbind(dev, master, data);
	418	}
	419
	420	static const struct component_ops rockchip_dp_component_ops = {
	421	.bind = rockchip_dp_bind,
	422	.unbind = rockchip_dp_unbind,
	423	};
	424
	425	static int rockchip_dp_probe(struct platform_device *pdev)
	426	{
	427	struct device *dev = &pdev->dev;
	428	struct device_node panel_node, port, *endpoint;
eb87c91c	429	struct drm_panel *panel = NULL;
9e32e16e	430	struct rockchip_dp_device *dp;
9e32e16e YY	431
9e32e16e YY	432	port = of_graph_get_port_by_id(dev->of_node, 1);
eb87c91c YY	433	if (port) {
	434	endpoint = of_get_child_by_name(port, "endpoint");
	435	of_node_put(port);
	436	if (!endpoint) {
	437	dev_err(dev, "no output endpoint found\n");
	438	return -EINVAL;
	439	}
	440
	441	panel_node = of_graph_get_remote_port_parent(endpoint);
	442	of_node_put(endpoint);
	443	if (!panel_node) {
	444	dev_err(dev, "no output node found\n");
	445	return -EINVAL;
	446	}
	447
	448	panel = of_drm_find_panel(panel_node);
9e32e16e	449	of_node_put(panel_node);
80826339	450	if (!panel)
eb87c91c	451	return -EPROBE_DEFER;
9e32e16e YY	452	}
9e32e16e YY	453
9e32e16e YY	454	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
	455	if (!dp)
	456	return -ENOMEM;
	457
	458	dp->dev = dev;
	459
	460	dp->plat_data.panel = panel;
	461
	462	/*
	463	* We just use the drvdata until driver run into component
	464	* add function, and then we would set drvdata to null, so
	465	* that analogix dp driver could take charge of the drvdata.
	466	*/
	467	platform_set_drvdata(pdev, dp);
	468
	469	return component_add(dev, &rockchip_dp_component_ops);
	470	}
	471
	472	static int rockchip_dp_remove(struct platform_device *pdev)
	473	{
	474	component_del(&pdev->dev, &rockchip_dp_component_ops);
	475
	476	return 0;
	477	}
	478
fe64ba5c	479	static const struct dev_pm_ops rockchip_dp_pm_ops = {
9e32e16e	480	#ifdef CONFIG_PM_SLEEP
fe64ba5c TV	481	.suspend = analogix_dp_suspend,
fe64ba5c TV	482	.resume_early = analogix_dp_resume,
9e32e16e	483	#endif
9e32e16e YY	484	};
9e32e16e YY	485
82872e42 YY	486	static const struct rockchip_dp_chip_data rk3399_edp = {
	487	.lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
	488	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
	489	.lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
	490	.chip_type = RK3399_EDP,
	491	};
	492
d9c900b0 YY	493	static const struct rockchip_dp_chip_data rk3288_dp = {
	494	.lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
	495	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
	496	.lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
	497	.chip_type = RK3288_DP,
	498	};
	499
9e32e16e	500	static const struct of_device_id rockchip_dp_dt_ids[] = {
d9c900b0	501	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
82872e42	502	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
9e32e16e YY	503	{}
	504	};
	505	MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
	506
	507	static struct platform_driver rockchip_dp_driver = {
	508	.probe = rockchip_dp_probe,
	509	.remove = rockchip_dp_remove,
	510	.driver = {
	511	.name = "rockchip-dp",
9e32e16e YY	512	.pm = &rockchip_dp_pm_ops,
	513	.of_match_table = of_match_ptr(rockchip_dp_dt_ids),
	514	},
	515	};
	516
	517	module_platform_driver(rockchip_dp_driver);
	518
	519	MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
	520	MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
	521	MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
	522	MODULE_LICENSE("GPL v2");