[deliverable/linux.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.h

/*
 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
 * Author:Mark Yao <mark.yao@rock-chips.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _ROCKCHIP_DRM_VOP_H
#define _ROCKCHIP_DRM_VOP_H

enum vop_data_format {
	VOP_FMT_ARGB8888 = 0,
	VOP_FMT_RGB888,
	VOP_FMT_RGB565,
	VOP_FMT_YUV420SP = 4,
	VOP_FMT_YUV422SP,
	VOP_FMT_YUV444SP,
};

struct vop_reg_data {
	uint32_t offset;
	uint32_t value;
};

struct vop_reg {
	uint32_t offset;
	uint32_t shift;
	uint32_t mask;
	bool write_mask;
};

struct vop_ctrl {
	struct vop_reg standby;
	struct vop_reg data_blank;
	struct vop_reg gate_en;
	struct vop_reg mmu_en;
	struct vop_reg rgb_en;
	struct vop_reg edp_en;
	struct vop_reg hdmi_en;
	struct vop_reg mipi_en;
	struct vop_reg out_mode;
	struct vop_reg dither_down;
	struct vop_reg dither_up;
	struct vop_reg pin_pol;
	struct vop_reg rgb_pin_pol;
	struct vop_reg hdmi_pin_pol;
	struct vop_reg edp_pin_pol;
	struct vop_reg mipi_pin_pol;

	struct vop_reg htotal_pw;
	struct vop_reg hact_st_end;
	struct vop_reg vtotal_pw;
	struct vop_reg vact_st_end;
	struct vop_reg hpost_st_end;
	struct vop_reg vpost_st_end;

	struct vop_reg line_flag_num[2];

	struct vop_reg cfg_done;
};

struct vop_intr {
	const int *intrs;
	uint32_t nintrs;
	struct vop_reg enable;
	struct vop_reg clear;
	struct vop_reg status;
};

struct vop_scl_extension {
	struct vop_reg cbcr_vsd_mode;
	struct vop_reg cbcr_vsu_mode;
	struct vop_reg cbcr_hsd_mode;
	struct vop_reg cbcr_ver_scl_mode;
	struct vop_reg cbcr_hor_scl_mode;
	struct vop_reg yrgb_vsd_mode;
	struct vop_reg yrgb_vsu_mode;
	struct vop_reg yrgb_hsd_mode;
	struct vop_reg yrgb_ver_scl_mode;
	struct vop_reg yrgb_hor_scl_mode;
	struct vop_reg line_load_mode;
	struct vop_reg cbcr_axi_gather_num;
	struct vop_reg yrgb_axi_gather_num;
	struct vop_reg vsd_cbcr_gt2;
	struct vop_reg vsd_cbcr_gt4;
	struct vop_reg vsd_yrgb_gt2;
	struct vop_reg vsd_yrgb_gt4;
	struct vop_reg bic_coe_sel;
	struct vop_reg cbcr_axi_gather_en;
	struct vop_reg yrgb_axi_gather_en;
	struct vop_reg lb_mode;
};

struct vop_scl_regs {
	const struct vop_scl_extension *ext;

	struct vop_reg scale_yrgb_x;
	struct vop_reg scale_yrgb_y;
	struct vop_reg scale_cbcr_x;
	struct vop_reg scale_cbcr_y;
};

struct vop_win_phy {
	const struct vop_scl_regs *scl;
	const uint32_t *data_formats;
	uint32_t nformats;

	struct vop_reg enable;
	struct vop_reg format;
	struct vop_reg rb_swap;
	struct vop_reg act_info;
	struct vop_reg dsp_info;
	struct vop_reg dsp_st;
	struct vop_reg yrgb_mst;
	struct vop_reg uv_mst;
	struct vop_reg yrgb_vir;
	struct vop_reg uv_vir;

	struct vop_reg dst_alpha_ctl;
	struct vop_reg src_alpha_ctl;
};

struct vop_win_data {
	uint32_t base;
	const struct vop_win_phy *phy;
	enum drm_plane_type type;
};

struct vop_data {
	const struct vop_reg_data *init_table;
	unsigned int table_size;
	const struct vop_ctrl *ctrl;
	const struct vop_intr *intr;
	const struct vop_win_data *win;
	unsigned int win_size;
};

/* interrupt define */
#define DSP_HOLD_VALID_INTR		(1 << 0)
#define FS_INTR				(1 << 1)
#define LINE_FLAG_INTR			(1 << 2)
#define BUS_ERROR_INTR			(1 << 3)

#define INTR_MASK			(DSP_HOLD_VALID_INTR | FS_INTR | \
					 LINE_FLAG_INTR | BUS_ERROR_INTR)

#define DSP_HOLD_VALID_INTR_EN(x)	((x) << 4)
#define FS_INTR_EN(x)			((x) << 5)
#define LINE_FLAG_INTR_EN(x)		((x) << 6)
#define BUS_ERROR_INTR_EN(x)		((x) << 7)
#define DSP_HOLD_VALID_INTR_MASK	(1 << 4)
#define FS_INTR_MASK			(1 << 5)
#define LINE_FLAG_INTR_MASK		(1 << 6)
#define BUS_ERROR_INTR_MASK		(1 << 7)

#define INTR_CLR_SHIFT			8
#define DSP_HOLD_VALID_INTR_CLR		(1 << (INTR_CLR_SHIFT + 0))
#define FS_INTR_CLR			(1 << (INTR_CLR_SHIFT + 1))
#define LINE_FLAG_INTR_CLR		(1 << (INTR_CLR_SHIFT + 2))
#define BUS_ERROR_INTR_CLR		(1 << (INTR_CLR_SHIFT + 3))

#define DSP_LINE_NUM(x)			(((x) & 0x1fff) << 12)
#define DSP_LINE_NUM_MASK		(0x1fff << 12)

/* src alpha ctrl define */
#define SRC_FADING_VALUE(x)		(((x) & 0xff) << 24)
#define SRC_GLOBAL_ALPHA(x)		(((x) & 0xff) << 16)
#define SRC_FACTOR_M0(x)		(((x) & 0x7) << 6)
#define SRC_ALPHA_CAL_M0(x)		(((x) & 0x1) << 5)
#define SRC_BLEND_M0(x)			(((x) & 0x3) << 3)
#define SRC_ALPHA_M0(x)			(((x) & 0x1) << 2)
#define SRC_COLOR_M0(x)			(((x) & 0x1) << 1)
#define SRC_ALPHA_EN(x)			(((x) & 0x1) << 0)
/* dst alpha ctrl define */
#define DST_FACTOR_M0(x)		(((x) & 0x7) << 6)

/*
 * display output interface supported by rockchip lcdc
 */
#define ROCKCHIP_OUT_MODE_P888	0
#define ROCKCHIP_OUT_MODE_P666	1
#define ROCKCHIP_OUT_MODE_P565	2
/* for use special outface */
#define ROCKCHIP_OUT_MODE_AAAA	15

enum alpha_mode {
	ALPHA_STRAIGHT,
	ALPHA_INVERSE,
};

enum global_blend_mode {
	ALPHA_GLOBAL,
	ALPHA_PER_PIX,
	ALPHA_PER_PIX_GLOBAL,
};

enum alpha_cal_mode {
	ALPHA_SATURATION,
	ALPHA_NO_SATURATION,
};

enum color_mode {
	ALPHA_SRC_PRE_MUL,
	ALPHA_SRC_NO_PRE_MUL,
};

enum factor_mode {
	ALPHA_ZERO,
	ALPHA_ONE,
	ALPHA_SRC,
	ALPHA_SRC_INVERSE,
	ALPHA_SRC_GLOBAL,
};

enum scale_mode {
	SCALE_NONE = 0x0,
	SCALE_UP   = 0x1,
	SCALE_DOWN = 0x2
};

enum lb_mode {
	LB_YUV_3840X5 = 0x0,
	LB_YUV_2560X8 = 0x1,
	LB_RGB_3840X2 = 0x2,
	LB_RGB_2560X4 = 0x3,
	LB_RGB_1920X5 = 0x4,
	LB_RGB_1280X8 = 0x5
};

enum sacle_up_mode {
	SCALE_UP_BIL = 0x0,
	SCALE_UP_BIC = 0x1
};

enum scale_down_mode {
	SCALE_DOWN_BIL = 0x0,
	SCALE_DOWN_AVG = 0x1
};

#define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
#define SCL_FT_DEFAULT_FIXPOINT_SHIFT	12
#define SCL_MAX_VSKIPLINES		4
#define MIN_SCL_FT_AFTER_VSKIP		1

static inline uint16_t scl_cal_scale(int src, int dst, int shift)
{
	return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
}

static inline uint16_t scl_cal_scale2(int src, int dst)
{
	return ((src - 1) << 12) / (dst - 1);
}

#define GET_SCL_FT_BILI_DN(src, dst)	scl_cal_scale(src, dst, 12)
#define GET_SCL_FT_BILI_UP(src, dst)	scl_cal_scale(src, dst, 16)
#define GET_SCL_FT_BIC(src, dst)	scl_cal_scale(src, dst, 16)

static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
					     int vskiplines)
{
	int act_height;

	act_height = (src_h + vskiplines - 1) / vskiplines;

	return GET_SCL_FT_BILI_DN(act_height, dst_h);
}

static inline enum scale_mode scl_get_scl_mode(int src, int dst)
{
	if (src < dst)
		return SCALE_UP;
	else if (src > dst)
		return SCALE_DOWN;

	return SCALE_NONE;
}

static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
{
	uint32_t vskiplines;

	for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
		if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
			break;

	return vskiplines;
}

static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
{
	int lb_mode;

	if (width > 2560)
		lb_mode = LB_RGB_3840X2;
	else if (width > 1920)
		lb_mode = LB_RGB_2560X4;
	else if (!is_yuv)
		lb_mode = LB_RGB_1920X5;
	else if (width > 1280)
		lb_mode = LB_YUV_3840X5;
	else
		lb_mode = LB_YUV_2560X8;

	return lb_mode;
}

extern const struct component_ops vop_component_ops;
#endif /* _ROCKCHIP_DRM_VOP_H */
Commit	Line	Data
2048e328 MY	1	/*
	2	* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
	3	* Author:Mark Yao <mark.yao@rock-chips.com>
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#ifndef _ROCKCHIP_DRM_VOP_H
	16	#define _ROCKCHIP_DRM_VOP_H
	17
a67719d1 MY	18	enum vop_data_format {
	19	VOP_FMT_ARGB8888 = 0,
	20	VOP_FMT_RGB888,
	21	VOP_FMT_RGB565,
	22	VOP_FMT_YUV420SP = 4,
	23	VOP_FMT_YUV422SP,
	24	VOP_FMT_YUV444SP,
	25	};
	26
	27	struct vop_reg_data {
	28	uint32_t offset;
	29	uint32_t value;
	30	};
	31
	32	struct vop_reg {
	33	uint32_t offset;
	34	uint32_t shift;
	35	uint32_t mask;
d49463ec	36	bool write_mask;
a67719d1 MY	37	};
	38
	39	struct vop_ctrl {
	40	struct vop_reg standby;
	41	struct vop_reg data_blank;
	42	struct vop_reg gate_en;
	43	struct vop_reg mmu_en;
	44	struct vop_reg rgb_en;
	45	struct vop_reg edp_en;
	46	struct vop_reg hdmi_en;
	47	struct vop_reg mipi_en;
	48	struct vop_reg out_mode;
	49	struct vop_reg dither_down;
	50	struct vop_reg dither_up;
	51	struct vop_reg pin_pol;
0a63bfd0 MY	52	struct vop_reg rgb_pin_pol;
	53	struct vop_reg hdmi_pin_pol;
	54	struct vop_reg edp_pin_pol;
	55	struct vop_reg mipi_pin_pol;
a67719d1 MY	56
	57	struct vop_reg htotal_pw;
	58	struct vop_reg hact_st_end;
	59	struct vop_reg vtotal_pw;
	60	struct vop_reg vact_st_end;
	61	struct vop_reg hpost_st_end;
	62	struct vop_reg vpost_st_end;
	63
69c34e41 YY	64	struct vop_reg line_flag_num[2];
69c34e41 YY	65
a67719d1 MY	66	struct vop_reg cfg_done;
	67	};
	68
	69	struct vop_intr {
	70	const int *intrs;
	71	uint32_t nintrs;
	72	struct vop_reg enable;
	73	struct vop_reg clear;
	74	struct vop_reg status;
	75	};
1194fffb MY	76
1194fffb MY	77	struct vop_scl_extension {
a67719d1 MY	78	struct vop_reg cbcr_vsd_mode;
	79	struct vop_reg cbcr_vsu_mode;
	80	struct vop_reg cbcr_hsd_mode;
	81	struct vop_reg cbcr_ver_scl_mode;
	82	struct vop_reg cbcr_hor_scl_mode;
	83	struct vop_reg yrgb_vsd_mode;
	84	struct vop_reg yrgb_vsu_mode;
	85	struct vop_reg yrgb_hsd_mode;
	86	struct vop_reg yrgb_ver_scl_mode;
	87	struct vop_reg yrgb_hor_scl_mode;
	88	struct vop_reg line_load_mode;
	89	struct vop_reg cbcr_axi_gather_num;
	90	struct vop_reg yrgb_axi_gather_num;
	91	struct vop_reg vsd_cbcr_gt2;
	92	struct vop_reg vsd_cbcr_gt4;
	93	struct vop_reg vsd_yrgb_gt2;
	94	struct vop_reg vsd_yrgb_gt4;
	95	struct vop_reg bic_coe_sel;
	96	struct vop_reg cbcr_axi_gather_en;
	97	struct vop_reg yrgb_axi_gather_en;
a67719d1	98	struct vop_reg lb_mode;
1194fffb MY	99	};
	100
	101	struct vop_scl_regs {
	102	const struct vop_scl_extension *ext;
	103
a67719d1 MY	104	struct vop_reg scale_yrgb_x;
	105	struct vop_reg scale_yrgb_y;
	106	struct vop_reg scale_cbcr_x;
	107	struct vop_reg scale_cbcr_y;
	108	};
	109
	110	struct vop_win_phy {
	111	const struct vop_scl_regs *scl;
	112	const uint32_t *data_formats;
	113	uint32_t nformats;
	114
	115	struct vop_reg enable;
	116	struct vop_reg format;
	117	struct vop_reg rb_swap;
	118	struct vop_reg act_info;
	119	struct vop_reg dsp_info;
	120	struct vop_reg dsp_st;
	121	struct vop_reg yrgb_mst;
	122	struct vop_reg uv_mst;
	123	struct vop_reg yrgb_vir;
	124	struct vop_reg uv_vir;
	125
	126	struct vop_reg dst_alpha_ctl;
	127	struct vop_reg src_alpha_ctl;
	128	};
	129
	130	struct vop_win_data {
	131	uint32_t base;
	132	const struct vop_win_phy *phy;
	133	enum drm_plane_type type;
	134	};
	135
	136	struct vop_data {
	137	const struct vop_reg_data *init_table;
	138	unsigned int table_size;
	139	const struct vop_ctrl *ctrl;
	140	const struct vop_intr *intr;
	141	const struct vop_win_data *win;
	142	unsigned int win_size;
	143	};
2048e328 MY	144
	145	/* interrupt define */
	146	#define DSP_HOLD_VALID_INTR (1 << 0)
	147	#define FS_INTR (1 << 1)
	148	#define LINE_FLAG_INTR (1 << 2)
	149	#define BUS_ERROR_INTR (1 << 3)
	150
	151	#define INTR_MASK (DSP_HOLD_VALID_INTR \| FS_INTR \| \
	152	LINE_FLAG_INTR \| BUS_ERROR_INTR)
	153
	154	#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
	155	#define FS_INTR_EN(x) ((x) << 5)
	156	#define LINE_FLAG_INTR_EN(x) ((x) << 6)
	157	#define BUS_ERROR_INTR_EN(x) ((x) << 7)
	158	#define DSP_HOLD_VALID_INTR_MASK (1 << 4)
	159	#define FS_INTR_MASK (1 << 5)
	160	#define LINE_FLAG_INTR_MASK (1 << 6)
	161	#define BUS_ERROR_INTR_MASK (1 << 7)
	162
	163	#define INTR_CLR_SHIFT 8
	164	#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
	165	#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
	166	#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
	167	#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
	168
	169	#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
	170	#define DSP_LINE_NUM_MASK (0x1fff << 12)
	171
	172	/* src alpha ctrl define */
	173	#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
	174	#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
	175	#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
	176	#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
	177	#define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
	178	#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
	179	#define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
	180	#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
	181	/* dst alpha ctrl define */
	182	#define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
	183
	184	/*
	185	* display output interface supported by rockchip lcdc
	186	*/
	187	#define ROCKCHIP_OUT_MODE_P888 0
	188	#define ROCKCHIP_OUT_MODE_P666 1
	189	#define ROCKCHIP_OUT_MODE_P565 2
	190	/* for use special outface */
	191	#define ROCKCHIP_OUT_MODE_AAAA 15
	192
	193	enum alpha_mode {
	194	ALPHA_STRAIGHT,
	195	ALPHA_INVERSE,
	196	};
	197
	198	enum global_blend_mode {
	199	ALPHA_GLOBAL,
	200	ALPHA_PER_PIX,
	201	ALPHA_PER_PIX_GLOBAL,
	202	};
	203
	204	enum alpha_cal_mode {
	205	ALPHA_SATURATION,
	206	ALPHA_NO_SATURATION,
	207	};
208
209	enum color_mode {
210	ALPHA_SRC_PRE_MUL,
211	ALPHA_SRC_NO_PRE_MUL,
212	};
213
214	enum factor_mode {
215	ALPHA_ZERO,
216	ALPHA_ONE,
217	ALPHA_SRC,
218	ALPHA_SRC_INVERSE,
219	ALPHA_SRC_GLOBAL,
220	};
221
4c156c21 MY	222	enum scale_mode {
	223	SCALE_NONE = 0x0,
	224	SCALE_UP = 0x1,
	225	SCALE_DOWN = 0x2
	226	};
	227
	228	enum lb_mode {
	229	LB_YUV_3840X5 = 0x0,
	230	LB_YUV_2560X8 = 0x1,
	231	LB_RGB_3840X2 = 0x2,
	232	LB_RGB_2560X4 = 0x3,
	233	LB_RGB_1920X5 = 0x4,
	234	LB_RGB_1280X8 = 0x5
	235	};
	236
	237	enum sacle_up_mode {
	238	SCALE_UP_BIL = 0x0,
	239	SCALE_UP_BIC = 0x1
	240	};
	241
	242	enum scale_down_mode {
	243	SCALE_DOWN_BIL = 0x0,
	244	SCALE_DOWN_AVG = 0x1
	245	};
	246
	247	#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
	248	#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
	249	#define SCL_MAX_VSKIPLINES 4
	250	#define MIN_SCL_FT_AFTER_VSKIP 1
	251
	252	static inline uint16_t scl_cal_scale(int src, int dst, int shift)
	253	{
	254	return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
	255	}
	256
1194fffb MY	257	static inline uint16_t scl_cal_scale2(int src, int dst)
	258	{
	259	return ((src - 1) << 12) / (dst - 1);
	260	}
	261
4c156c21 MY	262	#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
	263	#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
	264	#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
	265
	266	static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
	267	int vskiplines)
	268	{
	269	int act_height;
	270
	271	act_height = (src_h + vskiplines - 1) / vskiplines;
	272
	273	return GET_SCL_FT_BILI_DN(act_height, dst_h);
	274	}
	275
	276	static inline enum scale_mode scl_get_scl_mode(int src, int dst)
	277	{
	278	if (src < dst)
	279	return SCALE_UP;
	280	else if (src > dst)
	281	return SCALE_DOWN;
	282
	283	return SCALE_NONE;
	284	}
	285
	286	static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
	287	{
	288	uint32_t vskiplines;
	289
	290	for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
	291	if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
	292	break;
	293
	294	return vskiplines;
	295	}
	296
	297	static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
	298	{
	299	int lb_mode;
	300
	301	if (width > 2560)
	302	lb_mode = LB_RGB_3840X2;
	303	else if (width > 1920)
	304	lb_mode = LB_RGB_2560X4;
	305	else if (!is_yuv)
	306	lb_mode = LB_RGB_1920X5;
	307	else if (width > 1280)
	308	lb_mode = LB_YUV_3840X5;
	309	else
	310	lb_mode = LB_YUV_2560X8;
	311
	312	return lb_mode;
	313	}
	314
a67719d1	315	extern const struct component_ops vop_component_ops;
2048e328	316	#endif /* _ROCKCHIP_DRM_VOP_H */