[deliverable/linux.git] / drivers / gpu / drm / rockchip / rockchip_vop_reg.c

/*
 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
 * Author:Mark Yao <mark.yao@rock-chips.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <drm/drmP.h>

#include <linux/kernel.h>
#include <linux/component.h>

#include "rockchip_drm_vop.h"
#include "rockchip_vop_reg.h"

#define VOP_REG(off, _mask, s) \
		{.offset = off, \
		 .mask = _mask, \
		 .shift = s, \
		 .write_mask = false,}

#define VOP_REG_MASK(off, _mask, s) \
		{.offset = off, \
		 .mask = _mask, \
		 .shift = s, \
		 .write_mask = true,}

static const uint32_t formats_win_full[] = {
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_RGB888,
	DRM_FORMAT_BGR888,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_BGR565,
	DRM_FORMAT_NV12,
	DRM_FORMAT_NV16,
	DRM_FORMAT_NV24,
};

static const uint32_t formats_win_lite[] = {
	DRM_FORMAT_XRGB8888,
	DRM_FORMAT_ARGB8888,
	DRM_FORMAT_XBGR8888,
	DRM_FORMAT_ABGR8888,
	DRM_FORMAT_RGB888,
	DRM_FORMAT_BGR888,
	DRM_FORMAT_RGB565,
	DRM_FORMAT_BGR565,
};

static const struct vop_scl_regs rk3036_win_scl = {
	.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
	.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
	.scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
	.scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
};

static const struct vop_win_phy rk3036_win0_data = {
	.scl = &rk3036_win_scl,
	.data_formats = formats_win_full,
	.nformats = ARRAY_SIZE(formats_win_full),
	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
	.act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
	.dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
	.dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
	.yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
	.uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
	.yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
	.uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
};

static const struct vop_win_phy rk3036_win1_data = {
	.data_formats = formats_win_lite,
	.nformats = ARRAY_SIZE(formats_win_lite),
	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
	.act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
	.dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
	.dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
	.yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
	.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
};

static const struct vop_win_data rk3036_vop_win_data[] = {
	{ .base = 0x00, .phy = &rk3036_win0_data,
	  .type = DRM_PLANE_TYPE_PRIMARY },
	{ .base = 0x00, .phy = &rk3036_win1_data,
	  .type = DRM_PLANE_TYPE_CURSOR },
};

static const int rk3036_vop_intrs[] = {
	DSP_HOLD_VALID_INTR,
	FS_INTR,
	LINE_FLAG_INTR,
	BUS_ERROR_INTR,
};

static const struct vop_intr rk3036_intr = {
	.intrs = rk3036_vop_intrs,
	.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
	.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
	.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
	.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
};

static const struct vop_ctrl rk3036_ctrl_data = {
	.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
	.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
	.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
	.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
	.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
	.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
	.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
	.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
	.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
};

static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
	{RK3036_DSP_CTRL1, 0x00000000},
};

static const struct vop_data rk3036_vop = {
	.init_table = rk3036_vop_init_reg_table,
	.table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
	.ctrl = &rk3036_ctrl_data,
	.intr = &rk3036_intr,
	.win = rk3036_vop_win_data,
	.win_size = ARRAY_SIZE(rk3036_vop_win_data),
};

static const struct vop_scl_extension rk3288_win_full_scl_ext = {
	.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
	.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
	.cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
	.cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
	.cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
	.yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
	.yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
	.yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
	.yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
	.yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
	.line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
	.cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
	.yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
	.vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
	.vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
	.vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
	.vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
	.bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
	.cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
	.yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
	.lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
};

static const struct vop_scl_regs rk3288_win_full_scl = {
	.ext = &rk3288_win_full_scl_ext,
	.scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
	.scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
	.scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
	.scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
};

static const struct vop_win_phy rk3288_win01_data = {
	.scl = &rk3288_win_full_scl,
	.data_formats = formats_win_full,
	.nformats = ARRAY_SIZE(formats_win_full),
	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
};

static const struct vop_win_phy rk3288_win23_data = {
	.data_formats = formats_win_lite,
	.nformats = ARRAY_SIZE(formats_win_lite),
	.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
	.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
	.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
	.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
	.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
	.yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
	.yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
	.src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
	.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
};

static const struct vop_ctrl rk3288_ctrl_data = {
	.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
	.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
	.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
	.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
	.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
	.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
	.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
	.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
	.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
	.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
	.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
	.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
	.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
	.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
	.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
	.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
	.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
	.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
	.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
	.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
};

static const struct vop_reg_data rk3288_init_reg_table[] = {
	{RK3288_SYS_CTRL, 0x00c00000},
	{RK3288_DSP_CTRL0, 0x00000000},
	{RK3288_WIN0_CTRL0, 0x00000080},
	{RK3288_WIN1_CTRL0, 0x00000080},
	/* TODO: Win2/3 support multiple area function, but we haven't found
	 * a suitable way to use it yet, so let's just use them as other windows
	 * with only area 0 enabled.
	 */
	{RK3288_WIN2_CTRL0, 0x00000010},
	{RK3288_WIN3_CTRL0, 0x00000010},
};

/*
 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 * special support to get alpha blending working.  For now, just use overlay
 * window 3 for the drm cursor.
 *
 */
static const struct vop_win_data rk3288_vop_win_data[] = {
	{ .base = 0x00, .phy = &rk3288_win01_data,
	  .type = DRM_PLANE_TYPE_PRIMARY },
	{ .base = 0x40, .phy = &rk3288_win01_data,
	  .type = DRM_PLANE_TYPE_OVERLAY },
	{ .base = 0x00, .phy = &rk3288_win23_data,
	  .type = DRM_PLANE_TYPE_OVERLAY },
	{ .base = 0x50, .phy = &rk3288_win23_data,
	  .type = DRM_PLANE_TYPE_CURSOR },
};

static const int rk3288_vop_intrs[] = {
	DSP_HOLD_VALID_INTR,
	FS_INTR,
	LINE_FLAG_INTR,
	BUS_ERROR_INTR,
};

static const struct vop_intr rk3288_vop_intr = {
	.intrs = rk3288_vop_intrs,
	.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
	.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
	.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
	.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
};

static const struct vop_data rk3288_vop = {
	.init_table = rk3288_init_reg_table,
	.table_size = ARRAY_SIZE(rk3288_init_reg_table),
	.intr = &rk3288_vop_intr,
	.ctrl = &rk3288_ctrl_data,
	.win = rk3288_vop_win_data,
	.win_size = ARRAY_SIZE(rk3288_vop_win_data),
};

static const struct vop_ctrl rk3399_ctrl_data = {
	.standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
	.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
	.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
	.hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
	.edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
	.mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
	.dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
	.dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
	.data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
	.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
	.rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
	.hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
	.edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
	.mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
	.htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
	.hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
	.vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
	.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
	.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
	.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
	.line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0),
	.line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16),
	.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
};

static const int rk3399_vop_intrs[] = {
	FS_INTR,
	0, 0,
	LINE_FLAG_INTR,
	0,
	BUS_ERROR_INTR,
	0, 0, 0, 0, 0, 0, 0,
	DSP_HOLD_VALID_INTR,
};

static const struct vop_intr rk3399_vop_intr = {
	.intrs = rk3399_vop_intrs,
	.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
	.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
	.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
	.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
};

static const struct vop_reg_data rk3399_init_reg_table[] = {
	{RK3399_SYS_CTRL, 0x2000f800},
	{RK3399_DSP_CTRL0, 0x00000000},
	{RK3399_WIN0_CTRL0, 0x00000080},
	{RK3399_WIN1_CTRL0, 0x00000080},
	/* TODO: Win2/3 support multiple area function, but we haven't found
	 * a suitable way to use it yet, so let's just use them as other windows
	 * with only area 0 enabled.
	 */
	{RK3399_WIN2_CTRL0, 0x00000010},
	{RK3399_WIN3_CTRL0, 0x00000010},
};

static const struct vop_data rk3399_vop_big = {
	.init_table = rk3399_init_reg_table,
	.table_size = ARRAY_SIZE(rk3399_init_reg_table),
	.intr = &rk3399_vop_intr,
	.ctrl = &rk3399_ctrl_data,
	/*
	 * rk3399 vop big windows register layout is same as rk3288.
	 */
	.win = rk3288_vop_win_data,
	.win_size = ARRAY_SIZE(rk3288_vop_win_data),
};

static const struct vop_win_data rk3399_vop_lit_win_data[] = {
	{ .base = 0x00, .phy = &rk3288_win01_data,
	  .type = DRM_PLANE_TYPE_PRIMARY },
	{ .base = 0x00, .phy = &rk3288_win23_data,
	  .type = DRM_PLANE_TYPE_CURSOR},
};

static const struct vop_data rk3399_vop_lit = {
	.init_table = rk3399_init_reg_table,
	.table_size = ARRAY_SIZE(rk3399_init_reg_table),
	.intr = &rk3399_vop_intr,
	.ctrl = &rk3399_ctrl_data,
	/*
	 * rk3399 vop lit windows register layout is same as rk3288,
	 * but cut off the win1 and win3 windows.
	 */
	.win = rk3399_vop_lit_win_data,
	.win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
};

static const struct of_device_id vop_driver_dt_match[] = {
	{ .compatible = "rockchip,rk3036-vop",
	  .data = &rk3036_vop },
	{ .compatible = "rockchip,rk3288-vop",
	  .data = &rk3288_vop },
	{ .compatible = "rockchip,rk3399-vop-big",
	  .data = &rk3399_vop_big },
	{ .compatible = "rockchip,rk3399-vop-lit",
	  .data = &rk3399_vop_lit },
	{},
};
MODULE_DEVICE_TABLE(of, vop_driver_dt_match);

static int vop_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;

	if (!dev->of_node) {
		dev_err(dev, "can't find vop devices\n");
		return -ENODEV;
	}

	return component_add(dev, &vop_component_ops);
}

static int vop_remove(struct platform_device *pdev)
{
	component_del(&pdev->dev, &vop_component_ops);

	return 0;
}

static struct platform_driver vop_platform_driver = {
	.probe = vop_probe,
	.remove = vop_remove,
	.driver = {
		.name = "rockchip-vop",
		.of_match_table = of_match_ptr(vop_driver_dt_match),
	},
};

module_platform_driver(vop_platform_driver);

MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
a67719d1 MY	1	/*
	2	* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
	3	* Author:Mark Yao <mark.yao@rock-chips.com>
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
	15	#include <drm/drmP.h>
	16
	17	#include <linux/kernel.h>
	18	#include <linux/component.h>
	19
	20	#include "rockchip_drm_vop.h"
	21	#include "rockchip_vop_reg.h"
	22
	23	#define VOP_REG(off, _mask, s) \
	24	{.offset = off, \
	25	.mask = _mask, \
d49463ec MY	26	.shift = s, \
	27	.write_mask = false,}
	28
	29	#define VOP_REG_MASK(off, _mask, s) \
	30	{.offset = off, \
	31	.mask = _mask, \
	32	.shift = s, \
	33	.write_mask = true,}
a67719d1	34
f7673453	35	static const uint32_t formats_win_full[] = {
a67719d1 MY	36	DRM_FORMAT_XRGB8888,
	37	DRM_FORMAT_ARGB8888,
	38	DRM_FORMAT_XBGR8888,
	39	DRM_FORMAT_ABGR8888,
	40	DRM_FORMAT_RGB888,
	41	DRM_FORMAT_BGR888,
	42	DRM_FORMAT_RGB565,
	43	DRM_FORMAT_BGR565,
	44	DRM_FORMAT_NV12,
	45	DRM_FORMAT_NV16,
	46	DRM_FORMAT_NV24,
	47	};
	48
f7673453	49	static const uint32_t formats_win_lite[] = {
a67719d1 MY	50	DRM_FORMAT_XRGB8888,
	51	DRM_FORMAT_ARGB8888,
	52	DRM_FORMAT_XBGR8888,
	53	DRM_FORMAT_ABGR8888,
	54	DRM_FORMAT_RGB888,
	55	DRM_FORMAT_BGR888,
	56	DRM_FORMAT_RGB565,
	57	DRM_FORMAT_BGR565,
	58	};
	59
b51502ad MY	60	static const struct vop_scl_regs rk3036_win_scl = {
	61	.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
	62	.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
	63	.scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
	64	.scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
	65	};
	66
	67	static const struct vop_win_phy rk3036_win0_data = {
	68	.scl = &rk3036_win_scl,
	69	.data_formats = formats_win_full,
	70	.nformats = ARRAY_SIZE(formats_win_full),
	71	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
	72	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
	73	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
	74	.act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
	75	.dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
	76	.dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
	77	.yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
	78	.uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
	79	.yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
	80	.uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
	81	};
	82
	83	static const struct vop_win_phy rk3036_win1_data = {
	84	.data_formats = formats_win_lite,
	85	.nformats = ARRAY_SIZE(formats_win_lite),
	86	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
	87	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
	88	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
	89	.act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
	90	.dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
	91	.dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
	92	.yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
	93	.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
	94	};
	95
	96	static const struct vop_win_data rk3036_vop_win_data[] = {
	97	{ .base = 0x00, .phy = &rk3036_win0_data,
	98	.type = DRM_PLANE_TYPE_PRIMARY },
	99	{ .base = 0x00, .phy = &rk3036_win1_data,
	100	.type = DRM_PLANE_TYPE_CURSOR },
	101	};
	102
	103	static const int rk3036_vop_intrs[] = {
	104	DSP_HOLD_VALID_INTR,
	105	FS_INTR,
	106	LINE_FLAG_INTR,
	107	BUS_ERROR_INTR,
	108	};
	109
	110	static const struct vop_intr rk3036_intr = {
	111	.intrs = rk3036_vop_intrs,
	112	.nintrs = ARRAY_SIZE(rk3036_vop_intrs),
	113	.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
	114	.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
	115	.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
	116	};
	117
	118	static const struct vop_ctrl rk3036_ctrl_data = {
	119	.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
	120	.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
	121	.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
	122	.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
	123	.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
124	.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
125	.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
69c34e41	126	.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
b51502ad MY	127	.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
	128	};
	129
	130	static const struct vop_reg_data rk3036_vop_init_reg_table[] = {
	131	{RK3036_DSP_CTRL1, 0x00000000},
	132	};
	133
	134	static const struct vop_data rk3036_vop = {
	135	.init_table = rk3036_vop_init_reg_table,
	136	.table_size = ARRAY_SIZE(rk3036_vop_init_reg_table),
	137	.ctrl = &rk3036_ctrl_data,
	138	.intr = &rk3036_intr,
	139	.win = rk3036_vop_win_data,
	140	.win_size = ARRAY_SIZE(rk3036_vop_win_data),
	141	};
	142
f7673453 MY	143	static const struct vop_scl_extension rk3288_win_full_scl_ext = {
	144	.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
	145	.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
	146	.cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
	147	.cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
	148	.cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
	149	.yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
	150	.yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
	151	.yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
	152	.yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
	153	.yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
	154	.line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
	155	.cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
	156	.yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
	157	.vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
	158	.vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
	159	.vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
	160	.vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
	161	.bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
	162	.cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
	163	.yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
	164	.lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
	165	};
	166
	167	static const struct vop_scl_regs rk3288_win_full_scl = {
	168	.ext = &rk3288_win_full_scl_ext,
	169	.scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
	170	.scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
	171	.scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
	172	.scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
	173	};
	174
	175	static const struct vop_win_phy rk3288_win01_data = {
	176	.scl = &rk3288_win_full_scl,
	177	.data_formats = formats_win_full,
	178	.nformats = ARRAY_SIZE(formats_win_full),
	179	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
	180	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
	181	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
	182	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
	183	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
	184	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
	185	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
	186	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
	187	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
	188	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
	189	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
	190	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
	191	};
	192
	193	static const struct vop_win_phy rk3288_win23_data = {
	194	.data_formats = formats_win_lite,
	195	.nformats = ARRAY_SIZE(formats_win_lite),
	196	.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
	197	.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
	198	.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
	199	.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
	200	.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
	201	.yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
	202	.yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
	203	.src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
	204	.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
	205	};
	206
207	static const struct vop_ctrl rk3288_ctrl_data = {
208	.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
209	.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
210	.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
211	.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
212	.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
213	.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
214	.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
215	.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
216	.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
217	.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
218	.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
219	.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
220	.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
221	.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
222	.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
223	.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
224	.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
225	.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
69c34e41	226	.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
f7673453 MY	227	.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
	228	};
	229
	230	static const struct vop_reg_data rk3288_init_reg_table[] = {
	231	{RK3288_SYS_CTRL, 0x00c00000},
	232	{RK3288_DSP_CTRL0, 0x00000000},
	233	{RK3288_WIN0_CTRL0, 0x00000080},
	234	{RK3288_WIN1_CTRL0, 0x00000080},
a67719d1 MY	235	/* TODO: Win2/3 support multiple area function, but we haven't found
	236	* a suitable way to use it yet, so let's just use them as other windows
	237	* with only area 0 enabled.
	238	*/
f7673453 MY	239	{RK3288_WIN2_CTRL0, 0x00000010},
f7673453 MY	240	{RK3288_WIN3_CTRL0, 0x00000010},
a67719d1 MY	241	};
	242
	243	/*
	244	* Note: rk3288 has a dedicated 'cursor' window, however, that window requires
	245	* special support to get alpha blending working. For now, just use overlay
	246	* window 3 for the drm cursor.
	247	*
	248	*/
	249	static const struct vop_win_data rk3288_vop_win_data[] = {
f7673453 MY	250	{ .base = 0x00, .phy = &rk3288_win01_data,
	251	.type = DRM_PLANE_TYPE_PRIMARY },
	252	{ .base = 0x40, .phy = &rk3288_win01_data,
	253	.type = DRM_PLANE_TYPE_OVERLAY },
	254	{ .base = 0x00, .phy = &rk3288_win23_data,
	255	.type = DRM_PLANE_TYPE_OVERLAY },
	256	{ .base = 0x50, .phy = &rk3288_win23_data,
	257	.type = DRM_PLANE_TYPE_CURSOR },
a67719d1 MY	258	};
	259
	260	static const int rk3288_vop_intrs[] = {
	261	DSP_HOLD_VALID_INTR,
	262	FS_INTR,
	263	LINE_FLAG_INTR,
	264	BUS_ERROR_INTR,
	265	};
	266
	267	static const struct vop_intr rk3288_vop_intr = {
	268	.intrs = rk3288_vop_intrs,
	269	.nintrs = ARRAY_SIZE(rk3288_vop_intrs),
f7673453 MY	270	.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
	271	.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
	272	.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
a67719d1 MY	273	};
	274
	275	static const struct vop_data rk3288_vop = {
f7673453 MY	276	.init_table = rk3288_init_reg_table,
f7673453 MY	277	.table_size = ARRAY_SIZE(rk3288_init_reg_table),
a67719d1	278	.intr = &rk3288_vop_intr,
f7673453	279	.ctrl = &rk3288_ctrl_data,
a67719d1 MY	280	.win = rk3288_vop_win_data,
	281	.win_size = ARRAY_SIZE(rk3288_vop_win_data),
	282	};
	283
0a63bfd0 MY	284	static const struct vop_ctrl rk3399_ctrl_data = {
	285	.standby = VOP_REG(RK3399_SYS_CTRL, 0x1, 22),
	286	.gate_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 23),
	287	.rgb_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 12),
	288	.hdmi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 13),
	289	.edp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 14),
	290	.mipi_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 15),
	291	.dither_down = VOP_REG(RK3399_DSP_CTRL1, 0xf, 1),
	292	.dither_up = VOP_REG(RK3399_DSP_CTRL1, 0x1, 6),
	293	.data_blank = VOP_REG(RK3399_DSP_CTRL0, 0x1, 19),
	294	.out_mode = VOP_REG(RK3399_DSP_CTRL0, 0xf, 0),
	295	.rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16),
	296	.hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20),
	297	.edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24),
	298	.mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28),
	299	.htotal_pw = VOP_REG(RK3399_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
	300	.hact_st_end = VOP_REG(RK3399_DSP_HACT_ST_END, 0x1fff1fff, 0),
	301	.vtotal_pw = VOP_REG(RK3399_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
	302	.vact_st_end = VOP_REG(RK3399_DSP_VACT_ST_END, 0x1fff1fff, 0),
	303	.hpost_st_end = VOP_REG(RK3399_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
	304	.vpost_st_end = VOP_REG(RK3399_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
69c34e41 YY	305	.line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0),
69c34e41 YY	306	.line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16),
0a63bfd0	307	.cfg_done = VOP_REG_MASK(RK3399_REG_CFG_DONE, 0x1, 0),
f7673453 MY	308	};
f7673453 MY	309
0a63bfd0	310	static const int rk3399_vop_intrs[] = {
f7673453	311	FS_INTR,
0a63bfd0	312	0, 0,
f7673453	313	LINE_FLAG_INTR,
0a63bfd0	314	0,
f7673453	315	BUS_ERROR_INTR,
0a63bfd0 MY	316	0, 0, 0, 0, 0, 0, 0,
0a63bfd0 MY	317	DSP_HOLD_VALID_INTR,
f7673453 MY	318	};
f7673453 MY	319
0a63bfd0 MY	320	static const struct vop_intr rk3399_vop_intr = {
	321	.intrs = rk3399_vop_intrs,
	322	.nintrs = ARRAY_SIZE(rk3399_vop_intrs),
	323	.status = VOP_REG_MASK(RK3399_INTR_STATUS0, 0xffff, 0),
	324	.enable = VOP_REG_MASK(RK3399_INTR_EN0, 0xffff, 0),
	325	.clear = VOP_REG_MASK(RK3399_INTR_CLEAR0, 0xffff, 0),
f7673453 MY	326	};
f7673453 MY	327
0a63bfd0 MY	328	static const struct vop_reg_data rk3399_init_reg_table[] = {
	329	{RK3399_SYS_CTRL, 0x2000f800},
	330	{RK3399_DSP_CTRL0, 0x00000000},
	331	{RK3399_WIN0_CTRL0, 0x00000080},
	332	{RK3399_WIN1_CTRL0, 0x00000080},
	333	/* TODO: Win2/3 support multiple area function, but we haven't found
	334	* a suitable way to use it yet, so let's just use them as other windows
	335	* with only area 0 enabled.
	336	*/
	337	{RK3399_WIN2_CTRL0, 0x00000010},
	338	{RK3399_WIN3_CTRL0, 0x00000010},
f7673453 MY	339	};
f7673453 MY	340
0a63bfd0 MY	341	static const struct vop_data rk3399_vop_big = {
	342	.init_table = rk3399_init_reg_table,
	343	.table_size = ARRAY_SIZE(rk3399_init_reg_table),
	344	.intr = &rk3399_vop_intr,
	345	.ctrl = &rk3399_ctrl_data,
	346	/*
	347	* rk3399 vop big windows register layout is same as rk3288.
	348	*/
	349	.win = rk3288_vop_win_data,
	350	.win_size = ARRAY_SIZE(rk3288_vop_win_data),
f7673453 MY	351	};
f7673453 MY	352
0a63bfd0 MY	353	static const struct vop_win_data rk3399_vop_lit_win_data[] = {
	354	{ .base = 0x00, .phy = &rk3288_win01_data,
	355	.type = DRM_PLANE_TYPE_PRIMARY },
	356	{ .base = 0x00, .phy = &rk3288_win23_data,
	357	.type = DRM_PLANE_TYPE_CURSOR},
	358	};
	359
	360	static const struct vop_data rk3399_vop_lit = {
	361	.init_table = rk3399_init_reg_table,
	362	.table_size = ARRAY_SIZE(rk3399_init_reg_table),
	363	.intr = &rk3399_vop_intr,
	364	.ctrl = &rk3399_ctrl_data,
	365	/*
	366	* rk3399 vop lit windows register layout is same as rk3288,
	367	* but cut off the win1 and win3 windows.
	368	*/
	369	.win = rk3399_vop_lit_win_data,
	370	.win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
f7673453 MY	371	};
f7673453 MY	372
a67719d1	373	static const struct of_device_id vop_driver_dt_match[] = {
f7673453 MY	374	{ .compatible = "rockchip,rk3036-vop",
f7673453 MY	375	.data = &rk3036_vop },
b51502ad MY	376	{ .compatible = "rockchip,rk3288-vop",
b51502ad MY	377	.data = &rk3288_vop },
0a63bfd0 MY	378	{ .compatible = "rockchip,rk3399-vop-big",
	379	.data = &rk3399_vop_big },
	380	{ .compatible = "rockchip,rk3399-vop-lit",
	381	.data = &rk3399_vop_lit },
a67719d1 MY	382	{},
	383	};
	384	MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
	385
	386	static int vop_probe(struct platform_device *pdev)
	387	{
	388	struct device *dev = &pdev->dev;
	389
	390	if (!dev->of_node) {
	391	dev_err(dev, "can't find vop devices\n");
	392	return -ENODEV;
	393	}
	394
	395	return component_add(dev, &vop_component_ops);
	396	}
	397
	398	static int vop_remove(struct platform_device *pdev)
	399	{
	400	component_del(&pdev->dev, &vop_component_ops);
	401
	402	return 0;
	403	}
	404
8ff490ae	405	static struct platform_driver vop_platform_driver = {
a67719d1 MY	406	.probe = vop_probe,
	407	.remove = vop_remove,
	408	.driver = {
	409	.name = "rockchip-vop",
a67719d1 MY	410	.of_match_table = of_match_ptr(vop_driver_dt_match),
	411	},
	412	};
	413
	414	module_platform_driver(vop_platform_driver);
	415
	416	MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
	417	MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
	418	MODULE_LICENSE("GPL v2");