projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a67719d1 MY |
1 | /* |
| 2 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd | |
| 3 | * Author:Mark Yao <mark.yao@rock-chips.com> | |
| 4 | * | |
| 5 | * This software is licensed under the terms of the GNU General Public | |
| 6 | * License version 2, as published by the Free Software Foundation, and | |
| 7 | * may be copied, distributed, and modified under those terms. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, | |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 12 | * GNU General Public License for more details. | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef _ROCKCHIP_VOP_REG_H | |
| 16 | #define _ROCKCHIP_VOP_REG_H | |
| 17 | ||
| f7673453 MY |
18 | /* rk3288 register definition */ |
| 19 | #define RK3288_REG_CFG_DONE 0x0000 | |
| 20 | #define RK3288_VERSION_INFO 0x0004 | |
| 21 | #define RK3288_SYS_CTRL 0x0008 | |
| 22 | #define RK3288_SYS_CTRL1 0x000c | |
| 23 | #define RK3288_DSP_CTRL0 0x0010 | |
| 24 | #define RK3288_DSP_CTRL1 0x0014 | |
| 25 | #define RK3288_DSP_BG 0x0018 | |
| 26 | #define RK3288_MCU_CTRL 0x001c | |
| 27 | #define RK3288_INTR_CTRL0 0x0020 | |
| 28 | #define RK3288_INTR_CTRL1 0x0024 | |
| 29 | #define RK3288_WIN0_CTRL0 0x0030 | |
| 30 | #define RK3288_WIN0_CTRL1 0x0034 | |
| 31 | #define RK3288_WIN0_COLOR_KEY 0x0038 | |
| 32 | #define RK3288_WIN0_VIR 0x003c | |
| 33 | #define RK3288_WIN0_YRGB_MST 0x0040 | |
| 34 | #define RK3288_WIN0_CBR_MST 0x0044 | |
| 35 | #define RK3288_WIN0_ACT_INFO 0x0048 | |
| 36 | #define RK3288_WIN0_DSP_INFO 0x004c | |
| 37 | #define RK3288_WIN0_DSP_ST 0x0050 | |
| 38 | #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054 | |
| 39 | #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058 | |
| 40 | #define RK3288_WIN0_SCL_OFFSET 0x005c | |
| 41 | #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 | |
| 42 | #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 | |
| 43 | #define RK3288_WIN0_FADING_CTRL 0x0068 | |
| 44 | ||
| a67719d1 | 45 | /* win1 register */ |
| f7673453 MY |
46 | #define RK3288_WIN1_CTRL0 0x0070 |
| 47 | #define RK3288_WIN1_CTRL1 0x0074 | |
| 48 | #define RK3288_WIN1_COLOR_KEY 0x0078 | |
| 49 | #define RK3288_WIN1_VIR 0x007c | |
| 50 | #define RK3288_WIN1_YRGB_MST 0x0080 | |
| 51 | #define RK3288_WIN1_CBR_MST 0x0084 | |
| 52 | #define RK3288_WIN1_ACT_INFO 0x0088 | |
| 53 | #define RK3288_WIN1_DSP_INFO 0x008c | |
| 54 | #define RK3288_WIN1_DSP_ST 0x0090 | |
| 55 | #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094 | |
| 56 | #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098 | |
| 57 | #define RK3288_WIN1_SCL_OFFSET 0x009c | |
| 58 | #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0 | |
| 59 | #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4 | |
| 60 | #define RK3288_WIN1_FADING_CTRL 0x00a8 | |
| a67719d1 | 61 | /* win2 register */ |
| f7673453 MY |
62 | #define RK3288_WIN2_CTRL0 0x00b0 |
| 63 | #define RK3288_WIN2_CTRL1 0x00b4 | |
| 64 | #define RK3288_WIN2_VIR0_1 0x00b8 | |
| 65 | #define RK3288_WIN2_VIR2_3 0x00bc | |
| 66 | #define RK3288_WIN2_MST0 0x00c0 | |
| 67 | #define RK3288_WIN2_DSP_INFO0 0x00c4 | |
| 68 | #define RK3288_WIN2_DSP_ST0 0x00c8 | |
| 69 | #define RK3288_WIN2_COLOR_KEY 0x00cc | |
| 70 | #define RK3288_WIN2_MST1 0x00d0 | |
| 71 | #define RK3288_WIN2_DSP_INFO1 0x00d4 | |
| 72 | #define RK3288_WIN2_DSP_ST1 0x00d8 | |
| 73 | #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc | |
| 74 | #define RK3288_WIN2_MST2 0x00e0 | |
| 75 | #define RK3288_WIN2_DSP_INFO2 0x00e4 | |
| 76 | #define RK3288_WIN2_DSP_ST2 0x00e8 | |
| 77 | #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec | |
| 78 | #define RK3288_WIN2_MST3 0x00f0 | |
| 79 | #define RK3288_WIN2_DSP_INFO3 0x00f4 | |
| 80 | #define RK3288_WIN2_DSP_ST3 0x00f8 | |
| 81 | #define RK3288_WIN2_FADING_CTRL 0x00fc | |
| a67719d1 | 82 | /* win3 register */ |
| f7673453 MY |
83 | #define RK3288_WIN3_CTRL0 0x0100 |
| 84 | #define RK3288_WIN3_CTRL1 0x0104 | |
| 85 | #define RK3288_WIN3_VIR0_1 0x0108 | |
| 86 | #define RK3288_WIN3_VIR2_3 0x010c | |
| 87 | #define RK3288_WIN3_MST0 0x0110 | |
| 88 | #define RK3288_WIN3_DSP_INFO0 0x0114 | |
| 89 | #define RK3288_WIN3_DSP_ST0 0x0118 | |
| 90 | #define RK3288_WIN3_COLOR_KEY 0x011c | |
| 91 | #define RK3288_WIN3_MST1 0x0120 | |
| 92 | #define RK3288_WIN3_DSP_INFO1 0x0124 | |
| 93 | #define RK3288_WIN3_DSP_ST1 0x0128 | |
| 94 | #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c | |
| 95 | #define RK3288_WIN3_MST2 0x0130 | |
| 96 | #define RK3288_WIN3_DSP_INFO2 0x0134 | |
| 97 | #define RK3288_WIN3_DSP_ST2 0x0138 | |
| 98 | #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c | |
| 99 | #define RK3288_WIN3_MST3 0x0140 | |
| 100 | #define RK3288_WIN3_DSP_INFO3 0x0144 | |
| 101 | #define RK3288_WIN3_DSP_ST3 0x0148 | |
| 102 | #define RK3288_WIN3_FADING_CTRL 0x014c | |
| a67719d1 | 103 | /* hwc register */ |
| f7673453 MY |
104 | #define RK3288_HWC_CTRL0 0x0150 |
| 105 | #define RK3288_HWC_CTRL1 0x0154 | |
| 106 | #define RK3288_HWC_MST 0x0158 | |
| 107 | #define RK3288_HWC_DSP_ST 0x015c | |
| 108 | #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160 | |
| 109 | #define RK3288_HWC_DST_ALPHA_CTRL 0x0164 | |
| 110 | #define RK3288_HWC_FADING_CTRL 0x0168 | |
| a67719d1 | 111 | /* post process register */ |
| f7673453 MY |
112 | #define RK3288_POST_DSP_HACT_INFO 0x0170 |
| 113 | #define RK3288_POST_DSP_VACT_INFO 0x0174 | |
| 114 | #define RK3288_POST_SCL_FACTOR_YRGB 0x0178 | |
| 115 | #define RK3288_POST_SCL_CTRL 0x0180 | |
| 116 | #define RK3288_POST_DSP_VACT_INFO_F1 0x0184 | |
| 117 | #define RK3288_DSP_HTOTAL_HS_END 0x0188 | |
| 118 | #define RK3288_DSP_HACT_ST_END 0x018c | |
| 119 | #define RK3288_DSP_VTOTAL_VS_END 0x0190 | |
| 120 | #define RK3288_DSP_VACT_ST_END 0x0194 | |
| 121 | #define RK3288_DSP_VS_ST_END_F1 0x0198 | |
| 122 | #define RK3288_DSP_VACT_ST_END_F1 0x019c | |
| a67719d1 MY |
123 | /* register definition end */ |
| 124 | ||
| f7673453 MY |
125 | /* rk3036 register definition */ |
| 126 | #define RK3036_SYS_CTRL 0x00 | |
| 127 | #define RK3036_DSP_CTRL0 0x04 | |
| 128 | #define RK3036_DSP_CTRL1 0x08 | |
| 129 | #define RK3036_INT_STATUS 0x10 | |
| 130 | #define RK3036_ALPHA_CTRL 0x14 | |
| 131 | #define RK3036_WIN0_COLOR_KEY 0x18 | |
| 132 | #define RK3036_WIN1_COLOR_KEY 0x1c | |
| 133 | #define RK3036_WIN0_YRGB_MST 0x20 | |
| 134 | #define RK3036_WIN0_CBR_MST 0x24 | |
| 135 | #define RK3036_WIN1_VIR 0x28 | |
| 136 | #define RK3036_AXI_BUS_CTRL 0x2c | |
| 137 | #define RK3036_WIN0_VIR 0x30 | |
| 138 | #define RK3036_WIN0_ACT_INFO 0x34 | |
| 139 | #define RK3036_WIN0_DSP_INFO 0x38 | |
| 140 | #define RK3036_WIN0_DSP_ST 0x3c | |
| 141 | #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 | |
| 142 | #define RK3036_WIN0_SCL_FACTOR_CBR 0x44 | |
| 143 | #define RK3036_WIN0_SCL_OFFSET 0x48 | |
| 144 | #define RK3036_HWC_MST 0x58 | |
| 145 | #define RK3036_HWC_DSP_ST 0x5c | |
| 146 | #define RK3036_DSP_HTOTAL_HS_END 0x6c | |
| 147 | #define RK3036_DSP_HACT_ST_END 0x70 | |
| 148 | #define RK3036_DSP_VTOTAL_VS_END 0x74 | |
| 149 | #define RK3036_DSP_VACT_ST_END 0x78 | |
| 150 | #define RK3036_DSP_VS_ST_END_F1 0x7c | |
| 151 | #define RK3036_DSP_VACT_ST_END_F1 0x80 | |
| 152 | #define RK3036_GATHER_TRANSFER 0x84 | |
| 153 | #define RK3036_VERSION_INFO 0x94 | |
| 154 | #define RK3036_REG_CFG_DONE 0x90 | |
| 155 | #define RK3036_WIN1_MST 0xa0 | |
| 156 | #define RK3036_WIN1_ACT_INFO 0xb4 | |
| 157 | #define RK3036_WIN1_DSP_INFO 0xb8 | |
| 158 | #define RK3036_WIN1_DSP_ST 0xbc | |
| 159 | #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 | |
| 160 | #define RK3036_WIN1_SCL_OFFSET 0xc8 | |
| 161 | #define RK3036_BCSH_CTRL 0xd0 | |
| 162 | #define RK3036_BCSH_COLOR_BAR 0xd4 | |
| 163 | #define RK3036_BCSH_BCS 0xd8 | |
| 164 | #define RK3036_BCSH_H 0xdc | |
| 165 | #define RK3036_WIN1_LUT_ADDR 0x400 | |
| 166 | #define RK3036_HWC_LUT_ADDR 0x800 | |
| 167 | /* rk3036 register definition end */ | |
| 168 | ||
| 0a63bfd0 MY |
169 | /* rk3399 register definition */ |
| 170 | #define RK3399_REG_CFG_DONE 0x00000 | |
| 171 | #define RK3399_VERSION_INFO 0x00004 | |
| 172 | #define RK3399_SYS_CTRL 0x00008 | |
| 173 | #define RK3399_SYS_CTRL1 0x0000c | |
| 174 | #define RK3399_DSP_CTRL0 0x00010 | |
| 175 | #define RK3399_DSP_CTRL1 0x00014 | |
| 176 | #define RK3399_DSP_BG 0x00018 | |
| 177 | #define RK3399_MCU_CTRL 0x0001c | |
| 178 | #define RK3399_WB_CTRL0 0x00020 | |
| 179 | #define RK3399_WB_CTRL1 0x00024 | |
| 180 | #define RK3399_WB_YRGB_MST 0x00028 | |
| 181 | #define RK3399_WB_CBR_MST 0x0002c | |
| 182 | #define RK3399_WIN0_CTRL0 0x00030 | |
| 183 | #define RK3399_WIN0_CTRL1 0x00034 | |
| 184 | #define RK3399_WIN0_COLOR_KEY 0x00038 | |
| 185 | #define RK3399_WIN0_VIR 0x0003c | |
| 186 | #define RK3399_WIN0_YRGB_MST 0x00040 | |
| 187 | #define RK3399_WIN0_CBR_MST 0x00044 | |
| 188 | #define RK3399_WIN0_ACT_INFO 0x00048 | |
| 189 | #define RK3399_WIN0_DSP_INFO 0x0004c | |
| 190 | #define RK3399_WIN0_DSP_ST 0x00050 | |
| 191 | #define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054 | |
| 192 | #define RK3399_WIN0_SCL_FACTOR_CBR 0x00058 | |
| 193 | #define RK3399_WIN0_SCL_OFFSET 0x0005c | |
| 194 | #define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060 | |
| 195 | #define RK3399_WIN0_DST_ALPHA_CTRL 0x00064 | |
| 196 | #define RK3399_WIN0_FADING_CTRL 0x00068 | |
| 197 | #define RK3399_WIN0_CTRL2 0x0006c | |
| 198 | #define RK3399_WIN1_CTRL0 0x00070 | |
| 199 | #define RK3399_WIN1_CTRL1 0x00074 | |
| 200 | #define RK3399_WIN1_COLOR_KEY 0x00078 | |
| 201 | #define RK3399_WIN1_VIR 0x0007c | |
| 202 | #define RK3399_WIN1_YRGB_MST 0x00080 | |
| 203 | #define RK3399_WIN1_CBR_MST 0x00084 | |
| 204 | #define RK3399_WIN1_ACT_INFO 0x00088 | |
| 205 | #define RK3399_WIN1_DSP_INFO 0x0008c | |
| 206 | #define RK3399_WIN1_DSP_ST 0x00090 | |
| 207 | #define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094 | |
| 208 | #define RK3399_WIN1_SCL_FACTOR_CBR 0x00098 | |
| 209 | #define RK3399_WIN1_SCL_OFFSET 0x0009c | |
| 210 | #define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0 | |
| 211 | #define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4 | |
| 212 | #define RK3399_WIN1_FADING_CTRL 0x000a8 | |
| 213 | #define RK3399_WIN1_CTRL2 0x000ac | |
| 214 | #define RK3399_WIN2_CTRL0 0x000b0 | |
| 215 | #define RK3399_WIN2_CTRL1 0x000b4 | |
| 216 | #define RK3399_WIN2_VIR0_1 0x000b8 | |
| 217 | #define RK3399_WIN2_VIR2_3 0x000bc | |
| 218 | #define RK3399_WIN2_MST0 0x000c0 | |
| 219 | #define RK3399_WIN2_DSP_INFO0 0x000c4 | |
| 220 | #define RK3399_WIN2_DSP_ST0 0x000c8 | |
| 221 | #define RK3399_WIN2_COLOR_KEY 0x000cc | |
| 222 | #define RK3399_WIN2_MST1 0x000d0 | |
| 223 | #define RK3399_WIN2_DSP_INFO1 0x000d4 | |
| 224 | #define RK3399_WIN2_DSP_ST1 0x000d8 | |
| 225 | #define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc | |
| 226 | #define RK3399_WIN2_MST2 0x000e0 | |
| 227 | #define RK3399_WIN2_DSP_INFO2 0x000e4 | |
| 228 | #define RK3399_WIN2_DSP_ST2 0x000e8 | |
| 229 | #define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec | |
| 230 | #define RK3399_WIN2_MST3 0x000f0 | |
| 231 | #define RK3399_WIN2_DSP_INFO3 0x000f4 | |
| 232 | #define RK3399_WIN2_DSP_ST3 0x000f8 | |
| 233 | #define RK3399_WIN2_FADING_CTRL 0x000fc | |
| 234 | #define RK3399_WIN3_CTRL0 0x00100 | |
| 235 | #define RK3399_WIN3_CTRL1 0x00104 | |
| 236 | #define RK3399_WIN3_VIR0_1 0x00108 | |
| 237 | #define RK3399_WIN3_VIR2_3 0x0010c | |
| 238 | #define RK3399_WIN3_MST0 0x00110 | |
| 239 | #define RK3399_WIN3_DSP_INFO0 0x00114 | |
| 240 | #define RK3399_WIN3_DSP_ST0 0x00118 | |
| 241 | #define RK3399_WIN3_COLOR_KEY 0x0011c | |
| 242 | #define RK3399_WIN3_MST1 0x00120 | |
| 243 | #define RK3399_WIN3_DSP_INFO1 0x00124 | |
| 244 | #define RK3399_WIN3_DSP_ST1 0x00128 | |
| 245 | #define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c | |
| 246 | #define RK3399_WIN3_MST2 0x00130 | |
| 247 | #define RK3399_WIN3_DSP_INFO2 0x00134 | |
| 248 | #define RK3399_WIN3_DSP_ST2 0x00138 | |
| 249 | #define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c | |
| 250 | #define RK3399_WIN3_MST3 0x00140 | |
| 251 | #define RK3399_WIN3_DSP_INFO3 0x00144 | |
| 252 | #define RK3399_WIN3_DSP_ST3 0x00148 | |
| 253 | #define RK3399_WIN3_FADING_CTRL 0x0014c | |
| 254 | #define RK3399_HWC_CTRL0 0x00150 | |
| 255 | #define RK3399_HWC_CTRL1 0x00154 | |
| 256 | #define RK3399_HWC_MST 0x00158 | |
| 257 | #define RK3399_HWC_DSP_ST 0x0015c | |
| 258 | #define RK3399_HWC_SRC_ALPHA_CTRL 0x00160 | |
| 259 | #define RK3399_HWC_DST_ALPHA_CTRL 0x00164 | |
| 260 | #define RK3399_HWC_FADING_CTRL 0x00168 | |
| 261 | #define RK3399_HWC_RESERVED1 0x0016c | |
| 262 | #define RK3399_POST_DSP_HACT_INFO 0x00170 | |
| 263 | #define RK3399_POST_DSP_VACT_INFO 0x00174 | |
| 264 | #define RK3399_POST_SCL_FACTOR_YRGB 0x00178 | |
| 265 | #define RK3399_POST_RESERVED 0x0017c | |
| 266 | #define RK3399_POST_SCL_CTRL 0x00180 | |
| 267 | #define RK3399_POST_DSP_VACT_INFO_F1 0x00184 | |
| 268 | #define RK3399_DSP_HTOTAL_HS_END 0x00188 | |
| 269 | #define RK3399_DSP_HACT_ST_END 0x0018c | |
| 270 | #define RK3399_DSP_VTOTAL_VS_END 0x00190 | |
| 271 | #define RK3399_DSP_VACT_ST_END 0x00194 | |
| 272 | #define RK3399_DSP_VS_ST_END_F1 0x00198 | |
| 273 | #define RK3399_DSP_VACT_ST_END_F1 0x0019c | |
| 274 | #define RK3399_PWM_CTRL 0x001a0 | |
| 275 | #define RK3399_PWM_PERIOD_HPR 0x001a4 | |
| 276 | #define RK3399_PWM_DUTY_LPR 0x001a8 | |
| 277 | #define RK3399_PWM_CNT 0x001ac | |
| 278 | #define RK3399_BCSH_COLOR_BAR 0x001b0 | |
| 279 | #define RK3399_BCSH_BCS 0x001b4 | |
| 280 | #define RK3399_BCSH_H 0x001b8 | |
| 281 | #define RK3399_BCSH_CTRL 0x001bc | |
| 282 | #define RK3399_CABC_CTRL0 0x001c0 | |
| 283 | #define RK3399_CABC_CTRL1 0x001c4 | |
| 284 | #define RK3399_CABC_CTRL2 0x001c8 | |
| 285 | #define RK3399_CABC_CTRL3 0x001cc | |
| 286 | #define RK3399_CABC_GAUSS_LINE0_0 0x001d0 | |
| 287 | #define RK3399_CABC_GAUSS_LINE0_1 0x001d4 | |
| 288 | #define RK3399_CABC_GAUSS_LINE1_0 0x001d8 | |
| 289 | #define RK3399_CABC_GAUSS_LINE1_1 0x001dc | |
| 290 | #define RK3399_CABC_GAUSS_LINE2_0 0x001e0 | |
| 291 | #define RK3399_CABC_GAUSS_LINE2_1 0x001e4 | |
| 292 | #define RK3399_FRC_LOWER01_0 0x001e8 | |
| 293 | #define RK3399_FRC_LOWER01_1 0x001ec | |
| 294 | #define RK3399_FRC_LOWER10_0 0x001f0 | |
| 295 | #define RK3399_FRC_LOWER10_1 0x001f4 | |
| 296 | #define RK3399_FRC_LOWER11_0 0x001f8 | |
| 297 | #define RK3399_FRC_LOWER11_1 0x001fc | |
| 298 | #define RK3399_AFBCD0_CTRL 0x00200 | |
| 299 | #define RK3399_AFBCD0_HDR_PTR 0x00204 | |
| 300 | #define RK3399_AFBCD0_PIC_SIZE 0x00208 | |
| 301 | #define RK3399_AFBCD0_STATUS 0x0020c | |
| 302 | #define RK3399_AFBCD1_CTRL 0x00220 | |
| 303 | #define RK3399_AFBCD1_HDR_PTR 0x00224 | |
| 304 | #define RK3399_AFBCD1_PIC_SIZE 0x00228 | |
| 305 | #define RK3399_AFBCD1_STATUS 0x0022c | |
| 306 | #define RK3399_AFBCD2_CTRL 0x00240 | |
| 307 | #define RK3399_AFBCD2_HDR_PTR 0x00244 | |
| 308 | #define RK3399_AFBCD2_PIC_SIZE 0x00248 | |
| 309 | #define RK3399_AFBCD2_STATUS 0x0024c | |
| 310 | #define RK3399_AFBCD3_CTRL 0x00260 | |
| 311 | #define RK3399_AFBCD3_HDR_PTR 0x00264 | |
| 312 | #define RK3399_AFBCD3_PIC_SIZE 0x00268 | |
| 313 | #define RK3399_AFBCD3_STATUS 0x0026c | |
| 314 | #define RK3399_INTR_EN0 0x00280 | |
| 315 | #define RK3399_INTR_CLEAR0 0x00284 | |
| 316 | #define RK3399_INTR_STATUS0 0x00288 | |
| 317 | #define RK3399_INTR_RAW_STATUS0 0x0028c | |
| 318 | #define RK3399_INTR_EN1 0x00290 | |
| 319 | #define RK3399_INTR_CLEAR1 0x00294 | |
| 320 | #define RK3399_INTR_STATUS1 0x00298 | |
| 321 | #define RK3399_INTR_RAW_STATUS1 0x0029c | |
| 322 | #define RK3399_LINE_FLAG 0x002a0 | |
| 323 | #define RK3399_VOP_STATUS 0x002a4 | |
| 324 | #define RK3399_BLANKING_VALUE 0x002a8 | |
| 325 | #define RK3399_MCU_BYPASS_PORT 0x002ac | |
| 326 | #define RK3399_WIN0_DSP_BG 0x002b0 | |
| 327 | #define RK3399_WIN1_DSP_BG 0x002b4 | |
| 328 | #define RK3399_WIN2_DSP_BG 0x002b8 | |
| 329 | #define RK3399_WIN3_DSP_BG 0x002bc | |
| 330 | #define RK3399_YUV2YUV_WIN 0x002c0 | |
| 331 | #define RK3399_YUV2YUV_POST 0x002c4 | |
| 332 | #define RK3399_AUTO_GATING_EN 0x002cc | |
| 333 | #define RK3399_WIN0_CSC_COE 0x003a0 | |
| 334 | #define RK3399_WIN1_CSC_COE 0x003c0 | |
| 335 | #define RK3399_WIN2_CSC_COE 0x003e0 | |
| 336 | #define RK3399_WIN3_CSC_COE 0x00400 | |
| 337 | #define RK3399_HWC_CSC_COE 0x00420 | |
| 338 | #define RK3399_BCSH_R2Y_CSC_COE 0x00440 | |
| 339 | #define RK3399_BCSH_Y2R_CSC_COE 0x00460 | |
| 340 | #define RK3399_POST_YUV2YUV_Y2R_COE 0x00480 | |
| 341 | #define RK3399_POST_YUV2YUV_3X3_COE 0x004a0 | |
| 342 | #define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0 | |
| 343 | #define RK3399_WIN0_YUV2YUV_Y2R 0x004e0 | |
| 344 | #define RK3399_WIN0_YUV2YUV_3X3 0x00500 | |
| 345 | #define RK3399_WIN0_YUV2YUV_R2Y 0x00520 | |
| 346 | #define RK3399_WIN1_YUV2YUV_Y2R 0x00540 | |
| 347 | #define RK3399_WIN1_YUV2YUV_3X3 0x00560 | |
| 348 | #define RK3399_WIN1_YUV2YUV_R2Y 0x00580 | |
| 349 | #define RK3399_WIN2_YUV2YUV_Y2R 0x005a0 | |
| 350 | #define RK3399_WIN2_YUV2YUV_3X3 0x005c0 | |
| 351 | #define RK3399_WIN2_YUV2YUV_R2Y 0x005e0 | |
| 352 | #define RK3399_WIN3_YUV2YUV_Y2R 0x00600 | |
| 353 | #define RK3399_WIN3_YUV2YUV_3X3 0x00620 | |
| 354 | #define RK3399_WIN3_YUV2YUV_R2Y 0x00640 | |
| 355 | #define RK3399_WIN2_LUT_ADDR 0x01000 | |
| 356 | #define RK3399_WIN3_LUT_ADDR 0x01400 | |
| 357 | #define RK3399_HWC_LUT_ADDR 0x01800 | |
| 358 | #define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00 | |
| 359 | #define RK3399_GAMMA_LUT_ADDR 0x02000 | |
| 360 | /* rk3399 register definition end */ | |
| 361 | ||
| a67719d1 | 362 | #endif /* _ROCKCHIP_VOP_REG_H */ |