Merge remote-tracking branch 'vfio/next'
[deliverable/linux.git] / drivers / gpu / drm / tegra / drm.c
CommitLineData
d8f4a9ed
TR
1/*
2 * Copyright (C) 2012 Avionic Design GmbH
d43f81cb 3 * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved.
d8f4a9ed
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4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
776dc384 10#include <linux/host1x.h>
df06b759 11#include <linux/iommu.h>
776dc384 12
1503ca47 13#include <drm/drm_atomic.h>
07866963
TR
14#include <drm/drm_atomic_helper.h>
15
d8f4a9ed 16#include "drm.h"
de2ba664 17#include "gem.h"
d8f4a9ed
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18
19#define DRIVER_NAME "tegra"
20#define DRIVER_DESC "NVIDIA Tegra graphics"
21#define DRIVER_DATE "20120330"
22#define DRIVER_MAJOR 0
23#define DRIVER_MINOR 0
24#define DRIVER_PATCHLEVEL 0
25
08943e6c
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26struct tegra_drm_file {
27 struct list_head contexts;
28};
29
1503ca47
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30static void tegra_atomic_schedule(struct tegra_drm *tegra,
31 struct drm_atomic_state *state)
32{
33 tegra->commit.state = state;
34 schedule_work(&tegra->commit.work);
35}
36
37static void tegra_atomic_complete(struct tegra_drm *tegra,
38 struct drm_atomic_state *state)
39{
40 struct drm_device *drm = tegra->drm;
41
42 /*
43 * Everything below can be run asynchronously without the need to grab
44 * any modeset locks at all under one condition: It must be guaranteed
45 * that the asynchronous work has either been cancelled (if the driver
46 * supports it, which at least requires that the framebuffers get
47 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
48 * before the new state gets committed on the software side with
49 * drm_atomic_helper_swap_state().
50 *
51 * This scheme allows new atomic state updates to be prepared and
52 * checked in parallel to the asynchronous completion of the previous
53 * update. Which is important since compositors need to figure out the
54 * composition of the next frame right after having submitted the
55 * current layout.
56 */
57
1af434a9 58 drm_atomic_helper_commit_modeset_disables(drm, state);
1af434a9 59 drm_atomic_helper_commit_modeset_enables(drm, state);
2b58e98d
LY
60 drm_atomic_helper_commit_planes(drm, state,
61 DRM_PLANE_COMMIT_ACTIVE_ONLY);
1503ca47
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62
63 drm_atomic_helper_wait_for_vblanks(drm, state);
64
65 drm_atomic_helper_cleanup_planes(drm, state);
66 drm_atomic_state_free(state);
67}
68
69static void tegra_atomic_work(struct work_struct *work)
70{
71 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
72 commit.work);
73
74 tegra_atomic_complete(tegra, tegra->commit.state);
75}
76
77static int tegra_atomic_commit(struct drm_device *drm,
2dacdd70 78 struct drm_atomic_state *state, bool nonblock)
1503ca47
TR
79{
80 struct tegra_drm *tegra = drm->dev_private;
81 int err;
82
83 err = drm_atomic_helper_prepare_planes(drm, state);
84 if (err)
85 return err;
86
2dacdd70 87 /* serialize outstanding nonblocking commits */
1503ca47
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88 mutex_lock(&tegra->commit.lock);
89 flush_work(&tegra->commit.work);
90
91 /*
92 * This is the point of no return - everything below never fails except
93 * when the hw goes bonghits. Which means we can commit the new state on
94 * the software side now.
95 */
96
5e84c269 97 drm_atomic_helper_swap_state(state, true);
1503ca47 98
2dacdd70 99 if (nonblock)
1503ca47
TR
100 tegra_atomic_schedule(tegra, state);
101 else
102 tegra_atomic_complete(tegra, state);
103
104 mutex_unlock(&tegra->commit.lock);
105 return 0;
106}
107
f9914214
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108static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
109 .fb_create = tegra_fb_create,
b110ef37 110#ifdef CONFIG_DRM_FBDEV_EMULATION
f9914214
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111 .output_poll_changed = tegra_fb_output_poll_changed,
112#endif
07866963 113 .atomic_check = drm_atomic_helper_check,
1503ca47 114 .atomic_commit = tegra_atomic_commit,
f9914214
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115};
116
776dc384 117static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
692e6d7b 118{
776dc384 119 struct host1x_device *device = to_host1x_device(drm->dev);
386a2a71 120 struct tegra_drm *tegra;
692e6d7b
TB
121 int err;
122
776dc384 123 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
386a2a71 124 if (!tegra)
692e6d7b
TB
125 return -ENOMEM;
126
df06b759 127 if (iommu_present(&platform_bus_type)) {
4553f733
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128 struct iommu_domain_geometry *geometry;
129 u64 start, end;
130
df06b759 131 tegra->domain = iommu_domain_alloc(&platform_bus_type);
bf19b885
DC
132 if (!tegra->domain) {
133 err = -ENOMEM;
df06b759
TR
134 goto free;
135 }
136
4553f733
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137 geometry = &tegra->domain->geometry;
138 start = geometry->aperture_start;
139 end = geometry->aperture_end;
140
d2d8c358
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141 DRM_DEBUG_DRIVER("IOMMU aperture initialized (%#llx-%#llx)\n",
142 start, end);
4553f733 143 drm_mm_init(&tegra->mm, start, end - start + 1);
df06b759
TR
144 }
145
386a2a71
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146 mutex_init(&tegra->clients_lock);
147 INIT_LIST_HEAD(&tegra->clients);
1503ca47
TR
148
149 mutex_init(&tegra->commit.lock);
150 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
151
386a2a71
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152 drm->dev_private = tegra;
153 tegra->drm = drm;
d8f4a9ed
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154
155 drm_mode_config_init(drm);
156
f9914214
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157 drm->mode_config.min_width = 0;
158 drm->mode_config.min_height = 0;
159
160 drm->mode_config.max_width = 4096;
161 drm->mode_config.max_height = 4096;
162
163 drm->mode_config.funcs = &tegra_drm_mode_funcs;
164
e2215321
TR
165 err = tegra_drm_fb_prepare(drm);
166 if (err < 0)
1d1e6fe9 167 goto config;
e2215321
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168
169 drm_kms_helper_poll_init(drm);
170
776dc384 171 err = host1x_device_init(device);
d8f4a9ed 172 if (err < 0)
1d1e6fe9 173 goto fbdev;
d8f4a9ed 174
603f0cc9
TR
175 /*
176 * We don't use the drm_irq_install() helpers provided by the DRM
177 * core, so we need to set this manually in order to allow the
178 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
179 */
4423843c 180 drm->irq_enabled = true;
603f0cc9 181
42e9ce05 182 /* syncpoints are used for full 32-bit hardware VBLANK counters */
42e9ce05
TR
183 drm->max_vblank_count = 0xffffffff;
184
6e5ff998
TR
185 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
186 if (err < 0)
1d1e6fe9 187 goto device;
6e5ff998 188
31930d4d
TR
189 drm_mode_config_reset(drm);
190
d8f4a9ed
TR
191 err = tegra_drm_fb_init(drm);
192 if (err < 0)
1d1e6fe9 193 goto vblank;
d8f4a9ed 194
d8f4a9ed 195 return 0;
1d1e6fe9
TR
196
197vblank:
198 drm_vblank_cleanup(drm);
199device:
200 host1x_device_exit(device);
201fbdev:
202 drm_kms_helper_poll_fini(drm);
203 tegra_drm_fb_free(drm);
204config:
205 drm_mode_config_cleanup(drm);
df06b759
TR
206
207 if (tegra->domain) {
208 iommu_domain_free(tegra->domain);
209 drm_mm_takedown(&tegra->mm);
210 }
211free:
1d1e6fe9
TR
212 kfree(tegra);
213 return err;
d8f4a9ed
TR
214}
215
216static int tegra_drm_unload(struct drm_device *drm)
217{
776dc384 218 struct host1x_device *device = to_host1x_device(drm->dev);
df06b759 219 struct tegra_drm *tegra = drm->dev_private;
776dc384
TR
220 int err;
221
d8f4a9ed
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222 drm_kms_helper_poll_fini(drm);
223 tegra_drm_fb_exit(drm);
f002abc1 224 drm_mode_config_cleanup(drm);
4aa3df71 225 drm_vblank_cleanup(drm);
d8f4a9ed 226
776dc384
TR
227 err = host1x_device_exit(device);
228 if (err < 0)
229 return err;
230
df06b759
TR
231 if (tegra->domain) {
232 iommu_domain_free(tegra->domain);
233 drm_mm_takedown(&tegra->mm);
234 }
235
1053f4dd
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236 kfree(tegra);
237
d8f4a9ed
TR
238 return 0;
239}
240
241static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
242{
08943e6c 243 struct tegra_drm_file *fpriv;
d43f81cb
TB
244
245 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
246 if (!fpriv)
247 return -ENOMEM;
248
249 INIT_LIST_HEAD(&fpriv->contexts);
250 filp->driver_priv = fpriv;
251
d8f4a9ed
TR
252 return 0;
253}
254
c88c3630 255static void tegra_drm_context_free(struct tegra_drm_context *context)
d43f81cb
TB
256{
257 context->client->ops->close_channel(context);
258 kfree(context);
259}
260
d8f4a9ed
TR
261static void tegra_drm_lastclose(struct drm_device *drm)
262{
b110ef37 263#ifdef CONFIG_DRM_FBDEV_EMULATION
386a2a71 264 struct tegra_drm *tegra = drm->dev_private;
d8f4a9ed 265
386a2a71 266 tegra_fbdev_restore_mode(tegra->fbdev);
60c2f709 267#endif
d8f4a9ed
TR
268}
269
c40f0f1a 270static struct host1x_bo *
a8ad0bd8 271host1x_bo_lookup(struct drm_file *file, u32 handle)
c40f0f1a
TR
272{
273 struct drm_gem_object *gem;
274 struct tegra_bo *bo;
275
a8ad0bd8 276 gem = drm_gem_object_lookup(file, handle);
c40f0f1a
TR
277 if (!gem)
278 return NULL;
279
a07cdfe5 280 drm_gem_object_unreference_unlocked(gem);
c40f0f1a
TR
281
282 bo = to_tegra_bo(gem);
283 return &bo->base;
284}
285
961e3bea
TR
286static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
287 struct drm_tegra_reloc __user *src,
288 struct drm_device *drm,
289 struct drm_file *file)
290{
291 u32 cmdbuf, target;
292 int err;
293
294 err = get_user(cmdbuf, &src->cmdbuf.handle);
295 if (err < 0)
296 return err;
297
298 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
299 if (err < 0)
300 return err;
301
302 err = get_user(target, &src->target.handle);
303 if (err < 0)
304 return err;
305
31f40f86 306 err = get_user(dest->target.offset, &src->target.offset);
961e3bea
TR
307 if (err < 0)
308 return err;
309
310 err = get_user(dest->shift, &src->shift);
311 if (err < 0)
312 return err;
313
a8ad0bd8 314 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
961e3bea
TR
315 if (!dest->cmdbuf.bo)
316 return -ENOENT;
317
a8ad0bd8 318 dest->target.bo = host1x_bo_lookup(file, target);
961e3bea
TR
319 if (!dest->target.bo)
320 return -ENOENT;
321
322 return 0;
323}
324
c40f0f1a
TR
325int tegra_drm_submit(struct tegra_drm_context *context,
326 struct drm_tegra_submit *args, struct drm_device *drm,
327 struct drm_file *file)
328{
329 unsigned int num_cmdbufs = args->num_cmdbufs;
330 unsigned int num_relocs = args->num_relocs;
331 unsigned int num_waitchks = args->num_waitchks;
332 struct drm_tegra_cmdbuf __user *cmdbufs =
a7ed68fc 333 (void __user *)(uintptr_t)args->cmdbufs;
c40f0f1a 334 struct drm_tegra_reloc __user *relocs =
a7ed68fc 335 (void __user *)(uintptr_t)args->relocs;
c40f0f1a 336 struct drm_tegra_waitchk __user *waitchks =
a7ed68fc 337 (void __user *)(uintptr_t)args->waitchks;
c40f0f1a
TR
338 struct drm_tegra_syncpt syncpt;
339 struct host1x_job *job;
340 int err;
341
342 /* We don't yet support other than one syncpt_incr struct per submit */
343 if (args->num_syncpts != 1)
344 return -EINVAL;
345
346 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
347 args->num_relocs, args->num_waitchks);
348 if (!job)
349 return -ENOMEM;
350
351 job->num_relocs = args->num_relocs;
352 job->num_waitchk = args->num_waitchks;
353 job->client = (u32)args->context;
354 job->class = context->client->base.class;
355 job->serialize = true;
356
357 while (num_cmdbufs) {
358 struct drm_tegra_cmdbuf cmdbuf;
359 struct host1x_bo *bo;
360
9a991600
DC
361 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
362 err = -EFAULT;
c40f0f1a 363 goto fail;
9a991600 364 }
c40f0f1a 365
a8ad0bd8 366 bo = host1x_bo_lookup(file, cmdbuf.handle);
c40f0f1a
TR
367 if (!bo) {
368 err = -ENOENT;
369 goto fail;
370 }
371
372 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
373 num_cmdbufs--;
374 cmdbufs++;
375 }
376
961e3bea 377 /* copy and resolve relocations from submit */
c40f0f1a 378 while (num_relocs--) {
961e3bea
TR
379 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
380 &relocs[num_relocs], drm,
381 file);
382 if (err < 0)
c40f0f1a 383 goto fail;
c40f0f1a
TR
384 }
385
9a991600
DC
386 if (copy_from_user(job->waitchk, waitchks,
387 sizeof(*waitchks) * num_waitchks)) {
388 err = -EFAULT;
c40f0f1a 389 goto fail;
9a991600 390 }
c40f0f1a 391
9a991600
DC
392 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
393 sizeof(syncpt))) {
394 err = -EFAULT;
c40f0f1a 395 goto fail;
9a991600 396 }
c40f0f1a
TR
397
398 job->is_addr_reg = context->client->ops->is_addr_reg;
399 job->syncpt_incrs = syncpt.incrs;
400 job->syncpt_id = syncpt.id;
401 job->timeout = 10000;
402
403 if (args->timeout && args->timeout < 10000)
404 job->timeout = args->timeout;
405
406 err = host1x_job_pin(job, context->client->base.dev);
407 if (err)
408 goto fail;
409
410 err = host1x_job_submit(job);
411 if (err)
412 goto fail_submit;
413
414 args->fence = job->syncpt_end;
415
416 host1x_job_put(job);
417 return 0;
418
419fail_submit:
420 host1x_job_unpin(job);
421fail:
422 host1x_job_put(job);
423 return err;
424}
425
426
d43f81cb 427#ifdef CONFIG_DRM_TEGRA_STAGING
c88c3630
TR
428static struct tegra_drm_context *tegra_drm_get_context(__u64 context)
429{
430 return (struct tegra_drm_context *)(uintptr_t)context;
431}
432
08943e6c 433static bool tegra_drm_file_owns_context(struct tegra_drm_file *file,
c88c3630 434 struct tegra_drm_context *context)
d43f81cb 435{
c88c3630 436 struct tegra_drm_context *ctx;
d43f81cb
TB
437
438 list_for_each_entry(ctx, &file->contexts, list)
439 if (ctx == context)
440 return true;
441
442 return false;
443}
444
445static int tegra_gem_create(struct drm_device *drm, void *data,
446 struct drm_file *file)
447{
448 struct drm_tegra_gem_create *args = data;
449 struct tegra_bo *bo;
450
773af77f 451 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
d43f81cb
TB
452 &args->handle);
453 if (IS_ERR(bo))
454 return PTR_ERR(bo);
455
456 return 0;
457}
458
459static int tegra_gem_mmap(struct drm_device *drm, void *data,
460 struct drm_file *file)
461{
462 struct drm_tegra_gem_mmap *args = data;
463 struct drm_gem_object *gem;
464 struct tegra_bo *bo;
465
a8ad0bd8 466 gem = drm_gem_object_lookup(file, args->handle);
d43f81cb
TB
467 if (!gem)
468 return -EINVAL;
469
470 bo = to_tegra_bo(gem);
471
2bc7b0ca 472 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
d43f81cb 473
11533304 474 drm_gem_object_unreference_unlocked(gem);
d43f81cb
TB
475
476 return 0;
477}
478
479static int tegra_syncpt_read(struct drm_device *drm, void *data,
480 struct drm_file *file)
481{
776dc384 482 struct host1x *host = dev_get_drvdata(drm->dev->parent);
d43f81cb 483 struct drm_tegra_syncpt_read *args = data;
776dc384 484 struct host1x_syncpt *sp;
d43f81cb 485
776dc384 486 sp = host1x_syncpt_get(host, args->id);
d43f81cb
TB
487 if (!sp)
488 return -EINVAL;
489
490 args->value = host1x_syncpt_read_min(sp);
491 return 0;
492}
493
494static int tegra_syncpt_incr(struct drm_device *drm, void *data,
495 struct drm_file *file)
496{
776dc384 497 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
d43f81cb 498 struct drm_tegra_syncpt_incr *args = data;
776dc384 499 struct host1x_syncpt *sp;
d43f81cb 500
776dc384 501 sp = host1x_syncpt_get(host1x, args->id);
d43f81cb
TB
502 if (!sp)
503 return -EINVAL;
504
ebae30b1 505 return host1x_syncpt_incr(sp);
d43f81cb
TB
506}
507
508static int tegra_syncpt_wait(struct drm_device *drm, void *data,
509 struct drm_file *file)
510{
776dc384 511 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
d43f81cb 512 struct drm_tegra_syncpt_wait *args = data;
776dc384 513 struct host1x_syncpt *sp;
d43f81cb 514
776dc384 515 sp = host1x_syncpt_get(host1x, args->id);
d43f81cb
TB
516 if (!sp)
517 return -EINVAL;
518
519 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
520 &args->value);
521}
522
523static int tegra_open_channel(struct drm_device *drm, void *data,
524 struct drm_file *file)
525{
08943e6c 526 struct tegra_drm_file *fpriv = file->driver_priv;
386a2a71 527 struct tegra_drm *tegra = drm->dev_private;
d43f81cb 528 struct drm_tegra_open_channel *args = data;
c88c3630 529 struct tegra_drm_context *context;
53fa7f72 530 struct tegra_drm_client *client;
d43f81cb
TB
531 int err = -ENODEV;
532
533 context = kzalloc(sizeof(*context), GFP_KERNEL);
534 if (!context)
535 return -ENOMEM;
536
776dc384 537 list_for_each_entry(client, &tegra->clients, list)
53fa7f72 538 if (client->base.class == args->client) {
d43f81cb
TB
539 err = client->ops->open_channel(client, context);
540 if (err)
541 break;
542
d43f81cb
TB
543 list_add(&context->list, &fpriv->contexts);
544 args->context = (uintptr_t)context;
53fa7f72 545 context->client = client;
d43f81cb
TB
546 return 0;
547 }
548
549 kfree(context);
550 return err;
551}
552
553static int tegra_close_channel(struct drm_device *drm, void *data,
554 struct drm_file *file)
555{
08943e6c 556 struct tegra_drm_file *fpriv = file->driver_priv;
776dc384 557 struct drm_tegra_close_channel *args = data;
c88c3630
TR
558 struct tegra_drm_context *context;
559
560 context = tegra_drm_get_context(args->context);
d43f81cb 561
08943e6c 562 if (!tegra_drm_file_owns_context(fpriv, context))
d43f81cb
TB
563 return -EINVAL;
564
565 list_del(&context->list);
c88c3630 566 tegra_drm_context_free(context);
d43f81cb
TB
567
568 return 0;
569}
570
571static int tegra_get_syncpt(struct drm_device *drm, void *data,
572 struct drm_file *file)
573{
08943e6c 574 struct tegra_drm_file *fpriv = file->driver_priv;
d43f81cb 575 struct drm_tegra_get_syncpt *args = data;
c88c3630 576 struct tegra_drm_context *context;
d43f81cb
TB
577 struct host1x_syncpt *syncpt;
578
c88c3630
TR
579 context = tegra_drm_get_context(args->context);
580
08943e6c 581 if (!tegra_drm_file_owns_context(fpriv, context))
d43f81cb
TB
582 return -ENODEV;
583
53fa7f72 584 if (args->index >= context->client->base.num_syncpts)
d43f81cb
TB
585 return -EINVAL;
586
53fa7f72 587 syncpt = context->client->base.syncpts[args->index];
d43f81cb
TB
588 args->id = host1x_syncpt_id(syncpt);
589
590 return 0;
591}
592
593static int tegra_submit(struct drm_device *drm, void *data,
594 struct drm_file *file)
595{
08943e6c 596 struct tegra_drm_file *fpriv = file->driver_priv;
d43f81cb 597 struct drm_tegra_submit *args = data;
c88c3630
TR
598 struct tegra_drm_context *context;
599
600 context = tegra_drm_get_context(args->context);
d43f81cb 601
08943e6c 602 if (!tegra_drm_file_owns_context(fpriv, context))
d43f81cb
TB
603 return -ENODEV;
604
605 return context->client->ops->submit(context, args, drm, file);
606}
c54a169b
AM
607
608static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
609 struct drm_file *file)
610{
611 struct tegra_drm_file *fpriv = file->driver_priv;
612 struct drm_tegra_get_syncpt_base *args = data;
613 struct tegra_drm_context *context;
614 struct host1x_syncpt_base *base;
615 struct host1x_syncpt *syncpt;
616
617 context = tegra_drm_get_context(args->context);
618
619 if (!tegra_drm_file_owns_context(fpriv, context))
620 return -ENODEV;
621
622 if (args->syncpt >= context->client->base.num_syncpts)
623 return -EINVAL;
624
625 syncpt = context->client->base.syncpts[args->syncpt];
626
627 base = host1x_syncpt_get_base(syncpt);
628 if (!base)
629 return -ENXIO;
630
631 args->id = host1x_syncpt_base_id(base);
632
633 return 0;
634}
7678d71f
TR
635
636static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
637 struct drm_file *file)
638{
639 struct drm_tegra_gem_set_tiling *args = data;
640 enum tegra_bo_tiling_mode mode;
641 struct drm_gem_object *gem;
642 unsigned long value = 0;
643 struct tegra_bo *bo;
644
645 switch (args->mode) {
646 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
647 mode = TEGRA_BO_TILING_MODE_PITCH;
648
649 if (args->value != 0)
650 return -EINVAL;
651
652 break;
653
654 case DRM_TEGRA_GEM_TILING_MODE_TILED:
655 mode = TEGRA_BO_TILING_MODE_TILED;
656
657 if (args->value != 0)
658 return -EINVAL;
659
660 break;
661
662 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
663 mode = TEGRA_BO_TILING_MODE_BLOCK;
664
665 if (args->value > 5)
666 return -EINVAL;
667
668 value = args->value;
669 break;
670
671 default:
672 return -EINVAL;
673 }
674
a8ad0bd8 675 gem = drm_gem_object_lookup(file, args->handle);
7678d71f
TR
676 if (!gem)
677 return -ENOENT;
678
679 bo = to_tegra_bo(gem);
680
681 bo->tiling.mode = mode;
682 bo->tiling.value = value;
683
11533304 684 drm_gem_object_unreference_unlocked(gem);
7678d71f
TR
685
686 return 0;
687}
688
689static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
690 struct drm_file *file)
691{
692 struct drm_tegra_gem_get_tiling *args = data;
693 struct drm_gem_object *gem;
694 struct tegra_bo *bo;
695 int err = 0;
696
a8ad0bd8 697 gem = drm_gem_object_lookup(file, args->handle);
7678d71f
TR
698 if (!gem)
699 return -ENOENT;
700
701 bo = to_tegra_bo(gem);
702
703 switch (bo->tiling.mode) {
704 case TEGRA_BO_TILING_MODE_PITCH:
705 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
706 args->value = 0;
707 break;
708
709 case TEGRA_BO_TILING_MODE_TILED:
710 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
711 args->value = 0;
712 break;
713
714 case TEGRA_BO_TILING_MODE_BLOCK:
715 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
716 args->value = bo->tiling.value;
717 break;
718
719 default:
720 err = -EINVAL;
721 break;
722 }
723
11533304 724 drm_gem_object_unreference_unlocked(gem);
7678d71f
TR
725
726 return err;
727}
7b129087
TR
728
729static int tegra_gem_set_flags(struct drm_device *drm, void *data,
730 struct drm_file *file)
731{
732 struct drm_tegra_gem_set_flags *args = data;
733 struct drm_gem_object *gem;
734 struct tegra_bo *bo;
735
736 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
737 return -EINVAL;
738
a8ad0bd8 739 gem = drm_gem_object_lookup(file, args->handle);
7b129087
TR
740 if (!gem)
741 return -ENOENT;
742
743 bo = to_tegra_bo(gem);
744 bo->flags = 0;
745
746 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
747 bo->flags |= TEGRA_BO_BOTTOM_UP;
748
11533304 749 drm_gem_object_unreference_unlocked(gem);
7b129087
TR
750
751 return 0;
752}
753
754static int tegra_gem_get_flags(struct drm_device *drm, void *data,
755 struct drm_file *file)
756{
757 struct drm_tegra_gem_get_flags *args = data;
758 struct drm_gem_object *gem;
759 struct tegra_bo *bo;
760
a8ad0bd8 761 gem = drm_gem_object_lookup(file, args->handle);
7b129087
TR
762 if (!gem)
763 return -ENOENT;
764
765 bo = to_tegra_bo(gem);
766 args->flags = 0;
767
768 if (bo->flags & TEGRA_BO_BOTTOM_UP)
769 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
770
11533304 771 drm_gem_object_unreference_unlocked(gem);
7b129087
TR
772
773 return 0;
774}
d43f81cb
TB
775#endif
776
baa70943 777static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
d43f81cb 778#ifdef CONFIG_DRM_TEGRA_STAGING
f8c47144
DV
779 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
780 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
781 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
782 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
783 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
784 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
785 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
786 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
787 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
788 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
789 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
790 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
791 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
792 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
d43f81cb 793#endif
d8f4a9ed
TR
794};
795
796static const struct file_operations tegra_drm_fops = {
797 .owner = THIS_MODULE,
798 .open = drm_open,
799 .release = drm_release,
800 .unlocked_ioctl = drm_ioctl,
de2ba664 801 .mmap = tegra_drm_mmap,
d8f4a9ed 802 .poll = drm_poll,
d8f4a9ed
TR
803 .read = drm_read,
804#ifdef CONFIG_COMPAT
805 .compat_ioctl = drm_compat_ioctl,
806#endif
807 .llseek = noop_llseek,
808};
809
ed7dae58
TR
810static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm,
811 unsigned int pipe)
6e5ff998
TR
812{
813 struct drm_crtc *crtc;
814
815 list_for_each_entry(crtc, &drm->mode_config.crtc_list, head) {
ed7dae58 816 if (pipe == drm_crtc_index(crtc))
6e5ff998
TR
817 return crtc;
818 }
819
820 return NULL;
821}
822
88e72717
TR
823static u32 tegra_drm_get_vblank_counter(struct drm_device *drm,
824 unsigned int pipe)
6e5ff998 825{
ed7dae58 826 struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe);
42e9ce05 827 struct tegra_dc *dc = to_tegra_dc(crtc);
ed7dae58
TR
828
829 if (!crtc)
830 return 0;
831
42e9ce05 832 return tegra_dc_get_vblank_counter(dc);
6e5ff998
TR
833}
834
88e72717 835static int tegra_drm_enable_vblank(struct drm_device *drm, unsigned int pipe)
6e5ff998
TR
836{
837 struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe);
838 struct tegra_dc *dc = to_tegra_dc(crtc);
839
840 if (!crtc)
841 return -ENODEV;
842
843 tegra_dc_enable_vblank(dc);
844
845 return 0;
846}
847
88e72717 848static void tegra_drm_disable_vblank(struct drm_device *drm, unsigned int pipe)
6e5ff998
TR
849{
850 struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe);
851 struct tegra_dc *dc = to_tegra_dc(crtc);
852
853 if (crtc)
854 tegra_dc_disable_vblank(dc);
855}
856
3c03c46a
TR
857static void tegra_drm_preclose(struct drm_device *drm, struct drm_file *file)
858{
08943e6c 859 struct tegra_drm_file *fpriv = file->driver_priv;
c88c3630 860 struct tegra_drm_context *context, *tmp;
3c03c46a 861
d43f81cb 862 list_for_each_entry_safe(context, tmp, &fpriv->contexts, list)
c88c3630 863 tegra_drm_context_free(context);
d43f81cb
TB
864
865 kfree(fpriv);
3c03c46a
TR
866}
867
e450fcc6
TR
868#ifdef CONFIG_DEBUG_FS
869static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
870{
871 struct drm_info_node *node = (struct drm_info_node *)s->private;
872 struct drm_device *drm = node->minor->dev;
873 struct drm_framebuffer *fb;
874
875 mutex_lock(&drm->mode_config.fb_lock);
876
877 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
878 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
879 fb->base.id, fb->width, fb->height, fb->depth,
880 fb->bits_per_pixel,
747a598f 881 drm_framebuffer_read_refcount(fb));
e450fcc6
TR
882 }
883
884 mutex_unlock(&drm->mode_config.fb_lock);
885
886 return 0;
887}
888
28c23373
TR
889static int tegra_debugfs_iova(struct seq_file *s, void *data)
890{
891 struct drm_info_node *node = (struct drm_info_node *)s->private;
892 struct drm_device *drm = node->minor->dev;
893 struct tegra_drm *tegra = drm->dev_private;
894
895 return drm_mm_dump_table(s, &tegra->mm);
896}
897
e450fcc6
TR
898static struct drm_info_list tegra_debugfs_list[] = {
899 { "framebuffers", tegra_debugfs_framebuffers, 0 },
28c23373 900 { "iova", tegra_debugfs_iova, 0 },
e450fcc6
TR
901};
902
903static int tegra_debugfs_init(struct drm_minor *minor)
904{
905 return drm_debugfs_create_files(tegra_debugfs_list,
906 ARRAY_SIZE(tegra_debugfs_list),
907 minor->debugfs_root, minor);
908}
909
910static void tegra_debugfs_cleanup(struct drm_minor *minor)
911{
912 drm_debugfs_remove_files(tegra_debugfs_list,
913 ARRAY_SIZE(tegra_debugfs_list), minor);
914}
915#endif
916
9b57f5f2 917static struct drm_driver tegra_drm_driver = {
ad906599
TR
918 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
919 DRIVER_ATOMIC,
d8f4a9ed
TR
920 .load = tegra_drm_load,
921 .unload = tegra_drm_unload,
922 .open = tegra_drm_open,
3c03c46a 923 .preclose = tegra_drm_preclose,
d8f4a9ed
TR
924 .lastclose = tegra_drm_lastclose,
925
6e5ff998
TR
926 .get_vblank_counter = tegra_drm_get_vblank_counter,
927 .enable_vblank = tegra_drm_enable_vblank,
928 .disable_vblank = tegra_drm_disable_vblank,
929
e450fcc6
TR
930#if defined(CONFIG_DEBUG_FS)
931 .debugfs_init = tegra_debugfs_init,
932 .debugfs_cleanup = tegra_debugfs_cleanup,
933#endif
934
1ddbdbd6 935 .gem_free_object_unlocked = tegra_bo_free_object,
de2ba664 936 .gem_vm_ops = &tegra_bo_vm_ops,
3800391d
TR
937
938 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
939 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
940 .gem_prime_export = tegra_gem_prime_export,
941 .gem_prime_import = tegra_gem_prime_import,
942
de2ba664
AM
943 .dumb_create = tegra_bo_dumb_create,
944 .dumb_map_offset = tegra_bo_dumb_map_offset,
43387b37 945 .dumb_destroy = drm_gem_dumb_destroy,
d8f4a9ed
TR
946
947 .ioctls = tegra_drm_ioctls,
948 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
949 .fops = &tegra_drm_fops,
950
951 .name = DRIVER_NAME,
952 .desc = DRIVER_DESC,
953 .date = DRIVER_DATE,
954 .major = DRIVER_MAJOR,
955 .minor = DRIVER_MINOR,
956 .patchlevel = DRIVER_PATCHLEVEL,
957};
776dc384
TR
958
959int tegra_drm_register_client(struct tegra_drm *tegra,
960 struct tegra_drm_client *client)
961{
962 mutex_lock(&tegra->clients_lock);
963 list_add_tail(&client->list, &tegra->clients);
964 mutex_unlock(&tegra->clients_lock);
965
966 return 0;
967}
968
969int tegra_drm_unregister_client(struct tegra_drm *tegra,
970 struct tegra_drm_client *client)
971{
972 mutex_lock(&tegra->clients_lock);
973 list_del_init(&client->list);
974 mutex_unlock(&tegra->clients_lock);
975
976 return 0;
977}
978
9910f5c4 979static int host1x_drm_probe(struct host1x_device *dev)
776dc384 980{
9910f5c4
TR
981 struct drm_driver *driver = &tegra_drm_driver;
982 struct drm_device *drm;
983 int err;
984
985 drm = drm_dev_alloc(driver, &dev->dev);
986 if (!drm)
987 return -ENOMEM;
988
9910f5c4
TR
989 dev_set_drvdata(&dev->dev, drm);
990
991 err = drm_dev_register(drm, 0);
992 if (err < 0)
993 goto unref;
994
995 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name,
996 driver->major, driver->minor, driver->patchlevel,
997 driver->date, drm->primary->index);
998
999 return 0;
1000
1001unref:
1002 drm_dev_unref(drm);
1003 return err;
776dc384
TR
1004}
1005
9910f5c4 1006static int host1x_drm_remove(struct host1x_device *dev)
776dc384 1007{
9910f5c4
TR
1008 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1009
1010 drm_dev_unregister(drm);
1011 drm_dev_unref(drm);
776dc384
TR
1012
1013 return 0;
1014}
1015
359ae687
TR
1016#ifdef CONFIG_PM_SLEEP
1017static int host1x_drm_suspend(struct device *dev)
1018{
1019 struct drm_device *drm = dev_get_drvdata(dev);
986c58d1 1020 struct tegra_drm *tegra = drm->dev_private;
359ae687
TR
1021
1022 drm_kms_helper_poll_disable(drm);
986c58d1
TR
1023 tegra_drm_fb_suspend(drm);
1024
1025 tegra->state = drm_atomic_helper_suspend(drm);
1026 if (IS_ERR(tegra->state)) {
1027 tegra_drm_fb_resume(drm);
1028 drm_kms_helper_poll_enable(drm);
1029 return PTR_ERR(tegra->state);
1030 }
359ae687
TR
1031
1032 return 0;
1033}
1034
1035static int host1x_drm_resume(struct device *dev)
1036{
1037 struct drm_device *drm = dev_get_drvdata(dev);
986c58d1 1038 struct tegra_drm *tegra = drm->dev_private;
359ae687 1039
986c58d1
TR
1040 drm_atomic_helper_resume(drm, tegra->state);
1041 tegra_drm_fb_resume(drm);
359ae687
TR
1042 drm_kms_helper_poll_enable(drm);
1043
1044 return 0;
1045}
1046#endif
1047
a13f1dc4
TR
1048static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1049 host1x_drm_resume);
359ae687 1050
776dc384
TR
1051static const struct of_device_id host1x_drm_subdevs[] = {
1052 { .compatible = "nvidia,tegra20-dc", },
1053 { .compatible = "nvidia,tegra20-hdmi", },
1054 { .compatible = "nvidia,tegra20-gr2d", },
5f60ed0d 1055 { .compatible = "nvidia,tegra20-gr3d", },
776dc384
TR
1056 { .compatible = "nvidia,tegra30-dc", },
1057 { .compatible = "nvidia,tegra30-hdmi", },
1058 { .compatible = "nvidia,tegra30-gr2d", },
5f60ed0d 1059 { .compatible = "nvidia,tegra30-gr3d", },
dec72739 1060 { .compatible = "nvidia,tegra114-dsi", },
7d1d28ac 1061 { .compatible = "nvidia,tegra114-hdmi", },
5f60ed0d 1062 { .compatible = "nvidia,tegra114-gr3d", },
8620fc62 1063 { .compatible = "nvidia,tegra124-dc", },
6b6b6042 1064 { .compatible = "nvidia,tegra124-sor", },
fb7be70e 1065 { .compatible = "nvidia,tegra124-hdmi", },
7d338587 1066 { .compatible = "nvidia,tegra124-dsi", },
c06c7930 1067 { .compatible = "nvidia,tegra132-dsi", },
5b4f516f 1068 { .compatible = "nvidia,tegra210-dc", },
ddfb406b 1069 { .compatible = "nvidia,tegra210-dsi", },
3309ac83 1070 { .compatible = "nvidia,tegra210-sor", },
459cc2c6 1071 { .compatible = "nvidia,tegra210-sor1", },
776dc384
TR
1072 { /* sentinel */ }
1073};
1074
1075static struct host1x_driver host1x_drm_driver = {
f4c5cf88
TR
1076 .driver = {
1077 .name = "drm",
359ae687 1078 .pm = &host1x_drm_pm_ops,
f4c5cf88 1079 },
776dc384
TR
1080 .probe = host1x_drm_probe,
1081 .remove = host1x_drm_remove,
1082 .subdevs = host1x_drm_subdevs,
1083};
1084
473112e4
TR
1085static struct platform_driver * const drivers[] = {
1086 &tegra_dc_driver,
1087 &tegra_hdmi_driver,
1088 &tegra_dsi_driver,
1089 &tegra_dpaux_driver,
1090 &tegra_sor_driver,
1091 &tegra_gr2d_driver,
1092 &tegra_gr3d_driver,
1093};
1094
776dc384
TR
1095static int __init host1x_drm_init(void)
1096{
1097 int err;
1098
1099 err = host1x_driver_register(&host1x_drm_driver);
1100 if (err < 0)
1101 return err;
1102
473112e4 1103 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
776dc384
TR
1104 if (err < 0)
1105 goto unregister_host1x;
1106
776dc384
TR
1107 return 0;
1108
776dc384
TR
1109unregister_host1x:
1110 host1x_driver_unregister(&host1x_drm_driver);
1111 return err;
1112}
1113module_init(host1x_drm_init);
1114
1115static void __exit host1x_drm_exit(void)
1116{
473112e4 1117 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
776dc384
TR
1118 host1x_driver_unregister(&host1x_drm_driver);
1119}
1120module_exit(host1x_drm_exit);
1121
1122MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1123MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1124MODULE_LICENSE("GPL v2");
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