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drm: tegra: Rely on the default ->best_encoder() behavior
[deliverable/linux.git] / drivers / gpu / drm / tegra / dsi.c
CommitLineData
dec72739
TR		 1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
9a2ac2dc
TR		 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
dec72739
TR		 7 */
8
9#include <linux/clk.h>
10#include <linux/debugfs.h>
11#include <linux/host1x.h>
12#include <linux/module.h>
13#include <linux/of.h>
e94236cd 14#include <linux/of_platform.h>
dec72739
TR		 15#include <linux/platform_device.h>
16#include <linux/reset.h>
17
3b077afb
TR		 18#include <linux/regulator/consumer.h>
19
4aa3df71 20#include <drm/drm_atomic_helper.h>
dec72739
TR		 21#include <drm/drm_mipi_dsi.h>
22#include <drm/drm_panel.h>
23
24#include <video/mipi_display.h>
25
26#include "dc.h"
27#include "drm.h"
28#include "dsi.h"
29#include "mipi-phy.h"
30
ebd14afe
TR		 31struct tegra_dsi_state {
32 struct drm_connector_state base;
33
34 struct mipi_dphy_timing timing;
35 unsigned long period;
36
37 unsigned int vrefresh;
38 unsigned int lanes;
39 unsigned long pclk;
40 unsigned long bclk;
41
42 enum tegra_dsi_format format;
43 unsigned int mul;
44 unsigned int div;
45};
46
47static inline struct tegra_dsi_state *
48to_dsi_state(struct drm_connector_state *state)
49{
50 return container_of(state, struct tegra_dsi_state, base);
51}
52
dec72739
TR		 53struct tegra_dsi {
54 struct host1x_client client;
55 struct tegra_output output;
56 struct device *dev;
57
58 void __iomem *regs;
59
60 struct reset_control *rst;
61 struct clk *clk_parent;
62 struct clk *clk_lp;
63 struct clk *clk;
64
65 struct drm_info_list *debugfs_files;
66 struct drm_minor *minor;
67 struct dentry *debugfs;
68
17297a28 69 unsigned long flags;
dec72739
TR		 70 enum mipi_dsi_pixel_format format;
71 unsigned int lanes;
72
73 struct tegra_mipi_device *mipi;
74 struct mipi_dsi_host host;
3b077afb
TR		 75
76 struct regulator *vdd;
976cebc3
TR		 77
78 unsigned int video_fifo_depth;
79 unsigned int host_fifo_depth;
e94236cd
TR		 80
81 /* for ganged-mode support */
82 struct tegra_dsi *master;
83 struct tegra_dsi *slave;
dec72739
TR		 84};
85
86static inline struct tegra_dsi *
87host1x_client_to_dsi(struct host1x_client *client)
88{
89 return container_of(client, struct tegra_dsi, client);
90}
91
92static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
93{
94 return container_of(host, struct tegra_dsi, host);
95}
96
97static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
98{
99 return container_of(output, struct tegra_dsi, output);
100}
101
ebd14afe
TR		 102static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
103{
104 return to_dsi_state(dsi->output.connector.state);
105}
106
9c0b4ca1 107static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
dec72739
TR		 108{
109 return readl(dsi->regs + (reg << 2));
110}
111
9c0b4ca1 112static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
dec72739
TR		 113 unsigned long reg)
114{
115 writel(value, dsi->regs + (reg << 2));
116}
117
118static int tegra_dsi_show_regs(struct seq_file *s, void *data)
119{
120 struct drm_info_node *node = s->private;
121 struct tegra_dsi *dsi = node->info_ent->data;
171e2e6d
TR		 122 struct drm_crtc *crtc = dsi->output.encoder.crtc;
123 struct drm_device *drm = node->minor->dev;
124 int err = 0;
125
126 drm_modeset_lock_all(drm);
127
128 if (!crtc || !crtc->state->active) {
129 err = -EBUSY;
130 goto unlock;
131 }
dec72739
TR		 132
133#define DUMP_REG(name) \
9c0b4ca1 134 seq_printf(s, "%-32s %#05x %08x\n", #name, name, \
dec72739
TR		 135 tegra_dsi_readl(dsi, name))
136
137 DUMP_REG(DSI_INCR_SYNCPT);
138 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
139 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
140 DUMP_REG(DSI_CTXSW);
141 DUMP_REG(DSI_RD_DATA);
142 DUMP_REG(DSI_WR_DATA);
143 DUMP_REG(DSI_POWER_CONTROL);
144 DUMP_REG(DSI_INT_ENABLE);
145 DUMP_REG(DSI_INT_STATUS);
146 DUMP_REG(DSI_INT_MASK);
147 DUMP_REG(DSI_HOST_CONTROL);
148 DUMP_REG(DSI_CONTROL);
149 DUMP_REG(DSI_SOL_DELAY);
150 DUMP_REG(DSI_MAX_THRESHOLD);
151 DUMP_REG(DSI_TRIGGER);
152 DUMP_REG(DSI_TX_CRC);
153 DUMP_REG(DSI_STATUS);
154
155 DUMP_REG(DSI_INIT_SEQ_CONTROL);
156 DUMP_REG(DSI_INIT_SEQ_DATA_0);
157 DUMP_REG(DSI_INIT_SEQ_DATA_1);
158 DUMP_REG(DSI_INIT_SEQ_DATA_2);
159 DUMP_REG(DSI_INIT_SEQ_DATA_3);
160 DUMP_REG(DSI_INIT_SEQ_DATA_4);
161 DUMP_REG(DSI_INIT_SEQ_DATA_5);
162 DUMP_REG(DSI_INIT_SEQ_DATA_6);
163 DUMP_REG(DSI_INIT_SEQ_DATA_7);
164
165 DUMP_REG(DSI_PKT_SEQ_0_LO);
166 DUMP_REG(DSI_PKT_SEQ_0_HI);
167 DUMP_REG(DSI_PKT_SEQ_1_LO);
168 DUMP_REG(DSI_PKT_SEQ_1_HI);
169 DUMP_REG(DSI_PKT_SEQ_2_LO);
170 DUMP_REG(DSI_PKT_SEQ_2_HI);
171 DUMP_REG(DSI_PKT_SEQ_3_LO);
172 DUMP_REG(DSI_PKT_SEQ_3_HI);
173 DUMP_REG(DSI_PKT_SEQ_4_LO);
174 DUMP_REG(DSI_PKT_SEQ_4_HI);
175 DUMP_REG(DSI_PKT_SEQ_5_LO);
176 DUMP_REG(DSI_PKT_SEQ_5_HI);
177
178 DUMP_REG(DSI_DCS_CMDS);
179
180 DUMP_REG(DSI_PKT_LEN_0_1);
181 DUMP_REG(DSI_PKT_LEN_2_3);
182 DUMP_REG(DSI_PKT_LEN_4_5);
183 DUMP_REG(DSI_PKT_LEN_6_7);
184
185 DUMP_REG(DSI_PHY_TIMING_0);
186 DUMP_REG(DSI_PHY_TIMING_1);
187 DUMP_REG(DSI_PHY_TIMING_2);
188 DUMP_REG(DSI_BTA_TIMING);
189
190 DUMP_REG(DSI_TIMEOUT_0);
191 DUMP_REG(DSI_TIMEOUT_1);
192 DUMP_REG(DSI_TO_TALLY);
193
194 DUMP_REG(DSI_PAD_CONTROL_0);
195 DUMP_REG(DSI_PAD_CONTROL_CD);
196 DUMP_REG(DSI_PAD_CD_STATUS);
197 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
198 DUMP_REG(DSI_PAD_CONTROL_1);
199 DUMP_REG(DSI_PAD_CONTROL_2);
200 DUMP_REG(DSI_PAD_CONTROL_3);
201 DUMP_REG(DSI_PAD_CONTROL_4);
202
203 DUMP_REG(DSI_GANGED_MODE_CONTROL);
204 DUMP_REG(DSI_GANGED_MODE_START);
205 DUMP_REG(DSI_GANGED_MODE_SIZE);
206
207 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
208 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
209
210 DUMP_REG(DSI_INIT_SEQ_DATA_8);
211 DUMP_REG(DSI_INIT_SEQ_DATA_9);
212 DUMP_REG(DSI_INIT_SEQ_DATA_10);
213 DUMP_REG(DSI_INIT_SEQ_DATA_11);
214 DUMP_REG(DSI_INIT_SEQ_DATA_12);
215 DUMP_REG(DSI_INIT_SEQ_DATA_13);
216 DUMP_REG(DSI_INIT_SEQ_DATA_14);
217 DUMP_REG(DSI_INIT_SEQ_DATA_15);
218
219#undef DUMP_REG
220
171e2e6d
TR		 221unlock:
222 drm_modeset_unlock_all(drm);
223 return err;
dec72739
TR		 224}
225
226static struct drm_info_list debugfs_files[] = {
227 { "regs", tegra_dsi_show_regs, 0, NULL },
228};
229
230static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
231 struct drm_minor *minor)
232{
233 const char *name = dev_name(dsi->dev);
234 unsigned int i;
235 int err;
236
237 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
238 if (!dsi->debugfs)
239 return -ENOMEM;
240
241 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
242 GFP_KERNEL);
243 if (!dsi->debugfs_files) {
244 err = -ENOMEM;
245 goto remove;
246 }
247
248 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
249 dsi->debugfs_files[i].data = dsi;
250
251 err = drm_debugfs_create_files(dsi->debugfs_files,
252 ARRAY_SIZE(debugfs_files),
253 dsi->debugfs, minor);
254 if (err < 0)
255 goto free;
256
257 dsi->minor = minor;
258
259 return 0;
260
261free:
262 kfree(dsi->debugfs_files);
263 dsi->debugfs_files = NULL;
264remove:
265 debugfs_remove(dsi->debugfs);
266 dsi->debugfs = NULL;
267
268 return err;
269}
270
4009c224 271static void tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
dec72739
TR		 272{
273 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
274 dsi->minor);
275 dsi->minor = NULL;
276
277 kfree(dsi->debugfs_files);
278 dsi->debugfs_files = NULL;
279
280 debugfs_remove(dsi->debugfs);
281 dsi->debugfs = NULL;
dec72739
TR		 282}
283
284#define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
285#define PKT_LEN0(len) (((len) & 0x07) << 0)
286#define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
287#define PKT_LEN1(len) (((len) & 0x07) << 10)
288#define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
289#define PKT_LEN2(len) (((len) & 0x07) << 20)
290
291#define PKT_LP (1 << 30)
292#define NUM_PKT_SEQ 12
293
17297a28
TR		 294/*
295 * non-burst mode with sync pulses
296 */
297static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
dec72739
TR		 298 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
299 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
300 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
301 PKT_LP,
302 [ 1] = 0,
303 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
304 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
305 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
306 PKT_LP,
307 [ 3] = 0,
308 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
309 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
310 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
311 PKT_LP,
312 [ 5] = 0,
313 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
314 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
315 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
316 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
317 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
318 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
319 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
320 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
321 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
322 PKT_LP,
323 [ 9] = 0,
324 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
325 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
326 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
327 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
328 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
329 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
330};
331
17297a28
TR		 332/*
333 * non-burst mode with sync events
334 */
335static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
336 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
337 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
338 PKT_LP,
339 [ 1] = 0,
340 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
341 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
342 PKT_LP,
343 [ 3] = 0,
344 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
345 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
346 PKT_LP,
347 [ 5] = 0,
348 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
349 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
350 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
351 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
352 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
353 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
354 PKT_LP,
355 [ 9] = 0,
356 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
357 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
358 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
359 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
360};
361
337b443d
TR		 362static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
363 [ 0] = 0,
364 [ 1] = 0,
365 [ 2] = 0,
366 [ 3] = 0,
367 [ 4] = 0,
368 [ 5] = 0,
369 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
370 [ 7] = 0,
371 [ 8] = 0,
372 [ 9] = 0,
373 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
374 [11] = 0,
375};
376
ebd14afe
TR		 377static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
378 unsigned long period,
379 const struct mipi_dphy_timing *timing)
dec72739 380{
9c0b4ca1 381 u32 value;
dec72739 382
ebd14afe
TR		 383 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
384 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
385 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
386 DSI_TIMING_FIELD(timing->hsprepare, period, 1);
dec72739
TR		 387 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
388
ebd14afe
TR		 389 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
390 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
391 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
392 DSI_TIMING_FIELD(timing->lpx, period, 1);
dec72739
TR		 393 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
394
ebd14afe
TR		 395 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
396 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
dec72739
TR		 397 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
398 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
399
ebd14afe
TR		 400 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
401 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
402 DSI_TIMING_FIELD(timing->tago, period, 1);
dec72739
TR		 403 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
404
7e3bc3a9 405 if (dsi->slave)
ebd14afe 406 tegra_dsi_set_phy_timing(dsi->slave, period, timing);
dec72739
TR		 407}
408
409static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
410 unsigned int *mulp, unsigned int *divp)
411{
412 switch (format) {
413 case MIPI_DSI_FMT_RGB666_PACKED:
414 case MIPI_DSI_FMT_RGB888:
415 *mulp = 3;
416 *divp = 1;
417 break;
418
419 case MIPI_DSI_FMT_RGB565:
420 *mulp = 2;
421 *divp = 1;
422 break;
423
424 case MIPI_DSI_FMT_RGB666:
425 *mulp = 9;
426 *divp = 4;
427 break;
428
429 default:
430 return -EINVAL;
431 }
432
433 return 0;
434}
435
f7d6889b
TR		 436static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
437 enum tegra_dsi_format *fmt)
438{
439 switch (format) {
440 case MIPI_DSI_FMT_RGB888:
441 *fmt = TEGRA_DSI_FORMAT_24P;
442 break;
443
444 case MIPI_DSI_FMT_RGB666:
445 *fmt = TEGRA_DSI_FORMAT_18NP;
446 break;
447
448 case MIPI_DSI_FMT_RGB666_PACKED:
449 *fmt = TEGRA_DSI_FORMAT_18P;
450 break;
451
452 case MIPI_DSI_FMT_RGB565:
453 *fmt = TEGRA_DSI_FORMAT_16P;
454 break;
455
456 default:
457 return -EINVAL;
458 }
459
460 return 0;
461}
462
e94236cd
TR		 463static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
464 unsigned int size)
465{
466 u32 value;
467
468 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
469 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
470
471 value = DSI_GANGED_MODE_CONTROL_ENABLE;
472 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
473}
474
563eff1f
TR		 475static void tegra_dsi_enable(struct tegra_dsi *dsi)
476{
477 u32 value;
478
479 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
480 value |= DSI_POWER_CONTROL_ENABLE;
481 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
e94236cd
TR		 482
483 if (dsi->slave)
484 tegra_dsi_enable(dsi->slave);
485}
486
487static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
488{
489 if (dsi->master)
490 return dsi->master->lanes + dsi->lanes;
491
492 if (dsi->slave)
493 return dsi->lanes + dsi->slave->lanes;
494
495 return dsi->lanes;
563eff1f
TR		 496}
497
ebd14afe
TR		 498static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
499 const struct drm_display_mode *mode)
dec72739 500{
dec72739 501 unsigned int hact, hsw, hbp, hfp, i, mul, div;
ebd14afe 502 struct tegra_dsi_state *state;
17297a28 503 const u32 *pkt_seq;
563eff1f 504 u32 value;
ebd14afe
TR		 505
506 /* XXX: pass in state into this function? */
507 if (dsi->master)
508 state = tegra_dsi_get_state(dsi->master);
509 else
510 state = tegra_dsi_get_state(dsi);
511
512 mul = state->mul;
513 div = state->div;
dec72739 514
17297a28
TR		 515 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
516 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
517 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
337b443d 518 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
17297a28
TR		 519 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
520 pkt_seq = pkt_seq_video_non_burst_sync_events;
337b443d
TR		 521 } else {
522 DRM_DEBUG_KMS("Command mode\n");
523 pkt_seq = pkt_seq_command_mode;
17297a28
TR		 524 }
525
ebd14afe
TR		 526 value = DSI_CONTROL_CHANNEL(0) |
527 DSI_CONTROL_FORMAT(state->format) |
dec72739 528 DSI_CONTROL_LANES(dsi->lanes - 1) |
563eff1f 529 DSI_CONTROL_SOURCE(pipe);
dec72739
TR		 530 tegra_dsi_writel(dsi, value, DSI_CONTROL);
531
976cebc3 532 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
dec72739 533
563eff1f 534 value = DSI_HOST_CONTROL_HS;
dec72739
TR		 535 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
536
537 value = tegra_dsi_readl(dsi, DSI_CONTROL);
563eff1f 538
0c6b1e4b
AC		 539 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
540 value |= DSI_CONTROL_HS_CLK_CTRL;
563eff1f 541
dec72739 542 value &= ~DSI_CONTROL_TX_TRIG(3);
337b443d
TR		 543
544 /* enable DCS commands for command mode */
545 if (dsi->flags & MIPI_DSI_MODE_VIDEO)
546 value &= ~DSI_CONTROL_DCS_ENABLE;
547 else
548 value |= DSI_CONTROL_DCS_ENABLE;
549
dec72739
TR		 550 value |= DSI_CONTROL_VIDEO_ENABLE;
551 value &= ~DSI_CONTROL_HOST_ENABLE;
552 tegra_dsi_writel(dsi, value, DSI_CONTROL);
553
dec72739
TR		 554 for (i = 0; i < NUM_PKT_SEQ; i++)
555 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
556
337b443d
TR		 557 if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
558 /* horizontal active pixels */
559 hact = mode->hdisplay * mul / div;
560
561 /* horizontal sync width */
562 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
337b443d
TR		 563
564 /* horizontal back porch */
565 hbp = (mode->htotal - mode->hsync_end) * mul / div;
b8be0bdb
TR		 566
567 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
568 hbp += hsw;
337b443d
TR		 569
570 /* horizontal front porch */
571 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
b8be0bdb
TR		 572
573 /* subtract packet overhead */
574 hsw -= 10;
575 hbp -= 14;
337b443d 576 hfp -= 8;
dec72739 577
337b443d
TR		 578 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
579 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
580 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
581 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
dec72739 582
337b443d
TR		 583 /* set SOL delay (for non-burst mode only) */
584 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
e94236cd
TR		 585
586 /* TODO: implement ganged mode */
337b443d
TR		 587 } else {
588 u16 bytes;
589
e94236cd
TR		 590 if (dsi->master || dsi->slave) {
591 /*
592 * For ganged mode, assume symmetric left-right mode.
593 */
594 bytes = 1 + (mode->hdisplay / 2) * mul / div;
595 } else {
596 /* 1 byte (DCS command) + pixel data */
597 bytes = 1 + mode->hdisplay * mul / div;
598 }
dec72739 599
337b443d
TR		 600 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
601 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
602 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
603 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
dec72739 604
337b443d
TR		 605 value = MIPI_DCS_WRITE_MEMORY_START << 8 |
606 MIPI_DCS_WRITE_MEMORY_CONTINUE;
607 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
dec72739 608
e94236cd
TR		 609 /* set SOL delay */
610 if (dsi->master || dsi->slave) {
e94236cd 611 unsigned long delay, bclk, bclk_ganged;
ebd14afe 612 unsigned int lanes = state->lanes;
e94236cd
TR		 613
614 /* SOL to valid, valid to FIFO and FIFO write delay */
615 delay = 4 + 4 + 2;
616 delay = DIV_ROUND_UP(delay * mul, div * lanes);
617 /* FIFO read delay */
618 delay = delay + 6;
619
620 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
621 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
622 value = bclk - bclk_ganged + delay + 20;
623 } else {
624 /* TODO: revisit for non-ganged mode */
625 value = 8 * mul / div;
626 }
337b443d
TR		 627
628 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
629 }
dec72739 630
e94236cd 631 if (dsi->slave) {
ebd14afe 632 tegra_dsi_configure(dsi->slave, pipe, mode);
e94236cd
TR		 633
634 /*
635 * TODO: Support modes other than symmetrical left-right
636 * split.
637 */
638 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
639 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
640 mode->hdisplay / 2);
641 }
563eff1f
TR		 642}
643
563eff1f
TR		 644static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
645{
646 u32 value;
647
648 timeout = jiffies + msecs_to_jiffies(timeout);
649
650 while (time_before(jiffies, timeout)) {
651 value = tegra_dsi_readl(dsi, DSI_STATUS);
652 if (value & DSI_STATUS_IDLE)
653 return 0;
654
655 usleep_range(1000, 2000);
656 }
657
658 return -ETIMEDOUT;
659}
660
661static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
662{
663 u32 value;
664
665 value = tegra_dsi_readl(dsi, DSI_CONTROL);
666 value &= ~DSI_CONTROL_VIDEO_ENABLE;
667 tegra_dsi_writel(dsi, value, DSI_CONTROL);
e94236cd
TR		 668
669 if (dsi->slave)
670 tegra_dsi_video_disable(dsi->slave);
671}
672
673static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
674{
675 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
676 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
677 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
563eff1f
TR		 678}
679
5b901e78
TR		 680static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
681 unsigned int vrefresh)
682{
683 unsigned int timeout;
684 u32 value;
685
686 /* one frame high-speed transmission timeout */
687 timeout = (bclk / vrefresh) / 512;
688 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
689 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
690
691 /* 2 ms peripheral timeout for panel */
692 timeout = 2 * bclk / 512 * 1000;
693 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
694 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
695
696 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
697 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
698
699 if (dsi->slave)
700 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
701}
702
563eff1f
TR		 703static void tegra_dsi_disable(struct tegra_dsi *dsi)
704{
705 u32 value;
706
e94236cd
TR		 707 if (dsi->slave) {
708 tegra_dsi_ganged_disable(dsi->slave);
709 tegra_dsi_ganged_disable(dsi);
710 }
711
563eff1f
TR		 712 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
713 value &= ~DSI_POWER_CONTROL_ENABLE;
714 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
715
e94236cd
TR		 716 if (dsi->slave)
717 tegra_dsi_disable(dsi->slave);
718
563eff1f
TR		 719 usleep_range(5000, 10000);
720}
721
92f0e073
TR		 722static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
723{
724 u32 value;
725
726 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
727 value &= ~DSI_POWER_CONTROL_ENABLE;
728 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
729
730 usleep_range(300, 1000);
731
732 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
733 value |= DSI_POWER_CONTROL_ENABLE;
734 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
735
736 usleep_range(300, 1000);
737
738 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
739 if (value)
740 tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
741
742 if (dsi->slave)
743 tegra_dsi_soft_reset(dsi->slave);
744}
745
ebd14afe
TR		 746static void tegra_dsi_connector_reset(struct drm_connector *connector)
747{
280dc0e1 748 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
ebd14afe 749
280dc0e1
JH		 750 if (!state)
751 return;
752
753 if (connector->state) {
754 __drm_atomic_helper_connector_destroy_state(connector->state);
5459a2ad 755 kfree(connector->state);
5459a2ad 756 }
280dc0e1
JH		 757
758 __drm_atomic_helper_connector_reset(connector, &state->base);
ebd14afe
TR		 759}
760
761static struct drm_connector_state *
762tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
763{
764 struct tegra_dsi_state *state = to_dsi_state(connector->state);
765 struct tegra_dsi_state *copy;
766
767 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
768 if (!copy)
769 return NULL;
770
280dc0e1
JH		 771 __drm_atomic_helper_connector_duplicate_state(connector,
772 &copy->base);
773
ebd14afe
TR		 774 return &copy->base;
775}
776
5b901e78 777static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
171e2e6d 778 .dpms = drm_atomic_helper_connector_dpms,
ebd14afe 779 .reset = tegra_dsi_connector_reset,
5b901e78
TR		 780 .detect = tegra_output_connector_detect,
781 .fill_modes = drm_helper_probe_single_connector_modes,
782 .destroy = tegra_output_connector_destroy,
ebd14afe 783 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
4aa3df71 784 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5b901e78 785};
3f6b406f 786
5b901e78
TR		 787static enum drm_mode_status
788tegra_dsi_connector_mode_valid(struct drm_connector *connector,
789 struct drm_display_mode *mode)
790{
791 return MODE_OK;
792}
3f6b406f 793
5b901e78
TR		 794static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
795 .get_modes = tegra_output_connector_get_modes,
796 .mode_valid = tegra_dsi_connector_mode_valid,
5b901e78 797};
3f6b406f 798
5b901e78
TR		 799static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
800 .destroy = tegra_output_encoder_destroy,
801};
e94236cd 802
171e2e6d 803static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
5b901e78 804{
171e2e6d
TR		 805 struct tegra_output *output = encoder_to_output(encoder);
806 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
807 struct tegra_dsi *dsi = to_dsi(output);
808 u32 value;
809 int err;
3f6b406f 810
171e2e6d
TR		 811 if (output->panel)
812 drm_panel_disable(output->panel);
5b901e78 813
171e2e6d
TR		 814 tegra_dsi_video_disable(dsi);
815
816 /*
817 * The following accesses registers of the display controller, so make
818 * sure it's only executed when the output is attached to one.
819 */
820 if (dc) {
821 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
822 value &= ~DSI_ENABLE;
823 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
824
825 tegra_dc_commit(dc);
826 }
827
828 err = tegra_dsi_wait_idle(dsi, 100);
829 if (err < 0)
830 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
831
832 tegra_dsi_soft_reset(dsi);
833
834 if (output->panel)
835 drm_panel_unprepare(output->panel);
836
837 tegra_dsi_disable(dsi);
838
839 return;
dec72739
TR		 840}
841
171e2e6d 842static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
5b901e78 843{
171e2e6d 844 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
5b901e78
TR		 845 struct tegra_output *output = encoder_to_output(encoder);
846 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
847 struct tegra_dsi *dsi = to_dsi(output);
ebd14afe 848 struct tegra_dsi_state *state;
5b901e78 849 u32 value;
5b901e78 850
ebd14afe 851 state = tegra_dsi_get_state(dsi);
5b901e78 852
ebd14afe
TR		 853 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
854
855 /*
856 * The D-PHY timing fields are expressed in byte-clock cycles, so
857 * multiply the period by 8.
858 */
859 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
5b901e78
TR		 860
861 if (output->panel)
862 drm_panel_prepare(output->panel);
863
ebd14afe
TR		 864 tegra_dsi_configure(dsi, dc->pipe, mode);
865
5b901e78
TR		 866 /* enable display controller */
867 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
868 value |= DSI_ENABLE;
869 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
870
5b901e78
TR		 871 tegra_dc_commit(dc);
872
873 /* enable DSI controller */
874 tegra_dsi_enable(dsi);
875
876 if (output->panel)
877 drm_panel_enable(output->panel);
878
879 return;
880}
881
ebd14afe
TR		 882static int
883tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
884 struct drm_crtc_state *crtc_state,
885 struct drm_connector_state *conn_state)
886{
887 struct tegra_output *output = encoder_to_output(encoder);
888 struct tegra_dsi_state *state = to_dsi_state(conn_state);
889 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
890 struct tegra_dsi *dsi = to_dsi(output);
891 unsigned int scdiv;
892 unsigned long plld;
893 int err;
894
895 state->pclk = crtc_state->mode.clock * 1000;
896
897 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
898 if (err < 0)
899 return err;
900
901 state->lanes = tegra_dsi_get_lanes(dsi);
902
903 err = tegra_dsi_get_format(dsi->format, &state->format);
904 if (err < 0)
905 return err;
906
907 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
908
909 /* compute byte clock */
910 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
911
912 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
913 state->lanes);
914 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
915 state->vrefresh);
916 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
917
918 /*
919 * Compute bit clock and round up to the next MHz.
920 */
921 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
922 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
923
924 err = mipi_dphy_timing_get_default(&state->timing, state->period);
925 if (err < 0)
926 return err;
927
928 err = mipi_dphy_timing_validate(&state->timing, state->period);
929 if (err < 0) {
930 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
931 return err;
932 }
933
934 /*
935 * We divide the frequency by two here, but we make up for that by
936 * setting the shift clock divider (further below) to half of the
937 * correct value.
938 */
939 plld /= 2;
940
941 /*
942 * Derive pixel clock from bit clock using the shift clock divider.
943 * Note that this is only half of what we would expect, but we need
944 * that to make up for the fact that we divided the bit clock by a
945 * factor of two above.
946 *
947 * It's not clear exactly why this is necessary, but the display is
948 * not working properly otherwise. Perhaps the PLLs cannot generate
949 * frequencies sufficiently high.
950 */
951 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
952
953 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
954 plld, scdiv);
955 if (err < 0) {
956 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
957 return err;
958 }
959
960 return err;
961}
962
5b901e78 963static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
5b901e78 964 .disable = tegra_dsi_encoder_disable,
171e2e6d 965 .enable = tegra_dsi_encoder_enable,
ebd14afe 966 .atomic_check = tegra_dsi_encoder_atomic_check,
dec72739
TR		 967};
968
969static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
970{
9c0b4ca1 971 u32 value;
dec72739
TR		 972
973 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
974 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
975
976 return 0;
977}
978
979static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
980{
183ef288 981 u32 value;
dec72739
TR		 982
983 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
984 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
985 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
986 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
987 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
988
989 /* start calibration */
990 tegra_dsi_pad_enable(dsi);
991
992 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
993 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
994 DSI_PAD_OUT_CLK(0x0);
995 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
996
ddfb406b
TR		 997 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
998 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
999 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
1000
dec72739
TR		 1001 return tegra_mipi_calibrate(dsi->mipi);
1002}
1003
1004static int tegra_dsi_init(struct host1x_client *client)
1005{
9910f5c4 1006 struct drm_device *drm = dev_get_drvdata(client->parent);
dec72739 1007 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739
TR		 1008 int err;
1009
201106d8
TR		 1010 reset_control_deassert(dsi->rst);
1011
1012 err = tegra_dsi_pad_calibrate(dsi);
1013 if (err < 0) {
1014 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
1015 goto reset;
1016 }
1017
e94236cd
TR		 1018 /* Gangsters must not register their own outputs. */
1019 if (!dsi->master) {
e94236cd 1020 dsi->output.dev = client->dev;
e94236cd 1021
5b901e78
TR		 1022 drm_connector_init(drm, &dsi->output.connector,
1023 &tegra_dsi_connector_funcs,
1024 DRM_MODE_CONNECTOR_DSI);
1025 drm_connector_helper_add(&dsi->output.connector,
1026 &tegra_dsi_connector_helper_funcs);
1027 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1028
5b901e78
TR		 1029 drm_encoder_init(drm, &dsi->output.encoder,
1030 &tegra_dsi_encoder_funcs,
13a3d91f 1031 DRM_MODE_ENCODER_DSI, NULL);
5b901e78
TR		 1032 drm_encoder_helper_add(&dsi->output.encoder,
1033 &tegra_dsi_encoder_helper_funcs);
1034
1035 drm_mode_connector_attach_encoder(&dsi->output.connector,
1036 &dsi->output.encoder);
1037 drm_connector_register(&dsi->output.connector);
1038
ea130b24
TR		 1039 err = tegra_output_init(drm, &dsi->output);
1040 if (err < 0) {
1041 dev_err(client->dev,
1042 "failed to initialize output: %d\n",
1043 err);
1044 goto reset;
1045 }
1046
5b901e78 1047 dsi->output.encoder.possible_crtcs = 0x3;
dec72739
TR		 1048 }
1049
1050 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
9910f5c4 1051 err = tegra_dsi_debugfs_init(dsi, drm->primary);
dec72739
TR		 1052 if (err < 0)
1053 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
1054 }
1055
dec72739 1056 return 0;
201106d8
TR		 1057
1058reset:
1059 reset_control_assert(dsi->rst);
1060 return err;
dec72739
TR		 1061}
1062
1063static int tegra_dsi_exit(struct host1x_client *client)
1064{
1065 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
dec72739 1066
5b901e78
TR		 1067 tegra_output_exit(&dsi->output);
1068
4009c224
TR		 1069 if (IS_ENABLED(CONFIG_DEBUG_FS))
1070 tegra_dsi_debugfs_exit(dsi);
dec72739 1071
201106d8
TR		 1072 reset_control_assert(dsi->rst);
1073
dec72739
TR		 1074 return 0;
1075}
1076
1077static const struct host1x_client_ops dsi_client_ops = {
1078 .init = tegra_dsi_init,
1079 .exit = tegra_dsi_exit,
1080};
1081
1082static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1083{
1084 struct clk *parent;
1085 int err;
1086
1087 parent = clk_get_parent(dsi->clk);
1088 if (!parent)
1089 return -EINVAL;
1090
1091 err = clk_set_parent(parent, dsi->clk_parent);
1092 if (err < 0)
1093 return err;
1094
1095 return 0;
1096}
1097
0fffdf6c
TR		 1098static const char * const error_report[16] = {
1099 "SoT Error",
1100 "SoT Sync Error",
1101 "EoT Sync Error",
1102 "Escape Mode Entry Command Error",
1103 "Low-Power Transmit Sync Error",
1104 "Peripheral Timeout Error",
1105 "False Control Error",
1106 "Contention Detected",
1107 "ECC Error, single-bit",
1108 "ECC Error, multi-bit",
1109 "Checksum Error",
1110 "DSI Data Type Not Recognized",
1111 "DSI VC ID Invalid",
1112 "Invalid Transmission Length",
1113 "Reserved",
1114 "DSI Protocol Violation",
1115};
1116
1117static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1118 const struct mipi_dsi_msg *msg,
1119 size_t count)
1120{
1121 u8 *rx = msg->rx_buf;
1122 unsigned int i, j, k;
1123 size_t size = 0;
1124 u16 errors;
1125 u32 value;
1126
1127 /* read and parse packet header */
1128 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1129
1130 switch (value & 0x3f) {
1131 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1132 errors = (value >> 8) & 0xffff;
1133 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1134 errors);
1135 for (i = 0; i < ARRAY_SIZE(error_report); i++)
1136 if (errors & BIT(i))
1137 dev_dbg(dsi->dev, " %2u: %s\n", i,
1138 error_report[i]);
1139 break;
1140
1141 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1142 rx[0] = (value >> 8) & 0xff;
1143 size = 1;
1144 break;
1145
1146 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1147 rx[0] = (value >> 8) & 0xff;
1148 rx[1] = (value >> 16) & 0xff;
1149 size = 2;
1150 break;
1151
1152 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1153 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1154 break;
1155
1156 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1157 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1158 break;
1159
1160 default:
1161 dev_err(dsi->dev, "unhandled response type: %02x\n",
1162 value & 0x3f);
1163 return -EPROTO;
1164 }
1165
1166 size = min(size, msg->rx_len);
1167
1168 if (msg->rx_buf && size > 0) {
1169 for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1170 u8 *rx = msg->rx_buf + j;
1171
1172 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1173
1174 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1175 rx[j + k] = (value >> (k << 3)) & 0xff;
1176 }
1177 }
1178
1179 return size;
1180}
1181
1182static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1183{
1184 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1185
1186 timeout = jiffies + msecs_to_jiffies(timeout);
1187
1188 while (time_before(jiffies, timeout)) {
1189 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1190 if ((value & DSI_TRIGGER_HOST) == 0)
1191 return 0;
1192
1193 usleep_range(1000, 2000);
1194 }
1195
1196 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1197 return -ETIMEDOUT;
1198}
1199
1200static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1201 unsigned long timeout)
1202{
1203 timeout = jiffies + msecs_to_jiffies(250);
1204
1205 while (time_before(jiffies, timeout)) {
1206 u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1207 u8 count = value & 0x1f;
1208
1209 if (count > 0)
1210 return count;
1211
1212 usleep_range(1000, 2000);
1213 }
1214
1215 DRM_DEBUG_KMS("peripheral returned no data\n");
1216 return -ETIMEDOUT;
1217}
1218
1219static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1220 const void *buffer, size_t size)
1221{
1222 const u8 *buf = buffer;
1223 size_t i, j;
1224 u32 value;
1225
1226 for (j = 0; j < size; j += 4) {
1227 value = 0;
1228
1229 for (i = 0; i < 4 && j + i < size; i++)
1230 value |= buf[j + i] << (i << 3);
1231
1232 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1233 }
1234}
1235
1236static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1237 const struct mipi_dsi_msg *msg)
1238{
1239 struct tegra_dsi *dsi = host_to_tegra(host);
1240 struct mipi_dsi_packet packet;
1241 const u8 *header;
1242 size_t count;
1243 ssize_t err;
1244 u32 value;
1245
1246 err = mipi_dsi_create_packet(&packet, msg);
1247 if (err < 0)
1248 return err;
1249
1250 header = packet.header;
1251
1252 /* maximum FIFO depth is 1920 words */
1253 if (packet.size > dsi->video_fifo_depth * 4)
1254 return -ENOSPC;
1255
1256 /* reset underflow/overflow flags */
1257 value = tegra_dsi_readl(dsi, DSI_STATUS);
1258 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1259 value = DSI_HOST_CONTROL_FIFO_RESET;
1260 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1261 usleep_range(10, 20);
1262 }
1263
1264 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1265 value |= DSI_POWER_CONTROL_ENABLE;
1266 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1267
1268 usleep_range(5000, 10000);
1269
1270 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1271 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1272
1273 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1274 value |= DSI_HOST_CONTROL_HS;
1275
1276 /*
1277 * The host FIFO has a maximum of 64 words, so larger transmissions
1278 * need to use the video FIFO.
1279 */
1280 if (packet.size > dsi->host_fifo_depth * 4)
1281 value |= DSI_HOST_CONTROL_FIFO_SEL;
1282
1283 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1284
1285 /*
1286 * For reads and messages with explicitly requested ACK, generate a
1287 * BTA sequence after the transmission of the packet.
1288 */
1289 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1290 (msg->rx_buf && msg->rx_len > 0)) {
1291 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1292 value |= DSI_HOST_CONTROL_PKT_BTA;
1293 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1294 }
1295
1296 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1297 tegra_dsi_writel(dsi, value, DSI_CONTROL);
1298
1299 /* write packet header, ECC is generated by hardware */
1300 value = header[2] << 16 | header[1] << 8 | header[0];
1301 tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1302
1303 /* write payload (if any) */
1304 if (packet.payload_length > 0)
1305 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1306 packet.payload_length);
1307
1308 err = tegra_dsi_transmit(dsi, 250);
1309 if (err < 0)
1310 return err;
1311
1312 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1313 (msg->rx_buf && msg->rx_len > 0)) {
1314 err = tegra_dsi_wait_for_response(dsi, 250);
1315 if (err < 0)
1316 return err;
1317
1318 count = err;
1319
1320 value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1321 switch (value) {
1322 case 0x84:
1323 /*
1324 dev_dbg(dsi->dev, "ACK\n");
1325 */
1326 break;
1327
1328 case 0x87:
1329 /*
1330 dev_dbg(dsi->dev, "ESCAPE\n");
1331 */
1332 break;
1333
1334 default:
1335 dev_err(dsi->dev, "unknown status: %08x\n", value);
1336 break;
1337 }
1338
1339 if (count > 1) {
1340 err = tegra_dsi_read_response(dsi, msg, count);
1341 if (err < 0)
1342 dev_err(dsi->dev,
1343 "failed to parse response: %zd\n",
1344 err);
1345 else {
1346 /*
1347 * For read commands, return the number of
1348 * bytes returned by the peripheral.
1349 */
1350 count = err;
1351 }
1352 }
1353 } else {
1354 /*
1355 * For write commands, we have transmitted the 4-byte header
1356 * plus the variable-length payload.
1357 */
1358 count = 4 + packet.payload_length;
1359 }
1360
1361 return count;
1362}
1363
e94236cd
TR		 1364static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1365{
1366 struct clk *parent;
1367 int err;
1368
1369 /* make sure both DSI controllers share the same PLL */
1370 parent = clk_get_parent(dsi->slave->clk);
1371 if (!parent)
1372 return -EINVAL;
1373
1374 err = clk_set_parent(parent, dsi->clk_parent);
1375 if (err < 0)
1376 return err;
1377
1378 return 0;
1379}
1380
dec72739
TR		 1381static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1382 struct mipi_dsi_device *device)
1383{
1384 struct tegra_dsi *dsi = host_to_tegra(host);
dec72739 1385
17297a28 1386 dsi->flags = device->mode_flags;
dec72739
TR		 1387 dsi->format = device->format;
1388 dsi->lanes = device->lanes;
1389
e94236cd
TR		 1390 if (dsi->slave) {
1391 int err;
1392
1393 dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1394 dev_name(&device->dev));
1395
1396 err = tegra_dsi_ganged_setup(dsi);
1397 if (err < 0) {
1398 dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1399 err);
1400 return err;
1401 }
1402 }
1403
1404 /*
1405 * Slaves don't have a panel associated with them, so they provide
1406 * merely the second channel.
1407 */
1408 if (!dsi->master) {
1409 struct tegra_output *output = &dsi->output;
1410
1411 output->panel = of_drm_find_panel(device->dev.of_node);
1412 if (output->panel && output->connector.dev) {
1413 drm_panel_attach(output->panel, &output->connector);
dec72739 1414 drm_helper_hpd_irq_event(output->connector.dev);
e94236cd 1415 }
dec72739
TR		 1416 }
1417
1418 return 0;
1419}
1420
1421static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1422 struct mipi_dsi_device *device)
1423{
1424 struct tegra_dsi *dsi = host_to_tegra(host);
1425 struct tegra_output *output = &dsi->output;
1426
1427 if (output->panel && &device->dev == output->panel->dev) {
ba3df979
TR		 1428 output->panel = NULL;
1429
dec72739
TR		 1430 if (output->connector.dev)
1431 drm_helper_hpd_irq_event(output->connector.dev);
dec72739
TR		 1432 }
1433
1434 return 0;
1435}
1436
1437static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1438 .attach = tegra_dsi_host_attach,
1439 .detach = tegra_dsi_host_detach,
0fffdf6c 1440 .transfer = tegra_dsi_host_transfer,
dec72739
TR		 1441};
1442
e94236cd
TR		 1443static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1444{
1445 struct device_node *np;
1446
1447 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1448 if (np) {
1449 struct platform_device *gangster = of_find_device_by_node(np);
1450
1451 dsi->slave = platform_get_drvdata(gangster);
1452 of_node_put(np);
1453
1454 if (!dsi->slave)
1455 return -EPROBE_DEFER;
1456
1457 dsi->slave->master = dsi;
1458 }
1459
1460 return 0;
1461}
1462
dec72739
TR		 1463static int tegra_dsi_probe(struct platform_device *pdev)
1464{
1465 struct tegra_dsi *dsi;
1466 struct resource *regs;
1467 int err;
1468
1469 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1470 if (!dsi)
1471 return -ENOMEM;
1472
1473 dsi->output.dev = dsi->dev = &pdev->dev;
976cebc3
TR		 1474 dsi->video_fifo_depth = 1920;
1475 dsi->host_fifo_depth = 64;
dec72739 1476
e94236cd
TR		 1477 err = tegra_dsi_ganged_probe(dsi);
1478 if (err < 0)
1479 return err;
1480
dec72739
TR		 1481 err = tegra_output_probe(&dsi->output);
1482 if (err < 0)
1483 return err;
1484
ba3df979
TR		 1485 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1486
dec72739
TR		 1487 /*
1488 * Assume these values by default. When a DSI peripheral driver
1489 * attaches to the DSI host, the parameters will be taken from
1490 * the attached device.
1491 */
17297a28 1492 dsi->flags = MIPI_DSI_MODE_VIDEO;
dec72739
TR		 1493 dsi->format = MIPI_DSI_FMT_RGB888;
1494 dsi->lanes = 4;
1495
1496 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1497 if (IS_ERR(dsi->rst))
1498 return PTR_ERR(dsi->rst);
1499
1500 dsi->clk = devm_clk_get(&pdev->dev, NULL);
1501 if (IS_ERR(dsi->clk)) {
1502 dev_err(&pdev->dev, "cannot get DSI clock\n");
d2d0a9d2
TR		 1503 err = PTR_ERR(dsi->clk);
1504 goto reset;
dec72739
TR		 1505 }
1506
1507 err = clk_prepare_enable(dsi->clk);
1508 if (err < 0) {
1509 dev_err(&pdev->dev, "cannot enable DSI clock\n");
d2d0a9d2 1510 goto reset;
dec72739
TR		 1511 }
1512
1513 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1514 if (IS_ERR(dsi->clk_lp)) {
1515 dev_err(&pdev->dev, "cannot get low-power clock\n");
d2d0a9d2
TR		 1516 err = PTR_ERR(dsi->clk_lp);
1517 goto disable_clk;
dec72739
TR		 1518 }
1519
1520 err = clk_prepare_enable(dsi->clk_lp);
1521 if (err < 0) {
1522 dev_err(&pdev->dev, "cannot enable low-power clock\n");
d2d0a9d2 1523 goto disable_clk;
dec72739
TR		 1524 }
1525
1526 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1527 if (IS_ERR(dsi->clk_parent)) {
1528 dev_err(&pdev->dev, "cannot get parent clock\n");
d2d0a9d2
TR		 1529 err = PTR_ERR(dsi->clk_parent);
1530 goto disable_clk_lp;
dec72739
TR		 1531 }
1532
3b077afb
TR		 1533 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1534 if (IS_ERR(dsi->vdd)) {
1535 dev_err(&pdev->dev, "cannot get VDD supply\n");
d2d0a9d2
TR		 1536 err = PTR_ERR(dsi->vdd);
1537 goto disable_clk_lp;
3b077afb
TR		 1538 }
1539
1540 err = regulator_enable(dsi->vdd);
1541 if (err < 0) {
1542 dev_err(&pdev->dev, "cannot enable VDD supply\n");
d2d0a9d2 1543 goto disable_clk_lp;
3b077afb
TR		 1544 }
1545
dec72739
TR		 1546 err = tegra_dsi_setup_clocks(dsi);
1547 if (err < 0) {
1548 dev_err(&pdev->dev, "cannot setup clocks\n");
d2d0a9d2 1549 goto disable_vdd;
dec72739
TR		 1550 }
1551
1552 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1553 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
d2d0a9d2
TR		 1554 if (IS_ERR(dsi->regs)) {
1555 err = PTR_ERR(dsi->regs);
1556 goto disable_vdd;
1557 }
dec72739 1558
dec72739 1559 dsi->mipi = tegra_mipi_request(&pdev->dev);
d2d0a9d2
TR		 1560 if (IS_ERR(dsi->mipi)) {
1561 err = PTR_ERR(dsi->mipi);
1562 goto disable_vdd;
1563 }
dec72739
TR		 1564
1565 dsi->host.ops = &tegra_dsi_host_ops;
1566 dsi->host.dev = &pdev->dev;
1567
1568 err = mipi_dsi_host_register(&dsi->host);
1569 if (err < 0) {
1570 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
d2d0a9d2 1571 goto mipi_free;
dec72739
TR		 1572 }
1573
1574 INIT_LIST_HEAD(&dsi->client.list);
1575 dsi->client.ops = &dsi_client_ops;
1576 dsi->client.dev = &pdev->dev;
1577
1578 err = host1x_client_register(&dsi->client);
1579 if (err < 0) {
1580 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1581 err);
d2d0a9d2 1582 goto unregister;
dec72739
TR		 1583 }
1584
1585 platform_set_drvdata(pdev, dsi);
1586
1587 return 0;
d2d0a9d2
TR		 1588
1589unregister:
1590 mipi_dsi_host_unregister(&dsi->host);
1591mipi_free:
1592 tegra_mipi_free(dsi->mipi);
1593disable_vdd:
1594 regulator_disable(dsi->vdd);
1595disable_clk_lp:
1596 clk_disable_unprepare(dsi->clk_lp);
1597disable_clk:
1598 clk_disable_unprepare(dsi->clk);
1599reset:
1600 reset_control_assert(dsi->rst);
1601 return err;
dec72739
TR		 1602}
1603
1604static int tegra_dsi_remove(struct platform_device *pdev)
1605{
1606 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1607 int err;
1608
1609 err = host1x_client_unregister(&dsi->client);
1610 if (err < 0) {
1611 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1612 err);
1613 return err;
1614 }
1615
328ec69e 1616 tegra_output_remove(&dsi->output);
5b901e78 1617
dec72739
TR		 1618 mipi_dsi_host_unregister(&dsi->host);
1619 tegra_mipi_free(dsi->mipi);
1620
3b077afb 1621 regulator_disable(dsi->vdd);
dec72739
TR		 1622 clk_disable_unprepare(dsi->clk_lp);
1623 clk_disable_unprepare(dsi->clk);
cb825d89 1624 reset_control_assert(dsi->rst);
dec72739 1625
dec72739
TR		 1626 return 0;
1627}
1628
1629static const struct of_device_id tegra_dsi_of_match[] = {
ddfb406b 1630 { .compatible = "nvidia,tegra210-dsi", },
c06c7930 1631 { .compatible = "nvidia,tegra132-dsi", },
7d338587 1632 { .compatible = "nvidia,tegra124-dsi", },
dec72739
TR		 1633 { .compatible = "nvidia,tegra114-dsi", },
1634 { },
1635};
ef70728c 1636MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
dec72739
TR		 1637
1638struct platform_driver tegra_dsi_driver = {
1639 .driver = {
1640 .name = "tegra-dsi",
1641 .of_match_table = tegra_dsi_of_match,
1642 },
1643 .probe = tegra_dsi_probe,
1644 .remove = tegra_dsi_remove,
1645};
Linux kernel - Deliverables
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