Commit | Line | Data |
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16ea975e RC |
1 | /* |
2 | * Copyright (C) 2012 Texas Instruments | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
a464d618 | 18 | #include "drm_flip_work.h" |
3cb9ae4f | 19 | #include <drm/drm_plane_helper.h> |
305198de | 20 | #include <drm/drm_atomic_helper.h> |
16ea975e RC |
21 | |
22 | #include "tilcdc_drv.h" | |
23 | #include "tilcdc_regs.h" | |
24 | ||
2b3a8cd7 TV |
25 | #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000 |
26 | ||
16ea975e RC |
27 | struct tilcdc_crtc { |
28 | struct drm_crtc base; | |
29 | ||
47f571c6 | 30 | struct drm_plane primary; |
16ea975e | 31 | const struct tilcdc_panel_info *info; |
16ea975e | 32 | struct drm_pending_vblank_event *event; |
47bfd6c0 | 33 | bool enabled; |
16ea975e RC |
34 | wait_queue_head_t frame_done_wq; |
35 | bool frame_done; | |
2b3a8cd7 TV |
36 | spinlock_t irq_lock; |
37 | ||
38 | ktime_t last_vblank; | |
16ea975e | 39 | |
2b2080d7 | 40 | struct drm_framebuffer *curr_fb; |
2b3a8cd7 | 41 | struct drm_framebuffer *next_fb; |
16ea975e RC |
42 | |
43 | /* for deferred fb unref's: */ | |
a464d618 | 44 | struct drm_flip_work unref_work; |
103cd8bc JS |
45 | |
46 | /* Only set if an external encoder is connected */ | |
47 | bool simulate_vesa_sync; | |
5895d08f JS |
48 | |
49 | int sync_lost_count; | |
50 | bool frame_intact; | |
16ea975e RC |
51 | }; |
52 | #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) | |
53 | ||
a464d618 | 54 | static void unref_worker(struct drm_flip_work *work, void *val) |
16ea975e | 55 | { |
f7b45756 | 56 | struct tilcdc_crtc *tilcdc_crtc = |
a464d618 | 57 | container_of(work, struct tilcdc_crtc, unref_work); |
16ea975e | 58 | struct drm_device *dev = tilcdc_crtc->base.dev; |
16ea975e RC |
59 | |
60 | mutex_lock(&dev->mode_config.mutex); | |
a464d618 | 61 | drm_framebuffer_unreference(val); |
16ea975e RC |
62 | mutex_unlock(&dev->mode_config.mutex); |
63 | } | |
64 | ||
2b2080d7 | 65 | static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) |
16ea975e RC |
66 | { |
67 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
68 | struct drm_device *dev = crtc->dev; | |
16ea975e RC |
69 | struct drm_gem_cma_object *gem; |
70 | unsigned int depth, bpp; | |
2b2080d7 | 71 | dma_addr_t start, end; |
7eb9f069 | 72 | u64 dma_base_and_ceiling; |
16ea975e RC |
73 | |
74 | drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); | |
75 | gem = drm_fb_cma_get_gem_obj(fb, 0); | |
76 | ||
2b2080d7 TV |
77 | start = gem->paddr + fb->offsets[0] + |
78 | crtc->y * fb->pitches[0] + | |
79 | crtc->x * bpp / 8; | |
16ea975e | 80 | |
2b2080d7 | 81 | end = start + (crtc->mode.vdisplay * fb->pitches[0]); |
16ea975e | 82 | |
7eb9f069 JS |
83 | /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG |
84 | * with a single insruction, if available. This should make it more | |
85 | * unlikely that LCDC would fetch the DMA addresses in the middle of | |
86 | * an update. | |
87 | */ | |
88 | dma_base_and_ceiling = (u64)(end - 1) << 32 | start; | |
89 | tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling); | |
2b2080d7 TV |
90 | |
91 | if (tilcdc_crtc->curr_fb) | |
92 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
93 | tilcdc_crtc->curr_fb); | |
94 | ||
95 | tilcdc_crtc->curr_fb = fb; | |
16ea975e RC |
96 | } |
97 | ||
afaf833d JS |
98 | static void tilcdc_crtc_enable_irqs(struct drm_device *dev) |
99 | { | |
100 | struct tilcdc_drm_private *priv = dev->dev_private; | |
101 | ||
102 | tilcdc_clear_irqstatus(dev, 0xffffffff); | |
103 | ||
104 | if (priv->rev == 1) { | |
105 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, | |
106 | LCDC_V1_UNDERFLOW_INT_ENA); | |
8d6c3f7d KB |
107 | tilcdc_set(dev, LCDC_DMA_CTRL_REG, |
108 | LCDC_V1_END_OF_FRAME_INT_ENA); | |
afaf833d JS |
109 | } else { |
110 | tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, | |
111 | LCDC_V2_UNDERFLOW_INT_ENA | | |
112 | LCDC_V2_END_OF_FRAME0_INT_ENA | | |
113 | LCDC_FRAME_DONE | LCDC_SYNC_LOST); | |
114 | } | |
115 | } | |
116 | ||
117 | static void tilcdc_crtc_disable_irqs(struct drm_device *dev) | |
118 | { | |
119 | struct tilcdc_drm_private *priv = dev->dev_private; | |
120 | ||
121 | /* disable irqs that we might have enabled: */ | |
122 | if (priv->rev == 1) { | |
123 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, | |
124 | LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); | |
125 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, | |
126 | LCDC_V1_END_OF_FRAME_INT_ENA); | |
127 | } else { | |
128 | tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, | |
129 | LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | | |
130 | LCDC_V2_END_OF_FRAME0_INT_ENA | | |
131 | LCDC_FRAME_DONE | LCDC_SYNC_LOST); | |
132 | } | |
133 | } | |
134 | ||
2efec4f3 | 135 | static void reset(struct drm_crtc *crtc) |
16ea975e RC |
136 | { |
137 | struct drm_device *dev = crtc->dev; | |
138 | struct tilcdc_drm_private *priv = dev->dev_private; | |
139 | ||
2efec4f3 TV |
140 | if (priv->rev != 2) |
141 | return; | |
142 | ||
143 | tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); | |
144 | usleep_range(250, 1000); | |
145 | tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); | |
146 | } | |
147 | ||
47bfd6c0 | 148 | static void tilcdc_crtc_enable(struct drm_crtc *crtc) |
2efec4f3 TV |
149 | { |
150 | struct drm_device *dev = crtc->dev; | |
47bfd6c0 JS |
151 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
152 | ||
153 | if (tilcdc_crtc->enabled) | |
154 | return; | |
155 | ||
156 | pm_runtime_get_sync(dev->dev); | |
2efec4f3 TV |
157 | |
158 | reset(crtc); | |
16ea975e | 159 | |
afaf833d JS |
160 | tilcdc_crtc_enable_irqs(dev); |
161 | ||
2b2080d7 | 162 | tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); |
16ea975e RC |
163 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); |
164 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); | |
d85f850e JS |
165 | |
166 | drm_crtc_vblank_on(crtc); | |
47bfd6c0 JS |
167 | |
168 | tilcdc_crtc->enabled = true; | |
16ea975e RC |
169 | } |
170 | ||
47bfd6c0 | 171 | void tilcdc_crtc_disable(struct drm_crtc *crtc) |
16ea975e | 172 | { |
2d5be882 | 173 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
16ea975e | 174 | struct drm_device *dev = crtc->dev; |
2d5be882 | 175 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e | 176 | |
47bfd6c0 JS |
177 | if (!tilcdc_crtc->enabled) |
178 | return; | |
179 | ||
2d5be882 | 180 | tilcdc_crtc->frame_done = false; |
16ea975e | 181 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); |
2d5be882 JS |
182 | |
183 | /* | |
184 | * if necessary wait for framedone irq which will still come | |
185 | * before putting things to sleep.. | |
186 | */ | |
187 | if (priv->rev == 2) { | |
188 | int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq, | |
189 | tilcdc_crtc->frame_done, | |
437c7d94 | 190 | msecs_to_jiffies(500)); |
2d5be882 JS |
191 | if (ret == 0) |
192 | dev_err(dev->dev, "%s: timeout waiting for framedone\n", | |
193 | __func__); | |
194 | } | |
d85f850e JS |
195 | |
196 | drm_crtc_vblank_off(crtc); | |
afaf833d JS |
197 | |
198 | tilcdc_crtc_disable_irqs(dev); | |
47bfd6c0 JS |
199 | |
200 | pm_runtime_put_sync(dev->dev); | |
201 | ||
202 | if (tilcdc_crtc->next_fb) { | |
203 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
204 | tilcdc_crtc->next_fb); | |
205 | tilcdc_crtc->next_fb = NULL; | |
206 | } | |
207 | ||
208 | if (tilcdc_crtc->curr_fb) { | |
209 | drm_flip_work_queue(&tilcdc_crtc->unref_work, | |
210 | tilcdc_crtc->curr_fb); | |
211 | tilcdc_crtc->curr_fb = NULL; | |
212 | } | |
213 | ||
214 | drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); | |
215 | tilcdc_crtc->last_vblank = ktime_set(0, 0); | |
216 | ||
217 | tilcdc_crtc->enabled = false; | |
218 | } | |
219 | ||
220 | static bool tilcdc_crtc_is_on(struct drm_crtc *crtc) | |
221 | { | |
222 | return crtc->state && crtc->state->enable && crtc->state->active; | |
16ea975e RC |
223 | } |
224 | ||
225 | static void tilcdc_crtc_destroy(struct drm_crtc *crtc) | |
226 | { | |
227 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
228 | ||
47bfd6c0 | 229 | tilcdc_crtc_disable(crtc); |
16ea975e | 230 | |
d66284fb | 231 | of_node_put(crtc->port); |
16ea975e | 232 | drm_crtc_cleanup(crtc); |
a464d618 | 233 | drm_flip_work_cleanup(&tilcdc_crtc->unref_work); |
16ea975e RC |
234 | } |
235 | ||
e0e344e6 | 236 | int tilcdc_crtc_update_fb(struct drm_crtc *crtc, |
16ea975e | 237 | struct drm_framebuffer *fb, |
e0e344e6 | 238 | struct drm_pending_vblank_event *event) |
16ea975e RC |
239 | { |
240 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
241 | struct drm_device *dev = crtc->dev; | |
2b2080d7 | 242 | unsigned long flags; |
6f206e9d | 243 | |
16ea975e RC |
244 | if (tilcdc_crtc->event) { |
245 | dev_err(dev->dev, "already pending page flip!\n"); | |
246 | return -EBUSY; | |
247 | } | |
248 | ||
2b2080d7 TV |
249 | drm_framebuffer_reference(fb); |
250 | ||
f4510a27 | 251 | crtc->primary->fb = fb; |
65734a26 | 252 | |
2b3a8cd7 TV |
253 | spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); |
254 | ||
0a1fe1b7 JS |
255 | if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) { |
256 | ktime_t next_vblank; | |
257 | s64 tdiff; | |
2b2080d7 | 258 | |
0a1fe1b7 JS |
259 | next_vblank = ktime_add_us(tilcdc_crtc->last_vblank, |
260 | 1000000 / crtc->hwmode.vrefresh); | |
2b3a8cd7 | 261 | |
0a1fe1b7 JS |
262 | tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get())); |
263 | ||
264 | if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US) | |
265 | tilcdc_crtc->next_fb = fb; | |
266 | } | |
267 | ||
268 | if (tilcdc_crtc->next_fb != fb) | |
2b3a8cd7 | 269 | set_scanout(crtc, fb); |
2b2080d7 | 270 | |
2b2080d7 | 271 | tilcdc_crtc->event = event; |
2b3a8cd7 TV |
272 | |
273 | spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); | |
16ea975e RC |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
16ea975e RC |
278 | static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, |
279 | const struct drm_display_mode *mode, | |
280 | struct drm_display_mode *adjusted_mode) | |
281 | { | |
103cd8bc JS |
282 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); |
283 | ||
284 | if (!tilcdc_crtc->simulate_vesa_sync) | |
285 | return true; | |
286 | ||
287 | /* | |
288 | * tilcdc does not generate VESA-compliant sync but aligns | |
289 | * VS on the second edge of HS instead of first edge. | |
290 | * We use adjusted_mode, to fixup sync by aligning both rising | |
291 | * edges and add HSKEW offset to fix the sync. | |
292 | */ | |
293 | adjusted_mode->hskew = mode->hsync_end - mode->hsync_start; | |
294 | adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW; | |
295 | ||
296 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) { | |
297 | adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
298 | adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC; | |
299 | } else { | |
300 | adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
301 | adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC; | |
302 | } | |
303 | ||
16ea975e RC |
304 | return true; |
305 | } | |
306 | ||
f6382f18 JS |
307 | static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc) |
308 | { | |
309 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
310 | struct drm_device *dev = crtc->dev; | |
311 | struct tilcdc_drm_private *priv = dev->dev_private; | |
312 | const struct tilcdc_panel_info *info = tilcdc_crtc->info; | |
313 | uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; | |
314 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; | |
315 | struct drm_framebuffer *fb = crtc->primary->state->fb; | |
316 | ||
317 | if (WARN_ON(!info)) | |
318 | return; | |
319 | ||
320 | if (WARN_ON(!fb)) | |
321 | return; | |
322 | ||
f6382f18 JS |
323 | /* Configure the Burst Size and fifo threshold of DMA: */ |
324 | reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; | |
325 | switch (info->dma_burst_sz) { | |
326 | case 1: | |
327 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); | |
328 | break; | |
329 | case 2: | |
330 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); | |
331 | break; | |
332 | case 4: | |
333 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); | |
334 | break; | |
335 | case 8: | |
336 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); | |
337 | break; | |
338 | case 16: | |
339 | reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); | |
340 | break; | |
341 | default: | |
342 | dev_err(dev->dev, "invalid burst size\n"); | |
343 | return; | |
344 | } | |
345 | reg |= (info->fifo_th << 8); | |
346 | tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); | |
347 | ||
348 | /* Configure timings: */ | |
349 | hbp = mode->htotal - mode->hsync_end; | |
350 | hfp = mode->hsync_start - mode->hdisplay; | |
351 | hsw = mode->hsync_end - mode->hsync_start; | |
352 | vbp = mode->vtotal - mode->vsync_end; | |
353 | vfp = mode->vsync_start - mode->vdisplay; | |
354 | vsw = mode->vsync_end - mode->vsync_start; | |
355 | ||
356 | DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", | |
357 | mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); | |
358 | ||
359 | /* Set AC Bias Period and Number of Transitions per Interrupt: */ | |
360 | reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; | |
361 | reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | | |
362 | LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); | |
363 | ||
364 | /* | |
365 | * subtract one from hfp, hbp, hsw because the hardware uses | |
366 | * a value of 0 as 1 | |
367 | */ | |
368 | if (priv->rev == 2) { | |
369 | /* clear bits we're going to set */ | |
370 | reg &= ~0x78000033; | |
371 | reg |= ((hfp-1) & 0x300) >> 8; | |
372 | reg |= ((hbp-1) & 0x300) >> 4; | |
373 | reg |= ((hsw-1) & 0x3c0) << 21; | |
374 | } | |
375 | tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); | |
376 | ||
377 | reg = (((mode->hdisplay >> 4) - 1) << 4) | | |
378 | (((hbp-1) & 0xff) << 24) | | |
379 | (((hfp-1) & 0xff) << 16) | | |
380 | (((hsw-1) & 0x3f) << 10); | |
381 | if (priv->rev == 2) | |
382 | reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; | |
383 | tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); | |
384 | ||
385 | reg = ((mode->vdisplay - 1) & 0x3ff) | | |
386 | ((vbp & 0xff) << 24) | | |
387 | ((vfp & 0xff) << 16) | | |
388 | (((vsw-1) & 0x3f) << 10); | |
389 | tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); | |
390 | ||
391 | /* | |
392 | * be sure to set Bit 10 for the V2 LCDC controller, | |
393 | * otherwise limited to 1024 pixels width, stopping | |
394 | * 1920x1080 being supported. | |
395 | */ | |
396 | if (priv->rev == 2) { | |
397 | if ((mode->vdisplay - 1) & 0x400) { | |
398 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, | |
399 | LCDC_LPP_B10); | |
400 | } else { | |
401 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, | |
402 | LCDC_LPP_B10); | |
403 | } | |
404 | } | |
405 | ||
406 | /* Configure display type: */ | |
407 | reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & | |
408 | ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | | |
409 | LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | | |
410 | 0x000ff000 /* Palette Loading Delay bits */); | |
411 | reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ | |
412 | if (info->tft_alt_mode) | |
413 | reg |= LCDC_TFT_ALT_ENABLE; | |
414 | if (priv->rev == 2) { | |
415 | unsigned int depth, bpp; | |
416 | ||
417 | drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); | |
418 | switch (bpp) { | |
419 | case 16: | |
420 | break; | |
421 | case 32: | |
422 | reg |= LCDC_V2_TFT_24BPP_UNPACK; | |
423 | /* fallthrough */ | |
424 | case 24: | |
425 | reg |= LCDC_V2_TFT_24BPP_MODE; | |
426 | break; | |
427 | default: | |
428 | dev_err(dev->dev, "invalid pixel format\n"); | |
429 | return; | |
430 | } | |
431 | } | |
432 | reg |= info->fdd < 12; | |
433 | tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); | |
434 | ||
435 | if (info->invert_pxl_clk) | |
436 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); | |
437 | else | |
438 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); | |
439 | ||
440 | if (info->sync_ctrl) | |
441 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); | |
442 | else | |
443 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); | |
444 | ||
445 | if (info->sync_edge) | |
446 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); | |
447 | else | |
448 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); | |
449 | ||
450 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
451 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); | |
452 | else | |
453 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); | |
454 | ||
455 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
456 | tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); | |
457 | else | |
458 | tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); | |
459 | ||
460 | if (info->raster_order) | |
461 | tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); | |
462 | else | |
463 | tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); | |
464 | ||
465 | drm_framebuffer_reference(fb); | |
466 | ||
467 | set_scanout(crtc, fb); | |
468 | ||
469 | tilcdc_crtc_update_clk(crtc); | |
470 | ||
f6382f18 JS |
471 | crtc->hwmode = crtc->state->adjusted_mode; |
472 | } | |
473 | ||
db380c58 JS |
474 | static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc, |
475 | struct drm_crtc_state *state) | |
476 | { | |
477 | struct drm_display_mode *mode = &state->mode; | |
478 | int ret; | |
479 | ||
480 | /* If we are not active we don't care */ | |
481 | if (!state->active) | |
482 | return 0; | |
483 | ||
484 | if (state->state->planes[0].ptr != crtc->primary || | |
485 | state->state->planes[0].state == NULL || | |
486 | state->state->planes[0].state->crtc != crtc) { | |
487 | dev_dbg(crtc->dev->dev, "CRTC primary plane must be present"); | |
488 | return -EINVAL; | |
489 | } | |
490 | ||
491 | ret = tilcdc_crtc_mode_valid(crtc, mode); | |
492 | if (ret) { | |
493 | dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name); | |
494 | return -EINVAL; | |
495 | } | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
16ea975e | 500 | static const struct drm_crtc_funcs tilcdc_crtc_funcs = { |
305198de JS |
501 | .destroy = tilcdc_crtc_destroy, |
502 | .set_config = drm_atomic_helper_set_config, | |
503 | .page_flip = drm_atomic_helper_page_flip, | |
504 | .reset = drm_atomic_helper_crtc_reset, | |
505 | .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, | |
506 | .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, | |
16ea975e RC |
507 | }; |
508 | ||
509 | static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { | |
16ea975e | 510 | .mode_fixup = tilcdc_crtc_mode_fixup, |
305198de JS |
511 | .enable = tilcdc_crtc_enable, |
512 | .disable = tilcdc_crtc_disable, | |
db380c58 | 513 | .atomic_check = tilcdc_crtc_atomic_check, |
f6382f18 | 514 | .mode_set_nofb = tilcdc_crtc_mode_set_nofb, |
16ea975e RC |
515 | }; |
516 | ||
517 | int tilcdc_crtc_max_width(struct drm_crtc *crtc) | |
518 | { | |
519 | struct drm_device *dev = crtc->dev; | |
520 | struct tilcdc_drm_private *priv = dev->dev_private; | |
521 | int max_width = 0; | |
522 | ||
523 | if (priv->rev == 1) | |
524 | max_width = 1024; | |
525 | else if (priv->rev == 2) | |
526 | max_width = 2048; | |
527 | ||
528 | return max_width; | |
529 | } | |
530 | ||
531 | int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) | |
532 | { | |
533 | struct tilcdc_drm_private *priv = crtc->dev->dev_private; | |
534 | unsigned int bandwidth; | |
e1c5d0a8 | 535 | uint32_t hbp, hfp, hsw, vbp, vfp, vsw; |
16ea975e | 536 | |
e1c5d0a8 DE |
537 | /* |
538 | * check to see if the width is within the range that | |
539 | * the LCD Controller physically supports | |
540 | */ | |
16ea975e RC |
541 | if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) |
542 | return MODE_VIRTUAL_X; | |
543 | ||
544 | /* width must be multiple of 16 */ | |
545 | if (mode->hdisplay & 0xf) | |
546 | return MODE_VIRTUAL_X; | |
547 | ||
548 | if (mode->vdisplay > 2048) | |
549 | return MODE_VIRTUAL_Y; | |
550 | ||
e1c5d0a8 DE |
551 | DBG("Processing mode %dx%d@%d with pixel clock %d", |
552 | mode->hdisplay, mode->vdisplay, | |
553 | drm_mode_vrefresh(mode), mode->clock); | |
554 | ||
555 | hbp = mode->htotal - mode->hsync_end; | |
556 | hfp = mode->hsync_start - mode->hdisplay; | |
557 | hsw = mode->hsync_end - mode->hsync_start; | |
558 | vbp = mode->vtotal - mode->vsync_end; | |
559 | vfp = mode->vsync_start - mode->vdisplay; | |
560 | vsw = mode->vsync_end - mode->vsync_start; | |
561 | ||
562 | if ((hbp-1) & ~0x3ff) { | |
563 | DBG("Pruning mode: Horizontal Back Porch out of range"); | |
564 | return MODE_HBLANK_WIDE; | |
565 | } | |
566 | ||
567 | if ((hfp-1) & ~0x3ff) { | |
568 | DBG("Pruning mode: Horizontal Front Porch out of range"); | |
569 | return MODE_HBLANK_WIDE; | |
570 | } | |
571 | ||
572 | if ((hsw-1) & ~0x3ff) { | |
573 | DBG("Pruning mode: Horizontal Sync Width out of range"); | |
574 | return MODE_HSYNC_WIDE; | |
575 | } | |
576 | ||
577 | if (vbp & ~0xff) { | |
578 | DBG("Pruning mode: Vertical Back Porch out of range"); | |
579 | return MODE_VBLANK_WIDE; | |
580 | } | |
581 | ||
582 | if (vfp & ~0xff) { | |
583 | DBG("Pruning mode: Vertical Front Porch out of range"); | |
584 | return MODE_VBLANK_WIDE; | |
585 | } | |
586 | ||
587 | if ((vsw-1) & ~0x3f) { | |
588 | DBG("Pruning mode: Vertical Sync Width out of range"); | |
589 | return MODE_VSYNC_WIDE; | |
590 | } | |
591 | ||
4e564346 DE |
592 | /* |
593 | * some devices have a maximum allowed pixel clock | |
594 | * configured from the DT | |
595 | */ | |
596 | if (mode->clock > priv->max_pixelclock) { | |
f7b45756 | 597 | DBG("Pruning mode: pixel clock too high"); |
4e564346 DE |
598 | return MODE_CLOCK_HIGH; |
599 | } | |
600 | ||
601 | /* | |
602 | * some devices further limit the max horizontal resolution | |
603 | * configured from the DT | |
604 | */ | |
605 | if (mode->hdisplay > priv->max_width) | |
606 | return MODE_BAD_WIDTH; | |
607 | ||
16ea975e | 608 | /* filter out modes that would require too much memory bandwidth: */ |
4e564346 DE |
609 | bandwidth = mode->hdisplay * mode->vdisplay * |
610 | drm_mode_vrefresh(mode); | |
611 | if (bandwidth > priv->max_bandwidth) { | |
f7b45756 | 612 | DBG("Pruning mode: exceeds defined bandwidth limit"); |
16ea975e | 613 | return MODE_BAD; |
4e564346 | 614 | } |
16ea975e RC |
615 | |
616 | return MODE_OK; | |
617 | } | |
618 | ||
619 | void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, | |
620 | const struct tilcdc_panel_info *info) | |
621 | { | |
622 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
623 | tilcdc_crtc->info = info; | |
624 | } | |
625 | ||
103cd8bc JS |
626 | void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, |
627 | bool simulate_vesa_sync) | |
628 | { | |
629 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
630 | ||
631 | tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync; | |
632 | } | |
633 | ||
16ea975e RC |
634 | void tilcdc_crtc_update_clk(struct drm_crtc *crtc) |
635 | { | |
16ea975e RC |
636 | struct drm_device *dev = crtc->dev; |
637 | struct tilcdc_drm_private *priv = dev->dev_private; | |
3d19306a DE |
638 | unsigned long lcd_clk; |
639 | const unsigned clkdiv = 2; /* using a fixed divider of 2 */ | |
16ea975e RC |
640 | int ret; |
641 | ||
642 | pm_runtime_get_sync(dev->dev); | |
643 | ||
47bfd6c0 | 644 | tilcdc_crtc_disable(crtc); |
16ea975e | 645 | |
3d19306a DE |
646 | /* mode.clock is in KHz, set_rate wants parameter in Hz */ |
647 | ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv); | |
648 | if (ret < 0) { | |
16ea975e RC |
649 | dev_err(dev->dev, "failed to set display clock rate to: %d\n", |
650 | crtc->mode.clock); | |
651 | goto out; | |
652 | } | |
653 | ||
654 | lcd_clk = clk_get_rate(priv->clk); | |
16ea975e | 655 | |
3d19306a DE |
656 | DBG("lcd_clk=%lu, mode clock=%d, div=%u", |
657 | lcd_clk, crtc->mode.clock, clkdiv); | |
16ea975e RC |
658 | |
659 | /* Configure the LCD clock divisor. */ | |
3d19306a | 660 | tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) | |
16ea975e RC |
661 | LCDC_RASTER_MODE); |
662 | ||
663 | if (priv->rev == 2) | |
664 | tilcdc_set(dev, LCDC_CLK_ENABLE_REG, | |
665 | LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | | |
666 | LCDC_V2_CORE_CLK_EN); | |
667 | ||
47bfd6c0 JS |
668 | if (tilcdc_crtc_is_on(crtc)) |
669 | tilcdc_crtc_enable(crtc); | |
16ea975e RC |
670 | |
671 | out: | |
672 | pm_runtime_put_sync(dev->dev); | |
673 | } | |
674 | ||
5895d08f JS |
675 | #define SYNC_LOST_COUNT_LIMIT 50 |
676 | ||
16ea975e RC |
677 | irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) |
678 | { | |
679 | struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); | |
680 | struct drm_device *dev = crtc->dev; | |
681 | struct tilcdc_drm_private *priv = dev->dev_private; | |
317aae73 | 682 | uint32_t stat; |
16ea975e | 683 | |
317aae73 TV |
684 | stat = tilcdc_read_irqstatus(dev); |
685 | tilcdc_clear_irqstatus(dev, stat); | |
686 | ||
2b2080d7 | 687 | if (stat & LCDC_END_OF_FRAME0) { |
16ea975e | 688 | unsigned long flags; |
2b3a8cd7 TV |
689 | bool skip_event = false; |
690 | ktime_t now; | |
691 | ||
692 | now = ktime_get(); | |
16ea975e | 693 | |
2b2080d7 | 694 | drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); |
16ea975e | 695 | |
2b3a8cd7 TV |
696 | spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags); |
697 | ||
698 | tilcdc_crtc->last_vblank = now; | |
699 | ||
700 | if (tilcdc_crtc->next_fb) { | |
701 | set_scanout(crtc, tilcdc_crtc->next_fb); | |
702 | tilcdc_crtc->next_fb = NULL; | |
703 | skip_event = true; | |
704 | } | |
705 | ||
706 | spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags); | |
707 | ||
099ede83 | 708 | drm_crtc_handle_vblank(crtc); |
16ea975e | 709 | |
2b3a8cd7 TV |
710 | if (!skip_event) { |
711 | struct drm_pending_vblank_event *event; | |
16ea975e | 712 | |
2b3a8cd7 TV |
713 | spin_lock_irqsave(&dev->event_lock, flags); |
714 | ||
715 | event = tilcdc_crtc->event; | |
2b2080d7 | 716 | tilcdc_crtc->event = NULL; |
2b3a8cd7 | 717 | if (event) |
dfebc152 | 718 | drm_crtc_send_vblank_event(crtc, event); |
2b2080d7 | 719 | |
2b3a8cd7 TV |
720 | spin_unlock_irqrestore(&dev->event_lock, flags); |
721 | } | |
5895d08f JS |
722 | |
723 | if (tilcdc_crtc->frame_intact) | |
724 | tilcdc_crtc->sync_lost_count = 0; | |
725 | else | |
726 | tilcdc_crtc->frame_intact = true; | |
16ea975e RC |
727 | } |
728 | ||
14944113 JS |
729 | if (stat & LCDC_FIFO_UNDERFLOW) |
730 | dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow", | |
731 | __func__, stat); | |
732 | ||
733 | /* For revision 2 only */ | |
16ea975e RC |
734 | if (priv->rev == 2) { |
735 | if (stat & LCDC_FRAME_DONE) { | |
736 | tilcdc_crtc->frame_done = true; | |
737 | wake_up(&tilcdc_crtc->frame_done_wq); | |
738 | } | |
16ea975e | 739 | |
1abcdac8 JS |
740 | if (stat & LCDC_SYNC_LOST) { |
741 | dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost", | |
742 | __func__, stat); | |
743 | tilcdc_crtc->frame_intact = false; | |
744 | if (tilcdc_crtc->sync_lost_count++ > | |
745 | SYNC_LOST_COUNT_LIMIT) { | |
746 | dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat); | |
747 | tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, | |
748 | LCDC_SYNC_LOST); | |
749 | } | |
5895d08f | 750 | } |
c0c2baaa | 751 | |
14944113 JS |
752 | /* Indicate to LCDC that the interrupt service routine has |
753 | * completed, see 13.3.6.1.6 in AM335x TRM. | |
754 | */ | |
755 | tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); | |
756 | } | |
c0c2baaa | 757 | |
16ea975e RC |
758 | return IRQ_HANDLED; |
759 | } | |
760 | ||
16ea975e RC |
761 | struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) |
762 | { | |
d66284fb | 763 | struct tilcdc_drm_private *priv = dev->dev_private; |
16ea975e RC |
764 | struct tilcdc_crtc *tilcdc_crtc; |
765 | struct drm_crtc *crtc; | |
766 | int ret; | |
767 | ||
d0ec32ca | 768 | tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL); |
16ea975e RC |
769 | if (!tilcdc_crtc) { |
770 | dev_err(dev->dev, "allocation failed\n"); | |
771 | return NULL; | |
772 | } | |
773 | ||
774 | crtc = &tilcdc_crtc->base; | |
775 | ||
47f571c6 JS |
776 | ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary); |
777 | if (ret < 0) | |
778 | goto fail; | |
779 | ||
16ea975e RC |
780 | init_waitqueue_head(&tilcdc_crtc->frame_done_wq); |
781 | ||
d7f8db53 | 782 | drm_flip_work_init(&tilcdc_crtc->unref_work, |
a464d618 | 783 | "unref", unref_worker); |
16ea975e | 784 | |
2b3a8cd7 TV |
785 | spin_lock_init(&tilcdc_crtc->irq_lock); |
786 | ||
47f571c6 JS |
787 | ret = drm_crtc_init_with_planes(dev, crtc, |
788 | &tilcdc_crtc->primary, | |
789 | NULL, | |
790 | &tilcdc_crtc_funcs, | |
791 | "tilcdc crtc"); | |
16ea975e RC |
792 | if (ret < 0) |
793 | goto fail; | |
794 | ||
795 | drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); | |
796 | ||
d66284fb JS |
797 | if (priv->is_componentized) { |
798 | struct device_node *ports = | |
799 | of_get_child_by_name(dev->dev->of_node, "ports"); | |
800 | ||
801 | if (ports) { | |
802 | crtc->port = of_get_child_by_name(ports, "port"); | |
803 | of_node_put(ports); | |
804 | } else { | |
805 | crtc->port = | |
806 | of_get_child_by_name(dev->dev->of_node, "port"); | |
807 | } | |
808 | if (!crtc->port) { /* This should never happen */ | |
809 | dev_err(dev->dev, "Port node not found in %s\n", | |
810 | dev->dev->of_node->full_name); | |
811 | goto fail; | |
812 | } | |
813 | } | |
814 | ||
16ea975e RC |
815 | return crtc; |
816 | ||
817 | fail: | |
818 | tilcdc_crtc_destroy(crtc); | |
819 | return NULL; | |
820 | } |